MK64F12_osc.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_OSC_REGISTERS_H__
00088 #define __HW_OSC_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 OSC
00095  *
00096  * Oscillator
00097  *
00098  * Registers defined in this header file:
00099  * - HW_OSC_CR - OSC Control Register
00100  *
00101  * - hw_osc_t - Struct containing all module registers.
00102  */
00103 
00104 #define HW_OSC_INSTANCE_COUNT (1U) /*!< Number of instances of the OSC module. */
00105 
00106 /*******************************************************************************
00107  * HW_OSC_CR - OSC Control Register
00108  ******************************************************************************/
00109 
00110 /*!
00111  * @brief HW_OSC_CR - OSC Control Register (RW)
00112  *
00113  * Reset value: 0x00U
00114  *
00115  * After OSC is enabled and starts generating the clocks, the configurations
00116  * such as low power and frequency range, must not be changed.
00117  */
00118 typedef union _hw_osc_cr
00119 {
00120     uint8_t U;
00121     struct _hw_osc_cr_bitfields
00122     {
00123         uint8_t SC16P : 1;             /*!< [0] Oscillator 16 pF Capacitor Load Configure
00124                                         * */
00125         uint8_t SC8P : 1;              /*!< [1] Oscillator 8 pF Capacitor Load Configure */
00126         uint8_t SC4P : 1;              /*!< [2] Oscillator 4 pF Capacitor Load Configure */
00127         uint8_t SC2P : 1;              /*!< [3] Oscillator 2 pF Capacitor Load Configure */
00128         uint8_t RESERVED0 : 1;         /*!< [4]  */
00129         uint8_t EREFSTEN : 1;          /*!< [5] External Reference Stop Enable */
00130         uint8_t RESERVED1 : 1;         /*!< [6]  */
00131         uint8_t ERCLKEN : 1;           /*!< [7] External Reference Enable */
00132     } B;
00133 } hw_osc_cr_t;
00134 
00135 /*!
00136  * @name Constants and macros for entire OSC_CR register
00137  */
00138 /*@{*/
00139 #define HW_OSC_CR_ADDR(x)        ((x) + 0x0U)
00140 
00141 #define HW_OSC_CR(x)             (*(__IO hw_osc_cr_t *) HW_OSC_CR_ADDR(x))
00142 #define HW_OSC_CR_RD(x)          (ADDRESS_READ(hw_osc_cr_t, HW_OSC_CR_ADDR(x)))
00143 #define HW_OSC_CR_WR(x, v)       (ADDRESS_WRITE(hw_osc_cr_t, HW_OSC_CR_ADDR(x), v))
00144 #define HW_OSC_CR_SET(x, v)      (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) |  (v)))
00145 #define HW_OSC_CR_CLR(x, v)      (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) & ~(v)))
00146 #define HW_OSC_CR_TOG(x, v)      (HW_OSC_CR_WR(x, HW_OSC_CR_RD(x) ^  (v)))
00147 /*@}*/
00148 
00149 /*
00150  * Constants & macros for individual OSC_CR bitfields
00151  */
00152 
00153 /*!
00154  * @name Register OSC_CR, field SC16P[0] (RW)
00155  *
00156  * Configures the oscillator load.
00157  *
00158  * Values:
00159  * - 0 - Disable the selection.
00160  * - 1 - Add 16 pF capacitor to the oscillator load.
00161  */
00162 /*@{*/
00163 #define BP_OSC_CR_SC16P      (0U)          /*!< Bit position for OSC_CR_SC16P. */
00164 #define BM_OSC_CR_SC16P      (0x01U)       /*!< Bit mask for OSC_CR_SC16P. */
00165 #define BS_OSC_CR_SC16P      (1U)          /*!< Bit field size in bits for OSC_CR_SC16P. */
00166 
00167 /*! @brief Read current value of the OSC_CR_SC16P field. */
00168 #define BR_OSC_CR_SC16P(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC16P)))
00169 
00170 /*! @brief Format value for bitfield OSC_CR_SC16P. */
00171 #define BF_OSC_CR_SC16P(v)   ((uint8_t)((uint8_t)(v) << BP_OSC_CR_SC16P) & BM_OSC_CR_SC16P)
00172 
00173 /*! @brief Set the SC16P field to a new value. */
00174 #define BW_OSC_CR_SC16P(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC16P), v))
00175 /*@}*/
00176 
00177 /*!
00178  * @name Register OSC_CR, field SC8P[1] (RW)
00179  *
00180  * Configures the oscillator load.
00181  *
00182  * Values:
00183  * - 0 - Disable the selection.
00184  * - 1 - Add 8 pF capacitor to the oscillator load.
00185  */
00186 /*@{*/
00187 #define BP_OSC_CR_SC8P       (1U)          /*!< Bit position for OSC_CR_SC8P. */
00188 #define BM_OSC_CR_SC8P       (0x02U)       /*!< Bit mask for OSC_CR_SC8P. */
00189 #define BS_OSC_CR_SC8P       (1U)          /*!< Bit field size in bits for OSC_CR_SC8P. */
00190 
00191 /*! @brief Read current value of the OSC_CR_SC8P field. */
00192 #define BR_OSC_CR_SC8P(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC8P)))
00193 
00194 /*! @brief Format value for bitfield OSC_CR_SC8P. */
00195 #define BF_OSC_CR_SC8P(v)    ((uint8_t)((uint8_t)(v) << BP_OSC_CR_SC8P) & BM_OSC_CR_SC8P)
00196 
00197 /*! @brief Set the SC8P field to a new value. */
00198 #define BW_OSC_CR_SC8P(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC8P), v))
00199 /*@}*/
00200 
00201 /*!
00202  * @name Register OSC_CR, field SC4P[2] (RW)
00203  *
00204  * Configures the oscillator load.
00205  *
00206  * Values:
00207  * - 0 - Disable the selection.
00208  * - 1 - Add 4 pF capacitor to the oscillator load.
00209  */
00210 /*@{*/
00211 #define BP_OSC_CR_SC4P       (2U)          /*!< Bit position for OSC_CR_SC4P. */
00212 #define BM_OSC_CR_SC4P       (0x04U)       /*!< Bit mask for OSC_CR_SC4P. */
00213 #define BS_OSC_CR_SC4P       (1U)          /*!< Bit field size in bits for OSC_CR_SC4P. */
00214 
00215 /*! @brief Read current value of the OSC_CR_SC4P field. */
00216 #define BR_OSC_CR_SC4P(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC4P)))
00217 
00218 /*! @brief Format value for bitfield OSC_CR_SC4P. */
00219 #define BF_OSC_CR_SC4P(v)    ((uint8_t)((uint8_t)(v) << BP_OSC_CR_SC4P) & BM_OSC_CR_SC4P)
00220 
00221 /*! @brief Set the SC4P field to a new value. */
00222 #define BW_OSC_CR_SC4P(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC4P), v))
00223 /*@}*/
00224 
00225 /*!
00226  * @name Register OSC_CR, field SC2P[3] (RW)
00227  *
00228  * Configures the oscillator load.
00229  *
00230  * Values:
00231  * - 0 - Disable the selection.
00232  * - 1 - Add 2 pF capacitor to the oscillator load.
00233  */
00234 /*@{*/
00235 #define BP_OSC_CR_SC2P       (3U)          /*!< Bit position for OSC_CR_SC2P. */
00236 #define BM_OSC_CR_SC2P       (0x08U)       /*!< Bit mask for OSC_CR_SC2P. */
00237 #define BS_OSC_CR_SC2P       (1U)          /*!< Bit field size in bits for OSC_CR_SC2P. */
00238 
00239 /*! @brief Read current value of the OSC_CR_SC2P field. */
00240 #define BR_OSC_CR_SC2P(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC2P)))
00241 
00242 /*! @brief Format value for bitfield OSC_CR_SC2P. */
00243 #define BF_OSC_CR_SC2P(v)    ((uint8_t)((uint8_t)(v) << BP_OSC_CR_SC2P) & BM_OSC_CR_SC2P)
00244 
00245 /*! @brief Set the SC2P field to a new value. */
00246 #define BW_OSC_CR_SC2P(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_SC2P), v))
00247 /*@}*/
00248 
00249 /*!
00250  * @name Register OSC_CR, field EREFSTEN[5] (RW)
00251  *
00252  * Controls whether or not the external reference clock (OSCERCLK) remains
00253  * enabled when MCU enters Stop mode.
00254  *
00255  * Values:
00256  * - 0 - External reference clock is disabled in Stop mode.
00257  * - 1 - External reference clock stays enabled in Stop mode if ERCLKEN is set
00258  *     before entering Stop mode.
00259  */
00260 /*@{*/
00261 #define BP_OSC_CR_EREFSTEN   (5U)          /*!< Bit position for OSC_CR_EREFSTEN. */
00262 #define BM_OSC_CR_EREFSTEN   (0x20U)       /*!< Bit mask for OSC_CR_EREFSTEN. */
00263 #define BS_OSC_CR_EREFSTEN   (1U)          /*!< Bit field size in bits for OSC_CR_EREFSTEN. */
00264 
00265 /*! @brief Read current value of the OSC_CR_EREFSTEN field. */
00266 #define BR_OSC_CR_EREFSTEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_EREFSTEN)))
00267 
00268 /*! @brief Format value for bitfield OSC_CR_EREFSTEN. */
00269 #define BF_OSC_CR_EREFSTEN(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_EREFSTEN) & BM_OSC_CR_EREFSTEN)
00270 
00271 /*! @brief Set the EREFSTEN field to a new value. */
00272 #define BW_OSC_CR_EREFSTEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_EREFSTEN), v))
00273 /*@}*/
00274 
00275 /*!
00276  * @name Register OSC_CR, field ERCLKEN[7] (RW)
00277  *
00278  * Enables external reference clock (OSCERCLK).
00279  *
00280  * Values:
00281  * - 0 - External reference clock is inactive.
00282  * - 1 - External reference clock is enabled.
00283  */
00284 /*@{*/
00285 #define BP_OSC_CR_ERCLKEN    (7U)          /*!< Bit position for OSC_CR_ERCLKEN. */
00286 #define BM_OSC_CR_ERCLKEN    (0x80U)       /*!< Bit mask for OSC_CR_ERCLKEN. */
00287 #define BS_OSC_CR_ERCLKEN    (1U)          /*!< Bit field size in bits for OSC_CR_ERCLKEN. */
00288 
00289 /*! @brief Read current value of the OSC_CR_ERCLKEN field. */
00290 #define BR_OSC_CR_ERCLKEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_ERCLKEN)))
00291 
00292 /*! @brief Format value for bitfield OSC_CR_ERCLKEN. */
00293 #define BF_OSC_CR_ERCLKEN(v) ((uint8_t)((uint8_t)(v) << BP_OSC_CR_ERCLKEN) & BM_OSC_CR_ERCLKEN)
00294 
00295 /*! @brief Set the ERCLKEN field to a new value. */
00296 #define BW_OSC_CR_ERCLKEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_OSC_CR_ADDR(x), BP_OSC_CR_ERCLKEN), v))
00297 /*@}*/
00298 
00299 /*******************************************************************************
00300  * hw_osc_t - module struct
00301  ******************************************************************************/
00302 /*!
00303  * @brief All OSC module registers.
00304  */
00305 #pragma pack(1)
00306 typedef struct _hw_osc
00307 {
00308     __IO hw_osc_cr_t CR ;                   /*!< [0x0] OSC Control Register */
00309 } hw_osc_t;
00310 #pragma pack()
00311 
00312 /*! @brief Macro to access all OSC registers. */
00313 /*! @param x OSC module instance base address. */
00314 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
00315  *     use the '&' operator, like <code>&HW_OSC(OSC_BASE)</code>. */
00316 #define HW_OSC(x)      (*(hw_osc_t *)(x))
00317 
00318 #endif /* __HW_OSC_REGISTERS_H__ */
00319 /* EOF */