MK64F12_mpu.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_MPU_REGISTERS_H__
00088 #define __HW_MPU_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 MPU
00095  *
00096  * Memory protection unit
00097  *
00098  * Registers defined in this header file:
00099  * - HW_MPU_CESR - Control/Error Status Register
00100  * - HW_MPU_EARn - Error Address Register, slave port n
00101  * - HW_MPU_EDRn - Error Detail Register, slave port n
00102  * - HW_MPU_RGDn_WORD0 - Region Descriptor n, Word 0
00103  * - HW_MPU_RGDn_WORD1 - Region Descriptor n, Word 1
00104  * - HW_MPU_RGDn_WORD2 - Region Descriptor n, Word 2
00105  * - HW_MPU_RGDn_WORD3 - Region Descriptor n, Word 3
00106  * - HW_MPU_RGDAACn - Region Descriptor Alternate Access Control n
00107  *
00108  * - hw_mpu_t - Struct containing all module registers.
00109  */
00110 
00111 #define HW_MPU_INSTANCE_COUNT (1U) /*!< Number of instances of the MPU module. */
00112 
00113 /*******************************************************************************
00114  * HW_MPU_CESR - Control/Error Status Register
00115  ******************************************************************************/
00116 
00117 /*!
00118  * @brief HW_MPU_CESR - Control/Error Status Register (RW)
00119  *
00120  * Reset value: 0x00815101U
00121  */
00122 typedef union _hw_mpu_cesr
00123 {
00124     uint32_t U;
00125     struct _hw_mpu_cesr_bitfields
00126     {
00127         uint32_t VLD : 1;              /*!< [0] Valid */
00128         uint32_t RESERVED0 : 7;        /*!< [7:1]  */
00129         uint32_t NRGD : 4;             /*!< [11:8] Number Of Region Descriptors */
00130         uint32_t NSP : 4;              /*!< [15:12] Number Of Slave Ports */
00131         uint32_t HRL : 4;              /*!< [19:16] Hardware Revision Level */
00132         uint32_t RESERVED1 : 7;        /*!< [26:20]  */
00133         uint32_t SPERR : 5;            /*!< [31:27] Slave Port n Error */
00134     } B;
00135 } hw_mpu_cesr_t;
00136 
00137 /*!
00138  * @name Constants and macros for entire MPU_CESR register
00139  */
00140 /*@{*/
00141 #define HW_MPU_CESR_ADDR(x)      ((x) + 0x0U)
00142 
00143 #define HW_MPU_CESR(x)           (*(__IO hw_mpu_cesr_t *) HW_MPU_CESR_ADDR(x))
00144 #define HW_MPU_CESR_RD(x)        (ADDRESS_READ(hw_mpu_cesr_t, HW_MPU_CESR_ADDR(x)))
00145 #define HW_MPU_CESR_WR(x, v)     (ADDRESS_WRITE(hw_mpu_cesr_t, HW_MPU_CESR_ADDR(x), v))
00146 #define HW_MPU_CESR_SET(x, v)    (HW_MPU_CESR_WR(x, HW_MPU_CESR_RD(x) |  (v)))
00147 #define HW_MPU_CESR_CLR(x, v)    (HW_MPU_CESR_WR(x, HW_MPU_CESR_RD(x) & ~(v)))
00148 #define HW_MPU_CESR_TOG(x, v)    (HW_MPU_CESR_WR(x, HW_MPU_CESR_RD(x) ^  (v)))
00149 /*@}*/
00150 
00151 /*
00152  * Constants & macros for individual MPU_CESR bitfields
00153  */
00154 
00155 /*!
00156  * @name Register MPU_CESR, field VLD[0] (RW)
00157  *
00158  * Global enable/disable for the MPU.
00159  *
00160  * Values:
00161  * - 0 - MPU is disabled. All accesses from all bus masters are allowed.
00162  * - 1 - MPU is enabled
00163  */
00164 /*@{*/
00165 #define BP_MPU_CESR_VLD      (0U)          /*!< Bit position for MPU_CESR_VLD. */
00166 #define BM_MPU_CESR_VLD      (0x00000001U) /*!< Bit mask for MPU_CESR_VLD. */
00167 #define BS_MPU_CESR_VLD      (1U)          /*!< Bit field size in bits for MPU_CESR_VLD. */
00168 
00169 /*! @brief Read current value of the MPU_CESR_VLD field. */
00170 #define BR_MPU_CESR_VLD(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_MPU_CESR_ADDR(x), BP_MPU_CESR_VLD)))
00171 
00172 /*! @brief Format value for bitfield MPU_CESR_VLD. */
00173 #define BF_MPU_CESR_VLD(v)   ((uint32_t)((uint32_t)(v) << BP_MPU_CESR_VLD) & BM_MPU_CESR_VLD)
00174 
00175 /*! @brief Set the VLD field to a new value. */
00176 #define BW_MPU_CESR_VLD(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_MPU_CESR_ADDR(x), BP_MPU_CESR_VLD), v))
00177 /*@}*/
00178 
00179 /*!
00180  * @name Register MPU_CESR, field NRGD[11:8] (RO)
00181  *
00182  * Indicates the number of region descriptors implemented in the MPU.
00183  *
00184  * Values:
00185  * - 0000 - 8 region descriptors
00186  * - 0001 - 12 region descriptors
00187  * - 0010 - 16 region descriptors
00188  */
00189 /*@{*/
00190 #define BP_MPU_CESR_NRGD     (8U)          /*!< Bit position for MPU_CESR_NRGD. */
00191 #define BM_MPU_CESR_NRGD     (0x00000F00U) /*!< Bit mask for MPU_CESR_NRGD. */
00192 #define BS_MPU_CESR_NRGD     (4U)          /*!< Bit field size in bits for MPU_CESR_NRGD. */
00193 
00194 /*! @brief Read current value of the MPU_CESR_NRGD field. */
00195 #define BR_MPU_CESR_NRGD(x)  (UNION_READ(hw_mpu_cesr_t, HW_MPU_CESR_ADDR(x), U, B.NRGD))
00196 /*@}*/
00197 
00198 /*!
00199  * @name Register MPU_CESR, field NSP[15:12] (RO)
00200  *
00201  * Specifies the number of slave ports connected to the MPU.
00202  */
00203 /*@{*/
00204 #define BP_MPU_CESR_NSP      (12U)         /*!< Bit position for MPU_CESR_NSP. */
00205 #define BM_MPU_CESR_NSP      (0x0000F000U) /*!< Bit mask for MPU_CESR_NSP. */
00206 #define BS_MPU_CESR_NSP      (4U)          /*!< Bit field size in bits for MPU_CESR_NSP. */
00207 
00208 /*! @brief Read current value of the MPU_CESR_NSP field. */
00209 #define BR_MPU_CESR_NSP(x)   (UNION_READ(hw_mpu_cesr_t, HW_MPU_CESR_ADDR(x), U, B.NSP))
00210 /*@}*/
00211 
00212 /*!
00213  * @name Register MPU_CESR, field HRL[19:16] (RO)
00214  *
00215  * Specifies the MPU's hardware and definition revision level. It can be read by
00216  * software to determine the functional definition of the module.
00217  */
00218 /*@{*/
00219 #define BP_MPU_CESR_HRL      (16U)         /*!< Bit position for MPU_CESR_HRL. */
00220 #define BM_MPU_CESR_HRL      (0x000F0000U) /*!< Bit mask for MPU_CESR_HRL. */
00221 #define BS_MPU_CESR_HRL      (4U)          /*!< Bit field size in bits for MPU_CESR_HRL. */
00222 
00223 /*! @brief Read current value of the MPU_CESR_HRL field. */
00224 #define BR_MPU_CESR_HRL(x)   (UNION_READ(hw_mpu_cesr_t, HW_MPU_CESR_ADDR(x), U, B.HRL))
00225 /*@}*/
00226 
00227 /*!
00228  * @name Register MPU_CESR, field SPERR[31:27] (W1C)
00229  *
00230  * Indicates a captured error in EARn and EDRn. This bit is set when the
00231  * hardware detects an error and records the faulting address and attributes. It is
00232  * cleared by writing one to it. If another error is captured at the exact same cycle
00233  * as the write, the flag remains set. A find-first-one instruction or
00234  * equivalent can detect the presence of a captured error. The following shows the
00235  * correspondence between the bit number and slave port number: Bit 31 corresponds to
00236  * slave port 0. Bit 30 corresponds to slave port 1. Bit 29 corresponds to slave
00237  * port 2. Bit 28 corresponds to slave port 3. Bit 27 corresponds to slave port 4.
00238  *
00239  * Values:
00240  * - 0 - No error has occurred for slave port n.
00241  * - 1 - An error has occurred for slave port n.
00242  */
00243 /*@{*/
00244 #define BP_MPU_CESR_SPERR    (27U)         /*!< Bit position for MPU_CESR_SPERR. */
00245 #define BM_MPU_CESR_SPERR    (0xF8000000U) /*!< Bit mask for MPU_CESR_SPERR. */
00246 #define BS_MPU_CESR_SPERR    (5U)          /*!< Bit field size in bits for MPU_CESR_SPERR. */
00247 
00248 /*! @brief Read current value of the MPU_CESR_SPERR field. */
00249 #define BR_MPU_CESR_SPERR(x) (UNION_READ(hw_mpu_cesr_t, HW_MPU_CESR_ADDR(x), U, B.SPERR))
00250 
00251 /*! @brief Format value for bitfield MPU_CESR_SPERR. */
00252 #define BF_MPU_CESR_SPERR(v) ((uint32_t)((uint32_t)(v) << BP_MPU_CESR_SPERR) & BM_MPU_CESR_SPERR)
00253 
00254 /*! @brief Set the SPERR field to a new value. */
00255 #define BW_MPU_CESR_SPERR(x, v) (HW_MPU_CESR_WR(x, (HW_MPU_CESR_RD(x) & ~BM_MPU_CESR_SPERR) | BF_MPU_CESR_SPERR(v)))
00256 /*@}*/
00257 
00258 /*******************************************************************************
00259  * HW_MPU_EARn - Error Address Register, slave port n
00260  ******************************************************************************/
00261 
00262 /*!
00263  * @brief HW_MPU_EARn - Error Address Register, slave port n (RO)
00264  *
00265  * Reset value: 0x00000000U
00266  *
00267  * When the MPU detects an access error on slave port n, the 32-bit reference
00268  * address is captured in this read-only register and the corresponding bit in
00269  * CESR[SPERR] set. Additional information about the faulting access is captured in
00270  * the corresponding EDRn at the same time. This register and the corresponding
00271  * EDRn contain the most recent access error; there are no hardware interlocks with
00272  * CESR[SPERR], as the error registers are always loaded upon the occurrence of
00273  * each protection violation.
00274  */
00275 typedef union _hw_mpu_earn
00276 {
00277     uint32_t U;
00278     struct _hw_mpu_earn_bitfields
00279     {
00280         uint32_t EADDR : 32;           /*!< [31:0] Error Address */
00281     } B;
00282 } hw_mpu_earn_t;
00283 
00284 /*!
00285  * @name Constants and macros for entire MPU_EARn register
00286  */
00287 /*@{*/
00288 #define HW_MPU_EARn_COUNT (5U)
00289 
00290 #define HW_MPU_EARn_ADDR(x, n)   ((x) + 0x10U + (0x8U * (n)))
00291 
00292 #define HW_MPU_EARn(x, n)        (*(__I hw_mpu_earn_t *) HW_MPU_EARn_ADDR(x, n))
00293 #define HW_MPU_EARn_RD(x, n)     (ADDRESS_READ(hw_mpu_earn_t, HW_MPU_EARn_ADDR(x, n)))
00294 /*@}*/
00295 
00296 /*
00297  * Constants & macros for individual MPU_EARn bitfields
00298  */
00299 
00300 /*!
00301  * @name Register MPU_EARn, field EADDR[31:0] (RO)
00302  *
00303  * Indicates the reference address from slave port n that generated the access
00304  * error
00305  */
00306 /*@{*/
00307 #define BP_MPU_EARn_EADDR    (0U)          /*!< Bit position for MPU_EARn_EADDR. */
00308 #define BM_MPU_EARn_EADDR    (0xFFFFFFFFU) /*!< Bit mask for MPU_EARn_EADDR. */
00309 #define BS_MPU_EARn_EADDR    (32U)         /*!< Bit field size in bits for MPU_EARn_EADDR. */
00310 
00311 /*! @brief Read current value of the MPU_EARn_EADDR field. */
00312 #define BR_MPU_EARn_EADDR(x, n) (HW_MPU_EARn(x, n).U)
00313 /*@}*/
00314 /*******************************************************************************
00315  * HW_MPU_EDRn - Error Detail Register, slave port n
00316  ******************************************************************************/
00317 
00318 /*!
00319  * @brief HW_MPU_EDRn - Error Detail Register, slave port n (RO)
00320  *
00321  * Reset value: 0x00000000U
00322  *
00323  * When the MPU detects an access error on slave port n, 32 bits of error detail
00324  * are captured in this read-only register and the corresponding bit in
00325  * CESR[SPERR] is set. Information on the faulting address is captured in the
00326  * corresponding EARn register at the same time. This register and the corresponding EARn
00327  * register contain the most recent access error; there are no hardware interlocks
00328  * with CESR[SPERR] as the error registers are always loaded upon the occurrence
00329  * of each protection violation.
00330  */
00331 typedef union _hw_mpu_edrn
00332 {
00333     uint32_t U;
00334     struct _hw_mpu_edrn_bitfields
00335     {
00336         uint32_t ERW : 1;              /*!< [0] Error Read/Write */
00337         uint32_t EATTR : 3;            /*!< [3:1] Error Attributes */
00338         uint32_t EMN : 4;              /*!< [7:4] Error Master Number */
00339         uint32_t EPID : 8;             /*!< [15:8] Error Process Identification */
00340         uint32_t EACD : 16;            /*!< [31:16] Error Access Control Detail */
00341     } B;
00342 } hw_mpu_edrn_t;
00343 
00344 /*!
00345  * @name Constants and macros for entire MPU_EDRn register
00346  */
00347 /*@{*/
00348 #define HW_MPU_EDRn_COUNT (5U)
00349 
00350 #define HW_MPU_EDRn_ADDR(x, n)   ((x) + 0x14U + (0x8U * (n)))
00351 
00352 #define HW_MPU_EDRn(x, n)        (*(__I hw_mpu_edrn_t *) HW_MPU_EDRn_ADDR(x, n))
00353 #define HW_MPU_EDRn_RD(x, n)     (ADDRESS_READ(hw_mpu_edrn_t, HW_MPU_EDRn_ADDR(x, n)))
00354 /*@}*/
00355 
00356 /*
00357  * Constants & macros for individual MPU_EDRn bitfields
00358  */
00359 
00360 /*!
00361  * @name Register MPU_EDRn, field ERW[0] (RO)
00362  *
00363  * Indicates the access type of the faulting reference.
00364  *
00365  * Values:
00366  * - 0 - Read
00367  * - 1 - Write
00368  */
00369 /*@{*/
00370 #define BP_MPU_EDRn_ERW      (0U)          /*!< Bit position for MPU_EDRn_ERW. */
00371 #define BM_MPU_EDRn_ERW      (0x00000001U) /*!< Bit mask for MPU_EDRn_ERW. */
00372 #define BS_MPU_EDRn_ERW      (1U)          /*!< Bit field size in bits for MPU_EDRn_ERW. */
00373 
00374 /*! @brief Read current value of the MPU_EDRn_ERW field. */
00375 #define BR_MPU_EDRn_ERW(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_MPU_EDRn_ADDR(x, n), BP_MPU_EDRn_ERW)))
00376 /*@}*/
00377 
00378 /*!
00379  * @name Register MPU_EDRn, field EATTR[3:1] (RO)
00380  *
00381  * Indicates attribute information about the faulting reference. All other
00382  * encodings are reserved.
00383  *
00384  * Values:
00385  * - 000 - User mode, instruction access
00386  * - 001 - User mode, data access
00387  * - 010 - Supervisor mode, instruction access
00388  * - 011 - Supervisor mode, data access
00389  */
00390 /*@{*/
00391 #define BP_MPU_EDRn_EATTR    (1U)          /*!< Bit position for MPU_EDRn_EATTR. */
00392 #define BM_MPU_EDRn_EATTR    (0x0000000EU) /*!< Bit mask for MPU_EDRn_EATTR. */
00393 #define BS_MPU_EDRn_EATTR    (3U)          /*!< Bit field size in bits for MPU_EDRn_EATTR. */
00394 
00395 /*! @brief Read current value of the MPU_EDRn_EATTR field. */
00396 #define BR_MPU_EDRn_EATTR(x, n) (UNION_READ(hw_mpu_edrn_t, HW_MPU_EDRn_ADDR(x, n), U, B.EATTR))
00397 /*@}*/
00398 
00399 /*!
00400  * @name Register MPU_EDRn, field EMN[7:4] (RO)
00401  *
00402  * Indicates the bus master that generated the access error.
00403  */
00404 /*@{*/
00405 #define BP_MPU_EDRn_EMN      (4U)          /*!< Bit position for MPU_EDRn_EMN. */
00406 #define BM_MPU_EDRn_EMN      (0x000000F0U) /*!< Bit mask for MPU_EDRn_EMN. */
00407 #define BS_MPU_EDRn_EMN      (4U)          /*!< Bit field size in bits for MPU_EDRn_EMN. */
00408 
00409 /*! @brief Read current value of the MPU_EDRn_EMN field. */
00410 #define BR_MPU_EDRn_EMN(x, n) (UNION_READ(hw_mpu_edrn_t, HW_MPU_EDRn_ADDR(x, n), U, B.EMN))
00411 /*@}*/
00412 
00413 /*!
00414  * @name Register MPU_EDRn, field EPID[15:8] (RO)
00415  *
00416  * Records the process identifier of the faulting reference. The process
00417  * identifier is typically driven only by processor cores; for other bus masters, this
00418  * field is cleared.
00419  */
00420 /*@{*/
00421 #define BP_MPU_EDRn_EPID     (8U)          /*!< Bit position for MPU_EDRn_EPID. */
00422 #define BM_MPU_EDRn_EPID     (0x0000FF00U) /*!< Bit mask for MPU_EDRn_EPID. */
00423 #define BS_MPU_EDRn_EPID     (8U)          /*!< Bit field size in bits for MPU_EDRn_EPID. */
00424 
00425 /*! @brief Read current value of the MPU_EDRn_EPID field. */
00426 #define BR_MPU_EDRn_EPID(x, n) (UNION_READ(hw_mpu_edrn_t, HW_MPU_EDRn_ADDR(x, n), U, B.EPID))
00427 /*@}*/
00428 
00429 /*!
00430  * @name Register MPU_EDRn, field EACD[31:16] (RO)
00431  *
00432  * Indicates the region descriptor with the access error. If EDRn contains a
00433  * captured error and EACD is cleared, an access did not hit in any region
00434  * descriptor. If only a single EACD bit is set, the protection error was caused by a
00435  * single non-overlapping region descriptor. If two or more EACD bits are set, the
00436  * protection error was caused by an overlapping set of region descriptors.
00437  */
00438 /*@{*/
00439 #define BP_MPU_EDRn_EACD     (16U)         /*!< Bit position for MPU_EDRn_EACD. */
00440 #define BM_MPU_EDRn_EACD     (0xFFFF0000U) /*!< Bit mask for MPU_EDRn_EACD. */
00441 #define BS_MPU_EDRn_EACD     (16U)         /*!< Bit field size in bits for MPU_EDRn_EACD. */
00442 
00443 /*! @brief Read current value of the MPU_EDRn_EACD field. */
00444 #define BR_MPU_EDRn_EACD(x, n) (UNION_READ(hw_mpu_edrn_t, HW_MPU_EDRn_ADDR(x, n), U, B.EACD))
00445 /*@}*/
00446 
00447 /*******************************************************************************
00448  * HW_MPU_RGDn_WORD0 - Region Descriptor n, Word 0
00449  ******************************************************************************/
00450 
00451 /*!
00452  * @brief HW_MPU_RGDn_WORD0 - Region Descriptor n, Word 0 (RW)
00453  *
00454  * Reset value: 0x00000000U
00455  *
00456  * The first word of the region descriptor defines the 0-modulo-32 byte start
00457  * address of the memory region. Writes to this register clear the region
00458  * descriptor's valid bit (RGDn_WORD3[VLD]).
00459  */
00460 typedef union _hw_mpu_rgdn_word0
00461 {
00462     uint32_t U;
00463     struct _hw_mpu_rgdn_word0_bitfields
00464     {
00465         uint32_t RESERVED0 : 5;        /*!< [4:0]  */
00466         uint32_t SRTADDR : 27;         /*!< [31:5] Start Address */
00467     } B;
00468 } hw_mpu_rgdn_word0_t;
00469 
00470 /*!
00471  * @name Constants and macros for entire MPU_RGDn_WORD0 register
00472  */
00473 /*@{*/
00474 #define HW_MPU_RGDn_WORD0_COUNT (12U)
00475 
00476 #define HW_MPU_RGDn_WORD0_ADDR(x, n) ((x) + 0x400U + (0x10U * (n)))
00477 
00478 #define HW_MPU_RGDn_WORD0(x, n)  (*(__IO hw_mpu_rgdn_word0_t *) HW_MPU_RGDn_WORD0_ADDR(x, n))
00479 #define HW_MPU_RGDn_WORD0_RD(x, n) (ADDRESS_READ(hw_mpu_rgdn_word0_t, HW_MPU_RGDn_WORD0_ADDR(x, n)))
00480 #define HW_MPU_RGDn_WORD0_WR(x, n, v) (ADDRESS_WRITE(hw_mpu_rgdn_word0_t, HW_MPU_RGDn_WORD0_ADDR(x, n), v))
00481 #define HW_MPU_RGDn_WORD0_SET(x, n, v) (HW_MPU_RGDn_WORD0_WR(x, n, HW_MPU_RGDn_WORD0_RD(x, n) |  (v)))
00482 #define HW_MPU_RGDn_WORD0_CLR(x, n, v) (HW_MPU_RGDn_WORD0_WR(x, n, HW_MPU_RGDn_WORD0_RD(x, n) & ~(v)))
00483 #define HW_MPU_RGDn_WORD0_TOG(x, n, v) (HW_MPU_RGDn_WORD0_WR(x, n, HW_MPU_RGDn_WORD0_RD(x, n) ^  (v)))
00484 /*@}*/
00485 
00486 /*
00487  * Constants & macros for individual MPU_RGDn_WORD0 bitfields
00488  */
00489 
00490 /*!
00491  * @name Register MPU_RGDn_WORD0, field SRTADDR[31:5] (RW)
00492  *
00493  * Defines the most significant bits of the 0-modulo-32 byte start address of
00494  * the memory region.
00495  */
00496 /*@{*/
00497 #define BP_MPU_RGDn_WORD0_SRTADDR (5U)     /*!< Bit position for MPU_RGDn_WORD0_SRTADDR. */
00498 #define BM_MPU_RGDn_WORD0_SRTADDR (0xFFFFFFE0U) /*!< Bit mask for MPU_RGDn_WORD0_SRTADDR. */
00499 #define BS_MPU_RGDn_WORD0_SRTADDR (27U)    /*!< Bit field size in bits for MPU_RGDn_WORD0_SRTADDR. */
00500 
00501 /*! @brief Read current value of the MPU_RGDn_WORD0_SRTADDR field. */
00502 #define BR_MPU_RGDn_WORD0_SRTADDR(x, n) (UNION_READ(hw_mpu_rgdn_word0_t, HW_MPU_RGDn_WORD0_ADDR(x, n), U, B.SRTADDR))
00503 
00504 /*! @brief Format value for bitfield MPU_RGDn_WORD0_SRTADDR. */
00505 #define BF_MPU_RGDn_WORD0_SRTADDR(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD0_SRTADDR) & BM_MPU_RGDn_WORD0_SRTADDR)
00506 
00507 /*! @brief Set the SRTADDR field to a new value. */
00508 #define BW_MPU_RGDn_WORD0_SRTADDR(x, n, v) (HW_MPU_RGDn_WORD0_WR(x, n, (HW_MPU_RGDn_WORD0_RD(x, n) & ~BM_MPU_RGDn_WORD0_SRTADDR) | BF_MPU_RGDn_WORD0_SRTADDR(v)))
00509 /*@}*/
00510 /*******************************************************************************
00511  * HW_MPU_RGDn_WORD1 - Region Descriptor n, Word 1
00512  ******************************************************************************/
00513 
00514 /*!
00515  * @brief HW_MPU_RGDn_WORD1 - Region Descriptor n, Word 1 (RW)
00516  *
00517  * Reset value: 0xFFFFFFFFU
00518  *
00519  * The second word of the region descriptor defines the 31-modulo-32 byte end
00520  * address of the memory region. Writes to this register clear the region
00521  * descriptor's valid bit (RGDn_WORD3[VLD]).
00522  */
00523 typedef union _hw_mpu_rgdn_word1
00524 {
00525     uint32_t U;
00526     struct _hw_mpu_rgdn_word1_bitfields
00527     {
00528         uint32_t RESERVED0 : 5;        /*!< [4:0]  */
00529         uint32_t ENDADDR : 27;         /*!< [31:5] End Address */
00530     } B;
00531 } hw_mpu_rgdn_word1_t;
00532 
00533 /*!
00534  * @name Constants and macros for entire MPU_RGDn_WORD1 register
00535  */
00536 /*@{*/
00537 #define HW_MPU_RGDn_WORD1_COUNT (12U)
00538 
00539 #define HW_MPU_RGDn_WORD1_ADDR(x, n) ((x) + 0x404U + (0x10U * (n)))
00540 
00541 #define HW_MPU_RGDn_WORD1(x, n)  (*(__IO hw_mpu_rgdn_word1_t *) HW_MPU_RGDn_WORD1_ADDR(x, n))
00542 #define HW_MPU_RGDn_WORD1_RD(x, n) (ADDRESS_READ(hw_mpu_rgdn_word1_t, HW_MPU_RGDn_WORD1_ADDR(x, n)))
00543 #define HW_MPU_RGDn_WORD1_WR(x, n, v) (ADDRESS_WRITE(hw_mpu_rgdn_word1_t, HW_MPU_RGDn_WORD1_ADDR(x, n), v))
00544 #define HW_MPU_RGDn_WORD1_SET(x, n, v) (HW_MPU_RGDn_WORD1_WR(x, n, HW_MPU_RGDn_WORD1_RD(x, n) |  (v)))
00545 #define HW_MPU_RGDn_WORD1_CLR(x, n, v) (HW_MPU_RGDn_WORD1_WR(x, n, HW_MPU_RGDn_WORD1_RD(x, n) & ~(v)))
00546 #define HW_MPU_RGDn_WORD1_TOG(x, n, v) (HW_MPU_RGDn_WORD1_WR(x, n, HW_MPU_RGDn_WORD1_RD(x, n) ^  (v)))
00547 /*@}*/
00548 
00549 /*
00550  * Constants & macros for individual MPU_RGDn_WORD1 bitfields
00551  */
00552 
00553 /*!
00554  * @name Register MPU_RGDn_WORD1, field ENDADDR[31:5] (RW)
00555  *
00556  * Defines the most significant bits of the 31-modulo-32 byte end address of the
00557  * memory region. The MPU does not verify that ENDADDR >= SRTADDR.
00558  */
00559 /*@{*/
00560 #define BP_MPU_RGDn_WORD1_ENDADDR (5U)     /*!< Bit position for MPU_RGDn_WORD1_ENDADDR. */
00561 #define BM_MPU_RGDn_WORD1_ENDADDR (0xFFFFFFE0U) /*!< Bit mask for MPU_RGDn_WORD1_ENDADDR. */
00562 #define BS_MPU_RGDn_WORD1_ENDADDR (27U)    /*!< Bit field size in bits for MPU_RGDn_WORD1_ENDADDR. */
00563 
00564 /*! @brief Read current value of the MPU_RGDn_WORD1_ENDADDR field. */
00565 #define BR_MPU_RGDn_WORD1_ENDADDR(x, n) (UNION_READ(hw_mpu_rgdn_word1_t, HW_MPU_RGDn_WORD1_ADDR(x, n), U, B.ENDADDR))
00566 
00567 /*! @brief Format value for bitfield MPU_RGDn_WORD1_ENDADDR. */
00568 #define BF_MPU_RGDn_WORD1_ENDADDR(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD1_ENDADDR) & BM_MPU_RGDn_WORD1_ENDADDR)
00569 
00570 /*! @brief Set the ENDADDR field to a new value. */
00571 #define BW_MPU_RGDn_WORD1_ENDADDR(x, n, v) (HW_MPU_RGDn_WORD1_WR(x, n, (HW_MPU_RGDn_WORD1_RD(x, n) & ~BM_MPU_RGDn_WORD1_ENDADDR) | BF_MPU_RGDn_WORD1_ENDADDR(v)))
00572 /*@}*/
00573 /*******************************************************************************
00574  * HW_MPU_RGDn_WORD2 - Region Descriptor n, Word 2
00575  ******************************************************************************/
00576 
00577 /*!
00578  * @brief HW_MPU_RGDn_WORD2 - Region Descriptor n, Word 2 (RW)
00579  *
00580  * Reset value: 0x0061F7DFU
00581  *
00582  * The third word of the region descriptor defines the access control rights of
00583  * the memory region. The access control privileges depend on two broad
00584  * classifications of bus masters: Bus masters 0-3 have a 5-bit field defining separate
00585  * privilege rights for user and supervisor mode accesses, as well as the optional
00586  * inclusion of a process identification field within the definition. Bus masters
00587  * 4-7 are limited to separate read and write permissions. For the privilege
00588  * rights of bus masters 0-3, there are three flags associated with this function:
00589  * Read (r) refers to accessing the referenced memory address using an operand
00590  * (data) fetch Write (w) refers to updating the referenced memory address using a
00591  * store (data) instruction Execute (x) refers to reading the referenced memory
00592  * address using an instruction fetch Writes to RGDn_WORD2 clear the region
00593  * descriptor's valid bit (RGDn_WORD3[VLD]). If only updating the access controls, write
00594  * to RGDAACn instead because stores to these locations do not affect the
00595  * descriptor's valid bit.
00596  */
00597 typedef union _hw_mpu_rgdn_word2
00598 {
00599     uint32_t U;
00600     struct _hw_mpu_rgdn_word2_bitfields
00601     {
00602         uint32_t M0UM : 3;             /*!< [2:0] Bus Master 0 User Mode Access Control */
00603         uint32_t M0SM : 2;             /*!< [4:3] Bus Master 0 Supervisor Mode Access
00604                                         * Control */
00605         uint32_t M0PE : 1;             /*!< [5] Bus Master 0 Process Identifier enable */
00606         uint32_t M1UM : 3;             /*!< [8:6] Bus Master 1 User Mode Access Control */
00607         uint32_t M1SM : 2;             /*!< [10:9] Bus Master 1 Supervisor Mode Access
00608                                         * Control */
00609         uint32_t M1PE : 1;             /*!< [11] Bus Master 1 Process Identifier enable */
00610         uint32_t M2UM : 3;             /*!< [14:12] Bus Master 2 User Mode Access control
00611                                         * */
00612         uint32_t M2SM : 2;             /*!< [16:15] Bus Master 2 Supervisor Mode Access
00613                                         * Control */
00614         uint32_t M2PE : 1;             /*!< [17] Bus Master 2 Process Identifier Enable */
00615         uint32_t M3UM : 3;             /*!< [20:18] Bus Master 3 User Mode Access Control
00616                                         * */
00617         uint32_t M3SM : 2;             /*!< [22:21] Bus Master 3 Supervisor Mode Access
00618                                         * Control */
00619         uint32_t M3PE : 1;             /*!< [23] Bus Master 3 Process Identifier Enable */
00620         uint32_t M4WE : 1;             /*!< [24] Bus Master 4 Write Enable */
00621         uint32_t M4RE : 1;             /*!< [25] Bus Master 4 Read Enable */
00622         uint32_t M5WE : 1;             /*!< [26] Bus Master 5 Write Enable */
00623         uint32_t M5RE : 1;             /*!< [27] Bus Master 5 Read Enable */
00624         uint32_t M6WE : 1;             /*!< [28] Bus Master 6 Write Enable */
00625         uint32_t M6RE : 1;             /*!< [29] Bus Master 6 Read Enable */
00626         uint32_t M7WE : 1;             /*!< [30] Bus Master 7 Write Enable */
00627         uint32_t M7RE : 1;             /*!< [31] Bus Master 7 Read Enable */
00628     } B;
00629 } hw_mpu_rgdn_word2_t;
00630 
00631 /*!
00632  * @name Constants and macros for entire MPU_RGDn_WORD2 register
00633  */
00634 /*@{*/
00635 #define HW_MPU_RGDn_WORD2_COUNT (12U)
00636 
00637 #define HW_MPU_RGDn_WORD2_ADDR(x, n) ((x) + 0x408U + (0x10U * (n)))
00638 
00639 #define HW_MPU_RGDn_WORD2(x, n)  (*(__IO hw_mpu_rgdn_word2_t *) HW_MPU_RGDn_WORD2_ADDR(x, n))
00640 #define HW_MPU_RGDn_WORD2_RD(x, n) (ADDRESS_READ(hw_mpu_rgdn_word2_t, HW_MPU_RGDn_WORD2_ADDR(x, n)))
00641 #define HW_MPU_RGDn_WORD2_WR(x, n, v) (ADDRESS_WRITE(hw_mpu_rgdn_word2_t, HW_MPU_RGDn_WORD2_ADDR(x, n), v))
00642 #define HW_MPU_RGDn_WORD2_SET(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, HW_MPU_RGDn_WORD2_RD(x, n) |  (v)))
00643 #define HW_MPU_RGDn_WORD2_CLR(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, HW_MPU_RGDn_WORD2_RD(x, n) & ~(v)))
00644 #define HW_MPU_RGDn_WORD2_TOG(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, HW_MPU_RGDn_WORD2_RD(x, n) ^  (v)))
00645 /*@}*/
00646 
00647 /*
00648  * Constants & macros for individual MPU_RGDn_WORD2 bitfields
00649  */
00650 
00651 /*!
00652  * @name Register MPU_RGDn_WORD2, field M0UM[2:0] (RW)
00653  *
00654  * See M3UM description.
00655  */
00656 /*@{*/
00657 #define BP_MPU_RGDn_WORD2_M0UM (0U)        /*!< Bit position for MPU_RGDn_WORD2_M0UM. */
00658 #define BM_MPU_RGDn_WORD2_M0UM (0x00000007U) /*!< Bit mask for MPU_RGDn_WORD2_M0UM. */
00659 #define BS_MPU_RGDn_WORD2_M0UM (3U)        /*!< Bit field size in bits for MPU_RGDn_WORD2_M0UM. */
00660 
00661 /*! @brief Read current value of the MPU_RGDn_WORD2_M0UM field. */
00662 #define BR_MPU_RGDn_WORD2_M0UM(x, n) (UNION_READ(hw_mpu_rgdn_word2_t, HW_MPU_RGDn_WORD2_ADDR(x, n), U, B.M0UM))
00663 
00664 /*! @brief Format value for bitfield MPU_RGDn_WORD2_M0UM. */
00665 #define BF_MPU_RGDn_WORD2_M0UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M0UM) & BM_MPU_RGDn_WORD2_M0UM)
00666 
00667 /*! @brief Set the M0UM field to a new value. */
00668 #define BW_MPU_RGDn_WORD2_M0UM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M0UM) | BF_MPU_RGDn_WORD2_M0UM(v)))
00669 /*@}*/
00670 
00671 /*!
00672  * @name Register MPU_RGDn_WORD2, field M0SM[4:3] (RW)
00673  *
00674  * See M3SM description.
00675  */
00676 /*@{*/
00677 #define BP_MPU_RGDn_WORD2_M0SM (3U)        /*!< Bit position for MPU_RGDn_WORD2_M0SM. */
00678 #define BM_MPU_RGDn_WORD2_M0SM (0x00000018U) /*!< Bit mask for MPU_RGDn_WORD2_M0SM. */
00679 #define BS_MPU_RGDn_WORD2_M0SM (2U)        /*!< Bit field size in bits for MPU_RGDn_WORD2_M0SM. */
00680 
00681 /*! @brief Read current value of the MPU_RGDn_WORD2_M0SM field. */
00682 #define BR_MPU_RGDn_WORD2_M0SM(x, n) (UNION_READ(hw_mpu_rgdn_word2_t, HW_MPU_RGDn_WORD2_ADDR(x, n), U, B.M0SM))
00683 
00684 /*! @brief Format value for bitfield MPU_RGDn_WORD2_M0SM. */
00685 #define BF_MPU_RGDn_WORD2_M0SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M0SM) & BM_MPU_RGDn_WORD2_M0SM)
00686 
00687 /*! @brief Set the M0SM field to a new value. */
00688 #define BW_MPU_RGDn_WORD2_M0SM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M0SM) | BF_MPU_RGDn_WORD2_M0SM(v)))
00689 /*@}*/
00690 
00691 /*!
00692  * @name Register MPU_RGDn_WORD2, field M0PE[5] (RW)
00693  *
00694  * See M0PE description.
00695  */
00696 /*@{*/
00697 #define BP_MPU_RGDn_WORD2_M0PE (5U)        /*!< Bit position for MPU_RGDn_WORD2_M0PE. */
00698 #define BM_MPU_RGDn_WORD2_M0PE (0x00000020U) /*!< Bit mask for MPU_RGDn_WORD2_M0PE. */
00699 #define BS_MPU_RGDn_WORD2_M0PE (1U)        /*!< Bit field size in bits for MPU_RGDn_WORD2_M0PE. */
00700 
00701 /*! @brief Read current value of the MPU_RGDn_WORD2_M0PE field. */
00702 #define BR_MPU_RGDn_WORD2_M0PE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M0PE)))
00703 
00704 /*! @brief Format value for bitfield MPU_RGDn_WORD2_M0PE. */
00705 #define BF_MPU_RGDn_WORD2_M0PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M0PE) & BM_MPU_RGDn_WORD2_M0PE)
00706 
00707 /*! @brief Set the M0PE field to a new value. */
00708 #define BW_MPU_RGDn_WORD2_M0PE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M0PE), v))
00709 /*@}*/
00710 
00711 /*!
00712  * @name Register MPU_RGDn_WORD2, field M1UM[8:6] (RW)
00713  *
00714  * See M3UM description.
00715  */
00716 /*@{*/
00717 #define BP_MPU_RGDn_WORD2_M1UM (6U)        /*!< Bit position for MPU_RGDn_WORD2_M1UM. */
00718 #define BM_MPU_RGDn_WORD2_M1UM (0x000001C0U) /*!< Bit mask for MPU_RGDn_WORD2_M1UM. */
00719 #define BS_MPU_RGDn_WORD2_M1UM (3U)        /*!< Bit field size in bits for MPU_RGDn_WORD2_M1UM. */
00720 
00721 /*! @brief Read current value of the MPU_RGDn_WORD2_M1UM field. */
00722 #define BR_MPU_RGDn_WORD2_M1UM(x, n) (UNION_READ(hw_mpu_rgdn_word2_t, HW_MPU_RGDn_WORD2_ADDR(x, n), U, B.M1UM))
00723 
00724 /*! @brief Format value for bitfield MPU_RGDn_WORD2_M1UM. */
00725 #define BF_MPU_RGDn_WORD2_M1UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M1UM) & BM_MPU_RGDn_WORD2_M1UM)
00726 
00727 /*! @brief Set the M1UM field to a new value. */
00728 #define BW_MPU_RGDn_WORD2_M1UM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M1UM) | BF_MPU_RGDn_WORD2_M1UM(v)))
00729 /*@}*/
00730 
00731 /*!
00732  * @name Register MPU_RGDn_WORD2, field M1SM[10:9] (RW)
00733  *
00734  * See M3SM description.
00735  */
00736 /*@{*/
00737 #define BP_MPU_RGDn_WORD2_M1SM (9U)        /*!< Bit position for MPU_RGDn_WORD2_M1SM. */
00738 #define BM_MPU_RGDn_WORD2_M1SM (0x00000600U) /*!< Bit mask for MPU_RGDn_WORD2_M1SM. */
00739 #define BS_MPU_RGDn_WORD2_M1SM (2U)        /*!< Bit field size in bits for MPU_RGDn_WORD2_M1SM. */
00740 
00741 /*! @brief Read current value of the MPU_RGDn_WORD2_M1SM field. */
00742 #define BR_MPU_RGDn_WORD2_M1SM(x, n) (UNION_READ(hw_mpu_rgdn_word2_t, HW_MPU_RGDn_WORD2_ADDR(x, n), U, B.M1SM))
00743 
00744 /*! @brief Format value for bitfield MPU_RGDn_WORD2_M1SM. */
00745 #define BF_MPU_RGDn_WORD2_M1SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M1SM) & BM_MPU_RGDn_WORD2_M1SM)
00746 
00747 /*! @brief Set the M1SM field to a new value. */
00748 #define BW_MPU_RGDn_WORD2_M1SM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M1SM) | BF_MPU_RGDn_WORD2_M1SM(v)))
00749 /*@}*/
00750 
00751 /*!
00752  * @name Register MPU_RGDn_WORD2, field M1PE[11] (RW)
00753  *
00754  * See M3PE description.
00755  */
00756 /*@{*/
00757 #define BP_MPU_RGDn_WORD2_M1PE (11U)       /*!< Bit position for MPU_RGDn_WORD2_M1PE. */
00758 #define BM_MPU_RGDn_WORD2_M1PE (0x00000800U) /*!< Bit mask for MPU_RGDn_WORD2_M1PE. */
00759 #define BS_MPU_RGDn_WORD2_M1PE (1U)        /*!< Bit field size in bits for MPU_RGDn_WORD2_M1PE. */
00760 
00761 /*! @brief Read current value of the MPU_RGDn_WORD2_M1PE field. */
00762 #define BR_MPU_RGDn_WORD2_M1PE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M1PE)))
00763 
00764 /*! @brief Format value for bitfield MPU_RGDn_WORD2_M1PE. */
00765 #define BF_MPU_RGDn_WORD2_M1PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M1PE) & BM_MPU_RGDn_WORD2_M1PE)
00766 
00767 /*! @brief Set the M1PE field to a new value. */
00768 #define BW_MPU_RGDn_WORD2_M1PE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M1PE), v))
00769 /*@}*/
00770 
00771 /*!
00772  * @name Register MPU_RGDn_WORD2, field M2UM[14:12] (RW)
00773  *
00774  * See M3UM description.
00775  */
00776 /*@{*/
00777 #define BP_MPU_RGDn_WORD2_M2UM (12U)       /*!< Bit position for MPU_RGDn_WORD2_M2UM. */
00778 #define BM_MPU_RGDn_WORD2_M2UM (0x00007000U) /*!< Bit mask for MPU_RGDn_WORD2_M2UM. */
00779 #define BS_MPU_RGDn_WORD2_M2UM (3U)        /*!< Bit field size in bits for MPU_RGDn_WORD2_M2UM. */
00780 
00781 /*! @brief Read current value of the MPU_RGDn_WORD2_M2UM field. */
00782 #define BR_MPU_RGDn_WORD2_M2UM(x, n) (UNION_READ(hw_mpu_rgdn_word2_t, HW_MPU_RGDn_WORD2_ADDR(x, n), U, B.M2UM))
00783 
00784 /*! @brief Format value for bitfield MPU_RGDn_WORD2_M2UM. */
00785 #define BF_MPU_RGDn_WORD2_M2UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M2UM) & BM_MPU_RGDn_WORD2_M2UM)
00786 
00787 /*! @brief Set the M2UM field to a new value. */
00788 #define BW_MPU_RGDn_WORD2_M2UM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M2UM) | BF_MPU_RGDn_WORD2_M2UM(v)))
00789 /*@}*/
00790 
00791 /*!
00792  * @name Register MPU_RGDn_WORD2, field M2SM[16:15] (RW)
00793  *
00794  * See M3SM description.
00795  */
00796 /*@{*/
00797 #define BP_MPU_RGDn_WORD2_M2SM (15U)       /*!< Bit position for MPU_RGDn_WORD2_M2SM. */
00798 #define BM_MPU_RGDn_WORD2_M2SM (0x00018000U) /*!< Bit mask for MPU_RGDn_WORD2_M2SM. */
00799 #define BS_MPU_RGDn_WORD2_M2SM (2U)        /*!< Bit field size in bits for MPU_RGDn_WORD2_M2SM. */
00800 
00801 /*! @brief Read current value of the MPU_RGDn_WORD2_M2SM field. */
00802 #define BR_MPU_RGDn_WORD2_M2SM(x, n) (UNION_READ(hw_mpu_rgdn_word2_t, HW_MPU_RGDn_WORD2_ADDR(x, n), U, B.M2SM))
00803 
00804 /*! @brief Format value for bitfield MPU_RGDn_WORD2_M2SM. */
00805 #define BF_MPU_RGDn_WORD2_M2SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M2SM) & BM_MPU_RGDn_WORD2_M2SM)
00806 
00807 /*! @brief Set the M2SM field to a new value. */
00808 #define BW_MPU_RGDn_WORD2_M2SM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M2SM) | BF_MPU_RGDn_WORD2_M2SM(v)))
00809 /*@}*/
00810 
00811 /*!
00812  * @name Register MPU_RGDn_WORD2, field M2PE[17] (RW)
00813  *
00814  * See M3PE description.
00815  */
00816 /*@{*/
00817 #define BP_MPU_RGDn_WORD2_M2PE (17U)       /*!< Bit position for MPU_RGDn_WORD2_M2PE. */
00818 #define BM_MPU_RGDn_WORD2_M2PE (0x00020000U) /*!< Bit mask for MPU_RGDn_WORD2_M2PE. */
00819 #define BS_MPU_RGDn_WORD2_M2PE (1U)        /*!< Bit field size in bits for MPU_RGDn_WORD2_M2PE. */
00820 
00821 /*! @brief Read current value of the MPU_RGDn_WORD2_M2PE field. */
00822 #define BR_MPU_RGDn_WORD2_M2PE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M2PE)))
00823 
00824 /*! @brief Format value for bitfield MPU_RGDn_WORD2_M2PE. */
00825 #define BF_MPU_RGDn_WORD2_M2PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M2PE) & BM_MPU_RGDn_WORD2_M2PE)
00826 
00827 /*! @brief Set the M2PE field to a new value. */
00828 #define BW_MPU_RGDn_WORD2_M2PE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M2PE), v))
00829 /*@}*/
00830 
00831 /*!
00832  * @name Register MPU_RGDn_WORD2, field M3UM[20:18] (RW)
00833  *
00834  * Defines the access controls for bus master 3 in User mode. M3UM consists of
00835  * three independent bits, enabling read (r), write (w), and execute (x)
00836  * permissions.
00837  *
00838  * Values:
00839  * - 0 - An attempted access of that mode may be terminated with an access error
00840  *     (if not allowed by another descriptor) and the access not performed.
00841  * - 1 - Allows the given access type to occur
00842  */
00843 /*@{*/
00844 #define BP_MPU_RGDn_WORD2_M3UM (18U)       /*!< Bit position for MPU_RGDn_WORD2_M3UM. */
00845 #define BM_MPU_RGDn_WORD2_M3UM (0x001C0000U) /*!< Bit mask for MPU_RGDn_WORD2_M3UM. */
00846 #define BS_MPU_RGDn_WORD2_M3UM (3U)        /*!< Bit field size in bits for MPU_RGDn_WORD2_M3UM. */
00847 
00848 /*! @brief Read current value of the MPU_RGDn_WORD2_M3UM field. */
00849 #define BR_MPU_RGDn_WORD2_M3UM(x, n) (UNION_READ(hw_mpu_rgdn_word2_t, HW_MPU_RGDn_WORD2_ADDR(x, n), U, B.M3UM))
00850 
00851 /*! @brief Format value for bitfield MPU_RGDn_WORD2_M3UM. */
00852 #define BF_MPU_RGDn_WORD2_M3UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M3UM) & BM_MPU_RGDn_WORD2_M3UM)
00853 
00854 /*! @brief Set the M3UM field to a new value. */
00855 #define BW_MPU_RGDn_WORD2_M3UM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M3UM) | BF_MPU_RGDn_WORD2_M3UM(v)))
00856 /*@}*/
00857 
00858 /*!
00859  * @name Register MPU_RGDn_WORD2, field M3SM[22:21] (RW)
00860  *
00861  * Defines the access controls for bus master 3 in Supervisor mode.
00862  *
00863  * Values:
00864  * - 00 - r/w/x; read, write and execute allowed
00865  * - 01 - r/x; read and execute allowed, but no write
00866  * - 10 - r/w; read and write allowed, but no execute
00867  * - 11 - Same as User mode defined in M3UM
00868  */
00869 /*@{*/
00870 #define BP_MPU_RGDn_WORD2_M3SM (21U)       /*!< Bit position for MPU_RGDn_WORD2_M3SM. */
00871 #define BM_MPU_RGDn_WORD2_M3SM (0x00600000U) /*!< Bit mask for MPU_RGDn_WORD2_M3SM. */
00872 #define BS_MPU_RGDn_WORD2_M3SM (2U)        /*!< Bit field size in bits for MPU_RGDn_WORD2_M3SM. */
00873 
00874 /*! @brief Read current value of the MPU_RGDn_WORD2_M3SM field. */
00875 #define BR_MPU_RGDn_WORD2_M3SM(x, n) (UNION_READ(hw_mpu_rgdn_word2_t, HW_MPU_RGDn_WORD2_ADDR(x, n), U, B.M3SM))
00876 
00877 /*! @brief Format value for bitfield MPU_RGDn_WORD2_M3SM. */
00878 #define BF_MPU_RGDn_WORD2_M3SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M3SM) & BM_MPU_RGDn_WORD2_M3SM)
00879 
00880 /*! @brief Set the M3SM field to a new value. */
00881 #define BW_MPU_RGDn_WORD2_M3SM(x, n, v) (HW_MPU_RGDn_WORD2_WR(x, n, (HW_MPU_RGDn_WORD2_RD(x, n) & ~BM_MPU_RGDn_WORD2_M3SM) | BF_MPU_RGDn_WORD2_M3SM(v)))
00882 /*@}*/
00883 
00884 /*!
00885  * @name Register MPU_RGDn_WORD2, field M3PE[23] (RW)
00886  *
00887  * Values:
00888  * - 0 - Do not include the process identifier in the evaluation
00889  * - 1 - Include the process identifier and mask (RGDn_WORD3) in the region hit
00890  *     evaluation
00891  */
00892 /*@{*/
00893 #define BP_MPU_RGDn_WORD2_M3PE (23U)       /*!< Bit position for MPU_RGDn_WORD2_M3PE. */
00894 #define BM_MPU_RGDn_WORD2_M3PE (0x00800000U) /*!< Bit mask for MPU_RGDn_WORD2_M3PE. */
00895 #define BS_MPU_RGDn_WORD2_M3PE (1U)        /*!< Bit field size in bits for MPU_RGDn_WORD2_M3PE. */
00896 
00897 /*! @brief Read current value of the MPU_RGDn_WORD2_M3PE field. */
00898 #define BR_MPU_RGDn_WORD2_M3PE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M3PE)))
00899 
00900 /*! @brief Format value for bitfield MPU_RGDn_WORD2_M3PE. */
00901 #define BF_MPU_RGDn_WORD2_M3PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M3PE) & BM_MPU_RGDn_WORD2_M3PE)
00902 
00903 /*! @brief Set the M3PE field to a new value. */
00904 #define BW_MPU_RGDn_WORD2_M3PE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M3PE), v))
00905 /*@}*/
00906 
00907 /*!
00908  * @name Register MPU_RGDn_WORD2, field M4WE[24] (RW)
00909  *
00910  * Values:
00911  * - 0 - Bus master 4 writes terminate with an access error and the write is not
00912  *     performed
00913  * - 1 - Bus master 4 writes allowed
00914  */
00915 /*@{*/
00916 #define BP_MPU_RGDn_WORD2_M4WE (24U)       /*!< Bit position for MPU_RGDn_WORD2_M4WE. */
00917 #define BM_MPU_RGDn_WORD2_M4WE (0x01000000U) /*!< Bit mask for MPU_RGDn_WORD2_M4WE. */
00918 #define BS_MPU_RGDn_WORD2_M4WE (1U)        /*!< Bit field size in bits for MPU_RGDn_WORD2_M4WE. */
00919 
00920 /*! @brief Read current value of the MPU_RGDn_WORD2_M4WE field. */
00921 #define BR_MPU_RGDn_WORD2_M4WE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M4WE)))
00922 
00923 /*! @brief Format value for bitfield MPU_RGDn_WORD2_M4WE. */
00924 #define BF_MPU_RGDn_WORD2_M4WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M4WE) & BM_MPU_RGDn_WORD2_M4WE)
00925 
00926 /*! @brief Set the M4WE field to a new value. */
00927 #define BW_MPU_RGDn_WORD2_M4WE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M4WE), v))
00928 /*@}*/
00929 
00930 /*!
00931  * @name Register MPU_RGDn_WORD2, field M4RE[25] (RW)
00932  *
00933  * Values:
00934  * - 0 - Bus master 4 reads terminate with an access error and the read is not
00935  *     performed
00936  * - 1 - Bus master 4 reads allowed
00937  */
00938 /*@{*/
00939 #define BP_MPU_RGDn_WORD2_M4RE (25U)       /*!< Bit position for MPU_RGDn_WORD2_M4RE. */
00940 #define BM_MPU_RGDn_WORD2_M4RE (0x02000000U) /*!< Bit mask for MPU_RGDn_WORD2_M4RE. */
00941 #define BS_MPU_RGDn_WORD2_M4RE (1U)        /*!< Bit field size in bits for MPU_RGDn_WORD2_M4RE. */
00942 
00943 /*! @brief Read current value of the MPU_RGDn_WORD2_M4RE field. */
00944 #define BR_MPU_RGDn_WORD2_M4RE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M4RE)))
00945 
00946 /*! @brief Format value for bitfield MPU_RGDn_WORD2_M4RE. */
00947 #define BF_MPU_RGDn_WORD2_M4RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M4RE) & BM_MPU_RGDn_WORD2_M4RE)
00948 
00949 /*! @brief Set the M4RE field to a new value. */
00950 #define BW_MPU_RGDn_WORD2_M4RE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M4RE), v))
00951 /*@}*/
00952 
00953 /*!
00954  * @name Register MPU_RGDn_WORD2, field M5WE[26] (RW)
00955  *
00956  * Values:
00957  * - 0 - Bus master 5 writes terminate with an access error and the write is not
00958  *     performed
00959  * - 1 - Bus master 5 writes allowed
00960  */
00961 /*@{*/
00962 #define BP_MPU_RGDn_WORD2_M5WE (26U)       /*!< Bit position for MPU_RGDn_WORD2_M5WE. */
00963 #define BM_MPU_RGDn_WORD2_M5WE (0x04000000U) /*!< Bit mask for MPU_RGDn_WORD2_M5WE. */
00964 #define BS_MPU_RGDn_WORD2_M5WE (1U)        /*!< Bit field size in bits for MPU_RGDn_WORD2_M5WE. */
00965 
00966 /*! @brief Read current value of the MPU_RGDn_WORD2_M5WE field. */
00967 #define BR_MPU_RGDn_WORD2_M5WE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M5WE)))
00968 
00969 /*! @brief Format value for bitfield MPU_RGDn_WORD2_M5WE. */
00970 #define BF_MPU_RGDn_WORD2_M5WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M5WE) & BM_MPU_RGDn_WORD2_M5WE)
00971 
00972 /*! @brief Set the M5WE field to a new value. */
00973 #define BW_MPU_RGDn_WORD2_M5WE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M5WE), v))
00974 /*@}*/
00975 
00976 /*!
00977  * @name Register MPU_RGDn_WORD2, field M5RE[27] (RW)
00978  *
00979  * Values:
00980  * - 0 - Bus master 5 reads terminate with an access error and the read is not
00981  *     performed
00982  * - 1 - Bus master 5 reads allowed
00983  */
00984 /*@{*/
00985 #define BP_MPU_RGDn_WORD2_M5RE (27U)       /*!< Bit position for MPU_RGDn_WORD2_M5RE. */
00986 #define BM_MPU_RGDn_WORD2_M5RE (0x08000000U) /*!< Bit mask for MPU_RGDn_WORD2_M5RE. */
00987 #define BS_MPU_RGDn_WORD2_M5RE (1U)        /*!< Bit field size in bits for MPU_RGDn_WORD2_M5RE. */
00988 
00989 /*! @brief Read current value of the MPU_RGDn_WORD2_M5RE field. */
00990 #define BR_MPU_RGDn_WORD2_M5RE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M5RE)))
00991 
00992 /*! @brief Format value for bitfield MPU_RGDn_WORD2_M5RE. */
00993 #define BF_MPU_RGDn_WORD2_M5RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M5RE) & BM_MPU_RGDn_WORD2_M5RE)
00994 
00995 /*! @brief Set the M5RE field to a new value. */
00996 #define BW_MPU_RGDn_WORD2_M5RE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M5RE), v))
00997 /*@}*/
00998 
00999 /*!
01000  * @name Register MPU_RGDn_WORD2, field M6WE[28] (RW)
01001  *
01002  * Values:
01003  * - 0 - Bus master 6 writes terminate with an access error and the write is not
01004  *     performed
01005  * - 1 - Bus master 6 writes allowed
01006  */
01007 /*@{*/
01008 #define BP_MPU_RGDn_WORD2_M6WE (28U)       /*!< Bit position for MPU_RGDn_WORD2_M6WE. */
01009 #define BM_MPU_RGDn_WORD2_M6WE (0x10000000U) /*!< Bit mask for MPU_RGDn_WORD2_M6WE. */
01010 #define BS_MPU_RGDn_WORD2_M6WE (1U)        /*!< Bit field size in bits for MPU_RGDn_WORD2_M6WE. */
01011 
01012 /*! @brief Read current value of the MPU_RGDn_WORD2_M6WE field. */
01013 #define BR_MPU_RGDn_WORD2_M6WE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M6WE)))
01014 
01015 /*! @brief Format value for bitfield MPU_RGDn_WORD2_M6WE. */
01016 #define BF_MPU_RGDn_WORD2_M6WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M6WE) & BM_MPU_RGDn_WORD2_M6WE)
01017 
01018 /*! @brief Set the M6WE field to a new value. */
01019 #define BW_MPU_RGDn_WORD2_M6WE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M6WE), v))
01020 /*@}*/
01021 
01022 /*!
01023  * @name Register MPU_RGDn_WORD2, field M6RE[29] (RW)
01024  *
01025  * Values:
01026  * - 0 - Bus master 6 reads terminate with an access error and the read is not
01027  *     performed
01028  * - 1 - Bus master 6 reads allowed
01029  */
01030 /*@{*/
01031 #define BP_MPU_RGDn_WORD2_M6RE (29U)       /*!< Bit position for MPU_RGDn_WORD2_M6RE. */
01032 #define BM_MPU_RGDn_WORD2_M6RE (0x20000000U) /*!< Bit mask for MPU_RGDn_WORD2_M6RE. */
01033 #define BS_MPU_RGDn_WORD2_M6RE (1U)        /*!< Bit field size in bits for MPU_RGDn_WORD2_M6RE. */
01034 
01035 /*! @brief Read current value of the MPU_RGDn_WORD2_M6RE field. */
01036 #define BR_MPU_RGDn_WORD2_M6RE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M6RE)))
01037 
01038 /*! @brief Format value for bitfield MPU_RGDn_WORD2_M6RE. */
01039 #define BF_MPU_RGDn_WORD2_M6RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M6RE) & BM_MPU_RGDn_WORD2_M6RE)
01040 
01041 /*! @brief Set the M6RE field to a new value. */
01042 #define BW_MPU_RGDn_WORD2_M6RE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M6RE), v))
01043 /*@}*/
01044 
01045 /*!
01046  * @name Register MPU_RGDn_WORD2, field M7WE[30] (RW)
01047  *
01048  * Values:
01049  * - 0 - Bus master 7 writes terminate with an access error and the write is not
01050  *     performed
01051  * - 1 - Bus master 7 writes allowed
01052  */
01053 /*@{*/
01054 #define BP_MPU_RGDn_WORD2_M7WE (30U)       /*!< Bit position for MPU_RGDn_WORD2_M7WE. */
01055 #define BM_MPU_RGDn_WORD2_M7WE (0x40000000U) /*!< Bit mask for MPU_RGDn_WORD2_M7WE. */
01056 #define BS_MPU_RGDn_WORD2_M7WE (1U)        /*!< Bit field size in bits for MPU_RGDn_WORD2_M7WE. */
01057 
01058 /*! @brief Read current value of the MPU_RGDn_WORD2_M7WE field. */
01059 #define BR_MPU_RGDn_WORD2_M7WE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M7WE)))
01060 
01061 /*! @brief Format value for bitfield MPU_RGDn_WORD2_M7WE. */
01062 #define BF_MPU_RGDn_WORD2_M7WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M7WE) & BM_MPU_RGDn_WORD2_M7WE)
01063 
01064 /*! @brief Set the M7WE field to a new value. */
01065 #define BW_MPU_RGDn_WORD2_M7WE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M7WE), v))
01066 /*@}*/
01067 
01068 /*!
01069  * @name Register MPU_RGDn_WORD2, field M7RE[31] (RW)
01070  *
01071  * Values:
01072  * - 0 - Bus master 7 reads terminate with an access error and the read is not
01073  *     performed
01074  * - 1 - Bus master 7 reads allowed
01075  */
01076 /*@{*/
01077 #define BP_MPU_RGDn_WORD2_M7RE (31U)       /*!< Bit position for MPU_RGDn_WORD2_M7RE. */
01078 #define BM_MPU_RGDn_WORD2_M7RE (0x80000000U) /*!< Bit mask for MPU_RGDn_WORD2_M7RE. */
01079 #define BS_MPU_RGDn_WORD2_M7RE (1U)        /*!< Bit field size in bits for MPU_RGDn_WORD2_M7RE. */
01080 
01081 /*! @brief Read current value of the MPU_RGDn_WORD2_M7RE field. */
01082 #define BR_MPU_RGDn_WORD2_M7RE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M7RE)))
01083 
01084 /*! @brief Format value for bitfield MPU_RGDn_WORD2_M7RE. */
01085 #define BF_MPU_RGDn_WORD2_M7RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD2_M7RE) & BM_MPU_RGDn_WORD2_M7RE)
01086 
01087 /*! @brief Set the M7RE field to a new value. */
01088 #define BW_MPU_RGDn_WORD2_M7RE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDn_WORD2_ADDR(x, n), BP_MPU_RGDn_WORD2_M7RE), v))
01089 /*@}*/
01090 /*******************************************************************************
01091  * HW_MPU_RGDn_WORD3 - Region Descriptor n, Word 3
01092  ******************************************************************************/
01093 
01094 /*!
01095  * @brief HW_MPU_RGDn_WORD3 - Region Descriptor n, Word 3 (RW)
01096  *
01097  * Reset value: 0x00000001U
01098  *
01099  * The fourth word of the region descriptor contains the optional process
01100  * identifier and mask, plus the region descriptor's valid bit.
01101  */
01102 typedef union _hw_mpu_rgdn_word3
01103 {
01104     uint32_t U;
01105     struct _hw_mpu_rgdn_word3_bitfields
01106     {
01107         uint32_t VLD : 1;              /*!< [0] Valid */
01108         uint32_t RESERVED0 : 15;       /*!< [15:1]  */
01109         uint32_t PIDMASK : 8;          /*!< [23:16] Process Identifier Mask */
01110         uint32_t PID : 8;              /*!< [31:24] Process Identifier */
01111     } B;
01112 } hw_mpu_rgdn_word3_t;
01113 
01114 /*!
01115  * @name Constants and macros for entire MPU_RGDn_WORD3 register
01116  */
01117 /*@{*/
01118 #define HW_MPU_RGDn_WORD3_COUNT (12U)
01119 
01120 #define HW_MPU_RGDn_WORD3_ADDR(x, n) ((x) + 0x40CU + (0x10U * (n)))
01121 
01122 #define HW_MPU_RGDn_WORD3(x, n)  (*(__IO hw_mpu_rgdn_word3_t *) HW_MPU_RGDn_WORD3_ADDR(x, n))
01123 #define HW_MPU_RGDn_WORD3_RD(x, n) (ADDRESS_READ(hw_mpu_rgdn_word3_t, HW_MPU_RGDn_WORD3_ADDR(x, n)))
01124 #define HW_MPU_RGDn_WORD3_WR(x, n, v) (ADDRESS_WRITE(hw_mpu_rgdn_word3_t, HW_MPU_RGDn_WORD3_ADDR(x, n), v))
01125 #define HW_MPU_RGDn_WORD3_SET(x, n, v) (HW_MPU_RGDn_WORD3_WR(x, n, HW_MPU_RGDn_WORD3_RD(x, n) |  (v)))
01126 #define HW_MPU_RGDn_WORD3_CLR(x, n, v) (HW_MPU_RGDn_WORD3_WR(x, n, HW_MPU_RGDn_WORD3_RD(x, n) & ~(v)))
01127 #define HW_MPU_RGDn_WORD3_TOG(x, n, v) (HW_MPU_RGDn_WORD3_WR(x, n, HW_MPU_RGDn_WORD3_RD(x, n) ^  (v)))
01128 /*@}*/
01129 
01130 /*
01131  * Constants & macros for individual MPU_RGDn_WORD3 bitfields
01132  */
01133 
01134 /*!
01135  * @name Register MPU_RGDn_WORD3, field VLD[0] (RW)
01136  *
01137  * Signals the region descriptor is valid. Any write to RGDn_WORD0-2 clears this
01138  * bit.
01139  *
01140  * Values:
01141  * - 0 - Region descriptor is invalid
01142  * - 1 - Region descriptor is valid
01143  */
01144 /*@{*/
01145 #define BP_MPU_RGDn_WORD3_VLD (0U)         /*!< Bit position for MPU_RGDn_WORD3_VLD. */
01146 #define BM_MPU_RGDn_WORD3_VLD (0x00000001U) /*!< Bit mask for MPU_RGDn_WORD3_VLD. */
01147 #define BS_MPU_RGDn_WORD3_VLD (1U)         /*!< Bit field size in bits for MPU_RGDn_WORD3_VLD. */
01148 
01149 /*! @brief Read current value of the MPU_RGDn_WORD3_VLD field. */
01150 #define BR_MPU_RGDn_WORD3_VLD(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDn_WORD3_ADDR(x, n), BP_MPU_RGDn_WORD3_VLD)))
01151 
01152 /*! @brief Format value for bitfield MPU_RGDn_WORD3_VLD. */
01153 #define BF_MPU_RGDn_WORD3_VLD(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD3_VLD) & BM_MPU_RGDn_WORD3_VLD)
01154 
01155 /*! @brief Set the VLD field to a new value. */
01156 #define BW_MPU_RGDn_WORD3_VLD(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDn_WORD3_ADDR(x, n), BP_MPU_RGDn_WORD3_VLD), v))
01157 /*@}*/
01158 
01159 /*!
01160  * @name Register MPU_RGDn_WORD3, field PIDMASK[23:16] (RW)
01161  *
01162  * Provides a masking capability so that multiple process identifiers can be
01163  * included as part of the region hit determination. If a bit in PIDMASK is set,
01164  * then the corresponding PID bit is ignored in the comparison. This field and PID
01165  * are included in the region hit determination if RGDn_WORD2[MxPE] is set. For
01166  * more information on the handling of the PID and PIDMASK, see "Access Evaluation
01167  * - Hit Determination."
01168  */
01169 /*@{*/
01170 #define BP_MPU_RGDn_WORD3_PIDMASK (16U)    /*!< Bit position for MPU_RGDn_WORD3_PIDMASK. */
01171 #define BM_MPU_RGDn_WORD3_PIDMASK (0x00FF0000U) /*!< Bit mask for MPU_RGDn_WORD3_PIDMASK. */
01172 #define BS_MPU_RGDn_WORD3_PIDMASK (8U)     /*!< Bit field size in bits for MPU_RGDn_WORD3_PIDMASK. */
01173 
01174 /*! @brief Read current value of the MPU_RGDn_WORD3_PIDMASK field. */
01175 #define BR_MPU_RGDn_WORD3_PIDMASK(x, n) (UNION_READ(hw_mpu_rgdn_word3_t, HW_MPU_RGDn_WORD3_ADDR(x, n), U, B.PIDMASK))
01176 
01177 /*! @brief Format value for bitfield MPU_RGDn_WORD3_PIDMASK. */
01178 #define BF_MPU_RGDn_WORD3_PIDMASK(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD3_PIDMASK) & BM_MPU_RGDn_WORD3_PIDMASK)
01179 
01180 /*! @brief Set the PIDMASK field to a new value. */
01181 #define BW_MPU_RGDn_WORD3_PIDMASK(x, n, v) (HW_MPU_RGDn_WORD3_WR(x, n, (HW_MPU_RGDn_WORD3_RD(x, n) & ~BM_MPU_RGDn_WORD3_PIDMASK) | BF_MPU_RGDn_WORD3_PIDMASK(v)))
01182 /*@}*/
01183 
01184 /*!
01185  * @name Register MPU_RGDn_WORD3, field PID[31:24] (RW)
01186  *
01187  * Specifies the process identifier that is included in the region hit
01188  * determination if RGDn_WORD2[MxPE] is set. PIDMASK can mask individual bits in this
01189  * field.
01190  */
01191 /*@{*/
01192 #define BP_MPU_RGDn_WORD3_PID (24U)        /*!< Bit position for MPU_RGDn_WORD3_PID. */
01193 #define BM_MPU_RGDn_WORD3_PID (0xFF000000U) /*!< Bit mask for MPU_RGDn_WORD3_PID. */
01194 #define BS_MPU_RGDn_WORD3_PID (8U)         /*!< Bit field size in bits for MPU_RGDn_WORD3_PID. */
01195 
01196 /*! @brief Read current value of the MPU_RGDn_WORD3_PID field. */
01197 #define BR_MPU_RGDn_WORD3_PID(x, n) (UNION_READ(hw_mpu_rgdn_word3_t, HW_MPU_RGDn_WORD3_ADDR(x, n), U, B.PID))
01198 
01199 /*! @brief Format value for bitfield MPU_RGDn_WORD3_PID. */
01200 #define BF_MPU_RGDn_WORD3_PID(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDn_WORD3_PID) & BM_MPU_RGDn_WORD3_PID)
01201 
01202 /*! @brief Set the PID field to a new value. */
01203 #define BW_MPU_RGDn_WORD3_PID(x, n, v) (HW_MPU_RGDn_WORD3_WR(x, n, (HW_MPU_RGDn_WORD3_RD(x, n) & ~BM_MPU_RGDn_WORD3_PID) | BF_MPU_RGDn_WORD3_PID(v)))
01204 /*@}*/
01205 
01206 /*******************************************************************************
01207  * HW_MPU_RGDAACn - Region Descriptor Alternate Access Control n
01208  ******************************************************************************/
01209 
01210 /*!
01211  * @brief HW_MPU_RGDAACn - Region Descriptor Alternate Access Control n (RW)
01212  *
01213  * Reset value: 0x0061F7DFU
01214  *
01215  * Because software may adjust only the access controls within a region
01216  * descriptor (RGDn_WORD2) as different tasks execute, an alternate programming view of
01217  * this 32-bit entity is available. Writing to this register does not affect the
01218  * descriptor's valid bit.
01219  */
01220 typedef union _hw_mpu_rgdaacn
01221 {
01222     uint32_t U;
01223     struct _hw_mpu_rgdaacn_bitfields
01224     {
01225         uint32_t M0UM : 3;             /*!< [2:0] Bus Master 0 User Mode Access Control */
01226         uint32_t M0SM : 2;             /*!< [4:3] Bus Master 0 Supervisor Mode Access
01227                                         * Control */
01228         uint32_t M0PE : 1;             /*!< [5] Bus Master 0 Process Identifier Enable */
01229         uint32_t M1UM : 3;             /*!< [8:6] Bus Master 1 User Mode Access Control */
01230         uint32_t M1SM : 2;             /*!< [10:9] Bus Master 1 Supervisor Mode Access
01231                                         * Control */
01232         uint32_t M1PE : 1;             /*!< [11] Bus Master 1 Process Identifier Enable */
01233         uint32_t M2UM : 3;             /*!< [14:12] Bus Master 2 User Mode Access Control
01234                                         * */
01235         uint32_t M2SM : 2;             /*!< [16:15] Bus Master 2 Supervisor Mode Access
01236                                         * Control */
01237         uint32_t M2PE : 1;             /*!< [17] Bus Master 2 Process Identifier Enable */
01238         uint32_t M3UM : 3;             /*!< [20:18] Bus Master 3 User Mode Access Control
01239                                         * */
01240         uint32_t M3SM : 2;             /*!< [22:21] Bus Master 3 Supervisor Mode Access
01241                                         * Control */
01242         uint32_t M3PE : 1;             /*!< [23] Bus Master 3 Process Identifier Enable */
01243         uint32_t M4WE : 1;             /*!< [24] Bus Master 4 Write Enable */
01244         uint32_t M4RE : 1;             /*!< [25] Bus Master 4 Read Enable */
01245         uint32_t M5WE : 1;             /*!< [26] Bus Master 5 Write Enable */
01246         uint32_t M5RE : 1;             /*!< [27] Bus Master 5 Read Enable */
01247         uint32_t M6WE : 1;             /*!< [28] Bus Master 6 Write Enable */
01248         uint32_t M6RE : 1;             /*!< [29] Bus Master 6 Read Enable */
01249         uint32_t M7WE : 1;             /*!< [30] Bus Master 7 Write Enable */
01250         uint32_t M7RE : 1;             /*!< [31] Bus Master 7 Read Enable */
01251     } B;
01252 } hw_mpu_rgdaacn_t;
01253 
01254 /*!
01255  * @name Constants and macros for entire MPU_RGDAACn register
01256  */
01257 /*@{*/
01258 #define HW_MPU_RGDAACn_COUNT (12U)
01259 
01260 #define HW_MPU_RGDAACn_ADDR(x, n) ((x) + 0x800U + (0x4U * (n)))
01261 
01262 #define HW_MPU_RGDAACn(x, n)     (*(__IO hw_mpu_rgdaacn_t *) HW_MPU_RGDAACn_ADDR(x, n))
01263 #define HW_MPU_RGDAACn_RD(x, n)  (ADDRESS_READ(hw_mpu_rgdaacn_t, HW_MPU_RGDAACn_ADDR(x, n)))
01264 #define HW_MPU_RGDAACn_WR(x, n, v) (ADDRESS_WRITE(hw_mpu_rgdaacn_t, HW_MPU_RGDAACn_ADDR(x, n), v))
01265 #define HW_MPU_RGDAACn_SET(x, n, v) (HW_MPU_RGDAACn_WR(x, n, HW_MPU_RGDAACn_RD(x, n) |  (v)))
01266 #define HW_MPU_RGDAACn_CLR(x, n, v) (HW_MPU_RGDAACn_WR(x, n, HW_MPU_RGDAACn_RD(x, n) & ~(v)))
01267 #define HW_MPU_RGDAACn_TOG(x, n, v) (HW_MPU_RGDAACn_WR(x, n, HW_MPU_RGDAACn_RD(x, n) ^  (v)))
01268 /*@}*/
01269 
01270 /*
01271  * Constants & macros for individual MPU_RGDAACn bitfields
01272  */
01273 
01274 /*!
01275  * @name Register MPU_RGDAACn, field M0UM[2:0] (RW)
01276  *
01277  * See M3UM description.
01278  */
01279 /*@{*/
01280 #define BP_MPU_RGDAACn_M0UM  (0U)          /*!< Bit position for MPU_RGDAACn_M0UM. */
01281 #define BM_MPU_RGDAACn_M0UM  (0x00000007U) /*!< Bit mask for MPU_RGDAACn_M0UM. */
01282 #define BS_MPU_RGDAACn_M0UM  (3U)          /*!< Bit field size in bits for MPU_RGDAACn_M0UM. */
01283 
01284 /*! @brief Read current value of the MPU_RGDAACn_M0UM field. */
01285 #define BR_MPU_RGDAACn_M0UM(x, n) (UNION_READ(hw_mpu_rgdaacn_t, HW_MPU_RGDAACn_ADDR(x, n), U, B.M0UM))
01286 
01287 /*! @brief Format value for bitfield MPU_RGDAACn_M0UM. */
01288 #define BF_MPU_RGDAACn_M0UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M0UM) & BM_MPU_RGDAACn_M0UM)
01289 
01290 /*! @brief Set the M0UM field to a new value. */
01291 #define BW_MPU_RGDAACn_M0UM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M0UM) | BF_MPU_RGDAACn_M0UM(v)))
01292 /*@}*/
01293 
01294 /*!
01295  * @name Register MPU_RGDAACn, field M0SM[4:3] (RW)
01296  *
01297  * See M3SM description.
01298  */
01299 /*@{*/
01300 #define BP_MPU_RGDAACn_M0SM  (3U)          /*!< Bit position for MPU_RGDAACn_M0SM. */
01301 #define BM_MPU_RGDAACn_M0SM  (0x00000018U) /*!< Bit mask for MPU_RGDAACn_M0SM. */
01302 #define BS_MPU_RGDAACn_M0SM  (2U)          /*!< Bit field size in bits for MPU_RGDAACn_M0SM. */
01303 
01304 /*! @brief Read current value of the MPU_RGDAACn_M0SM field. */
01305 #define BR_MPU_RGDAACn_M0SM(x, n) (UNION_READ(hw_mpu_rgdaacn_t, HW_MPU_RGDAACn_ADDR(x, n), U, B.M0SM))
01306 
01307 /*! @brief Format value for bitfield MPU_RGDAACn_M0SM. */
01308 #define BF_MPU_RGDAACn_M0SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M0SM) & BM_MPU_RGDAACn_M0SM)
01309 
01310 /*! @brief Set the M0SM field to a new value. */
01311 #define BW_MPU_RGDAACn_M0SM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M0SM) | BF_MPU_RGDAACn_M0SM(v)))
01312 /*@}*/
01313 
01314 /*!
01315  * @name Register MPU_RGDAACn, field M0PE[5] (RW)
01316  *
01317  * See M3PE description.
01318  */
01319 /*@{*/
01320 #define BP_MPU_RGDAACn_M0PE  (5U)          /*!< Bit position for MPU_RGDAACn_M0PE. */
01321 #define BM_MPU_RGDAACn_M0PE  (0x00000020U) /*!< Bit mask for MPU_RGDAACn_M0PE. */
01322 #define BS_MPU_RGDAACn_M0PE  (1U)          /*!< Bit field size in bits for MPU_RGDAACn_M0PE. */
01323 
01324 /*! @brief Read current value of the MPU_RGDAACn_M0PE field. */
01325 #define BR_MPU_RGDAACn_M0PE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M0PE)))
01326 
01327 /*! @brief Format value for bitfield MPU_RGDAACn_M0PE. */
01328 #define BF_MPU_RGDAACn_M0PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M0PE) & BM_MPU_RGDAACn_M0PE)
01329 
01330 /*! @brief Set the M0PE field to a new value. */
01331 #define BW_MPU_RGDAACn_M0PE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M0PE), v))
01332 /*@}*/
01333 
01334 /*!
01335  * @name Register MPU_RGDAACn, field M1UM[8:6] (RW)
01336  *
01337  * See M3UM description.
01338  */
01339 /*@{*/
01340 #define BP_MPU_RGDAACn_M1UM  (6U)          /*!< Bit position for MPU_RGDAACn_M1UM. */
01341 #define BM_MPU_RGDAACn_M1UM  (0x000001C0U) /*!< Bit mask for MPU_RGDAACn_M1UM. */
01342 #define BS_MPU_RGDAACn_M1UM  (3U)          /*!< Bit field size in bits for MPU_RGDAACn_M1UM. */
01343 
01344 /*! @brief Read current value of the MPU_RGDAACn_M1UM field. */
01345 #define BR_MPU_RGDAACn_M1UM(x, n) (UNION_READ(hw_mpu_rgdaacn_t, HW_MPU_RGDAACn_ADDR(x, n), U, B.M1UM))
01346 
01347 /*! @brief Format value for bitfield MPU_RGDAACn_M1UM. */
01348 #define BF_MPU_RGDAACn_M1UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M1UM) & BM_MPU_RGDAACn_M1UM)
01349 
01350 /*! @brief Set the M1UM field to a new value. */
01351 #define BW_MPU_RGDAACn_M1UM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M1UM) | BF_MPU_RGDAACn_M1UM(v)))
01352 /*@}*/
01353 
01354 /*!
01355  * @name Register MPU_RGDAACn, field M1SM[10:9] (RW)
01356  *
01357  * See M3SM description.
01358  */
01359 /*@{*/
01360 #define BP_MPU_RGDAACn_M1SM  (9U)          /*!< Bit position for MPU_RGDAACn_M1SM. */
01361 #define BM_MPU_RGDAACn_M1SM  (0x00000600U) /*!< Bit mask for MPU_RGDAACn_M1SM. */
01362 #define BS_MPU_RGDAACn_M1SM  (2U)          /*!< Bit field size in bits for MPU_RGDAACn_M1SM. */
01363 
01364 /*! @brief Read current value of the MPU_RGDAACn_M1SM field. */
01365 #define BR_MPU_RGDAACn_M1SM(x, n) (UNION_READ(hw_mpu_rgdaacn_t, HW_MPU_RGDAACn_ADDR(x, n), U, B.M1SM))
01366 
01367 /*! @brief Format value for bitfield MPU_RGDAACn_M1SM. */
01368 #define BF_MPU_RGDAACn_M1SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M1SM) & BM_MPU_RGDAACn_M1SM)
01369 
01370 /*! @brief Set the M1SM field to a new value. */
01371 #define BW_MPU_RGDAACn_M1SM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M1SM) | BF_MPU_RGDAACn_M1SM(v)))
01372 /*@}*/
01373 
01374 /*!
01375  * @name Register MPU_RGDAACn, field M1PE[11] (RW)
01376  *
01377  * See M3PE description.
01378  */
01379 /*@{*/
01380 #define BP_MPU_RGDAACn_M1PE  (11U)         /*!< Bit position for MPU_RGDAACn_M1PE. */
01381 #define BM_MPU_RGDAACn_M1PE  (0x00000800U) /*!< Bit mask for MPU_RGDAACn_M1PE. */
01382 #define BS_MPU_RGDAACn_M1PE  (1U)          /*!< Bit field size in bits for MPU_RGDAACn_M1PE. */
01383 
01384 /*! @brief Read current value of the MPU_RGDAACn_M1PE field. */
01385 #define BR_MPU_RGDAACn_M1PE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M1PE)))
01386 
01387 /*! @brief Format value for bitfield MPU_RGDAACn_M1PE. */
01388 #define BF_MPU_RGDAACn_M1PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M1PE) & BM_MPU_RGDAACn_M1PE)
01389 
01390 /*! @brief Set the M1PE field to a new value. */
01391 #define BW_MPU_RGDAACn_M1PE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M1PE), v))
01392 /*@}*/
01393 
01394 /*!
01395  * @name Register MPU_RGDAACn, field M2UM[14:12] (RW)
01396  *
01397  * See M3UM description.
01398  */
01399 /*@{*/
01400 #define BP_MPU_RGDAACn_M2UM  (12U)         /*!< Bit position for MPU_RGDAACn_M2UM. */
01401 #define BM_MPU_RGDAACn_M2UM  (0x00007000U) /*!< Bit mask for MPU_RGDAACn_M2UM. */
01402 #define BS_MPU_RGDAACn_M2UM  (3U)          /*!< Bit field size in bits for MPU_RGDAACn_M2UM. */
01403 
01404 /*! @brief Read current value of the MPU_RGDAACn_M2UM field. */
01405 #define BR_MPU_RGDAACn_M2UM(x, n) (UNION_READ(hw_mpu_rgdaacn_t, HW_MPU_RGDAACn_ADDR(x, n), U, B.M2UM))
01406 
01407 /*! @brief Format value for bitfield MPU_RGDAACn_M2UM. */
01408 #define BF_MPU_RGDAACn_M2UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M2UM) & BM_MPU_RGDAACn_M2UM)
01409 
01410 /*! @brief Set the M2UM field to a new value. */
01411 #define BW_MPU_RGDAACn_M2UM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M2UM) | BF_MPU_RGDAACn_M2UM(v)))
01412 /*@}*/
01413 
01414 /*!
01415  * @name Register MPU_RGDAACn, field M2SM[16:15] (RW)
01416  *
01417  * See M3SM description.
01418  */
01419 /*@{*/
01420 #define BP_MPU_RGDAACn_M2SM  (15U)         /*!< Bit position for MPU_RGDAACn_M2SM. */
01421 #define BM_MPU_RGDAACn_M2SM  (0x00018000U) /*!< Bit mask for MPU_RGDAACn_M2SM. */
01422 #define BS_MPU_RGDAACn_M2SM  (2U)          /*!< Bit field size in bits for MPU_RGDAACn_M2SM. */
01423 
01424 /*! @brief Read current value of the MPU_RGDAACn_M2SM field. */
01425 #define BR_MPU_RGDAACn_M2SM(x, n) (UNION_READ(hw_mpu_rgdaacn_t, HW_MPU_RGDAACn_ADDR(x, n), U, B.M2SM))
01426 
01427 /*! @brief Format value for bitfield MPU_RGDAACn_M2SM. */
01428 #define BF_MPU_RGDAACn_M2SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M2SM) & BM_MPU_RGDAACn_M2SM)
01429 
01430 /*! @brief Set the M2SM field to a new value. */
01431 #define BW_MPU_RGDAACn_M2SM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M2SM) | BF_MPU_RGDAACn_M2SM(v)))
01432 /*@}*/
01433 
01434 /*!
01435  * @name Register MPU_RGDAACn, field M2PE[17] (RW)
01436  *
01437  * See M3PE description.
01438  */
01439 /*@{*/
01440 #define BP_MPU_RGDAACn_M2PE  (17U)         /*!< Bit position for MPU_RGDAACn_M2PE. */
01441 #define BM_MPU_RGDAACn_M2PE  (0x00020000U) /*!< Bit mask for MPU_RGDAACn_M2PE. */
01442 #define BS_MPU_RGDAACn_M2PE  (1U)          /*!< Bit field size in bits for MPU_RGDAACn_M2PE. */
01443 
01444 /*! @brief Read current value of the MPU_RGDAACn_M2PE field. */
01445 #define BR_MPU_RGDAACn_M2PE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M2PE)))
01446 
01447 /*! @brief Format value for bitfield MPU_RGDAACn_M2PE. */
01448 #define BF_MPU_RGDAACn_M2PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M2PE) & BM_MPU_RGDAACn_M2PE)
01449 
01450 /*! @brief Set the M2PE field to a new value. */
01451 #define BW_MPU_RGDAACn_M2PE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M2PE), v))
01452 /*@}*/
01453 
01454 /*!
01455  * @name Register MPU_RGDAACn, field M3UM[20:18] (RW)
01456  *
01457  * Defines the access controls for bus master 3 in user mode. M3UM consists of
01458  * three independent bits, enabling read (r), write (w), and execute (x)
01459  * permissions.
01460  *
01461  * Values:
01462  * - 0 - An attempted access of that mode may be terminated with an access error
01463  *     (if not allowed by another descriptor) and the access not performed.
01464  * - 1 - Allows the given access type to occur
01465  */
01466 /*@{*/
01467 #define BP_MPU_RGDAACn_M3UM  (18U)         /*!< Bit position for MPU_RGDAACn_M3UM. */
01468 #define BM_MPU_RGDAACn_M3UM  (0x001C0000U) /*!< Bit mask for MPU_RGDAACn_M3UM. */
01469 #define BS_MPU_RGDAACn_M3UM  (3U)          /*!< Bit field size in bits for MPU_RGDAACn_M3UM. */
01470 
01471 /*! @brief Read current value of the MPU_RGDAACn_M3UM field. */
01472 #define BR_MPU_RGDAACn_M3UM(x, n) (UNION_READ(hw_mpu_rgdaacn_t, HW_MPU_RGDAACn_ADDR(x, n), U, B.M3UM))
01473 
01474 /*! @brief Format value for bitfield MPU_RGDAACn_M3UM. */
01475 #define BF_MPU_RGDAACn_M3UM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M3UM) & BM_MPU_RGDAACn_M3UM)
01476 
01477 /*! @brief Set the M3UM field to a new value. */
01478 #define BW_MPU_RGDAACn_M3UM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M3UM) | BF_MPU_RGDAACn_M3UM(v)))
01479 /*@}*/
01480 
01481 /*!
01482  * @name Register MPU_RGDAACn, field M3SM[22:21] (RW)
01483  *
01484  * Defines the access controls for bus master 3 in Supervisor mode.
01485  *
01486  * Values:
01487  * - 00 - r/w/x; read, write and execute allowed
01488  * - 01 - r/x; read and execute allowed, but no write
01489  * - 10 - r/w; read and write allowed, but no execute
01490  * - 11 - Same as User mode defined in M3UM
01491  */
01492 /*@{*/
01493 #define BP_MPU_RGDAACn_M3SM  (21U)         /*!< Bit position for MPU_RGDAACn_M3SM. */
01494 #define BM_MPU_RGDAACn_M3SM  (0x00600000U) /*!< Bit mask for MPU_RGDAACn_M3SM. */
01495 #define BS_MPU_RGDAACn_M3SM  (2U)          /*!< Bit field size in bits for MPU_RGDAACn_M3SM. */
01496 
01497 /*! @brief Read current value of the MPU_RGDAACn_M3SM field. */
01498 #define BR_MPU_RGDAACn_M3SM(x, n) (UNION_READ(hw_mpu_rgdaacn_t, HW_MPU_RGDAACn_ADDR(x, n), U, B.M3SM))
01499 
01500 /*! @brief Format value for bitfield MPU_RGDAACn_M3SM. */
01501 #define BF_MPU_RGDAACn_M3SM(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M3SM) & BM_MPU_RGDAACn_M3SM)
01502 
01503 /*! @brief Set the M3SM field to a new value. */
01504 #define BW_MPU_RGDAACn_M3SM(x, n, v) (HW_MPU_RGDAACn_WR(x, n, (HW_MPU_RGDAACn_RD(x, n) & ~BM_MPU_RGDAACn_M3SM) | BF_MPU_RGDAACn_M3SM(v)))
01505 /*@}*/
01506 
01507 /*!
01508  * @name Register MPU_RGDAACn, field M3PE[23] (RW)
01509  *
01510  * Values:
01511  * - 0 - Do not include the process identifier in the evaluation
01512  * - 1 - Include the process identifier and mask (RGDn.RGDAAC) in the region hit
01513  *     evaluation
01514  */
01515 /*@{*/
01516 #define BP_MPU_RGDAACn_M3PE  (23U)         /*!< Bit position for MPU_RGDAACn_M3PE. */
01517 #define BM_MPU_RGDAACn_M3PE  (0x00800000U) /*!< Bit mask for MPU_RGDAACn_M3PE. */
01518 #define BS_MPU_RGDAACn_M3PE  (1U)          /*!< Bit field size in bits for MPU_RGDAACn_M3PE. */
01519 
01520 /*! @brief Read current value of the MPU_RGDAACn_M3PE field. */
01521 #define BR_MPU_RGDAACn_M3PE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M3PE)))
01522 
01523 /*! @brief Format value for bitfield MPU_RGDAACn_M3PE. */
01524 #define BF_MPU_RGDAACn_M3PE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M3PE) & BM_MPU_RGDAACn_M3PE)
01525 
01526 /*! @brief Set the M3PE field to a new value. */
01527 #define BW_MPU_RGDAACn_M3PE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M3PE), v))
01528 /*@}*/
01529 
01530 /*!
01531  * @name Register MPU_RGDAACn, field M4WE[24] (RW)
01532  *
01533  * Values:
01534  * - 0 - Bus master 4 writes terminate with an access error and the write is not
01535  *     performed
01536  * - 1 - Bus master 4 writes allowed
01537  */
01538 /*@{*/
01539 #define BP_MPU_RGDAACn_M4WE  (24U)         /*!< Bit position for MPU_RGDAACn_M4WE. */
01540 #define BM_MPU_RGDAACn_M4WE  (0x01000000U) /*!< Bit mask for MPU_RGDAACn_M4WE. */
01541 #define BS_MPU_RGDAACn_M4WE  (1U)          /*!< Bit field size in bits for MPU_RGDAACn_M4WE. */
01542 
01543 /*! @brief Read current value of the MPU_RGDAACn_M4WE field. */
01544 #define BR_MPU_RGDAACn_M4WE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M4WE)))
01545 
01546 /*! @brief Format value for bitfield MPU_RGDAACn_M4WE. */
01547 #define BF_MPU_RGDAACn_M4WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M4WE) & BM_MPU_RGDAACn_M4WE)
01548 
01549 /*! @brief Set the M4WE field to a new value. */
01550 #define BW_MPU_RGDAACn_M4WE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M4WE), v))
01551 /*@}*/
01552 
01553 /*!
01554  * @name Register MPU_RGDAACn, field M4RE[25] (RW)
01555  *
01556  * Values:
01557  * - 0 - Bus master 4 reads terminate with an access error and the read is not
01558  *     performed
01559  * - 1 - Bus master 4 reads allowed
01560  */
01561 /*@{*/
01562 #define BP_MPU_RGDAACn_M4RE  (25U)         /*!< Bit position for MPU_RGDAACn_M4RE. */
01563 #define BM_MPU_RGDAACn_M4RE  (0x02000000U) /*!< Bit mask for MPU_RGDAACn_M4RE. */
01564 #define BS_MPU_RGDAACn_M4RE  (1U)          /*!< Bit field size in bits for MPU_RGDAACn_M4RE. */
01565 
01566 /*! @brief Read current value of the MPU_RGDAACn_M4RE field. */
01567 #define BR_MPU_RGDAACn_M4RE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M4RE)))
01568 
01569 /*! @brief Format value for bitfield MPU_RGDAACn_M4RE. */
01570 #define BF_MPU_RGDAACn_M4RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M4RE) & BM_MPU_RGDAACn_M4RE)
01571 
01572 /*! @brief Set the M4RE field to a new value. */
01573 #define BW_MPU_RGDAACn_M4RE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M4RE), v))
01574 /*@}*/
01575 
01576 /*!
01577  * @name Register MPU_RGDAACn, field M5WE[26] (RW)
01578  *
01579  * Values:
01580  * - 0 - Bus master 5 writes terminate with an access error and the write is not
01581  *     performed
01582  * - 1 - Bus master 5 writes allowed
01583  */
01584 /*@{*/
01585 #define BP_MPU_RGDAACn_M5WE  (26U)         /*!< Bit position for MPU_RGDAACn_M5WE. */
01586 #define BM_MPU_RGDAACn_M5WE  (0x04000000U) /*!< Bit mask for MPU_RGDAACn_M5WE. */
01587 #define BS_MPU_RGDAACn_M5WE  (1U)          /*!< Bit field size in bits for MPU_RGDAACn_M5WE. */
01588 
01589 /*! @brief Read current value of the MPU_RGDAACn_M5WE field. */
01590 #define BR_MPU_RGDAACn_M5WE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M5WE)))
01591 
01592 /*! @brief Format value for bitfield MPU_RGDAACn_M5WE. */
01593 #define BF_MPU_RGDAACn_M5WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M5WE) & BM_MPU_RGDAACn_M5WE)
01594 
01595 /*! @brief Set the M5WE field to a new value. */
01596 #define BW_MPU_RGDAACn_M5WE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M5WE), v))
01597 /*@}*/
01598 
01599 /*!
01600  * @name Register MPU_RGDAACn, field M5RE[27] (RW)
01601  *
01602  * Values:
01603  * - 0 - Bus master 5 reads terminate with an access error and the read is not
01604  *     performed
01605  * - 1 - Bus master 5 reads allowed
01606  */
01607 /*@{*/
01608 #define BP_MPU_RGDAACn_M5RE  (27U)         /*!< Bit position for MPU_RGDAACn_M5RE. */
01609 #define BM_MPU_RGDAACn_M5RE  (0x08000000U) /*!< Bit mask for MPU_RGDAACn_M5RE. */
01610 #define BS_MPU_RGDAACn_M5RE  (1U)          /*!< Bit field size in bits for MPU_RGDAACn_M5RE. */
01611 
01612 /*! @brief Read current value of the MPU_RGDAACn_M5RE field. */
01613 #define BR_MPU_RGDAACn_M5RE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M5RE)))
01614 
01615 /*! @brief Format value for bitfield MPU_RGDAACn_M5RE. */
01616 #define BF_MPU_RGDAACn_M5RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M5RE) & BM_MPU_RGDAACn_M5RE)
01617 
01618 /*! @brief Set the M5RE field to a new value. */
01619 #define BW_MPU_RGDAACn_M5RE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M5RE), v))
01620 /*@}*/
01621 
01622 /*!
01623  * @name Register MPU_RGDAACn, field M6WE[28] (RW)
01624  *
01625  * Values:
01626  * - 0 - Bus master 6 writes terminate with an access error and the write is not
01627  *     performed
01628  * - 1 - Bus master 6 writes allowed
01629  */
01630 /*@{*/
01631 #define BP_MPU_RGDAACn_M6WE  (28U)         /*!< Bit position for MPU_RGDAACn_M6WE. */
01632 #define BM_MPU_RGDAACn_M6WE  (0x10000000U) /*!< Bit mask for MPU_RGDAACn_M6WE. */
01633 #define BS_MPU_RGDAACn_M6WE  (1U)          /*!< Bit field size in bits for MPU_RGDAACn_M6WE. */
01634 
01635 /*! @brief Read current value of the MPU_RGDAACn_M6WE field. */
01636 #define BR_MPU_RGDAACn_M6WE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M6WE)))
01637 
01638 /*! @brief Format value for bitfield MPU_RGDAACn_M6WE. */
01639 #define BF_MPU_RGDAACn_M6WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M6WE) & BM_MPU_RGDAACn_M6WE)
01640 
01641 /*! @brief Set the M6WE field to a new value. */
01642 #define BW_MPU_RGDAACn_M6WE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M6WE), v))
01643 /*@}*/
01644 
01645 /*!
01646  * @name Register MPU_RGDAACn, field M6RE[29] (RW)
01647  *
01648  * Values:
01649  * - 0 - Bus master 6 reads terminate with an access error and the read is not
01650  *     performed
01651  * - 1 - Bus master 6 reads allowed
01652  */
01653 /*@{*/
01654 #define BP_MPU_RGDAACn_M6RE  (29U)         /*!< Bit position for MPU_RGDAACn_M6RE. */
01655 #define BM_MPU_RGDAACn_M6RE  (0x20000000U) /*!< Bit mask for MPU_RGDAACn_M6RE. */
01656 #define BS_MPU_RGDAACn_M6RE  (1U)          /*!< Bit field size in bits for MPU_RGDAACn_M6RE. */
01657 
01658 /*! @brief Read current value of the MPU_RGDAACn_M6RE field. */
01659 #define BR_MPU_RGDAACn_M6RE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M6RE)))
01660 
01661 /*! @brief Format value for bitfield MPU_RGDAACn_M6RE. */
01662 #define BF_MPU_RGDAACn_M6RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M6RE) & BM_MPU_RGDAACn_M6RE)
01663 
01664 /*! @brief Set the M6RE field to a new value. */
01665 #define BW_MPU_RGDAACn_M6RE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M6RE), v))
01666 /*@}*/
01667 
01668 /*!
01669  * @name Register MPU_RGDAACn, field M7WE[30] (RW)
01670  *
01671  * Values:
01672  * - 0 - Bus master 7 writes terminate with an access error and the write is not
01673  *     performed
01674  * - 1 - Bus master 7 writes allowed
01675  */
01676 /*@{*/
01677 #define BP_MPU_RGDAACn_M7WE  (30U)         /*!< Bit position for MPU_RGDAACn_M7WE. */
01678 #define BM_MPU_RGDAACn_M7WE  (0x40000000U) /*!< Bit mask for MPU_RGDAACn_M7WE. */
01679 #define BS_MPU_RGDAACn_M7WE  (1U)          /*!< Bit field size in bits for MPU_RGDAACn_M7WE. */
01680 
01681 /*! @brief Read current value of the MPU_RGDAACn_M7WE field. */
01682 #define BR_MPU_RGDAACn_M7WE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M7WE)))
01683 
01684 /*! @brief Format value for bitfield MPU_RGDAACn_M7WE. */
01685 #define BF_MPU_RGDAACn_M7WE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M7WE) & BM_MPU_RGDAACn_M7WE)
01686 
01687 /*! @brief Set the M7WE field to a new value. */
01688 #define BW_MPU_RGDAACn_M7WE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M7WE), v))
01689 /*@}*/
01690 
01691 /*!
01692  * @name Register MPU_RGDAACn, field M7RE[31] (RW)
01693  *
01694  * Values:
01695  * - 0 - Bus master 7 reads terminate with an access error and the read is not
01696  *     performed
01697  * - 1 - Bus master 7 reads allowed
01698  */
01699 /*@{*/
01700 #define BP_MPU_RGDAACn_M7RE  (31U)         /*!< Bit position for MPU_RGDAACn_M7RE. */
01701 #define BM_MPU_RGDAACn_M7RE  (0x80000000U) /*!< Bit mask for MPU_RGDAACn_M7RE. */
01702 #define BS_MPU_RGDAACn_M7RE  (1U)          /*!< Bit field size in bits for MPU_RGDAACn_M7RE. */
01703 
01704 /*! @brief Read current value of the MPU_RGDAACn_M7RE field. */
01705 #define BR_MPU_RGDAACn_M7RE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M7RE)))
01706 
01707 /*! @brief Format value for bitfield MPU_RGDAACn_M7RE. */
01708 #define BF_MPU_RGDAACn_M7RE(v) ((uint32_t)((uint32_t)(v) << BP_MPU_RGDAACn_M7RE) & BM_MPU_RGDAACn_M7RE)
01709 
01710 /*! @brief Set the M7RE field to a new value. */
01711 #define BW_MPU_RGDAACn_M7RE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_MPU_RGDAACn_ADDR(x, n), BP_MPU_RGDAACn_M7RE), v))
01712 /*@}*/
01713 
01714 /*******************************************************************************
01715  * hw_mpu_t - module struct
01716  ******************************************************************************/
01717 /*!
01718  * @brief All MPU module registers.
01719  */
01720 #pragma pack(1)
01721 typedef struct _hw_mpu
01722 {
01723     __IO hw_mpu_cesr_t CESR ;               /*!< [0x0] Control/Error Status Register */
01724     uint8_t _reserved0[12];
01725     struct {
01726         __I hw_mpu_earn_t EARn ;            /*!< [0x10] Error Address Register, slave port n */
01727         __I hw_mpu_edrn_t EDRn ;            /*!< [0x14] Error Detail Register, slave port n */
01728     } SP[5];
01729     uint8_t _reserved1[968];
01730     struct {
01731         __IO hw_mpu_rgdn_word0_t RGDn_WORD0 ; /*!< [0x400] Region Descriptor n, Word 0 */
01732         __IO hw_mpu_rgdn_word1_t RGDn_WORD1 ; /*!< [0x404] Region Descriptor n, Word 1 */
01733         __IO hw_mpu_rgdn_word2_t RGDn_WORD2 ; /*!< [0x408] Region Descriptor n, Word 2 */
01734         __IO hw_mpu_rgdn_word3_t RGDn_WORD3 ; /*!< [0x40C] Region Descriptor n, Word 3 */
01735     } RGD[12];
01736     uint8_t _reserved2[832];
01737     __IO hw_mpu_rgdaacn_t RGDAACn [12];     /*!< [0x800] Region Descriptor Alternate Access Control n */
01738 } hw_mpu_t;
01739 #pragma pack()
01740 
01741 /*! @brief Macro to access all MPU registers. */
01742 /*! @param x MPU module instance base address. */
01743 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
01744  *     use the '&' operator, like <code>&HW_MPU(MPU_BASE)</code>. */
01745 #define HW_MPU(x)      (*(hw_mpu_t *)(x))
01746 
01747 #endif /* __HW_MPU_REGISTERS_H__ */
01748 /* EOF */