MK64F12_mcm.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_MCM_REGISTERS_H__
00088 #define __HW_MCM_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 MCM
00095  *
00096  * Core Platform Miscellaneous Control Module
00097  *
00098  * Registers defined in this header file:
00099  * - HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
00100  * - HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
00101  * - HW_MCM_CR - Control Register
00102  * - HW_MCM_ISCR - Interrupt Status Register
00103  * - HW_MCM_ETBCC - ETB Counter Control register
00104  * - HW_MCM_ETBRL - ETB Reload register
00105  * - HW_MCM_ETBCNT - ETB Counter Value register
00106  * - HW_MCM_PID - Process ID register
00107  *
00108  * - hw_mcm_t - Struct containing all module registers.
00109  */
00110 
00111 #define HW_MCM_INSTANCE_COUNT (1U) /*!< Number of instances of the MCM module. */
00112 
00113 /*******************************************************************************
00114  * HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
00115  ******************************************************************************/
00116 
00117 /*!
00118  * @brief HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration (RO)
00119  *
00120  * Reset value: 0x001FU
00121  *
00122  * PLASC is a 16-bit read-only register identifying the presence/absence of bus
00123  * slave connections to the device's crossbar switch.
00124  */
00125 typedef union _hw_mcm_plasc
00126 {
00127     uint16_t U;
00128     struct _hw_mcm_plasc_bitfields
00129     {
00130         uint16_t ASC : 8;              /*!< [7:0] Each bit in the ASC field indicates
00131                                         * whether there is a corresponding connection to the crossbar switch's slave
00132                                         * input port. */
00133         uint16_t RESERVED0 : 8;        /*!< [15:8]  */
00134     } B;
00135 } hw_mcm_plasc_t;
00136 
00137 /*!
00138  * @name Constants and macros for entire MCM_PLASC register
00139  */
00140 /*@{*/
00141 #define HW_MCM_PLASC_ADDR(x)     ((x) + 0x8U)
00142 
00143 #define HW_MCM_PLASC(x)          (*(__I hw_mcm_plasc_t *) HW_MCM_PLASC_ADDR(x))
00144 #define HW_MCM_PLASC_RD(x)       (ADDRESS_READ(hw_mcm_plasc_t, HW_MCM_PLASC_ADDR(x)))
00145 /*@}*/
00146 
00147 /*
00148  * Constants & macros for individual MCM_PLASC bitfields
00149  */
00150 
00151 /*!
00152  * @name Register MCM_PLASC, field ASC[7:0] (RO)
00153  *
00154  * Values:
00155  * - 0 - A bus slave connection to AXBS input port n is absent
00156  * - 1 - A bus slave connection to AXBS input port n is present
00157  */
00158 /*@{*/
00159 #define BP_MCM_PLASC_ASC     (0U)          /*!< Bit position for MCM_PLASC_ASC. */
00160 #define BM_MCM_PLASC_ASC     (0x00FFU)     /*!< Bit mask for MCM_PLASC_ASC. */
00161 #define BS_MCM_PLASC_ASC     (8U)          /*!< Bit field size in bits for MCM_PLASC_ASC. */
00162 
00163 /*! @brief Read current value of the MCM_PLASC_ASC field. */
00164 #define BR_MCM_PLASC_ASC(x)  (UNION_READ(hw_mcm_plasc_t, HW_MCM_PLASC_ADDR(x), U, B.ASC))
00165 /*@}*/
00166 
00167 /*******************************************************************************
00168  * HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
00169  ******************************************************************************/
00170 
00171 /*!
00172  * @brief HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration (RO)
00173  *
00174  * Reset value: 0x0037U
00175  *
00176  * PLAMC is a 16-bit read-only register identifying the presence/absence of bus
00177  * master connections to the device's crossbar switch.
00178  */
00179 typedef union _hw_mcm_plamc
00180 {
00181     uint16_t U;
00182     struct _hw_mcm_plamc_bitfields
00183     {
00184         uint16_t AMC : 8;              /*!< [7:0] Each bit in the AMC field indicates
00185                                         * whether there is a corresponding connection to the AXBS master input port. */
00186         uint16_t RESERVED0 : 8;        /*!< [15:8]  */
00187     } B;
00188 } hw_mcm_plamc_t;
00189 
00190 /*!
00191  * @name Constants and macros for entire MCM_PLAMC register
00192  */
00193 /*@{*/
00194 #define HW_MCM_PLAMC_ADDR(x)     ((x) + 0xAU)
00195 
00196 #define HW_MCM_PLAMC(x)          (*(__I hw_mcm_plamc_t *) HW_MCM_PLAMC_ADDR(x))
00197 #define HW_MCM_PLAMC_RD(x)       (ADDRESS_READ(hw_mcm_plamc_t, HW_MCM_PLAMC_ADDR(x)))
00198 /*@}*/
00199 
00200 /*
00201  * Constants & macros for individual MCM_PLAMC bitfields
00202  */
00203 
00204 /*!
00205  * @name Register MCM_PLAMC, field AMC[7:0] (RO)
00206  *
00207  * Values:
00208  * - 0 - A bus master connection to AXBS input port n is absent
00209  * - 1 - A bus master connection to AXBS input port n is present
00210  */
00211 /*@{*/
00212 #define BP_MCM_PLAMC_AMC     (0U)          /*!< Bit position for MCM_PLAMC_AMC. */
00213 #define BM_MCM_PLAMC_AMC     (0x00FFU)     /*!< Bit mask for MCM_PLAMC_AMC. */
00214 #define BS_MCM_PLAMC_AMC     (8U)          /*!< Bit field size in bits for MCM_PLAMC_AMC. */
00215 
00216 /*! @brief Read current value of the MCM_PLAMC_AMC field. */
00217 #define BR_MCM_PLAMC_AMC(x)  (UNION_READ(hw_mcm_plamc_t, HW_MCM_PLAMC_ADDR(x), U, B.AMC))
00218 /*@}*/
00219 
00220 /*******************************************************************************
00221  * HW_MCM_CR - Control Register
00222  ******************************************************************************/
00223 
00224 /*!
00225  * @brief HW_MCM_CR - Control Register (RW)
00226  *
00227  * Reset value: 0x00000000U
00228  *
00229  * CR defines the arbitration and protection schemes for the two system RAM
00230  * arrays.
00231  */
00232 typedef union _hw_mcm_cr
00233 {
00234     uint32_t U;
00235     struct _hw_mcm_cr_bitfields
00236     {
00237         uint32_t RESERVED0 : 24;       /*!< [23:0]  */
00238         uint32_t SRAMUAP : 2;          /*!< [25:24] SRAM_U arbitration priority */
00239         uint32_t SRAMUWP : 1;          /*!< [26] SRAM_U write protect */
00240         uint32_t RESERVED1 : 1;        /*!< [27]  */
00241         uint32_t SRAMLAP : 2;          /*!< [29:28] SRAM_L arbitration priority */
00242         uint32_t SRAMLWP : 1;          /*!< [30] SRAM_L Write Protect */
00243         uint32_t RESERVED2 : 1;        /*!< [31]  */
00244     } B;
00245 } hw_mcm_cr_t;
00246 
00247 /*!
00248  * @name Constants and macros for entire MCM_CR register
00249  */
00250 /*@{*/
00251 #define HW_MCM_CR_ADDR(x)        ((x) + 0xCU)
00252 
00253 #define HW_MCM_CR(x)             (*(__IO hw_mcm_cr_t *) HW_MCM_CR_ADDR(x))
00254 #define HW_MCM_CR_RD(x)          (ADDRESS_READ(hw_mcm_cr_t, HW_MCM_CR_ADDR(x)))
00255 #define HW_MCM_CR_WR(x, v)       (ADDRESS_WRITE(hw_mcm_cr_t, HW_MCM_CR_ADDR(x), v))
00256 #define HW_MCM_CR_SET(x, v)      (HW_MCM_CR_WR(x, HW_MCM_CR_RD(x) |  (v)))
00257 #define HW_MCM_CR_CLR(x, v)      (HW_MCM_CR_WR(x, HW_MCM_CR_RD(x) & ~(v)))
00258 #define HW_MCM_CR_TOG(x, v)      (HW_MCM_CR_WR(x, HW_MCM_CR_RD(x) ^  (v)))
00259 /*@}*/
00260 
00261 /*
00262  * Constants & macros for individual MCM_CR bitfields
00263  */
00264 
00265 /*!
00266  * @name Register MCM_CR, field SRAMUAP[25:24] (RW)
00267  *
00268  * Defines the arbitration scheme and priority for the processor and SRAM
00269  * backdoor accesses to the SRAM_U array.
00270  *
00271  * Values:
00272  * - 00 - Round robin
00273  * - 01 - Special round robin (favors SRAM backoor accesses over the processor)
00274  * - 10 - Fixed priority. Processor has highest, backdoor has lowest
00275  * - 11 - Fixed priority. Backdoor has highest, processor has lowest
00276  */
00277 /*@{*/
00278 #define BP_MCM_CR_SRAMUAP    (24U)         /*!< Bit position for MCM_CR_SRAMUAP. */
00279 #define BM_MCM_CR_SRAMUAP    (0x03000000U) /*!< Bit mask for MCM_CR_SRAMUAP. */
00280 #define BS_MCM_CR_SRAMUAP    (2U)          /*!< Bit field size in bits for MCM_CR_SRAMUAP. */
00281 
00282 /*! @brief Read current value of the MCM_CR_SRAMUAP field. */
00283 #define BR_MCM_CR_SRAMUAP(x) (UNION_READ(hw_mcm_cr_t, HW_MCM_CR_ADDR(x), U, B.SRAMUAP))
00284 
00285 /*! @brief Format value for bitfield MCM_CR_SRAMUAP. */
00286 #define BF_MCM_CR_SRAMUAP(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CR_SRAMUAP) & BM_MCM_CR_SRAMUAP)
00287 
00288 /*! @brief Set the SRAMUAP field to a new value. */
00289 #define BW_MCM_CR_SRAMUAP(x, v) (HW_MCM_CR_WR(x, (HW_MCM_CR_RD(x) & ~BM_MCM_CR_SRAMUAP) | BF_MCM_CR_SRAMUAP(v)))
00290 /*@}*/
00291 
00292 /*!
00293  * @name Register MCM_CR, field SRAMUWP[26] (RW)
00294  *
00295  * When this bit is set, writes to SRAM_U array generates a bus error.
00296  */
00297 /*@{*/
00298 #define BP_MCM_CR_SRAMUWP    (26U)         /*!< Bit position for MCM_CR_SRAMUWP. */
00299 #define BM_MCM_CR_SRAMUWP    (0x04000000U) /*!< Bit mask for MCM_CR_SRAMUWP. */
00300 #define BS_MCM_CR_SRAMUWP    (1U)          /*!< Bit field size in bits for MCM_CR_SRAMUWP. */
00301 
00302 /*! @brief Read current value of the MCM_CR_SRAMUWP field. */
00303 #define BR_MCM_CR_SRAMUWP(x) (UNION_READ(hw_mcm_cr_t, HW_MCM_CR_ADDR(x), U, B.SRAMUWP))
00304 
00305 /*! @brief Format value for bitfield MCM_CR_SRAMUWP. */
00306 #define BF_MCM_CR_SRAMUWP(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CR_SRAMUWP) & BM_MCM_CR_SRAMUWP)
00307 
00308 /*! @brief Set the SRAMUWP field to a new value. */
00309 #define BW_MCM_CR_SRAMUWP(x, v) (HW_MCM_CR_WR(x, (HW_MCM_CR_RD(x) & ~BM_MCM_CR_SRAMUWP) | BF_MCM_CR_SRAMUWP(v)))
00310 /*@}*/
00311 
00312 /*!
00313  * @name Register MCM_CR, field SRAMLAP[29:28] (RW)
00314  *
00315  * Defines the arbitration scheme and priority for the processor and SRAM
00316  * backdoor accesses to the SRAM_L array.
00317  *
00318  * Values:
00319  * - 00 - Round robin
00320  * - 01 - Special round robin (favors SRAM backoor accesses over the processor)
00321  * - 10 - Fixed priority. Processor has highest, backdoor has lowest
00322  * - 11 - Fixed priority. Backdoor has highest, processor has lowest
00323  */
00324 /*@{*/
00325 #define BP_MCM_CR_SRAMLAP    (28U)         /*!< Bit position for MCM_CR_SRAMLAP. */
00326 #define BM_MCM_CR_SRAMLAP    (0x30000000U) /*!< Bit mask for MCM_CR_SRAMLAP. */
00327 #define BS_MCM_CR_SRAMLAP    (2U)          /*!< Bit field size in bits for MCM_CR_SRAMLAP. */
00328 
00329 /*! @brief Read current value of the MCM_CR_SRAMLAP field. */
00330 #define BR_MCM_CR_SRAMLAP(x) (UNION_READ(hw_mcm_cr_t, HW_MCM_CR_ADDR(x), U, B.SRAMLAP))
00331 
00332 /*! @brief Format value for bitfield MCM_CR_SRAMLAP. */
00333 #define BF_MCM_CR_SRAMLAP(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CR_SRAMLAP) & BM_MCM_CR_SRAMLAP)
00334 
00335 /*! @brief Set the SRAMLAP field to a new value. */
00336 #define BW_MCM_CR_SRAMLAP(x, v) (HW_MCM_CR_WR(x, (HW_MCM_CR_RD(x) & ~BM_MCM_CR_SRAMLAP) | BF_MCM_CR_SRAMLAP(v)))
00337 /*@}*/
00338 
00339 /*!
00340  * @name Register MCM_CR, field SRAMLWP[30] (RW)
00341  *
00342  * When this bit is set, writes to SRAM_L array generates a bus error.
00343  */
00344 /*@{*/
00345 #define BP_MCM_CR_SRAMLWP    (30U)         /*!< Bit position for MCM_CR_SRAMLWP. */
00346 #define BM_MCM_CR_SRAMLWP    (0x40000000U) /*!< Bit mask for MCM_CR_SRAMLWP. */
00347 #define BS_MCM_CR_SRAMLWP    (1U)          /*!< Bit field size in bits for MCM_CR_SRAMLWP. */
00348 
00349 /*! @brief Read current value of the MCM_CR_SRAMLWP field. */
00350 #define BR_MCM_CR_SRAMLWP(x) (UNION_READ(hw_mcm_cr_t, HW_MCM_CR_ADDR(x), U, B.SRAMLWP))
00351 
00352 /*! @brief Format value for bitfield MCM_CR_SRAMLWP. */
00353 #define BF_MCM_CR_SRAMLWP(v) ((uint32_t)((uint32_t)(v) << BP_MCM_CR_SRAMLWP) & BM_MCM_CR_SRAMLWP)
00354 
00355 /*! @brief Set the SRAMLWP field to a new value. */
00356 #define BW_MCM_CR_SRAMLWP(x, v) (HW_MCM_CR_WR(x, (HW_MCM_CR_RD(x) & ~BM_MCM_CR_SRAMLWP) | BF_MCM_CR_SRAMLWP(v)))
00357 /*@}*/
00358 
00359 /*******************************************************************************
00360  * HW_MCM_ISCR - Interrupt Status Register
00361  ******************************************************************************/
00362 
00363 /*!
00364  * @brief HW_MCM_ISCR - Interrupt Status Register (RW)
00365  *
00366  * Reset value: 0x00000000U
00367  */
00368 typedef union _hw_mcm_iscr
00369 {
00370     uint32_t U;
00371     struct _hw_mcm_iscr_bitfields
00372     {
00373         uint32_t RESERVED0 : 1;        /*!< [0]  */
00374         uint32_t IRQ : 1;              /*!< [1] Normal Interrupt Pending */
00375         uint32_t NMI : 1;              /*!< [2] Non-maskable Interrupt Pending */
00376         uint32_t DHREQ : 1;            /*!< [3] Debug Halt Request Indicator */
00377         uint32_t RESERVED1 : 4;        /*!< [7:4]  */
00378         uint32_t FIOC : 1;             /*!< [8] FPU invalid operation interrupt status */
00379         uint32_t FDZC : 1;             /*!< [9] FPU divide-by-zero interrupt status */
00380         uint32_t FOFC : 1;             /*!< [10] FPU overflow interrupt status */
00381         uint32_t FUFC : 1;             /*!< [11] FPU underflow interrupt status */
00382         uint32_t FIXC : 1;             /*!< [12] FPU inexact interrupt status */
00383         uint32_t RESERVED2 : 2;        /*!< [14:13]  */
00384         uint32_t FIDC : 1;             /*!< [15] FPU input denormal interrupt status */
00385         uint32_t RESERVED3 : 8;        /*!< [23:16]  */
00386         uint32_t FIOCE : 1;            /*!< [24] FPU invalid operation interrupt enable
00387                                         * */
00388         uint32_t FDZCE : 1;            /*!< [25] FPU divide-by-zero interrupt enable */
00389         uint32_t FOFCE : 1;            /*!< [26] FPU overflow interrupt enable */
00390         uint32_t FUFCE : 1;            /*!< [27] FPU underflow interrupt enable */
00391         uint32_t FIXCE : 1;            /*!< [28] FPU inexact interrupt enable */
00392         uint32_t RESERVED4 : 2;        /*!< [30:29]  */
00393         uint32_t FIDCE : 1;            /*!< [31] FPU input denormal interrupt enable */
00394     } B;
00395 } hw_mcm_iscr_t;
00396 
00397 /*!
00398  * @name Constants and macros for entire MCM_ISCR register
00399  */
00400 /*@{*/
00401 #define HW_MCM_ISCR_ADDR(x)      ((x) + 0x10U)
00402 
00403 #define HW_MCM_ISCR(x)           (*(__IO hw_mcm_iscr_t *) HW_MCM_ISCR_ADDR(x))
00404 #define HW_MCM_ISCR_RD(x)        (ADDRESS_READ(hw_mcm_iscr_t, HW_MCM_ISCR_ADDR(x)))
00405 #define HW_MCM_ISCR_WR(x, v)     (ADDRESS_WRITE(hw_mcm_iscr_t, HW_MCM_ISCR_ADDR(x), v))
00406 #define HW_MCM_ISCR_SET(x, v)    (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) |  (v)))
00407 #define HW_MCM_ISCR_CLR(x, v)    (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) & ~(v)))
00408 #define HW_MCM_ISCR_TOG(x, v)    (HW_MCM_ISCR_WR(x, HW_MCM_ISCR_RD(x) ^  (v)))
00409 /*@}*/
00410 
00411 /*
00412  * Constants & macros for individual MCM_ISCR bitfields
00413  */
00414 
00415 /*!
00416  * @name Register MCM_ISCR, field IRQ[1] (W1C)
00417  *
00418  * If ETBCC[RSPT] is set to 01b, this bit is set when the ETB counter expires.
00419  *
00420  * Values:
00421  * - 0 - No pending interrupt
00422  * - 1 - Due to the ETB counter expiring, a normal interrupt is pending
00423  */
00424 /*@{*/
00425 #define BP_MCM_ISCR_IRQ      (1U)          /*!< Bit position for MCM_ISCR_IRQ. */
00426 #define BM_MCM_ISCR_IRQ      (0x00000002U) /*!< Bit mask for MCM_ISCR_IRQ. */
00427 #define BS_MCM_ISCR_IRQ      (1U)          /*!< Bit field size in bits for MCM_ISCR_IRQ. */
00428 
00429 /*! @brief Read current value of the MCM_ISCR_IRQ field. */
00430 #define BR_MCM_ISCR_IRQ(x)   (UNION_READ(hw_mcm_iscr_t, HW_MCM_ISCR_ADDR(x), U, B.IRQ))
00431 
00432 /*! @brief Format value for bitfield MCM_ISCR_IRQ. */
00433 #define BF_MCM_ISCR_IRQ(v)   ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_IRQ) & BM_MCM_ISCR_IRQ)
00434 
00435 /*! @brief Set the IRQ field to a new value. */
00436 #define BW_MCM_ISCR_IRQ(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_IRQ) | BF_MCM_ISCR_IRQ(v)))
00437 /*@}*/
00438 
00439 /*!
00440  * @name Register MCM_ISCR, field NMI[2] (W1C)
00441  *
00442  * If ETBCC[RSPT] is set to 10b, this bit is set when the ETB counter expires.
00443  *
00444  * Values:
00445  * - 0 - No pending NMI
00446  * - 1 - Due to the ETB counter expiring, an NMI is pending
00447  */
00448 /*@{*/
00449 #define BP_MCM_ISCR_NMI      (2U)          /*!< Bit position for MCM_ISCR_NMI. */
00450 #define BM_MCM_ISCR_NMI      (0x00000004U) /*!< Bit mask for MCM_ISCR_NMI. */
00451 #define BS_MCM_ISCR_NMI      (1U)          /*!< Bit field size in bits for MCM_ISCR_NMI. */
00452 
00453 /*! @brief Read current value of the MCM_ISCR_NMI field. */
00454 #define BR_MCM_ISCR_NMI(x)   (UNION_READ(hw_mcm_iscr_t, HW_MCM_ISCR_ADDR(x), U, B.NMI))
00455 
00456 /*! @brief Format value for bitfield MCM_ISCR_NMI. */
00457 #define BF_MCM_ISCR_NMI(v)   ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_NMI) & BM_MCM_ISCR_NMI)
00458 
00459 /*! @brief Set the NMI field to a new value. */
00460 #define BW_MCM_ISCR_NMI(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_NMI) | BF_MCM_ISCR_NMI(v)))
00461 /*@}*/
00462 
00463 /*!
00464  * @name Register MCM_ISCR, field DHREQ[3] (RO)
00465  *
00466  * Indicates that a debug halt request is initiated due to a ETB counter
00467  * expiration, ETBCC[2:0] = 3b111 & ETBCV[10:0] = 11h0. This bit is cleared when the
00468  * counter is disabled or when the ETB counter is reloaded.
00469  *
00470  * Values:
00471  * - 0 - No debug halt request
00472  * - 1 - Debug halt request initiated
00473  */
00474 /*@{*/
00475 #define BP_MCM_ISCR_DHREQ    (3U)          /*!< Bit position for MCM_ISCR_DHREQ. */
00476 #define BM_MCM_ISCR_DHREQ    (0x00000008U) /*!< Bit mask for MCM_ISCR_DHREQ. */
00477 #define BS_MCM_ISCR_DHREQ    (1U)          /*!< Bit field size in bits for MCM_ISCR_DHREQ. */
00478 
00479 /*! @brief Read current value of the MCM_ISCR_DHREQ field. */
00480 #define BR_MCM_ISCR_DHREQ(x) (UNION_READ(hw_mcm_iscr_t, HW_MCM_ISCR_ADDR(x), U, B.DHREQ))
00481 /*@}*/
00482 
00483 /*!
00484  * @name Register MCM_ISCR, field FIOC[8] (RO)
00485  *
00486  * This read-only bit is a copy of the core's FPSCR[IOC] bit and signals an
00487  * illegal operation has been detected in the processor's FPU. Once set, this bit
00488  * remains set until software clears the FPSCR[IOC] bit.
00489  *
00490  * Values:
00491  * - 0 - No interrupt
00492  * - 1 - Interrupt occurred
00493  */
00494 /*@{*/
00495 #define BP_MCM_ISCR_FIOC     (8U)          /*!< Bit position for MCM_ISCR_FIOC. */
00496 #define BM_MCM_ISCR_FIOC     (0x00000100U) /*!< Bit mask for MCM_ISCR_FIOC. */
00497 #define BS_MCM_ISCR_FIOC     (1U)          /*!< Bit field size in bits for MCM_ISCR_FIOC. */
00498 
00499 /*! @brief Read current value of the MCM_ISCR_FIOC field. */
00500 #define BR_MCM_ISCR_FIOC(x)  (UNION_READ(hw_mcm_iscr_t, HW_MCM_ISCR_ADDR(x), U, B.FIOC))
00501 /*@}*/
00502 
00503 /*!
00504  * @name Register MCM_ISCR, field FDZC[9] (RO)
00505  *
00506  * This read-only bit is a copy of the core's FPSCR[DZC] bit and signals a
00507  * divide by zero has been detected in the processor's FPU. Once set, this bit remains
00508  * set until software clears the FPSCR[DZC] bit.
00509  *
00510  * Values:
00511  * - 0 - No interrupt
00512  * - 1 - Interrupt occurred
00513  */
00514 /*@{*/
00515 #define BP_MCM_ISCR_FDZC     (9U)          /*!< Bit position for MCM_ISCR_FDZC. */
00516 #define BM_MCM_ISCR_FDZC     (0x00000200U) /*!< Bit mask for MCM_ISCR_FDZC. */
00517 #define BS_MCM_ISCR_FDZC     (1U)          /*!< Bit field size in bits for MCM_ISCR_FDZC. */
00518 
00519 /*! @brief Read current value of the MCM_ISCR_FDZC field. */
00520 #define BR_MCM_ISCR_FDZC(x)  (UNION_READ(hw_mcm_iscr_t, HW_MCM_ISCR_ADDR(x), U, B.FDZC))
00521 /*@}*/
00522 
00523 /*!
00524  * @name Register MCM_ISCR, field FOFC[10] (RO)
00525  *
00526  * This read-only bit is a copy of the core's FPSCR[OFC] bit and signals an
00527  * overflow has been detected in the processor's FPU. Once set, this bit remains set
00528  * until software clears the FPSCR[OFC] bit.
00529  *
00530  * Values:
00531  * - 0 - No interrupt
00532  * - 1 - Interrupt occurred
00533  */
00534 /*@{*/
00535 #define BP_MCM_ISCR_FOFC     (10U)         /*!< Bit position for MCM_ISCR_FOFC. */
00536 #define BM_MCM_ISCR_FOFC     (0x00000400U) /*!< Bit mask for MCM_ISCR_FOFC. */
00537 #define BS_MCM_ISCR_FOFC     (1U)          /*!< Bit field size in bits for MCM_ISCR_FOFC. */
00538 
00539 /*! @brief Read current value of the MCM_ISCR_FOFC field. */
00540 #define BR_MCM_ISCR_FOFC(x)  (UNION_READ(hw_mcm_iscr_t, HW_MCM_ISCR_ADDR(x), U, B.FOFC))
00541 /*@}*/
00542 
00543 /*!
00544  * @name Register MCM_ISCR, field FUFC[11] (RO)
00545  *
00546  * This read-only bit is a copy of the core's FPSCR[UFC] bit and signals an
00547  * underflow has been detected in the processor's FPU. Once set, this bit remains set
00548  * until software clears the FPSCR[UFC] bit.
00549  *
00550  * Values:
00551  * - 0 - No interrupt
00552  * - 1 - Interrupt occurred
00553  */
00554 /*@{*/
00555 #define BP_MCM_ISCR_FUFC     (11U)         /*!< Bit position for MCM_ISCR_FUFC. */
00556 #define BM_MCM_ISCR_FUFC     (0x00000800U) /*!< Bit mask for MCM_ISCR_FUFC. */
00557 #define BS_MCM_ISCR_FUFC     (1U)          /*!< Bit field size in bits for MCM_ISCR_FUFC. */
00558 
00559 /*! @brief Read current value of the MCM_ISCR_FUFC field. */
00560 #define BR_MCM_ISCR_FUFC(x)  (UNION_READ(hw_mcm_iscr_t, HW_MCM_ISCR_ADDR(x), U, B.FUFC))
00561 /*@}*/
00562 
00563 /*!
00564  * @name Register MCM_ISCR, field FIXC[12] (RO)
00565  *
00566  * This read-only bit is a copy of the core's FPSCR[IXC] bit and signals an
00567  * inexact number has been detected in the processor's FPU. Once set, this bit
00568  * remains set until software clears the FPSCR[IXC] bit.
00569  *
00570  * Values:
00571  * - 0 - No interrupt
00572  * - 1 - Interrupt occurred
00573  */
00574 /*@{*/
00575 #define BP_MCM_ISCR_FIXC     (12U)         /*!< Bit position for MCM_ISCR_FIXC. */
00576 #define BM_MCM_ISCR_FIXC     (0x00001000U) /*!< Bit mask for MCM_ISCR_FIXC. */
00577 #define BS_MCM_ISCR_FIXC     (1U)          /*!< Bit field size in bits for MCM_ISCR_FIXC. */
00578 
00579 /*! @brief Read current value of the MCM_ISCR_FIXC field. */
00580 #define BR_MCM_ISCR_FIXC(x)  (UNION_READ(hw_mcm_iscr_t, HW_MCM_ISCR_ADDR(x), U, B.FIXC))
00581 /*@}*/
00582 
00583 /*!
00584  * @name Register MCM_ISCR, field FIDC[15] (RO)
00585  *
00586  * This read-only bit is a copy of the core's FPSCR[IDC] bit and signals input
00587  * denormalized number has been detected in the processor's FPU. Once set, this
00588  * bit remains set until software clears the FPSCR[IDC] bit.
00589  *
00590  * Values:
00591  * - 0 - No interrupt
00592  * - 1 - Interrupt occurred
00593  */
00594 /*@{*/
00595 #define BP_MCM_ISCR_FIDC     (15U)         /*!< Bit position for MCM_ISCR_FIDC. */
00596 #define BM_MCM_ISCR_FIDC     (0x00008000U) /*!< Bit mask for MCM_ISCR_FIDC. */
00597 #define BS_MCM_ISCR_FIDC     (1U)          /*!< Bit field size in bits for MCM_ISCR_FIDC. */
00598 
00599 /*! @brief Read current value of the MCM_ISCR_FIDC field. */
00600 #define BR_MCM_ISCR_FIDC(x)  (UNION_READ(hw_mcm_iscr_t, HW_MCM_ISCR_ADDR(x), U, B.FIDC))
00601 /*@}*/
00602 
00603 /*!
00604  * @name Register MCM_ISCR, field FIOCE[24] (RW)
00605  *
00606  * Values:
00607  * - 0 - Disable interrupt
00608  * - 1 - Enable interrupt
00609  */
00610 /*@{*/
00611 #define BP_MCM_ISCR_FIOCE    (24U)         /*!< Bit position for MCM_ISCR_FIOCE. */
00612 #define BM_MCM_ISCR_FIOCE    (0x01000000U) /*!< Bit mask for MCM_ISCR_FIOCE. */
00613 #define BS_MCM_ISCR_FIOCE    (1U)          /*!< Bit field size in bits for MCM_ISCR_FIOCE. */
00614 
00615 /*! @brief Read current value of the MCM_ISCR_FIOCE field. */
00616 #define BR_MCM_ISCR_FIOCE(x) (UNION_READ(hw_mcm_iscr_t, HW_MCM_ISCR_ADDR(x), U, B.FIOCE))
00617 
00618 /*! @brief Format value for bitfield MCM_ISCR_FIOCE. */
00619 #define BF_MCM_ISCR_FIOCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIOCE) & BM_MCM_ISCR_FIOCE)
00620 
00621 /*! @brief Set the FIOCE field to a new value. */
00622 #define BW_MCM_ISCR_FIOCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIOCE) | BF_MCM_ISCR_FIOCE(v)))
00623 /*@}*/
00624 
00625 /*!
00626  * @name Register MCM_ISCR, field FDZCE[25] (RW)
00627  *
00628  * Values:
00629  * - 0 - Disable interrupt
00630  * - 1 - Enable interrupt
00631  */
00632 /*@{*/
00633 #define BP_MCM_ISCR_FDZCE    (25U)         /*!< Bit position for MCM_ISCR_FDZCE. */
00634 #define BM_MCM_ISCR_FDZCE    (0x02000000U) /*!< Bit mask for MCM_ISCR_FDZCE. */
00635 #define BS_MCM_ISCR_FDZCE    (1U)          /*!< Bit field size in bits for MCM_ISCR_FDZCE. */
00636 
00637 /*! @brief Read current value of the MCM_ISCR_FDZCE field. */
00638 #define BR_MCM_ISCR_FDZCE(x) (UNION_READ(hw_mcm_iscr_t, HW_MCM_ISCR_ADDR(x), U, B.FDZCE))
00639 
00640 /*! @brief Format value for bitfield MCM_ISCR_FDZCE. */
00641 #define BF_MCM_ISCR_FDZCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FDZCE) & BM_MCM_ISCR_FDZCE)
00642 
00643 /*! @brief Set the FDZCE field to a new value. */
00644 #define BW_MCM_ISCR_FDZCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FDZCE) | BF_MCM_ISCR_FDZCE(v)))
00645 /*@}*/
00646 
00647 /*!
00648  * @name Register MCM_ISCR, field FOFCE[26] (RW)
00649  *
00650  * Values:
00651  * - 0 - Disable interrupt
00652  * - 1 - Enable interrupt
00653  */
00654 /*@{*/
00655 #define BP_MCM_ISCR_FOFCE    (26U)         /*!< Bit position for MCM_ISCR_FOFCE. */
00656 #define BM_MCM_ISCR_FOFCE    (0x04000000U) /*!< Bit mask for MCM_ISCR_FOFCE. */
00657 #define BS_MCM_ISCR_FOFCE    (1U)          /*!< Bit field size in bits for MCM_ISCR_FOFCE. */
00658 
00659 /*! @brief Read current value of the MCM_ISCR_FOFCE field. */
00660 #define BR_MCM_ISCR_FOFCE(x) (UNION_READ(hw_mcm_iscr_t, HW_MCM_ISCR_ADDR(x), U, B.FOFCE))
00661 
00662 /*! @brief Format value for bitfield MCM_ISCR_FOFCE. */
00663 #define BF_MCM_ISCR_FOFCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FOFCE) & BM_MCM_ISCR_FOFCE)
00664 
00665 /*! @brief Set the FOFCE field to a new value. */
00666 #define BW_MCM_ISCR_FOFCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FOFCE) | BF_MCM_ISCR_FOFCE(v)))
00667 /*@}*/
00668 
00669 /*!
00670  * @name Register MCM_ISCR, field FUFCE[27] (RW)
00671  *
00672  * Values:
00673  * - 0 - Disable interrupt
00674  * - 1 - Enable interrupt
00675  */
00676 /*@{*/
00677 #define BP_MCM_ISCR_FUFCE    (27U)         /*!< Bit position for MCM_ISCR_FUFCE. */
00678 #define BM_MCM_ISCR_FUFCE    (0x08000000U) /*!< Bit mask for MCM_ISCR_FUFCE. */
00679 #define BS_MCM_ISCR_FUFCE    (1U)          /*!< Bit field size in bits for MCM_ISCR_FUFCE. */
00680 
00681 /*! @brief Read current value of the MCM_ISCR_FUFCE field. */
00682 #define BR_MCM_ISCR_FUFCE(x) (UNION_READ(hw_mcm_iscr_t, HW_MCM_ISCR_ADDR(x), U, B.FUFCE))
00683 
00684 /*! @brief Format value for bitfield MCM_ISCR_FUFCE. */
00685 #define BF_MCM_ISCR_FUFCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FUFCE) & BM_MCM_ISCR_FUFCE)
00686 
00687 /*! @brief Set the FUFCE field to a new value. */
00688 #define BW_MCM_ISCR_FUFCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FUFCE) | BF_MCM_ISCR_FUFCE(v)))
00689 /*@}*/
00690 
00691 /*!
00692  * @name Register MCM_ISCR, field FIXCE[28] (RW)
00693  *
00694  * Values:
00695  * - 0 - Disable interrupt
00696  * - 1 - Enable interrupt
00697  */
00698 /*@{*/
00699 #define BP_MCM_ISCR_FIXCE    (28U)         /*!< Bit position for MCM_ISCR_FIXCE. */
00700 #define BM_MCM_ISCR_FIXCE    (0x10000000U) /*!< Bit mask for MCM_ISCR_FIXCE. */
00701 #define BS_MCM_ISCR_FIXCE    (1U)          /*!< Bit field size in bits for MCM_ISCR_FIXCE. */
00702 
00703 /*! @brief Read current value of the MCM_ISCR_FIXCE field. */
00704 #define BR_MCM_ISCR_FIXCE(x) (UNION_READ(hw_mcm_iscr_t, HW_MCM_ISCR_ADDR(x), U, B.FIXCE))
00705 
00706 /*! @brief Format value for bitfield MCM_ISCR_FIXCE. */
00707 #define BF_MCM_ISCR_FIXCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIXCE) & BM_MCM_ISCR_FIXCE)
00708 
00709 /*! @brief Set the FIXCE field to a new value. */
00710 #define BW_MCM_ISCR_FIXCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIXCE) | BF_MCM_ISCR_FIXCE(v)))
00711 /*@}*/
00712 
00713 /*!
00714  * @name Register MCM_ISCR, field FIDCE[31] (RW)
00715  *
00716  * Values:
00717  * - 0 - Disable interrupt
00718  * - 1 - Enable interrupt
00719  */
00720 /*@{*/
00721 #define BP_MCM_ISCR_FIDCE    (31U)         /*!< Bit position for MCM_ISCR_FIDCE. */
00722 #define BM_MCM_ISCR_FIDCE    (0x80000000U) /*!< Bit mask for MCM_ISCR_FIDCE. */
00723 #define BS_MCM_ISCR_FIDCE    (1U)          /*!< Bit field size in bits for MCM_ISCR_FIDCE. */
00724 
00725 /*! @brief Read current value of the MCM_ISCR_FIDCE field. */
00726 #define BR_MCM_ISCR_FIDCE(x) (UNION_READ(hw_mcm_iscr_t, HW_MCM_ISCR_ADDR(x), U, B.FIDCE))
00727 
00728 /*! @brief Format value for bitfield MCM_ISCR_FIDCE. */
00729 #define BF_MCM_ISCR_FIDCE(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ISCR_FIDCE) & BM_MCM_ISCR_FIDCE)
00730 
00731 /*! @brief Set the FIDCE field to a new value. */
00732 #define BW_MCM_ISCR_FIDCE(x, v) (HW_MCM_ISCR_WR(x, (HW_MCM_ISCR_RD(x) & ~BM_MCM_ISCR_FIDCE) | BF_MCM_ISCR_FIDCE(v)))
00733 /*@}*/
00734 
00735 /*******************************************************************************
00736  * HW_MCM_ETBCC - ETB Counter Control register
00737  ******************************************************************************/
00738 
00739 /*!
00740  * @brief HW_MCM_ETBCC - ETB Counter Control register (RW)
00741  *
00742  * Reset value: 0x00000000U
00743  */
00744 typedef union _hw_mcm_etbcc
00745 {
00746     uint32_t U;
00747     struct _hw_mcm_etbcc_bitfields
00748     {
00749         uint32_t CNTEN : 1;            /*!< [0] Counter Enable */
00750         uint32_t RSPT : 2;             /*!< [2:1] Response Type */
00751         uint32_t RLRQ : 1;             /*!< [3] Reload Request */
00752         uint32_t ETDIS : 1;            /*!< [4] ETM-To-TPIU Disable */
00753         uint32_t ITDIS : 1;            /*!< [5] ITM-To-TPIU Disable */
00754         uint32_t RESERVED0 : 26;       /*!< [31:6]  */
00755     } B;
00756 } hw_mcm_etbcc_t;
00757 
00758 /*!
00759  * @name Constants and macros for entire MCM_ETBCC register
00760  */
00761 /*@{*/
00762 #define HW_MCM_ETBCC_ADDR(x)     ((x) + 0x14U)
00763 
00764 #define HW_MCM_ETBCC(x)          (*(__IO hw_mcm_etbcc_t *) HW_MCM_ETBCC_ADDR(x))
00765 #define HW_MCM_ETBCC_RD(x)       (ADDRESS_READ(hw_mcm_etbcc_t, HW_MCM_ETBCC_ADDR(x)))
00766 #define HW_MCM_ETBCC_WR(x, v)    (ADDRESS_WRITE(hw_mcm_etbcc_t, HW_MCM_ETBCC_ADDR(x), v))
00767 #define HW_MCM_ETBCC_SET(x, v)   (HW_MCM_ETBCC_WR(x, HW_MCM_ETBCC_RD(x) |  (v)))
00768 #define HW_MCM_ETBCC_CLR(x, v)   (HW_MCM_ETBCC_WR(x, HW_MCM_ETBCC_RD(x) & ~(v)))
00769 #define HW_MCM_ETBCC_TOG(x, v)   (HW_MCM_ETBCC_WR(x, HW_MCM_ETBCC_RD(x) ^  (v)))
00770 /*@}*/
00771 
00772 /*
00773  * Constants & macros for individual MCM_ETBCC bitfields
00774  */
00775 
00776 /*!
00777  * @name Register MCM_ETBCC, field CNTEN[0] (RW)
00778  *
00779  * Enables the ETB counter.
00780  *
00781  * Values:
00782  * - 0 - ETB counter disabled
00783  * - 1 - ETB counter enabled
00784  */
00785 /*@{*/
00786 #define BP_MCM_ETBCC_CNTEN   (0U)          /*!< Bit position for MCM_ETBCC_CNTEN. */
00787 #define BM_MCM_ETBCC_CNTEN   (0x00000001U) /*!< Bit mask for MCM_ETBCC_CNTEN. */
00788 #define BS_MCM_ETBCC_CNTEN   (1U)          /*!< Bit field size in bits for MCM_ETBCC_CNTEN. */
00789 
00790 /*! @brief Read current value of the MCM_ETBCC_CNTEN field. */
00791 #define BR_MCM_ETBCC_CNTEN(x) (UNION_READ(hw_mcm_etbcc_t, HW_MCM_ETBCC_ADDR(x), U, B.CNTEN))
00792 
00793 /*! @brief Format value for bitfield MCM_ETBCC_CNTEN. */
00794 #define BF_MCM_ETBCC_CNTEN(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBCC_CNTEN) & BM_MCM_ETBCC_CNTEN)
00795 
00796 /*! @brief Set the CNTEN field to a new value. */
00797 #define BW_MCM_ETBCC_CNTEN(x, v) (HW_MCM_ETBCC_WR(x, (HW_MCM_ETBCC_RD(x) & ~BM_MCM_ETBCC_CNTEN) | BF_MCM_ETBCC_CNTEN(v)))
00798 /*@}*/
00799 
00800 /*!
00801  * @name Register MCM_ETBCC, field RSPT[2:1] (RW)
00802  *
00803  * Values:
00804  * - 00 - No response when the ETB count expires
00805  * - 01 - Generate a normal interrupt when the ETB count expires
00806  * - 10 - Generate an NMI when the ETB count expires
00807  * - 11 - Generate a debug halt when the ETB count expires
00808  */
00809 /*@{*/
00810 #define BP_MCM_ETBCC_RSPT    (1U)          /*!< Bit position for MCM_ETBCC_RSPT. */
00811 #define BM_MCM_ETBCC_RSPT    (0x00000006U) /*!< Bit mask for MCM_ETBCC_RSPT. */
00812 #define BS_MCM_ETBCC_RSPT    (2U)          /*!< Bit field size in bits for MCM_ETBCC_RSPT. */
00813 
00814 /*! @brief Read current value of the MCM_ETBCC_RSPT field. */
00815 #define BR_MCM_ETBCC_RSPT(x) (UNION_READ(hw_mcm_etbcc_t, HW_MCM_ETBCC_ADDR(x), U, B.RSPT))
00816 
00817 /*! @brief Format value for bitfield MCM_ETBCC_RSPT. */
00818 #define BF_MCM_ETBCC_RSPT(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBCC_RSPT) & BM_MCM_ETBCC_RSPT)
00819 
00820 /*! @brief Set the RSPT field to a new value. */
00821 #define BW_MCM_ETBCC_RSPT(x, v) (HW_MCM_ETBCC_WR(x, (HW_MCM_ETBCC_RD(x) & ~BM_MCM_ETBCC_RSPT) | BF_MCM_ETBCC_RSPT(v)))
00822 /*@}*/
00823 
00824 /*!
00825  * @name Register MCM_ETBCC, field RLRQ[3] (RW)
00826  *
00827  * Reloads the ETB packet counter with the MCM_ETBRL RELOAD value. If IRQ or NMI
00828  * interrupts were enabled and an NMI or IRQ interrupt was generated on counter
00829  * expiration, setting this bit clears the pending NMI or IRQ interrupt request.
00830  * If debug halt was enabled and a debug halt request was asserted on counter
00831  * expiration, setting this bit clears the debug halt request.
00832  *
00833  * Values:
00834  * - 0 - No effect
00835  * - 1 - Clears pending debug halt, NMI, or IRQ interrupt requests
00836  */
00837 /*@{*/
00838 #define BP_MCM_ETBCC_RLRQ    (3U)          /*!< Bit position for MCM_ETBCC_RLRQ. */
00839 #define BM_MCM_ETBCC_RLRQ    (0x00000008U) /*!< Bit mask for MCM_ETBCC_RLRQ. */
00840 #define BS_MCM_ETBCC_RLRQ    (1U)          /*!< Bit field size in bits for MCM_ETBCC_RLRQ. */
00841 
00842 /*! @brief Read current value of the MCM_ETBCC_RLRQ field. */
00843 #define BR_MCM_ETBCC_RLRQ(x) (UNION_READ(hw_mcm_etbcc_t, HW_MCM_ETBCC_ADDR(x), U, B.RLRQ))
00844 
00845 /*! @brief Format value for bitfield MCM_ETBCC_RLRQ. */
00846 #define BF_MCM_ETBCC_RLRQ(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBCC_RLRQ) & BM_MCM_ETBCC_RLRQ)
00847 
00848 /*! @brief Set the RLRQ field to a new value. */
00849 #define BW_MCM_ETBCC_RLRQ(x, v) (HW_MCM_ETBCC_WR(x, (HW_MCM_ETBCC_RD(x) & ~BM_MCM_ETBCC_RLRQ) | BF_MCM_ETBCC_RLRQ(v)))
00850 /*@}*/
00851 
00852 /*!
00853  * @name Register MCM_ETBCC, field ETDIS[4] (RW)
00854  *
00855  * Disables the trace path from ETM to TPIU.
00856  *
00857  * Values:
00858  * - 0 - ETM-to-TPIU trace path enabled
00859  * - 1 - ETM-to-TPIU trace path disabled
00860  */
00861 /*@{*/
00862 #define BP_MCM_ETBCC_ETDIS   (4U)          /*!< Bit position for MCM_ETBCC_ETDIS. */
00863 #define BM_MCM_ETBCC_ETDIS   (0x00000010U) /*!< Bit mask for MCM_ETBCC_ETDIS. */
00864 #define BS_MCM_ETBCC_ETDIS   (1U)          /*!< Bit field size in bits for MCM_ETBCC_ETDIS. */
00865 
00866 /*! @brief Read current value of the MCM_ETBCC_ETDIS field. */
00867 #define BR_MCM_ETBCC_ETDIS(x) (UNION_READ(hw_mcm_etbcc_t, HW_MCM_ETBCC_ADDR(x), U, B.ETDIS))
00868 
00869 /*! @brief Format value for bitfield MCM_ETBCC_ETDIS. */
00870 #define BF_MCM_ETBCC_ETDIS(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBCC_ETDIS) & BM_MCM_ETBCC_ETDIS)
00871 
00872 /*! @brief Set the ETDIS field to a new value. */
00873 #define BW_MCM_ETBCC_ETDIS(x, v) (HW_MCM_ETBCC_WR(x, (HW_MCM_ETBCC_RD(x) & ~BM_MCM_ETBCC_ETDIS) | BF_MCM_ETBCC_ETDIS(v)))
00874 /*@}*/
00875 
00876 /*!
00877  * @name Register MCM_ETBCC, field ITDIS[5] (RW)
00878  *
00879  * Disables the trace path from ITM to TPIU.
00880  *
00881  * Values:
00882  * - 0 - ITM-to-TPIU trace path enabled
00883  * - 1 - ITM-to-TPIU trace path disabled
00884  */
00885 /*@{*/
00886 #define BP_MCM_ETBCC_ITDIS   (5U)          /*!< Bit position for MCM_ETBCC_ITDIS. */
00887 #define BM_MCM_ETBCC_ITDIS   (0x00000020U) /*!< Bit mask for MCM_ETBCC_ITDIS. */
00888 #define BS_MCM_ETBCC_ITDIS   (1U)          /*!< Bit field size in bits for MCM_ETBCC_ITDIS. */
00889 
00890 /*! @brief Read current value of the MCM_ETBCC_ITDIS field. */
00891 #define BR_MCM_ETBCC_ITDIS(x) (UNION_READ(hw_mcm_etbcc_t, HW_MCM_ETBCC_ADDR(x), U, B.ITDIS))
00892 
00893 /*! @brief Format value for bitfield MCM_ETBCC_ITDIS. */
00894 #define BF_MCM_ETBCC_ITDIS(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBCC_ITDIS) & BM_MCM_ETBCC_ITDIS)
00895 
00896 /*! @brief Set the ITDIS field to a new value. */
00897 #define BW_MCM_ETBCC_ITDIS(x, v) (HW_MCM_ETBCC_WR(x, (HW_MCM_ETBCC_RD(x) & ~BM_MCM_ETBCC_ITDIS) | BF_MCM_ETBCC_ITDIS(v)))
00898 /*@}*/
00899 
00900 /*******************************************************************************
00901  * HW_MCM_ETBRL - ETB Reload register
00902  ******************************************************************************/
00903 
00904 /*!
00905  * @brief HW_MCM_ETBRL - ETB Reload register (RW)
00906  *
00907  * Reset value: 0x00000000U
00908  */
00909 typedef union _hw_mcm_etbrl
00910 {
00911     uint32_t U;
00912     struct _hw_mcm_etbrl_bitfields
00913     {
00914         uint32_t RELOAD : 11;          /*!< [10:0] Byte Count Reload Value */
00915         uint32_t RESERVED0 : 21;       /*!< [31:11]  */
00916     } B;
00917 } hw_mcm_etbrl_t;
00918 
00919 /*!
00920  * @name Constants and macros for entire MCM_ETBRL register
00921  */
00922 /*@{*/
00923 #define HW_MCM_ETBRL_ADDR(x)     ((x) + 0x18U)
00924 
00925 #define HW_MCM_ETBRL(x)          (*(__IO hw_mcm_etbrl_t *) HW_MCM_ETBRL_ADDR(x))
00926 #define HW_MCM_ETBRL_RD(x)       (ADDRESS_READ(hw_mcm_etbrl_t, HW_MCM_ETBRL_ADDR(x)))
00927 #define HW_MCM_ETBRL_WR(x, v)    (ADDRESS_WRITE(hw_mcm_etbrl_t, HW_MCM_ETBRL_ADDR(x), v))
00928 #define HW_MCM_ETBRL_SET(x, v)   (HW_MCM_ETBRL_WR(x, HW_MCM_ETBRL_RD(x) |  (v)))
00929 #define HW_MCM_ETBRL_CLR(x, v)   (HW_MCM_ETBRL_WR(x, HW_MCM_ETBRL_RD(x) & ~(v)))
00930 #define HW_MCM_ETBRL_TOG(x, v)   (HW_MCM_ETBRL_WR(x, HW_MCM_ETBRL_RD(x) ^  (v)))
00931 /*@}*/
00932 
00933 /*
00934  * Constants & macros for individual MCM_ETBRL bitfields
00935  */
00936 
00937 /*!
00938  * @name Register MCM_ETBRL, field RELOAD[10:0] (RW)
00939  *
00940  * Indicates the 0-mod-4 value the counter reloads to. Writing a non-0-mod-4
00941  * value to this field results in a bus error.
00942  */
00943 /*@{*/
00944 #define BP_MCM_ETBRL_RELOAD  (0U)          /*!< Bit position for MCM_ETBRL_RELOAD. */
00945 #define BM_MCM_ETBRL_RELOAD  (0x000007FFU) /*!< Bit mask for MCM_ETBRL_RELOAD. */
00946 #define BS_MCM_ETBRL_RELOAD  (11U)         /*!< Bit field size in bits for MCM_ETBRL_RELOAD. */
00947 
00948 /*! @brief Read current value of the MCM_ETBRL_RELOAD field. */
00949 #define BR_MCM_ETBRL_RELOAD(x) (UNION_READ(hw_mcm_etbrl_t, HW_MCM_ETBRL_ADDR(x), U, B.RELOAD))
00950 
00951 /*! @brief Format value for bitfield MCM_ETBRL_RELOAD. */
00952 #define BF_MCM_ETBRL_RELOAD(v) ((uint32_t)((uint32_t)(v) << BP_MCM_ETBRL_RELOAD) & BM_MCM_ETBRL_RELOAD)
00953 
00954 /*! @brief Set the RELOAD field to a new value. */
00955 #define BW_MCM_ETBRL_RELOAD(x, v) (HW_MCM_ETBRL_WR(x, (HW_MCM_ETBRL_RD(x) & ~BM_MCM_ETBRL_RELOAD) | BF_MCM_ETBRL_RELOAD(v)))
00956 /*@}*/
00957 
00958 /*******************************************************************************
00959  * HW_MCM_ETBCNT - ETB Counter Value register
00960  ******************************************************************************/
00961 
00962 /*!
00963  * @brief HW_MCM_ETBCNT - ETB Counter Value register (RO)
00964  *
00965  * Reset value: 0x00000000U
00966  */
00967 typedef union _hw_mcm_etbcnt
00968 {
00969     uint32_t U;
00970     struct _hw_mcm_etbcnt_bitfields
00971     {
00972         uint32_t COUNTER : 11;         /*!< [10:0] Byte Count Counter Value */
00973         uint32_t RESERVED0 : 21;       /*!< [31:11]  */
00974     } B;
00975 } hw_mcm_etbcnt_t;
00976 
00977 /*!
00978  * @name Constants and macros for entire MCM_ETBCNT register
00979  */
00980 /*@{*/
00981 #define HW_MCM_ETBCNT_ADDR(x)    ((x) + 0x1CU)
00982 
00983 #define HW_MCM_ETBCNT(x)         (*(__I hw_mcm_etbcnt_t *) HW_MCM_ETBCNT_ADDR(x))
00984 #define HW_MCM_ETBCNT_RD(x)      (ADDRESS_READ(hw_mcm_etbcnt_t, HW_MCM_ETBCNT_ADDR(x)))
00985 /*@}*/
00986 
00987 /*
00988  * Constants & macros for individual MCM_ETBCNT bitfields
00989  */
00990 
00991 /*!
00992  * @name Register MCM_ETBCNT, field COUNTER[10:0] (RO)
00993  *
00994  * Indicates the current 0-mod-4 value of the counter.
00995  */
00996 /*@{*/
00997 #define BP_MCM_ETBCNT_COUNTER (0U)         /*!< Bit position for MCM_ETBCNT_COUNTER. */
00998 #define BM_MCM_ETBCNT_COUNTER (0x000007FFU) /*!< Bit mask for MCM_ETBCNT_COUNTER. */
00999 #define BS_MCM_ETBCNT_COUNTER (11U)        /*!< Bit field size in bits for MCM_ETBCNT_COUNTER. */
01000 
01001 /*! @brief Read current value of the MCM_ETBCNT_COUNTER field. */
01002 #define BR_MCM_ETBCNT_COUNTER(x) (UNION_READ(hw_mcm_etbcnt_t, HW_MCM_ETBCNT_ADDR(x), U, B.COUNTER))
01003 /*@}*/
01004 
01005 /*******************************************************************************
01006  * HW_MCM_PID - Process ID register
01007  ******************************************************************************/
01008 
01009 /*!
01010  * @brief HW_MCM_PID - Process ID register (RW)
01011  *
01012  * Reset value: 0x00000000U
01013  *
01014  * This register drives the M0_PID and M1_PID values in the Memory Protection
01015  * Unit(MPU). System software loads this register before passing control to a given
01016  * user mode process. If the PID of the process does not match the value in this
01017  * register, a bus error occurs. See the MPU chapter for more details.
01018  */
01019 typedef union _hw_mcm_pid
01020 {
01021     uint32_t U;
01022     struct _hw_mcm_pid_bitfields
01023     {
01024         uint32_t PID : 8;              /*!< [7:0] M0_PID And M1_PID For MPU */
01025         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
01026     } B;
01027 } hw_mcm_pid_t;
01028 
01029 /*!
01030  * @name Constants and macros for entire MCM_PID register
01031  */
01032 /*@{*/
01033 #define HW_MCM_PID_ADDR(x)       ((x) + 0x30U)
01034 
01035 #define HW_MCM_PID(x)            (*(__IO hw_mcm_pid_t *) HW_MCM_PID_ADDR(x))
01036 #define HW_MCM_PID_RD(x)         (ADDRESS_READ(hw_mcm_pid_t, HW_MCM_PID_ADDR(x)))
01037 #define HW_MCM_PID_WR(x, v)      (ADDRESS_WRITE(hw_mcm_pid_t, HW_MCM_PID_ADDR(x), v))
01038 #define HW_MCM_PID_SET(x, v)     (HW_MCM_PID_WR(x, HW_MCM_PID_RD(x) |  (v)))
01039 #define HW_MCM_PID_CLR(x, v)     (HW_MCM_PID_WR(x, HW_MCM_PID_RD(x) & ~(v)))
01040 #define HW_MCM_PID_TOG(x, v)     (HW_MCM_PID_WR(x, HW_MCM_PID_RD(x) ^  (v)))
01041 /*@}*/
01042 
01043 /*
01044  * Constants & macros for individual MCM_PID bitfields
01045  */
01046 
01047 /*!
01048  * @name Register MCM_PID, field PID[7:0] (RW)
01049  *
01050  * Drives the M0_PID and M1_PID values in the MPU.
01051  */
01052 /*@{*/
01053 #define BP_MCM_PID_PID       (0U)          /*!< Bit position for MCM_PID_PID. */
01054 #define BM_MCM_PID_PID       (0x000000FFU) /*!< Bit mask for MCM_PID_PID. */
01055 #define BS_MCM_PID_PID       (8U)          /*!< Bit field size in bits for MCM_PID_PID. */
01056 
01057 /*! @brief Read current value of the MCM_PID_PID field. */
01058 #define BR_MCM_PID_PID(x)    (UNION_READ(hw_mcm_pid_t, HW_MCM_PID_ADDR(x), U, B.PID))
01059 
01060 /*! @brief Format value for bitfield MCM_PID_PID. */
01061 #define BF_MCM_PID_PID(v)    ((uint32_t)((uint32_t)(v) << BP_MCM_PID_PID) & BM_MCM_PID_PID)
01062 
01063 /*! @brief Set the PID field to a new value. */
01064 #define BW_MCM_PID_PID(x, v) (HW_MCM_PID_WR(x, (HW_MCM_PID_RD(x) & ~BM_MCM_PID_PID) | BF_MCM_PID_PID(v)))
01065 /*@}*/
01066 
01067 /*******************************************************************************
01068  * hw_mcm_t - module struct
01069  ******************************************************************************/
01070 /*!
01071  * @brief All MCM module registers.
01072  */
01073 #pragma pack(1)
01074 typedef struct _hw_mcm
01075 {
01076     uint8_t _reserved0[8];
01077     __I hw_mcm_plasc_t PLASC ;              /*!< [0x8] Crossbar Switch (AXBS) Slave Configuration */
01078     __I hw_mcm_plamc_t PLAMC ;              /*!< [0xA] Crossbar Switch (AXBS) Master Configuration */
01079     __IO hw_mcm_cr_t CR ;                   /*!< [0xC] Control Register */
01080     __IO hw_mcm_iscr_t ISCR ;               /*!< [0x10] Interrupt Status Register */
01081     __IO hw_mcm_etbcc_t ETBCC ;             /*!< [0x14] ETB Counter Control register */
01082     __IO hw_mcm_etbrl_t ETBRL ;             /*!< [0x18] ETB Reload register */
01083     __I hw_mcm_etbcnt_t ETBCNT ;            /*!< [0x1C] ETB Counter Value register */
01084     uint8_t _reserved1[16];
01085     __IO hw_mcm_pid_t PID ;                 /*!< [0x30] Process ID register */
01086 } hw_mcm_t;
01087 #pragma pack()
01088 
01089 /*! @brief Macro to access all MCM registers. */
01090 /*! @param x MCM module instance base address. */
01091 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
01092  *     use the '&' operator, like <code>&HW_MCM(MCM_BASE)</code>. */
01093 #define HW_MCM(x)      (*(hw_mcm_t *)(x))
01094 
01095 #endif /* __HW_MCM_REGISTERS_H__ */
01096 /* EOF */