MK64F12_mcg.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_MCG_REGISTERS_H__
00088 #define __HW_MCG_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 MCG
00095  *
00096  * Multipurpose Clock Generator module
00097  *
00098  * Registers defined in this header file:
00099  * - HW_MCG_C1 - MCG Control 1 Register
00100  * - HW_MCG_C2 - MCG Control 2 Register
00101  * - HW_MCG_C3 - MCG Control 3 Register
00102  * - HW_MCG_C4 - MCG Control 4 Register
00103  * - HW_MCG_C5 - MCG Control 5 Register
00104  * - HW_MCG_C6 - MCG Control 6 Register
00105  * - HW_MCG_S - MCG Status Register
00106  * - HW_MCG_SC - MCG Status and Control Register
00107  * - HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register
00108  * - HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register
00109  * - HW_MCG_C7 - MCG Control 7 Register
00110  * - HW_MCG_C8 - MCG Control 8 Register
00111  *
00112  * - hw_mcg_t - Struct containing all module registers.
00113  */
00114 
00115 #define HW_MCG_INSTANCE_COUNT (1U) /*!< Number of instances of the MCG module. */
00116 
00117 /*******************************************************************************
00118  * HW_MCG_C1 - MCG Control 1 Register
00119  ******************************************************************************/
00120 
00121 /*!
00122  * @brief HW_MCG_C1 - MCG Control 1 Register (RW)
00123  *
00124  * Reset value: 0x04U
00125  */
00126 typedef union _hw_mcg_c1
00127 {
00128     uint8_t U;
00129     struct _hw_mcg_c1_bitfields
00130     {
00131         uint8_t IREFSTEN : 1;          /*!< [0] Internal Reference Stop Enable */
00132         uint8_t IRCLKEN : 1;           /*!< [1] Internal Reference Clock Enable */
00133         uint8_t IREFS : 1;             /*!< [2] Internal Reference Select */
00134         uint8_t FRDIV : 3;             /*!< [5:3] FLL External Reference Divider */
00135         uint8_t CLKS : 2;              /*!< [7:6] Clock Source Select */
00136     } B;
00137 } hw_mcg_c1_t;
00138 
00139 /*!
00140  * @name Constants and macros for entire MCG_C1 register
00141  */
00142 /*@{*/
00143 #define HW_MCG_C1_ADDR(x)        ((x) + 0x0U)
00144 
00145 #define HW_MCG_C1(x)             (*(__IO hw_mcg_c1_t *) HW_MCG_C1_ADDR(x))
00146 #define HW_MCG_C1_RD(x)          (ADDRESS_READ(hw_mcg_c1_t, HW_MCG_C1_ADDR(x)))
00147 #define HW_MCG_C1_WR(x, v)       (ADDRESS_WRITE(hw_mcg_c1_t, HW_MCG_C1_ADDR(x), v))
00148 #define HW_MCG_C1_SET(x, v)      (HW_MCG_C1_WR(x, HW_MCG_C1_RD(x) |  (v)))
00149 #define HW_MCG_C1_CLR(x, v)      (HW_MCG_C1_WR(x, HW_MCG_C1_RD(x) & ~(v)))
00150 #define HW_MCG_C1_TOG(x, v)      (HW_MCG_C1_WR(x, HW_MCG_C1_RD(x) ^  (v)))
00151 /*@}*/
00152 
00153 /*
00154  * Constants & macros for individual MCG_C1 bitfields
00155  */
00156 
00157 /*!
00158  * @name Register MCG_C1, field IREFSTEN[0] (RW)
00159  *
00160  * Controls whether or not the internal reference clock remains enabled when the
00161  * MCG enters Stop mode.
00162  *
00163  * Values:
00164  * - 0 - Internal reference clock is disabled in Stop mode.
00165  * - 1 - Internal reference clock is enabled in Stop mode if IRCLKEN is set or
00166  *     if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
00167  */
00168 /*@{*/
00169 #define BP_MCG_C1_IREFSTEN   (0U)          /*!< Bit position for MCG_C1_IREFSTEN. */
00170 #define BM_MCG_C1_IREFSTEN   (0x01U)       /*!< Bit mask for MCG_C1_IREFSTEN. */
00171 #define BS_MCG_C1_IREFSTEN   (1U)          /*!< Bit field size in bits for MCG_C1_IREFSTEN. */
00172 
00173 /*! @brief Read current value of the MCG_C1_IREFSTEN field. */
00174 #define BR_MCG_C1_IREFSTEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IREFSTEN)))
00175 
00176 /*! @brief Format value for bitfield MCG_C1_IREFSTEN. */
00177 #define BF_MCG_C1_IREFSTEN(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C1_IREFSTEN) & BM_MCG_C1_IREFSTEN)
00178 
00179 /*! @brief Set the IREFSTEN field to a new value. */
00180 #define BW_MCG_C1_IREFSTEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IREFSTEN), v))
00181 /*@}*/
00182 
00183 /*!
00184  * @name Register MCG_C1, field IRCLKEN[1] (RW)
00185  *
00186  * Enables the internal reference clock for use as MCGIRCLK.
00187  *
00188  * Values:
00189  * - 0 - MCGIRCLK inactive.
00190  * - 1 - MCGIRCLK active.
00191  */
00192 /*@{*/
00193 #define BP_MCG_C1_IRCLKEN    (1U)          /*!< Bit position for MCG_C1_IRCLKEN. */
00194 #define BM_MCG_C1_IRCLKEN    (0x02U)       /*!< Bit mask for MCG_C1_IRCLKEN. */
00195 #define BS_MCG_C1_IRCLKEN    (1U)          /*!< Bit field size in bits for MCG_C1_IRCLKEN. */
00196 
00197 /*! @brief Read current value of the MCG_C1_IRCLKEN field. */
00198 #define BR_MCG_C1_IRCLKEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IRCLKEN)))
00199 
00200 /*! @brief Format value for bitfield MCG_C1_IRCLKEN. */
00201 #define BF_MCG_C1_IRCLKEN(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C1_IRCLKEN) & BM_MCG_C1_IRCLKEN)
00202 
00203 /*! @brief Set the IRCLKEN field to a new value. */
00204 #define BW_MCG_C1_IRCLKEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IRCLKEN), v))
00205 /*@}*/
00206 
00207 /*!
00208  * @name Register MCG_C1, field IREFS[2] (RW)
00209  *
00210  * Selects the reference clock source for the FLL.
00211  *
00212  * Values:
00213  * - 0 - External reference clock is selected.
00214  * - 1 - The slow internal reference clock is selected.
00215  */
00216 /*@{*/
00217 #define BP_MCG_C1_IREFS      (2U)          /*!< Bit position for MCG_C1_IREFS. */
00218 #define BM_MCG_C1_IREFS      (0x04U)       /*!< Bit mask for MCG_C1_IREFS. */
00219 #define BS_MCG_C1_IREFS      (1U)          /*!< Bit field size in bits for MCG_C1_IREFS. */
00220 
00221 /*! @brief Read current value of the MCG_C1_IREFS field. */
00222 #define BR_MCG_C1_IREFS(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IREFS)))
00223 
00224 /*! @brief Format value for bitfield MCG_C1_IREFS. */
00225 #define BF_MCG_C1_IREFS(v)   ((uint8_t)((uint8_t)(v) << BP_MCG_C1_IREFS) & BM_MCG_C1_IREFS)
00226 
00227 /*! @brief Set the IREFS field to a new value. */
00228 #define BW_MCG_C1_IREFS(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_MCG_C1_ADDR(x), BP_MCG_C1_IREFS), v))
00229 /*@}*/
00230 
00231 /*!
00232  * @name Register MCG_C1, field FRDIV[5:3] (RW)
00233  *
00234  * Selects the amount to divide down the external reference clock for the FLL.
00235  * The resulting frequency must be in the range 31.25 kHz to 39.0625 kHz (This is
00236  * required when FLL/DCO is the clock source for MCGOUTCLK . In FBE mode, it is
00237  * not required to meet this range, but it is recommended in the cases when trying
00238  * to enter a FLL mode from FBE).
00239  *
00240  * Values:
00241  * - 000 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE
00242  *     values, Divide Factor is 32.
00243  * - 001 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE
00244  *     values, Divide Factor is 64.
00245  * - 010 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE
00246  *     values, Divide Factor is 128.
00247  * - 011 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE
00248  *     values, Divide Factor is 256.
00249  * - 100 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE
00250  *     values, Divide Factor is 512.
00251  * - 101 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE
00252  *     values, Divide Factor is 1024.
00253  * - 110 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE
00254  *     values, Divide Factor is 1280 .
00255  * - 111 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE
00256  *     values, Divide Factor is 1536 .
00257  */
00258 /*@{*/
00259 #define BP_MCG_C1_FRDIV      (3U)          /*!< Bit position for MCG_C1_FRDIV. */
00260 #define BM_MCG_C1_FRDIV      (0x38U)       /*!< Bit mask for MCG_C1_FRDIV. */
00261 #define BS_MCG_C1_FRDIV      (3U)          /*!< Bit field size in bits for MCG_C1_FRDIV. */
00262 
00263 /*! @brief Read current value of the MCG_C1_FRDIV field. */
00264 #define BR_MCG_C1_FRDIV(x)   (UNION_READ(hw_mcg_c1_t, HW_MCG_C1_ADDR(x), U, B.FRDIV))
00265 
00266 /*! @brief Format value for bitfield MCG_C1_FRDIV. */
00267 #define BF_MCG_C1_FRDIV(v)   ((uint8_t)((uint8_t)(v) << BP_MCG_C1_FRDIV) & BM_MCG_C1_FRDIV)
00268 
00269 /*! @brief Set the FRDIV field to a new value. */
00270 #define BW_MCG_C1_FRDIV(x, v) (HW_MCG_C1_WR(x, (HW_MCG_C1_RD(x) & ~BM_MCG_C1_FRDIV) | BF_MCG_C1_FRDIV(v)))
00271 /*@}*/
00272 
00273 /*!
00274  * @name Register MCG_C1, field CLKS[7:6] (RW)
00275  *
00276  * Selects the clock source for MCGOUTCLK .
00277  *
00278  * Values:
00279  * - 00 - Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control
00280  *     bit).
00281  * - 01 - Encoding 1 - Internal reference clock is selected.
00282  * - 10 - Encoding 2 - External reference clock is selected.
00283  * - 11 - Encoding 3 - Reserved.
00284  */
00285 /*@{*/
00286 #define BP_MCG_C1_CLKS       (6U)          /*!< Bit position for MCG_C1_CLKS. */
00287 #define BM_MCG_C1_CLKS       (0xC0U)       /*!< Bit mask for MCG_C1_CLKS. */
00288 #define BS_MCG_C1_CLKS       (2U)          /*!< Bit field size in bits for MCG_C1_CLKS. */
00289 
00290 /*! @brief Read current value of the MCG_C1_CLKS field. */
00291 #define BR_MCG_C1_CLKS(x)    (UNION_READ(hw_mcg_c1_t, HW_MCG_C1_ADDR(x), U, B.CLKS))
00292 
00293 /*! @brief Format value for bitfield MCG_C1_CLKS. */
00294 #define BF_MCG_C1_CLKS(v)    ((uint8_t)((uint8_t)(v) << BP_MCG_C1_CLKS) & BM_MCG_C1_CLKS)
00295 
00296 /*! @brief Set the CLKS field to a new value. */
00297 #define BW_MCG_C1_CLKS(x, v) (HW_MCG_C1_WR(x, (HW_MCG_C1_RD(x) & ~BM_MCG_C1_CLKS) | BF_MCG_C1_CLKS(v)))
00298 /*@}*/
00299 
00300 /*******************************************************************************
00301  * HW_MCG_C2 - MCG Control 2 Register
00302  ******************************************************************************/
00303 
00304 /*!
00305  * @brief HW_MCG_C2 - MCG Control 2 Register (RW)
00306  *
00307  * Reset value: 0x80U
00308  */
00309 typedef union _hw_mcg_c2
00310 {
00311     uint8_t U;
00312     struct _hw_mcg_c2_bitfields
00313     {
00314         uint8_t IRCS : 1;              /*!< [0] Internal Reference Clock Select */
00315         uint8_t LP : 1;                /*!< [1] Low Power Select */
00316         uint8_t EREFS : 1;             /*!< [2] External Reference Select */
00317         uint8_t HGO : 1;               /*!< [3] High Gain Oscillator Select */
00318         uint8_t RANGE : 2;             /*!< [5:4] Frequency Range Select */
00319         uint8_t FCFTRIM : 1;           /*!< [6] Fast Internal Reference Clock Fine Trim
00320                                         * */
00321         uint8_t LOCRE0 : 1;            /*!< [7] Loss of Clock Reset Enable */
00322     } B;
00323 } hw_mcg_c2_t;
00324 
00325 /*!
00326  * @name Constants and macros for entire MCG_C2 register
00327  */
00328 /*@{*/
00329 #define HW_MCG_C2_ADDR(x)        ((x) + 0x1U)
00330 
00331 #define HW_MCG_C2(x)             (*(__IO hw_mcg_c2_t *) HW_MCG_C2_ADDR(x))
00332 #define HW_MCG_C2_RD(x)          (ADDRESS_READ(hw_mcg_c2_t, HW_MCG_C2_ADDR(x)))
00333 #define HW_MCG_C2_WR(x, v)       (ADDRESS_WRITE(hw_mcg_c2_t, HW_MCG_C2_ADDR(x), v))
00334 #define HW_MCG_C2_SET(x, v)      (HW_MCG_C2_WR(x, HW_MCG_C2_RD(x) |  (v)))
00335 #define HW_MCG_C2_CLR(x, v)      (HW_MCG_C2_WR(x, HW_MCG_C2_RD(x) & ~(v)))
00336 #define HW_MCG_C2_TOG(x, v)      (HW_MCG_C2_WR(x, HW_MCG_C2_RD(x) ^  (v)))
00337 /*@}*/
00338 
00339 /*
00340  * Constants & macros for individual MCG_C2 bitfields
00341  */
00342 
00343 /*!
00344  * @name Register MCG_C2, field IRCS[0] (RW)
00345  *
00346  * Selects between the fast or slow internal reference clock source.
00347  *
00348  * Values:
00349  * - 0 - Slow internal reference clock selected.
00350  * - 1 - Fast internal reference clock selected.
00351  */
00352 /*@{*/
00353 #define BP_MCG_C2_IRCS       (0U)          /*!< Bit position for MCG_C2_IRCS. */
00354 #define BM_MCG_C2_IRCS       (0x01U)       /*!< Bit mask for MCG_C2_IRCS. */
00355 #define BS_MCG_C2_IRCS       (1U)          /*!< Bit field size in bits for MCG_C2_IRCS. */
00356 
00357 /*! @brief Read current value of the MCG_C2_IRCS field. */
00358 #define BR_MCG_C2_IRCS(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_IRCS)))
00359 
00360 /*! @brief Format value for bitfield MCG_C2_IRCS. */
00361 #define BF_MCG_C2_IRCS(v)    ((uint8_t)((uint8_t)(v) << BP_MCG_C2_IRCS) & BM_MCG_C2_IRCS)
00362 
00363 /*! @brief Set the IRCS field to a new value. */
00364 #define BW_MCG_C2_IRCS(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_IRCS), v))
00365 /*@}*/
00366 
00367 /*!
00368  * @name Register MCG_C2, field LP[1] (RW)
00369  *
00370  * Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. In FBE or
00371  * PBE modes, setting this bit to 1 will transition the MCG into BLPE mode; in
00372  * FBI mode, setting this bit to 1 will transition the MCG into BLPI mode. In any
00373  * other MCG mode, LP bit has no affect.
00374  *
00375  * Values:
00376  * - 0 - FLL or PLL is not disabled in bypass modes.
00377  * - 1 - FLL or PLL is disabled in bypass modes (lower power)
00378  */
00379 /*@{*/
00380 #define BP_MCG_C2_LP         (1U)          /*!< Bit position for MCG_C2_LP. */
00381 #define BM_MCG_C2_LP         (0x02U)       /*!< Bit mask for MCG_C2_LP. */
00382 #define BS_MCG_C2_LP         (1U)          /*!< Bit field size in bits for MCG_C2_LP. */
00383 
00384 /*! @brief Read current value of the MCG_C2_LP field. */
00385 #define BR_MCG_C2_LP(x)      (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_LP)))
00386 
00387 /*! @brief Format value for bitfield MCG_C2_LP. */
00388 #define BF_MCG_C2_LP(v)      ((uint8_t)((uint8_t)(v) << BP_MCG_C2_LP) & BM_MCG_C2_LP)
00389 
00390 /*! @brief Set the LP field to a new value. */
00391 #define BW_MCG_C2_LP(x, v)   (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_LP), v))
00392 /*@}*/
00393 
00394 /*!
00395  * @name Register MCG_C2, field EREFS[2] (RW)
00396  *
00397  * Selects the source for the external reference clock. See the Oscillator (OSC)
00398  * chapter for more details.
00399  *
00400  * Values:
00401  * - 0 - External reference clock requested.
00402  * - 1 - Oscillator requested.
00403  */
00404 /*@{*/
00405 #define BP_MCG_C2_EREFS      (2U)          /*!< Bit position for MCG_C2_EREFS. */
00406 #define BM_MCG_C2_EREFS      (0x04U)       /*!< Bit mask for MCG_C2_EREFS. */
00407 #define BS_MCG_C2_EREFS      (1U)          /*!< Bit field size in bits for MCG_C2_EREFS. */
00408 
00409 /*! @brief Read current value of the MCG_C2_EREFS field. */
00410 #define BR_MCG_C2_EREFS(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_EREFS)))
00411 
00412 /*! @brief Format value for bitfield MCG_C2_EREFS. */
00413 #define BF_MCG_C2_EREFS(v)   ((uint8_t)((uint8_t)(v) << BP_MCG_C2_EREFS) & BM_MCG_C2_EREFS)
00414 
00415 /*! @brief Set the EREFS field to a new value. */
00416 #define BW_MCG_C2_EREFS(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_EREFS), v))
00417 /*@}*/
00418 
00419 /*!
00420  * @name Register MCG_C2, field HGO[3] (RW)
00421  *
00422  * Controls the crystal oscillator mode of operation. See the Oscillator (OSC)
00423  * chapter for more details.
00424  *
00425  * Values:
00426  * - 0 - Configure crystal oscillator for low-power operation.
00427  * - 1 - Configure crystal oscillator for high-gain operation.
00428  */
00429 /*@{*/
00430 #define BP_MCG_C2_HGO        (3U)          /*!< Bit position for MCG_C2_HGO. */
00431 #define BM_MCG_C2_HGO        (0x08U)       /*!< Bit mask for MCG_C2_HGO. */
00432 #define BS_MCG_C2_HGO        (1U)          /*!< Bit field size in bits for MCG_C2_HGO. */
00433 
00434 /*! @brief Read current value of the MCG_C2_HGO field. */
00435 #define BR_MCG_C2_HGO(x)     (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_HGO)))
00436 
00437 /*! @brief Format value for bitfield MCG_C2_HGO. */
00438 #define BF_MCG_C2_HGO(v)     ((uint8_t)((uint8_t)(v) << BP_MCG_C2_HGO) & BM_MCG_C2_HGO)
00439 
00440 /*! @brief Set the HGO field to a new value. */
00441 #define BW_MCG_C2_HGO(x, v)  (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_HGO), v))
00442 /*@}*/
00443 
00444 /*!
00445  * @name Register MCG_C2, field RANGE[5:4] (RW)
00446  *
00447  * Selects the frequency range for the crystal oscillator or external clock
00448  * source. See the Oscillator (OSC) chapter for more details and the device data
00449  * sheet for the frequency ranges used.
00450  *
00451  * Values:
00452  * - 00 - Encoding 0 - Low frequency range selected for the crystal oscillator .
00453  * - 01 - Encoding 1 - High frequency range selected for the crystal oscillator .
00454  */
00455 /*@{*/
00456 #define BP_MCG_C2_RANGE      (4U)          /*!< Bit position for MCG_C2_RANGE. */
00457 #define BM_MCG_C2_RANGE      (0x30U)       /*!< Bit mask for MCG_C2_RANGE. */
00458 #define BS_MCG_C2_RANGE      (2U)          /*!< Bit field size in bits for MCG_C2_RANGE. */
00459 
00460 /*! @brief Read current value of the MCG_C2_RANGE field. */
00461 #define BR_MCG_C2_RANGE(x)   (UNION_READ(hw_mcg_c2_t, HW_MCG_C2_ADDR(x), U, B.RANGE))
00462 
00463 /*! @brief Format value for bitfield MCG_C2_RANGE. */
00464 #define BF_MCG_C2_RANGE(v)   ((uint8_t)((uint8_t)(v) << BP_MCG_C2_RANGE) & BM_MCG_C2_RANGE)
00465 
00466 /*! @brief Set the RANGE field to a new value. */
00467 #define BW_MCG_C2_RANGE(x, v) (HW_MCG_C2_WR(x, (HW_MCG_C2_RD(x) & ~BM_MCG_C2_RANGE) | BF_MCG_C2_RANGE(v)))
00468 /*@}*/
00469 
00470 /*!
00471  * @name Register MCG_C2, field FCFTRIM[6] (RW)
00472  *
00473  * FCFTRIM controls the smallest adjustment of the fast internal reference clock
00474  * frequency. Setting FCFTRIM increases the period and clearing FCFTRIM
00475  * decreases the period by the smallest amount possible. If an FCFTRIM value stored in
00476  * nonvolatile memory is to be used, it is your responsibility to copy that value
00477  * from the nonvolatile memory location to this bit.
00478  */
00479 /*@{*/
00480 #define BP_MCG_C2_FCFTRIM    (6U)          /*!< Bit position for MCG_C2_FCFTRIM. */
00481 #define BM_MCG_C2_FCFTRIM    (0x40U)       /*!< Bit mask for MCG_C2_FCFTRIM. */
00482 #define BS_MCG_C2_FCFTRIM    (1U)          /*!< Bit field size in bits for MCG_C2_FCFTRIM. */
00483 
00484 /*! @brief Read current value of the MCG_C2_FCFTRIM field. */
00485 #define BR_MCG_C2_FCFTRIM(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_FCFTRIM)))
00486 
00487 /*! @brief Format value for bitfield MCG_C2_FCFTRIM. */
00488 #define BF_MCG_C2_FCFTRIM(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C2_FCFTRIM) & BM_MCG_C2_FCFTRIM)
00489 
00490 /*! @brief Set the FCFTRIM field to a new value. */
00491 #define BW_MCG_C2_FCFTRIM(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_FCFTRIM), v))
00492 /*@}*/
00493 
00494 /*!
00495  * @name Register MCG_C2, field LOCRE0[7] (RW)
00496  *
00497  * Determines whether an interrupt or a reset request is made following a loss
00498  * of OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is
00499  * set.
00500  *
00501  * Values:
00502  * - 0 - Interrupt request is generated on a loss of OSC0 external reference
00503  *     clock.
00504  * - 1 - Generate a reset request on a loss of OSC0 external reference clock.
00505  */
00506 /*@{*/
00507 #define BP_MCG_C2_LOCRE0     (7U)          /*!< Bit position for MCG_C2_LOCRE0. */
00508 #define BM_MCG_C2_LOCRE0     (0x80U)       /*!< Bit mask for MCG_C2_LOCRE0. */
00509 #define BS_MCG_C2_LOCRE0     (1U)          /*!< Bit field size in bits for MCG_C2_LOCRE0. */
00510 
00511 /*! @brief Read current value of the MCG_C2_LOCRE0 field. */
00512 #define BR_MCG_C2_LOCRE0(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_LOCRE0)))
00513 
00514 /*! @brief Format value for bitfield MCG_C2_LOCRE0. */
00515 #define BF_MCG_C2_LOCRE0(v)  ((uint8_t)((uint8_t)(v) << BP_MCG_C2_LOCRE0) & BM_MCG_C2_LOCRE0)
00516 
00517 /*! @brief Set the LOCRE0 field to a new value. */
00518 #define BW_MCG_C2_LOCRE0(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_MCG_C2_ADDR(x), BP_MCG_C2_LOCRE0), v))
00519 /*@}*/
00520 
00521 /*******************************************************************************
00522  * HW_MCG_C3 - MCG Control 3 Register
00523  ******************************************************************************/
00524 
00525 /*!
00526  * @brief HW_MCG_C3 - MCG Control 3 Register (RW)
00527  *
00528  * Reset value: 0x00U
00529  */
00530 typedef union _hw_mcg_c3
00531 {
00532     uint8_t U;
00533     struct _hw_mcg_c3_bitfields
00534     {
00535         uint8_t SCTRIM : 8;            /*!< [7:0] Slow Internal Reference Clock Trim
00536                                         * Setting */
00537     } B;
00538 } hw_mcg_c3_t;
00539 
00540 /*!
00541  * @name Constants and macros for entire MCG_C3 register
00542  */
00543 /*@{*/
00544 #define HW_MCG_C3_ADDR(x)        ((x) + 0x2U)
00545 
00546 #define HW_MCG_C3(x)             (*(__IO hw_mcg_c3_t *) HW_MCG_C3_ADDR(x))
00547 #define HW_MCG_C3_RD(x)          (ADDRESS_READ(hw_mcg_c3_t, HW_MCG_C3_ADDR(x)))
00548 #define HW_MCG_C3_WR(x, v)       (ADDRESS_WRITE(hw_mcg_c3_t, HW_MCG_C3_ADDR(x), v))
00549 #define HW_MCG_C3_SET(x, v)      (HW_MCG_C3_WR(x, HW_MCG_C3_RD(x) |  (v)))
00550 #define HW_MCG_C3_CLR(x, v)      (HW_MCG_C3_WR(x, HW_MCG_C3_RD(x) & ~(v)))
00551 #define HW_MCG_C3_TOG(x, v)      (HW_MCG_C3_WR(x, HW_MCG_C3_RD(x) ^  (v)))
00552 /*@}*/
00553 
00554 /*
00555  * Constants & macros for individual MCG_C3 bitfields
00556  */
00557 
00558 /*!
00559  * @name Register MCG_C3, field SCTRIM[7:0] (RW)
00560  *
00561  * SCTRIM A value for SCTRIM is loaded during reset from a factory programmed
00562  * location. controls the slow internal reference clock frequency by controlling
00563  * the slow internal reference clock period. The SCTRIM bits are binary weighted,
00564  * that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value
00565  * increases the period, and decreasing the value decreases the period. An additional
00566  * fine trim bit is available in C4 register as the SCFTRIM bit. Upon reset,
00567  * this value is loaded with a factory trim value. If an SCTRIM value stored in
00568  * nonvolatile memory is to be used, it is your responsibility to copy that value
00569  * from the nonvolatile memory location to this register.
00570  */
00571 /*@{*/
00572 #define BP_MCG_C3_SCTRIM     (0U)          /*!< Bit position for MCG_C3_SCTRIM. */
00573 #define BM_MCG_C3_SCTRIM     (0xFFU)       /*!< Bit mask for MCG_C3_SCTRIM. */
00574 #define BS_MCG_C3_SCTRIM     (8U)          /*!< Bit field size in bits for MCG_C3_SCTRIM. */
00575 
00576 /*! @brief Read current value of the MCG_C3_SCTRIM field. */
00577 #define BR_MCG_C3_SCTRIM(x)  (HW_MCG_C3(x).U)
00578 
00579 /*! @brief Format value for bitfield MCG_C3_SCTRIM. */
00580 #define BF_MCG_C3_SCTRIM(v)  ((uint8_t)((uint8_t)(v) << BP_MCG_C3_SCTRIM) & BM_MCG_C3_SCTRIM)
00581 
00582 /*! @brief Set the SCTRIM field to a new value. */
00583 #define BW_MCG_C3_SCTRIM(x, v) (HW_MCG_C3_WR(x, v))
00584 /*@}*/
00585 
00586 /*******************************************************************************
00587  * HW_MCG_C4 - MCG Control 4 Register
00588  ******************************************************************************/
00589 
00590 /*!
00591  * @brief HW_MCG_C4 - MCG Control 4 Register (RW)
00592  *
00593  * Reset value: 0x00U
00594  *
00595  * Reset values for DRST and DMX32 bits are 0.
00596  */
00597 typedef union _hw_mcg_c4
00598 {
00599     uint8_t U;
00600     struct _hw_mcg_c4_bitfields
00601     {
00602         uint8_t SCFTRIM : 1;           /*!< [0] Slow Internal Reference Clock Fine Trim
00603                                         * */
00604         uint8_t FCTRIM : 4;            /*!< [4:1] Fast Internal Reference Clock Trim
00605                                         * Setting */
00606         uint8_t DRST_DRS : 2;          /*!< [6:5] DCO Range Select */
00607         uint8_t DMX32 : 1;             /*!< [7] DCO Maximum Frequency with 32.768 kHz
00608                                         * Reference */
00609     } B;
00610 } hw_mcg_c4_t;
00611 
00612 /*!
00613  * @name Constants and macros for entire MCG_C4 register
00614  */
00615 /*@{*/
00616 #define HW_MCG_C4_ADDR(x)        ((x) + 0x3U)
00617 
00618 #define HW_MCG_C4(x)             (*(__IO hw_mcg_c4_t *) HW_MCG_C4_ADDR(x))
00619 #define HW_MCG_C4_RD(x)          (ADDRESS_READ(hw_mcg_c4_t, HW_MCG_C4_ADDR(x)))
00620 #define HW_MCG_C4_WR(x, v)       (ADDRESS_WRITE(hw_mcg_c4_t, HW_MCG_C4_ADDR(x), v))
00621 #define HW_MCG_C4_SET(x, v)      (HW_MCG_C4_WR(x, HW_MCG_C4_RD(x) |  (v)))
00622 #define HW_MCG_C4_CLR(x, v)      (HW_MCG_C4_WR(x, HW_MCG_C4_RD(x) & ~(v)))
00623 #define HW_MCG_C4_TOG(x, v)      (HW_MCG_C4_WR(x, HW_MCG_C4_RD(x) ^  (v)))
00624 /*@}*/
00625 
00626 /*
00627  * Constants & macros for individual MCG_C4 bitfields
00628  */
00629 
00630 /*!
00631  * @name Register MCG_C4, field SCFTRIM[0] (RW)
00632  *
00633  * SCFTRIM A value for SCFTRIM is loaded during reset from a factory programmed
00634  * location . controls the smallest adjustment of the slow internal reference
00635  * clock frequency. Setting SCFTRIM increases the period and clearing SCFTRIM
00636  * decreases the period by the smallest amount possible. If an SCFTRIM value stored in
00637  * nonvolatile memory is to be used, it is your responsibility to copy that value
00638  * from the nonvolatile memory location to this bit.
00639  */
00640 /*@{*/
00641 #define BP_MCG_C4_SCFTRIM    (0U)          /*!< Bit position for MCG_C4_SCFTRIM. */
00642 #define BM_MCG_C4_SCFTRIM    (0x01U)       /*!< Bit mask for MCG_C4_SCFTRIM. */
00643 #define BS_MCG_C4_SCFTRIM    (1U)          /*!< Bit field size in bits for MCG_C4_SCFTRIM. */
00644 
00645 /*! @brief Read current value of the MCG_C4_SCFTRIM field. */
00646 #define BR_MCG_C4_SCFTRIM(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_C4_ADDR(x), BP_MCG_C4_SCFTRIM)))
00647 
00648 /*! @brief Format value for bitfield MCG_C4_SCFTRIM. */
00649 #define BF_MCG_C4_SCFTRIM(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C4_SCFTRIM) & BM_MCG_C4_SCFTRIM)
00650 
00651 /*! @brief Set the SCFTRIM field to a new value. */
00652 #define BW_MCG_C4_SCFTRIM(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_MCG_C4_ADDR(x), BP_MCG_C4_SCFTRIM), v))
00653 /*@}*/
00654 
00655 /*!
00656  * @name Register MCG_C4, field FCTRIM[4:1] (RW)
00657  *
00658  * FCTRIM A value for FCTRIM is loaded during reset from a factory programmed
00659  * location. controls the fast internal reference clock frequency by controlling
00660  * the fast internal reference clock period. The FCTRIM bits are binary weighted,
00661  * that is, bit 1 adjusts twice as much as bit 0. Increasing the binary value
00662  * increases the period, and decreasing the value decreases the period. If an
00663  * FCTRIM[3:0] value stored in nonvolatile memory is to be used, it is your
00664  * responsibility to copy that value from the nonvolatile memory location to this register.
00665  */
00666 /*@{*/
00667 #define BP_MCG_C4_FCTRIM     (1U)          /*!< Bit position for MCG_C4_FCTRIM. */
00668 #define BM_MCG_C4_FCTRIM     (0x1EU)       /*!< Bit mask for MCG_C4_FCTRIM. */
00669 #define BS_MCG_C4_FCTRIM     (4U)          /*!< Bit field size in bits for MCG_C4_FCTRIM. */
00670 
00671 /*! @brief Read current value of the MCG_C4_FCTRIM field. */
00672 #define BR_MCG_C4_FCTRIM(x)  (UNION_READ(hw_mcg_c4_t, HW_MCG_C4_ADDR(x), U, B.FCTRIM))
00673 
00674 /*! @brief Format value for bitfield MCG_C4_FCTRIM. */
00675 #define BF_MCG_C4_FCTRIM(v)  ((uint8_t)((uint8_t)(v) << BP_MCG_C4_FCTRIM) & BM_MCG_C4_FCTRIM)
00676 
00677 /*! @brief Set the FCTRIM field to a new value. */
00678 #define BW_MCG_C4_FCTRIM(x, v) (HW_MCG_C4_WR(x, (HW_MCG_C4_RD(x) & ~BM_MCG_C4_FCTRIM) | BF_MCG_C4_FCTRIM(v)))
00679 /*@}*/
00680 
00681 /*!
00682  * @name Register MCG_C4, field DRST_DRS[6:5] (RW)
00683  *
00684  * The DRS bits select the frequency range for the FLL output, DCOOUT. When the
00685  * LP bit is set, writes to the DRS bits are ignored. The DRST read field
00686  * indicates the current frequency range for DCOOUT. The DRST field does not update
00687  * immediately after a write to the DRS field due to internal synchronization between
00688  * clock domains. See the DCO Frequency Range table for more details.
00689  *
00690  * Values:
00691  * - 00 - Encoding 0 - Low range (reset default).
00692  * - 01 - Encoding 1 - Mid range.
00693  * - 10 - Encoding 2 - Mid-high range.
00694  * - 11 - Encoding 3 - High range.
00695  */
00696 /*@{*/
00697 #define BP_MCG_C4_DRST_DRS   (5U)          /*!< Bit position for MCG_C4_DRST_DRS. */
00698 #define BM_MCG_C4_DRST_DRS   (0x60U)       /*!< Bit mask for MCG_C4_DRST_DRS. */
00699 #define BS_MCG_C4_DRST_DRS   (2U)          /*!< Bit field size in bits for MCG_C4_DRST_DRS. */
00700 
00701 /*! @brief Read current value of the MCG_C4_DRST_DRS field. */
00702 #define BR_MCG_C4_DRST_DRS(x) (UNION_READ(hw_mcg_c4_t, HW_MCG_C4_ADDR(x), U, B.DRST_DRS))
00703 
00704 /*! @brief Format value for bitfield MCG_C4_DRST_DRS. */
00705 #define BF_MCG_C4_DRST_DRS(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C4_DRST_DRS) & BM_MCG_C4_DRST_DRS)
00706 
00707 /*! @brief Set the DRST_DRS field to a new value. */
00708 #define BW_MCG_C4_DRST_DRS(x, v) (HW_MCG_C4_WR(x, (HW_MCG_C4_RD(x) & ~BM_MCG_C4_DRST_DRS) | BF_MCG_C4_DRST_DRS(v)))
00709 /*@}*/
00710 
00711 /*!
00712  * @name Register MCG_C4, field DMX32[7] (RW)
00713  *
00714  * The DMX32 bit controls whether the DCO frequency range is narrowed to its
00715  * maximum frequency with a 32.768 kHz reference. The following table identifies
00716  * settings for the DCO frequency range. The system clocks derived from this source
00717  * should not exceed their specified maximums. DRST_DRS DMX32 Reference Range FLL
00718  * Factor DCO Range 00 0 31.25-39.0625 kHz 640 20-25 MHz 1 32.768 kHz 732 24 MHz
00719  * 01 0 31.25-39.0625 kHz 1280 40-50 MHz 1 32.768 kHz 1464 48 MHz 10 0
00720  * 31.25-39.0625 kHz 1920 60-75 MHz 1 32.768 kHz 2197 72 MHz 11 0 31.25-39.0625 kHz 2560
00721  * 80-100 MHz 1 32.768 kHz 2929 96 MHz
00722  *
00723  * Values:
00724  * - 0 - DCO has a default range of 25%.
00725  * - 1 - DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
00726  */
00727 /*@{*/
00728 #define BP_MCG_C4_DMX32      (7U)          /*!< Bit position for MCG_C4_DMX32. */
00729 #define BM_MCG_C4_DMX32      (0x80U)       /*!< Bit mask for MCG_C4_DMX32. */
00730 #define BS_MCG_C4_DMX32      (1U)          /*!< Bit field size in bits for MCG_C4_DMX32. */
00731 
00732 /*! @brief Read current value of the MCG_C4_DMX32 field. */
00733 #define BR_MCG_C4_DMX32(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_C4_ADDR(x), BP_MCG_C4_DMX32)))
00734 
00735 /*! @brief Format value for bitfield MCG_C4_DMX32. */
00736 #define BF_MCG_C4_DMX32(v)   ((uint8_t)((uint8_t)(v) << BP_MCG_C4_DMX32) & BM_MCG_C4_DMX32)
00737 
00738 /*! @brief Set the DMX32 field to a new value. */
00739 #define BW_MCG_C4_DMX32(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_MCG_C4_ADDR(x), BP_MCG_C4_DMX32), v))
00740 /*@}*/
00741 
00742 /*******************************************************************************
00743  * HW_MCG_C5 - MCG Control 5 Register
00744  ******************************************************************************/
00745 
00746 /*!
00747  * @brief HW_MCG_C5 - MCG Control 5 Register (RW)
00748  *
00749  * Reset value: 0x00U
00750  */
00751 typedef union _hw_mcg_c5
00752 {
00753     uint8_t U;
00754     struct _hw_mcg_c5_bitfields
00755     {
00756         uint8_t PRDIV0 : 5;            /*!< [4:0] PLL External Reference Divider */
00757         uint8_t PLLSTEN0 : 1;          /*!< [5] PLL Stop Enable */
00758         uint8_t PLLCLKEN0 : 1;         /*!< [6] PLL Clock Enable */
00759         uint8_t RESERVED0 : 1;         /*!< [7]  */
00760     } B;
00761 } hw_mcg_c5_t;
00762 
00763 /*!
00764  * @name Constants and macros for entire MCG_C5 register
00765  */
00766 /*@{*/
00767 #define HW_MCG_C5_ADDR(x)        ((x) + 0x4U)
00768 
00769 #define HW_MCG_C5(x)             (*(__IO hw_mcg_c5_t *) HW_MCG_C5_ADDR(x))
00770 #define HW_MCG_C5_RD(x)          (ADDRESS_READ(hw_mcg_c5_t, HW_MCG_C5_ADDR(x)))
00771 #define HW_MCG_C5_WR(x, v)       (ADDRESS_WRITE(hw_mcg_c5_t, HW_MCG_C5_ADDR(x), v))
00772 #define HW_MCG_C5_SET(x, v)      (HW_MCG_C5_WR(x, HW_MCG_C5_RD(x) |  (v)))
00773 #define HW_MCG_C5_CLR(x, v)      (HW_MCG_C5_WR(x, HW_MCG_C5_RD(x) & ~(v)))
00774 #define HW_MCG_C5_TOG(x, v)      (HW_MCG_C5_WR(x, HW_MCG_C5_RD(x) ^  (v)))
00775 /*@}*/
00776 
00777 /*
00778  * Constants & macros for individual MCG_C5 bitfields
00779  */
00780 
00781 /*!
00782  * @name Register MCG_C5, field PRDIV0[4:0] (RW)
00783  *
00784  * Selects the amount to divide down the external reference clock for the PLL.
00785  * The resulting frequency must be in the range of 2 MHz to 4 MHz. After the PLL
00786  * is enabled (by setting either PLLCLKEN 0 or PLLS), the PRDIV 0 value must not
00787  * be changed when LOCK0 is zero. PLL External Reference Divide Factor PRDIV 0
00788  * Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor PRDIV 0 Divide Factor
00789  * 00000 1 01000 9 10000 17 11000 25 00001 2 01001 10 10001 18 11001 Reserved
00790  * 00010 3 01010 11 10010 19 11010 Reserved 00011 4 01011 12 10011 20 11011 Reserved
00791  * 00100 5 01100 13 10100 21 11100 Reserved 00101 6 01101 14 10101 22 11101
00792  * Reserved 00110 7 01110 15 10110 23 11110 Reserved 00111 8 01111 16 10111 24 11111
00793  * Reserved
00794  */
00795 /*@{*/
00796 #define BP_MCG_C5_PRDIV0     (0U)          /*!< Bit position for MCG_C5_PRDIV0. */
00797 #define BM_MCG_C5_PRDIV0     (0x1FU)       /*!< Bit mask for MCG_C5_PRDIV0. */
00798 #define BS_MCG_C5_PRDIV0     (5U)          /*!< Bit field size in bits for MCG_C5_PRDIV0. */
00799 
00800 /*! @brief Read current value of the MCG_C5_PRDIV0 field. */
00801 #define BR_MCG_C5_PRDIV0(x)  (UNION_READ(hw_mcg_c5_t, HW_MCG_C5_ADDR(x), U, B.PRDIV0))
00802 
00803 /*! @brief Format value for bitfield MCG_C5_PRDIV0. */
00804 #define BF_MCG_C5_PRDIV0(v)  ((uint8_t)((uint8_t)(v) << BP_MCG_C5_PRDIV0) & BM_MCG_C5_PRDIV0)
00805 
00806 /*! @brief Set the PRDIV0 field to a new value. */
00807 #define BW_MCG_C5_PRDIV0(x, v) (HW_MCG_C5_WR(x, (HW_MCG_C5_RD(x) & ~BM_MCG_C5_PRDIV0) | BF_MCG_C5_PRDIV0(v)))
00808 /*@}*/
00809 
00810 /*!
00811  * @name Register MCG_C5, field PLLSTEN0[5] (RW)
00812  *
00813  * Enables the PLL Clock during Normal Stop. In Low Power Stop mode, the PLL
00814  * clock gets disabled even if PLLSTEN 0 =1. All other power modes, PLLSTEN 0 bit
00815  * has no affect and does not enable the PLL Clock to run if it is written to 1.
00816  *
00817  * Values:
00818  * - 0 - MCGPLLCLK is disabled in any of the Stop modes.
00819  * - 1 - MCGPLLCLK is enabled if system is in Normal Stop mode.
00820  */
00821 /*@{*/
00822 #define BP_MCG_C5_PLLSTEN0   (5U)          /*!< Bit position for MCG_C5_PLLSTEN0. */
00823 #define BM_MCG_C5_PLLSTEN0   (0x20U)       /*!< Bit mask for MCG_C5_PLLSTEN0. */
00824 #define BS_MCG_C5_PLLSTEN0   (1U)          /*!< Bit field size in bits for MCG_C5_PLLSTEN0. */
00825 
00826 /*! @brief Read current value of the MCG_C5_PLLSTEN0 field. */
00827 #define BR_MCG_C5_PLLSTEN0(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLSTEN0)))
00828 
00829 /*! @brief Format value for bitfield MCG_C5_PLLSTEN0. */
00830 #define BF_MCG_C5_PLLSTEN0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C5_PLLSTEN0) & BM_MCG_C5_PLLSTEN0)
00831 
00832 /*! @brief Set the PLLSTEN0 field to a new value. */
00833 #define BW_MCG_C5_PLLSTEN0(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLSTEN0), v))
00834 /*@}*/
00835 
00836 /*!
00837  * @name Register MCG_C5, field PLLCLKEN0[6] (RW)
00838  *
00839  * Enables the PLL independent of PLLS and enables the PLL clock for use as
00840  * MCGPLLCLK. (PRDIV 0 needs to be programmed to the correct divider to generate a
00841  * PLL reference clock in the range of 2 - 4 MHz range prior to setting the
00842  * PLLCLKEN 0 bit). Setting PLLCLKEN 0 will enable the external oscillator if not
00843  * already enabled. Whenever the PLL is being enabled by means of the PLLCLKEN 0 bit,
00844  * and the external oscillator is being used as the reference clock, the OSCINIT 0
00845  * bit should be checked to make sure it is set.
00846  *
00847  * Values:
00848  * - 0 - MCGPLLCLK is inactive.
00849  * - 1 - MCGPLLCLK is active.
00850  */
00851 /*@{*/
00852 #define BP_MCG_C5_PLLCLKEN0  (6U)          /*!< Bit position for MCG_C5_PLLCLKEN0. */
00853 #define BM_MCG_C5_PLLCLKEN0  (0x40U)       /*!< Bit mask for MCG_C5_PLLCLKEN0. */
00854 #define BS_MCG_C5_PLLCLKEN0  (1U)          /*!< Bit field size in bits for MCG_C5_PLLCLKEN0. */
00855 
00856 /*! @brief Read current value of the MCG_C5_PLLCLKEN0 field. */
00857 #define BR_MCG_C5_PLLCLKEN0(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLCLKEN0)))
00858 
00859 /*! @brief Format value for bitfield MCG_C5_PLLCLKEN0. */
00860 #define BF_MCG_C5_PLLCLKEN0(v) ((uint8_t)((uint8_t)(v) << BP_MCG_C5_PLLCLKEN0) & BM_MCG_C5_PLLCLKEN0)
00861 
00862 /*! @brief Set the PLLCLKEN0 field to a new value. */
00863 #define BW_MCG_C5_PLLCLKEN0(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_MCG_C5_ADDR(x), BP_MCG_C5_PLLCLKEN0), v))
00864 /*@}*/
00865 
00866 /*******************************************************************************
00867  * HW_MCG_C6 - MCG Control 6 Register
00868  ******************************************************************************/
00869 
00870 /*!
00871  * @brief HW_MCG_C6 - MCG Control 6 Register (RW)
00872  *
00873  * Reset value: 0x00U
00874  */
00875 typedef union _hw_mcg_c6
00876 {
00877     uint8_t U;
00878     struct _hw_mcg_c6_bitfields
00879     {
00880         uint8_t VDIV0 : 5;             /*!< [4:0] VCO 0 Divider */
00881         uint8_t CME0 : 1;              /*!< [5] Clock Monitor Enable */
00882         uint8_t PLLS : 1;              /*!< [6] PLL Select */
00883         uint8_t LOLIE0 : 1;            /*!< [7] Loss of Lock Interrrupt Enable */
00884     } B;
00885 } hw_mcg_c6_t;
00886 
00887 /*!
00888  * @name Constants and macros for entire MCG_C6 register
00889  */
00890 /*@{*/
00891 #define HW_MCG_C6_ADDR(x)        ((x) + 0x5U)
00892 
00893 #define HW_MCG_C6(x)             (*(__IO hw_mcg_c6_t *) HW_MCG_C6_ADDR(x))
00894 #define HW_MCG_C6_RD(x)          (ADDRESS_READ(hw_mcg_c6_t, HW_MCG_C6_ADDR(x)))
00895 #define HW_MCG_C6_WR(x, v)       (ADDRESS_WRITE(hw_mcg_c6_t, HW_MCG_C6_ADDR(x), v))
00896 #define HW_MCG_C6_SET(x, v)      (HW_MCG_C6_WR(x, HW_MCG_C6_RD(x) |  (v)))
00897 #define HW_MCG_C6_CLR(x, v)      (HW_MCG_C6_WR(x, HW_MCG_C6_RD(x) & ~(v)))
00898 #define HW_MCG_C6_TOG(x, v)      (HW_MCG_C6_WR(x, HW_MCG_C6_RD(x) ^  (v)))
00899 /*@}*/
00900 
00901 /*
00902  * Constants & macros for individual MCG_C6 bitfields
00903  */
00904 
00905 /*!
00906  * @name Register MCG_C6, field VDIV0[4:0] (RW)
00907  *
00908  * Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits
00909  * establish the multiplication factor (M) applied to the reference clock frequency.
00910  * After the PLL is enabled (by setting either PLLCLKEN 0 or PLLS), the VDIV 0
00911  * value must not be changed when LOCK 0 is zero. PLL VCO Divide Factor VDIV 0
00912  * Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply Factor VDIV 0 Multiply
00913  * Factor 00000 24 01000 32 10000 40 11000 48 00001 25 01001 33 10001 41 11001 49
00914  * 00010 26 01010 34 10010 42 11010 50 00011 27 01011 35 10011 43 11011 51 00100 28
00915  * 01100 36 10100 44 11100 52 00101 29 01101 37 10101 45 11101 53 00110 30 01110
00916  * 38 10110 46 11110 54 00111 31 01111 39 10111 47 11111 55
00917  */
00918 /*@{*/
00919 #define BP_MCG_C6_VDIV0      (0U)          /*!< Bit position for MCG_C6_VDIV0. */
00920 #define BM_MCG_C6_VDIV0      (0x1FU)       /*!< Bit mask for MCG_C6_VDIV0. */
00921 #define BS_MCG_C6_VDIV0      (5U)          /*!< Bit field size in bits for MCG_C6_VDIV0. */
00922 
00923 /*! @brief Read current value of the MCG_C6_VDIV0 field. */
00924 #define BR_MCG_C6_VDIV0(x)   (UNION_READ(hw_mcg_c6_t, HW_MCG_C6_ADDR(x), U, B.VDIV0))
00925 
00926 /*! @brief Format value for bitfield MCG_C6_VDIV0. */
00927 #define BF_MCG_C6_VDIV0(v)   ((uint8_t)((uint8_t)(v) << BP_MCG_C6_VDIV0) & BM_MCG_C6_VDIV0)
00928 
00929 /*! @brief Set the VDIV0 field to a new value. */
00930 #define BW_MCG_C6_VDIV0(x, v) (HW_MCG_C6_WR(x, (HW_MCG_C6_RD(x) & ~BM_MCG_C6_VDIV0) | BF_MCG_C6_VDIV0(v)))
00931 /*@}*/
00932 
00933 /*!
00934  * @name Register MCG_C6, field CME0[5] (RW)
00935  *
00936  * Enables the loss of clock monitoring circuit for the OSC0 external reference
00937  * mux select. The LOCRE0 bit will determine if a interrupt or a reset request is
00938  * generated following a loss of OSC0 indication. The CME0 bit must only be set
00939  * to a logic 1 when the MCG is in an operational mode that uses the external
00940  * clock (FEE, FBE, PEE, PBE, or BLPE) . Whenever the CME0 bit is set to a logic 1,
00941  * the value of the RANGE0 bits in the C2 register should not be changed. CME0
00942  * bit should be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
00943  * reset request may occur while in Stop mode. CME0 should also be set to a
00944  * logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode.
00945  *
00946  * Values:
00947  * - 0 - External clock monitor is disabled for OSC0.
00948  * - 1 - External clock monitor is enabled for OSC0.
00949  */
00950 /*@{*/
00951 #define BP_MCG_C6_CME0       (5U)          /*!< Bit position for MCG_C6_CME0. */
00952 #define BM_MCG_C6_CME0       (0x20U)       /*!< Bit mask for MCG_C6_CME0. */
00953 #define BS_MCG_C6_CME0       (1U)          /*!< Bit field size in bits for MCG_C6_CME0. */
00954 
00955 /*! @brief Read current value of the MCG_C6_CME0 field. */
00956 #define BR_MCG_C6_CME0(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_CME0)))
00957 
00958 /*! @brief Format value for bitfield MCG_C6_CME0. */
00959 #define BF_MCG_C6_CME0(v)    ((uint8_t)((uint8_t)(v) << BP_MCG_C6_CME0) & BM_MCG_C6_CME0)
00960 
00961 /*! @brief Set the CME0 field to a new value. */
00962 #define BW_MCG_C6_CME0(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_CME0), v))
00963 /*@}*/
00964 
00965 /*!
00966  * @name Register MCG_C6, field PLLS[6] (RW)
00967  *
00968  * Controls whether the PLL or FLL output is selected as the MCG source when
00969  * CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN 0 is not set, the PLL is
00970  * disabled in all modes. If the PLLS is set, the FLL is disabled in all modes.
00971  *
00972  * Values:
00973  * - 0 - FLL is selected.
00974  * - 1 - PLL is selected (PRDIV 0 need to be programmed to the correct divider
00975  *     to generate a PLL reference clock in the range of 2-4 MHz prior to setting
00976  *     the PLLS bit).
00977  */
00978 /*@{*/
00979 #define BP_MCG_C6_PLLS       (6U)          /*!< Bit position for MCG_C6_PLLS. */
00980 #define BM_MCG_C6_PLLS       (0x40U)       /*!< Bit mask for MCG_C6_PLLS. */
00981 #define BS_MCG_C6_PLLS       (1U)          /*!< Bit field size in bits for MCG_C6_PLLS. */
00982 
00983 /*! @brief Read current value of the MCG_C6_PLLS field. */
00984 #define BR_MCG_C6_PLLS(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_PLLS)))
00985 
00986 /*! @brief Format value for bitfield MCG_C6_PLLS. */
00987 #define BF_MCG_C6_PLLS(v)    ((uint8_t)((uint8_t)(v) << BP_MCG_C6_PLLS) & BM_MCG_C6_PLLS)
00988 
00989 /*! @brief Set the PLLS field to a new value. */
00990 #define BW_MCG_C6_PLLS(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_PLLS), v))
00991 /*@}*/
00992 
00993 /*!
00994  * @name Register MCG_C6, field LOLIE0[7] (RW)
00995  *
00996  * Determines if an interrupt request is made following a loss of lock
00997  * indication. This bit only has an effect when LOLS 0 is set.
00998  *
00999  * Values:
01000  * - 0 - No interrupt request is generated on loss of lock.
01001  * - 1 - Generate an interrupt request on loss of lock.
01002  */
01003 /*@{*/
01004 #define BP_MCG_C6_LOLIE0     (7U)          /*!< Bit position for MCG_C6_LOLIE0. */
01005 #define BM_MCG_C6_LOLIE0     (0x80U)       /*!< Bit mask for MCG_C6_LOLIE0. */
01006 #define BS_MCG_C6_LOLIE0     (1U)          /*!< Bit field size in bits for MCG_C6_LOLIE0. */
01007 
01008 /*! @brief Read current value of the MCG_C6_LOLIE0 field. */
01009 #define BR_MCG_C6_LOLIE0(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_LOLIE0)))
01010 
01011 /*! @brief Format value for bitfield MCG_C6_LOLIE0. */
01012 #define BF_MCG_C6_LOLIE0(v)  ((uint8_t)((uint8_t)(v) << BP_MCG_C6_LOLIE0) & BM_MCG_C6_LOLIE0)
01013 
01014 /*! @brief Set the LOLIE0 field to a new value. */
01015 #define BW_MCG_C6_LOLIE0(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_MCG_C6_ADDR(x), BP_MCG_C6_LOLIE0), v))
01016 /*@}*/
01017 
01018 /*******************************************************************************
01019  * HW_MCG_S - MCG Status Register
01020  ******************************************************************************/
01021 
01022 /*!
01023  * @brief HW_MCG_S - MCG Status Register (RW)
01024  *
01025  * Reset value: 0x10U
01026  */
01027 typedef union _hw_mcg_s
01028 {
01029     uint8_t U;
01030     struct _hw_mcg_s_bitfields
01031     {
01032         uint8_t IRCST : 1;             /*!< [0] Internal Reference Clock Status */
01033         uint8_t OSCINIT0 : 1;          /*!< [1] OSC Initialization */
01034         uint8_t CLKST : 2;             /*!< [3:2] Clock Mode Status */
01035         uint8_t IREFST : 1;            /*!< [4] Internal Reference Status */
01036         uint8_t PLLST : 1;             /*!< [5] PLL Select Status */
01037         uint8_t LOCK0 : 1;             /*!< [6] Lock Status */
01038         uint8_t LOLS0 : 1;             /*!< [7] Loss of Lock Status */
01039     } B;
01040 } hw_mcg_s_t;
01041 
01042 /*!
01043  * @name Constants and macros for entire MCG_S register
01044  */
01045 /*@{*/
01046 #define HW_MCG_S_ADDR(x)         ((x) + 0x6U)
01047 
01048 #define HW_MCG_S(x)              (*(__IO hw_mcg_s_t *) HW_MCG_S_ADDR(x))
01049 #define HW_MCG_S_RD(x)           (ADDRESS_READ(hw_mcg_s_t, HW_MCG_S_ADDR(x)))
01050 #define HW_MCG_S_WR(x, v)        (ADDRESS_WRITE(hw_mcg_s_t, HW_MCG_S_ADDR(x), v))
01051 #define HW_MCG_S_SET(x, v)       (HW_MCG_S_WR(x, HW_MCG_S_RD(x) |  (v)))
01052 #define HW_MCG_S_CLR(x, v)       (HW_MCG_S_WR(x, HW_MCG_S_RD(x) & ~(v)))
01053 #define HW_MCG_S_TOG(x, v)       (HW_MCG_S_WR(x, HW_MCG_S_RD(x) ^  (v)))
01054 /*@}*/
01055 
01056 /*
01057  * Constants & macros for individual MCG_S bitfields
01058  */
01059 
01060 /*!
01061  * @name Register MCG_S, field IRCST[0] (RO)
01062  *
01063  * The IRCST bit indicates the current source for the internal reference clock
01064  * select clock (IRCSCLK). The IRCST bit does not update immediately after a write
01065  * to the IRCS bit due to internal synchronization between clock domains. The
01066  * IRCST bit will only be updated if the internal reference clock is enabled,
01067  * either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN]
01068  * bit .
01069  *
01070  * Values:
01071  * - 0 - Source of internal reference clock is the slow clock (32 kHz IRC).
01072  * - 1 - Source of internal reference clock is the fast clock (4 MHz IRC).
01073  */
01074 /*@{*/
01075 #define BP_MCG_S_IRCST       (0U)          /*!< Bit position for MCG_S_IRCST. */
01076 #define BM_MCG_S_IRCST       (0x01U)       /*!< Bit mask for MCG_S_IRCST. */
01077 #define BS_MCG_S_IRCST       (1U)          /*!< Bit field size in bits for MCG_S_IRCST. */
01078 
01079 /*! @brief Read current value of the MCG_S_IRCST field. */
01080 #define BR_MCG_S_IRCST(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_S_ADDR(x), BP_MCG_S_IRCST)))
01081 /*@}*/
01082 
01083 /*!
01084  * @name Register MCG_S, field OSCINIT0[1] (RO)
01085  *
01086  * This bit, which resets to 0, is set to 1 after the initialization cycles of
01087  * the crystal oscillator clock have completed. After being set, the bit is
01088  * cleared to 0 if the OSC is subsequently disabled. See the OSC module's detailed
01089  * description for more information.
01090  */
01091 /*@{*/
01092 #define BP_MCG_S_OSCINIT0    (1U)          /*!< Bit position for MCG_S_OSCINIT0. */
01093 #define BM_MCG_S_OSCINIT0    (0x02U)       /*!< Bit mask for MCG_S_OSCINIT0. */
01094 #define BS_MCG_S_OSCINIT0    (1U)          /*!< Bit field size in bits for MCG_S_OSCINIT0. */
01095 
01096 /*! @brief Read current value of the MCG_S_OSCINIT0 field. */
01097 #define BR_MCG_S_OSCINIT0(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_S_ADDR(x), BP_MCG_S_OSCINIT0)))
01098 /*@}*/
01099 
01100 /*!
01101  * @name Register MCG_S, field CLKST[3:2] (RO)
01102  *
01103  * These bits indicate the current clock mode. The CLKST bits do not update
01104  * immediately after a write to the CLKS bits due to internal synchronization between
01105  * clock domains.
01106  *
01107  * Values:
01108  * - 00 - Encoding 0 - Output of the FLL is selected (reset default).
01109  * - 01 - Encoding 1 - Internal reference clock is selected.
01110  * - 10 - Encoding 2 - External reference clock is selected.
01111  * - 11 - Encoding 3 - Output of the PLL is selected.
01112  */
01113 /*@{*/
01114 #define BP_MCG_S_CLKST       (2U)          /*!< Bit position for MCG_S_CLKST. */
01115 #define BM_MCG_S_CLKST       (0x0CU)       /*!< Bit mask for MCG_S_CLKST. */
01116 #define BS_MCG_S_CLKST       (2U)          /*!< Bit field size in bits for MCG_S_CLKST. */
01117 
01118 /*! @brief Read current value of the MCG_S_CLKST field. */
01119 #define BR_MCG_S_CLKST(x)    (UNION_READ(hw_mcg_s_t, HW_MCG_S_ADDR(x), U, B.CLKST))
01120 /*@}*/
01121 
01122 /*!
01123  * @name Register MCG_S, field IREFST[4] (RO)
01124  *
01125  * This bit indicates the current source for the FLL reference clock. The IREFST
01126  * bit does not update immediately after a write to the IREFS bit due to
01127  * internal synchronization between clock domains.
01128  *
01129  * Values:
01130  * - 0 - Source of FLL reference clock is the external reference clock.
01131  * - 1 - Source of FLL reference clock is the internal reference clock.
01132  */
01133 /*@{*/
01134 #define BP_MCG_S_IREFST      (4U)          /*!< Bit position for MCG_S_IREFST. */
01135 #define BM_MCG_S_IREFST      (0x10U)       /*!< Bit mask for MCG_S_IREFST. */
01136 #define BS_MCG_S_IREFST      (1U)          /*!< Bit field size in bits for MCG_S_IREFST. */
01137 
01138 /*! @brief Read current value of the MCG_S_IREFST field. */
01139 #define BR_MCG_S_IREFST(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_S_ADDR(x), BP_MCG_S_IREFST)))
01140 /*@}*/
01141 
01142 /*!
01143  * @name Register MCG_S, field PLLST[5] (RO)
01144  *
01145  * This bit indicates the clock source selected by PLLS . The PLLST bit does not
01146  * update immediately after a write to the PLLS bit due to internal
01147  * synchronization between clock domains.
01148  *
01149  * Values:
01150  * - 0 - Source of PLLS clock is FLL clock.
01151  * - 1 - Source of PLLS clock is PLL output clock.
01152  */
01153 /*@{*/
01154 #define BP_MCG_S_PLLST       (5U)          /*!< Bit position for MCG_S_PLLST. */
01155 #define BM_MCG_S_PLLST       (0x20U)       /*!< Bit mask for MCG_S_PLLST. */
01156 #define BS_MCG_S_PLLST       (1U)          /*!< Bit field size in bits for MCG_S_PLLST. */
01157 
01158 /*! @brief Read current value of the MCG_S_PLLST field. */
01159 #define BR_MCG_S_PLLST(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_S_ADDR(x), BP_MCG_S_PLLST)))
01160 /*@}*/
01161 
01162 /*!
01163  * @name Register MCG_S, field LOCK0[6] (RO)
01164  *
01165  * This bit indicates whether the PLL has acquired lock. Lock detection is only
01166  * enabled when the PLL is enabled (either through clock mode selection or
01167  * PLLCLKEN0=1 setting). While the PLL clock is locking to the desired frequency, the
01168  * MCG PLL clock (MCGPLLCLK) will be gated off until the LOCK bit gets asserted.
01169  * If the lock status bit is set, changing the value of the PRDIV0 [4:0] bits in
01170  * the C5 register or the VDIV0[4:0] bits in the C6 register causes the lock
01171  * status bit to clear and stay cleared until the PLL has reacquired lock. Loss of PLL
01172  * reference clock will also cause the LOCK0 bit to clear until the PLL has
01173  * reacquired lock. Entry into LLS, VLPS, or regular Stop with PLLSTEN=0 also causes
01174  * the lock status bit to clear and stay cleared until the Stop mode is exited
01175  * and the PLL has reacquired lock. Any time the PLL is enabled and the LOCK0 bit
01176  * is cleared, the MCGPLLCLK will be gated off until the LOCK0 bit is asserted
01177  * again.
01178  *
01179  * Values:
01180  * - 0 - PLL is currently unlocked.
01181  * - 1 - PLL is currently locked.
01182  */
01183 /*@{*/
01184 #define BP_MCG_S_LOCK0       (6U)          /*!< Bit position for MCG_S_LOCK0. */
01185 #define BM_MCG_S_LOCK0       (0x40U)       /*!< Bit mask for MCG_S_LOCK0. */
01186 #define BS_MCG_S_LOCK0       (1U)          /*!< Bit field size in bits for MCG_S_LOCK0. */
01187 
01188 /*! @brief Read current value of the MCG_S_LOCK0 field. */
01189 #define BR_MCG_S_LOCK0(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_S_ADDR(x), BP_MCG_S_LOCK0)))
01190 /*@}*/
01191 
01192 /*!
01193  * @name Register MCG_S, field LOLS0[7] (W1C)
01194  *
01195  * This bit is a sticky bit indicating the lock status for the PLL. LOLS is set
01196  * if after acquiring lock, the PLL output frequency has fallen outside the lock
01197  * exit frequency tolerance, D unl . LOLIE determines whether an interrupt
01198  * request is made when LOLS is set. LOLRE determines whether a reset request is made
01199  * when LOLS is set. This bit is cleared by reset or by writing a logic 1 to it
01200  * when set. Writing a logic 0 to this bit has no effect.
01201  *
01202  * Values:
01203  * - 0 - PLL has not lost lock since LOLS 0 was last cleared.
01204  * - 1 - PLL has lost lock since LOLS 0 was last cleared.
01205  */
01206 /*@{*/
01207 #define BP_MCG_S_LOLS0       (7U)          /*!< Bit position for MCG_S_LOLS0. */
01208 #define BM_MCG_S_LOLS0       (0x80U)       /*!< Bit mask for MCG_S_LOLS0. */
01209 #define BS_MCG_S_LOLS0       (1U)          /*!< Bit field size in bits for MCG_S_LOLS0. */
01210 
01211 /*! @brief Read current value of the MCG_S_LOLS0 field. */
01212 #define BR_MCG_S_LOLS0(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_S_ADDR(x), BP_MCG_S_LOLS0)))
01213 
01214 /*! @brief Format value for bitfield MCG_S_LOLS0. */
01215 #define BF_MCG_S_LOLS0(v)    ((uint8_t)((uint8_t)(v) << BP_MCG_S_LOLS0) & BM_MCG_S_LOLS0)
01216 
01217 /*! @brief Set the LOLS0 field to a new value. */
01218 #define BW_MCG_S_LOLS0(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_MCG_S_ADDR(x), BP_MCG_S_LOLS0), v))
01219 /*@}*/
01220 
01221 /*******************************************************************************
01222  * HW_MCG_SC - MCG Status and Control Register
01223  ******************************************************************************/
01224 
01225 /*!
01226  * @brief HW_MCG_SC - MCG Status and Control Register (RW)
01227  *
01228  * Reset value: 0x02U
01229  */
01230 typedef union _hw_mcg_sc
01231 {
01232     uint8_t U;
01233     struct _hw_mcg_sc_bitfields
01234     {
01235         uint8_t LOCS0 : 1;             /*!< [0] OSC0 Loss of Clock Status */
01236         uint8_t FCRDIV : 3;            /*!< [3:1] Fast Clock Internal Reference Divider
01237                                         * */
01238         uint8_t FLTPRSRV : 1;          /*!< [4] FLL Filter Preserve Enable */
01239         uint8_t ATMF : 1;              /*!< [5] Automatic Trim Machine Fail Flag */
01240         uint8_t ATMS : 1;              /*!< [6] Automatic Trim Machine Select */
01241         uint8_t ATME : 1;              /*!< [7] Automatic Trim Machine Enable */
01242     } B;
01243 } hw_mcg_sc_t;
01244 
01245 /*!
01246  * @name Constants and macros for entire MCG_SC register
01247  */
01248 /*@{*/
01249 #define HW_MCG_SC_ADDR(x)        ((x) + 0x8U)
01250 
01251 #define HW_MCG_SC(x)             (*(__IO hw_mcg_sc_t *) HW_MCG_SC_ADDR(x))
01252 #define HW_MCG_SC_RD(x)          (ADDRESS_READ(hw_mcg_sc_t, HW_MCG_SC_ADDR(x)))
01253 #define HW_MCG_SC_WR(x, v)       (ADDRESS_WRITE(hw_mcg_sc_t, HW_MCG_SC_ADDR(x), v))
01254 #define HW_MCG_SC_SET(x, v)      (HW_MCG_SC_WR(x, HW_MCG_SC_RD(x) |  (v)))
01255 #define HW_MCG_SC_CLR(x, v)      (HW_MCG_SC_WR(x, HW_MCG_SC_RD(x) & ~(v)))
01256 #define HW_MCG_SC_TOG(x, v)      (HW_MCG_SC_WR(x, HW_MCG_SC_RD(x) ^  (v)))
01257 /*@}*/
01258 
01259 /*
01260  * Constants & macros for individual MCG_SC bitfields
01261  */
01262 
01263 /*!
01264  * @name Register MCG_SC, field LOCS0[0] (W1C)
01265  *
01266  * The LOCS0 indicates when a loss of OSC0 reference clock has occurred. The
01267  * LOCS0 bit only has an effect when CME0 is set. This bit is cleared by writing a
01268  * logic 1 to it when set.
01269  *
01270  * Values:
01271  * - 0 - Loss of OSC0 has not occurred.
01272  * - 1 - Loss of OSC0 has occurred.
01273  */
01274 /*@{*/
01275 #define BP_MCG_SC_LOCS0      (0U)          /*!< Bit position for MCG_SC_LOCS0. */
01276 #define BM_MCG_SC_LOCS0      (0x01U)       /*!< Bit mask for MCG_SC_LOCS0. */
01277 #define BS_MCG_SC_LOCS0      (1U)          /*!< Bit field size in bits for MCG_SC_LOCS0. */
01278 
01279 /*! @brief Read current value of the MCG_SC_LOCS0 field. */
01280 #define BR_MCG_SC_LOCS0(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_LOCS0)))
01281 
01282 /*! @brief Format value for bitfield MCG_SC_LOCS0. */
01283 #define BF_MCG_SC_LOCS0(v)   ((uint8_t)((uint8_t)(v) << BP_MCG_SC_LOCS0) & BM_MCG_SC_LOCS0)
01284 
01285 /*! @brief Set the LOCS0 field to a new value. */
01286 #define BW_MCG_SC_LOCS0(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_LOCS0), v))
01287 /*@}*/
01288 
01289 /*!
01290  * @name Register MCG_SC, field FCRDIV[3:1] (RW)
01291  *
01292  * Selects the amount to divide down the fast internal reference clock. The
01293  * resulting frequency will be in the range 31.25 kHz to 4 MHz (Note: Changing the
01294  * divider when the Fast IRC is enabled is not supported).
01295  *
01296  * Values:
01297  * - 000 - Divide Factor is 1
01298  * - 001 - Divide Factor is 2.
01299  * - 010 - Divide Factor is 4.
01300  * - 011 - Divide Factor is 8.
01301  * - 100 - Divide Factor is 16
01302  * - 101 - Divide Factor is 32
01303  * - 110 - Divide Factor is 64
01304  * - 111 - Divide Factor is 128.
01305  */
01306 /*@{*/
01307 #define BP_MCG_SC_FCRDIV     (1U)          /*!< Bit position for MCG_SC_FCRDIV. */
01308 #define BM_MCG_SC_FCRDIV     (0x0EU)       /*!< Bit mask for MCG_SC_FCRDIV. */
01309 #define BS_MCG_SC_FCRDIV     (3U)          /*!< Bit field size in bits for MCG_SC_FCRDIV. */
01310 
01311 /*! @brief Read current value of the MCG_SC_FCRDIV field. */
01312 #define BR_MCG_SC_FCRDIV(x)  (UNION_READ(hw_mcg_sc_t, HW_MCG_SC_ADDR(x), U, B.FCRDIV))
01313 
01314 /*! @brief Format value for bitfield MCG_SC_FCRDIV. */
01315 #define BF_MCG_SC_FCRDIV(v)  ((uint8_t)((uint8_t)(v) << BP_MCG_SC_FCRDIV) & BM_MCG_SC_FCRDIV)
01316 
01317 /*! @brief Set the FCRDIV field to a new value. */
01318 #define BW_MCG_SC_FCRDIV(x, v) (HW_MCG_SC_WR(x, (HW_MCG_SC_RD(x) & ~BM_MCG_SC_FCRDIV) | BF_MCG_SC_FCRDIV(v)))
01319 /*@}*/
01320 
01321 /*!
01322  * @name Register MCG_SC, field FLTPRSRV[4] (RW)
01323  *
01324  * This bit will prevent the FLL filter values from resetting allowing the FLL
01325  * output frequency to remain the same during clock mode changes where the FLL/DCO
01326  * output is still valid. (Note: This requires that the FLL reference frequency
01327  * to remain the same as what it was prior to the new clock mode switch.
01328  * Otherwise FLL filter and frequency values will change.)
01329  *
01330  * Values:
01331  * - 0 - FLL filter and FLL frequency will reset on changes to currect clock
01332  *     mode.
01333  * - 1 - Fll filter and FLL frequency retain their previous values during new
01334  *     clock mode change.
01335  */
01336 /*@{*/
01337 #define BP_MCG_SC_FLTPRSRV   (4U)          /*!< Bit position for MCG_SC_FLTPRSRV. */
01338 #define BM_MCG_SC_FLTPRSRV   (0x10U)       /*!< Bit mask for MCG_SC_FLTPRSRV. */
01339 #define BS_MCG_SC_FLTPRSRV   (1U)          /*!< Bit field size in bits for MCG_SC_FLTPRSRV. */
01340 
01341 /*! @brief Read current value of the MCG_SC_FLTPRSRV field. */
01342 #define BR_MCG_SC_FLTPRSRV(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_FLTPRSRV)))
01343 
01344 /*! @brief Format value for bitfield MCG_SC_FLTPRSRV. */
01345 #define BF_MCG_SC_FLTPRSRV(v) ((uint8_t)((uint8_t)(v) << BP_MCG_SC_FLTPRSRV) & BM_MCG_SC_FLTPRSRV)
01346 
01347 /*! @brief Set the FLTPRSRV field to a new value. */
01348 #define BW_MCG_SC_FLTPRSRV(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_FLTPRSRV), v))
01349 /*@}*/
01350 
01351 /*!
01352  * @name Register MCG_SC, field ATMF[5] (RW)
01353  *
01354  * Fail flag for the Automatic Trim Machine (ATM). This bit asserts when the
01355  * Automatic Trim Machine is enabled, ATME=1, and a write to the C1, C3, C4, and SC
01356  * registers is detected or the MCG enters into any Stop mode. A write to ATMF
01357  * clears the flag.
01358  *
01359  * Values:
01360  * - 0 - Automatic Trim Machine completed normally.
01361  * - 1 - Automatic Trim Machine failed.
01362  */
01363 /*@{*/
01364 #define BP_MCG_SC_ATMF       (5U)          /*!< Bit position for MCG_SC_ATMF. */
01365 #define BM_MCG_SC_ATMF       (0x20U)       /*!< Bit mask for MCG_SC_ATMF. */
01366 #define BS_MCG_SC_ATMF       (1U)          /*!< Bit field size in bits for MCG_SC_ATMF. */
01367 
01368 /*! @brief Read current value of the MCG_SC_ATMF field. */
01369 #define BR_MCG_SC_ATMF(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATMF)))
01370 
01371 /*! @brief Format value for bitfield MCG_SC_ATMF. */
01372 #define BF_MCG_SC_ATMF(v)    ((uint8_t)((uint8_t)(v) << BP_MCG_SC_ATMF) & BM_MCG_SC_ATMF)
01373 
01374 /*! @brief Set the ATMF field to a new value. */
01375 #define BW_MCG_SC_ATMF(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATMF), v))
01376 /*@}*/
01377 
01378 /*!
01379  * @name Register MCG_SC, field ATMS[6] (RW)
01380  *
01381  * Selects the IRCS clock for Auto Trim Test.
01382  *
01383  * Values:
01384  * - 0 - 32 kHz Internal Reference Clock selected.
01385  * - 1 - 4 MHz Internal Reference Clock selected.
01386  */
01387 /*@{*/
01388 #define BP_MCG_SC_ATMS       (6U)          /*!< Bit position for MCG_SC_ATMS. */
01389 #define BM_MCG_SC_ATMS       (0x40U)       /*!< Bit mask for MCG_SC_ATMS. */
01390 #define BS_MCG_SC_ATMS       (1U)          /*!< Bit field size in bits for MCG_SC_ATMS. */
01391 
01392 /*! @brief Read current value of the MCG_SC_ATMS field. */
01393 #define BR_MCG_SC_ATMS(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATMS)))
01394 
01395 /*! @brief Format value for bitfield MCG_SC_ATMS. */
01396 #define BF_MCG_SC_ATMS(v)    ((uint8_t)((uint8_t)(v) << BP_MCG_SC_ATMS) & BM_MCG_SC_ATMS)
01397 
01398 /*! @brief Set the ATMS field to a new value. */
01399 #define BW_MCG_SC_ATMS(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATMS), v))
01400 /*@}*/
01401 
01402 /*!
01403  * @name Register MCG_SC, field ATME[7] (RW)
01404  *
01405  * Enables the Auto Trim Machine to start automatically trimming the selected
01406  * Internal Reference Clock. ATME deasserts after the Auto Trim Machine has
01407  * completed trimming all trim bits of the IRCS clock selected by the ATMS bit. Writing
01408  * to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim
01409  * operation and clears this bit.
01410  *
01411  * Values:
01412  * - 0 - Auto Trim Machine disabled.
01413  * - 1 - Auto Trim Machine enabled.
01414  */
01415 /*@{*/
01416 #define BP_MCG_SC_ATME       (7U)          /*!< Bit position for MCG_SC_ATME. */
01417 #define BM_MCG_SC_ATME       (0x80U)       /*!< Bit mask for MCG_SC_ATME. */
01418 #define BS_MCG_SC_ATME       (1U)          /*!< Bit field size in bits for MCG_SC_ATME. */
01419 
01420 /*! @brief Read current value of the MCG_SC_ATME field. */
01421 #define BR_MCG_SC_ATME(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATME)))
01422 
01423 /*! @brief Format value for bitfield MCG_SC_ATME. */
01424 #define BF_MCG_SC_ATME(v)    ((uint8_t)((uint8_t)(v) << BP_MCG_SC_ATME) & BM_MCG_SC_ATME)
01425 
01426 /*! @brief Set the ATME field to a new value. */
01427 #define BW_MCG_SC_ATME(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_MCG_SC_ADDR(x), BP_MCG_SC_ATME), v))
01428 /*@}*/
01429 
01430 /*******************************************************************************
01431  * HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register
01432  ******************************************************************************/
01433 
01434 /*!
01435  * @brief HW_MCG_ATCVH - MCG Auto Trim Compare Value High Register (RW)
01436  *
01437  * Reset value: 0x00U
01438  */
01439 typedef union _hw_mcg_atcvh
01440 {
01441     uint8_t U;
01442     struct _hw_mcg_atcvh_bitfields
01443     {
01444         uint8_t ATCVH : 8;             /*!< [7:0] ATM Compare Value High */
01445     } B;
01446 } hw_mcg_atcvh_t;
01447 
01448 /*!
01449  * @name Constants and macros for entire MCG_ATCVH register
01450  */
01451 /*@{*/
01452 #define HW_MCG_ATCVH_ADDR(x)     ((x) + 0xAU)
01453 
01454 #define HW_MCG_ATCVH(x)          (*(__IO hw_mcg_atcvh_t *) HW_MCG_ATCVH_ADDR(x))
01455 #define HW_MCG_ATCVH_RD(x)       (ADDRESS_READ(hw_mcg_atcvh_t, HW_MCG_ATCVH_ADDR(x)))
01456 #define HW_MCG_ATCVH_WR(x, v)    (ADDRESS_WRITE(hw_mcg_atcvh_t, HW_MCG_ATCVH_ADDR(x), v))
01457 #define HW_MCG_ATCVH_SET(x, v)   (HW_MCG_ATCVH_WR(x, HW_MCG_ATCVH_RD(x) |  (v)))
01458 #define HW_MCG_ATCVH_CLR(x, v)   (HW_MCG_ATCVH_WR(x, HW_MCG_ATCVH_RD(x) & ~(v)))
01459 #define HW_MCG_ATCVH_TOG(x, v)   (HW_MCG_ATCVH_WR(x, HW_MCG_ATCVH_RD(x) ^  (v)))
01460 /*@}*/
01461 
01462 /*
01463  * Constants & macros for individual MCG_ATCVH bitfields
01464  */
01465 
01466 /*!
01467  * @name Register MCG_ATCVH, field ATCVH[7:0] (RW)
01468  *
01469  * Values are used by Auto Trim Machine to compare and adjust Internal Reference
01470  * trim values during ATM SAR conversion.
01471  */
01472 /*@{*/
01473 #define BP_MCG_ATCVH_ATCVH   (0U)          /*!< Bit position for MCG_ATCVH_ATCVH. */
01474 #define BM_MCG_ATCVH_ATCVH   (0xFFU)       /*!< Bit mask for MCG_ATCVH_ATCVH. */
01475 #define BS_MCG_ATCVH_ATCVH   (8U)          /*!< Bit field size in bits for MCG_ATCVH_ATCVH. */
01476 
01477 /*! @brief Read current value of the MCG_ATCVH_ATCVH field. */
01478 #define BR_MCG_ATCVH_ATCVH(x) (HW_MCG_ATCVH(x).U)
01479 
01480 /*! @brief Format value for bitfield MCG_ATCVH_ATCVH. */
01481 #define BF_MCG_ATCVH_ATCVH(v) ((uint8_t)((uint8_t)(v) << BP_MCG_ATCVH_ATCVH) & BM_MCG_ATCVH_ATCVH)
01482 
01483 /*! @brief Set the ATCVH field to a new value. */
01484 #define BW_MCG_ATCVH_ATCVH(x, v) (HW_MCG_ATCVH_WR(x, v))
01485 /*@}*/
01486 
01487 /*******************************************************************************
01488  * HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register
01489  ******************************************************************************/
01490 
01491 /*!
01492  * @brief HW_MCG_ATCVL - MCG Auto Trim Compare Value Low Register (RW)
01493  *
01494  * Reset value: 0x00U
01495  */
01496 typedef union _hw_mcg_atcvl
01497 {
01498     uint8_t U;
01499     struct _hw_mcg_atcvl_bitfields
01500     {
01501         uint8_t ATCVL : 8;             /*!< [7:0] ATM Compare Value Low */
01502     } B;
01503 } hw_mcg_atcvl_t;
01504 
01505 /*!
01506  * @name Constants and macros for entire MCG_ATCVL register
01507  */
01508 /*@{*/
01509 #define HW_MCG_ATCVL_ADDR(x)     ((x) + 0xBU)
01510 
01511 #define HW_MCG_ATCVL(x)          (*(__IO hw_mcg_atcvl_t *) HW_MCG_ATCVL_ADDR(x))
01512 #define HW_MCG_ATCVL_RD(x)       (ADDRESS_READ(hw_mcg_atcvl_t, HW_MCG_ATCVL_ADDR(x)))
01513 #define HW_MCG_ATCVL_WR(x, v)    (ADDRESS_WRITE(hw_mcg_atcvl_t, HW_MCG_ATCVL_ADDR(x), v))
01514 #define HW_MCG_ATCVL_SET(x, v)   (HW_MCG_ATCVL_WR(x, HW_MCG_ATCVL_RD(x) |  (v)))
01515 #define HW_MCG_ATCVL_CLR(x, v)   (HW_MCG_ATCVL_WR(x, HW_MCG_ATCVL_RD(x) & ~(v)))
01516 #define HW_MCG_ATCVL_TOG(x, v)   (HW_MCG_ATCVL_WR(x, HW_MCG_ATCVL_RD(x) ^  (v)))
01517 /*@}*/
01518 
01519 /*
01520  * Constants & macros for individual MCG_ATCVL bitfields
01521  */
01522 
01523 /*!
01524  * @name Register MCG_ATCVL, field ATCVL[7:0] (RW)
01525  *
01526  * Values are used by Auto Trim Machine to compare and adjust Internal Reference
01527  * trim values during ATM SAR conversion.
01528  */
01529 /*@{*/
01530 #define BP_MCG_ATCVL_ATCVL   (0U)          /*!< Bit position for MCG_ATCVL_ATCVL. */
01531 #define BM_MCG_ATCVL_ATCVL   (0xFFU)       /*!< Bit mask for MCG_ATCVL_ATCVL. */
01532 #define BS_MCG_ATCVL_ATCVL   (8U)          /*!< Bit field size in bits for MCG_ATCVL_ATCVL. */
01533 
01534 /*! @brief Read current value of the MCG_ATCVL_ATCVL field. */
01535 #define BR_MCG_ATCVL_ATCVL(x) (HW_MCG_ATCVL(x).U)
01536 
01537 /*! @brief Format value for bitfield MCG_ATCVL_ATCVL. */
01538 #define BF_MCG_ATCVL_ATCVL(v) ((uint8_t)((uint8_t)(v) << BP_MCG_ATCVL_ATCVL) & BM_MCG_ATCVL_ATCVL)
01539 
01540 /*! @brief Set the ATCVL field to a new value. */
01541 #define BW_MCG_ATCVL_ATCVL(x, v) (HW_MCG_ATCVL_WR(x, v))
01542 /*@}*/
01543 
01544 /*******************************************************************************
01545  * HW_MCG_C7 - MCG Control 7 Register
01546  ******************************************************************************/
01547 
01548 /*!
01549  * @brief HW_MCG_C7 - MCG Control 7 Register (RW)
01550  *
01551  * Reset value: 0x00U
01552  */
01553 typedef union _hw_mcg_c7
01554 {
01555     uint8_t U;
01556     struct _hw_mcg_c7_bitfields
01557     {
01558         uint8_t OSCSEL : 2;            /*!< [1:0] MCG OSC Clock Select */
01559         uint8_t RESERVED0 : 6;         /*!< [7:2]  */
01560     } B;
01561 } hw_mcg_c7_t;
01562 
01563 /*!
01564  * @name Constants and macros for entire MCG_C7 register
01565  */
01566 /*@{*/
01567 #define HW_MCG_C7_ADDR(x)        ((x) + 0xCU)
01568 
01569 #define HW_MCG_C7(x)             (*(__IO hw_mcg_c7_t *) HW_MCG_C7_ADDR(x))
01570 #define HW_MCG_C7_RD(x)          (ADDRESS_READ(hw_mcg_c7_t, HW_MCG_C7_ADDR(x)))
01571 #define HW_MCG_C7_WR(x, v)       (ADDRESS_WRITE(hw_mcg_c7_t, HW_MCG_C7_ADDR(x), v))
01572 #define HW_MCG_C7_SET(x, v)      (HW_MCG_C7_WR(x, HW_MCG_C7_RD(x) |  (v)))
01573 #define HW_MCG_C7_CLR(x, v)      (HW_MCG_C7_WR(x, HW_MCG_C7_RD(x) & ~(v)))
01574 #define HW_MCG_C7_TOG(x, v)      (HW_MCG_C7_WR(x, HW_MCG_C7_RD(x) ^  (v)))
01575 /*@}*/
01576 
01577 /*
01578  * Constants & macros for individual MCG_C7 bitfields
01579  */
01580 
01581 /*!
01582  * @name Register MCG_C7, field OSCSEL[1:0] (RW)
01583  *
01584  * Selects the MCG FLL external reference clock
01585  *
01586  * Values:
01587  * - 00 - Selects Oscillator (OSCCLK0).
01588  * - 01 - Selects 32 kHz RTC Oscillator.
01589  * - 10 - Selects Oscillator (OSCCLK1).
01590  * - 11 - RESERVED
01591  */
01592 /*@{*/
01593 #define BP_MCG_C7_OSCSEL     (0U)          /*!< Bit position for MCG_C7_OSCSEL. */
01594 #define BM_MCG_C7_OSCSEL     (0x03U)       /*!< Bit mask for MCG_C7_OSCSEL. */
01595 #define BS_MCG_C7_OSCSEL     (2U)          /*!< Bit field size in bits for MCG_C7_OSCSEL. */
01596 
01597 /*! @brief Read current value of the MCG_C7_OSCSEL field. */
01598 #define BR_MCG_C7_OSCSEL(x)  (UNION_READ(hw_mcg_c7_t, HW_MCG_C7_ADDR(x), U, B.OSCSEL))
01599 
01600 /*! @brief Format value for bitfield MCG_C7_OSCSEL. */
01601 #define BF_MCG_C7_OSCSEL(v)  ((uint8_t)((uint8_t)(v) << BP_MCG_C7_OSCSEL) & BM_MCG_C7_OSCSEL)
01602 
01603 /*! @brief Set the OSCSEL field to a new value. */
01604 #define BW_MCG_C7_OSCSEL(x, v) (HW_MCG_C7_WR(x, (HW_MCG_C7_RD(x) & ~BM_MCG_C7_OSCSEL) | BF_MCG_C7_OSCSEL(v)))
01605 /*@}*/
01606 
01607 /*******************************************************************************
01608  * HW_MCG_C8 - MCG Control 8 Register
01609  ******************************************************************************/
01610 
01611 /*!
01612  * @brief HW_MCG_C8 - MCG Control 8 Register (RW)
01613  *
01614  * Reset value: 0x80U
01615  */
01616 typedef union _hw_mcg_c8
01617 {
01618     uint8_t U;
01619     struct _hw_mcg_c8_bitfields
01620     {
01621         uint8_t LOCS1 : 1;             /*!< [0] RTC Loss of Clock Status */
01622         uint8_t RESERVED0 : 4;         /*!< [4:1]  */
01623         uint8_t CME1 : 1;              /*!< [5] Clock Monitor Enable1 */
01624         uint8_t LOLRE : 1;             /*!< [6] PLL Loss of Lock Reset Enable */
01625         uint8_t LOCRE1 : 1;            /*!< [7] Loss of Clock Reset Enable */
01626     } B;
01627 } hw_mcg_c8_t;
01628 
01629 /*!
01630  * @name Constants and macros for entire MCG_C8 register
01631  */
01632 /*@{*/
01633 #define HW_MCG_C8_ADDR(x)        ((x) + 0xDU)
01634 
01635 #define HW_MCG_C8(x)             (*(__IO hw_mcg_c8_t *) HW_MCG_C8_ADDR(x))
01636 #define HW_MCG_C8_RD(x)          (ADDRESS_READ(hw_mcg_c8_t, HW_MCG_C8_ADDR(x)))
01637 #define HW_MCG_C8_WR(x, v)       (ADDRESS_WRITE(hw_mcg_c8_t, HW_MCG_C8_ADDR(x), v))
01638 #define HW_MCG_C8_SET(x, v)      (HW_MCG_C8_WR(x, HW_MCG_C8_RD(x) |  (v)))
01639 #define HW_MCG_C8_CLR(x, v)      (HW_MCG_C8_WR(x, HW_MCG_C8_RD(x) & ~(v)))
01640 #define HW_MCG_C8_TOG(x, v)      (HW_MCG_C8_WR(x, HW_MCG_C8_RD(x) ^  (v)))
01641 /*@}*/
01642 
01643 /*
01644  * Constants & macros for individual MCG_C8 bitfields
01645  */
01646 
01647 /*!
01648  * @name Register MCG_C8, field LOCS1[0] (W1C)
01649  *
01650  * This bit indicates when a loss of clock has occurred. This bit is cleared by
01651  * writing a logic 1 to it when set.
01652  *
01653  * Values:
01654  * - 0 - Loss of RTC has not occur.
01655  * - 1 - Loss of RTC has occur
01656  */
01657 /*@{*/
01658 #define BP_MCG_C8_LOCS1      (0U)          /*!< Bit position for MCG_C8_LOCS1. */
01659 #define BM_MCG_C8_LOCS1      (0x01U)       /*!< Bit mask for MCG_C8_LOCS1. */
01660 #define BS_MCG_C8_LOCS1      (1U)          /*!< Bit field size in bits for MCG_C8_LOCS1. */
01661 
01662 /*! @brief Read current value of the MCG_C8_LOCS1 field. */
01663 #define BR_MCG_C8_LOCS1(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOCS1)))
01664 
01665 /*! @brief Format value for bitfield MCG_C8_LOCS1. */
01666 #define BF_MCG_C8_LOCS1(v)   ((uint8_t)((uint8_t)(v) << BP_MCG_C8_LOCS1) & BM_MCG_C8_LOCS1)
01667 
01668 /*! @brief Set the LOCS1 field to a new value. */
01669 #define BW_MCG_C8_LOCS1(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOCS1), v))
01670 /*@}*/
01671 
01672 /*!
01673  * @name Register MCG_C8, field CME1[5] (RW)
01674  *
01675  * Enables the loss of clock monitoring circuit for the output of the RTC
01676  * external reference clock. The LOCRE1 bit will determine whether an interrupt or a
01677  * reset request is generated following a loss of RTC clock indication. The CME1
01678  * bit should be set to a logic 1 when the MCG is in an operational mode that uses
01679  * the RTC as its external reference clock or if the RTC is operational. CME1 bit
01680  * must be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
01681  * reset request may occur when in Stop mode. CME1 should also be set to a logic 0
01682  * before entering VLPR or VLPW power modes.
01683  *
01684  * Values:
01685  * - 0 - External clock monitor is disabled for RTC clock.
01686  * - 1 - External clock monitor is enabled for RTC clock.
01687  */
01688 /*@{*/
01689 #define BP_MCG_C8_CME1       (5U)          /*!< Bit position for MCG_C8_CME1. */
01690 #define BM_MCG_C8_CME1       (0x20U)       /*!< Bit mask for MCG_C8_CME1. */
01691 #define BS_MCG_C8_CME1       (1U)          /*!< Bit field size in bits for MCG_C8_CME1. */
01692 
01693 /*! @brief Read current value of the MCG_C8_CME1 field. */
01694 #define BR_MCG_C8_CME1(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_CME1)))
01695 
01696 /*! @brief Format value for bitfield MCG_C8_CME1. */
01697 #define BF_MCG_C8_CME1(v)    ((uint8_t)((uint8_t)(v) << BP_MCG_C8_CME1) & BM_MCG_C8_CME1)
01698 
01699 /*! @brief Set the CME1 field to a new value. */
01700 #define BW_MCG_C8_CME1(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_CME1), v))
01701 /*@}*/
01702 
01703 /*!
01704  * @name Register MCG_C8, field LOLRE[6] (RW)
01705  *
01706  * Determines if an interrupt or a reset request is made following a PLL loss of
01707  * lock.
01708  *
01709  * Values:
01710  * - 0 - Interrupt request is generated on a PLL loss of lock indication. The
01711  *     PLL loss of lock interrupt enable bit must also be set to generate the
01712  *     interrupt request.
01713  * - 1 - Generate a reset request on a PLL loss of lock indication.
01714  */
01715 /*@{*/
01716 #define BP_MCG_C8_LOLRE      (6U)          /*!< Bit position for MCG_C8_LOLRE. */
01717 #define BM_MCG_C8_LOLRE      (0x40U)       /*!< Bit mask for MCG_C8_LOLRE. */
01718 #define BS_MCG_C8_LOLRE      (1U)          /*!< Bit field size in bits for MCG_C8_LOLRE. */
01719 
01720 /*! @brief Read current value of the MCG_C8_LOLRE field. */
01721 #define BR_MCG_C8_LOLRE(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOLRE)))
01722 
01723 /*! @brief Format value for bitfield MCG_C8_LOLRE. */
01724 #define BF_MCG_C8_LOLRE(v)   ((uint8_t)((uint8_t)(v) << BP_MCG_C8_LOLRE) & BM_MCG_C8_LOLRE)
01725 
01726 /*! @brief Set the LOLRE field to a new value. */
01727 #define BW_MCG_C8_LOLRE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOLRE), v))
01728 /*@}*/
01729 
01730 /*!
01731  * @name Register MCG_C8, field LOCRE1[7] (RW)
01732  *
01733  * Determines if a interrupt or a reset request is made following a loss of RTC
01734  * external reference clock. The LOCRE1 only has an affect when CME1 is set.
01735  *
01736  * Values:
01737  * - 0 - Interrupt request is generated on a loss of RTC external reference
01738  *     clock.
01739  * - 1 - Generate a reset request on a loss of RTC external reference clock
01740  */
01741 /*@{*/
01742 #define BP_MCG_C8_LOCRE1     (7U)          /*!< Bit position for MCG_C8_LOCRE1. */
01743 #define BM_MCG_C8_LOCRE1     (0x80U)       /*!< Bit mask for MCG_C8_LOCRE1. */
01744 #define BS_MCG_C8_LOCRE1     (1U)          /*!< Bit field size in bits for MCG_C8_LOCRE1. */
01745 
01746 /*! @brief Read current value of the MCG_C8_LOCRE1 field. */
01747 #define BR_MCG_C8_LOCRE1(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOCRE1)))
01748 
01749 /*! @brief Format value for bitfield MCG_C8_LOCRE1. */
01750 #define BF_MCG_C8_LOCRE1(v)  ((uint8_t)((uint8_t)(v) << BP_MCG_C8_LOCRE1) & BM_MCG_C8_LOCRE1)
01751 
01752 /*! @brief Set the LOCRE1 field to a new value. */
01753 #define BW_MCG_C8_LOCRE1(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_MCG_C8_ADDR(x), BP_MCG_C8_LOCRE1), v))
01754 /*@}*/
01755 
01756 /*******************************************************************************
01757  * hw_mcg_t - module struct
01758  ******************************************************************************/
01759 /*!
01760  * @brief All MCG module registers.
01761  */
01762 #pragma pack(1)
01763 typedef struct _hw_mcg
01764 {
01765     __IO hw_mcg_c1_t C1 ;                   /*!< [0x0] MCG Control 1 Register */
01766     __IO hw_mcg_c2_t C2 ;                   /*!< [0x1] MCG Control 2 Register */
01767     __IO hw_mcg_c3_t C3 ;                   /*!< [0x2] MCG Control 3 Register */
01768     __IO hw_mcg_c4_t C4 ;                   /*!< [0x3] MCG Control 4 Register */
01769     __IO hw_mcg_c5_t C5 ;                   /*!< [0x4] MCG Control 5 Register */
01770     __IO hw_mcg_c6_t C6 ;                   /*!< [0x5] MCG Control 6 Register */
01771     __IO hw_mcg_s_t S ;                     /*!< [0x6] MCG Status Register */
01772     uint8_t _reserved0[1];
01773     __IO hw_mcg_sc_t SC ;                   /*!< [0x8] MCG Status and Control Register */
01774     uint8_t _reserved1[1];
01775     __IO hw_mcg_atcvh_t ATCVH ;             /*!< [0xA] MCG Auto Trim Compare Value High Register */
01776     __IO hw_mcg_atcvl_t ATCVL ;             /*!< [0xB] MCG Auto Trim Compare Value Low Register */
01777     __IO hw_mcg_c7_t C7 ;                   /*!< [0xC] MCG Control 7 Register */
01778     __IO hw_mcg_c8_t C8 ;                   /*!< [0xD] MCG Control 8 Register */
01779 } hw_mcg_t;
01780 #pragma pack()
01781 
01782 /*! @brief Macro to access all MCG registers. */
01783 /*! @param x MCG module instance base address. */
01784 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
01785  *     use the '&' operator, like <code>&HW_MCG(MCG_BASE)</code>. */
01786 #define HW_MCG(x)      (*(hw_mcg_t *)(x))
01787 
01788 #endif /* __HW_MCG_REGISTERS_H__ */
01789 /* EOF */