MK64F12_lptmr.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_LPTMR_REGISTERS_H__
00088 #define __HW_LPTMR_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 LPTMR
00095  *
00096  * Low Power Timer
00097  *
00098  * Registers defined in this header file:
00099  * - HW_LPTMR_CSR - Low Power Timer Control Status Register
00100  * - HW_LPTMR_PSR - Low Power Timer Prescale Register
00101  * - HW_LPTMR_CMR - Low Power Timer Compare Register
00102  * - HW_LPTMR_CNR - Low Power Timer Counter Register
00103  *
00104  * - hw_lptmr_t - Struct containing all module registers.
00105  */
00106 
00107 #define HW_LPTMR_INSTANCE_COUNT (1U) /*!< Number of instances of the LPTMR module. */
00108 
00109 /*******************************************************************************
00110  * HW_LPTMR_CSR - Low Power Timer Control Status Register
00111  ******************************************************************************/
00112 
00113 /*!
00114  * @brief HW_LPTMR_CSR - Low Power Timer Control Status Register (RW)
00115  *
00116  * Reset value: 0x00000000U
00117  */
00118 typedef union _hw_lptmr_csr
00119 {
00120     uint32_t U;
00121     struct _hw_lptmr_csr_bitfields
00122     {
00123         uint32_t TEN : 1;              /*!< [0] Timer Enable */
00124         uint32_t TMS : 1;              /*!< [1] Timer Mode Select */
00125         uint32_t TFC : 1;              /*!< [2] Timer Free-Running Counter */
00126         uint32_t TPP : 1;              /*!< [3] Timer Pin Polarity */
00127         uint32_t TPS : 2;              /*!< [5:4] Timer Pin Select */
00128         uint32_t TIE : 1;              /*!< [6] Timer Interrupt Enable */
00129         uint32_t TCF : 1;              /*!< [7] Timer Compare Flag */
00130         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
00131     } B;
00132 } hw_lptmr_csr_t;
00133 
00134 /*!
00135  * @name Constants and macros for entire LPTMR_CSR register
00136  */
00137 /*@{*/
00138 #define HW_LPTMR_CSR_ADDR(x)     ((x) + 0x0U)
00139 
00140 #define HW_LPTMR_CSR(x)          (*(__IO hw_lptmr_csr_t *) HW_LPTMR_CSR_ADDR(x))
00141 #define HW_LPTMR_CSR_RD(x)       (ADDRESS_READ(hw_lptmr_csr_t, HW_LPTMR_CSR_ADDR(x)))
00142 #define HW_LPTMR_CSR_WR(x, v)    (ADDRESS_WRITE(hw_lptmr_csr_t, HW_LPTMR_CSR_ADDR(x), v))
00143 #define HW_LPTMR_CSR_SET(x, v)   (HW_LPTMR_CSR_WR(x, HW_LPTMR_CSR_RD(x) |  (v)))
00144 #define HW_LPTMR_CSR_CLR(x, v)   (HW_LPTMR_CSR_WR(x, HW_LPTMR_CSR_RD(x) & ~(v)))
00145 #define HW_LPTMR_CSR_TOG(x, v)   (HW_LPTMR_CSR_WR(x, HW_LPTMR_CSR_RD(x) ^  (v)))
00146 /*@}*/
00147 
00148 /*
00149  * Constants & macros for individual LPTMR_CSR bitfields
00150  */
00151 
00152 /*!
00153  * @name Register LPTMR_CSR, field TEN[0] (RW)
00154  *
00155  * When TEN is clear, it resets the LPTMR internal logic, including the CNR and
00156  * TCF. When TEN is set, the LPTMR is enabled. While writing 1 to this field,
00157  * CSR[5:1] must not be altered.
00158  *
00159  * Values:
00160  * - 0 - LPTMR is disabled and internal logic is reset.
00161  * - 1 - LPTMR is enabled.
00162  */
00163 /*@{*/
00164 #define BP_LPTMR_CSR_TEN     (0U)          /*!< Bit position for LPTMR_CSR_TEN. */
00165 #define BM_LPTMR_CSR_TEN     (0x00000001U) /*!< Bit mask for LPTMR_CSR_TEN. */
00166 #define BS_LPTMR_CSR_TEN     (1U)          /*!< Bit field size in bits for LPTMR_CSR_TEN. */
00167 
00168 /*! @brief Read current value of the LPTMR_CSR_TEN field. */
00169 #define BR_LPTMR_CSR_TEN(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TEN)))
00170 
00171 /*! @brief Format value for bitfield LPTMR_CSR_TEN. */
00172 #define BF_LPTMR_CSR_TEN(v)  ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TEN) & BM_LPTMR_CSR_TEN)
00173 
00174 /*! @brief Set the TEN field to a new value. */
00175 #define BW_LPTMR_CSR_TEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TEN), v))
00176 /*@}*/
00177 
00178 /*!
00179  * @name Register LPTMR_CSR, field TMS[1] (RW)
00180  *
00181  * Configures the mode of the LPTMR. TMS must be altered only when the LPTMR is
00182  * disabled.
00183  *
00184  * Values:
00185  * - 0 - Time Counter mode.
00186  * - 1 - Pulse Counter mode.
00187  */
00188 /*@{*/
00189 #define BP_LPTMR_CSR_TMS     (1U)          /*!< Bit position for LPTMR_CSR_TMS. */
00190 #define BM_LPTMR_CSR_TMS     (0x00000002U) /*!< Bit mask for LPTMR_CSR_TMS. */
00191 #define BS_LPTMR_CSR_TMS     (1U)          /*!< Bit field size in bits for LPTMR_CSR_TMS. */
00192 
00193 /*! @brief Read current value of the LPTMR_CSR_TMS field. */
00194 #define BR_LPTMR_CSR_TMS(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TMS)))
00195 
00196 /*! @brief Format value for bitfield LPTMR_CSR_TMS. */
00197 #define BF_LPTMR_CSR_TMS(v)  ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TMS) & BM_LPTMR_CSR_TMS)
00198 
00199 /*! @brief Set the TMS field to a new value. */
00200 #define BW_LPTMR_CSR_TMS(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TMS), v))
00201 /*@}*/
00202 
00203 /*!
00204  * @name Register LPTMR_CSR, field TFC[2] (RW)
00205  *
00206  * When clear, TFC configures the CNR to reset whenever TCF is set. When set,
00207  * TFC configures the CNR to reset on overflow. TFC must be altered only when the
00208  * LPTMR is disabled.
00209  *
00210  * Values:
00211  * - 0 - CNR is reset whenever TCF is set.
00212  * - 1 - CNR is reset on overflow.
00213  */
00214 /*@{*/
00215 #define BP_LPTMR_CSR_TFC     (2U)          /*!< Bit position for LPTMR_CSR_TFC. */
00216 #define BM_LPTMR_CSR_TFC     (0x00000004U) /*!< Bit mask for LPTMR_CSR_TFC. */
00217 #define BS_LPTMR_CSR_TFC     (1U)          /*!< Bit field size in bits for LPTMR_CSR_TFC. */
00218 
00219 /*! @brief Read current value of the LPTMR_CSR_TFC field. */
00220 #define BR_LPTMR_CSR_TFC(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TFC)))
00221 
00222 /*! @brief Format value for bitfield LPTMR_CSR_TFC. */
00223 #define BF_LPTMR_CSR_TFC(v)  ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TFC) & BM_LPTMR_CSR_TFC)
00224 
00225 /*! @brief Set the TFC field to a new value. */
00226 #define BW_LPTMR_CSR_TFC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TFC), v))
00227 /*@}*/
00228 
00229 /*!
00230  * @name Register LPTMR_CSR, field TPP[3] (RW)
00231  *
00232  * Configures the polarity of the input source in Pulse Counter mode. TPP must
00233  * be changed only when the LPTMR is disabled.
00234  *
00235  * Values:
00236  * - 0 - Pulse Counter input source is active-high, and the CNR will increment
00237  *     on the rising-edge.
00238  * - 1 - Pulse Counter input source is active-low, and the CNR will increment on
00239  *     the falling-edge.
00240  */
00241 /*@{*/
00242 #define BP_LPTMR_CSR_TPP     (3U)          /*!< Bit position for LPTMR_CSR_TPP. */
00243 #define BM_LPTMR_CSR_TPP     (0x00000008U) /*!< Bit mask for LPTMR_CSR_TPP. */
00244 #define BS_LPTMR_CSR_TPP     (1U)          /*!< Bit field size in bits for LPTMR_CSR_TPP. */
00245 
00246 /*! @brief Read current value of the LPTMR_CSR_TPP field. */
00247 #define BR_LPTMR_CSR_TPP(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TPP)))
00248 
00249 /*! @brief Format value for bitfield LPTMR_CSR_TPP. */
00250 #define BF_LPTMR_CSR_TPP(v)  ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TPP) & BM_LPTMR_CSR_TPP)
00251 
00252 /*! @brief Set the TPP field to a new value. */
00253 #define BW_LPTMR_CSR_TPP(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TPP), v))
00254 /*@}*/
00255 
00256 /*!
00257  * @name Register LPTMR_CSR, field TPS[5:4] (RW)
00258  *
00259  * Configures the input source to be used in Pulse Counter mode. TPS must be
00260  * altered only when the LPTMR is disabled. The input connections vary by device.
00261  * See the chip configuration details for information on the connections to these
00262  * inputs.
00263  *
00264  * Values:
00265  * - 00 - Pulse counter input 0 is selected.
00266  * - 01 - Pulse counter input 1 is selected.
00267  * - 10 - Pulse counter input 2 is selected.
00268  * - 11 - Pulse counter input 3 is selected.
00269  */
00270 /*@{*/
00271 #define BP_LPTMR_CSR_TPS     (4U)          /*!< Bit position for LPTMR_CSR_TPS. */
00272 #define BM_LPTMR_CSR_TPS     (0x00000030U) /*!< Bit mask for LPTMR_CSR_TPS. */
00273 #define BS_LPTMR_CSR_TPS     (2U)          /*!< Bit field size in bits for LPTMR_CSR_TPS. */
00274 
00275 /*! @brief Read current value of the LPTMR_CSR_TPS field. */
00276 #define BR_LPTMR_CSR_TPS(x)  (UNION_READ(hw_lptmr_csr_t, HW_LPTMR_CSR_ADDR(x), U, B.TPS))
00277 
00278 /*! @brief Format value for bitfield LPTMR_CSR_TPS. */
00279 #define BF_LPTMR_CSR_TPS(v)  ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TPS) & BM_LPTMR_CSR_TPS)
00280 
00281 /*! @brief Set the TPS field to a new value. */
00282 #define BW_LPTMR_CSR_TPS(x, v) (HW_LPTMR_CSR_WR(x, (HW_LPTMR_CSR_RD(x) & ~BM_LPTMR_CSR_TPS) | BF_LPTMR_CSR_TPS(v)))
00283 /*@}*/
00284 
00285 /*!
00286  * @name Register LPTMR_CSR, field TIE[6] (RW)
00287  *
00288  * When TIE is set, the LPTMR Interrupt is generated whenever TCF is also set.
00289  *
00290  * Values:
00291  * - 0 - Timer interrupt disabled.
00292  * - 1 - Timer interrupt enabled.
00293  */
00294 /*@{*/
00295 #define BP_LPTMR_CSR_TIE     (6U)          /*!< Bit position for LPTMR_CSR_TIE. */
00296 #define BM_LPTMR_CSR_TIE     (0x00000040U) /*!< Bit mask for LPTMR_CSR_TIE. */
00297 #define BS_LPTMR_CSR_TIE     (1U)          /*!< Bit field size in bits for LPTMR_CSR_TIE. */
00298 
00299 /*! @brief Read current value of the LPTMR_CSR_TIE field. */
00300 #define BR_LPTMR_CSR_TIE(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TIE)))
00301 
00302 /*! @brief Format value for bitfield LPTMR_CSR_TIE. */
00303 #define BF_LPTMR_CSR_TIE(v)  ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TIE) & BM_LPTMR_CSR_TIE)
00304 
00305 /*! @brief Set the TIE field to a new value. */
00306 #define BW_LPTMR_CSR_TIE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TIE), v))
00307 /*@}*/
00308 
00309 /*!
00310  * @name Register LPTMR_CSR, field TCF[7] (W1C)
00311  *
00312  * TCF is set when the LPTMR is enabled and the CNR equals the CMR and
00313  * increments. TCF is cleared when the LPTMR is disabled or a logic 1 is written to it.
00314  *
00315  * Values:
00316  * - 0 - The value of CNR is not equal to CMR and increments.
00317  * - 1 - The value of CNR is equal to CMR and increments.
00318  */
00319 /*@{*/
00320 #define BP_LPTMR_CSR_TCF     (7U)          /*!< Bit position for LPTMR_CSR_TCF. */
00321 #define BM_LPTMR_CSR_TCF     (0x00000080U) /*!< Bit mask for LPTMR_CSR_TCF. */
00322 #define BS_LPTMR_CSR_TCF     (1U)          /*!< Bit field size in bits for LPTMR_CSR_TCF. */
00323 
00324 /*! @brief Read current value of the LPTMR_CSR_TCF field. */
00325 #define BR_LPTMR_CSR_TCF(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TCF)))
00326 
00327 /*! @brief Format value for bitfield LPTMR_CSR_TCF. */
00328 #define BF_LPTMR_CSR_TCF(v)  ((uint32_t)((uint32_t)(v) << BP_LPTMR_CSR_TCF) & BM_LPTMR_CSR_TCF)
00329 
00330 /*! @brief Set the TCF field to a new value. */
00331 #define BW_LPTMR_CSR_TCF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_LPTMR_CSR_ADDR(x), BP_LPTMR_CSR_TCF), v))
00332 /*@}*/
00333 
00334 /*******************************************************************************
00335  * HW_LPTMR_PSR - Low Power Timer Prescale Register
00336  ******************************************************************************/
00337 
00338 /*!
00339  * @brief HW_LPTMR_PSR - Low Power Timer Prescale Register (RW)
00340  *
00341  * Reset value: 0x00000000U
00342  */
00343 typedef union _hw_lptmr_psr
00344 {
00345     uint32_t U;
00346     struct _hw_lptmr_psr_bitfields
00347     {
00348         uint32_t PCS : 2;              /*!< [1:0] Prescaler Clock Select */
00349         uint32_t PBYP : 1;             /*!< [2] Prescaler Bypass */
00350         uint32_t PRESCALE : 4;         /*!< [6:3] Prescale Value */
00351         uint32_t RESERVED0 : 25;       /*!< [31:7]  */
00352     } B;
00353 } hw_lptmr_psr_t;
00354 
00355 /*!
00356  * @name Constants and macros for entire LPTMR_PSR register
00357  */
00358 /*@{*/
00359 #define HW_LPTMR_PSR_ADDR(x)     ((x) + 0x4U)
00360 
00361 #define HW_LPTMR_PSR(x)          (*(__IO hw_lptmr_psr_t *) HW_LPTMR_PSR_ADDR(x))
00362 #define HW_LPTMR_PSR_RD(x)       (ADDRESS_READ(hw_lptmr_psr_t, HW_LPTMR_PSR_ADDR(x)))
00363 #define HW_LPTMR_PSR_WR(x, v)    (ADDRESS_WRITE(hw_lptmr_psr_t, HW_LPTMR_PSR_ADDR(x), v))
00364 #define HW_LPTMR_PSR_SET(x, v)   (HW_LPTMR_PSR_WR(x, HW_LPTMR_PSR_RD(x) |  (v)))
00365 #define HW_LPTMR_PSR_CLR(x, v)   (HW_LPTMR_PSR_WR(x, HW_LPTMR_PSR_RD(x) & ~(v)))
00366 #define HW_LPTMR_PSR_TOG(x, v)   (HW_LPTMR_PSR_WR(x, HW_LPTMR_PSR_RD(x) ^  (v)))
00367 /*@}*/
00368 
00369 /*
00370  * Constants & macros for individual LPTMR_PSR bitfields
00371  */
00372 
00373 /*!
00374  * @name Register LPTMR_PSR, field PCS[1:0] (RW)
00375  *
00376  * Selects the clock to be used by the LPTMR prescaler/glitch filter. PCS must
00377  * be altered only when the LPTMR is disabled. The clock connections vary by
00378  * device. See the chip configuration details for information on the connections to
00379  * these inputs.
00380  *
00381  * Values:
00382  * - 00 - Prescaler/glitch filter clock 0 selected.
00383  * - 01 - Prescaler/glitch filter clock 1 selected.
00384  * - 10 - Prescaler/glitch filter clock 2 selected.
00385  * - 11 - Prescaler/glitch filter clock 3 selected.
00386  */
00387 /*@{*/
00388 #define BP_LPTMR_PSR_PCS     (0U)          /*!< Bit position for LPTMR_PSR_PCS. */
00389 #define BM_LPTMR_PSR_PCS     (0x00000003U) /*!< Bit mask for LPTMR_PSR_PCS. */
00390 #define BS_LPTMR_PSR_PCS     (2U)          /*!< Bit field size in bits for LPTMR_PSR_PCS. */
00391 
00392 /*! @brief Read current value of the LPTMR_PSR_PCS field. */
00393 #define BR_LPTMR_PSR_PCS(x)  (UNION_READ(hw_lptmr_psr_t, HW_LPTMR_PSR_ADDR(x), U, B.PCS))
00394 
00395 /*! @brief Format value for bitfield LPTMR_PSR_PCS. */
00396 #define BF_LPTMR_PSR_PCS(v)  ((uint32_t)((uint32_t)(v) << BP_LPTMR_PSR_PCS) & BM_LPTMR_PSR_PCS)
00397 
00398 /*! @brief Set the PCS field to a new value. */
00399 #define BW_LPTMR_PSR_PCS(x, v) (HW_LPTMR_PSR_WR(x, (HW_LPTMR_PSR_RD(x) & ~BM_LPTMR_PSR_PCS) | BF_LPTMR_PSR_PCS(v)))
00400 /*@}*/
00401 
00402 /*!
00403  * @name Register LPTMR_PSR, field PBYP[2] (RW)
00404  *
00405  * When PBYP is set, the selected prescaler clock in Time Counter mode or
00406  * selected input source in Pulse Counter mode directly clocks the CNR. When PBYP is
00407  * clear, the CNR is clocked by the output of the prescaler/glitch filter. PBYP
00408  * must be altered only when the LPTMR is disabled.
00409  *
00410  * Values:
00411  * - 0 - Prescaler/glitch filter is enabled.
00412  * - 1 - Prescaler/glitch filter is bypassed.
00413  */
00414 /*@{*/
00415 #define BP_LPTMR_PSR_PBYP    (2U)          /*!< Bit position for LPTMR_PSR_PBYP. */
00416 #define BM_LPTMR_PSR_PBYP    (0x00000004U) /*!< Bit mask for LPTMR_PSR_PBYP. */
00417 #define BS_LPTMR_PSR_PBYP    (1U)          /*!< Bit field size in bits for LPTMR_PSR_PBYP. */
00418 
00419 /*! @brief Read current value of the LPTMR_PSR_PBYP field. */
00420 #define BR_LPTMR_PSR_PBYP(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_LPTMR_PSR_ADDR(x), BP_LPTMR_PSR_PBYP)))
00421 
00422 /*! @brief Format value for bitfield LPTMR_PSR_PBYP. */
00423 #define BF_LPTMR_PSR_PBYP(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_PSR_PBYP) & BM_LPTMR_PSR_PBYP)
00424 
00425 /*! @brief Set the PBYP field to a new value. */
00426 #define BW_LPTMR_PSR_PBYP(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_LPTMR_PSR_ADDR(x), BP_LPTMR_PSR_PBYP), v))
00427 /*@}*/
00428 
00429 /*!
00430  * @name Register LPTMR_PSR, field PRESCALE[6:3] (RW)
00431  *
00432  * Configures the size of the Prescaler in Time Counter mode or width of the
00433  * glitch filter in Pulse Counter mode. PRESCALE must be altered only when the LPTMR
00434  * is disabled.
00435  *
00436  * Values:
00437  * - 0000 - Prescaler divides the prescaler clock by 2; glitch filter does not
00438  *     support this configuration.
00439  * - 0001 - Prescaler divides the prescaler clock by 4; glitch filter recognizes
00440  *     change on input pin after 2 rising clock edges.
00441  * - 0010 - Prescaler divides the prescaler clock by 8; glitch filter recognizes
00442  *     change on input pin after 4 rising clock edges.
00443  * - 0011 - Prescaler divides the prescaler clock by 16; glitch filter
00444  *     recognizes change on input pin after 8 rising clock edges.
00445  * - 0100 - Prescaler divides the prescaler clock by 32; glitch filter
00446  *     recognizes change on input pin after 16 rising clock edges.
00447  * - 0101 - Prescaler divides the prescaler clock by 64; glitch filter
00448  *     recognizes change on input pin after 32 rising clock edges.
00449  * - 0110 - Prescaler divides the prescaler clock by 128; glitch filter
00450  *     recognizes change on input pin after 64 rising clock edges.
00451  * - 0111 - Prescaler divides the prescaler clock by 256; glitch filter
00452  *     recognizes change on input pin after 128 rising clock edges.
00453  * - 1000 - Prescaler divides the prescaler clock by 512; glitch filter
00454  *     recognizes change on input pin after 256 rising clock edges.
00455  * - 1001 - Prescaler divides the prescaler clock by 1024; glitch filter
00456  *     recognizes change on input pin after 512 rising clock edges.
00457  * - 1010 - Prescaler divides the prescaler clock by 2048; glitch filter
00458  *     recognizes change on input pin after 1024 rising clock edges.
00459  * - 1011 - Prescaler divides the prescaler clock by 4096; glitch filter
00460  *     recognizes change on input pin after 2048 rising clock edges.
00461  * - 1100 - Prescaler divides the prescaler clock by 8192; glitch filter
00462  *     recognizes change on input pin after 4096 rising clock edges.
00463  * - 1101 - Prescaler divides the prescaler clock by 16,384; glitch filter
00464  *     recognizes change on input pin after 8192 rising clock edges.
00465  * - 1110 - Prescaler divides the prescaler clock by 32,768; glitch filter
00466  *     recognizes change on input pin after 16,384 rising clock edges.
00467  * - 1111 - Prescaler divides the prescaler clock by 65,536; glitch filter
00468  *     recognizes change on input pin after 32,768 rising clock edges.
00469  */
00470 /*@{*/
00471 #define BP_LPTMR_PSR_PRESCALE (3U)         /*!< Bit position for LPTMR_PSR_PRESCALE. */
00472 #define BM_LPTMR_PSR_PRESCALE (0x00000078U) /*!< Bit mask for LPTMR_PSR_PRESCALE. */
00473 #define BS_LPTMR_PSR_PRESCALE (4U)         /*!< Bit field size in bits for LPTMR_PSR_PRESCALE. */
00474 
00475 /*! @brief Read current value of the LPTMR_PSR_PRESCALE field. */
00476 #define BR_LPTMR_PSR_PRESCALE(x) (UNION_READ(hw_lptmr_psr_t, HW_LPTMR_PSR_ADDR(x), U, B.PRESCALE))
00477 
00478 /*! @brief Format value for bitfield LPTMR_PSR_PRESCALE. */
00479 #define BF_LPTMR_PSR_PRESCALE(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_PSR_PRESCALE) & BM_LPTMR_PSR_PRESCALE)
00480 
00481 /*! @brief Set the PRESCALE field to a new value. */
00482 #define BW_LPTMR_PSR_PRESCALE(x, v) (HW_LPTMR_PSR_WR(x, (HW_LPTMR_PSR_RD(x) & ~BM_LPTMR_PSR_PRESCALE) | BF_LPTMR_PSR_PRESCALE(v)))
00483 /*@}*/
00484 
00485 /*******************************************************************************
00486  * HW_LPTMR_CMR - Low Power Timer Compare Register
00487  ******************************************************************************/
00488 
00489 /*!
00490  * @brief HW_LPTMR_CMR - Low Power Timer Compare Register (RW)
00491  *
00492  * Reset value: 0x00000000U
00493  */
00494 typedef union _hw_lptmr_cmr
00495 {
00496     uint32_t U;
00497     struct _hw_lptmr_cmr_bitfields
00498     {
00499         uint32_t COMPARE : 16;         /*!< [15:0] Compare Value */
00500         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
00501     } B;
00502 } hw_lptmr_cmr_t;
00503 
00504 /*!
00505  * @name Constants and macros for entire LPTMR_CMR register
00506  */
00507 /*@{*/
00508 #define HW_LPTMR_CMR_ADDR(x)     ((x) + 0x8U)
00509 
00510 #define HW_LPTMR_CMR(x)          (*(__IO hw_lptmr_cmr_t *) HW_LPTMR_CMR_ADDR(x))
00511 #define HW_LPTMR_CMR_RD(x)       (ADDRESS_READ(hw_lptmr_cmr_t, HW_LPTMR_CMR_ADDR(x)))
00512 #define HW_LPTMR_CMR_WR(x, v)    (ADDRESS_WRITE(hw_lptmr_cmr_t, HW_LPTMR_CMR_ADDR(x), v))
00513 #define HW_LPTMR_CMR_SET(x, v)   (HW_LPTMR_CMR_WR(x, HW_LPTMR_CMR_RD(x) |  (v)))
00514 #define HW_LPTMR_CMR_CLR(x, v)   (HW_LPTMR_CMR_WR(x, HW_LPTMR_CMR_RD(x) & ~(v)))
00515 #define HW_LPTMR_CMR_TOG(x, v)   (HW_LPTMR_CMR_WR(x, HW_LPTMR_CMR_RD(x) ^  (v)))
00516 /*@}*/
00517 
00518 /*
00519  * Constants & macros for individual LPTMR_CMR bitfields
00520  */
00521 
00522 /*!
00523  * @name Register LPTMR_CMR, field COMPARE[15:0] (RW)
00524  *
00525  * When the LPTMR is enabled and the CNR equals the value in the CMR and
00526  * increments, TCF is set and the hardware trigger asserts until the next time the CNR
00527  * increments. If the CMR is 0, the hardware trigger will remain asserted until
00528  * the LPTMR is disabled. If the LPTMR is enabled, the CMR must be altered only
00529  * when TCF is set.
00530  */
00531 /*@{*/
00532 #define BP_LPTMR_CMR_COMPARE (0U)          /*!< Bit position for LPTMR_CMR_COMPARE. */
00533 #define BM_LPTMR_CMR_COMPARE (0x0000FFFFU) /*!< Bit mask for LPTMR_CMR_COMPARE. */
00534 #define BS_LPTMR_CMR_COMPARE (16U)         /*!< Bit field size in bits for LPTMR_CMR_COMPARE. */
00535 
00536 /*! @brief Read current value of the LPTMR_CMR_COMPARE field. */
00537 #define BR_LPTMR_CMR_COMPARE(x) (UNION_READ(hw_lptmr_cmr_t, HW_LPTMR_CMR_ADDR(x), U, B.COMPARE))
00538 
00539 /*! @brief Format value for bitfield LPTMR_CMR_COMPARE. */
00540 #define BF_LPTMR_CMR_COMPARE(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CMR_COMPARE) & BM_LPTMR_CMR_COMPARE)
00541 
00542 /*! @brief Set the COMPARE field to a new value. */
00543 #define BW_LPTMR_CMR_COMPARE(x, v) (HW_LPTMR_CMR_WR(x, (HW_LPTMR_CMR_RD(x) & ~BM_LPTMR_CMR_COMPARE) | BF_LPTMR_CMR_COMPARE(v)))
00544 /*@}*/
00545 
00546 /*******************************************************************************
00547  * HW_LPTMR_CNR - Low Power Timer Counter Register
00548  ******************************************************************************/
00549 
00550 /*!
00551  * @brief HW_LPTMR_CNR - Low Power Timer Counter Register (RW)
00552  *
00553  * Reset value: 0x00000000U
00554  */
00555 typedef union _hw_lptmr_cnr
00556 {
00557     uint32_t U;
00558     struct _hw_lptmr_cnr_bitfields
00559     {
00560         uint32_t COUNTER : 16;         /*!< [15:0] Counter Value */
00561         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
00562     } B;
00563 } hw_lptmr_cnr_t;
00564 
00565 /*!
00566  * @name Constants and macros for entire LPTMR_CNR register
00567  */
00568 /*@{*/
00569 #define HW_LPTMR_CNR_ADDR(x)     ((x) + 0xCU)
00570 
00571 #define HW_LPTMR_CNR(x)          (*(__IO hw_lptmr_cnr_t *) HW_LPTMR_CNR_ADDR(x))
00572 #define HW_LPTMR_CNR_RD(x)       (ADDRESS_READ(hw_lptmr_cnr_t, HW_LPTMR_CNR_ADDR(x)))
00573 #define HW_LPTMR_CNR_WR(x, v)    (ADDRESS_WRITE(hw_lptmr_cnr_t, HW_LPTMR_CNR_ADDR(x), v))
00574 #define HW_LPTMR_CNR_SET(x, v)   (HW_LPTMR_CNR_WR(x, HW_LPTMR_CNR_RD(x) |  (v)))
00575 #define HW_LPTMR_CNR_CLR(x, v)   (HW_LPTMR_CNR_WR(x, HW_LPTMR_CNR_RD(x) & ~(v)))
00576 #define HW_LPTMR_CNR_TOG(x, v)   (HW_LPTMR_CNR_WR(x, HW_LPTMR_CNR_RD(x) ^  (v)))
00577 /*@}*/
00578 
00579 /*
00580  * Constants & macros for individual LPTMR_CNR bitfields
00581  */
00582 
00583 /*!
00584  * @name Register LPTMR_CNR, field COUNTER[15:0] (RW)
00585  */
00586 /*@{*/
00587 #define BP_LPTMR_CNR_COUNTER (0U)          /*!< Bit position for LPTMR_CNR_COUNTER. */
00588 #define BM_LPTMR_CNR_COUNTER (0x0000FFFFU) /*!< Bit mask for LPTMR_CNR_COUNTER. */
00589 #define BS_LPTMR_CNR_COUNTER (16U)         /*!< Bit field size in bits for LPTMR_CNR_COUNTER. */
00590 
00591 /*! @brief Read current value of the LPTMR_CNR_COUNTER field. */
00592 #define BR_LPTMR_CNR_COUNTER(x) (UNION_READ(hw_lptmr_cnr_t, HW_LPTMR_CNR_ADDR(x), U, B.COUNTER))
00593 
00594 /*! @brief Format value for bitfield LPTMR_CNR_COUNTER. */
00595 #define BF_LPTMR_CNR_COUNTER(v) ((uint32_t)((uint32_t)(v) << BP_LPTMR_CNR_COUNTER) & BM_LPTMR_CNR_COUNTER)
00596 
00597 /*! @brief Set the COUNTER field to a new value. */
00598 #define BW_LPTMR_CNR_COUNTER(x, v) (HW_LPTMR_CNR_WR(x, (HW_LPTMR_CNR_RD(x) & ~BM_LPTMR_CNR_COUNTER) | BF_LPTMR_CNR_COUNTER(v)))
00599 /*@}*/
00600 
00601 /*******************************************************************************
00602  * hw_lptmr_t - module struct
00603  ******************************************************************************/
00604 /*!
00605  * @brief All LPTMR module registers.
00606  */
00607 #pragma pack(1)
00608 typedef struct _hw_lptmr
00609 {
00610     __IO hw_lptmr_csr_t CSR ;               /*!< [0x0] Low Power Timer Control Status Register */
00611     __IO hw_lptmr_psr_t PSR ;               /*!< [0x4] Low Power Timer Prescale Register */
00612     __IO hw_lptmr_cmr_t CMR ;               /*!< [0x8] Low Power Timer Compare Register */
00613     __IO hw_lptmr_cnr_t CNR ;               /*!< [0xC] Low Power Timer Counter Register */
00614 } hw_lptmr_t;
00615 #pragma pack()
00616 
00617 /*! @brief Macro to access all LPTMR registers. */
00618 /*! @param x LPTMR module instance base address. */
00619 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
00620  *     use the '&' operator, like <code>&HW_LPTMR(LPTMR0_BASE)</code>. */
00621 #define HW_LPTMR(x)    (*(hw_lptmr_t *)(x))
00622 
00623 #endif /* __HW_LPTMR_REGISTERS_H__ */
00624 /* EOF */