MK64F12_i2c.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_I2C_REGISTERS_H__
00088 #define __HW_I2C_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 I2C
00095  *
00096  * Inter-Integrated Circuit
00097  *
00098  * Registers defined in this header file:
00099  * - HW_I2C_A1 - I2C Address Register 1
00100  * - HW_I2C_F - I2C Frequency Divider register
00101  * - HW_I2C_C1 - I2C Control Register 1
00102  * - HW_I2C_S - I2C Status register
00103  * - HW_I2C_D - I2C Data I/O register
00104  * - HW_I2C_C2 - I2C Control Register 2
00105  * - HW_I2C_FLT - I2C Programmable Input Glitch Filter register
00106  * - HW_I2C_RA - I2C Range Address register
00107  * - HW_I2C_SMB - I2C SMBus Control and Status register
00108  * - HW_I2C_A2 - I2C Address Register 2
00109  * - HW_I2C_SLTH - I2C SCL Low Timeout Register High
00110  * - HW_I2C_SLTL - I2C SCL Low Timeout Register Low
00111  *
00112  * - hw_i2c_t - Struct containing all module registers.
00113  */
00114 
00115 #define HW_I2C_INSTANCE_COUNT (3U) /*!< Number of instances of the I2C module. */
00116 #define HW_I2C0 (0U) /*!< Instance number for I2C0. */
00117 #define HW_I2C1 (1U) /*!< Instance number for I2C1. */
00118 #define HW_I2C2 (2U) /*!< Instance number for I2C2. */
00119 
00120 /*******************************************************************************
00121  * HW_I2C_A1 - I2C Address Register 1
00122  ******************************************************************************/
00123 
00124 /*!
00125  * @brief HW_I2C_A1 - I2C Address Register 1 (RW)
00126  *
00127  * Reset value: 0x00U
00128  *
00129  * This register contains the slave address to be used by the I2C module.
00130  */
00131 typedef union _hw_i2c_a1
00132 {
00133     uint8_t U;
00134     struct _hw_i2c_a1_bitfields
00135     {
00136         uint8_t RESERVED0 : 1;         /*!< [0]  */
00137         uint8_t AD : 7;                /*!< [7:1] Address */
00138     } B;
00139 } hw_i2c_a1_t;
00140 
00141 /*!
00142  * @name Constants and macros for entire I2C_A1 register
00143  */
00144 /*@{*/
00145 #define HW_I2C_A1_ADDR(x)        ((x) + 0x0U)
00146 
00147 #define HW_I2C_A1(x)             (*(__IO hw_i2c_a1_t *) HW_I2C_A1_ADDR(x))
00148 #define HW_I2C_A1_RD(x)          (ADDRESS_READ(hw_i2c_a1_t, HW_I2C_A1_ADDR(x)))
00149 #define HW_I2C_A1_WR(x, v)       (ADDRESS_WRITE(hw_i2c_a1_t, HW_I2C_A1_ADDR(x), v))
00150 #define HW_I2C_A1_SET(x, v)      (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) |  (v)))
00151 #define HW_I2C_A1_CLR(x, v)      (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) & ~(v)))
00152 #define HW_I2C_A1_TOG(x, v)      (HW_I2C_A1_WR(x, HW_I2C_A1_RD(x) ^  (v)))
00153 /*@}*/
00154 
00155 /*
00156  * Constants & macros for individual I2C_A1 bitfields
00157  */
00158 
00159 /*!
00160  * @name Register I2C_A1, field AD[7:1] (RW)
00161  *
00162  * Contains the primary slave address used by the I2C module when it is
00163  * addressed as a slave. This field is used in the 7-bit address scheme and the lower
00164  * seven bits in the 10-bit address scheme.
00165  */
00166 /*@{*/
00167 #define BP_I2C_A1_AD         (1U)          /*!< Bit position for I2C_A1_AD. */
00168 #define BM_I2C_A1_AD         (0xFEU)       /*!< Bit mask for I2C_A1_AD. */
00169 #define BS_I2C_A1_AD         (7U)          /*!< Bit field size in bits for I2C_A1_AD. */
00170 
00171 /*! @brief Read current value of the I2C_A1_AD field. */
00172 #define BR_I2C_A1_AD(x)      (UNION_READ(hw_i2c_a1_t, HW_I2C_A1_ADDR(x), U, B.AD))
00173 
00174 /*! @brief Format value for bitfield I2C_A1_AD. */
00175 #define BF_I2C_A1_AD(v)      ((uint8_t)((uint8_t)(v) << BP_I2C_A1_AD) & BM_I2C_A1_AD)
00176 
00177 /*! @brief Set the AD field to a new value. */
00178 #define BW_I2C_A1_AD(x, v)   (HW_I2C_A1_WR(x, (HW_I2C_A1_RD(x) & ~BM_I2C_A1_AD) | BF_I2C_A1_AD(v)))
00179 /*@}*/
00180 
00181 /*******************************************************************************
00182  * HW_I2C_F - I2C Frequency Divider register
00183  ******************************************************************************/
00184 
00185 /*!
00186  * @brief HW_I2C_F - I2C Frequency Divider register (RW)
00187  *
00188  * Reset value: 0x00U
00189  */
00190 typedef union _hw_i2c_f
00191 {
00192     uint8_t U;
00193     struct _hw_i2c_f_bitfields
00194     {
00195         uint8_t ICR : 6;               /*!< [5:0] ClockRate */
00196         uint8_t MULT : 2;              /*!< [7:6] Multiplier Factor */
00197     } B;
00198 } hw_i2c_f_t;
00199 
00200 /*!
00201  * @name Constants and macros for entire I2C_F register
00202  */
00203 /*@{*/
00204 #define HW_I2C_F_ADDR(x)         ((x) + 0x1U)
00205 
00206 #define HW_I2C_F(x)              (*(__IO hw_i2c_f_t *) HW_I2C_F_ADDR(x))
00207 #define HW_I2C_F_RD(x)           (ADDRESS_READ(hw_i2c_f_t, HW_I2C_F_ADDR(x)))
00208 #define HW_I2C_F_WR(x, v)        (ADDRESS_WRITE(hw_i2c_f_t, HW_I2C_F_ADDR(x), v))
00209 #define HW_I2C_F_SET(x, v)       (HW_I2C_F_WR(x, HW_I2C_F_RD(x) |  (v)))
00210 #define HW_I2C_F_CLR(x, v)       (HW_I2C_F_WR(x, HW_I2C_F_RD(x) & ~(v)))
00211 #define HW_I2C_F_TOG(x, v)       (HW_I2C_F_WR(x, HW_I2C_F_RD(x) ^  (v)))
00212 /*@}*/
00213 
00214 /*
00215  * Constants & macros for individual I2C_F bitfields
00216  */
00217 
00218 /*!
00219  * @name Register I2C_F, field ICR[5:0] (RW)
00220  *
00221  * Prescales the I2C module clock for bit rate selection. This field and the
00222  * MULT field determine the I2C baud rate, the SDA hold time, the SCL start hold
00223  * time, and the SCL stop hold time. For a list of values corresponding to each ICR
00224  * setting, see I2C divider and hold values. The SCL divider multiplied by
00225  * multiplier factor (mul) determines the I2C baud rate. I2C baud rate = I2C module
00226  * clock speed (Hz)/(mul * SCL divider) The SDA hold time is the delay from the
00227  * falling edge of SCL (I2C clock) to the changing of SDA (I2C data). SDA hold time =
00228  * I2C module clock period (s) * mul * SDA hold value The SCL start hold time is
00229  * the delay from the falling edge of SDA (I2C data) while SCL is high (start
00230  * condition) to the falling edge of SCL (I2C clock). SCL start hold time = I2C
00231  * module clock period (s) * mul * SCL start hold value The SCL stop hold time is
00232  * the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C
00233  * data) while SCL is high (stop condition). SCL stop hold time = I2C module
00234  * clock period (s) * mul * SCL stop hold value For example, if the I2C module clock
00235  * speed is 8 MHz, the following table shows the possible hold time values with
00236  * different ICR and MULT selections to achieve an I2C baud rate of 100 kbit/s.
00237  * MULT ICR Hold times (us) SDA SCL Start SCL Stop 2h 00h 3.500 3.000 5.500 1h 07h
00238  * 2.500 4.000 5.250 1h 0Bh 2.250 4.000 5.250 0h 14h 2.125 4.250 5.125 0h 18h
00239  * 1.125 4.750 5.125
00240  */
00241 /*@{*/
00242 #define BP_I2C_F_ICR         (0U)          /*!< Bit position for I2C_F_ICR. */
00243 #define BM_I2C_F_ICR         (0x3FU)       /*!< Bit mask for I2C_F_ICR. */
00244 #define BS_I2C_F_ICR         (6U)          /*!< Bit field size in bits for I2C_F_ICR. */
00245 
00246 /*! @brief Read current value of the I2C_F_ICR field. */
00247 #define BR_I2C_F_ICR(x)      (UNION_READ(hw_i2c_f_t, HW_I2C_F_ADDR(x), U, B.ICR))
00248 
00249 /*! @brief Format value for bitfield I2C_F_ICR. */
00250 #define BF_I2C_F_ICR(v)      ((uint8_t)((uint8_t)(v) << BP_I2C_F_ICR) & BM_I2C_F_ICR)
00251 
00252 /*! @brief Set the ICR field to a new value. */
00253 #define BW_I2C_F_ICR(x, v)   (HW_I2C_F_WR(x, (HW_I2C_F_RD(x) & ~BM_I2C_F_ICR) | BF_I2C_F_ICR(v)))
00254 /*@}*/
00255 
00256 /*!
00257  * @name Register I2C_F, field MULT[7:6] (RW)
00258  *
00259  * Defines the multiplier factor (mul). This factor is used along with the SCL
00260  * divider to generate the I2C baud rate.
00261  *
00262  * Values:
00263  * - 00 - mul = 1
00264  * - 01 - mul = 2
00265  * - 10 - mul = 4
00266  * - 11 - Reserved
00267  */
00268 /*@{*/
00269 #define BP_I2C_F_MULT        (6U)          /*!< Bit position for I2C_F_MULT. */
00270 #define BM_I2C_F_MULT        (0xC0U)       /*!< Bit mask for I2C_F_MULT. */
00271 #define BS_I2C_F_MULT        (2U)          /*!< Bit field size in bits for I2C_F_MULT. */
00272 
00273 /*! @brief Read current value of the I2C_F_MULT field. */
00274 #define BR_I2C_F_MULT(x)     (UNION_READ(hw_i2c_f_t, HW_I2C_F_ADDR(x), U, B.MULT))
00275 
00276 /*! @brief Format value for bitfield I2C_F_MULT. */
00277 #define BF_I2C_F_MULT(v)     ((uint8_t)((uint8_t)(v) << BP_I2C_F_MULT) & BM_I2C_F_MULT)
00278 
00279 /*! @brief Set the MULT field to a new value. */
00280 #define BW_I2C_F_MULT(x, v)  (HW_I2C_F_WR(x, (HW_I2C_F_RD(x) & ~BM_I2C_F_MULT) | BF_I2C_F_MULT(v)))
00281 /*@}*/
00282 
00283 /*******************************************************************************
00284  * HW_I2C_C1 - I2C Control Register 1
00285  ******************************************************************************/
00286 
00287 /*!
00288  * @brief HW_I2C_C1 - I2C Control Register 1 (RW)
00289  *
00290  * Reset value: 0x00U
00291  */
00292 typedef union _hw_i2c_c1
00293 {
00294     uint8_t U;
00295     struct _hw_i2c_c1_bitfields
00296     {
00297         uint8_t DMAEN : 1;             /*!< [0] DMA Enable */
00298         uint8_t WUEN : 1;              /*!< [1] Wakeup Enable */
00299         uint8_t RSTA : 1;              /*!< [2] Repeat START */
00300         uint8_t TXAK : 1;              /*!< [3] Transmit Acknowledge Enable */
00301         uint8_t TX : 1;                /*!< [4] Transmit Mode Select */
00302         uint8_t MST : 1;               /*!< [5] Master Mode Select */
00303         uint8_t IICIE : 1;             /*!< [6] I2C Interrupt Enable */
00304         uint8_t IICEN : 1;             /*!< [7] I2C Enable */
00305     } B;
00306 } hw_i2c_c1_t;
00307 
00308 /*!
00309  * @name Constants and macros for entire I2C_C1 register
00310  */
00311 /*@{*/
00312 #define HW_I2C_C1_ADDR(x)        ((x) + 0x2U)
00313 
00314 #define HW_I2C_C1(x)             (*(__IO hw_i2c_c1_t *) HW_I2C_C1_ADDR(x))
00315 #define HW_I2C_C1_RD(x)          (ADDRESS_READ(hw_i2c_c1_t, HW_I2C_C1_ADDR(x)))
00316 #define HW_I2C_C1_WR(x, v)       (ADDRESS_WRITE(hw_i2c_c1_t, HW_I2C_C1_ADDR(x), v))
00317 #define HW_I2C_C1_SET(x, v)      (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) |  (v)))
00318 #define HW_I2C_C1_CLR(x, v)      (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) & ~(v)))
00319 #define HW_I2C_C1_TOG(x, v)      (HW_I2C_C1_WR(x, HW_I2C_C1_RD(x) ^  (v)))
00320 /*@}*/
00321 
00322 /*
00323  * Constants & macros for individual I2C_C1 bitfields
00324  */
00325 
00326 /*!
00327  * @name Register I2C_C1, field DMAEN[0] (RW)
00328  *
00329  * Enables or disables the DMA function.
00330  *
00331  * Values:
00332  * - 0 - All DMA signalling disabled.
00333  * - 1 - DMA transfer is enabled. While SMB[FACK] = 0, the following conditions
00334  *     trigger the DMA request: a data byte is received, and either address or
00335  *     data is transmitted. (ACK/NACK is automatic) the first byte received matches
00336  *     the A1 register or is a general call address. If any address matching
00337  *     occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known
00338  *     from master to slave, then it is not required to check S[SRW]. With this
00339  *     assumption, DMA can also be used in this case. In other cases, if the master
00340  *     reads data from the slave, then it is required to rewrite the C1 register
00341  *     operation. With this assumption, DMA cannot be used. When FACK = 1, an
00342  *     address or a data byte is transmitted.
00343  */
00344 /*@{*/
00345 #define BP_I2C_C1_DMAEN      (0U)          /*!< Bit position for I2C_C1_DMAEN. */
00346 #define BM_I2C_C1_DMAEN      (0x01U)       /*!< Bit mask for I2C_C1_DMAEN. */
00347 #define BS_I2C_C1_DMAEN      (1U)          /*!< Bit field size in bits for I2C_C1_DMAEN. */
00348 
00349 /*! @brief Read current value of the I2C_C1_DMAEN field. */
00350 #define BR_I2C_C1_DMAEN(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_DMAEN)))
00351 
00352 /*! @brief Format value for bitfield I2C_C1_DMAEN. */
00353 #define BF_I2C_C1_DMAEN(v)   ((uint8_t)((uint8_t)(v) << BP_I2C_C1_DMAEN) & BM_I2C_C1_DMAEN)
00354 
00355 /*! @brief Set the DMAEN field to a new value. */
00356 #define BW_I2C_C1_DMAEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_DMAEN), v))
00357 /*@}*/
00358 
00359 /*!
00360  * @name Register I2C_C1, field WUEN[1] (RW)
00361  *
00362  * The I2C module can wake the MCU from low power mode with no peripheral bus
00363  * running when slave address matching occurs.
00364  *
00365  * Values:
00366  * - 0 - Normal operation. No interrupt generated when address matching in low
00367  *     power mode.
00368  * - 1 - Enables the wakeup function in low power mode.
00369  */
00370 /*@{*/
00371 #define BP_I2C_C1_WUEN       (1U)          /*!< Bit position for I2C_C1_WUEN. */
00372 #define BM_I2C_C1_WUEN       (0x02U)       /*!< Bit mask for I2C_C1_WUEN. */
00373 #define BS_I2C_C1_WUEN       (1U)          /*!< Bit field size in bits for I2C_C1_WUEN. */
00374 
00375 /*! @brief Read current value of the I2C_C1_WUEN field. */
00376 #define BR_I2C_C1_WUEN(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_WUEN)))
00377 
00378 /*! @brief Format value for bitfield I2C_C1_WUEN. */
00379 #define BF_I2C_C1_WUEN(v)    ((uint8_t)((uint8_t)(v) << BP_I2C_C1_WUEN) & BM_I2C_C1_WUEN)
00380 
00381 /*! @brief Set the WUEN field to a new value. */
00382 #define BW_I2C_C1_WUEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_WUEN), v))
00383 /*@}*/
00384 
00385 /*!
00386  * @name Register I2C_C1, field RSTA[2] (WORZ)
00387  *
00388  * Writing 1 to this bit generates a repeated START condition provided it is the
00389  * current master. This bit will always be read as 0. Attempting a repeat at the
00390  * wrong time results in loss of arbitration.
00391  */
00392 /*@{*/
00393 #define BP_I2C_C1_RSTA       (2U)          /*!< Bit position for I2C_C1_RSTA. */
00394 #define BM_I2C_C1_RSTA       (0x04U)       /*!< Bit mask for I2C_C1_RSTA. */
00395 #define BS_I2C_C1_RSTA       (1U)          /*!< Bit field size in bits for I2C_C1_RSTA. */
00396 
00397 /*! @brief Format value for bitfield I2C_C1_RSTA. */
00398 #define BF_I2C_C1_RSTA(v)    ((uint8_t)((uint8_t)(v) << BP_I2C_C1_RSTA) & BM_I2C_C1_RSTA)
00399 
00400 /*! @brief Set the RSTA field to a new value. */
00401 #define BW_I2C_C1_RSTA(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_RSTA), v))
00402 /*@}*/
00403 
00404 /*!
00405  * @name Register I2C_C1, field TXAK[3] (RW)
00406  *
00407  * Specifies the value driven onto the SDA during data acknowledge cycles for
00408  * both master and slave receivers. The value of SMB[FACK] affects NACK/ACK
00409  * generation. SCL is held low until TXAK is written.
00410  *
00411  * Values:
00412  * - 0 - An acknowledge signal is sent to the bus on the following receiving
00413  *     byte (if FACK is cleared) or the current receiving byte (if FACK is set).
00414  * - 1 - No acknowledge signal is sent to the bus on the following receiving
00415  *     data byte (if FACK is cleared) or the current receiving data byte (if FACK is
00416  *     set).
00417  */
00418 /*@{*/
00419 #define BP_I2C_C1_TXAK       (3U)          /*!< Bit position for I2C_C1_TXAK. */
00420 #define BM_I2C_C1_TXAK       (0x08U)       /*!< Bit mask for I2C_C1_TXAK. */
00421 #define BS_I2C_C1_TXAK       (1U)          /*!< Bit field size in bits for I2C_C1_TXAK. */
00422 
00423 /*! @brief Read current value of the I2C_C1_TXAK field. */
00424 #define BR_I2C_C1_TXAK(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TXAK)))
00425 
00426 /*! @brief Format value for bitfield I2C_C1_TXAK. */
00427 #define BF_I2C_C1_TXAK(v)    ((uint8_t)((uint8_t)(v) << BP_I2C_C1_TXAK) & BM_I2C_C1_TXAK)
00428 
00429 /*! @brief Set the TXAK field to a new value. */
00430 #define BW_I2C_C1_TXAK(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TXAK), v))
00431 /*@}*/
00432 
00433 /*!
00434  * @name Register I2C_C1, field TX[4] (RW)
00435  *
00436  * Selects the direction of master and slave transfers. In master mode this bit
00437  * must be set according to the type of transfer required. Therefore, for address
00438  * cycles, this bit is always set. When addressed as a slave this bit must be
00439  * set by software according to the SRW bit in the status register.
00440  *
00441  * Values:
00442  * - 0 - Receive
00443  * - 1 - Transmit
00444  */
00445 /*@{*/
00446 #define BP_I2C_C1_TX         (4U)          /*!< Bit position for I2C_C1_TX. */
00447 #define BM_I2C_C1_TX         (0x10U)       /*!< Bit mask for I2C_C1_TX. */
00448 #define BS_I2C_C1_TX         (1U)          /*!< Bit field size in bits for I2C_C1_TX. */
00449 
00450 /*! @brief Read current value of the I2C_C1_TX field. */
00451 #define BR_I2C_C1_TX(x)      (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TX)))
00452 
00453 /*! @brief Format value for bitfield I2C_C1_TX. */
00454 #define BF_I2C_C1_TX(v)      ((uint8_t)((uint8_t)(v) << BP_I2C_C1_TX) & BM_I2C_C1_TX)
00455 
00456 /*! @brief Set the TX field to a new value. */
00457 #define BW_I2C_C1_TX(x, v)   (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_TX), v))
00458 /*@}*/
00459 
00460 /*!
00461  * @name Register I2C_C1, field MST[5] (RW)
00462  *
00463  * When MST is changed from 0 to 1, a START signal is generated on the bus and
00464  * master mode is selected. When this bit changes from 1 to 0, a STOP signal is
00465  * generated and the mode of operation changes from master to slave.
00466  *
00467  * Values:
00468  * - 0 - Slave mode
00469  * - 1 - Master mode
00470  */
00471 /*@{*/
00472 #define BP_I2C_C1_MST        (5U)          /*!< Bit position for I2C_C1_MST. */
00473 #define BM_I2C_C1_MST        (0x20U)       /*!< Bit mask for I2C_C1_MST. */
00474 #define BS_I2C_C1_MST        (1U)          /*!< Bit field size in bits for I2C_C1_MST. */
00475 
00476 /*! @brief Read current value of the I2C_C1_MST field. */
00477 #define BR_I2C_C1_MST(x)     (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_MST)))
00478 
00479 /*! @brief Format value for bitfield I2C_C1_MST. */
00480 #define BF_I2C_C1_MST(v)     ((uint8_t)((uint8_t)(v) << BP_I2C_C1_MST) & BM_I2C_C1_MST)
00481 
00482 /*! @brief Set the MST field to a new value. */
00483 #define BW_I2C_C1_MST(x, v)  (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_MST), v))
00484 /*@}*/
00485 
00486 /*!
00487  * @name Register I2C_C1, field IICIE[6] (RW)
00488  *
00489  * Enables I2C interrupt requests.
00490  *
00491  * Values:
00492  * - 0 - Disabled
00493  * - 1 - Enabled
00494  */
00495 /*@{*/
00496 #define BP_I2C_C1_IICIE      (6U)          /*!< Bit position for I2C_C1_IICIE. */
00497 #define BM_I2C_C1_IICIE      (0x40U)       /*!< Bit mask for I2C_C1_IICIE. */
00498 #define BS_I2C_C1_IICIE      (1U)          /*!< Bit field size in bits for I2C_C1_IICIE. */
00499 
00500 /*! @brief Read current value of the I2C_C1_IICIE field. */
00501 #define BR_I2C_C1_IICIE(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICIE)))
00502 
00503 /*! @brief Format value for bitfield I2C_C1_IICIE. */
00504 #define BF_I2C_C1_IICIE(v)   ((uint8_t)((uint8_t)(v) << BP_I2C_C1_IICIE) & BM_I2C_C1_IICIE)
00505 
00506 /*! @brief Set the IICIE field to a new value. */
00507 #define BW_I2C_C1_IICIE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICIE), v))
00508 /*@}*/
00509 
00510 /*!
00511  * @name Register I2C_C1, field IICEN[7] (RW)
00512  *
00513  * Enables I2C module operation.
00514  *
00515  * Values:
00516  * - 0 - Disabled
00517  * - 1 - Enabled
00518  */
00519 /*@{*/
00520 #define BP_I2C_C1_IICEN      (7U)          /*!< Bit position for I2C_C1_IICEN. */
00521 #define BM_I2C_C1_IICEN      (0x80U)       /*!< Bit mask for I2C_C1_IICEN. */
00522 #define BS_I2C_C1_IICEN      (1U)          /*!< Bit field size in bits for I2C_C1_IICEN. */
00523 
00524 /*! @brief Read current value of the I2C_C1_IICEN field. */
00525 #define BR_I2C_C1_IICEN(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICEN)))
00526 
00527 /*! @brief Format value for bitfield I2C_C1_IICEN. */
00528 #define BF_I2C_C1_IICEN(v)   ((uint8_t)((uint8_t)(v) << BP_I2C_C1_IICEN) & BM_I2C_C1_IICEN)
00529 
00530 /*! @brief Set the IICEN field to a new value. */
00531 #define BW_I2C_C1_IICEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_I2C_C1_ADDR(x), BP_I2C_C1_IICEN), v))
00532 /*@}*/
00533 
00534 /*******************************************************************************
00535  * HW_I2C_S - I2C Status register
00536  ******************************************************************************/
00537 
00538 /*!
00539  * @brief HW_I2C_S - I2C Status register (RW)
00540  *
00541  * Reset value: 0x80U
00542  */
00543 typedef union _hw_i2c_s
00544 {
00545     uint8_t U;
00546     struct _hw_i2c_s_bitfields
00547     {
00548         uint8_t RXAK : 1;              /*!< [0] Receive Acknowledge */
00549         uint8_t IICIF : 1;             /*!< [1] Interrupt Flag */
00550         uint8_t SRW : 1;               /*!< [2] Slave Read/Write */
00551         uint8_t RAM : 1;               /*!< [3] Range Address Match */
00552         uint8_t ARBL : 1;              /*!< [4] Arbitration Lost */
00553         uint8_t BUSY : 1;              /*!< [5] Bus Busy */
00554         uint8_t IAAS : 1;              /*!< [6] Addressed As A Slave */
00555         uint8_t TCF : 1;               /*!< [7] Transfer Complete Flag */
00556     } B;
00557 } hw_i2c_s_t;
00558 
00559 /*!
00560  * @name Constants and macros for entire I2C_S register
00561  */
00562 /*@{*/
00563 #define HW_I2C_S_ADDR(x)         ((x) + 0x3U)
00564 
00565 #define HW_I2C_S(x)              (*(__IO hw_i2c_s_t *) HW_I2C_S_ADDR(x))
00566 #define HW_I2C_S_RD(x)           (ADDRESS_READ(hw_i2c_s_t, HW_I2C_S_ADDR(x)))
00567 #define HW_I2C_S_WR(x, v)        (ADDRESS_WRITE(hw_i2c_s_t, HW_I2C_S_ADDR(x), v))
00568 #define HW_I2C_S_SET(x, v)       (HW_I2C_S_WR(x, HW_I2C_S_RD(x) |  (v)))
00569 #define HW_I2C_S_CLR(x, v)       (HW_I2C_S_WR(x, HW_I2C_S_RD(x) & ~(v)))
00570 #define HW_I2C_S_TOG(x, v)       (HW_I2C_S_WR(x, HW_I2C_S_RD(x) ^  (v)))
00571 /*@}*/
00572 
00573 /*
00574  * Constants & macros for individual I2C_S bitfields
00575  */
00576 
00577 /*!
00578  * @name Register I2C_S, field RXAK[0] (RO)
00579  *
00580  * Values:
00581  * - 0 - Acknowledge signal was received after the completion of one byte of
00582  *     data transmission on the bus
00583  * - 1 - No acknowledge signal detected
00584  */
00585 /*@{*/
00586 #define BP_I2C_S_RXAK        (0U)          /*!< Bit position for I2C_S_RXAK. */
00587 #define BM_I2C_S_RXAK        (0x01U)       /*!< Bit mask for I2C_S_RXAK. */
00588 #define BS_I2C_S_RXAK        (1U)          /*!< Bit field size in bits for I2C_S_RXAK. */
00589 
00590 /*! @brief Read current value of the I2C_S_RXAK field. */
00591 #define BR_I2C_S_RXAK(x)     (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RXAK)))
00592 /*@}*/
00593 
00594 /*!
00595  * @name Register I2C_S, field IICIF[1] (W1C)
00596  *
00597  * This bit sets when an interrupt is pending. This bit must be cleared by
00598  * software by writing 1 to it, such as in the interrupt routine. One of the following
00599  * events can set this bit: One byte transfer, including ACK/NACK bit, completes
00600  * if FACK is 0. An ACK or NACK is sent on the bus by writing 0 or 1 to TXAK
00601  * after this bit is set in receive mode. One byte transfer, excluding ACK/NACK bit,
00602  * completes if FACK is 1. Match of slave address to calling address including
00603  * primary slave address, range slave address , alert response address, second
00604  * slave address, or general call address. Arbitration lost In SMBus mode, any
00605  * timeouts except SCL and SDA high timeouts I2C bus stop or start detection if the
00606  * SSIE bit in the Input Glitch Filter register is 1 To clear the I2C bus stop or
00607  * start detection interrupt: In the interrupt service routine, first clear the
00608  * STOPF or STARTF bit in the Input Glitch Filter register by writing 1 to it, and
00609  * then clear the IICIF bit. If this sequence is reversed, the IICIF bit is
00610  * asserted again.
00611  *
00612  * Values:
00613  * - 0 - No interrupt pending
00614  * - 1 - Interrupt pending
00615  */
00616 /*@{*/
00617 #define BP_I2C_S_IICIF       (1U)          /*!< Bit position for I2C_S_IICIF. */
00618 #define BM_I2C_S_IICIF       (0x02U)       /*!< Bit mask for I2C_S_IICIF. */
00619 #define BS_I2C_S_IICIF       (1U)          /*!< Bit field size in bits for I2C_S_IICIF. */
00620 
00621 /*! @brief Read current value of the I2C_S_IICIF field. */
00622 #define BR_I2C_S_IICIF(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IICIF)))
00623 
00624 /*! @brief Format value for bitfield I2C_S_IICIF. */
00625 #define BF_I2C_S_IICIF(v)    ((uint8_t)((uint8_t)(v) << BP_I2C_S_IICIF) & BM_I2C_S_IICIF)
00626 
00627 /*! @brief Set the IICIF field to a new value. */
00628 #define BW_I2C_S_IICIF(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IICIF), v))
00629 /*@}*/
00630 
00631 /*!
00632  * @name Register I2C_S, field SRW[2] (RO)
00633  *
00634  * When addressed as a slave, SRW indicates the value of the R/W command bit of
00635  * the calling address sent to the master.
00636  *
00637  * Values:
00638  * - 0 - Slave receive, master writing to slave
00639  * - 1 - Slave transmit, master reading from slave
00640  */
00641 /*@{*/
00642 #define BP_I2C_S_SRW         (2U)          /*!< Bit position for I2C_S_SRW. */
00643 #define BM_I2C_S_SRW         (0x04U)       /*!< Bit mask for I2C_S_SRW. */
00644 #define BS_I2C_S_SRW         (1U)          /*!< Bit field size in bits for I2C_S_SRW. */
00645 
00646 /*! @brief Read current value of the I2C_S_SRW field. */
00647 #define BR_I2C_S_SRW(x)      (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_S_ADDR(x), BP_I2C_S_SRW)))
00648 /*@}*/
00649 
00650 /*!
00651  * @name Register I2C_S, field RAM[3] (RW)
00652  *
00653  * This bit is set to 1 by any of the following conditions, if I2C_C2[RMEN] = 1:
00654  * Any nonzero calling address is received that matches the address in the RA
00655  * register. The calling address is within the range of values of the A1 and RA
00656  * registers. For the RAM bit to be set to 1 correctly, C1[IICIE] must be set to 1.
00657  * Writing the C1 register with any value clears this bit to 0.
00658  *
00659  * Values:
00660  * - 0 - Not addressed
00661  * - 1 - Addressed as a slave
00662  */
00663 /*@{*/
00664 #define BP_I2C_S_RAM         (3U)          /*!< Bit position for I2C_S_RAM. */
00665 #define BM_I2C_S_RAM         (0x08U)       /*!< Bit mask for I2C_S_RAM. */
00666 #define BS_I2C_S_RAM         (1U)          /*!< Bit field size in bits for I2C_S_RAM. */
00667 
00668 /*! @brief Read current value of the I2C_S_RAM field. */
00669 #define BR_I2C_S_RAM(x)      (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RAM)))
00670 
00671 /*! @brief Format value for bitfield I2C_S_RAM. */
00672 #define BF_I2C_S_RAM(v)      ((uint8_t)((uint8_t)(v) << BP_I2C_S_RAM) & BM_I2C_S_RAM)
00673 
00674 /*! @brief Set the RAM field to a new value. */
00675 #define BW_I2C_S_RAM(x, v)   (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_I2C_S_ADDR(x), BP_I2C_S_RAM), v))
00676 /*@}*/
00677 
00678 /*!
00679  * @name Register I2C_S, field ARBL[4] (W1C)
00680  *
00681  * This bit is set by hardware when the arbitration procedure is lost. The ARBL
00682  * bit must be cleared by software, by writing 1 to it.
00683  *
00684  * Values:
00685  * - 0 - Standard bus operation.
00686  * - 1 - Loss of arbitration.
00687  */
00688 /*@{*/
00689 #define BP_I2C_S_ARBL        (4U)          /*!< Bit position for I2C_S_ARBL. */
00690 #define BM_I2C_S_ARBL        (0x10U)       /*!< Bit mask for I2C_S_ARBL. */
00691 #define BS_I2C_S_ARBL        (1U)          /*!< Bit field size in bits for I2C_S_ARBL. */
00692 
00693 /*! @brief Read current value of the I2C_S_ARBL field. */
00694 #define BR_I2C_S_ARBL(x)     (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_S_ADDR(x), BP_I2C_S_ARBL)))
00695 
00696 /*! @brief Format value for bitfield I2C_S_ARBL. */
00697 #define BF_I2C_S_ARBL(v)     ((uint8_t)((uint8_t)(v) << BP_I2C_S_ARBL) & BM_I2C_S_ARBL)
00698 
00699 /*! @brief Set the ARBL field to a new value. */
00700 #define BW_I2C_S_ARBL(x, v)  (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_I2C_S_ADDR(x), BP_I2C_S_ARBL), v))
00701 /*@}*/
00702 
00703 /*!
00704  * @name Register I2C_S, field BUSY[5] (RO)
00705  *
00706  * Indicates the status of the bus regardless of slave or master mode. This bit
00707  * is set when a START signal is detected and cleared when a STOP signal is
00708  * detected.
00709  *
00710  * Values:
00711  * - 0 - Bus is idle
00712  * - 1 - Bus is busy
00713  */
00714 /*@{*/
00715 #define BP_I2C_S_BUSY        (5U)          /*!< Bit position for I2C_S_BUSY. */
00716 #define BM_I2C_S_BUSY        (0x20U)       /*!< Bit mask for I2C_S_BUSY. */
00717 #define BS_I2C_S_BUSY        (1U)          /*!< Bit field size in bits for I2C_S_BUSY. */
00718 
00719 /*! @brief Read current value of the I2C_S_BUSY field. */
00720 #define BR_I2C_S_BUSY(x)     (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_S_ADDR(x), BP_I2C_S_BUSY)))
00721 /*@}*/
00722 
00723 /*!
00724  * @name Register I2C_S, field IAAS[6] (RW)
00725  *
00726  * This bit is set by one of the following conditions: The calling address
00727  * matches the programmed primary slave address in the A1 register, or matches the
00728  * range address in the RA register (which must be set to a nonzero value and under
00729  * the condition I2C_C2[RMEN] = 1). C2[GCAEN] is set and a general call is
00730  * received. SMB[SIICAEN] is set and the calling address matches the second programmed
00731  * slave address. ALERTEN is set and an SMBus alert response address is received
00732  * RMEN is set and an address is received that is within the range between the
00733  * values of the A1 and RA registers. IAAS sets before the ACK bit. The CPU must
00734  * check the SRW bit and set TX/RX accordingly. Writing the C1 register with any
00735  * value clears this bit.
00736  *
00737  * Values:
00738  * - 0 - Not addressed
00739  * - 1 - Addressed as a slave
00740  */
00741 /*@{*/
00742 #define BP_I2C_S_IAAS        (6U)          /*!< Bit position for I2C_S_IAAS. */
00743 #define BM_I2C_S_IAAS        (0x40U)       /*!< Bit mask for I2C_S_IAAS. */
00744 #define BS_I2C_S_IAAS        (1U)          /*!< Bit field size in bits for I2C_S_IAAS. */
00745 
00746 /*! @brief Read current value of the I2C_S_IAAS field. */
00747 #define BR_I2C_S_IAAS(x)     (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IAAS)))
00748 
00749 /*! @brief Format value for bitfield I2C_S_IAAS. */
00750 #define BF_I2C_S_IAAS(v)     ((uint8_t)((uint8_t)(v) << BP_I2C_S_IAAS) & BM_I2C_S_IAAS)
00751 
00752 /*! @brief Set the IAAS field to a new value. */
00753 #define BW_I2C_S_IAAS(x, v)  (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_I2C_S_ADDR(x), BP_I2C_S_IAAS), v))
00754 /*@}*/
00755 
00756 /*!
00757  * @name Register I2C_S, field TCF[7] (RO)
00758  *
00759  * Acknowledges a byte transfer; TCF sets on the completion of a byte transfer.
00760  * This bit is valid only during or immediately following a transfer to or from
00761  * the I2C module. TCF is cleared by reading the I2C data register in receive mode
00762  * or by writing to the I2C data register in transmit mode.
00763  *
00764  * Values:
00765  * - 0 - Transfer in progress
00766  * - 1 - Transfer complete
00767  */
00768 /*@{*/
00769 #define BP_I2C_S_TCF         (7U)          /*!< Bit position for I2C_S_TCF. */
00770 #define BM_I2C_S_TCF         (0x80U)       /*!< Bit mask for I2C_S_TCF. */
00771 #define BS_I2C_S_TCF         (1U)          /*!< Bit field size in bits for I2C_S_TCF. */
00772 
00773 /*! @brief Read current value of the I2C_S_TCF field. */
00774 #define BR_I2C_S_TCF(x)      (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_S_ADDR(x), BP_I2C_S_TCF)))
00775 /*@}*/
00776 
00777 /*******************************************************************************
00778  * HW_I2C_D - I2C Data I/O register
00779  ******************************************************************************/
00780 
00781 /*!
00782  * @brief HW_I2C_D - I2C Data I/O register (RW)
00783  *
00784  * Reset value: 0x00U
00785  */
00786 typedef union _hw_i2c_d
00787 {
00788     uint8_t U;
00789     struct _hw_i2c_d_bitfields
00790     {
00791         uint8_t DATA : 8;              /*!< [7:0] Data */
00792     } B;
00793 } hw_i2c_d_t;
00794 
00795 /*!
00796  * @name Constants and macros for entire I2C_D register
00797  */
00798 /*@{*/
00799 #define HW_I2C_D_ADDR(x)         ((x) + 0x4U)
00800 
00801 #define HW_I2C_D(x)              (*(__IO hw_i2c_d_t *) HW_I2C_D_ADDR(x))
00802 #define HW_I2C_D_RD(x)           (ADDRESS_READ(hw_i2c_d_t, HW_I2C_D_ADDR(x)))
00803 #define HW_I2C_D_WR(x, v)        (ADDRESS_WRITE(hw_i2c_d_t, HW_I2C_D_ADDR(x), v))
00804 #define HW_I2C_D_SET(x, v)       (HW_I2C_D_WR(x, HW_I2C_D_RD(x) |  (v)))
00805 #define HW_I2C_D_CLR(x, v)       (HW_I2C_D_WR(x, HW_I2C_D_RD(x) & ~(v)))
00806 #define HW_I2C_D_TOG(x, v)       (HW_I2C_D_WR(x, HW_I2C_D_RD(x) ^  (v)))
00807 /*@}*/
00808 
00809 /*
00810  * Constants & macros for individual I2C_D bitfields
00811  */
00812 
00813 /*!
00814  * @name Register I2C_D, field DATA[7:0] (RW)
00815  *
00816  * In master transmit mode, when data is written to this register, a data
00817  * transfer is initiated. The most significant bit is sent first. In master receive
00818  * mode, reading this register initiates receiving of the next byte of data. When
00819  * making the transition out of master receive mode, switch the I2C mode before
00820  * reading the Data register to prevent an inadvertent initiation of a master
00821  * receive data transfer. In slave mode, the same functions are available after an
00822  * address match occurs. The C1[TX] bit must correctly reflect the desired direction
00823  * of transfer in master and slave modes for the transmission to begin. For
00824  * example, if the I2C module is configured for master transmit but a master receive
00825  * is desired, reading the Data register does not initiate the receive. Reading
00826  * the Data register returns the last byte received while the I2C module is
00827  * configured in master receive or slave receive mode. The Data register does not
00828  * reflect every byte that is transmitted on the I2C bus, and neither can software
00829  * verify that a byte has been written to the Data register correctly by reading it
00830  * back. In master transmit mode, the first byte of data written to the Data
00831  * register following assertion of MST (start bit) or assertion of RSTA (repeated
00832  * start bit) is used for the address transfer and must consist of the calling
00833  * address (in bits 7-1) concatenated with the required R/W bit (in position bit 0).
00834  */
00835 /*@{*/
00836 #define BP_I2C_D_DATA        (0U)          /*!< Bit position for I2C_D_DATA. */
00837 #define BM_I2C_D_DATA        (0xFFU)       /*!< Bit mask for I2C_D_DATA. */
00838 #define BS_I2C_D_DATA        (8U)          /*!< Bit field size in bits for I2C_D_DATA. */
00839 
00840 /*! @brief Read current value of the I2C_D_DATA field. */
00841 #define BR_I2C_D_DATA(x)     (HW_I2C_D(x).U)
00842 
00843 /*! @brief Format value for bitfield I2C_D_DATA. */
00844 #define BF_I2C_D_DATA(v)     ((uint8_t)((uint8_t)(v) << BP_I2C_D_DATA) & BM_I2C_D_DATA)
00845 
00846 /*! @brief Set the DATA field to a new value. */
00847 #define BW_I2C_D_DATA(x, v)  (HW_I2C_D_WR(x, v))
00848 /*@}*/
00849 
00850 /*******************************************************************************
00851  * HW_I2C_C2 - I2C Control Register 2
00852  ******************************************************************************/
00853 
00854 /*!
00855  * @brief HW_I2C_C2 - I2C Control Register 2 (RW)
00856  *
00857  * Reset value: 0x00U
00858  */
00859 typedef union _hw_i2c_c2
00860 {
00861     uint8_t U;
00862     struct _hw_i2c_c2_bitfields
00863     {
00864         uint8_t AD : 3;                /*!< [2:0] Slave Address */
00865         uint8_t RMEN : 1;              /*!< [3] Range Address Matching Enable */
00866         uint8_t SBRC : 1;              /*!< [4] Slave Baud Rate Control */
00867         uint8_t HDRS : 1;              /*!< [5] High Drive Select */
00868         uint8_t ADEXT : 1;             /*!< [6] Address Extension */
00869         uint8_t GCAEN : 1;             /*!< [7] General Call Address Enable */
00870     } B;
00871 } hw_i2c_c2_t;
00872 
00873 /*!
00874  * @name Constants and macros for entire I2C_C2 register
00875  */
00876 /*@{*/
00877 #define HW_I2C_C2_ADDR(x)        ((x) + 0x5U)
00878 
00879 #define HW_I2C_C2(x)             (*(__IO hw_i2c_c2_t *) HW_I2C_C2_ADDR(x))
00880 #define HW_I2C_C2_RD(x)          (ADDRESS_READ(hw_i2c_c2_t, HW_I2C_C2_ADDR(x)))
00881 #define HW_I2C_C2_WR(x, v)       (ADDRESS_WRITE(hw_i2c_c2_t, HW_I2C_C2_ADDR(x), v))
00882 #define HW_I2C_C2_SET(x, v)      (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) |  (v)))
00883 #define HW_I2C_C2_CLR(x, v)      (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) & ~(v)))
00884 #define HW_I2C_C2_TOG(x, v)      (HW_I2C_C2_WR(x, HW_I2C_C2_RD(x) ^  (v)))
00885 /*@}*/
00886 
00887 /*
00888  * Constants & macros for individual I2C_C2 bitfields
00889  */
00890 
00891 /*!
00892  * @name Register I2C_C2, field AD[2:0] (RW)
00893  *
00894  * Contains the upper three bits of the slave address in the 10-bit address
00895  * scheme. This field is valid only while the ADEXT bit is set.
00896  */
00897 /*@{*/
00898 #define BP_I2C_C2_AD         (0U)          /*!< Bit position for I2C_C2_AD. */
00899 #define BM_I2C_C2_AD         (0x07U)       /*!< Bit mask for I2C_C2_AD. */
00900 #define BS_I2C_C2_AD         (3U)          /*!< Bit field size in bits for I2C_C2_AD. */
00901 
00902 /*! @brief Read current value of the I2C_C2_AD field. */
00903 #define BR_I2C_C2_AD(x)      (UNION_READ(hw_i2c_c2_t, HW_I2C_C2_ADDR(x), U, B.AD))
00904 
00905 /*! @brief Format value for bitfield I2C_C2_AD. */
00906 #define BF_I2C_C2_AD(v)      ((uint8_t)((uint8_t)(v) << BP_I2C_C2_AD) & BM_I2C_C2_AD)
00907 
00908 /*! @brief Set the AD field to a new value. */
00909 #define BW_I2C_C2_AD(x, v)   (HW_I2C_C2_WR(x, (HW_I2C_C2_RD(x) & ~BM_I2C_C2_AD) | BF_I2C_C2_AD(v)))
00910 /*@}*/
00911 
00912 /*!
00913  * @name Register I2C_C2, field RMEN[3] (RW)
00914  *
00915  * This bit controls the slave address matching for addresses between the values
00916  * of the A1 and RA registers. When this bit is set, a slave address matching
00917  * occurs for any address greater than the value of the A1 register and less than
00918  * or equal to the value of the RA register.
00919  *
00920  * Values:
00921  * - 0 - Range mode disabled. No address matching occurs for an address within
00922  *     the range of values of the A1 and RA registers.
00923  * - 1 - Range mode enabled. Address matching occurs when a slave receives an
00924  *     address within the range of values of the A1 and RA registers.
00925  */
00926 /*@{*/
00927 #define BP_I2C_C2_RMEN       (3U)          /*!< Bit position for I2C_C2_RMEN. */
00928 #define BM_I2C_C2_RMEN       (0x08U)       /*!< Bit mask for I2C_C2_RMEN. */
00929 #define BS_I2C_C2_RMEN       (1U)          /*!< Bit field size in bits for I2C_C2_RMEN. */
00930 
00931 /*! @brief Read current value of the I2C_C2_RMEN field. */
00932 #define BR_I2C_C2_RMEN(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_RMEN)))
00933 
00934 /*! @brief Format value for bitfield I2C_C2_RMEN. */
00935 #define BF_I2C_C2_RMEN(v)    ((uint8_t)((uint8_t)(v) << BP_I2C_C2_RMEN) & BM_I2C_C2_RMEN)
00936 
00937 /*! @brief Set the RMEN field to a new value. */
00938 #define BW_I2C_C2_RMEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_RMEN), v))
00939 /*@}*/
00940 
00941 /*!
00942  * @name Register I2C_C2, field SBRC[4] (RW)
00943  *
00944  * Enables independent slave mode baud rate at maximum frequency, which forces
00945  * clock stretching on SCL in very fast I2C modes. To a slave, an example of a
00946  * "very fast" mode is when the master transfers at 40 kbit/s but the slave can
00947  * capture the master's data at only 10 kbit/s.
00948  *
00949  * Values:
00950  * - 0 - The slave baud rate follows the master baud rate and clock stretching
00951  *     may occur
00952  * - 1 - Slave baud rate is independent of the master baud rate
00953  */
00954 /*@{*/
00955 #define BP_I2C_C2_SBRC       (4U)          /*!< Bit position for I2C_C2_SBRC. */
00956 #define BM_I2C_C2_SBRC       (0x10U)       /*!< Bit mask for I2C_C2_SBRC. */
00957 #define BS_I2C_C2_SBRC       (1U)          /*!< Bit field size in bits for I2C_C2_SBRC. */
00958 
00959 /*! @brief Read current value of the I2C_C2_SBRC field. */
00960 #define BR_I2C_C2_SBRC(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_SBRC)))
00961 
00962 /*! @brief Format value for bitfield I2C_C2_SBRC. */
00963 #define BF_I2C_C2_SBRC(v)    ((uint8_t)((uint8_t)(v) << BP_I2C_C2_SBRC) & BM_I2C_C2_SBRC)
00964 
00965 /*! @brief Set the SBRC field to a new value. */
00966 #define BW_I2C_C2_SBRC(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_SBRC), v))
00967 /*@}*/
00968 
00969 /*!
00970  * @name Register I2C_C2, field HDRS[5] (RW)
00971  *
00972  * Controls the drive capability of the I2C pads.
00973  *
00974  * Values:
00975  * - 0 - Normal drive mode
00976  * - 1 - High drive mode
00977  */
00978 /*@{*/
00979 #define BP_I2C_C2_HDRS       (5U)          /*!< Bit position for I2C_C2_HDRS. */
00980 #define BM_I2C_C2_HDRS       (0x20U)       /*!< Bit mask for I2C_C2_HDRS. */
00981 #define BS_I2C_C2_HDRS       (1U)          /*!< Bit field size in bits for I2C_C2_HDRS. */
00982 
00983 /*! @brief Read current value of the I2C_C2_HDRS field. */
00984 #define BR_I2C_C2_HDRS(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_HDRS)))
00985 
00986 /*! @brief Format value for bitfield I2C_C2_HDRS. */
00987 #define BF_I2C_C2_HDRS(v)    ((uint8_t)((uint8_t)(v) << BP_I2C_C2_HDRS) & BM_I2C_C2_HDRS)
00988 
00989 /*! @brief Set the HDRS field to a new value. */
00990 #define BW_I2C_C2_HDRS(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_HDRS), v))
00991 /*@}*/
00992 
00993 /*!
00994  * @name Register I2C_C2, field ADEXT[6] (RW)
00995  *
00996  * Controls the number of bits used for the slave address.
00997  *
00998  * Values:
00999  * - 0 - 7-bit address scheme
01000  * - 1 - 10-bit address scheme
01001  */
01002 /*@{*/
01003 #define BP_I2C_C2_ADEXT      (6U)          /*!< Bit position for I2C_C2_ADEXT. */
01004 #define BM_I2C_C2_ADEXT      (0x40U)       /*!< Bit mask for I2C_C2_ADEXT. */
01005 #define BS_I2C_C2_ADEXT      (1U)          /*!< Bit field size in bits for I2C_C2_ADEXT. */
01006 
01007 /*! @brief Read current value of the I2C_C2_ADEXT field. */
01008 #define BR_I2C_C2_ADEXT(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_ADEXT)))
01009 
01010 /*! @brief Format value for bitfield I2C_C2_ADEXT. */
01011 #define BF_I2C_C2_ADEXT(v)   ((uint8_t)((uint8_t)(v) << BP_I2C_C2_ADEXT) & BM_I2C_C2_ADEXT)
01012 
01013 /*! @brief Set the ADEXT field to a new value. */
01014 #define BW_I2C_C2_ADEXT(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_ADEXT), v))
01015 /*@}*/
01016 
01017 /*!
01018  * @name Register I2C_C2, field GCAEN[7] (RW)
01019  *
01020  * Enables general call address.
01021  *
01022  * Values:
01023  * - 0 - Disabled
01024  * - 1 - Enabled
01025  */
01026 /*@{*/
01027 #define BP_I2C_C2_GCAEN      (7U)          /*!< Bit position for I2C_C2_GCAEN. */
01028 #define BM_I2C_C2_GCAEN      (0x80U)       /*!< Bit mask for I2C_C2_GCAEN. */
01029 #define BS_I2C_C2_GCAEN      (1U)          /*!< Bit field size in bits for I2C_C2_GCAEN. */
01030 
01031 /*! @brief Read current value of the I2C_C2_GCAEN field. */
01032 #define BR_I2C_C2_GCAEN(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_GCAEN)))
01033 
01034 /*! @brief Format value for bitfield I2C_C2_GCAEN. */
01035 #define BF_I2C_C2_GCAEN(v)   ((uint8_t)((uint8_t)(v) << BP_I2C_C2_GCAEN) & BM_I2C_C2_GCAEN)
01036 
01037 /*! @brief Set the GCAEN field to a new value. */
01038 #define BW_I2C_C2_GCAEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_I2C_C2_ADDR(x), BP_I2C_C2_GCAEN), v))
01039 /*@}*/
01040 
01041 /*******************************************************************************
01042  * HW_I2C_FLT - I2C Programmable Input Glitch Filter register
01043  ******************************************************************************/
01044 
01045 /*!
01046  * @brief HW_I2C_FLT - I2C Programmable Input Glitch Filter register (RW)
01047  *
01048  * Reset value: 0x00U
01049  */
01050 typedef union _hw_i2c_flt
01051 {
01052     uint8_t U;
01053     struct _hw_i2c_flt_bitfields
01054     {
01055         uint8_t FLT : 4;               /*!< [3:0] I2C Programmable Filter Factor */
01056         uint8_t STARTF : 1;            /*!< [4] I2C Bus Start Detect Flag */
01057         uint8_t SSIE : 1;              /*!< [5] I2C Bus Stop or Start Interrupt Enable */
01058         uint8_t STOPF : 1;             /*!< [6] I2C Bus Stop Detect Flag */
01059         uint8_t SHEN : 1;              /*!< [7] Stop Hold Enable */
01060     } B;
01061 } hw_i2c_flt_t;
01062 
01063 /*!
01064  * @name Constants and macros for entire I2C_FLT register
01065  */
01066 /*@{*/
01067 #define HW_I2C_FLT_ADDR(x)       ((x) + 0x6U)
01068 
01069 #define HW_I2C_FLT(x)            (*(__IO hw_i2c_flt_t *) HW_I2C_FLT_ADDR(x))
01070 #define HW_I2C_FLT_RD(x)         (ADDRESS_READ(hw_i2c_flt_t, HW_I2C_FLT_ADDR(x)))
01071 #define HW_I2C_FLT_WR(x, v)      (ADDRESS_WRITE(hw_i2c_flt_t, HW_I2C_FLT_ADDR(x), v))
01072 #define HW_I2C_FLT_SET(x, v)     (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) |  (v)))
01073 #define HW_I2C_FLT_CLR(x, v)     (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) & ~(v)))
01074 #define HW_I2C_FLT_TOG(x, v)     (HW_I2C_FLT_WR(x, HW_I2C_FLT_RD(x) ^  (v)))
01075 /*@}*/
01076 
01077 /*
01078  * Constants & macros for individual I2C_FLT bitfields
01079  */
01080 
01081 /*!
01082  * @name Register I2C_FLT, field FLT[3:0] (RW)
01083  *
01084  * Controls the width of the glitch, in terms of I2C module clock cycles, that
01085  * the filter must absorb. For any glitch whose size is less than or equal to this
01086  * width setting, the filter does not allow the glitch to pass.
01087  *
01088  * Values:
01089  * - 0 - No filter/bypass
01090  */
01091 /*@{*/
01092 #define BP_I2C_FLT_FLT       (0U)          /*!< Bit position for I2C_FLT_FLT. */
01093 #define BM_I2C_FLT_FLT       (0x0FU)       /*!< Bit mask for I2C_FLT_FLT. */
01094 #define BS_I2C_FLT_FLT       (4U)          /*!< Bit field size in bits for I2C_FLT_FLT. */
01095 
01096 /*! @brief Read current value of the I2C_FLT_FLT field. */
01097 #define BR_I2C_FLT_FLT(x)    (UNION_READ(hw_i2c_flt_t, HW_I2C_FLT_ADDR(x), U, B.FLT))
01098 
01099 /*! @brief Format value for bitfield I2C_FLT_FLT. */
01100 #define BF_I2C_FLT_FLT(v)    ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_FLT) & BM_I2C_FLT_FLT)
01101 
01102 /*! @brief Set the FLT field to a new value. */
01103 #define BW_I2C_FLT_FLT(x, v) (HW_I2C_FLT_WR(x, (HW_I2C_FLT_RD(x) & ~BM_I2C_FLT_FLT) | BF_I2C_FLT_FLT(v)))
01104 /*@}*/
01105 
01106 /*!
01107  * @name Register I2C_FLT, field STARTF[4] (W1C)
01108  *
01109  * Hardware sets this bit when the I2C bus's start status is detected. The
01110  * STARTF bit must be cleared by writing 1 to it.
01111  *
01112  * Values:
01113  * - 0 - No start happens on I2C bus
01114  * - 1 - Start detected on I2C bus
01115  */
01116 /*@{*/
01117 #define BP_I2C_FLT_STARTF    (4U)          /*!< Bit position for I2C_FLT_STARTF. */
01118 #define BM_I2C_FLT_STARTF    (0x10U)       /*!< Bit mask for I2C_FLT_STARTF. */
01119 #define BS_I2C_FLT_STARTF    (1U)          /*!< Bit field size in bits for I2C_FLT_STARTF. */
01120 
01121 /*! @brief Read current value of the I2C_FLT_STARTF field. */
01122 #define BR_I2C_FLT_STARTF(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STARTF)))
01123 
01124 /*! @brief Format value for bitfield I2C_FLT_STARTF. */
01125 #define BF_I2C_FLT_STARTF(v) ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_STARTF) & BM_I2C_FLT_STARTF)
01126 
01127 /*! @brief Set the STARTF field to a new value. */
01128 #define BW_I2C_FLT_STARTF(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STARTF), v))
01129 /*@}*/
01130 
01131 /*!
01132  * @name Register I2C_FLT, field SSIE[5] (RW)
01133  *
01134  * This bit enables the interrupt for I2C bus stop or start detection. To clear
01135  * the I2C bus stop or start detection interrupt: In the interrupt service
01136  * routine, first clear the STOPF or STARTF bit by writing 1 to it, and then clear the
01137  * IICIF bit in the status register. If this sequence is reversed, the IICIF bit
01138  * is asserted again.
01139  *
01140  * Values:
01141  * - 0 - Stop or start detection interrupt is disabled
01142  * - 1 - Stop or start detection interrupt is enabled
01143  */
01144 /*@{*/
01145 #define BP_I2C_FLT_SSIE      (5U)          /*!< Bit position for I2C_FLT_SSIE. */
01146 #define BM_I2C_FLT_SSIE      (0x20U)       /*!< Bit mask for I2C_FLT_SSIE. */
01147 #define BS_I2C_FLT_SSIE      (1U)          /*!< Bit field size in bits for I2C_FLT_SSIE. */
01148 
01149 /*! @brief Read current value of the I2C_FLT_SSIE field. */
01150 #define BR_I2C_FLT_SSIE(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SSIE)))
01151 
01152 /*! @brief Format value for bitfield I2C_FLT_SSIE. */
01153 #define BF_I2C_FLT_SSIE(v)   ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_SSIE) & BM_I2C_FLT_SSIE)
01154 
01155 /*! @brief Set the SSIE field to a new value. */
01156 #define BW_I2C_FLT_SSIE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SSIE), v))
01157 /*@}*/
01158 
01159 /*!
01160  * @name Register I2C_FLT, field STOPF[6] (W1C)
01161  *
01162  * Hardware sets this bit when the I2C bus's stop status is detected. The STOPF
01163  * bit must be cleared by writing 1 to it.
01164  *
01165  * Values:
01166  * - 0 - No stop happens on I2C bus
01167  * - 1 - Stop detected on I2C bus
01168  */
01169 /*@{*/
01170 #define BP_I2C_FLT_STOPF     (6U)          /*!< Bit position for I2C_FLT_STOPF. */
01171 #define BM_I2C_FLT_STOPF     (0x40U)       /*!< Bit mask for I2C_FLT_STOPF. */
01172 #define BS_I2C_FLT_STOPF     (1U)          /*!< Bit field size in bits for I2C_FLT_STOPF. */
01173 
01174 /*! @brief Read current value of the I2C_FLT_STOPF field. */
01175 #define BR_I2C_FLT_STOPF(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STOPF)))
01176 
01177 /*! @brief Format value for bitfield I2C_FLT_STOPF. */
01178 #define BF_I2C_FLT_STOPF(v)  ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_STOPF) & BM_I2C_FLT_STOPF)
01179 
01180 /*! @brief Set the STOPF field to a new value. */
01181 #define BW_I2C_FLT_STOPF(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_STOPF), v))
01182 /*@}*/
01183 
01184 /*!
01185  * @name Register I2C_FLT, field SHEN[7] (RW)
01186  *
01187  * Set this bit to hold off entry to stop mode when any data transmission or
01188  * reception is occurring. The following scenario explains the holdoff
01189  * functionality: The I2C module is configured for a basic transfer, and the SHEN bit is set
01190  * to 1. A transfer begins. The MCU signals the I2C module to enter stop mode. The
01191  * byte currently being transferred, including both address and data, completes
01192  * its transfer. The I2C slave or master acknowledges that the in-transfer byte
01193  * completed its transfer and acknowledges the request to enter stop mode. After
01194  * receiving the I2C module's acknowledgment of the request to enter stop mode,
01195  * the MCU determines whether to shut off the I2C module's clock. If the SHEN bit
01196  * is set to 1 and the I2C module is in an idle or disabled state when the MCU
01197  * signals to enter stop mode, the module immediately acknowledges the request to
01198  * enter stop mode. If SHEN is cleared to 0 and the overall data transmission or
01199  * reception that was suspended by stop mode entry was incomplete: To resume the
01200  * overall transmission or reception after the MCU exits stop mode, software must
01201  * reinitialize the transfer by resending the address of the slave. If the I2C
01202  * Control Register 1's IICIE bit was set to 1 before the MCU entered stop mode,
01203  * system software will receive the interrupt triggered by the I2C Status Register's
01204  * TCF bit after the MCU wakes from the stop mode.
01205  *
01206  * Values:
01207  * - 0 - Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
01208  * - 1 - Stop holdoff is enabled.
01209  */
01210 /*@{*/
01211 #define BP_I2C_FLT_SHEN      (7U)          /*!< Bit position for I2C_FLT_SHEN. */
01212 #define BM_I2C_FLT_SHEN      (0x80U)       /*!< Bit mask for I2C_FLT_SHEN. */
01213 #define BS_I2C_FLT_SHEN      (1U)          /*!< Bit field size in bits for I2C_FLT_SHEN. */
01214 
01215 /*! @brief Read current value of the I2C_FLT_SHEN field. */
01216 #define BR_I2C_FLT_SHEN(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SHEN)))
01217 
01218 /*! @brief Format value for bitfield I2C_FLT_SHEN. */
01219 #define BF_I2C_FLT_SHEN(v)   ((uint8_t)((uint8_t)(v) << BP_I2C_FLT_SHEN) & BM_I2C_FLT_SHEN)
01220 
01221 /*! @brief Set the SHEN field to a new value. */
01222 #define BW_I2C_FLT_SHEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_I2C_FLT_ADDR(x), BP_I2C_FLT_SHEN), v))
01223 /*@}*/
01224 
01225 /*******************************************************************************
01226  * HW_I2C_RA - I2C Range Address register
01227  ******************************************************************************/
01228 
01229 /*!
01230  * @brief HW_I2C_RA - I2C Range Address register (RW)
01231  *
01232  * Reset value: 0x00U
01233  */
01234 typedef union _hw_i2c_ra
01235 {
01236     uint8_t U;
01237     struct _hw_i2c_ra_bitfields
01238     {
01239         uint8_t RESERVED0 : 1;         /*!< [0]  */
01240         uint8_t RAD : 7;               /*!< [7:1] Range Slave Address */
01241     } B;
01242 } hw_i2c_ra_t;
01243 
01244 /*!
01245  * @name Constants and macros for entire I2C_RA register
01246  */
01247 /*@{*/
01248 #define HW_I2C_RA_ADDR(x)        ((x) + 0x7U)
01249 
01250 #define HW_I2C_RA(x)             (*(__IO hw_i2c_ra_t *) HW_I2C_RA_ADDR(x))
01251 #define HW_I2C_RA_RD(x)          (ADDRESS_READ(hw_i2c_ra_t, HW_I2C_RA_ADDR(x)))
01252 #define HW_I2C_RA_WR(x, v)       (ADDRESS_WRITE(hw_i2c_ra_t, HW_I2C_RA_ADDR(x), v))
01253 #define HW_I2C_RA_SET(x, v)      (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) |  (v)))
01254 #define HW_I2C_RA_CLR(x, v)      (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) & ~(v)))
01255 #define HW_I2C_RA_TOG(x, v)      (HW_I2C_RA_WR(x, HW_I2C_RA_RD(x) ^  (v)))
01256 /*@}*/
01257 
01258 /*
01259  * Constants & macros for individual I2C_RA bitfields
01260  */
01261 
01262 /*!
01263  * @name Register I2C_RA, field RAD[7:1] (RW)
01264  *
01265  * This field contains the slave address to be used by the I2C module. The field
01266  * is used in the 7-bit address scheme. If I2C_C2[RMEN] is set to 1, any nonzero
01267  * value write enables this register. This register value can be considered as a
01268  * maximum boundary in the range matching mode.
01269  */
01270 /*@{*/
01271 #define BP_I2C_RA_RAD        (1U)          /*!< Bit position for I2C_RA_RAD. */
01272 #define BM_I2C_RA_RAD        (0xFEU)       /*!< Bit mask for I2C_RA_RAD. */
01273 #define BS_I2C_RA_RAD        (7U)          /*!< Bit field size in bits for I2C_RA_RAD. */
01274 
01275 /*! @brief Read current value of the I2C_RA_RAD field. */
01276 #define BR_I2C_RA_RAD(x)     (UNION_READ(hw_i2c_ra_t, HW_I2C_RA_ADDR(x), U, B.RAD))
01277 
01278 /*! @brief Format value for bitfield I2C_RA_RAD. */
01279 #define BF_I2C_RA_RAD(v)     ((uint8_t)((uint8_t)(v) << BP_I2C_RA_RAD) & BM_I2C_RA_RAD)
01280 
01281 /*! @brief Set the RAD field to a new value. */
01282 #define BW_I2C_RA_RAD(x, v)  (HW_I2C_RA_WR(x, (HW_I2C_RA_RD(x) & ~BM_I2C_RA_RAD) | BF_I2C_RA_RAD(v)))
01283 /*@}*/
01284 
01285 /*******************************************************************************
01286  * HW_I2C_SMB - I2C SMBus Control and Status register
01287  ******************************************************************************/
01288 
01289 /*!
01290  * @brief HW_I2C_SMB - I2C SMBus Control and Status register (RW)
01291  *
01292  * Reset value: 0x00U
01293  *
01294  * When the SCL and SDA signals are held high for a length of time greater than
01295  * the high timeout period, the SHTF1 flag sets. Before reaching this threshold,
01296  * while the system is detecting how long these signals are being held high, a
01297  * master assumes that the bus is free. However, the SHTF1 bit is set to 1 in the
01298  * bus transmission process with the idle bus state. When the TCKSEL bit is set,
01299  * there is no need to monitor the SHTF1 bit because the bus speed is too high to
01300  * match the protocol of SMBus.
01301  */
01302 typedef union _hw_i2c_smb
01303 {
01304     uint8_t U;
01305     struct _hw_i2c_smb_bitfields
01306     {
01307         uint8_t SHTF2IE : 1;           /*!< [0] SHTF2 Interrupt Enable */
01308         uint8_t SHTF2 : 1;             /*!< [1] SCL High Timeout Flag 2 */
01309         uint8_t SHTF1 : 1;             /*!< [2] SCL High Timeout Flag 1 */
01310         uint8_t SLTF : 1;              /*!< [3] SCL Low Timeout Flag */
01311         uint8_t TCKSEL : 1;            /*!< [4] Timeout Counter Clock Select */
01312         uint8_t SIICAEN : 1;           /*!< [5] Second I2C Address Enable */
01313         uint8_t ALERTEN : 1;           /*!< [6] SMBus Alert Response Address Enable */
01314         uint8_t FACK : 1;              /*!< [7] Fast NACK/ACK Enable */
01315     } B;
01316 } hw_i2c_smb_t;
01317 
01318 /*!
01319  * @name Constants and macros for entire I2C_SMB register
01320  */
01321 /*@{*/
01322 #define HW_I2C_SMB_ADDR(x)       ((x) + 0x8U)
01323 
01324 #define HW_I2C_SMB(x)            (*(__IO hw_i2c_smb_t *) HW_I2C_SMB_ADDR(x))
01325 #define HW_I2C_SMB_RD(x)         (ADDRESS_READ(hw_i2c_smb_t, HW_I2C_SMB_ADDR(x)))
01326 #define HW_I2C_SMB_WR(x, v)      (ADDRESS_WRITE(hw_i2c_smb_t, HW_I2C_SMB_ADDR(x), v))
01327 #define HW_I2C_SMB_SET(x, v)     (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) |  (v)))
01328 #define HW_I2C_SMB_CLR(x, v)     (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) & ~(v)))
01329 #define HW_I2C_SMB_TOG(x, v)     (HW_I2C_SMB_WR(x, HW_I2C_SMB_RD(x) ^  (v)))
01330 /*@}*/
01331 
01332 /*
01333  * Constants & macros for individual I2C_SMB bitfields
01334  */
01335 
01336 /*!
01337  * @name Register I2C_SMB, field SHTF2IE[0] (RW)
01338  *
01339  * Enables SCL high and SDA low timeout interrupt.
01340  *
01341  * Values:
01342  * - 0 - SHTF2 interrupt is disabled
01343  * - 1 - SHTF2 interrupt is enabled
01344  */
01345 /*@{*/
01346 #define BP_I2C_SMB_SHTF2IE   (0U)          /*!< Bit position for I2C_SMB_SHTF2IE. */
01347 #define BM_I2C_SMB_SHTF2IE   (0x01U)       /*!< Bit mask for I2C_SMB_SHTF2IE. */
01348 #define BS_I2C_SMB_SHTF2IE   (1U)          /*!< Bit field size in bits for I2C_SMB_SHTF2IE. */
01349 
01350 /*! @brief Read current value of the I2C_SMB_SHTF2IE field. */
01351 #define BR_I2C_SMB_SHTF2IE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2IE)))
01352 
01353 /*! @brief Format value for bitfield I2C_SMB_SHTF2IE. */
01354 #define BF_I2C_SMB_SHTF2IE(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_SHTF2IE) & BM_I2C_SMB_SHTF2IE)
01355 
01356 /*! @brief Set the SHTF2IE field to a new value. */
01357 #define BW_I2C_SMB_SHTF2IE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2IE), v))
01358 /*@}*/
01359 
01360 /*!
01361  * @name Register I2C_SMB, field SHTF2[1] (W1C)
01362  *
01363  * This bit sets when SCL is held high and SDA is held low more than clock *
01364  * LoValue / 512. Software clears this bit by writing 1 to it.
01365  *
01366  * Values:
01367  * - 0 - No SCL high and SDA low timeout occurs
01368  * - 1 - SCL high and SDA low timeout occurs
01369  */
01370 /*@{*/
01371 #define BP_I2C_SMB_SHTF2     (1U)          /*!< Bit position for I2C_SMB_SHTF2. */
01372 #define BM_I2C_SMB_SHTF2     (0x02U)       /*!< Bit mask for I2C_SMB_SHTF2. */
01373 #define BS_I2C_SMB_SHTF2     (1U)          /*!< Bit field size in bits for I2C_SMB_SHTF2. */
01374 
01375 /*! @brief Read current value of the I2C_SMB_SHTF2 field. */
01376 #define BR_I2C_SMB_SHTF2(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2)))
01377 
01378 /*! @brief Format value for bitfield I2C_SMB_SHTF2. */
01379 #define BF_I2C_SMB_SHTF2(v)  ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_SHTF2) & BM_I2C_SMB_SHTF2)
01380 
01381 /*! @brief Set the SHTF2 field to a new value. */
01382 #define BW_I2C_SMB_SHTF2(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF2), v))
01383 /*@}*/
01384 
01385 /*!
01386  * @name Register I2C_SMB, field SHTF1[2] (RO)
01387  *
01388  * This read-only bit sets when SCL and SDA are held high more than clock *
01389  * LoValue / 512, which indicates the bus is free. This bit is cleared automatically.
01390  *
01391  * Values:
01392  * - 0 - No SCL high and SDA high timeout occurs
01393  * - 1 - SCL high and SDA high timeout occurs
01394  */
01395 /*@{*/
01396 #define BP_I2C_SMB_SHTF1     (2U)          /*!< Bit position for I2C_SMB_SHTF1. */
01397 #define BM_I2C_SMB_SHTF1     (0x04U)       /*!< Bit mask for I2C_SMB_SHTF1. */
01398 #define BS_I2C_SMB_SHTF1     (1U)          /*!< Bit field size in bits for I2C_SMB_SHTF1. */
01399 
01400 /*! @brief Read current value of the I2C_SMB_SHTF1 field. */
01401 #define BR_I2C_SMB_SHTF1(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SHTF1)))
01402 /*@}*/
01403 
01404 /*!
01405  * @name Register I2C_SMB, field SLTF[3] (W1C)
01406  *
01407  * This bit is set when the SLT register (consisting of the SLTH and SLTL
01408  * registers) is loaded with a non-zero value (LoValue) and an SCL low timeout occurs.
01409  * Software clears this bit by writing a logic 1 to it. The low timeout function
01410  * is disabled when the SLT register's value is 0.
01411  *
01412  * Values:
01413  * - 0 - No low timeout occurs
01414  * - 1 - Low timeout occurs
01415  */
01416 /*@{*/
01417 #define BP_I2C_SMB_SLTF      (3U)          /*!< Bit position for I2C_SMB_SLTF. */
01418 #define BM_I2C_SMB_SLTF      (0x08U)       /*!< Bit mask for I2C_SMB_SLTF. */
01419 #define BS_I2C_SMB_SLTF      (1U)          /*!< Bit field size in bits for I2C_SMB_SLTF. */
01420 
01421 /*! @brief Read current value of the I2C_SMB_SLTF field. */
01422 #define BR_I2C_SMB_SLTF(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SLTF)))
01423 
01424 /*! @brief Format value for bitfield I2C_SMB_SLTF. */
01425 #define BF_I2C_SMB_SLTF(v)   ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_SLTF) & BM_I2C_SMB_SLTF)
01426 
01427 /*! @brief Set the SLTF field to a new value. */
01428 #define BW_I2C_SMB_SLTF(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SLTF), v))
01429 /*@}*/
01430 
01431 /*!
01432  * @name Register I2C_SMB, field TCKSEL[4] (RW)
01433  *
01434  * Selects the clock source of the timeout counter.
01435  *
01436  * Values:
01437  * - 0 - Timeout counter counts at the frequency of the I2C module clock / 64
01438  * - 1 - Timeout counter counts at the frequency of the I2C module clock
01439  */
01440 /*@{*/
01441 #define BP_I2C_SMB_TCKSEL    (4U)          /*!< Bit position for I2C_SMB_TCKSEL. */
01442 #define BM_I2C_SMB_TCKSEL    (0x10U)       /*!< Bit mask for I2C_SMB_TCKSEL. */
01443 #define BS_I2C_SMB_TCKSEL    (1U)          /*!< Bit field size in bits for I2C_SMB_TCKSEL. */
01444 
01445 /*! @brief Read current value of the I2C_SMB_TCKSEL field. */
01446 #define BR_I2C_SMB_TCKSEL(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_TCKSEL)))
01447 
01448 /*! @brief Format value for bitfield I2C_SMB_TCKSEL. */
01449 #define BF_I2C_SMB_TCKSEL(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_TCKSEL) & BM_I2C_SMB_TCKSEL)
01450 
01451 /*! @brief Set the TCKSEL field to a new value. */
01452 #define BW_I2C_SMB_TCKSEL(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_TCKSEL), v))
01453 /*@}*/
01454 
01455 /*!
01456  * @name Register I2C_SMB, field SIICAEN[5] (RW)
01457  *
01458  * Enables or disables SMBus device default address.
01459  *
01460  * Values:
01461  * - 0 - I2C address register 2 matching is disabled
01462  * - 1 - I2C address register 2 matching is enabled
01463  */
01464 /*@{*/
01465 #define BP_I2C_SMB_SIICAEN   (5U)          /*!< Bit position for I2C_SMB_SIICAEN. */
01466 #define BM_I2C_SMB_SIICAEN   (0x20U)       /*!< Bit mask for I2C_SMB_SIICAEN. */
01467 #define BS_I2C_SMB_SIICAEN   (1U)          /*!< Bit field size in bits for I2C_SMB_SIICAEN. */
01468 
01469 /*! @brief Read current value of the I2C_SMB_SIICAEN field. */
01470 #define BR_I2C_SMB_SIICAEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SIICAEN)))
01471 
01472 /*! @brief Format value for bitfield I2C_SMB_SIICAEN. */
01473 #define BF_I2C_SMB_SIICAEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_SIICAEN) & BM_I2C_SMB_SIICAEN)
01474 
01475 /*! @brief Set the SIICAEN field to a new value. */
01476 #define BW_I2C_SMB_SIICAEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_SIICAEN), v))
01477 /*@}*/
01478 
01479 /*!
01480  * @name Register I2C_SMB, field ALERTEN[6] (RW)
01481  *
01482  * Enables or disables SMBus alert response address matching. After the host
01483  * responds to a device that used the alert response address, you must use software
01484  * to put the device's address on the bus. The alert protocol is described in the
01485  * SMBus specification.
01486  *
01487  * Values:
01488  * - 0 - SMBus alert response address matching is disabled
01489  * - 1 - SMBus alert response address matching is enabled
01490  */
01491 /*@{*/
01492 #define BP_I2C_SMB_ALERTEN   (6U)          /*!< Bit position for I2C_SMB_ALERTEN. */
01493 #define BM_I2C_SMB_ALERTEN   (0x40U)       /*!< Bit mask for I2C_SMB_ALERTEN. */
01494 #define BS_I2C_SMB_ALERTEN   (1U)          /*!< Bit field size in bits for I2C_SMB_ALERTEN. */
01495 
01496 /*! @brief Read current value of the I2C_SMB_ALERTEN field. */
01497 #define BR_I2C_SMB_ALERTEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_ALERTEN)))
01498 
01499 /*! @brief Format value for bitfield I2C_SMB_ALERTEN. */
01500 #define BF_I2C_SMB_ALERTEN(v) ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_ALERTEN) & BM_I2C_SMB_ALERTEN)
01501 
01502 /*! @brief Set the ALERTEN field to a new value. */
01503 #define BW_I2C_SMB_ALERTEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_ALERTEN), v))
01504 /*@}*/
01505 
01506 /*!
01507  * @name Register I2C_SMB, field FACK[7] (RW)
01508  *
01509  * For SMBus packet error checking, the CPU must be able to issue an ACK or NACK
01510  * according to the result of receiving data byte.
01511  *
01512  * Values:
01513  * - 0 - An ACK or NACK is sent on the following receiving data byte
01514  * - 1 - Writing 0 to TXAK after receiving a data byte generates an ACK. Writing
01515  *     1 to TXAK after receiving a data byte generates a NACK.
01516  */
01517 /*@{*/
01518 #define BP_I2C_SMB_FACK      (7U)          /*!< Bit position for I2C_SMB_FACK. */
01519 #define BM_I2C_SMB_FACK      (0x80U)       /*!< Bit mask for I2C_SMB_FACK. */
01520 #define BS_I2C_SMB_FACK      (1U)          /*!< Bit field size in bits for I2C_SMB_FACK. */
01521 
01522 /*! @brief Read current value of the I2C_SMB_FACK field. */
01523 #define BR_I2C_SMB_FACK(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_FACK)))
01524 
01525 /*! @brief Format value for bitfield I2C_SMB_FACK. */
01526 #define BF_I2C_SMB_FACK(v)   ((uint8_t)((uint8_t)(v) << BP_I2C_SMB_FACK) & BM_I2C_SMB_FACK)
01527 
01528 /*! @brief Set the FACK field to a new value. */
01529 #define BW_I2C_SMB_FACK(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_I2C_SMB_ADDR(x), BP_I2C_SMB_FACK), v))
01530 /*@}*/
01531 
01532 /*******************************************************************************
01533  * HW_I2C_A2 - I2C Address Register 2
01534  ******************************************************************************/
01535 
01536 /*!
01537  * @brief HW_I2C_A2 - I2C Address Register 2 (RW)
01538  *
01539  * Reset value: 0xC2U
01540  */
01541 typedef union _hw_i2c_a2
01542 {
01543     uint8_t U;
01544     struct _hw_i2c_a2_bitfields
01545     {
01546         uint8_t RESERVED0 : 1;         /*!< [0]  */
01547         uint8_t SAD : 7;               /*!< [7:1] SMBus Address */
01548     } B;
01549 } hw_i2c_a2_t;
01550 
01551 /*!
01552  * @name Constants and macros for entire I2C_A2 register
01553  */
01554 /*@{*/
01555 #define HW_I2C_A2_ADDR(x)        ((x) + 0x9U)
01556 
01557 #define HW_I2C_A2(x)             (*(__IO hw_i2c_a2_t *) HW_I2C_A2_ADDR(x))
01558 #define HW_I2C_A2_RD(x)          (ADDRESS_READ(hw_i2c_a2_t, HW_I2C_A2_ADDR(x)))
01559 #define HW_I2C_A2_WR(x, v)       (ADDRESS_WRITE(hw_i2c_a2_t, HW_I2C_A2_ADDR(x), v))
01560 #define HW_I2C_A2_SET(x, v)      (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) |  (v)))
01561 #define HW_I2C_A2_CLR(x, v)      (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) & ~(v)))
01562 #define HW_I2C_A2_TOG(x, v)      (HW_I2C_A2_WR(x, HW_I2C_A2_RD(x) ^  (v)))
01563 /*@}*/
01564 
01565 /*
01566  * Constants & macros for individual I2C_A2 bitfields
01567  */
01568 
01569 /*!
01570  * @name Register I2C_A2, field SAD[7:1] (RW)
01571  *
01572  * Contains the slave address used by the SMBus. This field is used on the
01573  * device default address or other related addresses.
01574  */
01575 /*@{*/
01576 #define BP_I2C_A2_SAD        (1U)          /*!< Bit position for I2C_A2_SAD. */
01577 #define BM_I2C_A2_SAD        (0xFEU)       /*!< Bit mask for I2C_A2_SAD. */
01578 #define BS_I2C_A2_SAD        (7U)          /*!< Bit field size in bits for I2C_A2_SAD. */
01579 
01580 /*! @brief Read current value of the I2C_A2_SAD field. */
01581 #define BR_I2C_A2_SAD(x)     (UNION_READ(hw_i2c_a2_t, HW_I2C_A2_ADDR(x), U, B.SAD))
01582 
01583 /*! @brief Format value for bitfield I2C_A2_SAD. */
01584 #define BF_I2C_A2_SAD(v)     ((uint8_t)((uint8_t)(v) << BP_I2C_A2_SAD) & BM_I2C_A2_SAD)
01585 
01586 /*! @brief Set the SAD field to a new value. */
01587 #define BW_I2C_A2_SAD(x, v)  (HW_I2C_A2_WR(x, (HW_I2C_A2_RD(x) & ~BM_I2C_A2_SAD) | BF_I2C_A2_SAD(v)))
01588 /*@}*/
01589 
01590 /*******************************************************************************
01591  * HW_I2C_SLTH - I2C SCL Low Timeout Register High
01592  ******************************************************************************/
01593 
01594 /*!
01595  * @brief HW_I2C_SLTH - I2C SCL Low Timeout Register High (RW)
01596  *
01597  * Reset value: 0x00U
01598  */
01599 typedef union _hw_i2c_slth
01600 {
01601     uint8_t U;
01602     struct _hw_i2c_slth_bitfields
01603     {
01604         uint8_t SSLT : 8;              /*!< [7:0]  */
01605     } B;
01606 } hw_i2c_slth_t;
01607 
01608 /*!
01609  * @name Constants and macros for entire I2C_SLTH register
01610  */
01611 /*@{*/
01612 #define HW_I2C_SLTH_ADDR(x)      ((x) + 0xAU)
01613 
01614 #define HW_I2C_SLTH(x)           (*(__IO hw_i2c_slth_t *) HW_I2C_SLTH_ADDR(x))
01615 #define HW_I2C_SLTH_RD(x)        (ADDRESS_READ(hw_i2c_slth_t, HW_I2C_SLTH_ADDR(x)))
01616 #define HW_I2C_SLTH_WR(x, v)     (ADDRESS_WRITE(hw_i2c_slth_t, HW_I2C_SLTH_ADDR(x), v))
01617 #define HW_I2C_SLTH_SET(x, v)    (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) |  (v)))
01618 #define HW_I2C_SLTH_CLR(x, v)    (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) & ~(v)))
01619 #define HW_I2C_SLTH_TOG(x, v)    (HW_I2C_SLTH_WR(x, HW_I2C_SLTH_RD(x) ^  (v)))
01620 /*@}*/
01621 
01622 /*
01623  * Constants & macros for individual I2C_SLTH bitfields
01624  */
01625 
01626 /*!
01627  * @name Register I2C_SLTH, field SSLT[7:0] (RW)
01628  *
01629  * Most significant byte of SCL low timeout value that determines the timeout
01630  * period of SCL low.
01631  */
01632 /*@{*/
01633 #define BP_I2C_SLTH_SSLT     (0U)          /*!< Bit position for I2C_SLTH_SSLT. */
01634 #define BM_I2C_SLTH_SSLT     (0xFFU)       /*!< Bit mask for I2C_SLTH_SSLT. */
01635 #define BS_I2C_SLTH_SSLT     (8U)          /*!< Bit field size in bits for I2C_SLTH_SSLT. */
01636 
01637 /*! @brief Read current value of the I2C_SLTH_SSLT field. */
01638 #define BR_I2C_SLTH_SSLT(x)  (HW_I2C_SLTH(x).U)
01639 
01640 /*! @brief Format value for bitfield I2C_SLTH_SSLT. */
01641 #define BF_I2C_SLTH_SSLT(v)  ((uint8_t)((uint8_t)(v) << BP_I2C_SLTH_SSLT) & BM_I2C_SLTH_SSLT)
01642 
01643 /*! @brief Set the SSLT field to a new value. */
01644 #define BW_I2C_SLTH_SSLT(x, v) (HW_I2C_SLTH_WR(x, v))
01645 /*@}*/
01646 
01647 /*******************************************************************************
01648  * HW_I2C_SLTL - I2C SCL Low Timeout Register Low
01649  ******************************************************************************/
01650 
01651 /*!
01652  * @brief HW_I2C_SLTL - I2C SCL Low Timeout Register Low (RW)
01653  *
01654  * Reset value: 0x00U
01655  */
01656 typedef union _hw_i2c_sltl
01657 {
01658     uint8_t U;
01659     struct _hw_i2c_sltl_bitfields
01660     {
01661         uint8_t SSLT : 8;              /*!< [7:0]  */
01662     } B;
01663 } hw_i2c_sltl_t;
01664 
01665 /*!
01666  * @name Constants and macros for entire I2C_SLTL register
01667  */
01668 /*@{*/
01669 #define HW_I2C_SLTL_ADDR(x)      ((x) + 0xBU)
01670 
01671 #define HW_I2C_SLTL(x)           (*(__IO hw_i2c_sltl_t *) HW_I2C_SLTL_ADDR(x))
01672 #define HW_I2C_SLTL_RD(x)        (ADDRESS_READ(hw_i2c_sltl_t, HW_I2C_SLTL_ADDR(x)))
01673 #define HW_I2C_SLTL_WR(x, v)     (ADDRESS_WRITE(hw_i2c_sltl_t, HW_I2C_SLTL_ADDR(x), v))
01674 #define HW_I2C_SLTL_SET(x, v)    (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) |  (v)))
01675 #define HW_I2C_SLTL_CLR(x, v)    (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) & ~(v)))
01676 #define HW_I2C_SLTL_TOG(x, v)    (HW_I2C_SLTL_WR(x, HW_I2C_SLTL_RD(x) ^  (v)))
01677 /*@}*/
01678 
01679 /*
01680  * Constants & macros for individual I2C_SLTL bitfields
01681  */
01682 
01683 /*!
01684  * @name Register I2C_SLTL, field SSLT[7:0] (RW)
01685  *
01686  * Least significant byte of SCL low timeout value that determines the timeout
01687  * period of SCL low.
01688  */
01689 /*@{*/
01690 #define BP_I2C_SLTL_SSLT     (0U)          /*!< Bit position for I2C_SLTL_SSLT. */
01691 #define BM_I2C_SLTL_SSLT     (0xFFU)       /*!< Bit mask for I2C_SLTL_SSLT. */
01692 #define BS_I2C_SLTL_SSLT     (8U)          /*!< Bit field size in bits for I2C_SLTL_SSLT. */
01693 
01694 /*! @brief Read current value of the I2C_SLTL_SSLT field. */
01695 #define BR_I2C_SLTL_SSLT(x)  (HW_I2C_SLTL(x).U)
01696 
01697 /*! @brief Format value for bitfield I2C_SLTL_SSLT. */
01698 #define BF_I2C_SLTL_SSLT(v)  ((uint8_t)((uint8_t)(v) << BP_I2C_SLTL_SSLT) & BM_I2C_SLTL_SSLT)
01699 
01700 /*! @brief Set the SSLT field to a new value. */
01701 #define BW_I2C_SLTL_SSLT(x, v) (HW_I2C_SLTL_WR(x, v))
01702 /*@}*/
01703 
01704 /*******************************************************************************
01705  * hw_i2c_t - module struct
01706  ******************************************************************************/
01707 /*!
01708  * @brief All I2C module registers.
01709  */
01710 #pragma pack(1)
01711 typedef struct _hw_i2c
01712 {
01713     __IO hw_i2c_a1_t A1 ;                   /*!< [0x0] I2C Address Register 1 */
01714     __IO hw_i2c_f_t F ;                     /*!< [0x1] I2C Frequency Divider register */
01715     __IO hw_i2c_c1_t C1 ;                   /*!< [0x2] I2C Control Register 1 */
01716     __IO hw_i2c_s_t S ;                     /*!< [0x3] I2C Status register */
01717     __IO hw_i2c_d_t D ;                     /*!< [0x4] I2C Data I/O register */
01718     __IO hw_i2c_c2_t C2 ;                   /*!< [0x5] I2C Control Register 2 */
01719     __IO hw_i2c_flt_t FLT ;                 /*!< [0x6] I2C Programmable Input Glitch Filter register */
01720     __IO hw_i2c_ra_t RA ;                   /*!< [0x7] I2C Range Address register */
01721     __IO hw_i2c_smb_t SMB ;                 /*!< [0x8] I2C SMBus Control and Status register */
01722     __IO hw_i2c_a2_t A2 ;                   /*!< [0x9] I2C Address Register 2 */
01723     __IO hw_i2c_slth_t SLTH ;               /*!< [0xA] I2C SCL Low Timeout Register High */
01724     __IO hw_i2c_sltl_t SLTL ;               /*!< [0xB] I2C SCL Low Timeout Register Low */
01725 } hw_i2c_t;
01726 #pragma pack()
01727 
01728 /*! @brief Macro to access all I2C registers. */
01729 /*! @param x I2C module instance base address. */
01730 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
01731  *     use the '&' operator, like <code>&HW_I2C(I2C0_BASE)</code>. */
01732 #define HW_I2C(x)      (*(hw_i2c_t *)(x))
01733 
01734 #endif /* __HW_I2C_REGISTERS_H__ */
01735 /* EOF */