MK64F12_gpio.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_GPIO_REGISTERS_H__
00088 #define __HW_GPIO_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 GPIO
00095  *
00096  * General Purpose Input/Output
00097  *
00098  * Registers defined in this header file:
00099  * - HW_GPIO_PDOR - Port Data Output Register
00100  * - HW_GPIO_PSOR - Port Set Output Register
00101  * - HW_GPIO_PCOR - Port Clear Output Register
00102  * - HW_GPIO_PTOR - Port Toggle Output Register
00103  * - HW_GPIO_PDIR - Port Data Input Register
00104  * - HW_GPIO_PDDR - Port Data Direction Register
00105  *
00106  * - hw_gpio_t - Struct containing all module registers.
00107  */
00108 
00109 #define HW_GPIO_INSTANCE_COUNT (5U) /*!< Number of instances of the GPIO module. */
00110 #define HW_GPIOA (0U) /*!< Instance number for GPIOA. */
00111 #define HW_GPIOB (1U) /*!< Instance number for GPIOB. */
00112 #define HW_GPIOC (2U) /*!< Instance number for GPIOC. */
00113 #define HW_GPIOD (3U) /*!< Instance number for GPIOD. */
00114 #define HW_GPIOE (4U) /*!< Instance number for GPIOE. */
00115 
00116 /*******************************************************************************
00117  * HW_GPIO_PDOR - Port Data Output Register
00118  ******************************************************************************/
00119 
00120 /*!
00121  * @brief HW_GPIO_PDOR - Port Data Output Register (RW)
00122  *
00123  * Reset value: 0x00000000U
00124  *
00125  * This register configures the logic levels that are driven on each
00126  * general-purpose output pins. Do not modify pin configuration registers associated with
00127  * pins not available in your selected package. All unbonded pins not available in
00128  * your package will default to DISABLE state for lowest power consumption.
00129  */
00130 typedef union _hw_gpio_pdor
00131 {
00132     uint32_t U;
00133     struct _hw_gpio_pdor_bitfields
00134     {
00135         uint32_t PDO : 32;             /*!< [31:0] Port Data Output */
00136     } B;
00137 } hw_gpio_pdor_t;
00138 
00139 /*!
00140  * @name Constants and macros for entire GPIO_PDOR register
00141  */
00142 /*@{*/
00143 #define HW_GPIO_PDOR_ADDR(x)     ((x) + 0x0U)
00144 
00145 #define HW_GPIO_PDOR(x)          (*(__IO hw_gpio_pdor_t *) HW_GPIO_PDOR_ADDR(x))
00146 #define HW_GPIO_PDOR_RD(x)       (ADDRESS_READ(hw_gpio_pdor_t, HW_GPIO_PDOR_ADDR(x)))
00147 #define HW_GPIO_PDOR_WR(x, v)    (ADDRESS_WRITE(hw_gpio_pdor_t, HW_GPIO_PDOR_ADDR(x), v))
00148 #define HW_GPIO_PDOR_SET(x, v)   (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) |  (v)))
00149 #define HW_GPIO_PDOR_CLR(x, v)   (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) & ~(v)))
00150 #define HW_GPIO_PDOR_TOG(x, v)   (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) ^  (v)))
00151 /*@}*/
00152 
00153 /*
00154  * Constants & macros for individual GPIO_PDOR bitfields
00155  */
00156 
00157 /*!
00158  * @name Register GPIO_PDOR, field PDO[31:0] (RW)
00159  *
00160  * Register bits for unbonded pins return a undefined value when read.
00161  *
00162  * Values:
00163  * - 0 - Logic level 0 is driven on pin, provided pin is configured for
00164  *     general-purpose output.
00165  * - 1 - Logic level 1 is driven on pin, provided pin is configured for
00166  *     general-purpose output.
00167  */
00168 /*@{*/
00169 #define BP_GPIO_PDOR_PDO     (0U)          /*!< Bit position for GPIO_PDOR_PDO. */
00170 #define BM_GPIO_PDOR_PDO     (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDOR_PDO. */
00171 #define BS_GPIO_PDOR_PDO     (32U)         /*!< Bit field size in bits for GPIO_PDOR_PDO. */
00172 
00173 /*! @brief Read current value of the GPIO_PDOR_PDO field. */
00174 #define BR_GPIO_PDOR_PDO(x)  (HW_GPIO_PDOR(x).U)
00175 
00176 /*! @brief Format value for bitfield GPIO_PDOR_PDO. */
00177 #define BF_GPIO_PDOR_PDO(v)  ((uint32_t)((uint32_t)(v) << BP_GPIO_PDOR_PDO) & BM_GPIO_PDOR_PDO)
00178 
00179 /*! @brief Set the PDO field to a new value. */
00180 #define BW_GPIO_PDOR_PDO(x, v) (HW_GPIO_PDOR_WR(x, v))
00181 /*@}*/
00182 
00183 /*******************************************************************************
00184  * HW_GPIO_PSOR - Port Set Output Register
00185  ******************************************************************************/
00186 
00187 /*!
00188  * @brief HW_GPIO_PSOR - Port Set Output Register (WORZ)
00189  *
00190  * Reset value: 0x00000000U
00191  *
00192  * This register configures whether to set the fields of the PDOR.
00193  */
00194 typedef union _hw_gpio_psor
00195 {
00196     uint32_t U;
00197     struct _hw_gpio_psor_bitfields
00198     {
00199         uint32_t PTSO : 32;            /*!< [31:0] Port Set Output */
00200     } B;
00201 } hw_gpio_psor_t;
00202 
00203 /*!
00204  * @name Constants and macros for entire GPIO_PSOR register
00205  */
00206 /*@{*/
00207 #define HW_GPIO_PSOR_ADDR(x)     ((x) + 0x4U)
00208 
00209 #define HW_GPIO_PSOR(x)          (*(__O hw_gpio_psor_t *) HW_GPIO_PSOR_ADDR(x))
00210 #define HW_GPIO_PSOR_RD(x)       (ADDRESS_READ(hw_gpio_psor_t, HW_GPIO_PSOR_ADDR(x)))
00211 #define HW_GPIO_PSOR_WR(x, v)    (ADDRESS_WRITE(hw_gpio_psor_t, HW_GPIO_PSOR_ADDR(x), v))
00212 /*@}*/
00213 
00214 /*
00215  * Constants & macros for individual GPIO_PSOR bitfields
00216  */
00217 
00218 /*!
00219  * @name Register GPIO_PSOR, field PTSO[31:0] (WORZ)
00220  *
00221  * Writing to this register will update the contents of the corresponding bit in
00222  * the PDOR as follows:
00223  *
00224  * Values:
00225  * - 0 - Corresponding bit in PDORn does not change.
00226  * - 1 - Corresponding bit in PDORn is set to logic 1.
00227  */
00228 /*@{*/
00229 #define BP_GPIO_PSOR_PTSO    (0U)          /*!< Bit position for GPIO_PSOR_PTSO. */
00230 #define BM_GPIO_PSOR_PTSO    (0xFFFFFFFFU) /*!< Bit mask for GPIO_PSOR_PTSO. */
00231 #define BS_GPIO_PSOR_PTSO    (32U)         /*!< Bit field size in bits for GPIO_PSOR_PTSO. */
00232 
00233 /*! @brief Format value for bitfield GPIO_PSOR_PTSO. */
00234 #define BF_GPIO_PSOR_PTSO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PSOR_PTSO) & BM_GPIO_PSOR_PTSO)
00235 
00236 /*! @brief Set the PTSO field to a new value. */
00237 #define BW_GPIO_PSOR_PTSO(x, v) (HW_GPIO_PSOR_WR(x, v))
00238 /*@}*/
00239 
00240 /*******************************************************************************
00241  * HW_GPIO_PCOR - Port Clear Output Register
00242  ******************************************************************************/
00243 
00244 /*!
00245  * @brief HW_GPIO_PCOR - Port Clear Output Register (WORZ)
00246  *
00247  * Reset value: 0x00000000U
00248  *
00249  * This register configures whether to clear the fields of PDOR.
00250  */
00251 typedef union _hw_gpio_pcor
00252 {
00253     uint32_t U;
00254     struct _hw_gpio_pcor_bitfields
00255     {
00256         uint32_t PTCO : 32;            /*!< [31:0] Port Clear Output */
00257     } B;
00258 } hw_gpio_pcor_t;
00259 
00260 /*!
00261  * @name Constants and macros for entire GPIO_PCOR register
00262  */
00263 /*@{*/
00264 #define HW_GPIO_PCOR_ADDR(x)     ((x) + 0x8U)
00265 
00266 #define HW_GPIO_PCOR(x)          (*(__O hw_gpio_pcor_t *) HW_GPIO_PCOR_ADDR(x))
00267 #define HW_GPIO_PCOR_RD(x)       (ADDRESS_READ(hw_gpio_pcor_t, HW_GPIO_PCOR_ADDR(x)))
00268 #define HW_GPIO_PCOR_WR(x, v)    (ADDRESS_WRITE(hw_gpio_pcor_t, HW_GPIO_PCOR_ADDR(x), v))
00269 /*@}*/
00270 
00271 /*
00272  * Constants & macros for individual GPIO_PCOR bitfields
00273  */
00274 
00275 /*!
00276  * @name Register GPIO_PCOR, field PTCO[31:0] (WORZ)
00277  *
00278  * Writing to this register will update the contents of the corresponding bit in
00279  * the Port Data Output Register (PDOR) as follows:
00280  *
00281  * Values:
00282  * - 0 - Corresponding bit in PDORn does not change.
00283  * - 1 - Corresponding bit in PDORn is cleared to logic 0.
00284  */
00285 /*@{*/
00286 #define BP_GPIO_PCOR_PTCO    (0U)          /*!< Bit position for GPIO_PCOR_PTCO. */
00287 #define BM_GPIO_PCOR_PTCO    (0xFFFFFFFFU) /*!< Bit mask for GPIO_PCOR_PTCO. */
00288 #define BS_GPIO_PCOR_PTCO    (32U)         /*!< Bit field size in bits for GPIO_PCOR_PTCO. */
00289 
00290 /*! @brief Format value for bitfield GPIO_PCOR_PTCO. */
00291 #define BF_GPIO_PCOR_PTCO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PCOR_PTCO) & BM_GPIO_PCOR_PTCO)
00292 
00293 /*! @brief Set the PTCO field to a new value. */
00294 #define BW_GPIO_PCOR_PTCO(x, v) (HW_GPIO_PCOR_WR(x, v))
00295 /*@}*/
00296 
00297 /*******************************************************************************
00298  * HW_GPIO_PTOR - Port Toggle Output Register
00299  ******************************************************************************/
00300 
00301 /*!
00302  * @brief HW_GPIO_PTOR - Port Toggle Output Register (WORZ)
00303  *
00304  * Reset value: 0x00000000U
00305  */
00306 typedef union _hw_gpio_ptor
00307 {
00308     uint32_t U;
00309     struct _hw_gpio_ptor_bitfields
00310     {
00311         uint32_t PTTO : 32;            /*!< [31:0] Port Toggle Output */
00312     } B;
00313 } hw_gpio_ptor_t;
00314 
00315 /*!
00316  * @name Constants and macros for entire GPIO_PTOR register
00317  */
00318 /*@{*/
00319 #define HW_GPIO_PTOR_ADDR(x)     ((x) + 0xCU)
00320 
00321 #define HW_GPIO_PTOR(x)          (*(__O hw_gpio_ptor_t *) HW_GPIO_PTOR_ADDR(x))
00322 #define HW_GPIO_PTOR_RD(x)       (ADDRESS_READ(hw_gpio_ptor_t, HW_GPIO_PTOR_ADDR(x)))
00323 #define HW_GPIO_PTOR_WR(x, v)    (ADDRESS_WRITE(hw_gpio_ptor_t, HW_GPIO_PTOR_ADDR(x), v))
00324 /*@}*/
00325 
00326 /*
00327  * Constants & macros for individual GPIO_PTOR bitfields
00328  */
00329 
00330 /*!
00331  * @name Register GPIO_PTOR, field PTTO[31:0] (WORZ)
00332  *
00333  * Writing to this register will update the contents of the corresponding bit in
00334  * the PDOR as follows:
00335  *
00336  * Values:
00337  * - 0 - Corresponding bit in PDORn does not change.
00338  * - 1 - Corresponding bit in PDORn is set to the inverse of its existing logic
00339  *     state.
00340  */
00341 /*@{*/
00342 #define BP_GPIO_PTOR_PTTO    (0U)          /*!< Bit position for GPIO_PTOR_PTTO. */
00343 #define BM_GPIO_PTOR_PTTO    (0xFFFFFFFFU) /*!< Bit mask for GPIO_PTOR_PTTO. */
00344 #define BS_GPIO_PTOR_PTTO    (32U)         /*!< Bit field size in bits for GPIO_PTOR_PTTO. */
00345 
00346 /*! @brief Format value for bitfield GPIO_PTOR_PTTO. */
00347 #define BF_GPIO_PTOR_PTTO(v) ((uint32_t)((uint32_t)(v) << BP_GPIO_PTOR_PTTO) & BM_GPIO_PTOR_PTTO)
00348 
00349 /*! @brief Set the PTTO field to a new value. */
00350 #define BW_GPIO_PTOR_PTTO(x, v) (HW_GPIO_PTOR_WR(x, v))
00351 /*@}*/
00352 
00353 /*******************************************************************************
00354  * HW_GPIO_PDIR - Port Data Input Register
00355  ******************************************************************************/
00356 
00357 /*!
00358  * @brief HW_GPIO_PDIR - Port Data Input Register (RO)
00359  *
00360  * Reset value: 0x00000000U
00361  *
00362  * Do not modify pin configuration registers associated with pins not available
00363  * in your selected package. All unbonded pins not available in your package will
00364  * default to DISABLE state for lowest power consumption.
00365  */
00366 typedef union _hw_gpio_pdir
00367 {
00368     uint32_t U;
00369     struct _hw_gpio_pdir_bitfields
00370     {
00371         uint32_t PDI : 32;             /*!< [31:0] Port Data Input */
00372     } B;
00373 } hw_gpio_pdir_t;
00374 
00375 /*!
00376  * @name Constants and macros for entire GPIO_PDIR register
00377  */
00378 /*@{*/
00379 #define HW_GPIO_PDIR_ADDR(x)     ((x) + 0x10U)
00380 
00381 #define HW_GPIO_PDIR(x)          (*(__I hw_gpio_pdir_t *) HW_GPIO_PDIR_ADDR(x))
00382 #define HW_GPIO_PDIR_RD(x)       (ADDRESS_READ(hw_gpio_pdir_t, HW_GPIO_PDIR_ADDR(x)))
00383 /*@}*/
00384 
00385 /*
00386  * Constants & macros for individual GPIO_PDIR bitfields
00387  */
00388 
00389 /*!
00390  * @name Register GPIO_PDIR, field PDI[31:0] (RO)
00391  *
00392  * Reads 0 at the unimplemented pins for a particular device. Pins that are not
00393  * configured for a digital function read 0. If the Port Control and Interrupt
00394  * module is disabled, then the corresponding bit in PDIR does not update.
00395  *
00396  * Values:
00397  * - 0 - Pin logic level is logic 0, or is not configured for use by digital
00398  *     function.
00399  * - 1 - Pin logic level is logic 1.
00400  */
00401 /*@{*/
00402 #define BP_GPIO_PDIR_PDI     (0U)          /*!< Bit position for GPIO_PDIR_PDI. */
00403 #define BM_GPIO_PDIR_PDI     (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDIR_PDI. */
00404 #define BS_GPIO_PDIR_PDI     (32U)         /*!< Bit field size in bits for GPIO_PDIR_PDI. */
00405 
00406 /*! @brief Read current value of the GPIO_PDIR_PDI field. */
00407 #define BR_GPIO_PDIR_PDI(x)  (HW_GPIO_PDIR(x).U)
00408 /*@}*/
00409 
00410 /*******************************************************************************
00411  * HW_GPIO_PDDR - Port Data Direction Register
00412  ******************************************************************************/
00413 
00414 /*!
00415  * @brief HW_GPIO_PDDR - Port Data Direction Register (RW)
00416  *
00417  * Reset value: 0x00000000U
00418  *
00419  * The PDDR configures the individual port pins for input or output.
00420  */
00421 typedef union _hw_gpio_pddr
00422 {
00423     uint32_t U;
00424     struct _hw_gpio_pddr_bitfields
00425     {
00426         uint32_t PDD : 32;             /*!< [31:0] Port Data Direction */
00427     } B;
00428 } hw_gpio_pddr_t;
00429 
00430 /*!
00431  * @name Constants and macros for entire GPIO_PDDR register
00432  */
00433 /*@{*/
00434 #define HW_GPIO_PDDR_ADDR(x)     ((x) + 0x14U)
00435 
00436 #define HW_GPIO_PDDR(x)          (*(__IO hw_gpio_pddr_t *) HW_GPIO_PDDR_ADDR(x))
00437 #define HW_GPIO_PDDR_RD(x)       (ADDRESS_READ(hw_gpio_pddr_t, HW_GPIO_PDDR_ADDR(x)))
00438 #define HW_GPIO_PDDR_WR(x, v)    (ADDRESS_WRITE(hw_gpio_pddr_t, HW_GPIO_PDDR_ADDR(x), v))
00439 #define HW_GPIO_PDDR_SET(x, v)   (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) |  (v)))
00440 #define HW_GPIO_PDDR_CLR(x, v)   (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) & ~(v)))
00441 #define HW_GPIO_PDDR_TOG(x, v)   (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) ^  (v)))
00442 /*@}*/
00443 
00444 /*
00445  * Constants & macros for individual GPIO_PDDR bitfields
00446  */
00447 
00448 /*!
00449  * @name Register GPIO_PDDR, field PDD[31:0] (RW)
00450  *
00451  * Configures individual port pins for input or output.
00452  *
00453  * Values:
00454  * - 0 - Pin is configured as general-purpose input, for the GPIO function.
00455  * - 1 - Pin is configured as general-purpose output, for the GPIO function.
00456  */
00457 /*@{*/
00458 #define BP_GPIO_PDDR_PDD     (0U)          /*!< Bit position for GPIO_PDDR_PDD. */
00459 #define BM_GPIO_PDDR_PDD     (0xFFFFFFFFU) /*!< Bit mask for GPIO_PDDR_PDD. */
00460 #define BS_GPIO_PDDR_PDD     (32U)         /*!< Bit field size in bits for GPIO_PDDR_PDD. */
00461 
00462 /*! @brief Read current value of the GPIO_PDDR_PDD field. */
00463 #define BR_GPIO_PDDR_PDD(x)  (HW_GPIO_PDDR(x).U)
00464 
00465 /*! @brief Format value for bitfield GPIO_PDDR_PDD. */
00466 #define BF_GPIO_PDDR_PDD(v)  ((uint32_t)((uint32_t)(v) << BP_GPIO_PDDR_PDD) & BM_GPIO_PDDR_PDD)
00467 
00468 /*! @brief Set the PDD field to a new value. */
00469 #define BW_GPIO_PDDR_PDD(x, v) (HW_GPIO_PDDR_WR(x, v))
00470 /*@}*/
00471 
00472 /*******************************************************************************
00473  * hw_gpio_t - module struct
00474  ******************************************************************************/
00475 /*!
00476  * @brief All GPIO module registers.
00477  */
00478 #pragma pack(1)
00479 typedef struct _hw_gpio
00480 {
00481     __IO hw_gpio_pdor_t PDOR ;              /*!< [0x0] Port Data Output Register */
00482     __O hw_gpio_psor_t PSOR ;               /*!< [0x4] Port Set Output Register */
00483     __O hw_gpio_pcor_t PCOR ;               /*!< [0x8] Port Clear Output Register */
00484     __O hw_gpio_ptor_t PTOR ;               /*!< [0xC] Port Toggle Output Register */
00485     __I hw_gpio_pdir_t PDIR ;               /*!< [0x10] Port Data Input Register */
00486     __IO hw_gpio_pddr_t PDDR ;              /*!< [0x14] Port Data Direction Register */
00487 } hw_gpio_t;
00488 #pragma pack()
00489 
00490 /*! @brief Macro to access all GPIO registers. */
00491 /*! @param x GPIO module instance base address. */
00492 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
00493  *     use the '&' operator, like <code>&HW_GPIO(GPIOA_BASE)</code>. */
00494 #define HW_GPIO(x)     (*(hw_gpio_t *)(x))
00495 
00496 #endif /* __HW_GPIO_REGISTERS_H__ */
00497 /* EOF */