MK64F12_ftm.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_FTM_REGISTERS_H__
00088 #define __HW_FTM_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 FTM
00095  *
00096  * FlexTimer Module
00097  *
00098  * Registers defined in this header file:
00099  * - HW_FTM_SC - Status And Control
00100  * - HW_FTM_CNT - Counter
00101  * - HW_FTM_MOD - Modulo
00102  * - HW_FTM_CnSC - Channel (n) Status And Control
00103  * - HW_FTM_CnV - Channel (n) Value
00104  * - HW_FTM_CNTIN - Counter Initial Value
00105  * - HW_FTM_STATUS - Capture And Compare Status
00106  * - HW_FTM_MODE - Features Mode Selection
00107  * - HW_FTM_SYNC - Synchronization
00108  * - HW_FTM_OUTINIT - Initial State For Channels Output
00109  * - HW_FTM_OUTMASK - Output Mask
00110  * - HW_FTM_COMBINE - Function For Linked Channels
00111  * - HW_FTM_DEADTIME - Deadtime Insertion Control
00112  * - HW_FTM_EXTTRIG - FTM External Trigger
00113  * - HW_FTM_POL - Channels Polarity
00114  * - HW_FTM_FMS - Fault Mode Status
00115  * - HW_FTM_FILTER - Input Capture Filter Control
00116  * - HW_FTM_FLTCTRL - Fault Control
00117  * - HW_FTM_QDCTRL - Quadrature Decoder Control And Status
00118  * - HW_FTM_CONF - Configuration
00119  * - HW_FTM_FLTPOL - FTM Fault Input Polarity
00120  * - HW_FTM_SYNCONF - Synchronization Configuration
00121  * - HW_FTM_INVCTRL - FTM Inverting Control
00122  * - HW_FTM_SWOCTRL - FTM Software Output Control
00123  * - HW_FTM_PWMLOAD - FTM PWM Load
00124  *
00125  * - hw_ftm_t - Struct containing all module registers.
00126  */
00127 
00128 #define HW_FTM_INSTANCE_COUNT (4U) /*!< Number of instances of the FTM module. */
00129 #define HW_FTM0 (0U) /*!< Instance number for FTM0. */
00130 #define HW_FTM1 (1U) /*!< Instance number for FTM1. */
00131 #define HW_FTM2 (2U) /*!< Instance number for FTM2. */
00132 #define HW_FTM3 (3U) /*!< Instance number for FTM3. */
00133 
00134 /*******************************************************************************
00135  * HW_FTM_SC - Status And Control
00136  ******************************************************************************/
00137 
00138 /*!
00139  * @brief HW_FTM_SC - Status And Control (RW)
00140  *
00141  * Reset value: 0x00000000U
00142  *
00143  * SC contains the overflow status flag and control bits used to configure the
00144  * interrupt enable, FTM configuration, clock source, and prescaler factor. These
00145  * controls relate to all channels within this module.
00146  */
00147 typedef union _hw_ftm_sc
00148 {
00149     uint32_t U;
00150     struct _hw_ftm_sc_bitfields
00151     {
00152         uint32_t PS : 3;               /*!< [2:0] Prescale Factor Selection */
00153         uint32_t CLKS : 2;             /*!< [4:3] Clock Source Selection */
00154         uint32_t CPWMS : 1;            /*!< [5] Center-Aligned PWM Select */
00155         uint32_t TOIE : 1;             /*!< [6] Timer Overflow Interrupt Enable */
00156         uint32_t TOF : 1;              /*!< [7] Timer Overflow Flag */
00157         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
00158     } B;
00159 } hw_ftm_sc_t;
00160 
00161 /*!
00162  * @name Constants and macros for entire FTM_SC register
00163  */
00164 /*@{*/
00165 #define HW_FTM_SC_ADDR(x)        ((x) + 0x0U)
00166 
00167 #define HW_FTM_SC(x)             (*(__IO hw_ftm_sc_t *) HW_FTM_SC_ADDR(x))
00168 #define HW_FTM_SC_RD(x)          (ADDRESS_READ(hw_ftm_sc_t, HW_FTM_SC_ADDR(x)))
00169 #define HW_FTM_SC_WR(x, v)       (ADDRESS_WRITE(hw_ftm_sc_t, HW_FTM_SC_ADDR(x), v))
00170 #define HW_FTM_SC_SET(x, v)      (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) |  (v)))
00171 #define HW_FTM_SC_CLR(x, v)      (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) & ~(v)))
00172 #define HW_FTM_SC_TOG(x, v)      (HW_FTM_SC_WR(x, HW_FTM_SC_RD(x) ^  (v)))
00173 /*@}*/
00174 
00175 /*
00176  * Constants & macros for individual FTM_SC bitfields
00177  */
00178 
00179 /*!
00180  * @name Register FTM_SC, field PS[2:0] (RW)
00181  *
00182  * Selects one of 8 division factors for the clock source selected by CLKS. The
00183  * new prescaler factor affects the clock source on the next system clock cycle
00184  * after the new value is updated into the register bits. This field is write
00185  * protected. It can be written only when MODE[WPDIS] = 1.
00186  *
00187  * Values:
00188  * - 000 - Divide by 1
00189  * - 001 - Divide by 2
00190  * - 010 - Divide by 4
00191  * - 011 - Divide by 8
00192  * - 100 - Divide by 16
00193  * - 101 - Divide by 32
00194  * - 110 - Divide by 64
00195  * - 111 - Divide by 128
00196  */
00197 /*@{*/
00198 #define BP_FTM_SC_PS         (0U)          /*!< Bit position for FTM_SC_PS. */
00199 #define BM_FTM_SC_PS         (0x00000007U) /*!< Bit mask for FTM_SC_PS. */
00200 #define BS_FTM_SC_PS         (3U)          /*!< Bit field size in bits for FTM_SC_PS. */
00201 
00202 /*! @brief Read current value of the FTM_SC_PS field. */
00203 #define BR_FTM_SC_PS(x)      (UNION_READ(hw_ftm_sc_t, HW_FTM_SC_ADDR(x), U, B.PS))
00204 
00205 /*! @brief Format value for bitfield FTM_SC_PS. */
00206 #define BF_FTM_SC_PS(v)      ((uint32_t)((uint32_t)(v) << BP_FTM_SC_PS) & BM_FTM_SC_PS)
00207 
00208 /*! @brief Set the PS field to a new value. */
00209 #define BW_FTM_SC_PS(x, v)   (HW_FTM_SC_WR(x, (HW_FTM_SC_RD(x) & ~BM_FTM_SC_PS) | BF_FTM_SC_PS(v)))
00210 /*@}*/
00211 
00212 /*!
00213  * @name Register FTM_SC, field CLKS[4:3] (RW)
00214  *
00215  * Selects one of the three FTM counter clock sources. This field is write
00216  * protected. It can be written only when MODE[WPDIS] = 1.
00217  *
00218  * Values:
00219  * - 00 - No clock selected. This in effect disables the FTM counter.
00220  * - 01 - System clock
00221  * - 10 - Fixed frequency clock
00222  * - 11 - External clock
00223  */
00224 /*@{*/
00225 #define BP_FTM_SC_CLKS       (3U)          /*!< Bit position for FTM_SC_CLKS. */
00226 #define BM_FTM_SC_CLKS       (0x00000018U) /*!< Bit mask for FTM_SC_CLKS. */
00227 #define BS_FTM_SC_CLKS       (2U)          /*!< Bit field size in bits for FTM_SC_CLKS. */
00228 
00229 /*! @brief Read current value of the FTM_SC_CLKS field. */
00230 #define BR_FTM_SC_CLKS(x)    (UNION_READ(hw_ftm_sc_t, HW_FTM_SC_ADDR(x), U, B.CLKS))
00231 
00232 /*! @brief Format value for bitfield FTM_SC_CLKS. */
00233 #define BF_FTM_SC_CLKS(v)    ((uint32_t)((uint32_t)(v) << BP_FTM_SC_CLKS) & BM_FTM_SC_CLKS)
00234 
00235 /*! @brief Set the CLKS field to a new value. */
00236 #define BW_FTM_SC_CLKS(x, v) (HW_FTM_SC_WR(x, (HW_FTM_SC_RD(x) & ~BM_FTM_SC_CLKS) | BF_FTM_SC_CLKS(v)))
00237 /*@}*/
00238 
00239 /*!
00240  * @name Register FTM_SC, field CPWMS[5] (RW)
00241  *
00242  * Selects CPWM mode. This mode configures the FTM to operate in Up-Down
00243  * Counting mode. This field is write protected. It can be written only when MODE[WPDIS]
00244  * = 1.
00245  *
00246  * Values:
00247  * - 0 - FTM counter operates in Up Counting mode.
00248  * - 1 - FTM counter operates in Up-Down Counting mode.
00249  */
00250 /*@{*/
00251 #define BP_FTM_SC_CPWMS      (5U)          /*!< Bit position for FTM_SC_CPWMS. */
00252 #define BM_FTM_SC_CPWMS      (0x00000020U) /*!< Bit mask for FTM_SC_CPWMS. */
00253 #define BS_FTM_SC_CPWMS      (1U)          /*!< Bit field size in bits for FTM_SC_CPWMS. */
00254 
00255 /*! @brief Read current value of the FTM_SC_CPWMS field. */
00256 #define BR_FTM_SC_CPWMS(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_CPWMS)))
00257 
00258 /*! @brief Format value for bitfield FTM_SC_CPWMS. */
00259 #define BF_FTM_SC_CPWMS(v)   ((uint32_t)((uint32_t)(v) << BP_FTM_SC_CPWMS) & BM_FTM_SC_CPWMS)
00260 
00261 /*! @brief Set the CPWMS field to a new value. */
00262 #define BW_FTM_SC_CPWMS(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_CPWMS), v))
00263 /*@}*/
00264 
00265 /*!
00266  * @name Register FTM_SC, field TOIE[6] (RW)
00267  *
00268  * Enables FTM overflow interrupts.
00269  *
00270  * Values:
00271  * - 0 - Disable TOF interrupts. Use software polling.
00272  * - 1 - Enable TOF interrupts. An interrupt is generated when TOF equals one.
00273  */
00274 /*@{*/
00275 #define BP_FTM_SC_TOIE       (6U)          /*!< Bit position for FTM_SC_TOIE. */
00276 #define BM_FTM_SC_TOIE       (0x00000040U) /*!< Bit mask for FTM_SC_TOIE. */
00277 #define BS_FTM_SC_TOIE       (1U)          /*!< Bit field size in bits for FTM_SC_TOIE. */
00278 
00279 /*! @brief Read current value of the FTM_SC_TOIE field. */
00280 #define BR_FTM_SC_TOIE(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOIE)))
00281 
00282 /*! @brief Format value for bitfield FTM_SC_TOIE. */
00283 #define BF_FTM_SC_TOIE(v)    ((uint32_t)((uint32_t)(v) << BP_FTM_SC_TOIE) & BM_FTM_SC_TOIE)
00284 
00285 /*! @brief Set the TOIE field to a new value. */
00286 #define BW_FTM_SC_TOIE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOIE), v))
00287 /*@}*/
00288 
00289 /*!
00290  * @name Register FTM_SC, field TOF[7] (ROWZ)
00291  *
00292  * Set by hardware when the FTM counter passes the value in the MOD register.
00293  * The TOF bit is cleared by reading the SC register while TOF is set and then
00294  * writing a 0 to TOF bit. Writing a 1 to TOF has no effect. If another FTM overflow
00295  * occurs between the read and write operations, the write operation has no
00296  * effect; therefore, TOF remains set indicating an overflow has occurred. In this
00297  * case, a TOF interrupt request is not lost due to the clearing sequence for a
00298  * previous TOF.
00299  *
00300  * Values:
00301  * - 0 - FTM counter has not overflowed.
00302  * - 1 - FTM counter has overflowed.
00303  */
00304 /*@{*/
00305 #define BP_FTM_SC_TOF        (7U)          /*!< Bit position for FTM_SC_TOF. */
00306 #define BM_FTM_SC_TOF        (0x00000080U) /*!< Bit mask for FTM_SC_TOF. */
00307 #define BS_FTM_SC_TOF        (1U)          /*!< Bit field size in bits for FTM_SC_TOF. */
00308 
00309 /*! @brief Read current value of the FTM_SC_TOF field. */
00310 #define BR_FTM_SC_TOF(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOF)))
00311 
00312 /*! @brief Format value for bitfield FTM_SC_TOF. */
00313 #define BF_FTM_SC_TOF(v)     ((uint32_t)((uint32_t)(v) << BP_FTM_SC_TOF) & BM_FTM_SC_TOF)
00314 
00315 /*! @brief Set the TOF field to a new value. */
00316 #define BW_FTM_SC_TOF(x, v)  (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SC_ADDR(x), BP_FTM_SC_TOF), v))
00317 /*@}*/
00318 
00319 /*******************************************************************************
00320  * HW_FTM_CNT - Counter
00321  ******************************************************************************/
00322 
00323 /*!
00324  * @brief HW_FTM_CNT - Counter (RW)
00325  *
00326  * Reset value: 0x00000000U
00327  *
00328  * The CNT register contains the FTM counter value. Reset clears the CNT
00329  * register. Writing any value to COUNT updates the counter with its initial value,
00330  * CNTIN. When BDM is active, the FTM counter is frozen. This is the value that you
00331  * may read.
00332  */
00333 typedef union _hw_ftm_cnt
00334 {
00335     uint32_t U;
00336     struct _hw_ftm_cnt_bitfields
00337     {
00338         uint32_t COUNT : 16;           /*!< [15:0] Counter Value */
00339         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
00340     } B;
00341 } hw_ftm_cnt_t;
00342 
00343 /*!
00344  * @name Constants and macros for entire FTM_CNT register
00345  */
00346 /*@{*/
00347 #define HW_FTM_CNT_ADDR(x)       ((x) + 0x4U)
00348 
00349 #define HW_FTM_CNT(x)            (*(__IO hw_ftm_cnt_t *) HW_FTM_CNT_ADDR(x))
00350 #define HW_FTM_CNT_RD(x)         (ADDRESS_READ(hw_ftm_cnt_t, HW_FTM_CNT_ADDR(x)))
00351 #define HW_FTM_CNT_WR(x, v)      (ADDRESS_WRITE(hw_ftm_cnt_t, HW_FTM_CNT_ADDR(x), v))
00352 #define HW_FTM_CNT_SET(x, v)     (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) |  (v)))
00353 #define HW_FTM_CNT_CLR(x, v)     (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) & ~(v)))
00354 #define HW_FTM_CNT_TOG(x, v)     (HW_FTM_CNT_WR(x, HW_FTM_CNT_RD(x) ^  (v)))
00355 /*@}*/
00356 
00357 /*
00358  * Constants & macros for individual FTM_CNT bitfields
00359  */
00360 
00361 /*!
00362  * @name Register FTM_CNT, field COUNT[15:0] (RW)
00363  */
00364 /*@{*/
00365 #define BP_FTM_CNT_COUNT     (0U)          /*!< Bit position for FTM_CNT_COUNT. */
00366 #define BM_FTM_CNT_COUNT     (0x0000FFFFU) /*!< Bit mask for FTM_CNT_COUNT. */
00367 #define BS_FTM_CNT_COUNT     (16U)         /*!< Bit field size in bits for FTM_CNT_COUNT. */
00368 
00369 /*! @brief Read current value of the FTM_CNT_COUNT field. */
00370 #define BR_FTM_CNT_COUNT(x)  (UNION_READ(hw_ftm_cnt_t, HW_FTM_CNT_ADDR(x), U, B.COUNT))
00371 
00372 /*! @brief Format value for bitfield FTM_CNT_COUNT. */
00373 #define BF_FTM_CNT_COUNT(v)  ((uint32_t)((uint32_t)(v) << BP_FTM_CNT_COUNT) & BM_FTM_CNT_COUNT)
00374 
00375 /*! @brief Set the COUNT field to a new value. */
00376 #define BW_FTM_CNT_COUNT(x, v) (HW_FTM_CNT_WR(x, (HW_FTM_CNT_RD(x) & ~BM_FTM_CNT_COUNT) | BF_FTM_CNT_COUNT(v)))
00377 /*@}*/
00378 
00379 /*******************************************************************************
00380  * HW_FTM_MOD - Modulo
00381  ******************************************************************************/
00382 
00383 /*!
00384  * @brief HW_FTM_MOD - Modulo (RW)
00385  *
00386  * Reset value: 0x00000000U
00387  *
00388  * The Modulo register contains the modulo value for the FTM counter. After the
00389  * FTM counter reaches the modulo value, the overflow flag (TOF) becomes set at
00390  * the next clock, and the next value of FTM counter depends on the selected
00391  * counting method; see Counter. Writing to the MOD register latches the value into a
00392  * buffer. The MOD register is updated with the value of its write buffer
00393  * according to Registers updated from write buffers. If FTMEN = 0, this write coherency
00394  * mechanism may be manually reset by writing to the SC register whether BDM is
00395  * active or not. Initialize the FTM counter, by writing to CNT, before writing
00396  * to the MOD register to avoid confusion about when the first counter overflow
00397  * will occur.
00398  */
00399 typedef union _hw_ftm_mod
00400 {
00401     uint32_t U;
00402     struct _hw_ftm_mod_bitfields
00403     {
00404         uint32_t MOD : 16;             /*!< [15:0]  */
00405         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
00406     } B;
00407 } hw_ftm_mod_t;
00408 
00409 /*!
00410  * @name Constants and macros for entire FTM_MOD register
00411  */
00412 /*@{*/
00413 #define HW_FTM_MOD_ADDR(x)       ((x) + 0x8U)
00414 
00415 #define HW_FTM_MOD(x)            (*(__IO hw_ftm_mod_t *) HW_FTM_MOD_ADDR(x))
00416 #define HW_FTM_MOD_RD(x)         (ADDRESS_READ(hw_ftm_mod_t, HW_FTM_MOD_ADDR(x)))
00417 #define HW_FTM_MOD_WR(x, v)      (ADDRESS_WRITE(hw_ftm_mod_t, HW_FTM_MOD_ADDR(x), v))
00418 #define HW_FTM_MOD_SET(x, v)     (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) |  (v)))
00419 #define HW_FTM_MOD_CLR(x, v)     (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) & ~(v)))
00420 #define HW_FTM_MOD_TOG(x, v)     (HW_FTM_MOD_WR(x, HW_FTM_MOD_RD(x) ^  (v)))
00421 /*@}*/
00422 
00423 /*
00424  * Constants & macros for individual FTM_MOD bitfields
00425  */
00426 
00427 /*!
00428  * @name Register FTM_MOD, field MOD[15:0] (RW)
00429  *
00430  * Modulo Value
00431  */
00432 /*@{*/
00433 #define BP_FTM_MOD_MOD       (0U)          /*!< Bit position for FTM_MOD_MOD. */
00434 #define BM_FTM_MOD_MOD       (0x0000FFFFU) /*!< Bit mask for FTM_MOD_MOD. */
00435 #define BS_FTM_MOD_MOD       (16U)         /*!< Bit field size in bits for FTM_MOD_MOD. */
00436 
00437 /*! @brief Read current value of the FTM_MOD_MOD field. */
00438 #define BR_FTM_MOD_MOD(x)    (UNION_READ(hw_ftm_mod_t, HW_FTM_MOD_ADDR(x), U, B.MOD))
00439 
00440 /*! @brief Format value for bitfield FTM_MOD_MOD. */
00441 #define BF_FTM_MOD_MOD(v)    ((uint32_t)((uint32_t)(v) << BP_FTM_MOD_MOD) & BM_FTM_MOD_MOD)
00442 
00443 /*! @brief Set the MOD field to a new value. */
00444 #define BW_FTM_MOD_MOD(x, v) (HW_FTM_MOD_WR(x, (HW_FTM_MOD_RD(x) & ~BM_FTM_MOD_MOD) | BF_FTM_MOD_MOD(v)))
00445 /*@}*/
00446 
00447 /*******************************************************************************
00448  * HW_FTM_CnSC - Channel (n) Status And Control
00449  ******************************************************************************/
00450 
00451 /*!
00452  * @brief HW_FTM_CnSC - Channel (n) Status And Control (RW)
00453  *
00454  * Reset value: 0x00000000U
00455  *
00456  * CnSC contains the channel-interrupt-status flag and control bits used to
00457  * configure the interrupt enable, channel configuration, and pin function. Mode,
00458  * edge, and level selection DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode
00459  * Configuration X X X XX 0 Pin not used for FTM-revert the channel pin to general
00460  * purpose I/O or other peripheral control 0 0 0 0 1 Input Capture Capture on Rising
00461  * Edge Only 10 Capture on Falling Edge Only 11 Capture on Rising or Falling Edge
00462  * 1 1 Output Compare Toggle Output on match 10 Clear Output on match 11 Set
00463  * Output on match 1X 10 Edge-Aligned PWM High-true pulses (clear Output on match)
00464  * X1 Low-true pulses (set Output on match) 1 XX 10 Center-Aligned PWM High-true
00465  * pulses (clear Output on match-up) X1 Low-true pulses (set Output on match-up) 1
00466  * 0 XX 10 Combine PWM High-true pulses (set on channel (n) match, and clear on
00467  * channel (n+1) match) X1 Low-true pulses (clear on channel (n) match, and set
00468  * on channel (n+1) match) 1 0 0 X0 See the following table (#ModeSel2Table). Dual
00469  * Edge Capture One-Shot Capture mode X1 Continuous Capture mode Dual Edge
00470  * Capture mode - edge polarity selection ELSnB ELSnA Channel Port Enable Detected
00471  * Edges 0 0 Disabled No edge 0 1 Enabled Rising edge 1 0 Enabled Falling edge 1 1
00472  * Enabled Rising and falling edges
00473  */
00474 typedef union _hw_ftm_cnsc
00475 {
00476     uint32_t U;
00477     struct _hw_ftm_cnsc_bitfields
00478     {
00479         uint32_t DMA : 1;              /*!< [0] DMA Enable */
00480         uint32_t RESERVED0 : 1;        /*!< [1]  */
00481         uint32_t ELSA : 1;             /*!< [2] Edge or Level Select */
00482         uint32_t ELSB : 1;             /*!< [3] Edge or Level Select */
00483         uint32_t MSA : 1;              /*!< [4] Channel Mode Select */
00484         uint32_t MSB : 1;              /*!< [5] Channel Mode Select */
00485         uint32_t CHIE : 1;             /*!< [6] Channel Interrupt Enable */
00486         uint32_t CHF : 1;              /*!< [7] Channel Flag */
00487         uint32_t RESERVED1 : 24;       /*!< [31:8]  */
00488     } B;
00489 } hw_ftm_cnsc_t;
00490 
00491 /*!
00492  * @name Constants and macros for entire FTM_CnSC register
00493  */
00494 /*@{*/
00495 #define HW_FTM_CnSC_COUNT (8U)
00496 
00497 #define HW_FTM_CnSC_ADDR(x, n)   ((x) + 0xCU + (0x8U * (n)))
00498 
00499 #define HW_FTM_CnSC(x, n)        (*(__IO hw_ftm_cnsc_t *) HW_FTM_CnSC_ADDR(x, n))
00500 #define HW_FTM_CnSC_RD(x, n)     (ADDRESS_READ(hw_ftm_cnsc_t, HW_FTM_CnSC_ADDR(x, n)))
00501 #define HW_FTM_CnSC_WR(x, n, v)  (ADDRESS_WRITE(hw_ftm_cnsc_t, HW_FTM_CnSC_ADDR(x, n), v))
00502 #define HW_FTM_CnSC_SET(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) |  (v)))
00503 #define HW_FTM_CnSC_CLR(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) & ~(v)))
00504 #define HW_FTM_CnSC_TOG(x, n, v) (HW_FTM_CnSC_WR(x, n, HW_FTM_CnSC_RD(x, n) ^  (v)))
00505 /*@}*/
00506 
00507 /*
00508  * Constants & macros for individual FTM_CnSC bitfields
00509  */
00510 
00511 /*!
00512  * @name Register FTM_CnSC, field DMA[0] (RW)
00513  *
00514  * Enables DMA transfers for the channel.
00515  *
00516  * Values:
00517  * - 0 - Disable DMA transfers.
00518  * - 1 - Enable DMA transfers.
00519  */
00520 /*@{*/
00521 #define BP_FTM_CnSC_DMA      (0U)          /*!< Bit position for FTM_CnSC_DMA. */
00522 #define BM_FTM_CnSC_DMA      (0x00000001U) /*!< Bit mask for FTM_CnSC_DMA. */
00523 #define BS_FTM_CnSC_DMA      (1U)          /*!< Bit field size in bits for FTM_CnSC_DMA. */
00524 
00525 /*! @brief Read current value of the FTM_CnSC_DMA field. */
00526 #define BR_FTM_CnSC_DMA(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_DMA)))
00527 
00528 /*! @brief Format value for bitfield FTM_CnSC_DMA. */
00529 #define BF_FTM_CnSC_DMA(v)   ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_DMA) & BM_FTM_CnSC_DMA)
00530 
00531 /*! @brief Set the DMA field to a new value. */
00532 #define BW_FTM_CnSC_DMA(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_DMA), v))
00533 /*@}*/
00534 
00535 /*!
00536  * @name Register FTM_CnSC, field ELSA[2] (RW)
00537  *
00538  * The functionality of ELSB and ELSA depends on the channel mode. See
00539  * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
00540  * = 1.
00541  */
00542 /*@{*/
00543 #define BP_FTM_CnSC_ELSA     (2U)          /*!< Bit position for FTM_CnSC_ELSA. */
00544 #define BM_FTM_CnSC_ELSA     (0x00000004U) /*!< Bit mask for FTM_CnSC_ELSA. */
00545 #define BS_FTM_CnSC_ELSA     (1U)          /*!< Bit field size in bits for FTM_CnSC_ELSA. */
00546 
00547 /*! @brief Read current value of the FTM_CnSC_ELSA field. */
00548 #define BR_FTM_CnSC_ELSA(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSA)))
00549 
00550 /*! @brief Format value for bitfield FTM_CnSC_ELSA. */
00551 #define BF_FTM_CnSC_ELSA(v)  ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_ELSA) & BM_FTM_CnSC_ELSA)
00552 
00553 /*! @brief Set the ELSA field to a new value. */
00554 #define BW_FTM_CnSC_ELSA(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSA), v))
00555 /*@}*/
00556 
00557 /*!
00558  * @name Register FTM_CnSC, field ELSB[3] (RW)
00559  *
00560  * The functionality of ELSB and ELSA depends on the channel mode. See
00561  * #ModeSel1Table. This field is write protected. It can be written only when MODE[WPDIS]
00562  * = 1.
00563  */
00564 /*@{*/
00565 #define BP_FTM_CnSC_ELSB     (3U)          /*!< Bit position for FTM_CnSC_ELSB. */
00566 #define BM_FTM_CnSC_ELSB     (0x00000008U) /*!< Bit mask for FTM_CnSC_ELSB. */
00567 #define BS_FTM_CnSC_ELSB     (1U)          /*!< Bit field size in bits for FTM_CnSC_ELSB. */
00568 
00569 /*! @brief Read current value of the FTM_CnSC_ELSB field. */
00570 #define BR_FTM_CnSC_ELSB(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSB)))
00571 
00572 /*! @brief Format value for bitfield FTM_CnSC_ELSB. */
00573 #define BF_FTM_CnSC_ELSB(v)  ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_ELSB) & BM_FTM_CnSC_ELSB)
00574 
00575 /*! @brief Set the ELSB field to a new value. */
00576 #define BW_FTM_CnSC_ELSB(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_ELSB), v))
00577 /*@}*/
00578 
00579 /*!
00580  * @name Register FTM_CnSC, field MSA[4] (RW)
00581  *
00582  * Used for further selections in the channel logic. Its functionality is
00583  * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
00584  * can be written only when MODE[WPDIS] = 1.
00585  */
00586 /*@{*/
00587 #define BP_FTM_CnSC_MSA      (4U)          /*!< Bit position for FTM_CnSC_MSA. */
00588 #define BM_FTM_CnSC_MSA      (0x00000010U) /*!< Bit mask for FTM_CnSC_MSA. */
00589 #define BS_FTM_CnSC_MSA      (1U)          /*!< Bit field size in bits for FTM_CnSC_MSA. */
00590 
00591 /*! @brief Read current value of the FTM_CnSC_MSA field. */
00592 #define BR_FTM_CnSC_MSA(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSA)))
00593 
00594 /*! @brief Format value for bitfield FTM_CnSC_MSA. */
00595 #define BF_FTM_CnSC_MSA(v)   ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_MSA) & BM_FTM_CnSC_MSA)
00596 
00597 /*! @brief Set the MSA field to a new value. */
00598 #define BW_FTM_CnSC_MSA(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSA), v))
00599 /*@}*/
00600 
00601 /*!
00602  * @name Register FTM_CnSC, field MSB[5] (RW)
00603  *
00604  * Used for further selections in the channel logic. Its functionality is
00605  * dependent on the channel mode. See #ModeSel1Table. This field is write protected. It
00606  * can be written only when MODE[WPDIS] = 1.
00607  */
00608 /*@{*/
00609 #define BP_FTM_CnSC_MSB      (5U)          /*!< Bit position for FTM_CnSC_MSB. */
00610 #define BM_FTM_CnSC_MSB      (0x00000020U) /*!< Bit mask for FTM_CnSC_MSB. */
00611 #define BS_FTM_CnSC_MSB      (1U)          /*!< Bit field size in bits for FTM_CnSC_MSB. */
00612 
00613 /*! @brief Read current value of the FTM_CnSC_MSB field. */
00614 #define BR_FTM_CnSC_MSB(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSB)))
00615 
00616 /*! @brief Format value for bitfield FTM_CnSC_MSB. */
00617 #define BF_FTM_CnSC_MSB(v)   ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_MSB) & BM_FTM_CnSC_MSB)
00618 
00619 /*! @brief Set the MSB field to a new value. */
00620 #define BW_FTM_CnSC_MSB(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_MSB), v))
00621 /*@}*/
00622 
00623 /*!
00624  * @name Register FTM_CnSC, field CHIE[6] (RW)
00625  *
00626  * Enables channel interrupts.
00627  *
00628  * Values:
00629  * - 0 - Disable channel interrupts. Use software polling.
00630  * - 1 - Enable channel interrupts.
00631  */
00632 /*@{*/
00633 #define BP_FTM_CnSC_CHIE     (6U)          /*!< Bit position for FTM_CnSC_CHIE. */
00634 #define BM_FTM_CnSC_CHIE     (0x00000040U) /*!< Bit mask for FTM_CnSC_CHIE. */
00635 #define BS_FTM_CnSC_CHIE     (1U)          /*!< Bit field size in bits for FTM_CnSC_CHIE. */
00636 
00637 /*! @brief Read current value of the FTM_CnSC_CHIE field. */
00638 #define BR_FTM_CnSC_CHIE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHIE)))
00639 
00640 /*! @brief Format value for bitfield FTM_CnSC_CHIE. */
00641 #define BF_FTM_CnSC_CHIE(v)  ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_CHIE) & BM_FTM_CnSC_CHIE)
00642 
00643 /*! @brief Set the CHIE field to a new value. */
00644 #define BW_FTM_CnSC_CHIE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHIE), v))
00645 /*@}*/
00646 
00647 /*!
00648  * @name Register FTM_CnSC, field CHF[7] (ROWZ)
00649  *
00650  * Set by hardware when an event occurs on the channel. CHF is cleared by
00651  * reading the CSC register while CHnF is set and then writing a 0 to the CHF bit.
00652  * Writing a 1 to CHF has no effect. If another event occurs between the read and
00653  * write operations, the write operation has no effect; therefore, CHF remains set
00654  * indicating an event has occurred. In this case a CHF interrupt request is not
00655  * lost due to the clearing sequence for a previous CHF.
00656  *
00657  * Values:
00658  * - 0 - No channel event has occurred.
00659  * - 1 - A channel event has occurred.
00660  */
00661 /*@{*/
00662 #define BP_FTM_CnSC_CHF      (7U)          /*!< Bit position for FTM_CnSC_CHF. */
00663 #define BM_FTM_CnSC_CHF      (0x00000080U) /*!< Bit mask for FTM_CnSC_CHF. */
00664 #define BS_FTM_CnSC_CHF      (1U)          /*!< Bit field size in bits for FTM_CnSC_CHF. */
00665 
00666 /*! @brief Read current value of the FTM_CnSC_CHF field. */
00667 #define BR_FTM_CnSC_CHF(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHF)))
00668 
00669 /*! @brief Format value for bitfield FTM_CnSC_CHF. */
00670 #define BF_FTM_CnSC_CHF(v)   ((uint32_t)((uint32_t)(v) << BP_FTM_CnSC_CHF) & BM_FTM_CnSC_CHF)
00671 
00672 /*! @brief Set the CHF field to a new value. */
00673 #define BW_FTM_CnSC_CHF(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_CnSC_ADDR(x, n), BP_FTM_CnSC_CHF), v))
00674 /*@}*/
00675 /*******************************************************************************
00676  * HW_FTM_CnV - Channel (n) Value
00677  ******************************************************************************/
00678 
00679 /*!
00680  * @brief HW_FTM_CnV - Channel (n) Value (RW)
00681  *
00682  * Reset value: 0x00000000U
00683  *
00684  * These registers contain the captured FTM counter value for the input modes or
00685  * the match value for the output modes. In Input Capture, Capture Test, and
00686  * Dual Edge Capture modes, any write to a CnV register is ignored. In output modes,
00687  * writing to a CnV register latches the value into a buffer. A CnV register is
00688  * updated with the value of its write buffer according to Registers updated from
00689  * write buffers. If FTMEN = 0, this write coherency mechanism may be manually
00690  * reset by writing to the CnSC register whether BDM mode is active or not.
00691  */
00692 typedef union _hw_ftm_cnv
00693 {
00694     uint32_t U;
00695     struct _hw_ftm_cnv_bitfields
00696     {
00697         uint32_t VAL : 16;             /*!< [15:0] Channel Value */
00698         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
00699     } B;
00700 } hw_ftm_cnv_t;
00701 
00702 /*!
00703  * @name Constants and macros for entire FTM_CnV register
00704  */
00705 /*@{*/
00706 #define HW_FTM_CnV_COUNT (8U)
00707 
00708 #define HW_FTM_CnV_ADDR(x, n)    ((x) + 0x10U + (0x8U * (n)))
00709 
00710 #define HW_FTM_CnV(x, n)         (*(__IO hw_ftm_cnv_t *) HW_FTM_CnV_ADDR(x, n))
00711 #define HW_FTM_CnV_RD(x, n)      (ADDRESS_READ(hw_ftm_cnv_t, HW_FTM_CnV_ADDR(x, n)))
00712 #define HW_FTM_CnV_WR(x, n, v)   (ADDRESS_WRITE(hw_ftm_cnv_t, HW_FTM_CnV_ADDR(x, n), v))
00713 #define HW_FTM_CnV_SET(x, n, v)  (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) |  (v)))
00714 #define HW_FTM_CnV_CLR(x, n, v)  (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) & ~(v)))
00715 #define HW_FTM_CnV_TOG(x, n, v)  (HW_FTM_CnV_WR(x, n, HW_FTM_CnV_RD(x, n) ^  (v)))
00716 /*@}*/
00717 
00718 /*
00719  * Constants & macros for individual FTM_CnV bitfields
00720  */
00721 
00722 /*!
00723  * @name Register FTM_CnV, field VAL[15:0] (RW)
00724  *
00725  * Captured FTM counter value of the input modes or the match value for the
00726  * output modes
00727  */
00728 /*@{*/
00729 #define BP_FTM_CnV_VAL       (0U)          /*!< Bit position for FTM_CnV_VAL. */
00730 #define BM_FTM_CnV_VAL       (0x0000FFFFU) /*!< Bit mask for FTM_CnV_VAL. */
00731 #define BS_FTM_CnV_VAL       (16U)         /*!< Bit field size in bits for FTM_CnV_VAL. */
00732 
00733 /*! @brief Read current value of the FTM_CnV_VAL field. */
00734 #define BR_FTM_CnV_VAL(x, n) (UNION_READ(hw_ftm_cnv_t, HW_FTM_CnV_ADDR(x, n), U, B.VAL))
00735 
00736 /*! @brief Format value for bitfield FTM_CnV_VAL. */
00737 #define BF_FTM_CnV_VAL(v)    ((uint32_t)((uint32_t)(v) << BP_FTM_CnV_VAL) & BM_FTM_CnV_VAL)
00738 
00739 /*! @brief Set the VAL field to a new value. */
00740 #define BW_FTM_CnV_VAL(x, n, v) (HW_FTM_CnV_WR(x, n, (HW_FTM_CnV_RD(x, n) & ~BM_FTM_CnV_VAL) | BF_FTM_CnV_VAL(v)))
00741 /*@}*/
00742 
00743 /*******************************************************************************
00744  * HW_FTM_CNTIN - Counter Initial Value
00745  ******************************************************************************/
00746 
00747 /*!
00748  * @brief HW_FTM_CNTIN - Counter Initial Value (RW)
00749  *
00750  * Reset value: 0x00000000U
00751  *
00752  * The Counter Initial Value register contains the initial value for the FTM
00753  * counter. Writing to the CNTIN register latches the value into a buffer. The CNTIN
00754  * register is updated with the value of its write buffer according to Registers
00755  * updated from write buffers. When the FTM clock is initially selected, by
00756  * writing a non-zero value to the CLKS bits, the FTM counter starts with the value
00757  * 0x0000. To avoid this behavior, before the first write to select the FTM clock,
00758  * write the new value to the the CNTIN register and then initialize the FTM
00759  * counter by writing any value to the CNT register.
00760  */
00761 typedef union _hw_ftm_cntin
00762 {
00763     uint32_t U;
00764     struct _hw_ftm_cntin_bitfields
00765     {
00766         uint32_t INIT : 16;            /*!< [15:0]  */
00767         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
00768     } B;
00769 } hw_ftm_cntin_t;
00770 
00771 /*!
00772  * @name Constants and macros for entire FTM_CNTIN register
00773  */
00774 /*@{*/
00775 #define HW_FTM_CNTIN_ADDR(x)     ((x) + 0x4CU)
00776 
00777 #define HW_FTM_CNTIN(x)          (*(__IO hw_ftm_cntin_t *) HW_FTM_CNTIN_ADDR(x))
00778 #define HW_FTM_CNTIN_RD(x)       (ADDRESS_READ(hw_ftm_cntin_t, HW_FTM_CNTIN_ADDR(x)))
00779 #define HW_FTM_CNTIN_WR(x, v)    (ADDRESS_WRITE(hw_ftm_cntin_t, HW_FTM_CNTIN_ADDR(x), v))
00780 #define HW_FTM_CNTIN_SET(x, v)   (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) |  (v)))
00781 #define HW_FTM_CNTIN_CLR(x, v)   (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) & ~(v)))
00782 #define HW_FTM_CNTIN_TOG(x, v)   (HW_FTM_CNTIN_WR(x, HW_FTM_CNTIN_RD(x) ^  (v)))
00783 /*@}*/
00784 
00785 /*
00786  * Constants & macros for individual FTM_CNTIN bitfields
00787  */
00788 
00789 /*!
00790  * @name Register FTM_CNTIN, field INIT[15:0] (RW)
00791  *
00792  * Initial Value Of The FTM Counter
00793  */
00794 /*@{*/
00795 #define BP_FTM_CNTIN_INIT    (0U)          /*!< Bit position for FTM_CNTIN_INIT. */
00796 #define BM_FTM_CNTIN_INIT    (0x0000FFFFU) /*!< Bit mask for FTM_CNTIN_INIT. */
00797 #define BS_FTM_CNTIN_INIT    (16U)         /*!< Bit field size in bits for FTM_CNTIN_INIT. */
00798 
00799 /*! @brief Read current value of the FTM_CNTIN_INIT field. */
00800 #define BR_FTM_CNTIN_INIT(x) (UNION_READ(hw_ftm_cntin_t, HW_FTM_CNTIN_ADDR(x), U, B.INIT))
00801 
00802 /*! @brief Format value for bitfield FTM_CNTIN_INIT. */
00803 #define BF_FTM_CNTIN_INIT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CNTIN_INIT) & BM_FTM_CNTIN_INIT)
00804 
00805 /*! @brief Set the INIT field to a new value. */
00806 #define BW_FTM_CNTIN_INIT(x, v) (HW_FTM_CNTIN_WR(x, (HW_FTM_CNTIN_RD(x) & ~BM_FTM_CNTIN_INIT) | BF_FTM_CNTIN_INIT(v)))
00807 /*@}*/
00808 
00809 /*******************************************************************************
00810  * HW_FTM_STATUS - Capture And Compare Status
00811  ******************************************************************************/
00812 
00813 /*!
00814  * @brief HW_FTM_STATUS - Capture And Compare Status (RW)
00815  *
00816  * Reset value: 0x00000000U
00817  *
00818  * The STATUS register contains a copy of the status flag CHnF bit in CnSC for
00819  * each FTM channel for software convenience. Each CHnF bit in STATUS is a mirror
00820  * of CHnF bit in CnSC. All CHnF bits can be checked using only one read of
00821  * STATUS. All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to
00822  * STATUS. Hardware sets the individual channel flags when an event occurs on the
00823  * channel. CHnF is cleared by reading STATUS while CHnF is set and then writing
00824  * a 0 to the CHnF bit. Writing a 1 to CHnF has no effect. If another event
00825  * occurs between the read and write operations, the write operation has no effect;
00826  * therefore, CHnF remains set indicating an event has occurred. In this case, a
00827  * CHnF interrupt request is not lost due to the clearing sequence for a previous
00828  * CHnF. The STATUS register should be used only in Combine mode.
00829  */
00830 typedef union _hw_ftm_status
00831 {
00832     uint32_t U;
00833     struct _hw_ftm_status_bitfields
00834     {
00835         uint32_t CH0F : 1;             /*!< [0] Channel 0 Flag */
00836         uint32_t CH1F : 1;             /*!< [1] Channel 1 Flag */
00837         uint32_t CH2F : 1;             /*!< [2] Channel 2 Flag */
00838         uint32_t CH3F : 1;             /*!< [3] Channel 3 Flag */
00839         uint32_t CH4F : 1;             /*!< [4] Channel 4 Flag */
00840         uint32_t CH5F : 1;             /*!< [5] Channel 5 Flag */
00841         uint32_t CH6F : 1;             /*!< [6] Channel 6 Flag */
00842         uint32_t CH7F : 1;             /*!< [7] Channel 7 Flag */
00843         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
00844     } B;
00845 } hw_ftm_status_t;
00846 
00847 /*!
00848  * @name Constants and macros for entire FTM_STATUS register
00849  */
00850 /*@{*/
00851 #define HW_FTM_STATUS_ADDR(x)    ((x) + 0x50U)
00852 
00853 #define HW_FTM_STATUS(x)         (*(__IO hw_ftm_status_t *) HW_FTM_STATUS_ADDR(x))
00854 #define HW_FTM_STATUS_RD(x)      (ADDRESS_READ(hw_ftm_status_t, HW_FTM_STATUS_ADDR(x)))
00855 #define HW_FTM_STATUS_WR(x, v)   (ADDRESS_WRITE(hw_ftm_status_t, HW_FTM_STATUS_ADDR(x), v))
00856 #define HW_FTM_STATUS_SET(x, v)  (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) |  (v)))
00857 #define HW_FTM_STATUS_CLR(x, v)  (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) & ~(v)))
00858 #define HW_FTM_STATUS_TOG(x, v)  (HW_FTM_STATUS_WR(x, HW_FTM_STATUS_RD(x) ^  (v)))
00859 /*@}*/
00860 
00861 /*
00862  * Constants & macros for individual FTM_STATUS bitfields
00863  */
00864 
00865 /*!
00866  * @name Register FTM_STATUS, field CH0F[0] (W1C)
00867  *
00868  * See the register description.
00869  *
00870  * Values:
00871  * - 0 - No channel event has occurred.
00872  * - 1 - A channel event has occurred.
00873  */
00874 /*@{*/
00875 #define BP_FTM_STATUS_CH0F   (0U)          /*!< Bit position for FTM_STATUS_CH0F. */
00876 #define BM_FTM_STATUS_CH0F   (0x00000001U) /*!< Bit mask for FTM_STATUS_CH0F. */
00877 #define BS_FTM_STATUS_CH0F   (1U)          /*!< Bit field size in bits for FTM_STATUS_CH0F. */
00878 
00879 /*! @brief Read current value of the FTM_STATUS_CH0F field. */
00880 #define BR_FTM_STATUS_CH0F(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH0F)))
00881 
00882 /*! @brief Format value for bitfield FTM_STATUS_CH0F. */
00883 #define BF_FTM_STATUS_CH0F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH0F) & BM_FTM_STATUS_CH0F)
00884 
00885 /*! @brief Set the CH0F field to a new value. */
00886 #define BW_FTM_STATUS_CH0F(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH0F), v))
00887 /*@}*/
00888 
00889 /*!
00890  * @name Register FTM_STATUS, field CH1F[1] (W1C)
00891  *
00892  * See the register description.
00893  *
00894  * Values:
00895  * - 0 - No channel event has occurred.
00896  * - 1 - A channel event has occurred.
00897  */
00898 /*@{*/
00899 #define BP_FTM_STATUS_CH1F   (1U)          /*!< Bit position for FTM_STATUS_CH1F. */
00900 #define BM_FTM_STATUS_CH1F   (0x00000002U) /*!< Bit mask for FTM_STATUS_CH1F. */
00901 #define BS_FTM_STATUS_CH1F   (1U)          /*!< Bit field size in bits for FTM_STATUS_CH1F. */
00902 
00903 /*! @brief Read current value of the FTM_STATUS_CH1F field. */
00904 #define BR_FTM_STATUS_CH1F(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH1F)))
00905 
00906 /*! @brief Format value for bitfield FTM_STATUS_CH1F. */
00907 #define BF_FTM_STATUS_CH1F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH1F) & BM_FTM_STATUS_CH1F)
00908 
00909 /*! @brief Set the CH1F field to a new value. */
00910 #define BW_FTM_STATUS_CH1F(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH1F), v))
00911 /*@}*/
00912 
00913 /*!
00914  * @name Register FTM_STATUS, field CH2F[2] (W1C)
00915  *
00916  * See the register description.
00917  *
00918  * Values:
00919  * - 0 - No channel event has occurred.
00920  * - 1 - A channel event has occurred.
00921  */
00922 /*@{*/
00923 #define BP_FTM_STATUS_CH2F   (2U)          /*!< Bit position for FTM_STATUS_CH2F. */
00924 #define BM_FTM_STATUS_CH2F   (0x00000004U) /*!< Bit mask for FTM_STATUS_CH2F. */
00925 #define BS_FTM_STATUS_CH2F   (1U)          /*!< Bit field size in bits for FTM_STATUS_CH2F. */
00926 
00927 /*! @brief Read current value of the FTM_STATUS_CH2F field. */
00928 #define BR_FTM_STATUS_CH2F(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH2F)))
00929 
00930 /*! @brief Format value for bitfield FTM_STATUS_CH2F. */
00931 #define BF_FTM_STATUS_CH2F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH2F) & BM_FTM_STATUS_CH2F)
00932 
00933 /*! @brief Set the CH2F field to a new value. */
00934 #define BW_FTM_STATUS_CH2F(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH2F), v))
00935 /*@}*/
00936 
00937 /*!
00938  * @name Register FTM_STATUS, field CH3F[3] (W1C)
00939  *
00940  * See the register description.
00941  *
00942  * Values:
00943  * - 0 - No channel event has occurred.
00944  * - 1 - A channel event has occurred.
00945  */
00946 /*@{*/
00947 #define BP_FTM_STATUS_CH3F   (3U)          /*!< Bit position for FTM_STATUS_CH3F. */
00948 #define BM_FTM_STATUS_CH3F   (0x00000008U) /*!< Bit mask for FTM_STATUS_CH3F. */
00949 #define BS_FTM_STATUS_CH3F   (1U)          /*!< Bit field size in bits for FTM_STATUS_CH3F. */
00950 
00951 /*! @brief Read current value of the FTM_STATUS_CH3F field. */
00952 #define BR_FTM_STATUS_CH3F(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH3F)))
00953 
00954 /*! @brief Format value for bitfield FTM_STATUS_CH3F. */
00955 #define BF_FTM_STATUS_CH3F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH3F) & BM_FTM_STATUS_CH3F)
00956 
00957 /*! @brief Set the CH3F field to a new value. */
00958 #define BW_FTM_STATUS_CH3F(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH3F), v))
00959 /*@}*/
00960 
00961 /*!
00962  * @name Register FTM_STATUS, field CH4F[4] (W1C)
00963  *
00964  * See the register description.
00965  *
00966  * Values:
00967  * - 0 - No channel event has occurred.
00968  * - 1 - A channel event has occurred.
00969  */
00970 /*@{*/
00971 #define BP_FTM_STATUS_CH4F   (4U)          /*!< Bit position for FTM_STATUS_CH4F. */
00972 #define BM_FTM_STATUS_CH4F   (0x00000010U) /*!< Bit mask for FTM_STATUS_CH4F. */
00973 #define BS_FTM_STATUS_CH4F   (1U)          /*!< Bit field size in bits for FTM_STATUS_CH4F. */
00974 
00975 /*! @brief Read current value of the FTM_STATUS_CH4F field. */
00976 #define BR_FTM_STATUS_CH4F(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH4F)))
00977 
00978 /*! @brief Format value for bitfield FTM_STATUS_CH4F. */
00979 #define BF_FTM_STATUS_CH4F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH4F) & BM_FTM_STATUS_CH4F)
00980 
00981 /*! @brief Set the CH4F field to a new value. */
00982 #define BW_FTM_STATUS_CH4F(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH4F), v))
00983 /*@}*/
00984 
00985 /*!
00986  * @name Register FTM_STATUS, field CH5F[5] (W1C)
00987  *
00988  * See the register description.
00989  *
00990  * Values:
00991  * - 0 - No channel event has occurred.
00992  * - 1 - A channel event has occurred.
00993  */
00994 /*@{*/
00995 #define BP_FTM_STATUS_CH5F   (5U)          /*!< Bit position for FTM_STATUS_CH5F. */
00996 #define BM_FTM_STATUS_CH5F   (0x00000020U) /*!< Bit mask for FTM_STATUS_CH5F. */
00997 #define BS_FTM_STATUS_CH5F   (1U)          /*!< Bit field size in bits for FTM_STATUS_CH5F. */
00998 
00999 /*! @brief Read current value of the FTM_STATUS_CH5F field. */
01000 #define BR_FTM_STATUS_CH5F(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH5F)))
01001 
01002 /*! @brief Format value for bitfield FTM_STATUS_CH5F. */
01003 #define BF_FTM_STATUS_CH5F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH5F) & BM_FTM_STATUS_CH5F)
01004 
01005 /*! @brief Set the CH5F field to a new value. */
01006 #define BW_FTM_STATUS_CH5F(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH5F), v))
01007 /*@}*/
01008 
01009 /*!
01010  * @name Register FTM_STATUS, field CH6F[6] (W1C)
01011  *
01012  * See the register description.
01013  *
01014  * Values:
01015  * - 0 - No channel event has occurred.
01016  * - 1 - A channel event has occurred.
01017  */
01018 /*@{*/
01019 #define BP_FTM_STATUS_CH6F   (6U)          /*!< Bit position for FTM_STATUS_CH6F. */
01020 #define BM_FTM_STATUS_CH6F   (0x00000040U) /*!< Bit mask for FTM_STATUS_CH6F. */
01021 #define BS_FTM_STATUS_CH6F   (1U)          /*!< Bit field size in bits for FTM_STATUS_CH6F. */
01022 
01023 /*! @brief Read current value of the FTM_STATUS_CH6F field. */
01024 #define BR_FTM_STATUS_CH6F(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH6F)))
01025 
01026 /*! @brief Format value for bitfield FTM_STATUS_CH6F. */
01027 #define BF_FTM_STATUS_CH6F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH6F) & BM_FTM_STATUS_CH6F)
01028 
01029 /*! @brief Set the CH6F field to a new value. */
01030 #define BW_FTM_STATUS_CH6F(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH6F), v))
01031 /*@}*/
01032 
01033 /*!
01034  * @name Register FTM_STATUS, field CH7F[7] (W1C)
01035  *
01036  * See the register description.
01037  *
01038  * Values:
01039  * - 0 - No channel event has occurred.
01040  * - 1 - A channel event has occurred.
01041  */
01042 /*@{*/
01043 #define BP_FTM_STATUS_CH7F   (7U)          /*!< Bit position for FTM_STATUS_CH7F. */
01044 #define BM_FTM_STATUS_CH7F   (0x00000080U) /*!< Bit mask for FTM_STATUS_CH7F. */
01045 #define BS_FTM_STATUS_CH7F   (1U)          /*!< Bit field size in bits for FTM_STATUS_CH7F. */
01046 
01047 /*! @brief Read current value of the FTM_STATUS_CH7F field. */
01048 #define BR_FTM_STATUS_CH7F(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH7F)))
01049 
01050 /*! @brief Format value for bitfield FTM_STATUS_CH7F. */
01051 #define BF_FTM_STATUS_CH7F(v) ((uint32_t)((uint32_t)(v) << BP_FTM_STATUS_CH7F) & BM_FTM_STATUS_CH7F)
01052 
01053 /*! @brief Set the CH7F field to a new value. */
01054 #define BW_FTM_STATUS_CH7F(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_STATUS_ADDR(x), BP_FTM_STATUS_CH7F), v))
01055 /*@}*/
01056 
01057 /*******************************************************************************
01058  * HW_FTM_MODE - Features Mode Selection
01059  ******************************************************************************/
01060 
01061 /*!
01062  * @brief HW_FTM_MODE - Features Mode Selection (RW)
01063  *
01064  * Reset value: 0x00000004U
01065  *
01066  * This register contains the global enable bit for FTM-specific features and
01067  * the control bits used to configure: Fault control mode and interrupt Capture
01068  * Test mode PWM synchronization Write protection Channel output initialization
01069  * These controls relate to all channels within this module.
01070  */
01071 typedef union _hw_ftm_mode
01072 {
01073     uint32_t U;
01074     struct _hw_ftm_mode_bitfields
01075     {
01076         uint32_t FTMEN : 1;            /*!< [0] FTM Enable */
01077         uint32_t INIT : 1;             /*!< [1] Initialize The Channels Output */
01078         uint32_t WPDIS : 1;            /*!< [2] Write Protection Disable */
01079         uint32_t PWMSYNC : 1;          /*!< [3] PWM Synchronization Mode */
01080         uint32_t CAPTEST : 1;          /*!< [4] Capture Test Mode Enable */
01081         uint32_t FAULTM : 2;           /*!< [6:5] Fault Control Mode */
01082         uint32_t FAULTIE : 1;          /*!< [7] Fault Interrupt Enable */
01083         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
01084     } B;
01085 } hw_ftm_mode_t;
01086 
01087 /*!
01088  * @name Constants and macros for entire FTM_MODE register
01089  */
01090 /*@{*/
01091 #define HW_FTM_MODE_ADDR(x)      ((x) + 0x54U)
01092 
01093 #define HW_FTM_MODE(x)           (*(__IO hw_ftm_mode_t *) HW_FTM_MODE_ADDR(x))
01094 #define HW_FTM_MODE_RD(x)        (ADDRESS_READ(hw_ftm_mode_t, HW_FTM_MODE_ADDR(x)))
01095 #define HW_FTM_MODE_WR(x, v)     (ADDRESS_WRITE(hw_ftm_mode_t, HW_FTM_MODE_ADDR(x), v))
01096 #define HW_FTM_MODE_SET(x, v)    (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) |  (v)))
01097 #define HW_FTM_MODE_CLR(x, v)    (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) & ~(v)))
01098 #define HW_FTM_MODE_TOG(x, v)    (HW_FTM_MODE_WR(x, HW_FTM_MODE_RD(x) ^  (v)))
01099 /*@}*/
01100 
01101 /*
01102  * Constants & macros for individual FTM_MODE bitfields
01103  */
01104 
01105 /*!
01106  * @name Register FTM_MODE, field FTMEN[0] (RW)
01107  *
01108  * This field is write protected. It can be written only when MODE[WPDIS] = 1.
01109  *
01110  * Values:
01111  * - 0 - Only the TPM-compatible registers (first set of registers) can be used
01112  *     without any restriction. Do not use the FTM-specific registers.
01113  * - 1 - All registers including the FTM-specific registers (second set of
01114  *     registers) are available for use with no restrictions.
01115  */
01116 /*@{*/
01117 #define BP_FTM_MODE_FTMEN    (0U)          /*!< Bit position for FTM_MODE_FTMEN. */
01118 #define BM_FTM_MODE_FTMEN    (0x00000001U) /*!< Bit mask for FTM_MODE_FTMEN. */
01119 #define BS_FTM_MODE_FTMEN    (1U)          /*!< Bit field size in bits for FTM_MODE_FTMEN. */
01120 
01121 /*! @brief Read current value of the FTM_MODE_FTMEN field. */
01122 #define BR_FTM_MODE_FTMEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FTMEN)))
01123 
01124 /*! @brief Format value for bitfield FTM_MODE_FTMEN. */
01125 #define BF_FTM_MODE_FTMEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_FTMEN) & BM_FTM_MODE_FTMEN)
01126 
01127 /*! @brief Set the FTMEN field to a new value. */
01128 #define BW_FTM_MODE_FTMEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FTMEN), v))
01129 /*@}*/
01130 
01131 /*!
01132  * @name Register FTM_MODE, field INIT[1] (RW)
01133  *
01134  * When a 1 is written to INIT bit the channels output is initialized according
01135  * to the state of their corresponding bit in the OUTINIT register. Writing a 0
01136  * to INIT bit has no effect. The INIT bit is always read as 0.
01137  */
01138 /*@{*/
01139 #define BP_FTM_MODE_INIT     (1U)          /*!< Bit position for FTM_MODE_INIT. */
01140 #define BM_FTM_MODE_INIT     (0x00000002U) /*!< Bit mask for FTM_MODE_INIT. */
01141 #define BS_FTM_MODE_INIT     (1U)          /*!< Bit field size in bits for FTM_MODE_INIT. */
01142 
01143 /*! @brief Read current value of the FTM_MODE_INIT field. */
01144 #define BR_FTM_MODE_INIT(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_INIT)))
01145 
01146 /*! @brief Format value for bitfield FTM_MODE_INIT. */
01147 #define BF_FTM_MODE_INIT(v)  ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_INIT) & BM_FTM_MODE_INIT)
01148 
01149 /*! @brief Set the INIT field to a new value. */
01150 #define BW_FTM_MODE_INIT(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_INIT), v))
01151 /*@}*/
01152 
01153 /*!
01154  * @name Register FTM_MODE, field WPDIS[2] (RW)
01155  *
01156  * When write protection is enabled (WPDIS = 0), write protected bits cannot be
01157  * written. When write protection is disabled (WPDIS = 1), write protected bits
01158  * can be written. The WPDIS bit is the negation of the WPEN bit. WPDIS is cleared
01159  * when 1 is written to WPEN. WPDIS is set when WPEN bit is read as a 1 and then
01160  * 1 is written to WPDIS. Writing 0 to WPDIS has no effect.
01161  *
01162  * Values:
01163  * - 0 - Write protection is enabled.
01164  * - 1 - Write protection is disabled.
01165  */
01166 /*@{*/
01167 #define BP_FTM_MODE_WPDIS    (2U)          /*!< Bit position for FTM_MODE_WPDIS. */
01168 #define BM_FTM_MODE_WPDIS    (0x00000004U) /*!< Bit mask for FTM_MODE_WPDIS. */
01169 #define BS_FTM_MODE_WPDIS    (1U)          /*!< Bit field size in bits for FTM_MODE_WPDIS. */
01170 
01171 /*! @brief Read current value of the FTM_MODE_WPDIS field. */
01172 #define BR_FTM_MODE_WPDIS(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_WPDIS)))
01173 
01174 /*! @brief Format value for bitfield FTM_MODE_WPDIS. */
01175 #define BF_FTM_MODE_WPDIS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_WPDIS) & BM_FTM_MODE_WPDIS)
01176 
01177 /*! @brief Set the WPDIS field to a new value. */
01178 #define BW_FTM_MODE_WPDIS(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_WPDIS), v))
01179 /*@}*/
01180 
01181 /*!
01182  * @name Register FTM_MODE, field PWMSYNC[3] (RW)
01183  *
01184  * Selects which triggers can be used by MOD, CnV, OUTMASK, and FTM counter
01185  * synchronization. See PWM synchronization. The PWMSYNC bit configures the
01186  * synchronization when SYNCMODE is 0.
01187  *
01188  * Values:
01189  * - 0 - No restrictions. Software and hardware triggers can be used by MOD,
01190  *     CnV, OUTMASK, and FTM counter synchronization.
01191  * - 1 - Software trigger can only be used by MOD and CnV synchronization, and
01192  *     hardware triggers can only be used by OUTMASK and FTM counter
01193  *     synchronization.
01194  */
01195 /*@{*/
01196 #define BP_FTM_MODE_PWMSYNC  (3U)          /*!< Bit position for FTM_MODE_PWMSYNC. */
01197 #define BM_FTM_MODE_PWMSYNC  (0x00000008U) /*!< Bit mask for FTM_MODE_PWMSYNC. */
01198 #define BS_FTM_MODE_PWMSYNC  (1U)          /*!< Bit field size in bits for FTM_MODE_PWMSYNC. */
01199 
01200 /*! @brief Read current value of the FTM_MODE_PWMSYNC field. */
01201 #define BR_FTM_MODE_PWMSYNC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_PWMSYNC)))
01202 
01203 /*! @brief Format value for bitfield FTM_MODE_PWMSYNC. */
01204 #define BF_FTM_MODE_PWMSYNC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_PWMSYNC) & BM_FTM_MODE_PWMSYNC)
01205 
01206 /*! @brief Set the PWMSYNC field to a new value. */
01207 #define BW_FTM_MODE_PWMSYNC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_PWMSYNC), v))
01208 /*@}*/
01209 
01210 /*!
01211  * @name Register FTM_MODE, field CAPTEST[4] (RW)
01212  *
01213  * Enables the capture test mode. This field is write protected. It can be
01214  * written only when MODE[WPDIS] = 1.
01215  *
01216  * Values:
01217  * - 0 - Capture test mode is disabled.
01218  * - 1 - Capture test mode is enabled.
01219  */
01220 /*@{*/
01221 #define BP_FTM_MODE_CAPTEST  (4U)          /*!< Bit position for FTM_MODE_CAPTEST. */
01222 #define BM_FTM_MODE_CAPTEST  (0x00000010U) /*!< Bit mask for FTM_MODE_CAPTEST. */
01223 #define BS_FTM_MODE_CAPTEST  (1U)          /*!< Bit field size in bits for FTM_MODE_CAPTEST. */
01224 
01225 /*! @brief Read current value of the FTM_MODE_CAPTEST field. */
01226 #define BR_FTM_MODE_CAPTEST(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_CAPTEST)))
01227 
01228 /*! @brief Format value for bitfield FTM_MODE_CAPTEST. */
01229 #define BF_FTM_MODE_CAPTEST(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_CAPTEST) & BM_FTM_MODE_CAPTEST)
01230 
01231 /*! @brief Set the CAPTEST field to a new value. */
01232 #define BW_FTM_MODE_CAPTEST(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_CAPTEST), v))
01233 /*@}*/
01234 
01235 /*!
01236  * @name Register FTM_MODE, field FAULTM[6:5] (RW)
01237  *
01238  * Defines the FTM fault control mode. This field is write protected. It can be
01239  * written only when MODE[WPDIS] = 1.
01240  *
01241  * Values:
01242  * - 00 - Fault control is disabled for all channels.
01243  * - 01 - Fault control is enabled for even channels only (channels 0, 2, 4, and
01244  *     6), and the selected mode is the manual fault clearing.
01245  * - 10 - Fault control is enabled for all channels, and the selected mode is
01246  *     the manual fault clearing.
01247  * - 11 - Fault control is enabled for all channels, and the selected mode is
01248  *     the automatic fault clearing.
01249  */
01250 /*@{*/
01251 #define BP_FTM_MODE_FAULTM   (5U)          /*!< Bit position for FTM_MODE_FAULTM. */
01252 #define BM_FTM_MODE_FAULTM   (0x00000060U) /*!< Bit mask for FTM_MODE_FAULTM. */
01253 #define BS_FTM_MODE_FAULTM   (2U)          /*!< Bit field size in bits for FTM_MODE_FAULTM. */
01254 
01255 /*! @brief Read current value of the FTM_MODE_FAULTM field. */
01256 #define BR_FTM_MODE_FAULTM(x) (UNION_READ(hw_ftm_mode_t, HW_FTM_MODE_ADDR(x), U, B.FAULTM))
01257 
01258 /*! @brief Format value for bitfield FTM_MODE_FAULTM. */
01259 #define BF_FTM_MODE_FAULTM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_FAULTM) & BM_FTM_MODE_FAULTM)
01260 
01261 /*! @brief Set the FAULTM field to a new value. */
01262 #define BW_FTM_MODE_FAULTM(x, v) (HW_FTM_MODE_WR(x, (HW_FTM_MODE_RD(x) & ~BM_FTM_MODE_FAULTM) | BF_FTM_MODE_FAULTM(v)))
01263 /*@}*/
01264 
01265 /*!
01266  * @name Register FTM_MODE, field FAULTIE[7] (RW)
01267  *
01268  * Enables the generation of an interrupt when a fault is detected by FTM and
01269  * the FTM fault control is enabled.
01270  *
01271  * Values:
01272  * - 0 - Fault control interrupt is disabled.
01273  * - 1 - Fault control interrupt is enabled.
01274  */
01275 /*@{*/
01276 #define BP_FTM_MODE_FAULTIE  (7U)          /*!< Bit position for FTM_MODE_FAULTIE. */
01277 #define BM_FTM_MODE_FAULTIE  (0x00000080U) /*!< Bit mask for FTM_MODE_FAULTIE. */
01278 #define BS_FTM_MODE_FAULTIE  (1U)          /*!< Bit field size in bits for FTM_MODE_FAULTIE. */
01279 
01280 /*! @brief Read current value of the FTM_MODE_FAULTIE field. */
01281 #define BR_FTM_MODE_FAULTIE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FAULTIE)))
01282 
01283 /*! @brief Format value for bitfield FTM_MODE_FAULTIE. */
01284 #define BF_FTM_MODE_FAULTIE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_MODE_FAULTIE) & BM_FTM_MODE_FAULTIE)
01285 
01286 /*! @brief Set the FAULTIE field to a new value. */
01287 #define BW_FTM_MODE_FAULTIE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_MODE_ADDR(x), BP_FTM_MODE_FAULTIE), v))
01288 /*@}*/
01289 
01290 /*******************************************************************************
01291  * HW_FTM_SYNC - Synchronization
01292  ******************************************************************************/
01293 
01294 /*!
01295  * @brief HW_FTM_SYNC - Synchronization (RW)
01296  *
01297  * Reset value: 0x00000000U
01298  *
01299  * This register configures the PWM synchronization. A synchronization event can
01300  * perform the synchronized update of MOD, CV, and OUTMASK registers with the
01301  * value of their write buffer and the FTM counter initialization. The software
01302  * trigger, SWSYNC bit, and hardware triggers TRIG0, TRIG1, and TRIG2 bits have a
01303  * potential conflict if used together when SYNCMODE = 0. Use only hardware or
01304  * software triggers but not both at the same time, otherwise unpredictable behavior
01305  * is likely to happen. The selection of the loading point, CNTMAX and CNTMIN
01306  * bits, is intended to provide the update of MOD, CNTIN, and CnV registers across
01307  * all enabled channels simultaneously. The use of the loading point selection
01308  * together with SYNCMODE = 0 and hardware trigger selection, TRIG0, TRIG1, or TRIG2
01309  * bits, is likely to result in unpredictable behavior. The synchronization
01310  * event selection also depends on the PWMSYNC (MODE register) and SYNCMODE (SYNCONF
01311  * register) bits. See PWM synchronization.
01312  */
01313 typedef union _hw_ftm_sync
01314 {
01315     uint32_t U;
01316     struct _hw_ftm_sync_bitfields
01317     {
01318         uint32_t CNTMIN : 1;           /*!< [0] Minimum Loading Point Enable */
01319         uint32_t CNTMAX : 1;           /*!< [1] Maximum Loading Point Enable */
01320         uint32_t REINIT : 1;           /*!< [2] FTM Counter Reinitialization By
01321                                         * Synchronization (FTM counter synchronization) */
01322         uint32_t SYNCHOM : 1;          /*!< [3] Output Mask Synchronization */
01323         uint32_t TRIG0 : 1;            /*!< [4] PWM Synchronization Hardware Trigger 0 */
01324         uint32_t TRIG1 : 1;            /*!< [5] PWM Synchronization Hardware Trigger 1 */
01325         uint32_t TRIG2 : 1;            /*!< [6] PWM Synchronization Hardware Trigger 2 */
01326         uint32_t SWSYNC : 1;           /*!< [7] PWM Synchronization Software Trigger */
01327         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
01328     } B;
01329 } hw_ftm_sync_t;
01330 
01331 /*!
01332  * @name Constants and macros for entire FTM_SYNC register
01333  */
01334 /*@{*/
01335 #define HW_FTM_SYNC_ADDR(x)      ((x) + 0x58U)
01336 
01337 #define HW_FTM_SYNC(x)           (*(__IO hw_ftm_sync_t *) HW_FTM_SYNC_ADDR(x))
01338 #define HW_FTM_SYNC_RD(x)        (ADDRESS_READ(hw_ftm_sync_t, HW_FTM_SYNC_ADDR(x)))
01339 #define HW_FTM_SYNC_WR(x, v)     (ADDRESS_WRITE(hw_ftm_sync_t, HW_FTM_SYNC_ADDR(x), v))
01340 #define HW_FTM_SYNC_SET(x, v)    (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) |  (v)))
01341 #define HW_FTM_SYNC_CLR(x, v)    (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) & ~(v)))
01342 #define HW_FTM_SYNC_TOG(x, v)    (HW_FTM_SYNC_WR(x, HW_FTM_SYNC_RD(x) ^  (v)))
01343 /*@}*/
01344 
01345 /*
01346  * Constants & macros for individual FTM_SYNC bitfields
01347  */
01348 
01349 /*!
01350  * @name Register FTM_SYNC, field CNTMIN[0] (RW)
01351  *
01352  * Selects the minimum loading point to PWM synchronization. See Boundary cycle
01353  * and loading points. If CNTMIN is one, the selected loading point is when the
01354  * FTM counter reaches its minimum value (CNTIN register).
01355  *
01356  * Values:
01357  * - 0 - The minimum loading point is disabled.
01358  * - 1 - The minimum loading point is enabled.
01359  */
01360 /*@{*/
01361 #define BP_FTM_SYNC_CNTMIN   (0U)          /*!< Bit position for FTM_SYNC_CNTMIN. */
01362 #define BM_FTM_SYNC_CNTMIN   (0x00000001U) /*!< Bit mask for FTM_SYNC_CNTMIN. */
01363 #define BS_FTM_SYNC_CNTMIN   (1U)          /*!< Bit field size in bits for FTM_SYNC_CNTMIN. */
01364 
01365 /*! @brief Read current value of the FTM_SYNC_CNTMIN field. */
01366 #define BR_FTM_SYNC_CNTMIN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMIN)))
01367 
01368 /*! @brief Format value for bitfield FTM_SYNC_CNTMIN. */
01369 #define BF_FTM_SYNC_CNTMIN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_CNTMIN) & BM_FTM_SYNC_CNTMIN)
01370 
01371 /*! @brief Set the CNTMIN field to a new value. */
01372 #define BW_FTM_SYNC_CNTMIN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMIN), v))
01373 /*@}*/
01374 
01375 /*!
01376  * @name Register FTM_SYNC, field CNTMAX[1] (RW)
01377  *
01378  * Selects the maximum loading point to PWM synchronization. See Boundary cycle
01379  * and loading points. If CNTMAX is 1, the selected loading point is when the FTM
01380  * counter reaches its maximum value (MOD register).
01381  *
01382  * Values:
01383  * - 0 - The maximum loading point is disabled.
01384  * - 1 - The maximum loading point is enabled.
01385  */
01386 /*@{*/
01387 #define BP_FTM_SYNC_CNTMAX   (1U)          /*!< Bit position for FTM_SYNC_CNTMAX. */
01388 #define BM_FTM_SYNC_CNTMAX   (0x00000002U) /*!< Bit mask for FTM_SYNC_CNTMAX. */
01389 #define BS_FTM_SYNC_CNTMAX   (1U)          /*!< Bit field size in bits for FTM_SYNC_CNTMAX. */
01390 
01391 /*! @brief Read current value of the FTM_SYNC_CNTMAX field. */
01392 #define BR_FTM_SYNC_CNTMAX(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMAX)))
01393 
01394 /*! @brief Format value for bitfield FTM_SYNC_CNTMAX. */
01395 #define BF_FTM_SYNC_CNTMAX(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_CNTMAX) & BM_FTM_SYNC_CNTMAX)
01396 
01397 /*! @brief Set the CNTMAX field to a new value. */
01398 #define BW_FTM_SYNC_CNTMAX(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_CNTMAX), v))
01399 /*@}*/
01400 
01401 /*!
01402  * @name Register FTM_SYNC, field REINIT[2] (RW)
01403  *
01404  * Determines if the FTM counter is reinitialized when the selected trigger for
01405  * the synchronization is detected. The REINIT bit configures the synchronization
01406  * when SYNCMODE is zero.
01407  *
01408  * Values:
01409  * - 0 - FTM counter continues to count normally.
01410  * - 1 - FTM counter is updated with its initial value when the selected trigger
01411  *     is detected.
01412  */
01413 /*@{*/
01414 #define BP_FTM_SYNC_REINIT   (2U)          /*!< Bit position for FTM_SYNC_REINIT. */
01415 #define BM_FTM_SYNC_REINIT   (0x00000004U) /*!< Bit mask for FTM_SYNC_REINIT. */
01416 #define BS_FTM_SYNC_REINIT   (1U)          /*!< Bit field size in bits for FTM_SYNC_REINIT. */
01417 
01418 /*! @brief Read current value of the FTM_SYNC_REINIT field. */
01419 #define BR_FTM_SYNC_REINIT(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_REINIT)))
01420 
01421 /*! @brief Format value for bitfield FTM_SYNC_REINIT. */
01422 #define BF_FTM_SYNC_REINIT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_REINIT) & BM_FTM_SYNC_REINIT)
01423 
01424 /*! @brief Set the REINIT field to a new value. */
01425 #define BW_FTM_SYNC_REINIT(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_REINIT), v))
01426 /*@}*/
01427 
01428 /*!
01429  * @name Register FTM_SYNC, field SYNCHOM[3] (RW)
01430  *
01431  * Selects when the OUTMASK register is updated with the value of its buffer.
01432  *
01433  * Values:
01434  * - 0 - OUTMASK register is updated with the value of its buffer in all rising
01435  *     edges of the system clock.
01436  * - 1 - OUTMASK register is updated with the value of its buffer only by the
01437  *     PWM synchronization.
01438  */
01439 /*@{*/
01440 #define BP_FTM_SYNC_SYNCHOM  (3U)          /*!< Bit position for FTM_SYNC_SYNCHOM. */
01441 #define BM_FTM_SYNC_SYNCHOM  (0x00000008U) /*!< Bit mask for FTM_SYNC_SYNCHOM. */
01442 #define BS_FTM_SYNC_SYNCHOM  (1U)          /*!< Bit field size in bits for FTM_SYNC_SYNCHOM. */
01443 
01444 /*! @brief Read current value of the FTM_SYNC_SYNCHOM field. */
01445 #define BR_FTM_SYNC_SYNCHOM(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SYNCHOM)))
01446 
01447 /*! @brief Format value for bitfield FTM_SYNC_SYNCHOM. */
01448 #define BF_FTM_SYNC_SYNCHOM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_SYNCHOM) & BM_FTM_SYNC_SYNCHOM)
01449 
01450 /*! @brief Set the SYNCHOM field to a new value. */
01451 #define BW_FTM_SYNC_SYNCHOM(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SYNCHOM), v))
01452 /*@}*/
01453 
01454 /*!
01455  * @name Register FTM_SYNC, field TRIG0[4] (RW)
01456  *
01457  * Enables hardware trigger 0 to the PWM synchronization. Hardware trigger 0
01458  * occurs when a rising edge is detected at the trigger 0 input signal.
01459  *
01460  * Values:
01461  * - 0 - Trigger is disabled.
01462  * - 1 - Trigger is enabled.
01463  */
01464 /*@{*/
01465 #define BP_FTM_SYNC_TRIG0    (4U)          /*!< Bit position for FTM_SYNC_TRIG0. */
01466 #define BM_FTM_SYNC_TRIG0    (0x00000010U) /*!< Bit mask for FTM_SYNC_TRIG0. */
01467 #define BS_FTM_SYNC_TRIG0    (1U)          /*!< Bit field size in bits for FTM_SYNC_TRIG0. */
01468 
01469 /*! @brief Read current value of the FTM_SYNC_TRIG0 field. */
01470 #define BR_FTM_SYNC_TRIG0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG0)))
01471 
01472 /*! @brief Format value for bitfield FTM_SYNC_TRIG0. */
01473 #define BF_FTM_SYNC_TRIG0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_TRIG0) & BM_FTM_SYNC_TRIG0)
01474 
01475 /*! @brief Set the TRIG0 field to a new value. */
01476 #define BW_FTM_SYNC_TRIG0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG0), v))
01477 /*@}*/
01478 
01479 /*!
01480  * @name Register FTM_SYNC, field TRIG1[5] (RW)
01481  *
01482  * Enables hardware trigger 1 to the PWM synchronization. Hardware trigger 1
01483  * happens when a rising edge is detected at the trigger 1 input signal.
01484  *
01485  * Values:
01486  * - 0 - Trigger is disabled.
01487  * - 1 - Trigger is enabled.
01488  */
01489 /*@{*/
01490 #define BP_FTM_SYNC_TRIG1    (5U)          /*!< Bit position for FTM_SYNC_TRIG1. */
01491 #define BM_FTM_SYNC_TRIG1    (0x00000020U) /*!< Bit mask for FTM_SYNC_TRIG1. */
01492 #define BS_FTM_SYNC_TRIG1    (1U)          /*!< Bit field size in bits for FTM_SYNC_TRIG1. */
01493 
01494 /*! @brief Read current value of the FTM_SYNC_TRIG1 field. */
01495 #define BR_FTM_SYNC_TRIG1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG1)))
01496 
01497 /*! @brief Format value for bitfield FTM_SYNC_TRIG1. */
01498 #define BF_FTM_SYNC_TRIG1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_TRIG1) & BM_FTM_SYNC_TRIG1)
01499 
01500 /*! @brief Set the TRIG1 field to a new value. */
01501 #define BW_FTM_SYNC_TRIG1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG1), v))
01502 /*@}*/
01503 
01504 /*!
01505  * @name Register FTM_SYNC, field TRIG2[6] (RW)
01506  *
01507  * Enables hardware trigger 2 to the PWM synchronization. Hardware trigger 2
01508  * happens when a rising edge is detected at the trigger 2 input signal.
01509  *
01510  * Values:
01511  * - 0 - Trigger is disabled.
01512  * - 1 - Trigger is enabled.
01513  */
01514 /*@{*/
01515 #define BP_FTM_SYNC_TRIG2    (6U)          /*!< Bit position for FTM_SYNC_TRIG2. */
01516 #define BM_FTM_SYNC_TRIG2    (0x00000040U) /*!< Bit mask for FTM_SYNC_TRIG2. */
01517 #define BS_FTM_SYNC_TRIG2    (1U)          /*!< Bit field size in bits for FTM_SYNC_TRIG2. */
01518 
01519 /*! @brief Read current value of the FTM_SYNC_TRIG2 field. */
01520 #define BR_FTM_SYNC_TRIG2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG2)))
01521 
01522 /*! @brief Format value for bitfield FTM_SYNC_TRIG2. */
01523 #define BF_FTM_SYNC_TRIG2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_TRIG2) & BM_FTM_SYNC_TRIG2)
01524 
01525 /*! @brief Set the TRIG2 field to a new value. */
01526 #define BW_FTM_SYNC_TRIG2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_TRIG2), v))
01527 /*@}*/
01528 
01529 /*!
01530  * @name Register FTM_SYNC, field SWSYNC[7] (RW)
01531  *
01532  * Selects the software trigger as the PWM synchronization trigger. The software
01533  * trigger happens when a 1 is written to SWSYNC bit.
01534  *
01535  * Values:
01536  * - 0 - Software trigger is not selected.
01537  * - 1 - Software trigger is selected.
01538  */
01539 /*@{*/
01540 #define BP_FTM_SYNC_SWSYNC   (7U)          /*!< Bit position for FTM_SYNC_SWSYNC. */
01541 #define BM_FTM_SYNC_SWSYNC   (0x00000080U) /*!< Bit mask for FTM_SYNC_SWSYNC. */
01542 #define BS_FTM_SYNC_SWSYNC   (1U)          /*!< Bit field size in bits for FTM_SYNC_SWSYNC. */
01543 
01544 /*! @brief Read current value of the FTM_SYNC_SWSYNC field. */
01545 #define BR_FTM_SYNC_SWSYNC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SWSYNC)))
01546 
01547 /*! @brief Format value for bitfield FTM_SYNC_SWSYNC. */
01548 #define BF_FTM_SYNC_SWSYNC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNC_SWSYNC) & BM_FTM_SYNC_SWSYNC)
01549 
01550 /*! @brief Set the SWSYNC field to a new value. */
01551 #define BW_FTM_SYNC_SWSYNC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNC_ADDR(x), BP_FTM_SYNC_SWSYNC), v))
01552 /*@}*/
01553 
01554 /*******************************************************************************
01555  * HW_FTM_OUTINIT - Initial State For Channels Output
01556  ******************************************************************************/
01557 
01558 /*!
01559  * @brief HW_FTM_OUTINIT - Initial State For Channels Output (RW)
01560  *
01561  * Reset value: 0x00000000U
01562  */
01563 typedef union _hw_ftm_outinit
01564 {
01565     uint32_t U;
01566     struct _hw_ftm_outinit_bitfields
01567     {
01568         uint32_t CH0OI : 1;            /*!< [0] Channel 0 Output Initialization Value */
01569         uint32_t CH1OI : 1;            /*!< [1] Channel 1 Output Initialization Value */
01570         uint32_t CH2OI : 1;            /*!< [2] Channel 2 Output Initialization Value */
01571         uint32_t CH3OI : 1;            /*!< [3] Channel 3 Output Initialization Value */
01572         uint32_t CH4OI : 1;            /*!< [4] Channel 4 Output Initialization Value */
01573         uint32_t CH5OI : 1;            /*!< [5] Channel 5 Output Initialization Value */
01574         uint32_t CH6OI : 1;            /*!< [6] Channel 6 Output Initialization Value */
01575         uint32_t CH7OI : 1;            /*!< [7] Channel 7 Output Initialization Value */
01576         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
01577     } B;
01578 } hw_ftm_outinit_t;
01579 
01580 /*!
01581  * @name Constants and macros for entire FTM_OUTINIT register
01582  */
01583 /*@{*/
01584 #define HW_FTM_OUTINIT_ADDR(x)   ((x) + 0x5CU)
01585 
01586 #define HW_FTM_OUTINIT(x)        (*(__IO hw_ftm_outinit_t *) HW_FTM_OUTINIT_ADDR(x))
01587 #define HW_FTM_OUTINIT_RD(x)     (ADDRESS_READ(hw_ftm_outinit_t, HW_FTM_OUTINIT_ADDR(x)))
01588 #define HW_FTM_OUTINIT_WR(x, v)  (ADDRESS_WRITE(hw_ftm_outinit_t, HW_FTM_OUTINIT_ADDR(x), v))
01589 #define HW_FTM_OUTINIT_SET(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) |  (v)))
01590 #define HW_FTM_OUTINIT_CLR(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) & ~(v)))
01591 #define HW_FTM_OUTINIT_TOG(x, v) (HW_FTM_OUTINIT_WR(x, HW_FTM_OUTINIT_RD(x) ^  (v)))
01592 /*@}*/
01593 
01594 /*
01595  * Constants & macros for individual FTM_OUTINIT bitfields
01596  */
01597 
01598 /*!
01599  * @name Register FTM_OUTINIT, field CH0OI[0] (RW)
01600  *
01601  * Selects the value that is forced into the channel output when the
01602  * initialization occurs.
01603  *
01604  * Values:
01605  * - 0 - The initialization value is 0.
01606  * - 1 - The initialization value is 1.
01607  */
01608 /*@{*/
01609 #define BP_FTM_OUTINIT_CH0OI (0U)          /*!< Bit position for FTM_OUTINIT_CH0OI. */
01610 #define BM_FTM_OUTINIT_CH0OI (0x00000001U) /*!< Bit mask for FTM_OUTINIT_CH0OI. */
01611 #define BS_FTM_OUTINIT_CH0OI (1U)          /*!< Bit field size in bits for FTM_OUTINIT_CH0OI. */
01612 
01613 /*! @brief Read current value of the FTM_OUTINIT_CH0OI field. */
01614 #define BR_FTM_OUTINIT_CH0OI(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH0OI)))
01615 
01616 /*! @brief Format value for bitfield FTM_OUTINIT_CH0OI. */
01617 #define BF_FTM_OUTINIT_CH0OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH0OI) & BM_FTM_OUTINIT_CH0OI)
01618 
01619 /*! @brief Set the CH0OI field to a new value. */
01620 #define BW_FTM_OUTINIT_CH0OI(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH0OI), v))
01621 /*@}*/
01622 
01623 /*!
01624  * @name Register FTM_OUTINIT, field CH1OI[1] (RW)
01625  *
01626  * Selects the value that is forced into the channel output when the
01627  * initialization occurs.
01628  *
01629  * Values:
01630  * - 0 - The initialization value is 0.
01631  * - 1 - The initialization value is 1.
01632  */
01633 /*@{*/
01634 #define BP_FTM_OUTINIT_CH1OI (1U)          /*!< Bit position for FTM_OUTINIT_CH1OI. */
01635 #define BM_FTM_OUTINIT_CH1OI (0x00000002U) /*!< Bit mask for FTM_OUTINIT_CH1OI. */
01636 #define BS_FTM_OUTINIT_CH1OI (1U)          /*!< Bit field size in bits for FTM_OUTINIT_CH1OI. */
01637 
01638 /*! @brief Read current value of the FTM_OUTINIT_CH1OI field. */
01639 #define BR_FTM_OUTINIT_CH1OI(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH1OI)))
01640 
01641 /*! @brief Format value for bitfield FTM_OUTINIT_CH1OI. */
01642 #define BF_FTM_OUTINIT_CH1OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH1OI) & BM_FTM_OUTINIT_CH1OI)
01643 
01644 /*! @brief Set the CH1OI field to a new value. */
01645 #define BW_FTM_OUTINIT_CH1OI(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH1OI), v))
01646 /*@}*/
01647 
01648 /*!
01649  * @name Register FTM_OUTINIT, field CH2OI[2] (RW)
01650  *
01651  * Selects the value that is forced into the channel output when the
01652  * initialization occurs.
01653  *
01654  * Values:
01655  * - 0 - The initialization value is 0.
01656  * - 1 - The initialization value is 1.
01657  */
01658 /*@{*/
01659 #define BP_FTM_OUTINIT_CH2OI (2U)          /*!< Bit position for FTM_OUTINIT_CH2OI. */
01660 #define BM_FTM_OUTINIT_CH2OI (0x00000004U) /*!< Bit mask for FTM_OUTINIT_CH2OI. */
01661 #define BS_FTM_OUTINIT_CH2OI (1U)          /*!< Bit field size in bits for FTM_OUTINIT_CH2OI. */
01662 
01663 /*! @brief Read current value of the FTM_OUTINIT_CH2OI field. */
01664 #define BR_FTM_OUTINIT_CH2OI(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH2OI)))
01665 
01666 /*! @brief Format value for bitfield FTM_OUTINIT_CH2OI. */
01667 #define BF_FTM_OUTINIT_CH2OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH2OI) & BM_FTM_OUTINIT_CH2OI)
01668 
01669 /*! @brief Set the CH2OI field to a new value. */
01670 #define BW_FTM_OUTINIT_CH2OI(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH2OI), v))
01671 /*@}*/
01672 
01673 /*!
01674  * @name Register FTM_OUTINIT, field CH3OI[3] (RW)
01675  *
01676  * Selects the value that is forced into the channel output when the
01677  * initialization occurs.
01678  *
01679  * Values:
01680  * - 0 - The initialization value is 0.
01681  * - 1 - The initialization value is 1.
01682  */
01683 /*@{*/
01684 #define BP_FTM_OUTINIT_CH3OI (3U)          /*!< Bit position for FTM_OUTINIT_CH3OI. */
01685 #define BM_FTM_OUTINIT_CH3OI (0x00000008U) /*!< Bit mask for FTM_OUTINIT_CH3OI. */
01686 #define BS_FTM_OUTINIT_CH3OI (1U)          /*!< Bit field size in bits for FTM_OUTINIT_CH3OI. */
01687 
01688 /*! @brief Read current value of the FTM_OUTINIT_CH3OI field. */
01689 #define BR_FTM_OUTINIT_CH3OI(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH3OI)))
01690 
01691 /*! @brief Format value for bitfield FTM_OUTINIT_CH3OI. */
01692 #define BF_FTM_OUTINIT_CH3OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH3OI) & BM_FTM_OUTINIT_CH3OI)
01693 
01694 /*! @brief Set the CH3OI field to a new value. */
01695 #define BW_FTM_OUTINIT_CH3OI(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH3OI), v))
01696 /*@}*/
01697 
01698 /*!
01699  * @name Register FTM_OUTINIT, field CH4OI[4] (RW)
01700  *
01701  * Selects the value that is forced into the channel output when the
01702  * initialization occurs.
01703  *
01704  * Values:
01705  * - 0 - The initialization value is 0.
01706  * - 1 - The initialization value is 1.
01707  */
01708 /*@{*/
01709 #define BP_FTM_OUTINIT_CH4OI (4U)          /*!< Bit position for FTM_OUTINIT_CH4OI. */
01710 #define BM_FTM_OUTINIT_CH4OI (0x00000010U) /*!< Bit mask for FTM_OUTINIT_CH4OI. */
01711 #define BS_FTM_OUTINIT_CH4OI (1U)          /*!< Bit field size in bits for FTM_OUTINIT_CH4OI. */
01712 
01713 /*! @brief Read current value of the FTM_OUTINIT_CH4OI field. */
01714 #define BR_FTM_OUTINIT_CH4OI(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH4OI)))
01715 
01716 /*! @brief Format value for bitfield FTM_OUTINIT_CH4OI. */
01717 #define BF_FTM_OUTINIT_CH4OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH4OI) & BM_FTM_OUTINIT_CH4OI)
01718 
01719 /*! @brief Set the CH4OI field to a new value. */
01720 #define BW_FTM_OUTINIT_CH4OI(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH4OI), v))
01721 /*@}*/
01722 
01723 /*!
01724  * @name Register FTM_OUTINIT, field CH5OI[5] (RW)
01725  *
01726  * Selects the value that is forced into the channel output when the
01727  * initialization occurs.
01728  *
01729  * Values:
01730  * - 0 - The initialization value is 0.
01731  * - 1 - The initialization value is 1.
01732  */
01733 /*@{*/
01734 #define BP_FTM_OUTINIT_CH5OI (5U)          /*!< Bit position for FTM_OUTINIT_CH5OI. */
01735 #define BM_FTM_OUTINIT_CH5OI (0x00000020U) /*!< Bit mask for FTM_OUTINIT_CH5OI. */
01736 #define BS_FTM_OUTINIT_CH5OI (1U)          /*!< Bit field size in bits for FTM_OUTINIT_CH5OI. */
01737 
01738 /*! @brief Read current value of the FTM_OUTINIT_CH5OI field. */
01739 #define BR_FTM_OUTINIT_CH5OI(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH5OI)))
01740 
01741 /*! @brief Format value for bitfield FTM_OUTINIT_CH5OI. */
01742 #define BF_FTM_OUTINIT_CH5OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH5OI) & BM_FTM_OUTINIT_CH5OI)
01743 
01744 /*! @brief Set the CH5OI field to a new value. */
01745 #define BW_FTM_OUTINIT_CH5OI(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH5OI), v))
01746 /*@}*/
01747 
01748 /*!
01749  * @name Register FTM_OUTINIT, field CH6OI[6] (RW)
01750  *
01751  * Selects the value that is forced into the channel output when the
01752  * initialization occurs.
01753  *
01754  * Values:
01755  * - 0 - The initialization value is 0.
01756  * - 1 - The initialization value is 1.
01757  */
01758 /*@{*/
01759 #define BP_FTM_OUTINIT_CH6OI (6U)          /*!< Bit position for FTM_OUTINIT_CH6OI. */
01760 #define BM_FTM_OUTINIT_CH6OI (0x00000040U) /*!< Bit mask for FTM_OUTINIT_CH6OI. */
01761 #define BS_FTM_OUTINIT_CH6OI (1U)          /*!< Bit field size in bits for FTM_OUTINIT_CH6OI. */
01762 
01763 /*! @brief Read current value of the FTM_OUTINIT_CH6OI field. */
01764 #define BR_FTM_OUTINIT_CH6OI(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH6OI)))
01765 
01766 /*! @brief Format value for bitfield FTM_OUTINIT_CH6OI. */
01767 #define BF_FTM_OUTINIT_CH6OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH6OI) & BM_FTM_OUTINIT_CH6OI)
01768 
01769 /*! @brief Set the CH6OI field to a new value. */
01770 #define BW_FTM_OUTINIT_CH6OI(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH6OI), v))
01771 /*@}*/
01772 
01773 /*!
01774  * @name Register FTM_OUTINIT, field CH7OI[7] (RW)
01775  *
01776  * Selects the value that is forced into the channel output when the
01777  * initialization occurs.
01778  *
01779  * Values:
01780  * - 0 - The initialization value is 0.
01781  * - 1 - The initialization value is 1.
01782  */
01783 /*@{*/
01784 #define BP_FTM_OUTINIT_CH7OI (7U)          /*!< Bit position for FTM_OUTINIT_CH7OI. */
01785 #define BM_FTM_OUTINIT_CH7OI (0x00000080U) /*!< Bit mask for FTM_OUTINIT_CH7OI. */
01786 #define BS_FTM_OUTINIT_CH7OI (1U)          /*!< Bit field size in bits for FTM_OUTINIT_CH7OI. */
01787 
01788 /*! @brief Read current value of the FTM_OUTINIT_CH7OI field. */
01789 #define BR_FTM_OUTINIT_CH7OI(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH7OI)))
01790 
01791 /*! @brief Format value for bitfield FTM_OUTINIT_CH7OI. */
01792 #define BF_FTM_OUTINIT_CH7OI(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTINIT_CH7OI) & BM_FTM_OUTINIT_CH7OI)
01793 
01794 /*! @brief Set the CH7OI field to a new value. */
01795 #define BW_FTM_OUTINIT_CH7OI(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTINIT_ADDR(x), BP_FTM_OUTINIT_CH7OI), v))
01796 /*@}*/
01797 
01798 /*******************************************************************************
01799  * HW_FTM_OUTMASK - Output Mask
01800  ******************************************************************************/
01801 
01802 /*!
01803  * @brief HW_FTM_OUTMASK - Output Mask (RW)
01804  *
01805  * Reset value: 0x00000000U
01806  *
01807  * This register provides a mask for each FTM channel. The mask of a channel
01808  * determines if its output responds, that is, it is masked or not, when a match
01809  * occurs. This feature is used for BLDC control where the PWM signal is presented
01810  * to an electric motor at specific times to provide electronic commutation. Any
01811  * write to the OUTMASK register, stores the value in its write buffer. The
01812  * register is updated with the value of its write buffer according to PWM
01813  * synchronization.
01814  */
01815 typedef union _hw_ftm_outmask
01816 {
01817     uint32_t U;
01818     struct _hw_ftm_outmask_bitfields
01819     {
01820         uint32_t CH0OM : 1;            /*!< [0] Channel 0 Output Mask */
01821         uint32_t CH1OM : 1;            /*!< [1] Channel 1 Output Mask */
01822         uint32_t CH2OM : 1;            /*!< [2] Channel 2 Output Mask */
01823         uint32_t CH3OM : 1;            /*!< [3] Channel 3 Output Mask */
01824         uint32_t CH4OM : 1;            /*!< [4] Channel 4 Output Mask */
01825         uint32_t CH5OM : 1;            /*!< [5] Channel 5 Output Mask */
01826         uint32_t CH6OM : 1;            /*!< [6] Channel 6 Output Mask */
01827         uint32_t CH7OM : 1;            /*!< [7] Channel 7 Output Mask */
01828         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
01829     } B;
01830 } hw_ftm_outmask_t;
01831 
01832 /*!
01833  * @name Constants and macros for entire FTM_OUTMASK register
01834  */
01835 /*@{*/
01836 #define HW_FTM_OUTMASK_ADDR(x)   ((x) + 0x60U)
01837 
01838 #define HW_FTM_OUTMASK(x)        (*(__IO hw_ftm_outmask_t *) HW_FTM_OUTMASK_ADDR(x))
01839 #define HW_FTM_OUTMASK_RD(x)     (ADDRESS_READ(hw_ftm_outmask_t, HW_FTM_OUTMASK_ADDR(x)))
01840 #define HW_FTM_OUTMASK_WR(x, v)  (ADDRESS_WRITE(hw_ftm_outmask_t, HW_FTM_OUTMASK_ADDR(x), v))
01841 #define HW_FTM_OUTMASK_SET(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) |  (v)))
01842 #define HW_FTM_OUTMASK_CLR(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) & ~(v)))
01843 #define HW_FTM_OUTMASK_TOG(x, v) (HW_FTM_OUTMASK_WR(x, HW_FTM_OUTMASK_RD(x) ^  (v)))
01844 /*@}*/
01845 
01846 /*
01847  * Constants & macros for individual FTM_OUTMASK bitfields
01848  */
01849 
01850 /*!
01851  * @name Register FTM_OUTMASK, field CH0OM[0] (RW)
01852  *
01853  * Defines if the channel output is masked or unmasked.
01854  *
01855  * Values:
01856  * - 0 - Channel output is not masked. It continues to operate normally.
01857  * - 1 - Channel output is masked. It is forced to its inactive state.
01858  */
01859 /*@{*/
01860 #define BP_FTM_OUTMASK_CH0OM (0U)          /*!< Bit position for FTM_OUTMASK_CH0OM. */
01861 #define BM_FTM_OUTMASK_CH0OM (0x00000001U) /*!< Bit mask for FTM_OUTMASK_CH0OM. */
01862 #define BS_FTM_OUTMASK_CH0OM (1U)          /*!< Bit field size in bits for FTM_OUTMASK_CH0OM. */
01863 
01864 /*! @brief Read current value of the FTM_OUTMASK_CH0OM field. */
01865 #define BR_FTM_OUTMASK_CH0OM(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH0OM)))
01866 
01867 /*! @brief Format value for bitfield FTM_OUTMASK_CH0OM. */
01868 #define BF_FTM_OUTMASK_CH0OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH0OM) & BM_FTM_OUTMASK_CH0OM)
01869 
01870 /*! @brief Set the CH0OM field to a new value. */
01871 #define BW_FTM_OUTMASK_CH0OM(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH0OM), v))
01872 /*@}*/
01873 
01874 /*!
01875  * @name Register FTM_OUTMASK, field CH1OM[1] (RW)
01876  *
01877  * Defines if the channel output is masked or unmasked.
01878  *
01879  * Values:
01880  * - 0 - Channel output is not masked. It continues to operate normally.
01881  * - 1 - Channel output is masked. It is forced to its inactive state.
01882  */
01883 /*@{*/
01884 #define BP_FTM_OUTMASK_CH1OM (1U)          /*!< Bit position for FTM_OUTMASK_CH1OM. */
01885 #define BM_FTM_OUTMASK_CH1OM (0x00000002U) /*!< Bit mask for FTM_OUTMASK_CH1OM. */
01886 #define BS_FTM_OUTMASK_CH1OM (1U)          /*!< Bit field size in bits for FTM_OUTMASK_CH1OM. */
01887 
01888 /*! @brief Read current value of the FTM_OUTMASK_CH1OM field. */
01889 #define BR_FTM_OUTMASK_CH1OM(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH1OM)))
01890 
01891 /*! @brief Format value for bitfield FTM_OUTMASK_CH1OM. */
01892 #define BF_FTM_OUTMASK_CH1OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH1OM) & BM_FTM_OUTMASK_CH1OM)
01893 
01894 /*! @brief Set the CH1OM field to a new value. */
01895 #define BW_FTM_OUTMASK_CH1OM(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH1OM), v))
01896 /*@}*/
01897 
01898 /*!
01899  * @name Register FTM_OUTMASK, field CH2OM[2] (RW)
01900  *
01901  * Defines if the channel output is masked or unmasked.
01902  *
01903  * Values:
01904  * - 0 - Channel output is not masked. It continues to operate normally.
01905  * - 1 - Channel output is masked. It is forced to its inactive state.
01906  */
01907 /*@{*/
01908 #define BP_FTM_OUTMASK_CH2OM (2U)          /*!< Bit position for FTM_OUTMASK_CH2OM. */
01909 #define BM_FTM_OUTMASK_CH2OM (0x00000004U) /*!< Bit mask for FTM_OUTMASK_CH2OM. */
01910 #define BS_FTM_OUTMASK_CH2OM (1U)          /*!< Bit field size in bits for FTM_OUTMASK_CH2OM. */
01911 
01912 /*! @brief Read current value of the FTM_OUTMASK_CH2OM field. */
01913 #define BR_FTM_OUTMASK_CH2OM(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH2OM)))
01914 
01915 /*! @brief Format value for bitfield FTM_OUTMASK_CH2OM. */
01916 #define BF_FTM_OUTMASK_CH2OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH2OM) & BM_FTM_OUTMASK_CH2OM)
01917 
01918 /*! @brief Set the CH2OM field to a new value. */
01919 #define BW_FTM_OUTMASK_CH2OM(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH2OM), v))
01920 /*@}*/
01921 
01922 /*!
01923  * @name Register FTM_OUTMASK, field CH3OM[3] (RW)
01924  *
01925  * Defines if the channel output is masked or unmasked.
01926  *
01927  * Values:
01928  * - 0 - Channel output is not masked. It continues to operate normally.
01929  * - 1 - Channel output is masked. It is forced to its inactive state.
01930  */
01931 /*@{*/
01932 #define BP_FTM_OUTMASK_CH3OM (3U)          /*!< Bit position for FTM_OUTMASK_CH3OM. */
01933 #define BM_FTM_OUTMASK_CH3OM (0x00000008U) /*!< Bit mask for FTM_OUTMASK_CH3OM. */
01934 #define BS_FTM_OUTMASK_CH3OM (1U)          /*!< Bit field size in bits for FTM_OUTMASK_CH3OM. */
01935 
01936 /*! @brief Read current value of the FTM_OUTMASK_CH3OM field. */
01937 #define BR_FTM_OUTMASK_CH3OM(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH3OM)))
01938 
01939 /*! @brief Format value for bitfield FTM_OUTMASK_CH3OM. */
01940 #define BF_FTM_OUTMASK_CH3OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH3OM) & BM_FTM_OUTMASK_CH3OM)
01941 
01942 /*! @brief Set the CH3OM field to a new value. */
01943 #define BW_FTM_OUTMASK_CH3OM(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH3OM), v))
01944 /*@}*/
01945 
01946 /*!
01947  * @name Register FTM_OUTMASK, field CH4OM[4] (RW)
01948  *
01949  * Defines if the channel output is masked or unmasked.
01950  *
01951  * Values:
01952  * - 0 - Channel output is not masked. It continues to operate normally.
01953  * - 1 - Channel output is masked. It is forced to its inactive state.
01954  */
01955 /*@{*/
01956 #define BP_FTM_OUTMASK_CH4OM (4U)          /*!< Bit position for FTM_OUTMASK_CH4OM. */
01957 #define BM_FTM_OUTMASK_CH4OM (0x00000010U) /*!< Bit mask for FTM_OUTMASK_CH4OM. */
01958 #define BS_FTM_OUTMASK_CH4OM (1U)          /*!< Bit field size in bits for FTM_OUTMASK_CH4OM. */
01959 
01960 /*! @brief Read current value of the FTM_OUTMASK_CH4OM field. */
01961 #define BR_FTM_OUTMASK_CH4OM(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH4OM)))
01962 
01963 /*! @brief Format value for bitfield FTM_OUTMASK_CH4OM. */
01964 #define BF_FTM_OUTMASK_CH4OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH4OM) & BM_FTM_OUTMASK_CH4OM)
01965 
01966 /*! @brief Set the CH4OM field to a new value. */
01967 #define BW_FTM_OUTMASK_CH4OM(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH4OM), v))
01968 /*@}*/
01969 
01970 /*!
01971  * @name Register FTM_OUTMASK, field CH5OM[5] (RW)
01972  *
01973  * Defines if the channel output is masked or unmasked.
01974  *
01975  * Values:
01976  * - 0 - Channel output is not masked. It continues to operate normally.
01977  * - 1 - Channel output is masked. It is forced to its inactive state.
01978  */
01979 /*@{*/
01980 #define BP_FTM_OUTMASK_CH5OM (5U)          /*!< Bit position for FTM_OUTMASK_CH5OM. */
01981 #define BM_FTM_OUTMASK_CH5OM (0x00000020U) /*!< Bit mask for FTM_OUTMASK_CH5OM. */
01982 #define BS_FTM_OUTMASK_CH5OM (1U)          /*!< Bit field size in bits for FTM_OUTMASK_CH5OM. */
01983 
01984 /*! @brief Read current value of the FTM_OUTMASK_CH5OM field. */
01985 #define BR_FTM_OUTMASK_CH5OM(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH5OM)))
01986 
01987 /*! @brief Format value for bitfield FTM_OUTMASK_CH5OM. */
01988 #define BF_FTM_OUTMASK_CH5OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH5OM) & BM_FTM_OUTMASK_CH5OM)
01989 
01990 /*! @brief Set the CH5OM field to a new value. */
01991 #define BW_FTM_OUTMASK_CH5OM(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH5OM), v))
01992 /*@}*/
01993 
01994 /*!
01995  * @name Register FTM_OUTMASK, field CH6OM[6] (RW)
01996  *
01997  * Defines if the channel output is masked or unmasked.
01998  *
01999  * Values:
02000  * - 0 - Channel output is not masked. It continues to operate normally.
02001  * - 1 - Channel output is masked. It is forced to its inactive state.
02002  */
02003 /*@{*/
02004 #define BP_FTM_OUTMASK_CH6OM (6U)          /*!< Bit position for FTM_OUTMASK_CH6OM. */
02005 #define BM_FTM_OUTMASK_CH6OM (0x00000040U) /*!< Bit mask for FTM_OUTMASK_CH6OM. */
02006 #define BS_FTM_OUTMASK_CH6OM (1U)          /*!< Bit field size in bits for FTM_OUTMASK_CH6OM. */
02007 
02008 /*! @brief Read current value of the FTM_OUTMASK_CH6OM field. */
02009 #define BR_FTM_OUTMASK_CH6OM(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH6OM)))
02010 
02011 /*! @brief Format value for bitfield FTM_OUTMASK_CH6OM. */
02012 #define BF_FTM_OUTMASK_CH6OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH6OM) & BM_FTM_OUTMASK_CH6OM)
02013 
02014 /*! @brief Set the CH6OM field to a new value. */
02015 #define BW_FTM_OUTMASK_CH6OM(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH6OM), v))
02016 /*@}*/
02017 
02018 /*!
02019  * @name Register FTM_OUTMASK, field CH7OM[7] (RW)
02020  *
02021  * Defines if the channel output is masked or unmasked.
02022  *
02023  * Values:
02024  * - 0 - Channel output is not masked. It continues to operate normally.
02025  * - 1 - Channel output is masked. It is forced to its inactive state.
02026  */
02027 /*@{*/
02028 #define BP_FTM_OUTMASK_CH7OM (7U)          /*!< Bit position for FTM_OUTMASK_CH7OM. */
02029 #define BM_FTM_OUTMASK_CH7OM (0x00000080U) /*!< Bit mask for FTM_OUTMASK_CH7OM. */
02030 #define BS_FTM_OUTMASK_CH7OM (1U)          /*!< Bit field size in bits for FTM_OUTMASK_CH7OM. */
02031 
02032 /*! @brief Read current value of the FTM_OUTMASK_CH7OM field. */
02033 #define BR_FTM_OUTMASK_CH7OM(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH7OM)))
02034 
02035 /*! @brief Format value for bitfield FTM_OUTMASK_CH7OM. */
02036 #define BF_FTM_OUTMASK_CH7OM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_OUTMASK_CH7OM) & BM_FTM_OUTMASK_CH7OM)
02037 
02038 /*! @brief Set the CH7OM field to a new value. */
02039 #define BW_FTM_OUTMASK_CH7OM(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_OUTMASK_ADDR(x), BP_FTM_OUTMASK_CH7OM), v))
02040 /*@}*/
02041 
02042 /*******************************************************************************
02043  * HW_FTM_COMBINE - Function For Linked Channels
02044  ******************************************************************************/
02045 
02046 /*!
02047  * @brief HW_FTM_COMBINE - Function For Linked Channels (RW)
02048  *
02049  * Reset value: 0x00000000U
02050  *
02051  * This register contains the control bits used to configure the fault control,
02052  * synchronization, deadtime insertion, Dual Edge Capture mode, Complementary,
02053  * and Combine mode for each pair of channels (n) and (n+1), where n equals 0, 2,
02054  * 4, and 6.
02055  */
02056 typedef union _hw_ftm_combine
02057 {
02058     uint32_t U;
02059     struct _hw_ftm_combine_bitfields
02060     {
02061         uint32_t COMBINE0 : 1;         /*!< [0] Combine Channels For n = 0 */
02062         uint32_t COMP0 : 1;            /*!< [1] Complement Of Channel (n) For n = 0 */
02063         uint32_t DECAPEN0 : 1;         /*!< [2] Dual Edge Capture Mode Enable For n =
02064                                         * 0 */
02065         uint32_t DECAP0 : 1;           /*!< [3] Dual Edge Capture Mode Captures For n =
02066                                         * 0 */
02067         uint32_t DTEN0 : 1;            /*!< [4] Deadtime Enable For n = 0 */
02068         uint32_t SYNCEN0 : 1;          /*!< [5] Synchronization Enable For n = 0 */
02069         uint32_t FAULTEN0 : 1;         /*!< [6] Fault Control Enable For n = 0 */
02070         uint32_t RESERVED0 : 1;        /*!< [7]  */
02071         uint32_t COMBINE1 : 1;         /*!< [8] Combine Channels For n = 2 */
02072         uint32_t COMP1 : 1;            /*!< [9] Complement Of Channel (n) For n = 2 */
02073         uint32_t DECAPEN1 : 1;         /*!< [10] Dual Edge Capture Mode Enable For n
02074                                         * = 2 */
02075         uint32_t DECAP1 : 1;           /*!< [11] Dual Edge Capture Mode Captures For n
02076                                         * = 2 */
02077         uint32_t DTEN1 : 1;            /*!< [12] Deadtime Enable For n = 2 */
02078         uint32_t SYNCEN1 : 1;          /*!< [13] Synchronization Enable For n = 2 */
02079         uint32_t FAULTEN1 : 1;         /*!< [14] Fault Control Enable For n = 2 */
02080         uint32_t RESERVED1 : 1;        /*!< [15]  */
02081         uint32_t COMBINE2 : 1;         /*!< [16] Combine Channels For n = 4 */
02082         uint32_t COMP2 : 1;            /*!< [17] Complement Of Channel (n) For n = 4 */
02083         uint32_t DECAPEN2 : 1;         /*!< [18] Dual Edge Capture Mode Enable For n
02084                                         * = 4 */
02085         uint32_t DECAP2 : 1;           /*!< [19] Dual Edge Capture Mode Captures For n
02086                                         * = 4 */
02087         uint32_t DTEN2 : 1;            /*!< [20] Deadtime Enable For n = 4 */
02088         uint32_t SYNCEN2 : 1;          /*!< [21] Synchronization Enable For n = 4 */
02089         uint32_t FAULTEN2 : 1;         /*!< [22] Fault Control Enable For n = 4 */
02090         uint32_t RESERVED2 : 1;        /*!< [23]  */
02091         uint32_t COMBINE3 : 1;         /*!< [24] Combine Channels For n = 6 */
02092         uint32_t COMP3 : 1;            /*!< [25] Complement Of Channel (n) for n = 6 */
02093         uint32_t DECAPEN3 : 1;         /*!< [26] Dual Edge Capture Mode Enable For n
02094                                         * = 6 */
02095         uint32_t DECAP3 : 1;           /*!< [27] Dual Edge Capture Mode Captures For n
02096                                         * = 6 */
02097         uint32_t DTEN3 : 1;            /*!< [28] Deadtime Enable For n = 6 */
02098         uint32_t SYNCEN3 : 1;          /*!< [29] Synchronization Enable For n = 6 */
02099         uint32_t FAULTEN3 : 1;         /*!< [30] Fault Control Enable For n = 6 */
02100         uint32_t RESERVED3 : 1;        /*!< [31]  */
02101     } B;
02102 } hw_ftm_combine_t;
02103 
02104 /*!
02105  * @name Constants and macros for entire FTM_COMBINE register
02106  */
02107 /*@{*/
02108 #define HW_FTM_COMBINE_ADDR(x)   ((x) + 0x64U)
02109 
02110 #define HW_FTM_COMBINE(x)        (*(__IO hw_ftm_combine_t *) HW_FTM_COMBINE_ADDR(x))
02111 #define HW_FTM_COMBINE_RD(x)     (ADDRESS_READ(hw_ftm_combine_t, HW_FTM_COMBINE_ADDR(x)))
02112 #define HW_FTM_COMBINE_WR(x, v)  (ADDRESS_WRITE(hw_ftm_combine_t, HW_FTM_COMBINE_ADDR(x), v))
02113 #define HW_FTM_COMBINE_SET(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) |  (v)))
02114 #define HW_FTM_COMBINE_CLR(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) & ~(v)))
02115 #define HW_FTM_COMBINE_TOG(x, v) (HW_FTM_COMBINE_WR(x, HW_FTM_COMBINE_RD(x) ^  (v)))
02116 /*@}*/
02117 
02118 /*
02119  * Constants & macros for individual FTM_COMBINE bitfields
02120  */
02121 
02122 /*!
02123  * @name Register FTM_COMBINE, field COMBINE0[0] (RW)
02124  *
02125  * Enables the combine feature for channels (n) and (n+1). This field is write
02126  * protected. It can be written only when MODE[WPDIS] = 1.
02127  *
02128  * Values:
02129  * - 0 - Channels (n) and (n+1) are independent.
02130  * - 1 - Channels (n) and (n+1) are combined.
02131  */
02132 /*@{*/
02133 #define BP_FTM_COMBINE_COMBINE0 (0U)       /*!< Bit position for FTM_COMBINE_COMBINE0. */
02134 #define BM_FTM_COMBINE_COMBINE0 (0x00000001U) /*!< Bit mask for FTM_COMBINE_COMBINE0. */
02135 #define BS_FTM_COMBINE_COMBINE0 (1U)       /*!< Bit field size in bits for FTM_COMBINE_COMBINE0. */
02136 
02137 /*! @brief Read current value of the FTM_COMBINE_COMBINE0 field. */
02138 #define BR_FTM_COMBINE_COMBINE0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE0)))
02139 
02140 /*! @brief Format value for bitfield FTM_COMBINE_COMBINE0. */
02141 #define BF_FTM_COMBINE_COMBINE0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE0) & BM_FTM_COMBINE_COMBINE0)
02142 
02143 /*! @brief Set the COMBINE0 field to a new value. */
02144 #define BW_FTM_COMBINE_COMBINE0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE0), v))
02145 /*@}*/
02146 
02147 /*!
02148  * @name Register FTM_COMBINE, field COMP0[1] (RW)
02149  *
02150  * Enables Complementary mode for the combined channels. In Complementary mode
02151  * the channel (n+1) output is the inverse of the channel (n) output. This field
02152  * is write protected. It can be written only when MODE[WPDIS] = 1.
02153  *
02154  * Values:
02155  * - 0 - The channel (n+1) output is the same as the channel (n) output.
02156  * - 1 - The channel (n+1) output is the complement of the channel (n) output.
02157  */
02158 /*@{*/
02159 #define BP_FTM_COMBINE_COMP0 (1U)          /*!< Bit position for FTM_COMBINE_COMP0. */
02160 #define BM_FTM_COMBINE_COMP0 (0x00000002U) /*!< Bit mask for FTM_COMBINE_COMP0. */
02161 #define BS_FTM_COMBINE_COMP0 (1U)          /*!< Bit field size in bits for FTM_COMBINE_COMP0. */
02162 
02163 /*! @brief Read current value of the FTM_COMBINE_COMP0 field. */
02164 #define BR_FTM_COMBINE_COMP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP0)))
02165 
02166 /*! @brief Format value for bitfield FTM_COMBINE_COMP0. */
02167 #define BF_FTM_COMBINE_COMP0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP0) & BM_FTM_COMBINE_COMP0)
02168 
02169 /*! @brief Set the COMP0 field to a new value. */
02170 #define BW_FTM_COMBINE_COMP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP0), v))
02171 /*@}*/
02172 
02173 /*!
02174  * @name Register FTM_COMBINE, field DECAPEN0[2] (RW)
02175  *
02176  * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
02177  * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
02178  * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
02179  * when FTMEN = 1. This field is write protected. It can be written only when
02180  * MODE[WPDIS] = 1.
02181  *
02182  * Values:
02183  * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
02184  * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
02185  */
02186 /*@{*/
02187 #define BP_FTM_COMBINE_DECAPEN0 (2U)       /*!< Bit position for FTM_COMBINE_DECAPEN0. */
02188 #define BM_FTM_COMBINE_DECAPEN0 (0x00000004U) /*!< Bit mask for FTM_COMBINE_DECAPEN0. */
02189 #define BS_FTM_COMBINE_DECAPEN0 (1U)       /*!< Bit field size in bits for FTM_COMBINE_DECAPEN0. */
02190 
02191 /*! @brief Read current value of the FTM_COMBINE_DECAPEN0 field. */
02192 #define BR_FTM_COMBINE_DECAPEN0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN0)))
02193 
02194 /*! @brief Format value for bitfield FTM_COMBINE_DECAPEN0. */
02195 #define BF_FTM_COMBINE_DECAPEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN0) & BM_FTM_COMBINE_DECAPEN0)
02196 
02197 /*! @brief Set the DECAPEN0 field to a new value. */
02198 #define BW_FTM_COMBINE_DECAPEN0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN0), v))
02199 /*@}*/
02200 
02201 /*!
02202  * @name Register FTM_COMBINE, field DECAP0[3] (RW)
02203  *
02204  * Enables the capture of the FTM counter value according to the channel (n)
02205  * input event and the configuration of the dual edge capture bits. This field
02206  * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
02207  * hardware if dual edge capture - one-shot mode is selected and when the capture
02208  * of channel (n+1) event is made.
02209  *
02210  * Values:
02211  * - 0 - The dual edge captures are inactive.
02212  * - 1 - The dual edge captures are active.
02213  */
02214 /*@{*/
02215 #define BP_FTM_COMBINE_DECAP0 (3U)         /*!< Bit position for FTM_COMBINE_DECAP0. */
02216 #define BM_FTM_COMBINE_DECAP0 (0x00000008U) /*!< Bit mask for FTM_COMBINE_DECAP0. */
02217 #define BS_FTM_COMBINE_DECAP0 (1U)         /*!< Bit field size in bits for FTM_COMBINE_DECAP0. */
02218 
02219 /*! @brief Read current value of the FTM_COMBINE_DECAP0 field. */
02220 #define BR_FTM_COMBINE_DECAP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP0)))
02221 
02222 /*! @brief Format value for bitfield FTM_COMBINE_DECAP0. */
02223 #define BF_FTM_COMBINE_DECAP0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP0) & BM_FTM_COMBINE_DECAP0)
02224 
02225 /*! @brief Set the DECAP0 field to a new value. */
02226 #define BW_FTM_COMBINE_DECAP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP0), v))
02227 /*@}*/
02228 
02229 /*!
02230  * @name Register FTM_COMBINE, field DTEN0[4] (RW)
02231  *
02232  * Enables the deadtime insertion in the channels (n) and (n+1). This field is
02233  * write protected. It can be written only when MODE[WPDIS] = 1.
02234  *
02235  * Values:
02236  * - 0 - The deadtime insertion in this pair of channels is disabled.
02237  * - 1 - The deadtime insertion in this pair of channels is enabled.
02238  */
02239 /*@{*/
02240 #define BP_FTM_COMBINE_DTEN0 (4U)          /*!< Bit position for FTM_COMBINE_DTEN0. */
02241 #define BM_FTM_COMBINE_DTEN0 (0x00000010U) /*!< Bit mask for FTM_COMBINE_DTEN0. */
02242 #define BS_FTM_COMBINE_DTEN0 (1U)          /*!< Bit field size in bits for FTM_COMBINE_DTEN0. */
02243 
02244 /*! @brief Read current value of the FTM_COMBINE_DTEN0 field. */
02245 #define BR_FTM_COMBINE_DTEN0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN0)))
02246 
02247 /*! @brief Format value for bitfield FTM_COMBINE_DTEN0. */
02248 #define BF_FTM_COMBINE_DTEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN0) & BM_FTM_COMBINE_DTEN0)
02249 
02250 /*! @brief Set the DTEN0 field to a new value. */
02251 #define BW_FTM_COMBINE_DTEN0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN0), v))
02252 /*@}*/
02253 
02254 /*!
02255  * @name Register FTM_COMBINE, field SYNCEN0[5] (RW)
02256  *
02257  * Enables PWM synchronization of registers C(n)V and C(n+1)V.
02258  *
02259  * Values:
02260  * - 0 - The PWM synchronization in this pair of channels is disabled.
02261  * - 1 - The PWM synchronization in this pair of channels is enabled.
02262  */
02263 /*@{*/
02264 #define BP_FTM_COMBINE_SYNCEN0 (5U)        /*!< Bit position for FTM_COMBINE_SYNCEN0. */
02265 #define BM_FTM_COMBINE_SYNCEN0 (0x00000020U) /*!< Bit mask for FTM_COMBINE_SYNCEN0. */
02266 #define BS_FTM_COMBINE_SYNCEN0 (1U)        /*!< Bit field size in bits for FTM_COMBINE_SYNCEN0. */
02267 
02268 /*! @brief Read current value of the FTM_COMBINE_SYNCEN0 field. */
02269 #define BR_FTM_COMBINE_SYNCEN0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN0)))
02270 
02271 /*! @brief Format value for bitfield FTM_COMBINE_SYNCEN0. */
02272 #define BF_FTM_COMBINE_SYNCEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN0) & BM_FTM_COMBINE_SYNCEN0)
02273 
02274 /*! @brief Set the SYNCEN0 field to a new value. */
02275 #define BW_FTM_COMBINE_SYNCEN0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN0), v))
02276 /*@}*/
02277 
02278 /*!
02279  * @name Register FTM_COMBINE, field FAULTEN0[6] (RW)
02280  *
02281  * Enables the fault control in channels (n) and (n+1). This field is write
02282  * protected. It can be written only when MODE[WPDIS] = 1.
02283  *
02284  * Values:
02285  * - 0 - The fault control in this pair of channels is disabled.
02286  * - 1 - The fault control in this pair of channels is enabled.
02287  */
02288 /*@{*/
02289 #define BP_FTM_COMBINE_FAULTEN0 (6U)       /*!< Bit position for FTM_COMBINE_FAULTEN0. */
02290 #define BM_FTM_COMBINE_FAULTEN0 (0x00000040U) /*!< Bit mask for FTM_COMBINE_FAULTEN0. */
02291 #define BS_FTM_COMBINE_FAULTEN0 (1U)       /*!< Bit field size in bits for FTM_COMBINE_FAULTEN0. */
02292 
02293 /*! @brief Read current value of the FTM_COMBINE_FAULTEN0 field. */
02294 #define BR_FTM_COMBINE_FAULTEN0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN0)))
02295 
02296 /*! @brief Format value for bitfield FTM_COMBINE_FAULTEN0. */
02297 #define BF_FTM_COMBINE_FAULTEN0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN0) & BM_FTM_COMBINE_FAULTEN0)
02298 
02299 /*! @brief Set the FAULTEN0 field to a new value. */
02300 #define BW_FTM_COMBINE_FAULTEN0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN0), v))
02301 /*@}*/
02302 
02303 /*!
02304  * @name Register FTM_COMBINE, field COMBINE1[8] (RW)
02305  *
02306  * Enables the combine feature for channels (n) and (n+1). This field is write
02307  * protected. It can be written only when MODE[WPDIS] = 1.
02308  *
02309  * Values:
02310  * - 0 - Channels (n) and (n+1) are independent.
02311  * - 1 - Channels (n) and (n+1) are combined.
02312  */
02313 /*@{*/
02314 #define BP_FTM_COMBINE_COMBINE1 (8U)       /*!< Bit position for FTM_COMBINE_COMBINE1. */
02315 #define BM_FTM_COMBINE_COMBINE1 (0x00000100U) /*!< Bit mask for FTM_COMBINE_COMBINE1. */
02316 #define BS_FTM_COMBINE_COMBINE1 (1U)       /*!< Bit field size in bits for FTM_COMBINE_COMBINE1. */
02317 
02318 /*! @brief Read current value of the FTM_COMBINE_COMBINE1 field. */
02319 #define BR_FTM_COMBINE_COMBINE1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE1)))
02320 
02321 /*! @brief Format value for bitfield FTM_COMBINE_COMBINE1. */
02322 #define BF_FTM_COMBINE_COMBINE1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE1) & BM_FTM_COMBINE_COMBINE1)
02323 
02324 /*! @brief Set the COMBINE1 field to a new value. */
02325 #define BW_FTM_COMBINE_COMBINE1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE1), v))
02326 /*@}*/
02327 
02328 /*!
02329  * @name Register FTM_COMBINE, field COMP1[9] (RW)
02330  *
02331  * Enables Complementary mode for the combined channels. In Complementary mode
02332  * the channel (n+1) output is the inverse of the channel (n) output. This field
02333  * is write protected. It can be written only when MODE[WPDIS] = 1.
02334  *
02335  * Values:
02336  * - 0 - The channel (n+1) output is the same as the channel (n) output.
02337  * - 1 - The channel (n+1) output is the complement of the channel (n) output.
02338  */
02339 /*@{*/
02340 #define BP_FTM_COMBINE_COMP1 (9U)          /*!< Bit position for FTM_COMBINE_COMP1. */
02341 #define BM_FTM_COMBINE_COMP1 (0x00000200U) /*!< Bit mask for FTM_COMBINE_COMP1. */
02342 #define BS_FTM_COMBINE_COMP1 (1U)          /*!< Bit field size in bits for FTM_COMBINE_COMP1. */
02343 
02344 /*! @brief Read current value of the FTM_COMBINE_COMP1 field. */
02345 #define BR_FTM_COMBINE_COMP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP1)))
02346 
02347 /*! @brief Format value for bitfield FTM_COMBINE_COMP1. */
02348 #define BF_FTM_COMBINE_COMP1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP1) & BM_FTM_COMBINE_COMP1)
02349 
02350 /*! @brief Set the COMP1 field to a new value. */
02351 #define BW_FTM_COMBINE_COMP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP1), v))
02352 /*@}*/
02353 
02354 /*!
02355  * @name Register FTM_COMBINE, field DECAPEN1[10] (RW)
02356  *
02357  * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
02358  * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
02359  * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
02360  * when FTMEN = 1. This field is write protected. It can be written only when
02361  * MODE[WPDIS] = 1.
02362  *
02363  * Values:
02364  * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
02365  * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
02366  */
02367 /*@{*/
02368 #define BP_FTM_COMBINE_DECAPEN1 (10U)      /*!< Bit position for FTM_COMBINE_DECAPEN1. */
02369 #define BM_FTM_COMBINE_DECAPEN1 (0x00000400U) /*!< Bit mask for FTM_COMBINE_DECAPEN1. */
02370 #define BS_FTM_COMBINE_DECAPEN1 (1U)       /*!< Bit field size in bits for FTM_COMBINE_DECAPEN1. */
02371 
02372 /*! @brief Read current value of the FTM_COMBINE_DECAPEN1 field. */
02373 #define BR_FTM_COMBINE_DECAPEN1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN1)))
02374 
02375 /*! @brief Format value for bitfield FTM_COMBINE_DECAPEN1. */
02376 #define BF_FTM_COMBINE_DECAPEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN1) & BM_FTM_COMBINE_DECAPEN1)
02377 
02378 /*! @brief Set the DECAPEN1 field to a new value. */
02379 #define BW_FTM_COMBINE_DECAPEN1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN1), v))
02380 /*@}*/
02381 
02382 /*!
02383  * @name Register FTM_COMBINE, field DECAP1[11] (RW)
02384  *
02385  * Enables the capture of the FTM counter value according to the channel (n)
02386  * input event and the configuration of the dual edge capture bits. This field
02387  * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
02388  * hardware if Dual Edge Capture - One-Shot mode is selected and when the capture
02389  * of channel (n+1) event is made.
02390  *
02391  * Values:
02392  * - 0 - The dual edge captures are inactive.
02393  * - 1 - The dual edge captures are active.
02394  */
02395 /*@{*/
02396 #define BP_FTM_COMBINE_DECAP1 (11U)        /*!< Bit position for FTM_COMBINE_DECAP1. */
02397 #define BM_FTM_COMBINE_DECAP1 (0x00000800U) /*!< Bit mask for FTM_COMBINE_DECAP1. */
02398 #define BS_FTM_COMBINE_DECAP1 (1U)         /*!< Bit field size in bits for FTM_COMBINE_DECAP1. */
02399 
02400 /*! @brief Read current value of the FTM_COMBINE_DECAP1 field. */
02401 #define BR_FTM_COMBINE_DECAP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP1)))
02402 
02403 /*! @brief Format value for bitfield FTM_COMBINE_DECAP1. */
02404 #define BF_FTM_COMBINE_DECAP1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP1) & BM_FTM_COMBINE_DECAP1)
02405 
02406 /*! @brief Set the DECAP1 field to a new value. */
02407 #define BW_FTM_COMBINE_DECAP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP1), v))
02408 /*@}*/
02409 
02410 /*!
02411  * @name Register FTM_COMBINE, field DTEN1[12] (RW)
02412  *
02413  * Enables the deadtime insertion in the channels (n) and (n+1). This field is
02414  * write protected. It can be written only when MODE[WPDIS] = 1.
02415  *
02416  * Values:
02417  * - 0 - The deadtime insertion in this pair of channels is disabled.
02418  * - 1 - The deadtime insertion in this pair of channels is enabled.
02419  */
02420 /*@{*/
02421 #define BP_FTM_COMBINE_DTEN1 (12U)         /*!< Bit position for FTM_COMBINE_DTEN1. */
02422 #define BM_FTM_COMBINE_DTEN1 (0x00001000U) /*!< Bit mask for FTM_COMBINE_DTEN1. */
02423 #define BS_FTM_COMBINE_DTEN1 (1U)          /*!< Bit field size in bits for FTM_COMBINE_DTEN1. */
02424 
02425 /*! @brief Read current value of the FTM_COMBINE_DTEN1 field. */
02426 #define BR_FTM_COMBINE_DTEN1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN1)))
02427 
02428 /*! @brief Format value for bitfield FTM_COMBINE_DTEN1. */
02429 #define BF_FTM_COMBINE_DTEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN1) & BM_FTM_COMBINE_DTEN1)
02430 
02431 /*! @brief Set the DTEN1 field to a new value. */
02432 #define BW_FTM_COMBINE_DTEN1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN1), v))
02433 /*@}*/
02434 
02435 /*!
02436  * @name Register FTM_COMBINE, field SYNCEN1[13] (RW)
02437  *
02438  * Enables PWM synchronization of registers C(n)V and C(n+1)V.
02439  *
02440  * Values:
02441  * - 0 - The PWM synchronization in this pair of channels is disabled.
02442  * - 1 - The PWM synchronization in this pair of channels is enabled.
02443  */
02444 /*@{*/
02445 #define BP_FTM_COMBINE_SYNCEN1 (13U)       /*!< Bit position for FTM_COMBINE_SYNCEN1. */
02446 #define BM_FTM_COMBINE_SYNCEN1 (0x00002000U) /*!< Bit mask for FTM_COMBINE_SYNCEN1. */
02447 #define BS_FTM_COMBINE_SYNCEN1 (1U)        /*!< Bit field size in bits for FTM_COMBINE_SYNCEN1. */
02448 
02449 /*! @brief Read current value of the FTM_COMBINE_SYNCEN1 field. */
02450 #define BR_FTM_COMBINE_SYNCEN1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN1)))
02451 
02452 /*! @brief Format value for bitfield FTM_COMBINE_SYNCEN1. */
02453 #define BF_FTM_COMBINE_SYNCEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN1) & BM_FTM_COMBINE_SYNCEN1)
02454 
02455 /*! @brief Set the SYNCEN1 field to a new value. */
02456 #define BW_FTM_COMBINE_SYNCEN1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN1), v))
02457 /*@}*/
02458 
02459 /*!
02460  * @name Register FTM_COMBINE, field FAULTEN1[14] (RW)
02461  *
02462  * Enables the fault control in channels (n) and (n+1). This field is write
02463  * protected. It can be written only when MODE[WPDIS] = 1.
02464  *
02465  * Values:
02466  * - 0 - The fault control in this pair of channels is disabled.
02467  * - 1 - The fault control in this pair of channels is enabled.
02468  */
02469 /*@{*/
02470 #define BP_FTM_COMBINE_FAULTEN1 (14U)      /*!< Bit position for FTM_COMBINE_FAULTEN1. */
02471 #define BM_FTM_COMBINE_FAULTEN1 (0x00004000U) /*!< Bit mask for FTM_COMBINE_FAULTEN1. */
02472 #define BS_FTM_COMBINE_FAULTEN1 (1U)       /*!< Bit field size in bits for FTM_COMBINE_FAULTEN1. */
02473 
02474 /*! @brief Read current value of the FTM_COMBINE_FAULTEN1 field. */
02475 #define BR_FTM_COMBINE_FAULTEN1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN1)))
02476 
02477 /*! @brief Format value for bitfield FTM_COMBINE_FAULTEN1. */
02478 #define BF_FTM_COMBINE_FAULTEN1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN1) & BM_FTM_COMBINE_FAULTEN1)
02479 
02480 /*! @brief Set the FAULTEN1 field to a new value. */
02481 #define BW_FTM_COMBINE_FAULTEN1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN1), v))
02482 /*@}*/
02483 
02484 /*!
02485  * @name Register FTM_COMBINE, field COMBINE2[16] (RW)
02486  *
02487  * Enables the combine feature for channels (n) and (n+1). This field is write
02488  * protected. It can be written only when MODE[WPDIS] = 1.
02489  *
02490  * Values:
02491  * - 0 - Channels (n) and (n+1) are independent.
02492  * - 1 - Channels (n) and (n+1) are combined.
02493  */
02494 /*@{*/
02495 #define BP_FTM_COMBINE_COMBINE2 (16U)      /*!< Bit position for FTM_COMBINE_COMBINE2. */
02496 #define BM_FTM_COMBINE_COMBINE2 (0x00010000U) /*!< Bit mask for FTM_COMBINE_COMBINE2. */
02497 #define BS_FTM_COMBINE_COMBINE2 (1U)       /*!< Bit field size in bits for FTM_COMBINE_COMBINE2. */
02498 
02499 /*! @brief Read current value of the FTM_COMBINE_COMBINE2 field. */
02500 #define BR_FTM_COMBINE_COMBINE2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE2)))
02501 
02502 /*! @brief Format value for bitfield FTM_COMBINE_COMBINE2. */
02503 #define BF_FTM_COMBINE_COMBINE2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE2) & BM_FTM_COMBINE_COMBINE2)
02504 
02505 /*! @brief Set the COMBINE2 field to a new value. */
02506 #define BW_FTM_COMBINE_COMBINE2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE2), v))
02507 /*@}*/
02508 
02509 /*!
02510  * @name Register FTM_COMBINE, field COMP2[17] (RW)
02511  *
02512  * Enables Complementary mode for the combined channels. In Complementary mode
02513  * the channel (n+1) output is the inverse of the channel (n) output. This field
02514  * is write protected. It can be written only when MODE[WPDIS] = 1.
02515  *
02516  * Values:
02517  * - 0 - The channel (n+1) output is the same as the channel (n) output.
02518  * - 1 - The channel (n+1) output is the complement of the channel (n) output.
02519  */
02520 /*@{*/
02521 #define BP_FTM_COMBINE_COMP2 (17U)         /*!< Bit position for FTM_COMBINE_COMP2. */
02522 #define BM_FTM_COMBINE_COMP2 (0x00020000U) /*!< Bit mask for FTM_COMBINE_COMP2. */
02523 #define BS_FTM_COMBINE_COMP2 (1U)          /*!< Bit field size in bits for FTM_COMBINE_COMP2. */
02524 
02525 /*! @brief Read current value of the FTM_COMBINE_COMP2 field. */
02526 #define BR_FTM_COMBINE_COMP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP2)))
02527 
02528 /*! @brief Format value for bitfield FTM_COMBINE_COMP2. */
02529 #define BF_FTM_COMBINE_COMP2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP2) & BM_FTM_COMBINE_COMP2)
02530 
02531 /*! @brief Set the COMP2 field to a new value. */
02532 #define BW_FTM_COMBINE_COMP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP2), v))
02533 /*@}*/
02534 
02535 /*!
02536  * @name Register FTM_COMBINE, field DECAPEN2[18] (RW)
02537  *
02538  * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
02539  * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
02540  * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
02541  * when FTMEN = 1. This field is write protected. It can be written only when
02542  * MODE[WPDIS] = 1.
02543  *
02544  * Values:
02545  * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
02546  * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
02547  */
02548 /*@{*/
02549 #define BP_FTM_COMBINE_DECAPEN2 (18U)      /*!< Bit position for FTM_COMBINE_DECAPEN2. */
02550 #define BM_FTM_COMBINE_DECAPEN2 (0x00040000U) /*!< Bit mask for FTM_COMBINE_DECAPEN2. */
02551 #define BS_FTM_COMBINE_DECAPEN2 (1U)       /*!< Bit field size in bits for FTM_COMBINE_DECAPEN2. */
02552 
02553 /*! @brief Read current value of the FTM_COMBINE_DECAPEN2 field. */
02554 #define BR_FTM_COMBINE_DECAPEN2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN2)))
02555 
02556 /*! @brief Format value for bitfield FTM_COMBINE_DECAPEN2. */
02557 #define BF_FTM_COMBINE_DECAPEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN2) & BM_FTM_COMBINE_DECAPEN2)
02558 
02559 /*! @brief Set the DECAPEN2 field to a new value. */
02560 #define BW_FTM_COMBINE_DECAPEN2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN2), v))
02561 /*@}*/
02562 
02563 /*!
02564  * @name Register FTM_COMBINE, field DECAP2[19] (RW)
02565  *
02566  * Enables the capture of the FTM counter value according to the channel (n)
02567  * input event and the configuration of the dual edge capture bits. This field
02568  * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
02569  * hardware if dual edge capture - one-shot mode is selected and when the capture
02570  * of channel (n+1) event is made.
02571  *
02572  * Values:
02573  * - 0 - The dual edge captures are inactive.
02574  * - 1 - The dual edge captures are active.
02575  */
02576 /*@{*/
02577 #define BP_FTM_COMBINE_DECAP2 (19U)        /*!< Bit position for FTM_COMBINE_DECAP2. */
02578 #define BM_FTM_COMBINE_DECAP2 (0x00080000U) /*!< Bit mask for FTM_COMBINE_DECAP2. */
02579 #define BS_FTM_COMBINE_DECAP2 (1U)         /*!< Bit field size in bits for FTM_COMBINE_DECAP2. */
02580 
02581 /*! @brief Read current value of the FTM_COMBINE_DECAP2 field. */
02582 #define BR_FTM_COMBINE_DECAP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP2)))
02583 
02584 /*! @brief Format value for bitfield FTM_COMBINE_DECAP2. */
02585 #define BF_FTM_COMBINE_DECAP2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP2) & BM_FTM_COMBINE_DECAP2)
02586 
02587 /*! @brief Set the DECAP2 field to a new value. */
02588 #define BW_FTM_COMBINE_DECAP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP2), v))
02589 /*@}*/
02590 
02591 /*!
02592  * @name Register FTM_COMBINE, field DTEN2[20] (RW)
02593  *
02594  * Enables the deadtime insertion in the channels (n) and (n+1). This field is
02595  * write protected. It can be written only when MODE[WPDIS] = 1.
02596  *
02597  * Values:
02598  * - 0 - The deadtime insertion in this pair of channels is disabled.
02599  * - 1 - The deadtime insertion in this pair of channels is enabled.
02600  */
02601 /*@{*/
02602 #define BP_FTM_COMBINE_DTEN2 (20U)         /*!< Bit position for FTM_COMBINE_DTEN2. */
02603 #define BM_FTM_COMBINE_DTEN2 (0x00100000U) /*!< Bit mask for FTM_COMBINE_DTEN2. */
02604 #define BS_FTM_COMBINE_DTEN2 (1U)          /*!< Bit field size in bits for FTM_COMBINE_DTEN2. */
02605 
02606 /*! @brief Read current value of the FTM_COMBINE_DTEN2 field. */
02607 #define BR_FTM_COMBINE_DTEN2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN2)))
02608 
02609 /*! @brief Format value for bitfield FTM_COMBINE_DTEN2. */
02610 #define BF_FTM_COMBINE_DTEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN2) & BM_FTM_COMBINE_DTEN2)
02611 
02612 /*! @brief Set the DTEN2 field to a new value. */
02613 #define BW_FTM_COMBINE_DTEN2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN2), v))
02614 /*@}*/
02615 
02616 /*!
02617  * @name Register FTM_COMBINE, field SYNCEN2[21] (RW)
02618  *
02619  * Enables PWM synchronization of registers C(n)V and C(n+1)V.
02620  *
02621  * Values:
02622  * - 0 - The PWM synchronization in this pair of channels is disabled.
02623  * - 1 - The PWM synchronization in this pair of channels is enabled.
02624  */
02625 /*@{*/
02626 #define BP_FTM_COMBINE_SYNCEN2 (21U)       /*!< Bit position for FTM_COMBINE_SYNCEN2. */
02627 #define BM_FTM_COMBINE_SYNCEN2 (0x00200000U) /*!< Bit mask for FTM_COMBINE_SYNCEN2. */
02628 #define BS_FTM_COMBINE_SYNCEN2 (1U)        /*!< Bit field size in bits for FTM_COMBINE_SYNCEN2. */
02629 
02630 /*! @brief Read current value of the FTM_COMBINE_SYNCEN2 field. */
02631 #define BR_FTM_COMBINE_SYNCEN2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN2)))
02632 
02633 /*! @brief Format value for bitfield FTM_COMBINE_SYNCEN2. */
02634 #define BF_FTM_COMBINE_SYNCEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN2) & BM_FTM_COMBINE_SYNCEN2)
02635 
02636 /*! @brief Set the SYNCEN2 field to a new value. */
02637 #define BW_FTM_COMBINE_SYNCEN2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN2), v))
02638 /*@}*/
02639 
02640 /*!
02641  * @name Register FTM_COMBINE, field FAULTEN2[22] (RW)
02642  *
02643  * Enables the fault control in channels (n) and (n+1). This field is write
02644  * protected. It can be written only when MODE[WPDIS] = 1.
02645  *
02646  * Values:
02647  * - 0 - The fault control in this pair of channels is disabled.
02648  * - 1 - The fault control in this pair of channels is enabled.
02649  */
02650 /*@{*/
02651 #define BP_FTM_COMBINE_FAULTEN2 (22U)      /*!< Bit position for FTM_COMBINE_FAULTEN2. */
02652 #define BM_FTM_COMBINE_FAULTEN2 (0x00400000U) /*!< Bit mask for FTM_COMBINE_FAULTEN2. */
02653 #define BS_FTM_COMBINE_FAULTEN2 (1U)       /*!< Bit field size in bits for FTM_COMBINE_FAULTEN2. */
02654 
02655 /*! @brief Read current value of the FTM_COMBINE_FAULTEN2 field. */
02656 #define BR_FTM_COMBINE_FAULTEN2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN2)))
02657 
02658 /*! @brief Format value for bitfield FTM_COMBINE_FAULTEN2. */
02659 #define BF_FTM_COMBINE_FAULTEN2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN2) & BM_FTM_COMBINE_FAULTEN2)
02660 
02661 /*! @brief Set the FAULTEN2 field to a new value. */
02662 #define BW_FTM_COMBINE_FAULTEN2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN2), v))
02663 /*@}*/
02664 
02665 /*!
02666  * @name Register FTM_COMBINE, field COMBINE3[24] (RW)
02667  *
02668  * Enables the combine feature for channels (n) and (n+1). This field is write
02669  * protected. It can be written only when MODE[WPDIS] = 1.
02670  *
02671  * Values:
02672  * - 0 - Channels (n) and (n+1) are independent.
02673  * - 1 - Channels (n) and (n+1) are combined.
02674  */
02675 /*@{*/
02676 #define BP_FTM_COMBINE_COMBINE3 (24U)      /*!< Bit position for FTM_COMBINE_COMBINE3. */
02677 #define BM_FTM_COMBINE_COMBINE3 (0x01000000U) /*!< Bit mask for FTM_COMBINE_COMBINE3. */
02678 #define BS_FTM_COMBINE_COMBINE3 (1U)       /*!< Bit field size in bits for FTM_COMBINE_COMBINE3. */
02679 
02680 /*! @brief Read current value of the FTM_COMBINE_COMBINE3 field. */
02681 #define BR_FTM_COMBINE_COMBINE3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE3)))
02682 
02683 /*! @brief Format value for bitfield FTM_COMBINE_COMBINE3. */
02684 #define BF_FTM_COMBINE_COMBINE3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMBINE3) & BM_FTM_COMBINE_COMBINE3)
02685 
02686 /*! @brief Set the COMBINE3 field to a new value. */
02687 #define BW_FTM_COMBINE_COMBINE3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMBINE3), v))
02688 /*@}*/
02689 
02690 /*!
02691  * @name Register FTM_COMBINE, field COMP3[25] (RW)
02692  *
02693  * Enables Complementary mode for the combined channels. In Complementary mode
02694  * the channel (n+1) output is the inverse of the channel (n) output. This field
02695  * is write protected. It can be written only when MODE[WPDIS] = 1.
02696  *
02697  * Values:
02698  * - 0 - The channel (n+1) output is the same as the channel (n) output.
02699  * - 1 - The channel (n+1) output is the complement of the channel (n) output.
02700  */
02701 /*@{*/
02702 #define BP_FTM_COMBINE_COMP3 (25U)         /*!< Bit position for FTM_COMBINE_COMP3. */
02703 #define BM_FTM_COMBINE_COMP3 (0x02000000U) /*!< Bit mask for FTM_COMBINE_COMP3. */
02704 #define BS_FTM_COMBINE_COMP3 (1U)          /*!< Bit field size in bits for FTM_COMBINE_COMP3. */
02705 
02706 /*! @brief Read current value of the FTM_COMBINE_COMP3 field. */
02707 #define BR_FTM_COMBINE_COMP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP3)))
02708 
02709 /*! @brief Format value for bitfield FTM_COMBINE_COMP3. */
02710 #define BF_FTM_COMBINE_COMP3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_COMP3) & BM_FTM_COMBINE_COMP3)
02711 
02712 /*! @brief Set the COMP3 field to a new value. */
02713 #define BW_FTM_COMBINE_COMP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_COMP3), v))
02714 /*@}*/
02715 
02716 /*!
02717  * @name Register FTM_COMBINE, field DECAPEN3[26] (RW)
02718  *
02719  * Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit
02720  * reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in
02721  * Dual Edge Capture mode according to #ModeSel1Table. This field applies only
02722  * when FTMEN = 1. This field is write protected. It can be written only when
02723  * MODE[WPDIS] = 1.
02724  *
02725  * Values:
02726  * - 0 - The Dual Edge Capture mode in this pair of channels is disabled.
02727  * - 1 - The Dual Edge Capture mode in this pair of channels is enabled.
02728  */
02729 /*@{*/
02730 #define BP_FTM_COMBINE_DECAPEN3 (26U)      /*!< Bit position for FTM_COMBINE_DECAPEN3. */
02731 #define BM_FTM_COMBINE_DECAPEN3 (0x04000000U) /*!< Bit mask for FTM_COMBINE_DECAPEN3. */
02732 #define BS_FTM_COMBINE_DECAPEN3 (1U)       /*!< Bit field size in bits for FTM_COMBINE_DECAPEN3. */
02733 
02734 /*! @brief Read current value of the FTM_COMBINE_DECAPEN3 field. */
02735 #define BR_FTM_COMBINE_DECAPEN3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN3)))
02736 
02737 /*! @brief Format value for bitfield FTM_COMBINE_DECAPEN3. */
02738 #define BF_FTM_COMBINE_DECAPEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAPEN3) & BM_FTM_COMBINE_DECAPEN3)
02739 
02740 /*! @brief Set the DECAPEN3 field to a new value. */
02741 #define BW_FTM_COMBINE_DECAPEN3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAPEN3), v))
02742 /*@}*/
02743 
02744 /*!
02745  * @name Register FTM_COMBINE, field DECAP3[27] (RW)
02746  *
02747  * Enables the capture of the FTM counter value according to the channel (n)
02748  * input event and the configuration of the dual edge capture bits. This field
02749  * applies only when FTMEN = 1 and DECAPEN = 1. DECAP bit is cleared automatically by
02750  * hardware if dual edge capture - one-shot mode is selected and when the capture
02751  * of channel (n+1) event is made.
02752  *
02753  * Values:
02754  * - 0 - The dual edge captures are inactive.
02755  * - 1 - The dual edge captures are active.
02756  */
02757 /*@{*/
02758 #define BP_FTM_COMBINE_DECAP3 (27U)        /*!< Bit position for FTM_COMBINE_DECAP3. */
02759 #define BM_FTM_COMBINE_DECAP3 (0x08000000U) /*!< Bit mask for FTM_COMBINE_DECAP3. */
02760 #define BS_FTM_COMBINE_DECAP3 (1U)         /*!< Bit field size in bits for FTM_COMBINE_DECAP3. */
02761 
02762 /*! @brief Read current value of the FTM_COMBINE_DECAP3 field. */
02763 #define BR_FTM_COMBINE_DECAP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP3)))
02764 
02765 /*! @brief Format value for bitfield FTM_COMBINE_DECAP3. */
02766 #define BF_FTM_COMBINE_DECAP3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DECAP3) & BM_FTM_COMBINE_DECAP3)
02767 
02768 /*! @brief Set the DECAP3 field to a new value. */
02769 #define BW_FTM_COMBINE_DECAP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DECAP3), v))
02770 /*@}*/
02771 
02772 /*!
02773  * @name Register FTM_COMBINE, field DTEN3[28] (RW)
02774  *
02775  * Enables the deadtime insertion in the channels (n) and (n+1). This field is
02776  * write protected. It can be written only when MODE[WPDIS] = 1.
02777  *
02778  * Values:
02779  * - 0 - The deadtime insertion in this pair of channels is disabled.
02780  * - 1 - The deadtime insertion in this pair of channels is enabled.
02781  */
02782 /*@{*/
02783 #define BP_FTM_COMBINE_DTEN3 (28U)         /*!< Bit position for FTM_COMBINE_DTEN3. */
02784 #define BM_FTM_COMBINE_DTEN3 (0x10000000U) /*!< Bit mask for FTM_COMBINE_DTEN3. */
02785 #define BS_FTM_COMBINE_DTEN3 (1U)          /*!< Bit field size in bits for FTM_COMBINE_DTEN3. */
02786 
02787 /*! @brief Read current value of the FTM_COMBINE_DTEN3 field. */
02788 #define BR_FTM_COMBINE_DTEN3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN3)))
02789 
02790 /*! @brief Format value for bitfield FTM_COMBINE_DTEN3. */
02791 #define BF_FTM_COMBINE_DTEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_DTEN3) & BM_FTM_COMBINE_DTEN3)
02792 
02793 /*! @brief Set the DTEN3 field to a new value. */
02794 #define BW_FTM_COMBINE_DTEN3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_DTEN3), v))
02795 /*@}*/
02796 
02797 /*!
02798  * @name Register FTM_COMBINE, field SYNCEN3[29] (RW)
02799  *
02800  * Enables PWM synchronization of registers C(n)V and C(n+1)V.
02801  *
02802  * Values:
02803  * - 0 - The PWM synchronization in this pair of channels is disabled.
02804  * - 1 - The PWM synchronization in this pair of channels is enabled.
02805  */
02806 /*@{*/
02807 #define BP_FTM_COMBINE_SYNCEN3 (29U)       /*!< Bit position for FTM_COMBINE_SYNCEN3. */
02808 #define BM_FTM_COMBINE_SYNCEN3 (0x20000000U) /*!< Bit mask for FTM_COMBINE_SYNCEN3. */
02809 #define BS_FTM_COMBINE_SYNCEN3 (1U)        /*!< Bit field size in bits for FTM_COMBINE_SYNCEN3. */
02810 
02811 /*! @brief Read current value of the FTM_COMBINE_SYNCEN3 field. */
02812 #define BR_FTM_COMBINE_SYNCEN3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN3)))
02813 
02814 /*! @brief Format value for bitfield FTM_COMBINE_SYNCEN3. */
02815 #define BF_FTM_COMBINE_SYNCEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_SYNCEN3) & BM_FTM_COMBINE_SYNCEN3)
02816 
02817 /*! @brief Set the SYNCEN3 field to a new value. */
02818 #define BW_FTM_COMBINE_SYNCEN3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_SYNCEN3), v))
02819 /*@}*/
02820 
02821 /*!
02822  * @name Register FTM_COMBINE, field FAULTEN3[30] (RW)
02823  *
02824  * Enables the fault control in channels (n) and (n+1). This field is write
02825  * protected. It can be written only when MODE[WPDIS] = 1.
02826  *
02827  * Values:
02828  * - 0 - The fault control in this pair of channels is disabled.
02829  * - 1 - The fault control in this pair of channels is enabled.
02830  */
02831 /*@{*/
02832 #define BP_FTM_COMBINE_FAULTEN3 (30U)      /*!< Bit position for FTM_COMBINE_FAULTEN3. */
02833 #define BM_FTM_COMBINE_FAULTEN3 (0x40000000U) /*!< Bit mask for FTM_COMBINE_FAULTEN3. */
02834 #define BS_FTM_COMBINE_FAULTEN3 (1U)       /*!< Bit field size in bits for FTM_COMBINE_FAULTEN3. */
02835 
02836 /*! @brief Read current value of the FTM_COMBINE_FAULTEN3 field. */
02837 #define BR_FTM_COMBINE_FAULTEN3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN3)))
02838 
02839 /*! @brief Format value for bitfield FTM_COMBINE_FAULTEN3. */
02840 #define BF_FTM_COMBINE_FAULTEN3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_COMBINE_FAULTEN3) & BM_FTM_COMBINE_FAULTEN3)
02841 
02842 /*! @brief Set the FAULTEN3 field to a new value. */
02843 #define BW_FTM_COMBINE_FAULTEN3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_COMBINE_ADDR(x), BP_FTM_COMBINE_FAULTEN3), v))
02844 /*@}*/
02845 
02846 /*******************************************************************************
02847  * HW_FTM_DEADTIME - Deadtime Insertion Control
02848  ******************************************************************************/
02849 
02850 /*!
02851  * @brief HW_FTM_DEADTIME - Deadtime Insertion Control (RW)
02852  *
02853  * Reset value: 0x00000000U
02854  *
02855  * This register selects the deadtime prescaler factor and deadtime value. All
02856  * FTM channels use this clock prescaler and this deadtime value for the deadtime
02857  * insertion.
02858  */
02859 typedef union _hw_ftm_deadtime
02860 {
02861     uint32_t U;
02862     struct _hw_ftm_deadtime_bitfields
02863     {
02864         uint32_t DTVAL : 6;            /*!< [5:0] Deadtime Value */
02865         uint32_t DTPS : 2;             /*!< [7:6] Deadtime Prescaler Value */
02866         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
02867     } B;
02868 } hw_ftm_deadtime_t;
02869 
02870 /*!
02871  * @name Constants and macros for entire FTM_DEADTIME register
02872  */
02873 /*@{*/
02874 #define HW_FTM_DEADTIME_ADDR(x)  ((x) + 0x68U)
02875 
02876 #define HW_FTM_DEADTIME(x)       (*(__IO hw_ftm_deadtime_t *) HW_FTM_DEADTIME_ADDR(x))
02877 #define HW_FTM_DEADTIME_RD(x)    (ADDRESS_READ(hw_ftm_deadtime_t, HW_FTM_DEADTIME_ADDR(x)))
02878 #define HW_FTM_DEADTIME_WR(x, v) (ADDRESS_WRITE(hw_ftm_deadtime_t, HW_FTM_DEADTIME_ADDR(x), v))
02879 #define HW_FTM_DEADTIME_SET(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) |  (v)))
02880 #define HW_FTM_DEADTIME_CLR(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) & ~(v)))
02881 #define HW_FTM_DEADTIME_TOG(x, v) (HW_FTM_DEADTIME_WR(x, HW_FTM_DEADTIME_RD(x) ^  (v)))
02882 /*@}*/
02883 
02884 /*
02885  * Constants & macros for individual FTM_DEADTIME bitfields
02886  */
02887 
02888 /*!
02889  * @name Register FTM_DEADTIME, field DTVAL[5:0] (RW)
02890  *
02891  * Selects the deadtime insertion value for the deadtime counter. The deadtime
02892  * counter is clocked by a scaled version of the system clock. See the description
02893  * of DTPS. Deadtime insert value = (DTPS * DTVAL). DTVAL selects the number of
02894  * deadtime counts inserted as follows: When DTVAL is 0, no counts are inserted.
02895  * When DTVAL is 1, 1 count is inserted. When DTVAL is 2, 2 counts are inserted.
02896  * This pattern continues up to a possible 63 counts. This field is write
02897  * protected. It can be written only when MODE[WPDIS] = 1.
02898  */
02899 /*@{*/
02900 #define BP_FTM_DEADTIME_DTVAL (0U)         /*!< Bit position for FTM_DEADTIME_DTVAL. */
02901 #define BM_FTM_DEADTIME_DTVAL (0x0000003FU) /*!< Bit mask for FTM_DEADTIME_DTVAL. */
02902 #define BS_FTM_DEADTIME_DTVAL (6U)         /*!< Bit field size in bits for FTM_DEADTIME_DTVAL. */
02903 
02904 /*! @brief Read current value of the FTM_DEADTIME_DTVAL field. */
02905 #define BR_FTM_DEADTIME_DTVAL(x) (UNION_READ(hw_ftm_deadtime_t, HW_FTM_DEADTIME_ADDR(x), U, B.DTVAL))
02906 
02907 /*! @brief Format value for bitfield FTM_DEADTIME_DTVAL. */
02908 #define BF_FTM_DEADTIME_DTVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_DEADTIME_DTVAL) & BM_FTM_DEADTIME_DTVAL)
02909 
02910 /*! @brief Set the DTVAL field to a new value. */
02911 #define BW_FTM_DEADTIME_DTVAL(x, v) (HW_FTM_DEADTIME_WR(x, (HW_FTM_DEADTIME_RD(x) & ~BM_FTM_DEADTIME_DTVAL) | BF_FTM_DEADTIME_DTVAL(v)))
02912 /*@}*/
02913 
02914 /*!
02915  * @name Register FTM_DEADTIME, field DTPS[7:6] (RW)
02916  *
02917  * Selects the division factor of the system clock. This prescaled clock is used
02918  * by the deadtime counter. This field is write protected. It can be written
02919  * only when MODE[WPDIS] = 1.
02920  *
02921  * Values:
02922  * - 0x - Divide the system clock by 1.
02923  * - 10 - Divide the system clock by 4.
02924  * - 11 - Divide the system clock by 16.
02925  */
02926 /*@{*/
02927 #define BP_FTM_DEADTIME_DTPS (6U)          /*!< Bit position for FTM_DEADTIME_DTPS. */
02928 #define BM_FTM_DEADTIME_DTPS (0x000000C0U) /*!< Bit mask for FTM_DEADTIME_DTPS. */
02929 #define BS_FTM_DEADTIME_DTPS (2U)          /*!< Bit field size in bits for FTM_DEADTIME_DTPS. */
02930 
02931 /*! @brief Read current value of the FTM_DEADTIME_DTPS field. */
02932 #define BR_FTM_DEADTIME_DTPS(x) (UNION_READ(hw_ftm_deadtime_t, HW_FTM_DEADTIME_ADDR(x), U, B.DTPS))
02933 
02934 /*! @brief Format value for bitfield FTM_DEADTIME_DTPS. */
02935 #define BF_FTM_DEADTIME_DTPS(v) ((uint32_t)((uint32_t)(v) << BP_FTM_DEADTIME_DTPS) & BM_FTM_DEADTIME_DTPS)
02936 
02937 /*! @brief Set the DTPS field to a new value. */
02938 #define BW_FTM_DEADTIME_DTPS(x, v) (HW_FTM_DEADTIME_WR(x, (HW_FTM_DEADTIME_RD(x) & ~BM_FTM_DEADTIME_DTPS) | BF_FTM_DEADTIME_DTPS(v)))
02939 /*@}*/
02940 
02941 /*******************************************************************************
02942  * HW_FTM_EXTTRIG - FTM External Trigger
02943  ******************************************************************************/
02944 
02945 /*!
02946  * @brief HW_FTM_EXTTRIG - FTM External Trigger (RW)
02947  *
02948  * Reset value: 0x00000000U
02949  *
02950  * This register: Indicates when a channel trigger was generated Enables the
02951  * generation of a trigger when the FTM counter is equal to its initial value
02952  * Selects which channels are used in the generation of the channel triggers Several
02953  * channels can be selected to generate multiple triggers in one PWM period.
02954  * Channels 6 and 7 are not used to generate channel triggers.
02955  */
02956 typedef union _hw_ftm_exttrig
02957 {
02958     uint32_t U;
02959     struct _hw_ftm_exttrig_bitfields
02960     {
02961         uint32_t CH2TRIG : 1;          /*!< [0] Channel 2 Trigger Enable */
02962         uint32_t CH3TRIG : 1;          /*!< [1] Channel 3 Trigger Enable */
02963         uint32_t CH4TRIG : 1;          /*!< [2] Channel 4 Trigger Enable */
02964         uint32_t CH5TRIG : 1;          /*!< [3] Channel 5 Trigger Enable */
02965         uint32_t CH0TRIG : 1;          /*!< [4] Channel 0 Trigger Enable */
02966         uint32_t CH1TRIG : 1;          /*!< [5] Channel 1 Trigger Enable */
02967         uint32_t INITTRIGEN : 1;       /*!< [6] Initialization Trigger Enable */
02968         uint32_t TRIGF : 1;            /*!< [7] Channel Trigger Flag */
02969         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
02970     } B;
02971 } hw_ftm_exttrig_t;
02972 
02973 /*!
02974  * @name Constants and macros for entire FTM_EXTTRIG register
02975  */
02976 /*@{*/
02977 #define HW_FTM_EXTTRIG_ADDR(x)   ((x) + 0x6CU)
02978 
02979 #define HW_FTM_EXTTRIG(x)        (*(__IO hw_ftm_exttrig_t *) HW_FTM_EXTTRIG_ADDR(x))
02980 #define HW_FTM_EXTTRIG_RD(x)     (ADDRESS_READ(hw_ftm_exttrig_t, HW_FTM_EXTTRIG_ADDR(x)))
02981 #define HW_FTM_EXTTRIG_WR(x, v)  (ADDRESS_WRITE(hw_ftm_exttrig_t, HW_FTM_EXTTRIG_ADDR(x), v))
02982 #define HW_FTM_EXTTRIG_SET(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) |  (v)))
02983 #define HW_FTM_EXTTRIG_CLR(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) & ~(v)))
02984 #define HW_FTM_EXTTRIG_TOG(x, v) (HW_FTM_EXTTRIG_WR(x, HW_FTM_EXTTRIG_RD(x) ^  (v)))
02985 /*@}*/
02986 
02987 /*
02988  * Constants & macros for individual FTM_EXTTRIG bitfields
02989  */
02990 
02991 /*!
02992  * @name Register FTM_EXTTRIG, field CH2TRIG[0] (RW)
02993  *
02994  * Enables the generation of the channel trigger when the FTM counter is equal
02995  * to the CnV register.
02996  *
02997  * Values:
02998  * - 0 - The generation of the channel trigger is disabled.
02999  * - 1 - The generation of the channel trigger is enabled.
03000  */
03001 /*@{*/
03002 #define BP_FTM_EXTTRIG_CH2TRIG (0U)        /*!< Bit position for FTM_EXTTRIG_CH2TRIG. */
03003 #define BM_FTM_EXTTRIG_CH2TRIG (0x00000001U) /*!< Bit mask for FTM_EXTTRIG_CH2TRIG. */
03004 #define BS_FTM_EXTTRIG_CH2TRIG (1U)        /*!< Bit field size in bits for FTM_EXTTRIG_CH2TRIG. */
03005 
03006 /*! @brief Read current value of the FTM_EXTTRIG_CH2TRIG field. */
03007 #define BR_FTM_EXTTRIG_CH2TRIG(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH2TRIG)))
03008 
03009 /*! @brief Format value for bitfield FTM_EXTTRIG_CH2TRIG. */
03010 #define BF_FTM_EXTTRIG_CH2TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH2TRIG) & BM_FTM_EXTTRIG_CH2TRIG)
03011 
03012 /*! @brief Set the CH2TRIG field to a new value. */
03013 #define BW_FTM_EXTTRIG_CH2TRIG(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH2TRIG), v))
03014 /*@}*/
03015 
03016 /*!
03017  * @name Register FTM_EXTTRIG, field CH3TRIG[1] (RW)
03018  *
03019  * Enables the generation of the channel trigger when the FTM counter is equal
03020  * to the CnV register.
03021  *
03022  * Values:
03023  * - 0 - The generation of the channel trigger is disabled.
03024  * - 1 - The generation of the channel trigger is enabled.
03025  */
03026 /*@{*/
03027 #define BP_FTM_EXTTRIG_CH3TRIG (1U)        /*!< Bit position for FTM_EXTTRIG_CH3TRIG. */
03028 #define BM_FTM_EXTTRIG_CH3TRIG (0x00000002U) /*!< Bit mask for FTM_EXTTRIG_CH3TRIG. */
03029 #define BS_FTM_EXTTRIG_CH3TRIG (1U)        /*!< Bit field size in bits for FTM_EXTTRIG_CH3TRIG. */
03030 
03031 /*! @brief Read current value of the FTM_EXTTRIG_CH3TRIG field. */
03032 #define BR_FTM_EXTTRIG_CH3TRIG(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH3TRIG)))
03033 
03034 /*! @brief Format value for bitfield FTM_EXTTRIG_CH3TRIG. */
03035 #define BF_FTM_EXTTRIG_CH3TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH3TRIG) & BM_FTM_EXTTRIG_CH3TRIG)
03036 
03037 /*! @brief Set the CH3TRIG field to a new value. */
03038 #define BW_FTM_EXTTRIG_CH3TRIG(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH3TRIG), v))
03039 /*@}*/
03040 
03041 /*!
03042  * @name Register FTM_EXTTRIG, field CH4TRIG[2] (RW)
03043  *
03044  * Enables the generation of the channel trigger when the FTM counter is equal
03045  * to the CnV register.
03046  *
03047  * Values:
03048  * - 0 - The generation of the channel trigger is disabled.
03049  * - 1 - The generation of the channel trigger is enabled.
03050  */
03051 /*@{*/
03052 #define BP_FTM_EXTTRIG_CH4TRIG (2U)        /*!< Bit position for FTM_EXTTRIG_CH4TRIG. */
03053 #define BM_FTM_EXTTRIG_CH4TRIG (0x00000004U) /*!< Bit mask for FTM_EXTTRIG_CH4TRIG. */
03054 #define BS_FTM_EXTTRIG_CH4TRIG (1U)        /*!< Bit field size in bits for FTM_EXTTRIG_CH4TRIG. */
03055 
03056 /*! @brief Read current value of the FTM_EXTTRIG_CH4TRIG field. */
03057 #define BR_FTM_EXTTRIG_CH4TRIG(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH4TRIG)))
03058 
03059 /*! @brief Format value for bitfield FTM_EXTTRIG_CH4TRIG. */
03060 #define BF_FTM_EXTTRIG_CH4TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH4TRIG) & BM_FTM_EXTTRIG_CH4TRIG)
03061 
03062 /*! @brief Set the CH4TRIG field to a new value. */
03063 #define BW_FTM_EXTTRIG_CH4TRIG(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH4TRIG), v))
03064 /*@}*/
03065 
03066 /*!
03067  * @name Register FTM_EXTTRIG, field CH5TRIG[3] (RW)
03068  *
03069  * Enables the generation of the channel trigger when the FTM counter is equal
03070  * to the CnV register.
03071  *
03072  * Values:
03073  * - 0 - The generation of the channel trigger is disabled.
03074  * - 1 - The generation of the channel trigger is enabled.
03075  */
03076 /*@{*/
03077 #define BP_FTM_EXTTRIG_CH5TRIG (3U)        /*!< Bit position for FTM_EXTTRIG_CH5TRIG. */
03078 #define BM_FTM_EXTTRIG_CH5TRIG (0x00000008U) /*!< Bit mask for FTM_EXTTRIG_CH5TRIG. */
03079 #define BS_FTM_EXTTRIG_CH5TRIG (1U)        /*!< Bit field size in bits for FTM_EXTTRIG_CH5TRIG. */
03080 
03081 /*! @brief Read current value of the FTM_EXTTRIG_CH5TRIG field. */
03082 #define BR_FTM_EXTTRIG_CH5TRIG(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH5TRIG)))
03083 
03084 /*! @brief Format value for bitfield FTM_EXTTRIG_CH5TRIG. */
03085 #define BF_FTM_EXTTRIG_CH5TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH5TRIG) & BM_FTM_EXTTRIG_CH5TRIG)
03086 
03087 /*! @brief Set the CH5TRIG field to a new value. */
03088 #define BW_FTM_EXTTRIG_CH5TRIG(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH5TRIG), v))
03089 /*@}*/
03090 
03091 /*!
03092  * @name Register FTM_EXTTRIG, field CH0TRIG[4] (RW)
03093  *
03094  * Enables the generation of the channel trigger when the FTM counter is equal
03095  * to the CnV register.
03096  *
03097  * Values:
03098  * - 0 - The generation of the channel trigger is disabled.
03099  * - 1 - The generation of the channel trigger is enabled.
03100  */
03101 /*@{*/
03102 #define BP_FTM_EXTTRIG_CH0TRIG (4U)        /*!< Bit position for FTM_EXTTRIG_CH0TRIG. */
03103 #define BM_FTM_EXTTRIG_CH0TRIG (0x00000010U) /*!< Bit mask for FTM_EXTTRIG_CH0TRIG. */
03104 #define BS_FTM_EXTTRIG_CH0TRIG (1U)        /*!< Bit field size in bits for FTM_EXTTRIG_CH0TRIG. */
03105 
03106 /*! @brief Read current value of the FTM_EXTTRIG_CH0TRIG field. */
03107 #define BR_FTM_EXTTRIG_CH0TRIG(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH0TRIG)))
03108 
03109 /*! @brief Format value for bitfield FTM_EXTTRIG_CH0TRIG. */
03110 #define BF_FTM_EXTTRIG_CH0TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH0TRIG) & BM_FTM_EXTTRIG_CH0TRIG)
03111 
03112 /*! @brief Set the CH0TRIG field to a new value. */
03113 #define BW_FTM_EXTTRIG_CH0TRIG(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH0TRIG), v))
03114 /*@}*/
03115 
03116 /*!
03117  * @name Register FTM_EXTTRIG, field CH1TRIG[5] (RW)
03118  *
03119  * Enables the generation of the channel trigger when the FTM counter is equal
03120  * to the CnV register.
03121  *
03122  * Values:
03123  * - 0 - The generation of the channel trigger is disabled.
03124  * - 1 - The generation of the channel trigger is enabled.
03125  */
03126 /*@{*/
03127 #define BP_FTM_EXTTRIG_CH1TRIG (5U)        /*!< Bit position for FTM_EXTTRIG_CH1TRIG. */
03128 #define BM_FTM_EXTTRIG_CH1TRIG (0x00000020U) /*!< Bit mask for FTM_EXTTRIG_CH1TRIG. */
03129 #define BS_FTM_EXTTRIG_CH1TRIG (1U)        /*!< Bit field size in bits for FTM_EXTTRIG_CH1TRIG. */
03130 
03131 /*! @brief Read current value of the FTM_EXTTRIG_CH1TRIG field. */
03132 #define BR_FTM_EXTTRIG_CH1TRIG(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH1TRIG)))
03133 
03134 /*! @brief Format value for bitfield FTM_EXTTRIG_CH1TRIG. */
03135 #define BF_FTM_EXTTRIG_CH1TRIG(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_CH1TRIG) & BM_FTM_EXTTRIG_CH1TRIG)
03136 
03137 /*! @brief Set the CH1TRIG field to a new value. */
03138 #define BW_FTM_EXTTRIG_CH1TRIG(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_CH1TRIG), v))
03139 /*@}*/
03140 
03141 /*!
03142  * @name Register FTM_EXTTRIG, field INITTRIGEN[6] (RW)
03143  *
03144  * Enables the generation of the trigger when the FTM counter is equal to the
03145  * CNTIN register.
03146  *
03147  * Values:
03148  * - 0 - The generation of initialization trigger is disabled.
03149  * - 1 - The generation of initialization trigger is enabled.
03150  */
03151 /*@{*/
03152 #define BP_FTM_EXTTRIG_INITTRIGEN (6U)     /*!< Bit position for FTM_EXTTRIG_INITTRIGEN. */
03153 #define BM_FTM_EXTTRIG_INITTRIGEN (0x00000040U) /*!< Bit mask for FTM_EXTTRIG_INITTRIGEN. */
03154 #define BS_FTM_EXTTRIG_INITTRIGEN (1U)     /*!< Bit field size in bits for FTM_EXTTRIG_INITTRIGEN. */
03155 
03156 /*! @brief Read current value of the FTM_EXTTRIG_INITTRIGEN field. */
03157 #define BR_FTM_EXTTRIG_INITTRIGEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_INITTRIGEN)))
03158 
03159 /*! @brief Format value for bitfield FTM_EXTTRIG_INITTRIGEN. */
03160 #define BF_FTM_EXTTRIG_INITTRIGEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_INITTRIGEN) & BM_FTM_EXTTRIG_INITTRIGEN)
03161 
03162 /*! @brief Set the INITTRIGEN field to a new value. */
03163 #define BW_FTM_EXTTRIG_INITTRIGEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_INITTRIGEN), v))
03164 /*@}*/
03165 
03166 /*!
03167  * @name Register FTM_EXTTRIG, field TRIGF[7] (ROWZ)
03168  *
03169  * Set by hardware when a channel trigger is generated. Clear TRIGF by reading
03170  * EXTTRIG while TRIGF is set and then writing a 0 to TRIGF. Writing a 1 to TRIGF
03171  * has no effect. If another channel trigger is generated before the clearing
03172  * sequence is completed, the sequence is reset so TRIGF remains set after the clear
03173  * sequence is completed for the earlier TRIGF.
03174  *
03175  * Values:
03176  * - 0 - No channel trigger was generated.
03177  * - 1 - A channel trigger was generated.
03178  */
03179 /*@{*/
03180 #define BP_FTM_EXTTRIG_TRIGF (7U)          /*!< Bit position for FTM_EXTTRIG_TRIGF. */
03181 #define BM_FTM_EXTTRIG_TRIGF (0x00000080U) /*!< Bit mask for FTM_EXTTRIG_TRIGF. */
03182 #define BS_FTM_EXTTRIG_TRIGF (1U)          /*!< Bit field size in bits for FTM_EXTTRIG_TRIGF. */
03183 
03184 /*! @brief Read current value of the FTM_EXTTRIG_TRIGF field. */
03185 #define BR_FTM_EXTTRIG_TRIGF(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_TRIGF)))
03186 
03187 /*! @brief Format value for bitfield FTM_EXTTRIG_TRIGF. */
03188 #define BF_FTM_EXTTRIG_TRIGF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_EXTTRIG_TRIGF) & BM_FTM_EXTTRIG_TRIGF)
03189 
03190 /*! @brief Set the TRIGF field to a new value. */
03191 #define BW_FTM_EXTTRIG_TRIGF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_EXTTRIG_ADDR(x), BP_FTM_EXTTRIG_TRIGF), v))
03192 /*@}*/
03193 
03194 /*******************************************************************************
03195  * HW_FTM_POL - Channels Polarity
03196  ******************************************************************************/
03197 
03198 /*!
03199  * @brief HW_FTM_POL - Channels Polarity (RW)
03200  *
03201  * Reset value: 0x00000000U
03202  *
03203  * This register defines the output polarity of the FTM channels. The safe value
03204  * that is driven in a channel output when the fault control is enabled and a
03205  * fault condition is detected is the inactive state of the channel. That is, the
03206  * safe value of a channel is the value of its POL bit.
03207  */
03208 typedef union _hw_ftm_pol
03209 {
03210     uint32_t U;
03211     struct _hw_ftm_pol_bitfields
03212     {
03213         uint32_t POL0 : 1;             /*!< [0] Channel 0 Polarity */
03214         uint32_t POL1 : 1;             /*!< [1] Channel 1 Polarity */
03215         uint32_t POL2 : 1;             /*!< [2] Channel 2 Polarity */
03216         uint32_t POL3 : 1;             /*!< [3] Channel 3 Polarity */
03217         uint32_t POL4 : 1;             /*!< [4] Channel 4 Polarity */
03218         uint32_t POL5 : 1;             /*!< [5] Channel 5 Polarity */
03219         uint32_t POL6 : 1;             /*!< [6] Channel 6 Polarity */
03220         uint32_t POL7 : 1;             /*!< [7] Channel 7 Polarity */
03221         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
03222     } B;
03223 } hw_ftm_pol_t;
03224 
03225 /*!
03226  * @name Constants and macros for entire FTM_POL register
03227  */
03228 /*@{*/
03229 #define HW_FTM_POL_ADDR(x)       ((x) + 0x70U)
03230 
03231 #define HW_FTM_POL(x)            (*(__IO hw_ftm_pol_t *) HW_FTM_POL_ADDR(x))
03232 #define HW_FTM_POL_RD(x)         (ADDRESS_READ(hw_ftm_pol_t, HW_FTM_POL_ADDR(x)))
03233 #define HW_FTM_POL_WR(x, v)      (ADDRESS_WRITE(hw_ftm_pol_t, HW_FTM_POL_ADDR(x), v))
03234 #define HW_FTM_POL_SET(x, v)     (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) |  (v)))
03235 #define HW_FTM_POL_CLR(x, v)     (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) & ~(v)))
03236 #define HW_FTM_POL_TOG(x, v)     (HW_FTM_POL_WR(x, HW_FTM_POL_RD(x) ^  (v)))
03237 /*@}*/
03238 
03239 /*
03240  * Constants & macros for individual FTM_POL bitfields
03241  */
03242 
03243 /*!
03244  * @name Register FTM_POL, field POL0[0] (RW)
03245  *
03246  * Defines the polarity of the channel output. This field is write protected. It
03247  * can be written only when MODE[WPDIS] = 1.
03248  *
03249  * Values:
03250  * - 0 - The channel polarity is active high.
03251  * - 1 - The channel polarity is active low.
03252  */
03253 /*@{*/
03254 #define BP_FTM_POL_POL0      (0U)          /*!< Bit position for FTM_POL_POL0. */
03255 #define BM_FTM_POL_POL0      (0x00000001U) /*!< Bit mask for FTM_POL_POL0. */
03256 #define BS_FTM_POL_POL0      (1U)          /*!< Bit field size in bits for FTM_POL_POL0. */
03257 
03258 /*! @brief Read current value of the FTM_POL_POL0 field. */
03259 #define BR_FTM_POL_POL0(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL0)))
03260 
03261 /*! @brief Format value for bitfield FTM_POL_POL0. */
03262 #define BF_FTM_POL_POL0(v)   ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL0) & BM_FTM_POL_POL0)
03263 
03264 /*! @brief Set the POL0 field to a new value. */
03265 #define BW_FTM_POL_POL0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL0), v))
03266 /*@}*/
03267 
03268 /*!
03269  * @name Register FTM_POL, field POL1[1] (RW)
03270  *
03271  * Defines the polarity of the channel output. This field is write protected. It
03272  * can be written only when MODE[WPDIS] = 1.
03273  *
03274  * Values:
03275  * - 0 - The channel polarity is active high.
03276  * - 1 - The channel polarity is active low.
03277  */
03278 /*@{*/
03279 #define BP_FTM_POL_POL1      (1U)          /*!< Bit position for FTM_POL_POL1. */
03280 #define BM_FTM_POL_POL1      (0x00000002U) /*!< Bit mask for FTM_POL_POL1. */
03281 #define BS_FTM_POL_POL1      (1U)          /*!< Bit field size in bits for FTM_POL_POL1. */
03282 
03283 /*! @brief Read current value of the FTM_POL_POL1 field. */
03284 #define BR_FTM_POL_POL1(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL1)))
03285 
03286 /*! @brief Format value for bitfield FTM_POL_POL1. */
03287 #define BF_FTM_POL_POL1(v)   ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL1) & BM_FTM_POL_POL1)
03288 
03289 /*! @brief Set the POL1 field to a new value. */
03290 #define BW_FTM_POL_POL1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL1), v))
03291 /*@}*/
03292 
03293 /*!
03294  * @name Register FTM_POL, field POL2[2] (RW)
03295  *
03296  * Defines the polarity of the channel output. This field is write protected. It
03297  * can be written only when MODE[WPDIS] = 1.
03298  *
03299  * Values:
03300  * - 0 - The channel polarity is active high.
03301  * - 1 - The channel polarity is active low.
03302  */
03303 /*@{*/
03304 #define BP_FTM_POL_POL2      (2U)          /*!< Bit position for FTM_POL_POL2. */
03305 #define BM_FTM_POL_POL2      (0x00000004U) /*!< Bit mask for FTM_POL_POL2. */
03306 #define BS_FTM_POL_POL2      (1U)          /*!< Bit field size in bits for FTM_POL_POL2. */
03307 
03308 /*! @brief Read current value of the FTM_POL_POL2 field. */
03309 #define BR_FTM_POL_POL2(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL2)))
03310 
03311 /*! @brief Format value for bitfield FTM_POL_POL2. */
03312 #define BF_FTM_POL_POL2(v)   ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL2) & BM_FTM_POL_POL2)
03313 
03314 /*! @brief Set the POL2 field to a new value. */
03315 #define BW_FTM_POL_POL2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL2), v))
03316 /*@}*/
03317 
03318 /*!
03319  * @name Register FTM_POL, field POL3[3] (RW)
03320  *
03321  * Defines the polarity of the channel output. This field is write protected. It
03322  * can be written only when MODE[WPDIS] = 1.
03323  *
03324  * Values:
03325  * - 0 - The channel polarity is active high.
03326  * - 1 - The channel polarity is active low.
03327  */
03328 /*@{*/
03329 #define BP_FTM_POL_POL3      (3U)          /*!< Bit position for FTM_POL_POL3. */
03330 #define BM_FTM_POL_POL3      (0x00000008U) /*!< Bit mask for FTM_POL_POL3. */
03331 #define BS_FTM_POL_POL3      (1U)          /*!< Bit field size in bits for FTM_POL_POL3. */
03332 
03333 /*! @brief Read current value of the FTM_POL_POL3 field. */
03334 #define BR_FTM_POL_POL3(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL3)))
03335 
03336 /*! @brief Format value for bitfield FTM_POL_POL3. */
03337 #define BF_FTM_POL_POL3(v)   ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL3) & BM_FTM_POL_POL3)
03338 
03339 /*! @brief Set the POL3 field to a new value. */
03340 #define BW_FTM_POL_POL3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL3), v))
03341 /*@}*/
03342 
03343 /*!
03344  * @name Register FTM_POL, field POL4[4] (RW)
03345  *
03346  * Defines the polarity of the channel output. This field is write protected. It
03347  * can be written only when MODE[WPDIS] = 1.
03348  *
03349  * Values:
03350  * - 0 - The channel polarity is active high.
03351  * - 1 - The channel polarity is active low.
03352  */
03353 /*@{*/
03354 #define BP_FTM_POL_POL4      (4U)          /*!< Bit position for FTM_POL_POL4. */
03355 #define BM_FTM_POL_POL4      (0x00000010U) /*!< Bit mask for FTM_POL_POL4. */
03356 #define BS_FTM_POL_POL4      (1U)          /*!< Bit field size in bits for FTM_POL_POL4. */
03357 
03358 /*! @brief Read current value of the FTM_POL_POL4 field. */
03359 #define BR_FTM_POL_POL4(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL4)))
03360 
03361 /*! @brief Format value for bitfield FTM_POL_POL4. */
03362 #define BF_FTM_POL_POL4(v)   ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL4) & BM_FTM_POL_POL4)
03363 
03364 /*! @brief Set the POL4 field to a new value. */
03365 #define BW_FTM_POL_POL4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL4), v))
03366 /*@}*/
03367 
03368 /*!
03369  * @name Register FTM_POL, field POL5[5] (RW)
03370  *
03371  * Defines the polarity of the channel output. This field is write protected. It
03372  * can be written only when MODE[WPDIS] = 1.
03373  *
03374  * Values:
03375  * - 0 - The channel polarity is active high.
03376  * - 1 - The channel polarity is active low.
03377  */
03378 /*@{*/
03379 #define BP_FTM_POL_POL5      (5U)          /*!< Bit position for FTM_POL_POL5. */
03380 #define BM_FTM_POL_POL5      (0x00000020U) /*!< Bit mask for FTM_POL_POL5. */
03381 #define BS_FTM_POL_POL5      (1U)          /*!< Bit field size in bits for FTM_POL_POL5. */
03382 
03383 /*! @brief Read current value of the FTM_POL_POL5 field. */
03384 #define BR_FTM_POL_POL5(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL5)))
03385 
03386 /*! @brief Format value for bitfield FTM_POL_POL5. */
03387 #define BF_FTM_POL_POL5(v)   ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL5) & BM_FTM_POL_POL5)
03388 
03389 /*! @brief Set the POL5 field to a new value. */
03390 #define BW_FTM_POL_POL5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL5), v))
03391 /*@}*/
03392 
03393 /*!
03394  * @name Register FTM_POL, field POL6[6] (RW)
03395  *
03396  * Defines the polarity of the channel output. This field is write protected. It
03397  * can be written only when MODE[WPDIS] = 1.
03398  *
03399  * Values:
03400  * - 0 - The channel polarity is active high.
03401  * - 1 - The channel polarity is active low.
03402  */
03403 /*@{*/
03404 #define BP_FTM_POL_POL6      (6U)          /*!< Bit position for FTM_POL_POL6. */
03405 #define BM_FTM_POL_POL6      (0x00000040U) /*!< Bit mask for FTM_POL_POL6. */
03406 #define BS_FTM_POL_POL6      (1U)          /*!< Bit field size in bits for FTM_POL_POL6. */
03407 
03408 /*! @brief Read current value of the FTM_POL_POL6 field. */
03409 #define BR_FTM_POL_POL6(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL6)))
03410 
03411 /*! @brief Format value for bitfield FTM_POL_POL6. */
03412 #define BF_FTM_POL_POL6(v)   ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL6) & BM_FTM_POL_POL6)
03413 
03414 /*! @brief Set the POL6 field to a new value. */
03415 #define BW_FTM_POL_POL6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL6), v))
03416 /*@}*/
03417 
03418 /*!
03419  * @name Register FTM_POL, field POL7[7] (RW)
03420  *
03421  * Defines the polarity of the channel output. This field is write protected. It
03422  * can be written only when MODE[WPDIS] = 1.
03423  *
03424  * Values:
03425  * - 0 - The channel polarity is active high.
03426  * - 1 - The channel polarity is active low.
03427  */
03428 /*@{*/
03429 #define BP_FTM_POL_POL7      (7U)          /*!< Bit position for FTM_POL_POL7. */
03430 #define BM_FTM_POL_POL7      (0x00000080U) /*!< Bit mask for FTM_POL_POL7. */
03431 #define BS_FTM_POL_POL7      (1U)          /*!< Bit field size in bits for FTM_POL_POL7. */
03432 
03433 /*! @brief Read current value of the FTM_POL_POL7 field. */
03434 #define BR_FTM_POL_POL7(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL7)))
03435 
03436 /*! @brief Format value for bitfield FTM_POL_POL7. */
03437 #define BF_FTM_POL_POL7(v)   ((uint32_t)((uint32_t)(v) << BP_FTM_POL_POL7) & BM_FTM_POL_POL7)
03438 
03439 /*! @brief Set the POL7 field to a new value. */
03440 #define BW_FTM_POL_POL7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_POL_ADDR(x), BP_FTM_POL_POL7), v))
03441 /*@}*/
03442 
03443 /*******************************************************************************
03444  * HW_FTM_FMS - Fault Mode Status
03445  ******************************************************************************/
03446 
03447 /*!
03448  * @brief HW_FTM_FMS - Fault Mode Status (RW)
03449  *
03450  * Reset value: 0x00000000U
03451  *
03452  * This register contains the fault detection flags, write protection enable
03453  * bit, and the logic OR of the enabled fault inputs.
03454  */
03455 typedef union _hw_ftm_fms
03456 {
03457     uint32_t U;
03458     struct _hw_ftm_fms_bitfields
03459     {
03460         uint32_t FAULTF0 : 1;          /*!< [0] Fault Detection Flag 0 */
03461         uint32_t FAULTF1 : 1;          /*!< [1] Fault Detection Flag 1 */
03462         uint32_t FAULTF2 : 1;          /*!< [2] Fault Detection Flag 2 */
03463         uint32_t FAULTF3 : 1;          /*!< [3] Fault Detection Flag 3 */
03464         uint32_t RESERVED0 : 1;        /*!< [4]  */
03465         uint32_t FAULTIN : 1;          /*!< [5] Fault Inputs */
03466         uint32_t WPEN : 1;             /*!< [6] Write Protection Enable */
03467         uint32_t FAULTF : 1;           /*!< [7] Fault Detection Flag */
03468         uint32_t RESERVED1 : 24;       /*!< [31:8]  */
03469     } B;
03470 } hw_ftm_fms_t;
03471 
03472 /*!
03473  * @name Constants and macros for entire FTM_FMS register
03474  */
03475 /*@{*/
03476 #define HW_FTM_FMS_ADDR(x)       ((x) + 0x74U)
03477 
03478 #define HW_FTM_FMS(x)            (*(__IO hw_ftm_fms_t *) HW_FTM_FMS_ADDR(x))
03479 #define HW_FTM_FMS_RD(x)         (ADDRESS_READ(hw_ftm_fms_t, HW_FTM_FMS_ADDR(x)))
03480 #define HW_FTM_FMS_WR(x, v)      (ADDRESS_WRITE(hw_ftm_fms_t, HW_FTM_FMS_ADDR(x), v))
03481 #define HW_FTM_FMS_SET(x, v)     (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) |  (v)))
03482 #define HW_FTM_FMS_CLR(x, v)     (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) & ~(v)))
03483 #define HW_FTM_FMS_TOG(x, v)     (HW_FTM_FMS_WR(x, HW_FTM_FMS_RD(x) ^  (v)))
03484 /*@}*/
03485 
03486 /*
03487  * Constants & macros for individual FTM_FMS bitfields
03488  */
03489 
03490 /*!
03491  * @name Register FTM_FMS, field FAULTF0[0] (ROWZ)
03492  *
03493  * Set by hardware when fault control is enabled, the corresponding fault input
03494  * is enabled and a fault condition is detected at the fault input. Clear FAULTF0
03495  * by reading the FMS register while FAULTF0 is set and then writing a 0 to
03496  * FAULTF0 while there is no existing fault condition at the corresponding fault
03497  * input. Writing a 1 to FAULTF0 has no effect. FAULTF0 bit is also cleared when
03498  * FAULTF bit is cleared. If another fault condition is detected at the corresponding
03499  * fault input before the clearing sequence is completed, the sequence is reset
03500  * so FAULTF0 remains set after the clearing sequence is completed for the
03501  * earlier fault condition.
03502  *
03503  * Values:
03504  * - 0 - No fault condition was detected at the fault input.
03505  * - 1 - A fault condition was detected at the fault input.
03506  */
03507 /*@{*/
03508 #define BP_FTM_FMS_FAULTF0   (0U)          /*!< Bit position for FTM_FMS_FAULTF0. */
03509 #define BM_FTM_FMS_FAULTF0   (0x00000001U) /*!< Bit mask for FTM_FMS_FAULTF0. */
03510 #define BS_FTM_FMS_FAULTF0   (1U)          /*!< Bit field size in bits for FTM_FMS_FAULTF0. */
03511 
03512 /*! @brief Read current value of the FTM_FMS_FAULTF0 field. */
03513 #define BR_FTM_FMS_FAULTF0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF0)))
03514 
03515 /*! @brief Format value for bitfield FTM_FMS_FAULTF0. */
03516 #define BF_FTM_FMS_FAULTF0(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF0) & BM_FTM_FMS_FAULTF0)
03517 
03518 /*! @brief Set the FAULTF0 field to a new value. */
03519 #define BW_FTM_FMS_FAULTF0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF0), v))
03520 /*@}*/
03521 
03522 /*!
03523  * @name Register FTM_FMS, field FAULTF1[1] (ROWZ)
03524  *
03525  * Set by hardware when fault control is enabled, the corresponding fault input
03526  * is enabled and a fault condition is detected at the fault input. Clear FAULTF1
03527  * by reading the FMS register while FAULTF1 is set and then writing a 0 to
03528  * FAULTF1 while there is no existing fault condition at the corresponding fault
03529  * input. Writing a 1 to FAULTF1 has no effect. FAULTF1 bit is also cleared when
03530  * FAULTF bit is cleared. If another fault condition is detected at the corresponding
03531  * fault input before the clearing sequence is completed, the sequence is reset
03532  * so FAULTF1 remains set after the clearing sequence is completed for the
03533  * earlier fault condition.
03534  *
03535  * Values:
03536  * - 0 - No fault condition was detected at the fault input.
03537  * - 1 - A fault condition was detected at the fault input.
03538  */
03539 /*@{*/
03540 #define BP_FTM_FMS_FAULTF1   (1U)          /*!< Bit position for FTM_FMS_FAULTF1. */
03541 #define BM_FTM_FMS_FAULTF1   (0x00000002U) /*!< Bit mask for FTM_FMS_FAULTF1. */
03542 #define BS_FTM_FMS_FAULTF1   (1U)          /*!< Bit field size in bits for FTM_FMS_FAULTF1. */
03543 
03544 /*! @brief Read current value of the FTM_FMS_FAULTF1 field. */
03545 #define BR_FTM_FMS_FAULTF1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF1)))
03546 
03547 /*! @brief Format value for bitfield FTM_FMS_FAULTF1. */
03548 #define BF_FTM_FMS_FAULTF1(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF1) & BM_FTM_FMS_FAULTF1)
03549 
03550 /*! @brief Set the FAULTF1 field to a new value. */
03551 #define BW_FTM_FMS_FAULTF1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF1), v))
03552 /*@}*/
03553 
03554 /*!
03555  * @name Register FTM_FMS, field FAULTF2[2] (ROWZ)
03556  *
03557  * Set by hardware when fault control is enabled, the corresponding fault input
03558  * is enabled and a fault condition is detected at the fault input. Clear FAULTF2
03559  * by reading the FMS register while FAULTF2 is set and then writing a 0 to
03560  * FAULTF2 while there is no existing fault condition at the corresponding fault
03561  * input. Writing a 1 to FAULTF2 has no effect. FAULTF2 bit is also cleared when
03562  * FAULTF bit is cleared. If another fault condition is detected at the corresponding
03563  * fault input before the clearing sequence is completed, the sequence is reset
03564  * so FAULTF2 remains set after the clearing sequence is completed for the
03565  * earlier fault condition.
03566  *
03567  * Values:
03568  * - 0 - No fault condition was detected at the fault input.
03569  * - 1 - A fault condition was detected at the fault input.
03570  */
03571 /*@{*/
03572 #define BP_FTM_FMS_FAULTF2   (2U)          /*!< Bit position for FTM_FMS_FAULTF2. */
03573 #define BM_FTM_FMS_FAULTF2   (0x00000004U) /*!< Bit mask for FTM_FMS_FAULTF2. */
03574 #define BS_FTM_FMS_FAULTF2   (1U)          /*!< Bit field size in bits for FTM_FMS_FAULTF2. */
03575 
03576 /*! @brief Read current value of the FTM_FMS_FAULTF2 field. */
03577 #define BR_FTM_FMS_FAULTF2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF2)))
03578 
03579 /*! @brief Format value for bitfield FTM_FMS_FAULTF2. */
03580 #define BF_FTM_FMS_FAULTF2(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF2) & BM_FTM_FMS_FAULTF2)
03581 
03582 /*! @brief Set the FAULTF2 field to a new value. */
03583 #define BW_FTM_FMS_FAULTF2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF2), v))
03584 /*@}*/
03585 
03586 /*!
03587  * @name Register FTM_FMS, field FAULTF3[3] (ROWZ)
03588  *
03589  * Set by hardware when fault control is enabled, the corresponding fault input
03590  * is enabled and a fault condition is detected at the fault input. Clear FAULTF3
03591  * by reading the FMS register while FAULTF3 is set and then writing a 0 to
03592  * FAULTF3 while there is no existing fault condition at the corresponding fault
03593  * input. Writing a 1 to FAULTF3 has no effect. FAULTF3 bit is also cleared when
03594  * FAULTF bit is cleared. If another fault condition is detected at the corresponding
03595  * fault input before the clearing sequence is completed, the sequence is reset
03596  * so FAULTF3 remains set after the clearing sequence is completed for the
03597  * earlier fault condition.
03598  *
03599  * Values:
03600  * - 0 - No fault condition was detected at the fault input.
03601  * - 1 - A fault condition was detected at the fault input.
03602  */
03603 /*@{*/
03604 #define BP_FTM_FMS_FAULTF3   (3U)          /*!< Bit position for FTM_FMS_FAULTF3. */
03605 #define BM_FTM_FMS_FAULTF3   (0x00000008U) /*!< Bit mask for FTM_FMS_FAULTF3. */
03606 #define BS_FTM_FMS_FAULTF3   (1U)          /*!< Bit field size in bits for FTM_FMS_FAULTF3. */
03607 
03608 /*! @brief Read current value of the FTM_FMS_FAULTF3 field. */
03609 #define BR_FTM_FMS_FAULTF3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF3)))
03610 
03611 /*! @brief Format value for bitfield FTM_FMS_FAULTF3. */
03612 #define BF_FTM_FMS_FAULTF3(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF3) & BM_FTM_FMS_FAULTF3)
03613 
03614 /*! @brief Set the FAULTF3 field to a new value. */
03615 #define BW_FTM_FMS_FAULTF3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF3), v))
03616 /*@}*/
03617 
03618 /*!
03619  * @name Register FTM_FMS, field FAULTIN[5] (RO)
03620  *
03621  * Represents the logic OR of the enabled fault inputs after their filter (if
03622  * their filter is enabled) when fault control is enabled.
03623  *
03624  * Values:
03625  * - 0 - The logic OR of the enabled fault inputs is 0.
03626  * - 1 - The logic OR of the enabled fault inputs is 1.
03627  */
03628 /*@{*/
03629 #define BP_FTM_FMS_FAULTIN   (5U)          /*!< Bit position for FTM_FMS_FAULTIN. */
03630 #define BM_FTM_FMS_FAULTIN   (0x00000020U) /*!< Bit mask for FTM_FMS_FAULTIN. */
03631 #define BS_FTM_FMS_FAULTIN   (1U)          /*!< Bit field size in bits for FTM_FMS_FAULTIN. */
03632 
03633 /*! @brief Read current value of the FTM_FMS_FAULTIN field. */
03634 #define BR_FTM_FMS_FAULTIN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTIN)))
03635 /*@}*/
03636 
03637 /*!
03638  * @name Register FTM_FMS, field WPEN[6] (RW)
03639  *
03640  * The WPEN bit is the negation of the WPDIS bit. WPEN is set when 1 is written
03641  * to it. WPEN is cleared when WPEN bit is read as a 1 and then 1 is written to
03642  * WPDIS. Writing 0 to WPEN has no effect.
03643  *
03644  * Values:
03645  * - 0 - Write protection is disabled. Write protected bits can be written.
03646  * - 1 - Write protection is enabled. Write protected bits cannot be written.
03647  */
03648 /*@{*/
03649 #define BP_FTM_FMS_WPEN      (6U)          /*!< Bit position for FTM_FMS_WPEN. */
03650 #define BM_FTM_FMS_WPEN      (0x00000040U) /*!< Bit mask for FTM_FMS_WPEN. */
03651 #define BS_FTM_FMS_WPEN      (1U)          /*!< Bit field size in bits for FTM_FMS_WPEN. */
03652 
03653 /*! @brief Read current value of the FTM_FMS_WPEN field. */
03654 #define BR_FTM_FMS_WPEN(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_WPEN)))
03655 
03656 /*! @brief Format value for bitfield FTM_FMS_WPEN. */
03657 #define BF_FTM_FMS_WPEN(v)   ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_WPEN) & BM_FTM_FMS_WPEN)
03658 
03659 /*! @brief Set the WPEN field to a new value. */
03660 #define BW_FTM_FMS_WPEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_WPEN), v))
03661 /*@}*/
03662 
03663 /*!
03664  * @name Register FTM_FMS, field FAULTF[7] (ROWZ)
03665  *
03666  * Represents the logic OR of the individual FAULTFj bits where j = 3, 2, 1, 0.
03667  * Clear FAULTF by reading the FMS register while FAULTF is set and then writing
03668  * a 0 to FAULTF while there is no existing fault condition at the enabled fault
03669  * inputs. Writing a 1 to FAULTF has no effect. If another fault condition is
03670  * detected in an enabled fault input before the clearing sequence is completed, the
03671  * sequence is reset so FAULTF remains set after the clearing sequence is
03672  * completed for the earlier fault condition. FAULTF is also cleared when FAULTFj bits
03673  * are cleared individually.
03674  *
03675  * Values:
03676  * - 0 - No fault condition was detected.
03677  * - 1 - A fault condition was detected.
03678  */
03679 /*@{*/
03680 #define BP_FTM_FMS_FAULTF    (7U)          /*!< Bit position for FTM_FMS_FAULTF. */
03681 #define BM_FTM_FMS_FAULTF    (0x00000080U) /*!< Bit mask for FTM_FMS_FAULTF. */
03682 #define BS_FTM_FMS_FAULTF    (1U)          /*!< Bit field size in bits for FTM_FMS_FAULTF. */
03683 
03684 /*! @brief Read current value of the FTM_FMS_FAULTF field. */
03685 #define BR_FTM_FMS_FAULTF(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF)))
03686 
03687 /*! @brief Format value for bitfield FTM_FMS_FAULTF. */
03688 #define BF_FTM_FMS_FAULTF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FMS_FAULTF) & BM_FTM_FMS_FAULTF)
03689 
03690 /*! @brief Set the FAULTF field to a new value. */
03691 #define BW_FTM_FMS_FAULTF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_FMS_ADDR(x), BP_FTM_FMS_FAULTF), v))
03692 /*@}*/
03693 
03694 /*******************************************************************************
03695  * HW_FTM_FILTER - Input Capture Filter Control
03696  ******************************************************************************/
03697 
03698 /*!
03699  * @brief HW_FTM_FILTER - Input Capture Filter Control (RW)
03700  *
03701  * Reset value: 0x00000000U
03702  *
03703  * This register selects the filter value for the inputs of channels. Channels
03704  * 4, 5, 6 and 7 do not have an input filter. Writing to the FILTER register has
03705  * immediate effect and must be done only when the channels 0, 1, 2, and 3 are not
03706  * in input modes. Failure to do this could result in a missing valid signal.
03707  */
03708 typedef union _hw_ftm_filter
03709 {
03710     uint32_t U;
03711     struct _hw_ftm_filter_bitfields
03712     {
03713         uint32_t CH0FVAL : 4;          /*!< [3:0] Channel 0 Input Filter */
03714         uint32_t CH1FVAL : 4;          /*!< [7:4] Channel 1 Input Filter */
03715         uint32_t CH2FVAL : 4;          /*!< [11:8] Channel 2 Input Filter */
03716         uint32_t CH3FVAL : 4;          /*!< [15:12] Channel 3 Input Filter */
03717         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
03718     } B;
03719 } hw_ftm_filter_t;
03720 
03721 /*!
03722  * @name Constants and macros for entire FTM_FILTER register
03723  */
03724 /*@{*/
03725 #define HW_FTM_FILTER_ADDR(x)    ((x) + 0x78U)
03726 
03727 #define HW_FTM_FILTER(x)         (*(__IO hw_ftm_filter_t *) HW_FTM_FILTER_ADDR(x))
03728 #define HW_FTM_FILTER_RD(x)      (ADDRESS_READ(hw_ftm_filter_t, HW_FTM_FILTER_ADDR(x)))
03729 #define HW_FTM_FILTER_WR(x, v)   (ADDRESS_WRITE(hw_ftm_filter_t, HW_FTM_FILTER_ADDR(x), v))
03730 #define HW_FTM_FILTER_SET(x, v)  (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) |  (v)))
03731 #define HW_FTM_FILTER_CLR(x, v)  (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) & ~(v)))
03732 #define HW_FTM_FILTER_TOG(x, v)  (HW_FTM_FILTER_WR(x, HW_FTM_FILTER_RD(x) ^  (v)))
03733 /*@}*/
03734 
03735 /*
03736  * Constants & macros for individual FTM_FILTER bitfields
03737  */
03738 
03739 /*!
03740  * @name Register FTM_FILTER, field CH0FVAL[3:0] (RW)
03741  *
03742  * Selects the filter value for the channel input. The filter is disabled when
03743  * the value is zero.
03744  */
03745 /*@{*/
03746 #define BP_FTM_FILTER_CH0FVAL (0U)         /*!< Bit position for FTM_FILTER_CH0FVAL. */
03747 #define BM_FTM_FILTER_CH0FVAL (0x0000000FU) /*!< Bit mask for FTM_FILTER_CH0FVAL. */
03748 #define BS_FTM_FILTER_CH0FVAL (4U)         /*!< Bit field size in bits for FTM_FILTER_CH0FVAL. */
03749 
03750 /*! @brief Read current value of the FTM_FILTER_CH0FVAL field. */
03751 #define BR_FTM_FILTER_CH0FVAL(x) (UNION_READ(hw_ftm_filter_t, HW_FTM_FILTER_ADDR(x), U, B.CH0FVAL))
03752 
03753 /*! @brief Format value for bitfield FTM_FILTER_CH0FVAL. */
03754 #define BF_FTM_FILTER_CH0FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH0FVAL) & BM_FTM_FILTER_CH0FVAL)
03755 
03756 /*! @brief Set the CH0FVAL field to a new value. */
03757 #define BW_FTM_FILTER_CH0FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH0FVAL) | BF_FTM_FILTER_CH0FVAL(v)))
03758 /*@}*/
03759 
03760 /*!
03761  * @name Register FTM_FILTER, field CH1FVAL[7:4] (RW)
03762  *
03763  * Selects the filter value for the channel input. The filter is disabled when
03764  * the value is zero.
03765  */
03766 /*@{*/
03767 #define BP_FTM_FILTER_CH1FVAL (4U)         /*!< Bit position for FTM_FILTER_CH1FVAL. */
03768 #define BM_FTM_FILTER_CH1FVAL (0x000000F0U) /*!< Bit mask for FTM_FILTER_CH1FVAL. */
03769 #define BS_FTM_FILTER_CH1FVAL (4U)         /*!< Bit field size in bits for FTM_FILTER_CH1FVAL. */
03770 
03771 /*! @brief Read current value of the FTM_FILTER_CH1FVAL field. */
03772 #define BR_FTM_FILTER_CH1FVAL(x) (UNION_READ(hw_ftm_filter_t, HW_FTM_FILTER_ADDR(x), U, B.CH1FVAL))
03773 
03774 /*! @brief Format value for bitfield FTM_FILTER_CH1FVAL. */
03775 #define BF_FTM_FILTER_CH1FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH1FVAL) & BM_FTM_FILTER_CH1FVAL)
03776 
03777 /*! @brief Set the CH1FVAL field to a new value. */
03778 #define BW_FTM_FILTER_CH1FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH1FVAL) | BF_FTM_FILTER_CH1FVAL(v)))
03779 /*@}*/
03780 
03781 /*!
03782  * @name Register FTM_FILTER, field CH2FVAL[11:8] (RW)
03783  *
03784  * Selects the filter value for the channel input. The filter is disabled when
03785  * the value is zero.
03786  */
03787 /*@{*/
03788 #define BP_FTM_FILTER_CH2FVAL (8U)         /*!< Bit position for FTM_FILTER_CH2FVAL. */
03789 #define BM_FTM_FILTER_CH2FVAL (0x00000F00U) /*!< Bit mask for FTM_FILTER_CH2FVAL. */
03790 #define BS_FTM_FILTER_CH2FVAL (4U)         /*!< Bit field size in bits for FTM_FILTER_CH2FVAL. */
03791 
03792 /*! @brief Read current value of the FTM_FILTER_CH2FVAL field. */
03793 #define BR_FTM_FILTER_CH2FVAL(x) (UNION_READ(hw_ftm_filter_t, HW_FTM_FILTER_ADDR(x), U, B.CH2FVAL))
03794 
03795 /*! @brief Format value for bitfield FTM_FILTER_CH2FVAL. */
03796 #define BF_FTM_FILTER_CH2FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH2FVAL) & BM_FTM_FILTER_CH2FVAL)
03797 
03798 /*! @brief Set the CH2FVAL field to a new value. */
03799 #define BW_FTM_FILTER_CH2FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH2FVAL) | BF_FTM_FILTER_CH2FVAL(v)))
03800 /*@}*/
03801 
03802 /*!
03803  * @name Register FTM_FILTER, field CH3FVAL[15:12] (RW)
03804  *
03805  * Selects the filter value for the channel input. The filter is disabled when
03806  * the value is zero.
03807  */
03808 /*@{*/
03809 #define BP_FTM_FILTER_CH3FVAL (12U)        /*!< Bit position for FTM_FILTER_CH3FVAL. */
03810 #define BM_FTM_FILTER_CH3FVAL (0x0000F000U) /*!< Bit mask for FTM_FILTER_CH3FVAL. */
03811 #define BS_FTM_FILTER_CH3FVAL (4U)         /*!< Bit field size in bits for FTM_FILTER_CH3FVAL. */
03812 
03813 /*! @brief Read current value of the FTM_FILTER_CH3FVAL field. */
03814 #define BR_FTM_FILTER_CH3FVAL(x) (UNION_READ(hw_ftm_filter_t, HW_FTM_FILTER_ADDR(x), U, B.CH3FVAL))
03815 
03816 /*! @brief Format value for bitfield FTM_FILTER_CH3FVAL. */
03817 #define BF_FTM_FILTER_CH3FVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FILTER_CH3FVAL) & BM_FTM_FILTER_CH3FVAL)
03818 
03819 /*! @brief Set the CH3FVAL field to a new value. */
03820 #define BW_FTM_FILTER_CH3FVAL(x, v) (HW_FTM_FILTER_WR(x, (HW_FTM_FILTER_RD(x) & ~BM_FTM_FILTER_CH3FVAL) | BF_FTM_FILTER_CH3FVAL(v)))
03821 /*@}*/
03822 
03823 /*******************************************************************************
03824  * HW_FTM_FLTCTRL - Fault Control
03825  ******************************************************************************/
03826 
03827 /*!
03828  * @brief HW_FTM_FLTCTRL - Fault Control (RW)
03829  *
03830  * Reset value: 0x00000000U
03831  *
03832  * This register selects the filter value for the fault inputs, enables the
03833  * fault inputs and the fault inputs filter.
03834  */
03835 typedef union _hw_ftm_fltctrl
03836 {
03837     uint32_t U;
03838     struct _hw_ftm_fltctrl_bitfields
03839     {
03840         uint32_t FAULT0EN : 1;         /*!< [0] Fault Input 0 Enable */
03841         uint32_t FAULT1EN : 1;         /*!< [1] Fault Input 1 Enable */
03842         uint32_t FAULT2EN : 1;         /*!< [2] Fault Input 2 Enable */
03843         uint32_t FAULT3EN : 1;         /*!< [3] Fault Input 3 Enable */
03844         uint32_t FFLTR0EN : 1;         /*!< [4] Fault Input 0 Filter Enable */
03845         uint32_t FFLTR1EN : 1;         /*!< [5] Fault Input 1 Filter Enable */
03846         uint32_t FFLTR2EN : 1;         /*!< [6] Fault Input 2 Filter Enable */
03847         uint32_t FFLTR3EN : 1;         /*!< [7] Fault Input 3 Filter Enable */
03848         uint32_t FFVAL : 4;            /*!< [11:8] Fault Input Filter */
03849         uint32_t RESERVED0 : 20;       /*!< [31:12]  */
03850     } B;
03851 } hw_ftm_fltctrl_t;
03852 
03853 /*!
03854  * @name Constants and macros for entire FTM_FLTCTRL register
03855  */
03856 /*@{*/
03857 #define HW_FTM_FLTCTRL_ADDR(x)   ((x) + 0x7CU)
03858 
03859 #define HW_FTM_FLTCTRL(x)        (*(__IO hw_ftm_fltctrl_t *) HW_FTM_FLTCTRL_ADDR(x))
03860 #define HW_FTM_FLTCTRL_RD(x)     (ADDRESS_READ(hw_ftm_fltctrl_t, HW_FTM_FLTCTRL_ADDR(x)))
03861 #define HW_FTM_FLTCTRL_WR(x, v)  (ADDRESS_WRITE(hw_ftm_fltctrl_t, HW_FTM_FLTCTRL_ADDR(x), v))
03862 #define HW_FTM_FLTCTRL_SET(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) |  (v)))
03863 #define HW_FTM_FLTCTRL_CLR(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) & ~(v)))
03864 #define HW_FTM_FLTCTRL_TOG(x, v) (HW_FTM_FLTCTRL_WR(x, HW_FTM_FLTCTRL_RD(x) ^  (v)))
03865 /*@}*/
03866 
03867 /*
03868  * Constants & macros for individual FTM_FLTCTRL bitfields
03869  */
03870 
03871 /*!
03872  * @name Register FTM_FLTCTRL, field FAULT0EN[0] (RW)
03873  *
03874  * Enables the fault input. This field is write protected. It can be written
03875  * only when MODE[WPDIS] = 1.
03876  *
03877  * Values:
03878  * - 0 - Fault input is disabled.
03879  * - 1 - Fault input is enabled.
03880  */
03881 /*@{*/
03882 #define BP_FTM_FLTCTRL_FAULT0EN (0U)       /*!< Bit position for FTM_FLTCTRL_FAULT0EN. */
03883 #define BM_FTM_FLTCTRL_FAULT0EN (0x00000001U) /*!< Bit mask for FTM_FLTCTRL_FAULT0EN. */
03884 #define BS_FTM_FLTCTRL_FAULT0EN (1U)       /*!< Bit field size in bits for FTM_FLTCTRL_FAULT0EN. */
03885 
03886 /*! @brief Read current value of the FTM_FLTCTRL_FAULT0EN field. */
03887 #define BR_FTM_FLTCTRL_FAULT0EN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT0EN)))
03888 
03889 /*! @brief Format value for bitfield FTM_FLTCTRL_FAULT0EN. */
03890 #define BF_FTM_FLTCTRL_FAULT0EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT0EN) & BM_FTM_FLTCTRL_FAULT0EN)
03891 
03892 /*! @brief Set the FAULT0EN field to a new value. */
03893 #define BW_FTM_FLTCTRL_FAULT0EN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT0EN), v))
03894 /*@}*/
03895 
03896 /*!
03897  * @name Register FTM_FLTCTRL, field FAULT1EN[1] (RW)
03898  *
03899  * Enables the fault input. This field is write protected. It can be written
03900  * only when MODE[WPDIS] = 1.
03901  *
03902  * Values:
03903  * - 0 - Fault input is disabled.
03904  * - 1 - Fault input is enabled.
03905  */
03906 /*@{*/
03907 #define BP_FTM_FLTCTRL_FAULT1EN (1U)       /*!< Bit position for FTM_FLTCTRL_FAULT1EN. */
03908 #define BM_FTM_FLTCTRL_FAULT1EN (0x00000002U) /*!< Bit mask for FTM_FLTCTRL_FAULT1EN. */
03909 #define BS_FTM_FLTCTRL_FAULT1EN (1U)       /*!< Bit field size in bits for FTM_FLTCTRL_FAULT1EN. */
03910 
03911 /*! @brief Read current value of the FTM_FLTCTRL_FAULT1EN field. */
03912 #define BR_FTM_FLTCTRL_FAULT1EN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT1EN)))
03913 
03914 /*! @brief Format value for bitfield FTM_FLTCTRL_FAULT1EN. */
03915 #define BF_FTM_FLTCTRL_FAULT1EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT1EN) & BM_FTM_FLTCTRL_FAULT1EN)
03916 
03917 /*! @brief Set the FAULT1EN field to a new value. */
03918 #define BW_FTM_FLTCTRL_FAULT1EN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT1EN), v))
03919 /*@}*/
03920 
03921 /*!
03922  * @name Register FTM_FLTCTRL, field FAULT2EN[2] (RW)
03923  *
03924  * Enables the fault input. This field is write protected. It can be written
03925  * only when MODE[WPDIS] = 1.
03926  *
03927  * Values:
03928  * - 0 - Fault input is disabled.
03929  * - 1 - Fault input is enabled.
03930  */
03931 /*@{*/
03932 #define BP_FTM_FLTCTRL_FAULT2EN (2U)       /*!< Bit position for FTM_FLTCTRL_FAULT2EN. */
03933 #define BM_FTM_FLTCTRL_FAULT2EN (0x00000004U) /*!< Bit mask for FTM_FLTCTRL_FAULT2EN. */
03934 #define BS_FTM_FLTCTRL_FAULT2EN (1U)       /*!< Bit field size in bits for FTM_FLTCTRL_FAULT2EN. */
03935 
03936 /*! @brief Read current value of the FTM_FLTCTRL_FAULT2EN field. */
03937 #define BR_FTM_FLTCTRL_FAULT2EN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT2EN)))
03938 
03939 /*! @brief Format value for bitfield FTM_FLTCTRL_FAULT2EN. */
03940 #define BF_FTM_FLTCTRL_FAULT2EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT2EN) & BM_FTM_FLTCTRL_FAULT2EN)
03941 
03942 /*! @brief Set the FAULT2EN field to a new value. */
03943 #define BW_FTM_FLTCTRL_FAULT2EN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT2EN), v))
03944 /*@}*/
03945 
03946 /*!
03947  * @name Register FTM_FLTCTRL, field FAULT3EN[3] (RW)
03948  *
03949  * Enables the fault input. This field is write protected. It can be written
03950  * only when MODE[WPDIS] = 1.
03951  *
03952  * Values:
03953  * - 0 - Fault input is disabled.
03954  * - 1 - Fault input is enabled.
03955  */
03956 /*@{*/
03957 #define BP_FTM_FLTCTRL_FAULT3EN (3U)       /*!< Bit position for FTM_FLTCTRL_FAULT3EN. */
03958 #define BM_FTM_FLTCTRL_FAULT3EN (0x00000008U) /*!< Bit mask for FTM_FLTCTRL_FAULT3EN. */
03959 #define BS_FTM_FLTCTRL_FAULT3EN (1U)       /*!< Bit field size in bits for FTM_FLTCTRL_FAULT3EN. */
03960 
03961 /*! @brief Read current value of the FTM_FLTCTRL_FAULT3EN field. */
03962 #define BR_FTM_FLTCTRL_FAULT3EN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT3EN)))
03963 
03964 /*! @brief Format value for bitfield FTM_FLTCTRL_FAULT3EN. */
03965 #define BF_FTM_FLTCTRL_FAULT3EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FAULT3EN) & BM_FTM_FLTCTRL_FAULT3EN)
03966 
03967 /*! @brief Set the FAULT3EN field to a new value. */
03968 #define BW_FTM_FLTCTRL_FAULT3EN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FAULT3EN), v))
03969 /*@}*/
03970 
03971 /*!
03972  * @name Register FTM_FLTCTRL, field FFLTR0EN[4] (RW)
03973  *
03974  * Enables the filter for the fault input. This field is write protected. It can
03975  * be written only when MODE[WPDIS] = 1.
03976  *
03977  * Values:
03978  * - 0 - Fault input filter is disabled.
03979  * - 1 - Fault input filter is enabled.
03980  */
03981 /*@{*/
03982 #define BP_FTM_FLTCTRL_FFLTR0EN (4U)       /*!< Bit position for FTM_FLTCTRL_FFLTR0EN. */
03983 #define BM_FTM_FLTCTRL_FFLTR0EN (0x00000010U) /*!< Bit mask for FTM_FLTCTRL_FFLTR0EN. */
03984 #define BS_FTM_FLTCTRL_FFLTR0EN (1U)       /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR0EN. */
03985 
03986 /*! @brief Read current value of the FTM_FLTCTRL_FFLTR0EN field. */
03987 #define BR_FTM_FLTCTRL_FFLTR0EN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR0EN)))
03988 
03989 /*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR0EN. */
03990 #define BF_FTM_FLTCTRL_FFLTR0EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR0EN) & BM_FTM_FLTCTRL_FFLTR0EN)
03991 
03992 /*! @brief Set the FFLTR0EN field to a new value. */
03993 #define BW_FTM_FLTCTRL_FFLTR0EN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR0EN), v))
03994 /*@}*/
03995 
03996 /*!
03997  * @name Register FTM_FLTCTRL, field FFLTR1EN[5] (RW)
03998  *
03999  * Enables the filter for the fault input. This field is write protected. It can
04000  * be written only when MODE[WPDIS] = 1.
04001  *
04002  * Values:
04003  * - 0 - Fault input filter is disabled.
04004  * - 1 - Fault input filter is enabled.
04005  */
04006 /*@{*/
04007 #define BP_FTM_FLTCTRL_FFLTR1EN (5U)       /*!< Bit position for FTM_FLTCTRL_FFLTR1EN. */
04008 #define BM_FTM_FLTCTRL_FFLTR1EN (0x00000020U) /*!< Bit mask for FTM_FLTCTRL_FFLTR1EN. */
04009 #define BS_FTM_FLTCTRL_FFLTR1EN (1U)       /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR1EN. */
04010 
04011 /*! @brief Read current value of the FTM_FLTCTRL_FFLTR1EN field. */
04012 #define BR_FTM_FLTCTRL_FFLTR1EN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR1EN)))
04013 
04014 /*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR1EN. */
04015 #define BF_FTM_FLTCTRL_FFLTR1EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR1EN) & BM_FTM_FLTCTRL_FFLTR1EN)
04016 
04017 /*! @brief Set the FFLTR1EN field to a new value. */
04018 #define BW_FTM_FLTCTRL_FFLTR1EN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR1EN), v))
04019 /*@}*/
04020 
04021 /*!
04022  * @name Register FTM_FLTCTRL, field FFLTR2EN[6] (RW)
04023  *
04024  * Enables the filter for the fault input. This field is write protected. It can
04025  * be written only when MODE[WPDIS] = 1.
04026  *
04027  * Values:
04028  * - 0 - Fault input filter is disabled.
04029  * - 1 - Fault input filter is enabled.
04030  */
04031 /*@{*/
04032 #define BP_FTM_FLTCTRL_FFLTR2EN (6U)       /*!< Bit position for FTM_FLTCTRL_FFLTR2EN. */
04033 #define BM_FTM_FLTCTRL_FFLTR2EN (0x00000040U) /*!< Bit mask for FTM_FLTCTRL_FFLTR2EN. */
04034 #define BS_FTM_FLTCTRL_FFLTR2EN (1U)       /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR2EN. */
04035 
04036 /*! @brief Read current value of the FTM_FLTCTRL_FFLTR2EN field. */
04037 #define BR_FTM_FLTCTRL_FFLTR2EN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR2EN)))
04038 
04039 /*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR2EN. */
04040 #define BF_FTM_FLTCTRL_FFLTR2EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR2EN) & BM_FTM_FLTCTRL_FFLTR2EN)
04041 
04042 /*! @brief Set the FFLTR2EN field to a new value. */
04043 #define BW_FTM_FLTCTRL_FFLTR2EN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR2EN), v))
04044 /*@}*/
04045 
04046 /*!
04047  * @name Register FTM_FLTCTRL, field FFLTR3EN[7] (RW)
04048  *
04049  * Enables the filter for the fault input. This field is write protected. It can
04050  * be written only when MODE[WPDIS] = 1.
04051  *
04052  * Values:
04053  * - 0 - Fault input filter is disabled.
04054  * - 1 - Fault input filter is enabled.
04055  */
04056 /*@{*/
04057 #define BP_FTM_FLTCTRL_FFLTR3EN (7U)       /*!< Bit position for FTM_FLTCTRL_FFLTR3EN. */
04058 #define BM_FTM_FLTCTRL_FFLTR3EN (0x00000080U) /*!< Bit mask for FTM_FLTCTRL_FFLTR3EN. */
04059 #define BS_FTM_FLTCTRL_FFLTR3EN (1U)       /*!< Bit field size in bits for FTM_FLTCTRL_FFLTR3EN. */
04060 
04061 /*! @brief Read current value of the FTM_FLTCTRL_FFLTR3EN field. */
04062 #define BR_FTM_FLTCTRL_FFLTR3EN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR3EN)))
04063 
04064 /*! @brief Format value for bitfield FTM_FLTCTRL_FFLTR3EN. */
04065 #define BF_FTM_FLTCTRL_FFLTR3EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFLTR3EN) & BM_FTM_FLTCTRL_FFLTR3EN)
04066 
04067 /*! @brief Set the FFLTR3EN field to a new value. */
04068 #define BW_FTM_FLTCTRL_FFLTR3EN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_FLTCTRL_ADDR(x), BP_FTM_FLTCTRL_FFLTR3EN), v))
04069 /*@}*/
04070 
04071 /*!
04072  * @name Register FTM_FLTCTRL, field FFVAL[11:8] (RW)
04073  *
04074  * Selects the filter value for the fault inputs. The fault filter is disabled
04075  * when the value is zero. Writing to this field has immediate effect and must be
04076  * done only when the fault control or all fault inputs are disabled. Failure to
04077  * do this could result in a missing fault detection.
04078  */
04079 /*@{*/
04080 #define BP_FTM_FLTCTRL_FFVAL (8U)          /*!< Bit position for FTM_FLTCTRL_FFVAL. */
04081 #define BM_FTM_FLTCTRL_FFVAL (0x00000F00U) /*!< Bit mask for FTM_FLTCTRL_FFVAL. */
04082 #define BS_FTM_FLTCTRL_FFVAL (4U)          /*!< Bit field size in bits for FTM_FLTCTRL_FFVAL. */
04083 
04084 /*! @brief Read current value of the FTM_FLTCTRL_FFVAL field. */
04085 #define BR_FTM_FLTCTRL_FFVAL(x) (UNION_READ(hw_ftm_fltctrl_t, HW_FTM_FLTCTRL_ADDR(x), U, B.FFVAL))
04086 
04087 /*! @brief Format value for bitfield FTM_FLTCTRL_FFVAL. */
04088 #define BF_FTM_FLTCTRL_FFVAL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTCTRL_FFVAL) & BM_FTM_FLTCTRL_FFVAL)
04089 
04090 /*! @brief Set the FFVAL field to a new value. */
04091 #define BW_FTM_FLTCTRL_FFVAL(x, v) (HW_FTM_FLTCTRL_WR(x, (HW_FTM_FLTCTRL_RD(x) & ~BM_FTM_FLTCTRL_FFVAL) | BF_FTM_FLTCTRL_FFVAL(v)))
04092 /*@}*/
04093 
04094 /*******************************************************************************
04095  * HW_FTM_QDCTRL - Quadrature Decoder Control And Status
04096  ******************************************************************************/
04097 
04098 /*!
04099  * @brief HW_FTM_QDCTRL - Quadrature Decoder Control And Status (RW)
04100  *
04101  * Reset value: 0x00000000U
04102  *
04103  * This register has the control and status bits for the Quadrature Decoder mode.
04104  */
04105 typedef union _hw_ftm_qdctrl
04106 {
04107     uint32_t U;
04108     struct _hw_ftm_qdctrl_bitfields
04109     {
04110         uint32_t QUADEN : 1;           /*!< [0] Quadrature Decoder Mode Enable */
04111         uint32_t TOFDIR : 1;           /*!< [1] Timer Overflow Direction In Quadrature
04112                                         * Decoder Mode */
04113         uint32_t QUADIR : 1;           /*!< [2] FTM Counter Direction In Quadrature
04114                                         * Decoder Mode */
04115         uint32_t QUADMODE : 1;         /*!< [3] Quadrature Decoder Mode */
04116         uint32_t PHBPOL : 1;           /*!< [4] Phase B Input Polarity */
04117         uint32_t PHAPOL : 1;           /*!< [5] Phase A Input Polarity */
04118         uint32_t PHBFLTREN : 1;        /*!< [6] Phase B Input Filter Enable */
04119         uint32_t PHAFLTREN : 1;        /*!< [7] Phase A Input Filter Enable */
04120         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
04121     } B;
04122 } hw_ftm_qdctrl_t;
04123 
04124 /*!
04125  * @name Constants and macros for entire FTM_QDCTRL register
04126  */
04127 /*@{*/
04128 #define HW_FTM_QDCTRL_ADDR(x)    ((x) + 0x80U)
04129 
04130 #define HW_FTM_QDCTRL(x)         (*(__IO hw_ftm_qdctrl_t *) HW_FTM_QDCTRL_ADDR(x))
04131 #define HW_FTM_QDCTRL_RD(x)      (ADDRESS_READ(hw_ftm_qdctrl_t, HW_FTM_QDCTRL_ADDR(x)))
04132 #define HW_FTM_QDCTRL_WR(x, v)   (ADDRESS_WRITE(hw_ftm_qdctrl_t, HW_FTM_QDCTRL_ADDR(x), v))
04133 #define HW_FTM_QDCTRL_SET(x, v)  (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) |  (v)))
04134 #define HW_FTM_QDCTRL_CLR(x, v)  (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) & ~(v)))
04135 #define HW_FTM_QDCTRL_TOG(x, v)  (HW_FTM_QDCTRL_WR(x, HW_FTM_QDCTRL_RD(x) ^  (v)))
04136 /*@}*/
04137 
04138 /*
04139  * Constants & macros for individual FTM_QDCTRL bitfields
04140  */
04141 
04142 /*!
04143  * @name Register FTM_QDCTRL, field QUADEN[0] (RW)
04144  *
04145  * Enables the Quadrature Decoder mode. In this mode, the phase A and B input
04146  * signals control the FTM counter direction. The Quadrature Decoder mode has
04147  * precedence over the other modes. See #ModeSel1Table. This field is write protected.
04148  * It can be written only when MODE[WPDIS] = 1.
04149  *
04150  * Values:
04151  * - 0 - Quadrature Decoder mode is disabled.
04152  * - 1 - Quadrature Decoder mode is enabled.
04153  */
04154 /*@{*/
04155 #define BP_FTM_QDCTRL_QUADEN (0U)          /*!< Bit position for FTM_QDCTRL_QUADEN. */
04156 #define BM_FTM_QDCTRL_QUADEN (0x00000001U) /*!< Bit mask for FTM_QDCTRL_QUADEN. */
04157 #define BS_FTM_QDCTRL_QUADEN (1U)          /*!< Bit field size in bits for FTM_QDCTRL_QUADEN. */
04158 
04159 /*! @brief Read current value of the FTM_QDCTRL_QUADEN field. */
04160 #define BR_FTM_QDCTRL_QUADEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADEN)))
04161 
04162 /*! @brief Format value for bitfield FTM_QDCTRL_QUADEN. */
04163 #define BF_FTM_QDCTRL_QUADEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_QUADEN) & BM_FTM_QDCTRL_QUADEN)
04164 
04165 /*! @brief Set the QUADEN field to a new value. */
04166 #define BW_FTM_QDCTRL_QUADEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADEN), v))
04167 /*@}*/
04168 
04169 /*!
04170  * @name Register FTM_QDCTRL, field TOFDIR[1] (RO)
04171  *
04172  * Indicates if the TOF bit was set on the top or the bottom of counting.
04173  *
04174  * Values:
04175  * - 0 - TOF bit was set on the bottom of counting. There was an FTM counter
04176  *     decrement and FTM counter changes from its minimum value (CNTIN register) to
04177  *     its maximum value (MOD register).
04178  * - 1 - TOF bit was set on the top of counting. There was an FTM counter
04179  *     increment and FTM counter changes from its maximum value (MOD register) to its
04180  *     minimum value (CNTIN register).
04181  */
04182 /*@{*/
04183 #define BP_FTM_QDCTRL_TOFDIR (1U)          /*!< Bit position for FTM_QDCTRL_TOFDIR. */
04184 #define BM_FTM_QDCTRL_TOFDIR (0x00000002U) /*!< Bit mask for FTM_QDCTRL_TOFDIR. */
04185 #define BS_FTM_QDCTRL_TOFDIR (1U)          /*!< Bit field size in bits for FTM_QDCTRL_TOFDIR. */
04186 
04187 /*! @brief Read current value of the FTM_QDCTRL_TOFDIR field. */
04188 #define BR_FTM_QDCTRL_TOFDIR(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_TOFDIR)))
04189 /*@}*/
04190 
04191 /*!
04192  * @name Register FTM_QDCTRL, field QUADIR[2] (RO)
04193  *
04194  * Indicates the counting direction.
04195  *
04196  * Values:
04197  * - 0 - Counting direction is decreasing (FTM counter decrement).
04198  * - 1 - Counting direction is increasing (FTM counter increment).
04199  */
04200 /*@{*/
04201 #define BP_FTM_QDCTRL_QUADIR (2U)          /*!< Bit position for FTM_QDCTRL_QUADIR. */
04202 #define BM_FTM_QDCTRL_QUADIR (0x00000004U) /*!< Bit mask for FTM_QDCTRL_QUADIR. */
04203 #define BS_FTM_QDCTRL_QUADIR (1U)          /*!< Bit field size in bits for FTM_QDCTRL_QUADIR. */
04204 
04205 /*! @brief Read current value of the FTM_QDCTRL_QUADIR field. */
04206 #define BR_FTM_QDCTRL_QUADIR(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADIR)))
04207 /*@}*/
04208 
04209 /*!
04210  * @name Register FTM_QDCTRL, field QUADMODE[3] (RW)
04211  *
04212  * Selects the encoding mode used in the Quadrature Decoder mode.
04213  *
04214  * Values:
04215  * - 0 - Phase A and phase B encoding mode.
04216  * - 1 - Count and direction encoding mode.
04217  */
04218 /*@{*/
04219 #define BP_FTM_QDCTRL_QUADMODE (3U)        /*!< Bit position for FTM_QDCTRL_QUADMODE. */
04220 #define BM_FTM_QDCTRL_QUADMODE (0x00000008U) /*!< Bit mask for FTM_QDCTRL_QUADMODE. */
04221 #define BS_FTM_QDCTRL_QUADMODE (1U)        /*!< Bit field size in bits for FTM_QDCTRL_QUADMODE. */
04222 
04223 /*! @brief Read current value of the FTM_QDCTRL_QUADMODE field. */
04224 #define BR_FTM_QDCTRL_QUADMODE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADMODE)))
04225 
04226 /*! @brief Format value for bitfield FTM_QDCTRL_QUADMODE. */
04227 #define BF_FTM_QDCTRL_QUADMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_QUADMODE) & BM_FTM_QDCTRL_QUADMODE)
04228 
04229 /*! @brief Set the QUADMODE field to a new value. */
04230 #define BW_FTM_QDCTRL_QUADMODE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_QUADMODE), v))
04231 /*@}*/
04232 
04233 /*!
04234  * @name Register FTM_QDCTRL, field PHBPOL[4] (RW)
04235  *
04236  * Selects the polarity for the quadrature decoder phase B input.
04237  *
04238  * Values:
04239  * - 0 - Normal polarity. Phase B input signal is not inverted before
04240  *     identifying the rising and falling edges of this signal.
04241  * - 1 - Inverted polarity. Phase B input signal is inverted before identifying
04242  *     the rising and falling edges of this signal.
04243  */
04244 /*@{*/
04245 #define BP_FTM_QDCTRL_PHBPOL (4U)          /*!< Bit position for FTM_QDCTRL_PHBPOL. */
04246 #define BM_FTM_QDCTRL_PHBPOL (0x00000010U) /*!< Bit mask for FTM_QDCTRL_PHBPOL. */
04247 #define BS_FTM_QDCTRL_PHBPOL (1U)          /*!< Bit field size in bits for FTM_QDCTRL_PHBPOL. */
04248 
04249 /*! @brief Read current value of the FTM_QDCTRL_PHBPOL field. */
04250 #define BR_FTM_QDCTRL_PHBPOL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBPOL)))
04251 
04252 /*! @brief Format value for bitfield FTM_QDCTRL_PHBPOL. */
04253 #define BF_FTM_QDCTRL_PHBPOL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHBPOL) & BM_FTM_QDCTRL_PHBPOL)
04254 
04255 /*! @brief Set the PHBPOL field to a new value. */
04256 #define BW_FTM_QDCTRL_PHBPOL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBPOL), v))
04257 /*@}*/
04258 
04259 /*!
04260  * @name Register FTM_QDCTRL, field PHAPOL[5] (RW)
04261  *
04262  * Selects the polarity for the quadrature decoder phase A input.
04263  *
04264  * Values:
04265  * - 0 - Normal polarity. Phase A input signal is not inverted before
04266  *     identifying the rising and falling edges of this signal.
04267  * - 1 - Inverted polarity. Phase A input signal is inverted before identifying
04268  *     the rising and falling edges of this signal.
04269  */
04270 /*@{*/
04271 #define BP_FTM_QDCTRL_PHAPOL (5U)          /*!< Bit position for FTM_QDCTRL_PHAPOL. */
04272 #define BM_FTM_QDCTRL_PHAPOL (0x00000020U) /*!< Bit mask for FTM_QDCTRL_PHAPOL. */
04273 #define BS_FTM_QDCTRL_PHAPOL (1U)          /*!< Bit field size in bits for FTM_QDCTRL_PHAPOL. */
04274 
04275 /*! @brief Read current value of the FTM_QDCTRL_PHAPOL field. */
04276 #define BR_FTM_QDCTRL_PHAPOL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAPOL)))
04277 
04278 /*! @brief Format value for bitfield FTM_QDCTRL_PHAPOL. */
04279 #define BF_FTM_QDCTRL_PHAPOL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHAPOL) & BM_FTM_QDCTRL_PHAPOL)
04280 
04281 /*! @brief Set the PHAPOL field to a new value. */
04282 #define BW_FTM_QDCTRL_PHAPOL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAPOL), v))
04283 /*@}*/
04284 
04285 /*!
04286  * @name Register FTM_QDCTRL, field PHBFLTREN[6] (RW)
04287  *
04288  * Enables the filter for the quadrature decoder phase B input. The filter value
04289  * for the phase B input is defined by the CH1FVAL field of FILTER. The phase B
04290  * filter is also disabled when CH1FVAL is zero.
04291  *
04292  * Values:
04293  * - 0 - Phase B input filter is disabled.
04294  * - 1 - Phase B input filter is enabled.
04295  */
04296 /*@{*/
04297 #define BP_FTM_QDCTRL_PHBFLTREN (6U)       /*!< Bit position for FTM_QDCTRL_PHBFLTREN. */
04298 #define BM_FTM_QDCTRL_PHBFLTREN (0x00000040U) /*!< Bit mask for FTM_QDCTRL_PHBFLTREN. */
04299 #define BS_FTM_QDCTRL_PHBFLTREN (1U)       /*!< Bit field size in bits for FTM_QDCTRL_PHBFLTREN. */
04300 
04301 /*! @brief Read current value of the FTM_QDCTRL_PHBFLTREN field. */
04302 #define BR_FTM_QDCTRL_PHBFLTREN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBFLTREN)))
04303 
04304 /*! @brief Format value for bitfield FTM_QDCTRL_PHBFLTREN. */
04305 #define BF_FTM_QDCTRL_PHBFLTREN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHBFLTREN) & BM_FTM_QDCTRL_PHBFLTREN)
04306 
04307 /*! @brief Set the PHBFLTREN field to a new value. */
04308 #define BW_FTM_QDCTRL_PHBFLTREN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHBFLTREN), v))
04309 /*@}*/
04310 
04311 /*!
04312  * @name Register FTM_QDCTRL, field PHAFLTREN[7] (RW)
04313  *
04314  * Enables the filter for the quadrature decoder phase A input. The filter value
04315  * for the phase A input is defined by the CH0FVAL field of FILTER. The phase A
04316  * filter is also disabled when CH0FVAL is zero.
04317  *
04318  * Values:
04319  * - 0 - Phase A input filter is disabled.
04320  * - 1 - Phase A input filter is enabled.
04321  */
04322 /*@{*/
04323 #define BP_FTM_QDCTRL_PHAFLTREN (7U)       /*!< Bit position for FTM_QDCTRL_PHAFLTREN. */
04324 #define BM_FTM_QDCTRL_PHAFLTREN (0x00000080U) /*!< Bit mask for FTM_QDCTRL_PHAFLTREN. */
04325 #define BS_FTM_QDCTRL_PHAFLTREN (1U)       /*!< Bit field size in bits for FTM_QDCTRL_PHAFLTREN. */
04326 
04327 /*! @brief Read current value of the FTM_QDCTRL_PHAFLTREN field. */
04328 #define BR_FTM_QDCTRL_PHAFLTREN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAFLTREN)))
04329 
04330 /*! @brief Format value for bitfield FTM_QDCTRL_PHAFLTREN. */
04331 #define BF_FTM_QDCTRL_PHAFLTREN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_QDCTRL_PHAFLTREN) & BM_FTM_QDCTRL_PHAFLTREN)
04332 
04333 /*! @brief Set the PHAFLTREN field to a new value. */
04334 #define BW_FTM_QDCTRL_PHAFLTREN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_QDCTRL_ADDR(x), BP_FTM_QDCTRL_PHAFLTREN), v))
04335 /*@}*/
04336 
04337 /*******************************************************************************
04338  * HW_FTM_CONF - Configuration
04339  ******************************************************************************/
04340 
04341 /*!
04342  * @brief HW_FTM_CONF - Configuration (RW)
04343  *
04344  * Reset value: 0x00000000U
04345  *
04346  * This register selects the number of times that the FTM counter overflow
04347  * should occur before the TOF bit to be set, the FTM behavior in BDM modes, the use
04348  * of an external global time base, and the global time base signal generation.
04349  */
04350 typedef union _hw_ftm_conf
04351 {
04352     uint32_t U;
04353     struct _hw_ftm_conf_bitfields
04354     {
04355         uint32_t NUMTOF : 5;           /*!< [4:0] TOF Frequency */
04356         uint32_t RESERVED0 : 1;        /*!< [5]  */
04357         uint32_t BDMMODE : 2;          /*!< [7:6] BDM Mode */
04358         uint32_t RESERVED1 : 1;        /*!< [8]  */
04359         uint32_t GTBEEN : 1;           /*!< [9] Global Time Base Enable */
04360         uint32_t GTBEOUT : 1;          /*!< [10] Global Time Base Output */
04361         uint32_t RESERVED2 : 21;       /*!< [31:11]  */
04362     } B;
04363 } hw_ftm_conf_t;
04364 
04365 /*!
04366  * @name Constants and macros for entire FTM_CONF register
04367  */
04368 /*@{*/
04369 #define HW_FTM_CONF_ADDR(x)      ((x) + 0x84U)
04370 
04371 #define HW_FTM_CONF(x)           (*(__IO hw_ftm_conf_t *) HW_FTM_CONF_ADDR(x))
04372 #define HW_FTM_CONF_RD(x)        (ADDRESS_READ(hw_ftm_conf_t, HW_FTM_CONF_ADDR(x)))
04373 #define HW_FTM_CONF_WR(x, v)     (ADDRESS_WRITE(hw_ftm_conf_t, HW_FTM_CONF_ADDR(x), v))
04374 #define HW_FTM_CONF_SET(x, v)    (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) |  (v)))
04375 #define HW_FTM_CONF_CLR(x, v)    (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) & ~(v)))
04376 #define HW_FTM_CONF_TOG(x, v)    (HW_FTM_CONF_WR(x, HW_FTM_CONF_RD(x) ^  (v)))
04377 /*@}*/
04378 
04379 /*
04380  * Constants & macros for individual FTM_CONF bitfields
04381  */
04382 
04383 /*!
04384  * @name Register FTM_CONF, field NUMTOF[4:0] (RW)
04385  *
04386  * Selects the ratio between the number of counter overflows to the number of
04387  * times the TOF bit is set. NUMTOF = 0: The TOF bit is set for each counter
04388  * overflow. NUMTOF = 1: The TOF bit is set for the first counter overflow but not for
04389  * the next overflow. NUMTOF = 2: The TOF bit is set for the first counter
04390  * overflow but not for the next 2 overflows. NUMTOF = 3: The TOF bit is set for the
04391  * first counter overflow but not for the next 3 overflows. This pattern continues
04392  * up to a maximum of 31.
04393  */
04394 /*@{*/
04395 #define BP_FTM_CONF_NUMTOF   (0U)          /*!< Bit position for FTM_CONF_NUMTOF. */
04396 #define BM_FTM_CONF_NUMTOF   (0x0000001FU) /*!< Bit mask for FTM_CONF_NUMTOF. */
04397 #define BS_FTM_CONF_NUMTOF   (5U)          /*!< Bit field size in bits for FTM_CONF_NUMTOF. */
04398 
04399 /*! @brief Read current value of the FTM_CONF_NUMTOF field. */
04400 #define BR_FTM_CONF_NUMTOF(x) (UNION_READ(hw_ftm_conf_t, HW_FTM_CONF_ADDR(x), U, B.NUMTOF))
04401 
04402 /*! @brief Format value for bitfield FTM_CONF_NUMTOF. */
04403 #define BF_FTM_CONF_NUMTOF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_NUMTOF) & BM_FTM_CONF_NUMTOF)
04404 
04405 /*! @brief Set the NUMTOF field to a new value. */
04406 #define BW_FTM_CONF_NUMTOF(x, v) (HW_FTM_CONF_WR(x, (HW_FTM_CONF_RD(x) & ~BM_FTM_CONF_NUMTOF) | BF_FTM_CONF_NUMTOF(v)))
04407 /*@}*/
04408 
04409 /*!
04410  * @name Register FTM_CONF, field BDMMODE[7:6] (RW)
04411  *
04412  * Selects the FTM behavior in BDM mode. See BDM mode.
04413  */
04414 /*@{*/
04415 #define BP_FTM_CONF_BDMMODE  (6U)          /*!< Bit position for FTM_CONF_BDMMODE. */
04416 #define BM_FTM_CONF_BDMMODE  (0x000000C0U) /*!< Bit mask for FTM_CONF_BDMMODE. */
04417 #define BS_FTM_CONF_BDMMODE  (2U)          /*!< Bit field size in bits for FTM_CONF_BDMMODE. */
04418 
04419 /*! @brief Read current value of the FTM_CONF_BDMMODE field. */
04420 #define BR_FTM_CONF_BDMMODE(x) (UNION_READ(hw_ftm_conf_t, HW_FTM_CONF_ADDR(x), U, B.BDMMODE))
04421 
04422 /*! @brief Format value for bitfield FTM_CONF_BDMMODE. */
04423 #define BF_FTM_CONF_BDMMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_BDMMODE) & BM_FTM_CONF_BDMMODE)
04424 
04425 /*! @brief Set the BDMMODE field to a new value. */
04426 #define BW_FTM_CONF_BDMMODE(x, v) (HW_FTM_CONF_WR(x, (HW_FTM_CONF_RD(x) & ~BM_FTM_CONF_BDMMODE) | BF_FTM_CONF_BDMMODE(v)))
04427 /*@}*/
04428 
04429 /*!
04430  * @name Register FTM_CONF, field GTBEEN[9] (RW)
04431  *
04432  * Configures the FTM to use an external global time base signal that is
04433  * generated by another FTM.
04434  *
04435  * Values:
04436  * - 0 - Use of an external global time base is disabled.
04437  * - 1 - Use of an external global time base is enabled.
04438  */
04439 /*@{*/
04440 #define BP_FTM_CONF_GTBEEN   (9U)          /*!< Bit position for FTM_CONF_GTBEEN. */
04441 #define BM_FTM_CONF_GTBEEN   (0x00000200U) /*!< Bit mask for FTM_CONF_GTBEEN. */
04442 #define BS_FTM_CONF_GTBEEN   (1U)          /*!< Bit field size in bits for FTM_CONF_GTBEEN. */
04443 
04444 /*! @brief Read current value of the FTM_CONF_GTBEEN field. */
04445 #define BR_FTM_CONF_GTBEEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEEN)))
04446 
04447 /*! @brief Format value for bitfield FTM_CONF_GTBEEN. */
04448 #define BF_FTM_CONF_GTBEEN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_GTBEEN) & BM_FTM_CONF_GTBEEN)
04449 
04450 /*! @brief Set the GTBEEN field to a new value. */
04451 #define BW_FTM_CONF_GTBEEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEEN), v))
04452 /*@}*/
04453 
04454 /*!
04455  * @name Register FTM_CONF, field GTBEOUT[10] (RW)
04456  *
04457  * Enables the global time base signal generation to other FTMs.
04458  *
04459  * Values:
04460  * - 0 - A global time base signal generation is disabled.
04461  * - 1 - A global time base signal generation is enabled.
04462  */
04463 /*@{*/
04464 #define BP_FTM_CONF_GTBEOUT  (10U)         /*!< Bit position for FTM_CONF_GTBEOUT. */
04465 #define BM_FTM_CONF_GTBEOUT  (0x00000400U) /*!< Bit mask for FTM_CONF_GTBEOUT. */
04466 #define BS_FTM_CONF_GTBEOUT  (1U)          /*!< Bit field size in bits for FTM_CONF_GTBEOUT. */
04467 
04468 /*! @brief Read current value of the FTM_CONF_GTBEOUT field. */
04469 #define BR_FTM_CONF_GTBEOUT(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEOUT)))
04470 
04471 /*! @brief Format value for bitfield FTM_CONF_GTBEOUT. */
04472 #define BF_FTM_CONF_GTBEOUT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_CONF_GTBEOUT) & BM_FTM_CONF_GTBEOUT)
04473 
04474 /*! @brief Set the GTBEOUT field to a new value. */
04475 #define BW_FTM_CONF_GTBEOUT(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_CONF_ADDR(x), BP_FTM_CONF_GTBEOUT), v))
04476 /*@}*/
04477 
04478 /*******************************************************************************
04479  * HW_FTM_FLTPOL - FTM Fault Input Polarity
04480  ******************************************************************************/
04481 
04482 /*!
04483  * @brief HW_FTM_FLTPOL - FTM Fault Input Polarity (RW)
04484  *
04485  * Reset value: 0x00000000U
04486  *
04487  * This register defines the fault inputs polarity.
04488  */
04489 typedef union _hw_ftm_fltpol
04490 {
04491     uint32_t U;
04492     struct _hw_ftm_fltpol_bitfields
04493     {
04494         uint32_t FLT0POL : 1;          /*!< [0] Fault Input 0 Polarity */
04495         uint32_t FLT1POL : 1;          /*!< [1] Fault Input 1 Polarity */
04496         uint32_t FLT2POL : 1;          /*!< [2] Fault Input 2 Polarity */
04497         uint32_t FLT3POL : 1;          /*!< [3] Fault Input 3 Polarity */
04498         uint32_t RESERVED0 : 28;       /*!< [31:4]  */
04499     } B;
04500 } hw_ftm_fltpol_t;
04501 
04502 /*!
04503  * @name Constants and macros for entire FTM_FLTPOL register
04504  */
04505 /*@{*/
04506 #define HW_FTM_FLTPOL_ADDR(x)    ((x) + 0x88U)
04507 
04508 #define HW_FTM_FLTPOL(x)         (*(__IO hw_ftm_fltpol_t *) HW_FTM_FLTPOL_ADDR(x))
04509 #define HW_FTM_FLTPOL_RD(x)      (ADDRESS_READ(hw_ftm_fltpol_t, HW_FTM_FLTPOL_ADDR(x)))
04510 #define HW_FTM_FLTPOL_WR(x, v)   (ADDRESS_WRITE(hw_ftm_fltpol_t, HW_FTM_FLTPOL_ADDR(x), v))
04511 #define HW_FTM_FLTPOL_SET(x, v)  (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) |  (v)))
04512 #define HW_FTM_FLTPOL_CLR(x, v)  (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) & ~(v)))
04513 #define HW_FTM_FLTPOL_TOG(x, v)  (HW_FTM_FLTPOL_WR(x, HW_FTM_FLTPOL_RD(x) ^  (v)))
04514 /*@}*/
04515 
04516 /*
04517  * Constants & macros for individual FTM_FLTPOL bitfields
04518  */
04519 
04520 /*!
04521  * @name Register FTM_FLTPOL, field FLT0POL[0] (RW)
04522  *
04523  * Defines the polarity of the fault input. This field is write protected. It
04524  * can be written only when MODE[WPDIS] = 1.
04525  *
04526  * Values:
04527  * - 0 - The fault input polarity is active high. A 1 at the fault input
04528  *     indicates a fault.
04529  * - 1 - The fault input polarity is active low. A 0 at the fault input
04530  *     indicates a fault.
04531  */
04532 /*@{*/
04533 #define BP_FTM_FLTPOL_FLT0POL (0U)         /*!< Bit position for FTM_FLTPOL_FLT0POL. */
04534 #define BM_FTM_FLTPOL_FLT0POL (0x00000001U) /*!< Bit mask for FTM_FLTPOL_FLT0POL. */
04535 #define BS_FTM_FLTPOL_FLT0POL (1U)         /*!< Bit field size in bits for FTM_FLTPOL_FLT0POL. */
04536 
04537 /*! @brief Read current value of the FTM_FLTPOL_FLT0POL field. */
04538 #define BR_FTM_FLTPOL_FLT0POL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT0POL)))
04539 
04540 /*! @brief Format value for bitfield FTM_FLTPOL_FLT0POL. */
04541 #define BF_FTM_FLTPOL_FLT0POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT0POL) & BM_FTM_FLTPOL_FLT0POL)
04542 
04543 /*! @brief Set the FLT0POL field to a new value. */
04544 #define BW_FTM_FLTPOL_FLT0POL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT0POL), v))
04545 /*@}*/
04546 
04547 /*!
04548  * @name Register FTM_FLTPOL, field FLT1POL[1] (RW)
04549  *
04550  * Defines the polarity of the fault input. This field is write protected. It
04551  * can be written only when MODE[WPDIS] = 1.
04552  *
04553  * Values:
04554  * - 0 - The fault input polarity is active high. A 1 at the fault input
04555  *     indicates a fault.
04556  * - 1 - The fault input polarity is active low. A 0 at the fault input
04557  *     indicates a fault.
04558  */
04559 /*@{*/
04560 #define BP_FTM_FLTPOL_FLT1POL (1U)         /*!< Bit position for FTM_FLTPOL_FLT1POL. */
04561 #define BM_FTM_FLTPOL_FLT1POL (0x00000002U) /*!< Bit mask for FTM_FLTPOL_FLT1POL. */
04562 #define BS_FTM_FLTPOL_FLT1POL (1U)         /*!< Bit field size in bits for FTM_FLTPOL_FLT1POL. */
04563 
04564 /*! @brief Read current value of the FTM_FLTPOL_FLT1POL field. */
04565 #define BR_FTM_FLTPOL_FLT1POL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT1POL)))
04566 
04567 /*! @brief Format value for bitfield FTM_FLTPOL_FLT1POL. */
04568 #define BF_FTM_FLTPOL_FLT1POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT1POL) & BM_FTM_FLTPOL_FLT1POL)
04569 
04570 /*! @brief Set the FLT1POL field to a new value. */
04571 #define BW_FTM_FLTPOL_FLT1POL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT1POL), v))
04572 /*@}*/
04573 
04574 /*!
04575  * @name Register FTM_FLTPOL, field FLT2POL[2] (RW)
04576  *
04577  * Defines the polarity of the fault input. This field is write protected. It
04578  * can be written only when MODE[WPDIS] = 1.
04579  *
04580  * Values:
04581  * - 0 - The fault input polarity is active high. A 1 at the fault input
04582  *     indicates a fault.
04583  * - 1 - The fault input polarity is active low. A 0 at the fault input
04584  *     indicates a fault.
04585  */
04586 /*@{*/
04587 #define BP_FTM_FLTPOL_FLT2POL (2U)         /*!< Bit position for FTM_FLTPOL_FLT2POL. */
04588 #define BM_FTM_FLTPOL_FLT2POL (0x00000004U) /*!< Bit mask for FTM_FLTPOL_FLT2POL. */
04589 #define BS_FTM_FLTPOL_FLT2POL (1U)         /*!< Bit field size in bits for FTM_FLTPOL_FLT2POL. */
04590 
04591 /*! @brief Read current value of the FTM_FLTPOL_FLT2POL field. */
04592 #define BR_FTM_FLTPOL_FLT2POL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT2POL)))
04593 
04594 /*! @brief Format value for bitfield FTM_FLTPOL_FLT2POL. */
04595 #define BF_FTM_FLTPOL_FLT2POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT2POL) & BM_FTM_FLTPOL_FLT2POL)
04596 
04597 /*! @brief Set the FLT2POL field to a new value. */
04598 #define BW_FTM_FLTPOL_FLT2POL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT2POL), v))
04599 /*@}*/
04600 
04601 /*!
04602  * @name Register FTM_FLTPOL, field FLT3POL[3] (RW)
04603  *
04604  * Defines the polarity of the fault input. This field is write protected. It
04605  * can be written only when MODE[WPDIS] = 1.
04606  *
04607  * Values:
04608  * - 0 - The fault input polarity is active high. A 1 at the fault input
04609  *     indicates a fault.
04610  * - 1 - The fault input polarity is active low. A 0 at the fault input
04611  *     indicates a fault.
04612  */
04613 /*@{*/
04614 #define BP_FTM_FLTPOL_FLT3POL (3U)         /*!< Bit position for FTM_FLTPOL_FLT3POL. */
04615 #define BM_FTM_FLTPOL_FLT3POL (0x00000008U) /*!< Bit mask for FTM_FLTPOL_FLT3POL. */
04616 #define BS_FTM_FLTPOL_FLT3POL (1U)         /*!< Bit field size in bits for FTM_FLTPOL_FLT3POL. */
04617 
04618 /*! @brief Read current value of the FTM_FLTPOL_FLT3POL field. */
04619 #define BR_FTM_FLTPOL_FLT3POL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT3POL)))
04620 
04621 /*! @brief Format value for bitfield FTM_FLTPOL_FLT3POL. */
04622 #define BF_FTM_FLTPOL_FLT3POL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_FLTPOL_FLT3POL) & BM_FTM_FLTPOL_FLT3POL)
04623 
04624 /*! @brief Set the FLT3POL field to a new value. */
04625 #define BW_FTM_FLTPOL_FLT3POL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_FLTPOL_ADDR(x), BP_FTM_FLTPOL_FLT3POL), v))
04626 /*@}*/
04627 
04628 /*******************************************************************************
04629  * HW_FTM_SYNCONF - Synchronization Configuration
04630  ******************************************************************************/
04631 
04632 /*!
04633  * @brief HW_FTM_SYNCONF - Synchronization Configuration (RW)
04634  *
04635  * Reset value: 0x00000000U
04636  *
04637  * This register selects the PWM synchronization configuration, SWOCTRL, INVCTRL
04638  * and CNTIN registers synchronization, if FTM clears the TRIGj bit, where j =
04639  * 0, 1, 2, when the hardware trigger j is detected.
04640  */
04641 typedef union _hw_ftm_synconf
04642 {
04643     uint32_t U;
04644     struct _hw_ftm_synconf_bitfields
04645     {
04646         uint32_t HWTRIGMODE : 1;       /*!< [0] Hardware Trigger Mode */
04647         uint32_t RESERVED0 : 1;        /*!< [1]  */
04648         uint32_t CNTINC : 1;           /*!< [2] CNTIN Register Synchronization */
04649         uint32_t RESERVED1 : 1;        /*!< [3]  */
04650         uint32_t INVC : 1;             /*!< [4] INVCTRL Register Synchronization */
04651         uint32_t SWOC : 1;             /*!< [5] SWOCTRL Register Synchronization */
04652         uint32_t RESERVED2 : 1;        /*!< [6]  */
04653         uint32_t SYNCMODE : 1;         /*!< [7] Synchronization Mode */
04654         uint32_t SWRSTCNT : 1;         /*!< [8]  */
04655         uint32_t SWWRBUF : 1;          /*!< [9]  */
04656         uint32_t SWOM : 1;             /*!< [10]  */
04657         uint32_t SWINVC : 1;           /*!< [11]  */
04658         uint32_t SWSOC : 1;            /*!< [12]  */
04659         uint32_t RESERVED3 : 3;        /*!< [15:13]  */
04660         uint32_t HWRSTCNT : 1;         /*!< [16]  */
04661         uint32_t HWWRBUF : 1;          /*!< [17]  */
04662         uint32_t HWOM : 1;             /*!< [18]  */
04663         uint32_t HWINVC : 1;           /*!< [19]  */
04664         uint32_t HWSOC : 1;            /*!< [20]  */
04665         uint32_t RESERVED4 : 11;       /*!< [31:21]  */
04666     } B;
04667 } hw_ftm_synconf_t;
04668 
04669 /*!
04670  * @name Constants and macros for entire FTM_SYNCONF register
04671  */
04672 /*@{*/
04673 #define HW_FTM_SYNCONF_ADDR(x)   ((x) + 0x8CU)
04674 
04675 #define HW_FTM_SYNCONF(x)        (*(__IO hw_ftm_synconf_t *) HW_FTM_SYNCONF_ADDR(x))
04676 #define HW_FTM_SYNCONF_RD(x)     (ADDRESS_READ(hw_ftm_synconf_t, HW_FTM_SYNCONF_ADDR(x)))
04677 #define HW_FTM_SYNCONF_WR(x, v)  (ADDRESS_WRITE(hw_ftm_synconf_t, HW_FTM_SYNCONF_ADDR(x), v))
04678 #define HW_FTM_SYNCONF_SET(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) |  (v)))
04679 #define HW_FTM_SYNCONF_CLR(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) & ~(v)))
04680 #define HW_FTM_SYNCONF_TOG(x, v) (HW_FTM_SYNCONF_WR(x, HW_FTM_SYNCONF_RD(x) ^  (v)))
04681 /*@}*/
04682 
04683 /*
04684  * Constants & macros for individual FTM_SYNCONF bitfields
04685  */
04686 
04687 /*!
04688  * @name Register FTM_SYNCONF, field HWTRIGMODE[0] (RW)
04689  *
04690  * Values:
04691  * - 0 - FTM clears the TRIGj bit when the hardware trigger j is detected, where
04692  *     j = 0, 1,2.
04693  * - 1 - FTM does not clear the TRIGj bit when the hardware trigger j is
04694  *     detected, where j = 0, 1,2.
04695  */
04696 /*@{*/
04697 #define BP_FTM_SYNCONF_HWTRIGMODE (0U)     /*!< Bit position for FTM_SYNCONF_HWTRIGMODE. */
04698 #define BM_FTM_SYNCONF_HWTRIGMODE (0x00000001U) /*!< Bit mask for FTM_SYNCONF_HWTRIGMODE. */
04699 #define BS_FTM_SYNCONF_HWTRIGMODE (1U)     /*!< Bit field size in bits for FTM_SYNCONF_HWTRIGMODE. */
04700 
04701 /*! @brief Read current value of the FTM_SYNCONF_HWTRIGMODE field. */
04702 #define BR_FTM_SYNCONF_HWTRIGMODE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWTRIGMODE)))
04703 
04704 /*! @brief Format value for bitfield FTM_SYNCONF_HWTRIGMODE. */
04705 #define BF_FTM_SYNCONF_HWTRIGMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWTRIGMODE) & BM_FTM_SYNCONF_HWTRIGMODE)
04706 
04707 /*! @brief Set the HWTRIGMODE field to a new value. */
04708 #define BW_FTM_SYNCONF_HWTRIGMODE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWTRIGMODE), v))
04709 /*@}*/
04710 
04711 /*!
04712  * @name Register FTM_SYNCONF, field CNTINC[2] (RW)
04713  *
04714  * Values:
04715  * - 0 - CNTIN register is updated with its buffer value at all rising edges of
04716  *     system clock.
04717  * - 1 - CNTIN register is updated with its buffer value by the PWM
04718  *     synchronization.
04719  */
04720 /*@{*/
04721 #define BP_FTM_SYNCONF_CNTINC (2U)         /*!< Bit position for FTM_SYNCONF_CNTINC. */
04722 #define BM_FTM_SYNCONF_CNTINC (0x00000004U) /*!< Bit mask for FTM_SYNCONF_CNTINC. */
04723 #define BS_FTM_SYNCONF_CNTINC (1U)         /*!< Bit field size in bits for FTM_SYNCONF_CNTINC. */
04724 
04725 /*! @brief Read current value of the FTM_SYNCONF_CNTINC field. */
04726 #define BR_FTM_SYNCONF_CNTINC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_CNTINC)))
04727 
04728 /*! @brief Format value for bitfield FTM_SYNCONF_CNTINC. */
04729 #define BF_FTM_SYNCONF_CNTINC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_CNTINC) & BM_FTM_SYNCONF_CNTINC)
04730 
04731 /*! @brief Set the CNTINC field to a new value. */
04732 #define BW_FTM_SYNCONF_CNTINC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_CNTINC), v))
04733 /*@}*/
04734 
04735 /*!
04736  * @name Register FTM_SYNCONF, field INVC[4] (RW)
04737  *
04738  * Values:
04739  * - 0 - INVCTRL register is updated with its buffer value at all rising edges
04740  *     of system clock.
04741  * - 1 - INVCTRL register is updated with its buffer value by the PWM
04742  *     synchronization.
04743  */
04744 /*@{*/
04745 #define BP_FTM_SYNCONF_INVC  (4U)          /*!< Bit position for FTM_SYNCONF_INVC. */
04746 #define BM_FTM_SYNCONF_INVC  (0x00000010U) /*!< Bit mask for FTM_SYNCONF_INVC. */
04747 #define BS_FTM_SYNCONF_INVC  (1U)          /*!< Bit field size in bits for FTM_SYNCONF_INVC. */
04748 
04749 /*! @brief Read current value of the FTM_SYNCONF_INVC field. */
04750 #define BR_FTM_SYNCONF_INVC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_INVC)))
04751 
04752 /*! @brief Format value for bitfield FTM_SYNCONF_INVC. */
04753 #define BF_FTM_SYNCONF_INVC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_INVC) & BM_FTM_SYNCONF_INVC)
04754 
04755 /*! @brief Set the INVC field to a new value. */
04756 #define BW_FTM_SYNCONF_INVC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_INVC), v))
04757 /*@}*/
04758 
04759 /*!
04760  * @name Register FTM_SYNCONF, field SWOC[5] (RW)
04761  *
04762  * Values:
04763  * - 0 - SWOCTRL register is updated with its buffer value at all rising edges
04764  *     of system clock.
04765  * - 1 - SWOCTRL register is updated with its buffer value by the PWM
04766  *     synchronization.
04767  */
04768 /*@{*/
04769 #define BP_FTM_SYNCONF_SWOC  (5U)          /*!< Bit position for FTM_SYNCONF_SWOC. */
04770 #define BM_FTM_SYNCONF_SWOC  (0x00000020U) /*!< Bit mask for FTM_SYNCONF_SWOC. */
04771 #define BS_FTM_SYNCONF_SWOC  (1U)          /*!< Bit field size in bits for FTM_SYNCONF_SWOC. */
04772 
04773 /*! @brief Read current value of the FTM_SYNCONF_SWOC field. */
04774 #define BR_FTM_SYNCONF_SWOC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOC)))
04775 
04776 /*! @brief Format value for bitfield FTM_SYNCONF_SWOC. */
04777 #define BF_FTM_SYNCONF_SWOC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWOC) & BM_FTM_SYNCONF_SWOC)
04778 
04779 /*! @brief Set the SWOC field to a new value. */
04780 #define BW_FTM_SYNCONF_SWOC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOC), v))
04781 /*@}*/
04782 
04783 /*!
04784  * @name Register FTM_SYNCONF, field SYNCMODE[7] (RW)
04785  *
04786  * Selects the PWM Synchronization mode.
04787  *
04788  * Values:
04789  * - 0 - Legacy PWM synchronization is selected.
04790  * - 1 - Enhanced PWM synchronization is selected.
04791  */
04792 /*@{*/
04793 #define BP_FTM_SYNCONF_SYNCMODE (7U)       /*!< Bit position for FTM_SYNCONF_SYNCMODE. */
04794 #define BM_FTM_SYNCONF_SYNCMODE (0x00000080U) /*!< Bit mask for FTM_SYNCONF_SYNCMODE. */
04795 #define BS_FTM_SYNCONF_SYNCMODE (1U)       /*!< Bit field size in bits for FTM_SYNCONF_SYNCMODE. */
04796 
04797 /*! @brief Read current value of the FTM_SYNCONF_SYNCMODE field. */
04798 #define BR_FTM_SYNCONF_SYNCMODE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SYNCMODE)))
04799 
04800 /*! @brief Format value for bitfield FTM_SYNCONF_SYNCMODE. */
04801 #define BF_FTM_SYNCONF_SYNCMODE(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SYNCMODE) & BM_FTM_SYNCONF_SYNCMODE)
04802 
04803 /*! @brief Set the SYNCMODE field to a new value. */
04804 #define BW_FTM_SYNCONF_SYNCMODE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SYNCMODE), v))
04805 /*@}*/
04806 
04807 /*!
04808  * @name Register FTM_SYNCONF, field SWRSTCNT[8] (RW)
04809  *
04810  * FTM counter synchronization is activated by the software trigger.
04811  *
04812  * Values:
04813  * - 0 - The software trigger does not activate the FTM counter synchronization.
04814  * - 1 - The software trigger activates the FTM counter synchronization.
04815  */
04816 /*@{*/
04817 #define BP_FTM_SYNCONF_SWRSTCNT (8U)       /*!< Bit position for FTM_SYNCONF_SWRSTCNT. */
04818 #define BM_FTM_SYNCONF_SWRSTCNT (0x00000100U) /*!< Bit mask for FTM_SYNCONF_SWRSTCNT. */
04819 #define BS_FTM_SYNCONF_SWRSTCNT (1U)       /*!< Bit field size in bits for FTM_SYNCONF_SWRSTCNT. */
04820 
04821 /*! @brief Read current value of the FTM_SYNCONF_SWRSTCNT field. */
04822 #define BR_FTM_SYNCONF_SWRSTCNT(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWRSTCNT)))
04823 
04824 /*! @brief Format value for bitfield FTM_SYNCONF_SWRSTCNT. */
04825 #define BF_FTM_SYNCONF_SWRSTCNT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWRSTCNT) & BM_FTM_SYNCONF_SWRSTCNT)
04826 
04827 /*! @brief Set the SWRSTCNT field to a new value. */
04828 #define BW_FTM_SYNCONF_SWRSTCNT(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWRSTCNT), v))
04829 /*@}*/
04830 
04831 /*!
04832  * @name Register FTM_SYNCONF, field SWWRBUF[9] (RW)
04833  *
04834  * MOD, CNTIN, and CV registers synchronization is activated by the software
04835  * trigger.
04836  *
04837  * Values:
04838  * - 0 - The software trigger does not activate MOD, CNTIN, and CV registers
04839  *     synchronization.
04840  * - 1 - The software trigger activates MOD, CNTIN, and CV registers
04841  *     synchronization.
04842  */
04843 /*@{*/
04844 #define BP_FTM_SYNCONF_SWWRBUF (9U)        /*!< Bit position for FTM_SYNCONF_SWWRBUF. */
04845 #define BM_FTM_SYNCONF_SWWRBUF (0x00000200U) /*!< Bit mask for FTM_SYNCONF_SWWRBUF. */
04846 #define BS_FTM_SYNCONF_SWWRBUF (1U)        /*!< Bit field size in bits for FTM_SYNCONF_SWWRBUF. */
04847 
04848 /*! @brief Read current value of the FTM_SYNCONF_SWWRBUF field. */
04849 #define BR_FTM_SYNCONF_SWWRBUF(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWWRBUF)))
04850 
04851 /*! @brief Format value for bitfield FTM_SYNCONF_SWWRBUF. */
04852 #define BF_FTM_SYNCONF_SWWRBUF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWWRBUF) & BM_FTM_SYNCONF_SWWRBUF)
04853 
04854 /*! @brief Set the SWWRBUF field to a new value. */
04855 #define BW_FTM_SYNCONF_SWWRBUF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWWRBUF), v))
04856 /*@}*/
04857 
04858 /*!
04859  * @name Register FTM_SYNCONF, field SWOM[10] (RW)
04860  *
04861  * Output mask synchronization is activated by the software trigger.
04862  *
04863  * Values:
04864  * - 0 - The software trigger does not activate the OUTMASK register
04865  *     synchronization.
04866  * - 1 - The software trigger activates the OUTMASK register synchronization.
04867  */
04868 /*@{*/
04869 #define BP_FTM_SYNCONF_SWOM  (10U)         /*!< Bit position for FTM_SYNCONF_SWOM. */
04870 #define BM_FTM_SYNCONF_SWOM  (0x00000400U) /*!< Bit mask for FTM_SYNCONF_SWOM. */
04871 #define BS_FTM_SYNCONF_SWOM  (1U)          /*!< Bit field size in bits for FTM_SYNCONF_SWOM. */
04872 
04873 /*! @brief Read current value of the FTM_SYNCONF_SWOM field. */
04874 #define BR_FTM_SYNCONF_SWOM(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOM)))
04875 
04876 /*! @brief Format value for bitfield FTM_SYNCONF_SWOM. */
04877 #define BF_FTM_SYNCONF_SWOM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWOM) & BM_FTM_SYNCONF_SWOM)
04878 
04879 /*! @brief Set the SWOM field to a new value. */
04880 #define BW_FTM_SYNCONF_SWOM(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWOM), v))
04881 /*@}*/
04882 
04883 /*!
04884  * @name Register FTM_SYNCONF, field SWINVC[11] (RW)
04885  *
04886  * Inverting control synchronization is activated by the software trigger.
04887  *
04888  * Values:
04889  * - 0 - The software trigger does not activate the INVCTRL register
04890  *     synchronization.
04891  * - 1 - The software trigger activates the INVCTRL register synchronization.
04892  */
04893 /*@{*/
04894 #define BP_FTM_SYNCONF_SWINVC (11U)        /*!< Bit position for FTM_SYNCONF_SWINVC. */
04895 #define BM_FTM_SYNCONF_SWINVC (0x00000800U) /*!< Bit mask for FTM_SYNCONF_SWINVC. */
04896 #define BS_FTM_SYNCONF_SWINVC (1U)         /*!< Bit field size in bits for FTM_SYNCONF_SWINVC. */
04897 
04898 /*! @brief Read current value of the FTM_SYNCONF_SWINVC field. */
04899 #define BR_FTM_SYNCONF_SWINVC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWINVC)))
04900 
04901 /*! @brief Format value for bitfield FTM_SYNCONF_SWINVC. */
04902 #define BF_FTM_SYNCONF_SWINVC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWINVC) & BM_FTM_SYNCONF_SWINVC)
04903 
04904 /*! @brief Set the SWINVC field to a new value. */
04905 #define BW_FTM_SYNCONF_SWINVC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWINVC), v))
04906 /*@}*/
04907 
04908 /*!
04909  * @name Register FTM_SYNCONF, field SWSOC[12] (RW)
04910  *
04911  * Software output control synchronization is activated by the software trigger.
04912  *
04913  * Values:
04914  * - 0 - The software trigger does not activate the SWOCTRL register
04915  *     synchronization.
04916  * - 1 - The software trigger activates the SWOCTRL register synchronization.
04917  */
04918 /*@{*/
04919 #define BP_FTM_SYNCONF_SWSOC (12U)         /*!< Bit position for FTM_SYNCONF_SWSOC. */
04920 #define BM_FTM_SYNCONF_SWSOC (0x00001000U) /*!< Bit mask for FTM_SYNCONF_SWSOC. */
04921 #define BS_FTM_SYNCONF_SWSOC (1U)          /*!< Bit field size in bits for FTM_SYNCONF_SWSOC. */
04922 
04923 /*! @brief Read current value of the FTM_SYNCONF_SWSOC field. */
04924 #define BR_FTM_SYNCONF_SWSOC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWSOC)))
04925 
04926 /*! @brief Format value for bitfield FTM_SYNCONF_SWSOC. */
04927 #define BF_FTM_SYNCONF_SWSOC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_SWSOC) & BM_FTM_SYNCONF_SWSOC)
04928 
04929 /*! @brief Set the SWSOC field to a new value. */
04930 #define BW_FTM_SYNCONF_SWSOC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_SWSOC), v))
04931 /*@}*/
04932 
04933 /*!
04934  * @name Register FTM_SYNCONF, field HWRSTCNT[16] (RW)
04935  *
04936  * FTM counter synchronization is activated by a hardware trigger.
04937  *
04938  * Values:
04939  * - 0 - A hardware trigger does not activate the FTM counter synchronization.
04940  * - 1 - A hardware trigger activates the FTM counter synchronization.
04941  */
04942 /*@{*/
04943 #define BP_FTM_SYNCONF_HWRSTCNT (16U)      /*!< Bit position for FTM_SYNCONF_HWRSTCNT. */
04944 #define BM_FTM_SYNCONF_HWRSTCNT (0x00010000U) /*!< Bit mask for FTM_SYNCONF_HWRSTCNT. */
04945 #define BS_FTM_SYNCONF_HWRSTCNT (1U)       /*!< Bit field size in bits for FTM_SYNCONF_HWRSTCNT. */
04946 
04947 /*! @brief Read current value of the FTM_SYNCONF_HWRSTCNT field. */
04948 #define BR_FTM_SYNCONF_HWRSTCNT(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWRSTCNT)))
04949 
04950 /*! @brief Format value for bitfield FTM_SYNCONF_HWRSTCNT. */
04951 #define BF_FTM_SYNCONF_HWRSTCNT(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWRSTCNT) & BM_FTM_SYNCONF_HWRSTCNT)
04952 
04953 /*! @brief Set the HWRSTCNT field to a new value. */
04954 #define BW_FTM_SYNCONF_HWRSTCNT(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWRSTCNT), v))
04955 /*@}*/
04956 
04957 /*!
04958  * @name Register FTM_SYNCONF, field HWWRBUF[17] (RW)
04959  *
04960  * MOD, CNTIN, and CV registers synchronization is activated by a hardware
04961  * trigger.
04962  *
04963  * Values:
04964  * - 0 - A hardware trigger does not activate MOD, CNTIN, and CV registers
04965  *     synchronization.
04966  * - 1 - A hardware trigger activates MOD, CNTIN, and CV registers
04967  *     synchronization.
04968  */
04969 /*@{*/
04970 #define BP_FTM_SYNCONF_HWWRBUF (17U)       /*!< Bit position for FTM_SYNCONF_HWWRBUF. */
04971 #define BM_FTM_SYNCONF_HWWRBUF (0x00020000U) /*!< Bit mask for FTM_SYNCONF_HWWRBUF. */
04972 #define BS_FTM_SYNCONF_HWWRBUF (1U)        /*!< Bit field size in bits for FTM_SYNCONF_HWWRBUF. */
04973 
04974 /*! @brief Read current value of the FTM_SYNCONF_HWWRBUF field. */
04975 #define BR_FTM_SYNCONF_HWWRBUF(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWWRBUF)))
04976 
04977 /*! @brief Format value for bitfield FTM_SYNCONF_HWWRBUF. */
04978 #define BF_FTM_SYNCONF_HWWRBUF(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWWRBUF) & BM_FTM_SYNCONF_HWWRBUF)
04979 
04980 /*! @brief Set the HWWRBUF field to a new value. */
04981 #define BW_FTM_SYNCONF_HWWRBUF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWWRBUF), v))
04982 /*@}*/
04983 
04984 /*!
04985  * @name Register FTM_SYNCONF, field HWOM[18] (RW)
04986  *
04987  * Output mask synchronization is activated by a hardware trigger.
04988  *
04989  * Values:
04990  * - 0 - A hardware trigger does not activate the OUTMASK register
04991  *     synchronization.
04992  * - 1 - A hardware trigger activates the OUTMASK register synchronization.
04993  */
04994 /*@{*/
04995 #define BP_FTM_SYNCONF_HWOM  (18U)         /*!< Bit position for FTM_SYNCONF_HWOM. */
04996 #define BM_FTM_SYNCONF_HWOM  (0x00040000U) /*!< Bit mask for FTM_SYNCONF_HWOM. */
04997 #define BS_FTM_SYNCONF_HWOM  (1U)          /*!< Bit field size in bits for FTM_SYNCONF_HWOM. */
04998 
04999 /*! @brief Read current value of the FTM_SYNCONF_HWOM field. */
05000 #define BR_FTM_SYNCONF_HWOM(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWOM)))
05001 
05002 /*! @brief Format value for bitfield FTM_SYNCONF_HWOM. */
05003 #define BF_FTM_SYNCONF_HWOM(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWOM) & BM_FTM_SYNCONF_HWOM)
05004 
05005 /*! @brief Set the HWOM field to a new value. */
05006 #define BW_FTM_SYNCONF_HWOM(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWOM), v))
05007 /*@}*/
05008 
05009 /*!
05010  * @name Register FTM_SYNCONF, field HWINVC[19] (RW)
05011  *
05012  * Inverting control synchronization is activated by a hardware trigger.
05013  *
05014  * Values:
05015  * - 0 - A hardware trigger does not activate the INVCTRL register
05016  *     synchronization.
05017  * - 1 - A hardware trigger activates the INVCTRL register synchronization.
05018  */
05019 /*@{*/
05020 #define BP_FTM_SYNCONF_HWINVC (19U)        /*!< Bit position for FTM_SYNCONF_HWINVC. */
05021 #define BM_FTM_SYNCONF_HWINVC (0x00080000U) /*!< Bit mask for FTM_SYNCONF_HWINVC. */
05022 #define BS_FTM_SYNCONF_HWINVC (1U)         /*!< Bit field size in bits for FTM_SYNCONF_HWINVC. */
05023 
05024 /*! @brief Read current value of the FTM_SYNCONF_HWINVC field. */
05025 #define BR_FTM_SYNCONF_HWINVC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWINVC)))
05026 
05027 /*! @brief Format value for bitfield FTM_SYNCONF_HWINVC. */
05028 #define BF_FTM_SYNCONF_HWINVC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWINVC) & BM_FTM_SYNCONF_HWINVC)
05029 
05030 /*! @brief Set the HWINVC field to a new value. */
05031 #define BW_FTM_SYNCONF_HWINVC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWINVC), v))
05032 /*@}*/
05033 
05034 /*!
05035  * @name Register FTM_SYNCONF, field HWSOC[20] (RW)
05036  *
05037  * Software output control synchronization is activated by a hardware trigger.
05038  *
05039  * Values:
05040  * - 0 - A hardware trigger does not activate the SWOCTRL register
05041  *     synchronization.
05042  * - 1 - A hardware trigger activates the SWOCTRL register synchronization.
05043  */
05044 /*@{*/
05045 #define BP_FTM_SYNCONF_HWSOC (20U)         /*!< Bit position for FTM_SYNCONF_HWSOC. */
05046 #define BM_FTM_SYNCONF_HWSOC (0x00100000U) /*!< Bit mask for FTM_SYNCONF_HWSOC. */
05047 #define BS_FTM_SYNCONF_HWSOC (1U)          /*!< Bit field size in bits for FTM_SYNCONF_HWSOC. */
05048 
05049 /*! @brief Read current value of the FTM_SYNCONF_HWSOC field. */
05050 #define BR_FTM_SYNCONF_HWSOC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWSOC)))
05051 
05052 /*! @brief Format value for bitfield FTM_SYNCONF_HWSOC. */
05053 #define BF_FTM_SYNCONF_HWSOC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SYNCONF_HWSOC) & BM_FTM_SYNCONF_HWSOC)
05054 
05055 /*! @brief Set the HWSOC field to a new value. */
05056 #define BW_FTM_SYNCONF_HWSOC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SYNCONF_ADDR(x), BP_FTM_SYNCONF_HWSOC), v))
05057 /*@}*/
05058 
05059 /*******************************************************************************
05060  * HW_FTM_INVCTRL - FTM Inverting Control
05061  ******************************************************************************/
05062 
05063 /*!
05064  * @brief HW_FTM_INVCTRL - FTM Inverting Control (RW)
05065  *
05066  * Reset value: 0x00000000U
05067  *
05068  * This register controls when the channel (n) output becomes the channel (n+1)
05069  * output, and channel (n+1) output becomes the channel (n) output. Each INVmEN
05070  * bit enables the inverting operation for the corresponding pair channels m. This
05071  * register has a write buffer. The INVmEN bit is updated by the INVCTRL
05072  * register synchronization.
05073  */
05074 typedef union _hw_ftm_invctrl
05075 {
05076     uint32_t U;
05077     struct _hw_ftm_invctrl_bitfields
05078     {
05079         uint32_t INV0EN : 1;           /*!< [0] Pair Channels 0 Inverting Enable */
05080         uint32_t INV1EN : 1;           /*!< [1] Pair Channels 1 Inverting Enable */
05081         uint32_t INV2EN : 1;           /*!< [2] Pair Channels 2 Inverting Enable */
05082         uint32_t INV3EN : 1;           /*!< [3] Pair Channels 3 Inverting Enable */
05083         uint32_t RESERVED0 : 28;       /*!< [31:4]  */
05084     } B;
05085 } hw_ftm_invctrl_t;
05086 
05087 /*!
05088  * @name Constants and macros for entire FTM_INVCTRL register
05089  */
05090 /*@{*/
05091 #define HW_FTM_INVCTRL_ADDR(x)   ((x) + 0x90U)
05092 
05093 #define HW_FTM_INVCTRL(x)        (*(__IO hw_ftm_invctrl_t *) HW_FTM_INVCTRL_ADDR(x))
05094 #define HW_FTM_INVCTRL_RD(x)     (ADDRESS_READ(hw_ftm_invctrl_t, HW_FTM_INVCTRL_ADDR(x)))
05095 #define HW_FTM_INVCTRL_WR(x, v)  (ADDRESS_WRITE(hw_ftm_invctrl_t, HW_FTM_INVCTRL_ADDR(x), v))
05096 #define HW_FTM_INVCTRL_SET(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) |  (v)))
05097 #define HW_FTM_INVCTRL_CLR(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) & ~(v)))
05098 #define HW_FTM_INVCTRL_TOG(x, v) (HW_FTM_INVCTRL_WR(x, HW_FTM_INVCTRL_RD(x) ^  (v)))
05099 /*@}*/
05100 
05101 /*
05102  * Constants & macros for individual FTM_INVCTRL bitfields
05103  */
05104 
05105 /*!
05106  * @name Register FTM_INVCTRL, field INV0EN[0] (RW)
05107  *
05108  * Values:
05109  * - 0 - Inverting is disabled.
05110  * - 1 - Inverting is enabled.
05111  */
05112 /*@{*/
05113 #define BP_FTM_INVCTRL_INV0EN (0U)         /*!< Bit position for FTM_INVCTRL_INV0EN. */
05114 #define BM_FTM_INVCTRL_INV0EN (0x00000001U) /*!< Bit mask for FTM_INVCTRL_INV0EN. */
05115 #define BS_FTM_INVCTRL_INV0EN (1U)         /*!< Bit field size in bits for FTM_INVCTRL_INV0EN. */
05116 
05117 /*! @brief Read current value of the FTM_INVCTRL_INV0EN field. */
05118 #define BR_FTM_INVCTRL_INV0EN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV0EN)))
05119 
05120 /*! @brief Format value for bitfield FTM_INVCTRL_INV0EN. */
05121 #define BF_FTM_INVCTRL_INV0EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV0EN) & BM_FTM_INVCTRL_INV0EN)
05122 
05123 /*! @brief Set the INV0EN field to a new value. */
05124 #define BW_FTM_INVCTRL_INV0EN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV0EN), v))
05125 /*@}*/
05126 
05127 /*!
05128  * @name Register FTM_INVCTRL, field INV1EN[1] (RW)
05129  *
05130  * Values:
05131  * - 0 - Inverting is disabled.
05132  * - 1 - Inverting is enabled.
05133  */
05134 /*@{*/
05135 #define BP_FTM_INVCTRL_INV1EN (1U)         /*!< Bit position for FTM_INVCTRL_INV1EN. */
05136 #define BM_FTM_INVCTRL_INV1EN (0x00000002U) /*!< Bit mask for FTM_INVCTRL_INV1EN. */
05137 #define BS_FTM_INVCTRL_INV1EN (1U)         /*!< Bit field size in bits for FTM_INVCTRL_INV1EN. */
05138 
05139 /*! @brief Read current value of the FTM_INVCTRL_INV1EN field. */
05140 #define BR_FTM_INVCTRL_INV1EN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV1EN)))
05141 
05142 /*! @brief Format value for bitfield FTM_INVCTRL_INV1EN. */
05143 #define BF_FTM_INVCTRL_INV1EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV1EN) & BM_FTM_INVCTRL_INV1EN)
05144 
05145 /*! @brief Set the INV1EN field to a new value. */
05146 #define BW_FTM_INVCTRL_INV1EN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV1EN), v))
05147 /*@}*/
05148 
05149 /*!
05150  * @name Register FTM_INVCTRL, field INV2EN[2] (RW)
05151  *
05152  * Values:
05153  * - 0 - Inverting is disabled.
05154  * - 1 - Inverting is enabled.
05155  */
05156 /*@{*/
05157 #define BP_FTM_INVCTRL_INV2EN (2U)         /*!< Bit position for FTM_INVCTRL_INV2EN. */
05158 #define BM_FTM_INVCTRL_INV2EN (0x00000004U) /*!< Bit mask for FTM_INVCTRL_INV2EN. */
05159 #define BS_FTM_INVCTRL_INV2EN (1U)         /*!< Bit field size in bits for FTM_INVCTRL_INV2EN. */
05160 
05161 /*! @brief Read current value of the FTM_INVCTRL_INV2EN field. */
05162 #define BR_FTM_INVCTRL_INV2EN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV2EN)))
05163 
05164 /*! @brief Format value for bitfield FTM_INVCTRL_INV2EN. */
05165 #define BF_FTM_INVCTRL_INV2EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV2EN) & BM_FTM_INVCTRL_INV2EN)
05166 
05167 /*! @brief Set the INV2EN field to a new value. */
05168 #define BW_FTM_INVCTRL_INV2EN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV2EN), v))
05169 /*@}*/
05170 
05171 /*!
05172  * @name Register FTM_INVCTRL, field INV3EN[3] (RW)
05173  *
05174  * Values:
05175  * - 0 - Inverting is disabled.
05176  * - 1 - Inverting is enabled.
05177  */
05178 /*@{*/
05179 #define BP_FTM_INVCTRL_INV3EN (3U)         /*!< Bit position for FTM_INVCTRL_INV3EN. */
05180 #define BM_FTM_INVCTRL_INV3EN (0x00000008U) /*!< Bit mask for FTM_INVCTRL_INV3EN. */
05181 #define BS_FTM_INVCTRL_INV3EN (1U)         /*!< Bit field size in bits for FTM_INVCTRL_INV3EN. */
05182 
05183 /*! @brief Read current value of the FTM_INVCTRL_INV3EN field. */
05184 #define BR_FTM_INVCTRL_INV3EN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV3EN)))
05185 
05186 /*! @brief Format value for bitfield FTM_INVCTRL_INV3EN. */
05187 #define BF_FTM_INVCTRL_INV3EN(v) ((uint32_t)((uint32_t)(v) << BP_FTM_INVCTRL_INV3EN) & BM_FTM_INVCTRL_INV3EN)
05188 
05189 /*! @brief Set the INV3EN field to a new value. */
05190 #define BW_FTM_INVCTRL_INV3EN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_INVCTRL_ADDR(x), BP_FTM_INVCTRL_INV3EN), v))
05191 /*@}*/
05192 
05193 /*******************************************************************************
05194  * HW_FTM_SWOCTRL - FTM Software Output Control
05195  ******************************************************************************/
05196 
05197 /*!
05198  * @brief HW_FTM_SWOCTRL - FTM Software Output Control (RW)
05199  *
05200  * Reset value: 0x00000000U
05201  *
05202  * This register enables software control of channel (n) output and defines the
05203  * value forced to the channel (n) output: The CHnOC bits enable the control of
05204  * the corresponding channel (n) output by software. The CHnOCV bits select the
05205  * value that is forced at the corresponding channel (n) output. This register has
05206  * a write buffer. The fields are updated by the SWOCTRL register synchronization.
05207  */
05208 typedef union _hw_ftm_swoctrl
05209 {
05210     uint32_t U;
05211     struct _hw_ftm_swoctrl_bitfields
05212     {
05213         uint32_t CH0OC : 1;            /*!< [0] Channel 0 Software Output Control Enable
05214                                         * */
05215         uint32_t CH1OC : 1;            /*!< [1] Channel 1 Software Output Control Enable
05216                                         * */
05217         uint32_t CH2OC : 1;            /*!< [2] Channel 2 Software Output Control Enable
05218                                         * */
05219         uint32_t CH3OC : 1;            /*!< [3] Channel 3 Software Output Control Enable
05220                                         * */
05221         uint32_t CH4OC : 1;            /*!< [4] Channel 4 Software Output Control Enable
05222                                         * */
05223         uint32_t CH5OC : 1;            /*!< [5] Channel 5 Software Output Control Enable
05224                                         * */
05225         uint32_t CH6OC : 1;            /*!< [6] Channel 6 Software Output Control Enable
05226                                         * */
05227         uint32_t CH7OC : 1;            /*!< [7] Channel 7 Software Output Control Enable
05228                                         * */
05229         uint32_t CH0OCV : 1;           /*!< [8] Channel 0 Software Output Control Value
05230                                         * */
05231         uint32_t CH1OCV : 1;           /*!< [9] Channel 1 Software Output Control Value
05232                                         * */
05233         uint32_t CH2OCV : 1;           /*!< [10] Channel 2 Software Output Control
05234                                         * Value */
05235         uint32_t CH3OCV : 1;           /*!< [11] Channel 3 Software Output Control
05236                                         * Value */
05237         uint32_t CH4OCV : 1;           /*!< [12] Channel 4 Software Output Control
05238                                         * Value */
05239         uint32_t CH5OCV : 1;           /*!< [13] Channel 5 Software Output Control
05240                                         * Value */
05241         uint32_t CH6OCV : 1;           /*!< [14] Channel 6 Software Output Control
05242                                         * Value */
05243         uint32_t CH7OCV : 1;           /*!< [15] Channel 7 Software Output Control
05244                                         * Value */
05245         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05246     } B;
05247 } hw_ftm_swoctrl_t;
05248 
05249 /*!
05250  * @name Constants and macros for entire FTM_SWOCTRL register
05251  */
05252 /*@{*/
05253 #define HW_FTM_SWOCTRL_ADDR(x)   ((x) + 0x94U)
05254 
05255 #define HW_FTM_SWOCTRL(x)        (*(__IO hw_ftm_swoctrl_t *) HW_FTM_SWOCTRL_ADDR(x))
05256 #define HW_FTM_SWOCTRL_RD(x)     (ADDRESS_READ(hw_ftm_swoctrl_t, HW_FTM_SWOCTRL_ADDR(x)))
05257 #define HW_FTM_SWOCTRL_WR(x, v)  (ADDRESS_WRITE(hw_ftm_swoctrl_t, HW_FTM_SWOCTRL_ADDR(x), v))
05258 #define HW_FTM_SWOCTRL_SET(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) |  (v)))
05259 #define HW_FTM_SWOCTRL_CLR(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) & ~(v)))
05260 #define HW_FTM_SWOCTRL_TOG(x, v) (HW_FTM_SWOCTRL_WR(x, HW_FTM_SWOCTRL_RD(x) ^  (v)))
05261 /*@}*/
05262 
05263 /*
05264  * Constants & macros for individual FTM_SWOCTRL bitfields
05265  */
05266 
05267 /*!
05268  * @name Register FTM_SWOCTRL, field CH0OC[0] (RW)
05269  *
05270  * Values:
05271  * - 0 - The channel output is not affected by software output control.
05272  * - 1 - The channel output is affected by software output control.
05273  */
05274 /*@{*/
05275 #define BP_FTM_SWOCTRL_CH0OC (0U)          /*!< Bit position for FTM_SWOCTRL_CH0OC. */
05276 #define BM_FTM_SWOCTRL_CH0OC (0x00000001U) /*!< Bit mask for FTM_SWOCTRL_CH0OC. */
05277 #define BS_FTM_SWOCTRL_CH0OC (1U)          /*!< Bit field size in bits for FTM_SWOCTRL_CH0OC. */
05278 
05279 /*! @brief Read current value of the FTM_SWOCTRL_CH0OC field. */
05280 #define BR_FTM_SWOCTRL_CH0OC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OC)))
05281 
05282 /*! @brief Format value for bitfield FTM_SWOCTRL_CH0OC. */
05283 #define BF_FTM_SWOCTRL_CH0OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH0OC) & BM_FTM_SWOCTRL_CH0OC)
05284 
05285 /*! @brief Set the CH0OC field to a new value. */
05286 #define BW_FTM_SWOCTRL_CH0OC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OC), v))
05287 /*@}*/
05288 
05289 /*!
05290  * @name Register FTM_SWOCTRL, field CH1OC[1] (RW)
05291  *
05292  * Values:
05293  * - 0 - The channel output is not affected by software output control.
05294  * - 1 - The channel output is affected by software output control.
05295  */
05296 /*@{*/
05297 #define BP_FTM_SWOCTRL_CH1OC (1U)          /*!< Bit position for FTM_SWOCTRL_CH1OC. */
05298 #define BM_FTM_SWOCTRL_CH1OC (0x00000002U) /*!< Bit mask for FTM_SWOCTRL_CH1OC. */
05299 #define BS_FTM_SWOCTRL_CH1OC (1U)          /*!< Bit field size in bits for FTM_SWOCTRL_CH1OC. */
05300 
05301 /*! @brief Read current value of the FTM_SWOCTRL_CH1OC field. */
05302 #define BR_FTM_SWOCTRL_CH1OC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OC)))
05303 
05304 /*! @brief Format value for bitfield FTM_SWOCTRL_CH1OC. */
05305 #define BF_FTM_SWOCTRL_CH1OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH1OC) & BM_FTM_SWOCTRL_CH1OC)
05306 
05307 /*! @brief Set the CH1OC field to a new value. */
05308 #define BW_FTM_SWOCTRL_CH1OC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OC), v))
05309 /*@}*/
05310 
05311 /*!
05312  * @name Register FTM_SWOCTRL, field CH2OC[2] (RW)
05313  *
05314  * Values:
05315  * - 0 - The channel output is not affected by software output control.
05316  * - 1 - The channel output is affected by software output control.
05317  */
05318 /*@{*/
05319 #define BP_FTM_SWOCTRL_CH2OC (2U)          /*!< Bit position for FTM_SWOCTRL_CH2OC. */
05320 #define BM_FTM_SWOCTRL_CH2OC (0x00000004U) /*!< Bit mask for FTM_SWOCTRL_CH2OC. */
05321 #define BS_FTM_SWOCTRL_CH2OC (1U)          /*!< Bit field size in bits for FTM_SWOCTRL_CH2OC. */
05322 
05323 /*! @brief Read current value of the FTM_SWOCTRL_CH2OC field. */
05324 #define BR_FTM_SWOCTRL_CH2OC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OC)))
05325 
05326 /*! @brief Format value for bitfield FTM_SWOCTRL_CH2OC. */
05327 #define BF_FTM_SWOCTRL_CH2OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH2OC) & BM_FTM_SWOCTRL_CH2OC)
05328 
05329 /*! @brief Set the CH2OC field to a new value. */
05330 #define BW_FTM_SWOCTRL_CH2OC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OC), v))
05331 /*@}*/
05332 
05333 /*!
05334  * @name Register FTM_SWOCTRL, field CH3OC[3] (RW)
05335  *
05336  * Values:
05337  * - 0 - The channel output is not affected by software output control.
05338  * - 1 - The channel output is affected by software output control.
05339  */
05340 /*@{*/
05341 #define BP_FTM_SWOCTRL_CH3OC (3U)          /*!< Bit position for FTM_SWOCTRL_CH3OC. */
05342 #define BM_FTM_SWOCTRL_CH3OC (0x00000008U) /*!< Bit mask for FTM_SWOCTRL_CH3OC. */
05343 #define BS_FTM_SWOCTRL_CH3OC (1U)          /*!< Bit field size in bits for FTM_SWOCTRL_CH3OC. */
05344 
05345 /*! @brief Read current value of the FTM_SWOCTRL_CH3OC field. */
05346 #define BR_FTM_SWOCTRL_CH3OC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OC)))
05347 
05348 /*! @brief Format value for bitfield FTM_SWOCTRL_CH3OC. */
05349 #define BF_FTM_SWOCTRL_CH3OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH3OC) & BM_FTM_SWOCTRL_CH3OC)
05350 
05351 /*! @brief Set the CH3OC field to a new value. */
05352 #define BW_FTM_SWOCTRL_CH3OC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OC), v))
05353 /*@}*/
05354 
05355 /*!
05356  * @name Register FTM_SWOCTRL, field CH4OC[4] (RW)
05357  *
05358  * Values:
05359  * - 0 - The channel output is not affected by software output control.
05360  * - 1 - The channel output is affected by software output control.
05361  */
05362 /*@{*/
05363 #define BP_FTM_SWOCTRL_CH4OC (4U)          /*!< Bit position for FTM_SWOCTRL_CH4OC. */
05364 #define BM_FTM_SWOCTRL_CH4OC (0x00000010U) /*!< Bit mask for FTM_SWOCTRL_CH4OC. */
05365 #define BS_FTM_SWOCTRL_CH4OC (1U)          /*!< Bit field size in bits for FTM_SWOCTRL_CH4OC. */
05366 
05367 /*! @brief Read current value of the FTM_SWOCTRL_CH4OC field. */
05368 #define BR_FTM_SWOCTRL_CH4OC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OC)))
05369 
05370 /*! @brief Format value for bitfield FTM_SWOCTRL_CH4OC. */
05371 #define BF_FTM_SWOCTRL_CH4OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH4OC) & BM_FTM_SWOCTRL_CH4OC)
05372 
05373 /*! @brief Set the CH4OC field to a new value. */
05374 #define BW_FTM_SWOCTRL_CH4OC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OC), v))
05375 /*@}*/
05376 
05377 /*!
05378  * @name Register FTM_SWOCTRL, field CH5OC[5] (RW)
05379  *
05380  * Values:
05381  * - 0 - The channel output is not affected by software output control.
05382  * - 1 - The channel output is affected by software output control.
05383  */
05384 /*@{*/
05385 #define BP_FTM_SWOCTRL_CH5OC (5U)          /*!< Bit position for FTM_SWOCTRL_CH5OC. */
05386 #define BM_FTM_SWOCTRL_CH5OC (0x00000020U) /*!< Bit mask for FTM_SWOCTRL_CH5OC. */
05387 #define BS_FTM_SWOCTRL_CH5OC (1U)          /*!< Bit field size in bits for FTM_SWOCTRL_CH5OC. */
05388 
05389 /*! @brief Read current value of the FTM_SWOCTRL_CH5OC field. */
05390 #define BR_FTM_SWOCTRL_CH5OC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OC)))
05391 
05392 /*! @brief Format value for bitfield FTM_SWOCTRL_CH5OC. */
05393 #define BF_FTM_SWOCTRL_CH5OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH5OC) & BM_FTM_SWOCTRL_CH5OC)
05394 
05395 /*! @brief Set the CH5OC field to a new value. */
05396 #define BW_FTM_SWOCTRL_CH5OC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OC), v))
05397 /*@}*/
05398 
05399 /*!
05400  * @name Register FTM_SWOCTRL, field CH6OC[6] (RW)
05401  *
05402  * Values:
05403  * - 0 - The channel output is not affected by software output control.
05404  * - 1 - The channel output is affected by software output control.
05405  */
05406 /*@{*/
05407 #define BP_FTM_SWOCTRL_CH6OC (6U)          /*!< Bit position for FTM_SWOCTRL_CH6OC. */
05408 #define BM_FTM_SWOCTRL_CH6OC (0x00000040U) /*!< Bit mask for FTM_SWOCTRL_CH6OC. */
05409 #define BS_FTM_SWOCTRL_CH6OC (1U)          /*!< Bit field size in bits for FTM_SWOCTRL_CH6OC. */
05410 
05411 /*! @brief Read current value of the FTM_SWOCTRL_CH6OC field. */
05412 #define BR_FTM_SWOCTRL_CH6OC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OC)))
05413 
05414 /*! @brief Format value for bitfield FTM_SWOCTRL_CH6OC. */
05415 #define BF_FTM_SWOCTRL_CH6OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH6OC) & BM_FTM_SWOCTRL_CH6OC)
05416 
05417 /*! @brief Set the CH6OC field to a new value. */
05418 #define BW_FTM_SWOCTRL_CH6OC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OC), v))
05419 /*@}*/
05420 
05421 /*!
05422  * @name Register FTM_SWOCTRL, field CH7OC[7] (RW)
05423  *
05424  * Values:
05425  * - 0 - The channel output is not affected by software output control.
05426  * - 1 - The channel output is affected by software output control.
05427  */
05428 /*@{*/
05429 #define BP_FTM_SWOCTRL_CH7OC (7U)          /*!< Bit position for FTM_SWOCTRL_CH7OC. */
05430 #define BM_FTM_SWOCTRL_CH7OC (0x00000080U) /*!< Bit mask for FTM_SWOCTRL_CH7OC. */
05431 #define BS_FTM_SWOCTRL_CH7OC (1U)          /*!< Bit field size in bits for FTM_SWOCTRL_CH7OC. */
05432 
05433 /*! @brief Read current value of the FTM_SWOCTRL_CH7OC field. */
05434 #define BR_FTM_SWOCTRL_CH7OC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OC)))
05435 
05436 /*! @brief Format value for bitfield FTM_SWOCTRL_CH7OC. */
05437 #define BF_FTM_SWOCTRL_CH7OC(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH7OC) & BM_FTM_SWOCTRL_CH7OC)
05438 
05439 /*! @brief Set the CH7OC field to a new value. */
05440 #define BW_FTM_SWOCTRL_CH7OC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OC), v))
05441 /*@}*/
05442 
05443 /*!
05444  * @name Register FTM_SWOCTRL, field CH0OCV[8] (RW)
05445  *
05446  * Values:
05447  * - 0 - The software output control forces 0 to the channel output.
05448  * - 1 - The software output control forces 1 to the channel output.
05449  */
05450 /*@{*/
05451 #define BP_FTM_SWOCTRL_CH0OCV (8U)         /*!< Bit position for FTM_SWOCTRL_CH0OCV. */
05452 #define BM_FTM_SWOCTRL_CH0OCV (0x00000100U) /*!< Bit mask for FTM_SWOCTRL_CH0OCV. */
05453 #define BS_FTM_SWOCTRL_CH0OCV (1U)         /*!< Bit field size in bits for FTM_SWOCTRL_CH0OCV. */
05454 
05455 /*! @brief Read current value of the FTM_SWOCTRL_CH0OCV field. */
05456 #define BR_FTM_SWOCTRL_CH0OCV(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OCV)))
05457 
05458 /*! @brief Format value for bitfield FTM_SWOCTRL_CH0OCV. */
05459 #define BF_FTM_SWOCTRL_CH0OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH0OCV) & BM_FTM_SWOCTRL_CH0OCV)
05460 
05461 /*! @brief Set the CH0OCV field to a new value. */
05462 #define BW_FTM_SWOCTRL_CH0OCV(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH0OCV), v))
05463 /*@}*/
05464 
05465 /*!
05466  * @name Register FTM_SWOCTRL, field CH1OCV[9] (RW)
05467  *
05468  * Values:
05469  * - 0 - The software output control forces 0 to the channel output.
05470  * - 1 - The software output control forces 1 to the channel output.
05471  */
05472 /*@{*/
05473 #define BP_FTM_SWOCTRL_CH1OCV (9U)         /*!< Bit position for FTM_SWOCTRL_CH1OCV. */
05474 #define BM_FTM_SWOCTRL_CH1OCV (0x00000200U) /*!< Bit mask for FTM_SWOCTRL_CH1OCV. */
05475 #define BS_FTM_SWOCTRL_CH1OCV (1U)         /*!< Bit field size in bits for FTM_SWOCTRL_CH1OCV. */
05476 
05477 /*! @brief Read current value of the FTM_SWOCTRL_CH1OCV field. */
05478 #define BR_FTM_SWOCTRL_CH1OCV(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OCV)))
05479 
05480 /*! @brief Format value for bitfield FTM_SWOCTRL_CH1OCV. */
05481 #define BF_FTM_SWOCTRL_CH1OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH1OCV) & BM_FTM_SWOCTRL_CH1OCV)
05482 
05483 /*! @brief Set the CH1OCV field to a new value. */
05484 #define BW_FTM_SWOCTRL_CH1OCV(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH1OCV), v))
05485 /*@}*/
05486 
05487 /*!
05488  * @name Register FTM_SWOCTRL, field CH2OCV[10] (RW)
05489  *
05490  * Values:
05491  * - 0 - The software output control forces 0 to the channel output.
05492  * - 1 - The software output control forces 1 to the channel output.
05493  */
05494 /*@{*/
05495 #define BP_FTM_SWOCTRL_CH2OCV (10U)        /*!< Bit position for FTM_SWOCTRL_CH2OCV. */
05496 #define BM_FTM_SWOCTRL_CH2OCV (0x00000400U) /*!< Bit mask for FTM_SWOCTRL_CH2OCV. */
05497 #define BS_FTM_SWOCTRL_CH2OCV (1U)         /*!< Bit field size in bits for FTM_SWOCTRL_CH2OCV. */
05498 
05499 /*! @brief Read current value of the FTM_SWOCTRL_CH2OCV field. */
05500 #define BR_FTM_SWOCTRL_CH2OCV(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OCV)))
05501 
05502 /*! @brief Format value for bitfield FTM_SWOCTRL_CH2OCV. */
05503 #define BF_FTM_SWOCTRL_CH2OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH2OCV) & BM_FTM_SWOCTRL_CH2OCV)
05504 
05505 /*! @brief Set the CH2OCV field to a new value. */
05506 #define BW_FTM_SWOCTRL_CH2OCV(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH2OCV), v))
05507 /*@}*/
05508 
05509 /*!
05510  * @name Register FTM_SWOCTRL, field CH3OCV[11] (RW)
05511  *
05512  * Values:
05513  * - 0 - The software output control forces 0 to the channel output.
05514  * - 1 - The software output control forces 1 to the channel output.
05515  */
05516 /*@{*/
05517 #define BP_FTM_SWOCTRL_CH3OCV (11U)        /*!< Bit position for FTM_SWOCTRL_CH3OCV. */
05518 #define BM_FTM_SWOCTRL_CH3OCV (0x00000800U) /*!< Bit mask for FTM_SWOCTRL_CH3OCV. */
05519 #define BS_FTM_SWOCTRL_CH3OCV (1U)         /*!< Bit field size in bits for FTM_SWOCTRL_CH3OCV. */
05520 
05521 /*! @brief Read current value of the FTM_SWOCTRL_CH3OCV field. */
05522 #define BR_FTM_SWOCTRL_CH3OCV(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OCV)))
05523 
05524 /*! @brief Format value for bitfield FTM_SWOCTRL_CH3OCV. */
05525 #define BF_FTM_SWOCTRL_CH3OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH3OCV) & BM_FTM_SWOCTRL_CH3OCV)
05526 
05527 /*! @brief Set the CH3OCV field to a new value. */
05528 #define BW_FTM_SWOCTRL_CH3OCV(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH3OCV), v))
05529 /*@}*/
05530 
05531 /*!
05532  * @name Register FTM_SWOCTRL, field CH4OCV[12] (RW)
05533  *
05534  * Values:
05535  * - 0 - The software output control forces 0 to the channel output.
05536  * - 1 - The software output control forces 1 to the channel output.
05537  */
05538 /*@{*/
05539 #define BP_FTM_SWOCTRL_CH4OCV (12U)        /*!< Bit position for FTM_SWOCTRL_CH4OCV. */
05540 #define BM_FTM_SWOCTRL_CH4OCV (0x00001000U) /*!< Bit mask for FTM_SWOCTRL_CH4OCV. */
05541 #define BS_FTM_SWOCTRL_CH4OCV (1U)         /*!< Bit field size in bits for FTM_SWOCTRL_CH4OCV. */
05542 
05543 /*! @brief Read current value of the FTM_SWOCTRL_CH4OCV field. */
05544 #define BR_FTM_SWOCTRL_CH4OCV(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OCV)))
05545 
05546 /*! @brief Format value for bitfield FTM_SWOCTRL_CH4OCV. */
05547 #define BF_FTM_SWOCTRL_CH4OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH4OCV) & BM_FTM_SWOCTRL_CH4OCV)
05548 
05549 /*! @brief Set the CH4OCV field to a new value. */
05550 #define BW_FTM_SWOCTRL_CH4OCV(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH4OCV), v))
05551 /*@}*/
05552 
05553 /*!
05554  * @name Register FTM_SWOCTRL, field CH5OCV[13] (RW)
05555  *
05556  * Values:
05557  * - 0 - The software output control forces 0 to the channel output.
05558  * - 1 - The software output control forces 1 to the channel output.
05559  */
05560 /*@{*/
05561 #define BP_FTM_SWOCTRL_CH5OCV (13U)        /*!< Bit position for FTM_SWOCTRL_CH5OCV. */
05562 #define BM_FTM_SWOCTRL_CH5OCV (0x00002000U) /*!< Bit mask for FTM_SWOCTRL_CH5OCV. */
05563 #define BS_FTM_SWOCTRL_CH5OCV (1U)         /*!< Bit field size in bits for FTM_SWOCTRL_CH5OCV. */
05564 
05565 /*! @brief Read current value of the FTM_SWOCTRL_CH5OCV field. */
05566 #define BR_FTM_SWOCTRL_CH5OCV(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OCV)))
05567 
05568 /*! @brief Format value for bitfield FTM_SWOCTRL_CH5OCV. */
05569 #define BF_FTM_SWOCTRL_CH5OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH5OCV) & BM_FTM_SWOCTRL_CH5OCV)
05570 
05571 /*! @brief Set the CH5OCV field to a new value. */
05572 #define BW_FTM_SWOCTRL_CH5OCV(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH5OCV), v))
05573 /*@}*/
05574 
05575 /*!
05576  * @name Register FTM_SWOCTRL, field CH6OCV[14] (RW)
05577  *
05578  * Values:
05579  * - 0 - The software output control forces 0 to the channel output.
05580  * - 1 - The software output control forces 1 to the channel output.
05581  */
05582 /*@{*/
05583 #define BP_FTM_SWOCTRL_CH6OCV (14U)        /*!< Bit position for FTM_SWOCTRL_CH6OCV. */
05584 #define BM_FTM_SWOCTRL_CH6OCV (0x00004000U) /*!< Bit mask for FTM_SWOCTRL_CH6OCV. */
05585 #define BS_FTM_SWOCTRL_CH6OCV (1U)         /*!< Bit field size in bits for FTM_SWOCTRL_CH6OCV. */
05586 
05587 /*! @brief Read current value of the FTM_SWOCTRL_CH6OCV field. */
05588 #define BR_FTM_SWOCTRL_CH6OCV(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OCV)))
05589 
05590 /*! @brief Format value for bitfield FTM_SWOCTRL_CH6OCV. */
05591 #define BF_FTM_SWOCTRL_CH6OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH6OCV) & BM_FTM_SWOCTRL_CH6OCV)
05592 
05593 /*! @brief Set the CH6OCV field to a new value. */
05594 #define BW_FTM_SWOCTRL_CH6OCV(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH6OCV), v))
05595 /*@}*/
05596 
05597 /*!
05598  * @name Register FTM_SWOCTRL, field CH7OCV[15] (RW)
05599  *
05600  * Values:
05601  * - 0 - The software output control forces 0 to the channel output.
05602  * - 1 - The software output control forces 1 to the channel output.
05603  */
05604 /*@{*/
05605 #define BP_FTM_SWOCTRL_CH7OCV (15U)        /*!< Bit position for FTM_SWOCTRL_CH7OCV. */
05606 #define BM_FTM_SWOCTRL_CH7OCV (0x00008000U) /*!< Bit mask for FTM_SWOCTRL_CH7OCV. */
05607 #define BS_FTM_SWOCTRL_CH7OCV (1U)         /*!< Bit field size in bits for FTM_SWOCTRL_CH7OCV. */
05608 
05609 /*! @brief Read current value of the FTM_SWOCTRL_CH7OCV field. */
05610 #define BR_FTM_SWOCTRL_CH7OCV(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OCV)))
05611 
05612 /*! @brief Format value for bitfield FTM_SWOCTRL_CH7OCV. */
05613 #define BF_FTM_SWOCTRL_CH7OCV(v) ((uint32_t)((uint32_t)(v) << BP_FTM_SWOCTRL_CH7OCV) & BM_FTM_SWOCTRL_CH7OCV)
05614 
05615 /*! @brief Set the CH7OCV field to a new value. */
05616 #define BW_FTM_SWOCTRL_CH7OCV(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_SWOCTRL_ADDR(x), BP_FTM_SWOCTRL_CH7OCV), v))
05617 /*@}*/
05618 
05619 /*******************************************************************************
05620  * HW_FTM_PWMLOAD - FTM PWM Load
05621  ******************************************************************************/
05622 
05623 /*!
05624  * @brief HW_FTM_PWMLOAD - FTM PWM Load (RW)
05625  *
05626  * Reset value: 0x00000000U
05627  *
05628  * Enables the loading of the MOD, CNTIN, C(n)V, and C(n+1)V registers with the
05629  * values of their write buffers when the FTM counter changes from the MOD
05630  * register value to its next value or when a channel (j) match occurs. A match occurs
05631  * for the channel (j) when FTM counter = C(j)V.
05632  */
05633 typedef union _hw_ftm_pwmload
05634 {
05635     uint32_t U;
05636     struct _hw_ftm_pwmload_bitfields
05637     {
05638         uint32_t CH0SEL : 1;           /*!< [0] Channel 0 Select */
05639         uint32_t CH1SEL : 1;           /*!< [1] Channel 1 Select */
05640         uint32_t CH2SEL : 1;           /*!< [2] Channel 2 Select */
05641         uint32_t CH3SEL : 1;           /*!< [3] Channel 3 Select */
05642         uint32_t CH4SEL : 1;           /*!< [4] Channel 4 Select */
05643         uint32_t CH5SEL : 1;           /*!< [5] Channel 5 Select */
05644         uint32_t CH6SEL : 1;           /*!< [6] Channel 6 Select */
05645         uint32_t CH7SEL : 1;           /*!< [7] Channel 7 Select */
05646         uint32_t RESERVED0 : 1;        /*!< [8]  */
05647         uint32_t LDOK : 1;             /*!< [9] Load Enable */
05648         uint32_t RESERVED1 : 22;       /*!< [31:10]  */
05649     } B;
05650 } hw_ftm_pwmload_t;
05651 
05652 /*!
05653  * @name Constants and macros for entire FTM_PWMLOAD register
05654  */
05655 /*@{*/
05656 #define HW_FTM_PWMLOAD_ADDR(x)   ((x) + 0x98U)
05657 
05658 #define HW_FTM_PWMLOAD(x)        (*(__IO hw_ftm_pwmload_t *) HW_FTM_PWMLOAD_ADDR(x))
05659 #define HW_FTM_PWMLOAD_RD(x)     (ADDRESS_READ(hw_ftm_pwmload_t, HW_FTM_PWMLOAD_ADDR(x)))
05660 #define HW_FTM_PWMLOAD_WR(x, v)  (ADDRESS_WRITE(hw_ftm_pwmload_t, HW_FTM_PWMLOAD_ADDR(x), v))
05661 #define HW_FTM_PWMLOAD_SET(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) |  (v)))
05662 #define HW_FTM_PWMLOAD_CLR(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) & ~(v)))
05663 #define HW_FTM_PWMLOAD_TOG(x, v) (HW_FTM_PWMLOAD_WR(x, HW_FTM_PWMLOAD_RD(x) ^  (v)))
05664 /*@}*/
05665 
05666 /*
05667  * Constants & macros for individual FTM_PWMLOAD bitfields
05668  */
05669 
05670 /*!
05671  * @name Register FTM_PWMLOAD, field CH0SEL[0] (RW)
05672  *
05673  * Values:
05674  * - 0 - Do not include the channel in the matching process.
05675  * - 1 - Include the channel in the matching process.
05676  */
05677 /*@{*/
05678 #define BP_FTM_PWMLOAD_CH0SEL (0U)         /*!< Bit position for FTM_PWMLOAD_CH0SEL. */
05679 #define BM_FTM_PWMLOAD_CH0SEL (0x00000001U) /*!< Bit mask for FTM_PWMLOAD_CH0SEL. */
05680 #define BS_FTM_PWMLOAD_CH0SEL (1U)         /*!< Bit field size in bits for FTM_PWMLOAD_CH0SEL. */
05681 
05682 /*! @brief Read current value of the FTM_PWMLOAD_CH0SEL field. */
05683 #define BR_FTM_PWMLOAD_CH0SEL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH0SEL)))
05684 
05685 /*! @brief Format value for bitfield FTM_PWMLOAD_CH0SEL. */
05686 #define BF_FTM_PWMLOAD_CH0SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH0SEL) & BM_FTM_PWMLOAD_CH0SEL)
05687 
05688 /*! @brief Set the CH0SEL field to a new value. */
05689 #define BW_FTM_PWMLOAD_CH0SEL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH0SEL), v))
05690 /*@}*/
05691 
05692 /*!
05693  * @name Register FTM_PWMLOAD, field CH1SEL[1] (RW)
05694  *
05695  * Values:
05696  * - 0 - Do not include the channel in the matching process.
05697  * - 1 - Include the channel in the matching process.
05698  */
05699 /*@{*/
05700 #define BP_FTM_PWMLOAD_CH1SEL (1U)         /*!< Bit position for FTM_PWMLOAD_CH1SEL. */
05701 #define BM_FTM_PWMLOAD_CH1SEL (0x00000002U) /*!< Bit mask for FTM_PWMLOAD_CH1SEL. */
05702 #define BS_FTM_PWMLOAD_CH1SEL (1U)         /*!< Bit field size in bits for FTM_PWMLOAD_CH1SEL. */
05703 
05704 /*! @brief Read current value of the FTM_PWMLOAD_CH1SEL field. */
05705 #define BR_FTM_PWMLOAD_CH1SEL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH1SEL)))
05706 
05707 /*! @brief Format value for bitfield FTM_PWMLOAD_CH1SEL. */
05708 #define BF_FTM_PWMLOAD_CH1SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH1SEL) & BM_FTM_PWMLOAD_CH1SEL)
05709 
05710 /*! @brief Set the CH1SEL field to a new value. */
05711 #define BW_FTM_PWMLOAD_CH1SEL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH1SEL), v))
05712 /*@}*/
05713 
05714 /*!
05715  * @name Register FTM_PWMLOAD, field CH2SEL[2] (RW)
05716  *
05717  * Values:
05718  * - 0 - Do not include the channel in the matching process.
05719  * - 1 - Include the channel in the matching process.
05720  */
05721 /*@{*/
05722 #define BP_FTM_PWMLOAD_CH2SEL (2U)         /*!< Bit position for FTM_PWMLOAD_CH2SEL. */
05723 #define BM_FTM_PWMLOAD_CH2SEL (0x00000004U) /*!< Bit mask for FTM_PWMLOAD_CH2SEL. */
05724 #define BS_FTM_PWMLOAD_CH2SEL (1U)         /*!< Bit field size in bits for FTM_PWMLOAD_CH2SEL. */
05725 
05726 /*! @brief Read current value of the FTM_PWMLOAD_CH2SEL field. */
05727 #define BR_FTM_PWMLOAD_CH2SEL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH2SEL)))
05728 
05729 /*! @brief Format value for bitfield FTM_PWMLOAD_CH2SEL. */
05730 #define BF_FTM_PWMLOAD_CH2SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH2SEL) & BM_FTM_PWMLOAD_CH2SEL)
05731 
05732 /*! @brief Set the CH2SEL field to a new value. */
05733 #define BW_FTM_PWMLOAD_CH2SEL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH2SEL), v))
05734 /*@}*/
05735 
05736 /*!
05737  * @name Register FTM_PWMLOAD, field CH3SEL[3] (RW)
05738  *
05739  * Values:
05740  * - 0 - Do not include the channel in the matching process.
05741  * - 1 - Include the channel in the matching process.
05742  */
05743 /*@{*/
05744 #define BP_FTM_PWMLOAD_CH3SEL (3U)         /*!< Bit position for FTM_PWMLOAD_CH3SEL. */
05745 #define BM_FTM_PWMLOAD_CH3SEL (0x00000008U) /*!< Bit mask for FTM_PWMLOAD_CH3SEL. */
05746 #define BS_FTM_PWMLOAD_CH3SEL (1U)         /*!< Bit field size in bits for FTM_PWMLOAD_CH3SEL. */
05747 
05748 /*! @brief Read current value of the FTM_PWMLOAD_CH3SEL field. */
05749 #define BR_FTM_PWMLOAD_CH3SEL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH3SEL)))
05750 
05751 /*! @brief Format value for bitfield FTM_PWMLOAD_CH3SEL. */
05752 #define BF_FTM_PWMLOAD_CH3SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH3SEL) & BM_FTM_PWMLOAD_CH3SEL)
05753 
05754 /*! @brief Set the CH3SEL field to a new value. */
05755 #define BW_FTM_PWMLOAD_CH3SEL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH3SEL), v))
05756 /*@}*/
05757 
05758 /*!
05759  * @name Register FTM_PWMLOAD, field CH4SEL[4] (RW)
05760  *
05761  * Values:
05762  * - 0 - Do not include the channel in the matching process.
05763  * - 1 - Include the channel in the matching process.
05764  */
05765 /*@{*/
05766 #define BP_FTM_PWMLOAD_CH4SEL (4U)         /*!< Bit position for FTM_PWMLOAD_CH4SEL. */
05767 #define BM_FTM_PWMLOAD_CH4SEL (0x00000010U) /*!< Bit mask for FTM_PWMLOAD_CH4SEL. */
05768 #define BS_FTM_PWMLOAD_CH4SEL (1U)         /*!< Bit field size in bits for FTM_PWMLOAD_CH4SEL. */
05769 
05770 /*! @brief Read current value of the FTM_PWMLOAD_CH4SEL field. */
05771 #define BR_FTM_PWMLOAD_CH4SEL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH4SEL)))
05772 
05773 /*! @brief Format value for bitfield FTM_PWMLOAD_CH4SEL. */
05774 #define BF_FTM_PWMLOAD_CH4SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH4SEL) & BM_FTM_PWMLOAD_CH4SEL)
05775 
05776 /*! @brief Set the CH4SEL field to a new value. */
05777 #define BW_FTM_PWMLOAD_CH4SEL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH4SEL), v))
05778 /*@}*/
05779 
05780 /*!
05781  * @name Register FTM_PWMLOAD, field CH5SEL[5] (RW)
05782  *
05783  * Values:
05784  * - 0 - Do not include the channel in the matching process.
05785  * - 1 - Include the channel in the matching process.
05786  */
05787 /*@{*/
05788 #define BP_FTM_PWMLOAD_CH5SEL (5U)         /*!< Bit position for FTM_PWMLOAD_CH5SEL. */
05789 #define BM_FTM_PWMLOAD_CH5SEL (0x00000020U) /*!< Bit mask for FTM_PWMLOAD_CH5SEL. */
05790 #define BS_FTM_PWMLOAD_CH5SEL (1U)         /*!< Bit field size in bits for FTM_PWMLOAD_CH5SEL. */
05791 
05792 /*! @brief Read current value of the FTM_PWMLOAD_CH5SEL field. */
05793 #define BR_FTM_PWMLOAD_CH5SEL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH5SEL)))
05794 
05795 /*! @brief Format value for bitfield FTM_PWMLOAD_CH5SEL. */
05796 #define BF_FTM_PWMLOAD_CH5SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH5SEL) & BM_FTM_PWMLOAD_CH5SEL)
05797 
05798 /*! @brief Set the CH5SEL field to a new value. */
05799 #define BW_FTM_PWMLOAD_CH5SEL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH5SEL), v))
05800 /*@}*/
05801 
05802 /*!
05803  * @name Register FTM_PWMLOAD, field CH6SEL[6] (RW)
05804  *
05805  * Values:
05806  * - 0 - Do not include the channel in the matching process.
05807  * - 1 - Include the channel in the matching process.
05808  */
05809 /*@{*/
05810 #define BP_FTM_PWMLOAD_CH6SEL (6U)         /*!< Bit position for FTM_PWMLOAD_CH6SEL. */
05811 #define BM_FTM_PWMLOAD_CH6SEL (0x00000040U) /*!< Bit mask for FTM_PWMLOAD_CH6SEL. */
05812 #define BS_FTM_PWMLOAD_CH6SEL (1U)         /*!< Bit field size in bits for FTM_PWMLOAD_CH6SEL. */
05813 
05814 /*! @brief Read current value of the FTM_PWMLOAD_CH6SEL field. */
05815 #define BR_FTM_PWMLOAD_CH6SEL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH6SEL)))
05816 
05817 /*! @brief Format value for bitfield FTM_PWMLOAD_CH6SEL. */
05818 #define BF_FTM_PWMLOAD_CH6SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH6SEL) & BM_FTM_PWMLOAD_CH6SEL)
05819 
05820 /*! @brief Set the CH6SEL field to a new value. */
05821 #define BW_FTM_PWMLOAD_CH6SEL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH6SEL), v))
05822 /*@}*/
05823 
05824 /*!
05825  * @name Register FTM_PWMLOAD, field CH7SEL[7] (RW)
05826  *
05827  * Values:
05828  * - 0 - Do not include the channel in the matching process.
05829  * - 1 - Include the channel in the matching process.
05830  */
05831 /*@{*/
05832 #define BP_FTM_PWMLOAD_CH7SEL (7U)         /*!< Bit position for FTM_PWMLOAD_CH7SEL. */
05833 #define BM_FTM_PWMLOAD_CH7SEL (0x00000080U) /*!< Bit mask for FTM_PWMLOAD_CH7SEL. */
05834 #define BS_FTM_PWMLOAD_CH7SEL (1U)         /*!< Bit field size in bits for FTM_PWMLOAD_CH7SEL. */
05835 
05836 /*! @brief Read current value of the FTM_PWMLOAD_CH7SEL field. */
05837 #define BR_FTM_PWMLOAD_CH7SEL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH7SEL)))
05838 
05839 /*! @brief Format value for bitfield FTM_PWMLOAD_CH7SEL. */
05840 #define BF_FTM_PWMLOAD_CH7SEL(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_CH7SEL) & BM_FTM_PWMLOAD_CH7SEL)
05841 
05842 /*! @brief Set the CH7SEL field to a new value. */
05843 #define BW_FTM_PWMLOAD_CH7SEL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_CH7SEL), v))
05844 /*@}*/
05845 
05846 /*!
05847  * @name Register FTM_PWMLOAD, field LDOK[9] (RW)
05848  *
05849  * Enables the loading of the MOD, CNTIN, and CV registers with the values of
05850  * their write buffers.
05851  *
05852  * Values:
05853  * - 0 - Loading updated values is disabled.
05854  * - 1 - Loading updated values is enabled.
05855  */
05856 /*@{*/
05857 #define BP_FTM_PWMLOAD_LDOK  (9U)          /*!< Bit position for FTM_PWMLOAD_LDOK. */
05858 #define BM_FTM_PWMLOAD_LDOK  (0x00000200U) /*!< Bit mask for FTM_PWMLOAD_LDOK. */
05859 #define BS_FTM_PWMLOAD_LDOK  (1U)          /*!< Bit field size in bits for FTM_PWMLOAD_LDOK. */
05860 
05861 /*! @brief Read current value of the FTM_PWMLOAD_LDOK field. */
05862 #define BR_FTM_PWMLOAD_LDOK(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_LDOK)))
05863 
05864 /*! @brief Format value for bitfield FTM_PWMLOAD_LDOK. */
05865 #define BF_FTM_PWMLOAD_LDOK(v) ((uint32_t)((uint32_t)(v) << BP_FTM_PWMLOAD_LDOK) & BM_FTM_PWMLOAD_LDOK)
05866 
05867 /*! @brief Set the LDOK field to a new value. */
05868 #define BW_FTM_PWMLOAD_LDOK(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_FTM_PWMLOAD_ADDR(x), BP_FTM_PWMLOAD_LDOK), v))
05869 /*@}*/
05870 
05871 /*******************************************************************************
05872  * hw_ftm_t - module struct
05873  ******************************************************************************/
05874 /*!
05875  * @brief All FTM module registers.
05876  */
05877 #pragma pack(1)
05878 typedef struct _hw_ftm
05879 {
05880     __IO hw_ftm_sc_t SC ;                   /*!< [0x0] Status And Control */
05881     __IO hw_ftm_cnt_t CNT ;                 /*!< [0x4] Counter */
05882     __IO hw_ftm_mod_t MOD ;                 /*!< [0x8] Modulo */
05883     struct {
05884         __IO hw_ftm_cnsc_t CnSC ;           /*!< [0xC] Channel (n) Status And Control */
05885         __IO hw_ftm_cnv_t CnV ;             /*!< [0x10] Channel (n) Value */
05886     } CONTROLS[8];
05887     __IO hw_ftm_cntin_t CNTIN ;             /*!< [0x4C] Counter Initial Value */
05888     __IO hw_ftm_status_t STATUS ;           /*!< [0x50] Capture And Compare Status */
05889     __IO hw_ftm_mode_t MODE ;               /*!< [0x54] Features Mode Selection */
05890     __IO hw_ftm_sync_t SYNC ;               /*!< [0x58] Synchronization */
05891     __IO hw_ftm_outinit_t OUTINIT ;         /*!< [0x5C] Initial State For Channels Output */
05892     __IO hw_ftm_outmask_t OUTMASK ;         /*!< [0x60] Output Mask */
05893     __IO hw_ftm_combine_t COMBINE ;         /*!< [0x64] Function For Linked Channels */
05894     __IO hw_ftm_deadtime_t DEADTIME ;       /*!< [0x68] Deadtime Insertion Control */
05895     __IO hw_ftm_exttrig_t EXTTRIG ;         /*!< [0x6C] FTM External Trigger */
05896     __IO hw_ftm_pol_t POL ;                 /*!< [0x70] Channels Polarity */
05897     __IO hw_ftm_fms_t FMS ;                 /*!< [0x74] Fault Mode Status */
05898     __IO hw_ftm_filter_t FILTER ;           /*!< [0x78] Input Capture Filter Control */
05899     __IO hw_ftm_fltctrl_t FLTCTRL ;         /*!< [0x7C] Fault Control */
05900     __IO hw_ftm_qdctrl_t QDCTRL ;           /*!< [0x80] Quadrature Decoder Control And Status */
05901     __IO hw_ftm_conf_t CONF ;               /*!< [0x84] Configuration */
05902     __IO hw_ftm_fltpol_t FLTPOL ;           /*!< [0x88] FTM Fault Input Polarity */
05903     __IO hw_ftm_synconf_t SYNCONF ;         /*!< [0x8C] Synchronization Configuration */
05904     __IO hw_ftm_invctrl_t INVCTRL ;         /*!< [0x90] FTM Inverting Control */
05905     __IO hw_ftm_swoctrl_t SWOCTRL ;         /*!< [0x94] FTM Software Output Control */
05906     __IO hw_ftm_pwmload_t PWMLOAD ;         /*!< [0x98] FTM PWM Load */
05907 } hw_ftm_t;
05908 #pragma pack()
05909 
05910 /*! @brief Macro to access all FTM registers. */
05911 /*! @param x FTM module instance base address. */
05912 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
05913  *     use the '&' operator, like <code>&HW_FTM(FTM0_BASE)</code>. */
05914 #define HW_FTM(x)      (*(hw_ftm_t *)(x))
05915 
05916 #endif /* __HW_FTM_REGISTERS_H__ */
05917 /* EOF */