MK64F12_ftfe.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_FTFE_REGISTERS_H__
00088 #define __HW_FTFE_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 FTFE
00095  *
00096  * Flash Memory Interface
00097  *
00098  * Registers defined in this header file:
00099  * - HW_FTFE_FSTAT - Flash Status Register
00100  * - HW_FTFE_FCNFG - Flash Configuration Register
00101  * - HW_FTFE_FSEC - Flash Security Register
00102  * - HW_FTFE_FOPT - Flash Option Register
00103  * - HW_FTFE_FCCOB3 - Flash Common Command Object Registers
00104  * - HW_FTFE_FCCOB2 - Flash Common Command Object Registers
00105  * - HW_FTFE_FCCOB1 - Flash Common Command Object Registers
00106  * - HW_FTFE_FCCOB0 - Flash Common Command Object Registers
00107  * - HW_FTFE_FCCOB7 - Flash Common Command Object Registers
00108  * - HW_FTFE_FCCOB6 - Flash Common Command Object Registers
00109  * - HW_FTFE_FCCOB5 - Flash Common Command Object Registers
00110  * - HW_FTFE_FCCOB4 - Flash Common Command Object Registers
00111  * - HW_FTFE_FCCOBB - Flash Common Command Object Registers
00112  * - HW_FTFE_FCCOBA - Flash Common Command Object Registers
00113  * - HW_FTFE_FCCOB9 - Flash Common Command Object Registers
00114  * - HW_FTFE_FCCOB8 - Flash Common Command Object Registers
00115  * - HW_FTFE_FPROT3 - Program Flash Protection Registers
00116  * - HW_FTFE_FPROT2 - Program Flash Protection Registers
00117  * - HW_FTFE_FPROT1 - Program Flash Protection Registers
00118  * - HW_FTFE_FPROT0 - Program Flash Protection Registers
00119  * - HW_FTFE_FEPROT - EEPROM Protection Register
00120  * - HW_FTFE_FDPROT - Data Flash Protection Register
00121  *
00122  * - hw_ftfe_t - Struct containing all module registers.
00123  */
00124 
00125 #define HW_FTFE_INSTANCE_COUNT (1U) /*!< Number of instances of the FTFE module. */
00126 
00127 /*******************************************************************************
00128  * HW_FTFE_FSTAT - Flash Status Register
00129  ******************************************************************************/
00130 
00131 /*!
00132  * @brief HW_FTFE_FSTAT - Flash Status Register (RW)
00133  *
00134  * Reset value: 0x00U
00135  *
00136  * The FSTAT register reports the operational status of the FTFE module. The
00137  * CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The MGSTAT0
00138  * bit is read only. The unassigned bits read 0 and are not writable. When set, the
00139  * Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in this
00140  * register prevent the launch of any more commands or writes to the FlexRAM (when
00141  * EEERDY is set) until the flag is cleared (by writing a one to it).
00142  */
00143 typedef union _hw_ftfe_fstat
00144 {
00145     uint8_t U;
00146     struct _hw_ftfe_fstat_bitfields
00147     {
00148         uint8_t MGSTAT0 : 1;           /*!< [0] Memory Controller Command Completion
00149                                         * Status Flag */
00150         uint8_t RESERVED0 : 3;         /*!< [3:1]  */
00151         uint8_t FPVIOL : 1;            /*!< [4] Flash Protection Violation Flag */
00152         uint8_t ACCERR : 1;            /*!< [5] Flash Access Error Flag */
00153         uint8_t RDCOLERR : 1;          /*!< [6] FTFE Read Collision Error Flag */
00154         uint8_t CCIF : 1;              /*!< [7] Command Complete Interrupt Flag */
00155     } B;
00156 } hw_ftfe_fstat_t;
00157 
00158 /*!
00159  * @name Constants and macros for entire FTFE_FSTAT register
00160  */
00161 /*@{*/
00162 #define HW_FTFE_FSTAT_ADDR(x)    ((x) + 0x0U)
00163 
00164 #define HW_FTFE_FSTAT(x)         (*(__IO hw_ftfe_fstat_t *) HW_FTFE_FSTAT_ADDR(x))
00165 #define HW_FTFE_FSTAT_RD(x)      (ADDRESS_READ(hw_ftfe_fstat_t, HW_FTFE_FSTAT_ADDR(x)))
00166 #define HW_FTFE_FSTAT_WR(x, v)   (ADDRESS_WRITE(hw_ftfe_fstat_t, HW_FTFE_FSTAT_ADDR(x), v))
00167 #define HW_FTFE_FSTAT_SET(x, v)  (HW_FTFE_FSTAT_WR(x, HW_FTFE_FSTAT_RD(x) |  (v)))
00168 #define HW_FTFE_FSTAT_CLR(x, v)  (HW_FTFE_FSTAT_WR(x, HW_FTFE_FSTAT_RD(x) & ~(v)))
00169 #define HW_FTFE_FSTAT_TOG(x, v)  (HW_FTFE_FSTAT_WR(x, HW_FTFE_FSTAT_RD(x) ^  (v)))
00170 /*@}*/
00171 
00172 /*
00173  * Constants & macros for individual FTFE_FSTAT bitfields
00174  */
00175 
00176 /*!
00177  * @name Register FTFE_FSTAT, field MGSTAT0[0] (RO)
00178  *
00179  * The MGSTAT0 status flag is set if an error is detected during execution of an
00180  * FTFE command or during the flash reset sequence. As a status flag, this bit
00181  * cannot (and need not) be cleared by the user like the other error flags in this
00182  * register. The value of the MGSTAT0 bit for "command-N" is valid only at the
00183  * end of the "command-N" execution when CCIF=1 and before the next command has
00184  * been launched. At some point during the execution of "command-N+1," the previous
00185  * result is discarded and any previous error is cleared.
00186  */
00187 /*@{*/
00188 #define BP_FTFE_FSTAT_MGSTAT0 (0U)         /*!< Bit position for FTFE_FSTAT_MGSTAT0. */
00189 #define BM_FTFE_FSTAT_MGSTAT0 (0x01U)      /*!< Bit mask for FTFE_FSTAT_MGSTAT0. */
00190 #define BS_FTFE_FSTAT_MGSTAT0 (1U)         /*!< Bit field size in bits for FTFE_FSTAT_MGSTAT0. */
00191 
00192 /*! @brief Read current value of the FTFE_FSTAT_MGSTAT0 field. */
00193 #define BR_FTFE_FSTAT_MGSTAT0(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_MGSTAT0)))
00194 /*@}*/
00195 
00196 /*!
00197  * @name Register FTFE_FSTAT, field FPVIOL[4] (W1C)
00198  *
00199  * The FPVIOL error bit indicates an attempt was made to program or erase an
00200  * address in a protected area of program flash or data flash memory during a
00201  * command write sequence or a write was attempted to a protected area of the FlexRAM
00202  * while enabled for EEPROM. While FPVIOL is set, the CCIF flag cannot be cleared
00203  * to launch a command. The FPVIOL bit is cleared by writing a 1 to it. Writing a
00204  * 0 to the FPVIOL bit has no effect.
00205  *
00206  * Values:
00207  * - 0 - No protection violation detected
00208  * - 1 - Protection violation detected
00209  */
00210 /*@{*/
00211 #define BP_FTFE_FSTAT_FPVIOL (4U)          /*!< Bit position for FTFE_FSTAT_FPVIOL. */
00212 #define BM_FTFE_FSTAT_FPVIOL (0x10U)       /*!< Bit mask for FTFE_FSTAT_FPVIOL. */
00213 #define BS_FTFE_FSTAT_FPVIOL (1U)          /*!< Bit field size in bits for FTFE_FSTAT_FPVIOL. */
00214 
00215 /*! @brief Read current value of the FTFE_FSTAT_FPVIOL field. */
00216 #define BR_FTFE_FSTAT_FPVIOL(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_FPVIOL)))
00217 
00218 /*! @brief Format value for bitfield FTFE_FSTAT_FPVIOL. */
00219 #define BF_FTFE_FSTAT_FPVIOL(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FSTAT_FPVIOL) & BM_FTFE_FSTAT_FPVIOL)
00220 
00221 /*! @brief Set the FPVIOL field to a new value. */
00222 #define BW_FTFE_FSTAT_FPVIOL(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_FPVIOL), v))
00223 /*@}*/
00224 
00225 /*!
00226  * @name Register FTFE_FSTAT, field ACCERR[5] (W1C)
00227  *
00228  * The ACCERR error bit indicates an illegal access has occurred to an FTFE
00229  * resource caused by a violation of the command write sequence or issuing an illegal
00230  * FTFE command. While ACCERR is set, the CCIF flag cannot be cleared to launch
00231  * a command. The ACCERR bit is cleared by writing a 1 to it. Writing a 0 to the
00232  * ACCERR bit has no effect.
00233  *
00234  * Values:
00235  * - 0 - No access error detected
00236  * - 1 - Access error detected
00237  */
00238 /*@{*/
00239 #define BP_FTFE_FSTAT_ACCERR (5U)          /*!< Bit position for FTFE_FSTAT_ACCERR. */
00240 #define BM_FTFE_FSTAT_ACCERR (0x20U)       /*!< Bit mask for FTFE_FSTAT_ACCERR. */
00241 #define BS_FTFE_FSTAT_ACCERR (1U)          /*!< Bit field size in bits for FTFE_FSTAT_ACCERR. */
00242 
00243 /*! @brief Read current value of the FTFE_FSTAT_ACCERR field. */
00244 #define BR_FTFE_FSTAT_ACCERR(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_ACCERR)))
00245 
00246 /*! @brief Format value for bitfield FTFE_FSTAT_ACCERR. */
00247 #define BF_FTFE_FSTAT_ACCERR(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FSTAT_ACCERR) & BM_FTFE_FSTAT_ACCERR)
00248 
00249 /*! @brief Set the ACCERR field to a new value. */
00250 #define BW_FTFE_FSTAT_ACCERR(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_ACCERR), v))
00251 /*@}*/
00252 
00253 /*!
00254  * @name Register FTFE_FSTAT, field RDCOLERR[6] (W1C)
00255  *
00256  * The RDCOLERR error bit indicates that the MCU attempted a read from an FTFE
00257  * resource that was being manipulated by an FTFE command (CCIF=0). Any
00258  * simultaneous access is detected as a collision error by the block arbitration logic. The
00259  * read data in this case cannot be guaranteed. The RDCOLERR bit is cleared by
00260  * writing a 1 to it. Writing a 0 to RDCOLERR has no effect.
00261  *
00262  * Values:
00263  * - 0 - No collision error detected
00264  * - 1 - Collision error detected
00265  */
00266 /*@{*/
00267 #define BP_FTFE_FSTAT_RDCOLERR (6U)        /*!< Bit position for FTFE_FSTAT_RDCOLERR. */
00268 #define BM_FTFE_FSTAT_RDCOLERR (0x40U)     /*!< Bit mask for FTFE_FSTAT_RDCOLERR. */
00269 #define BS_FTFE_FSTAT_RDCOLERR (1U)        /*!< Bit field size in bits for FTFE_FSTAT_RDCOLERR. */
00270 
00271 /*! @brief Read current value of the FTFE_FSTAT_RDCOLERR field. */
00272 #define BR_FTFE_FSTAT_RDCOLERR(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_RDCOLERR)))
00273 
00274 /*! @brief Format value for bitfield FTFE_FSTAT_RDCOLERR. */
00275 #define BF_FTFE_FSTAT_RDCOLERR(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FSTAT_RDCOLERR) & BM_FTFE_FSTAT_RDCOLERR)
00276 
00277 /*! @brief Set the RDCOLERR field to a new value. */
00278 #define BW_FTFE_FSTAT_RDCOLERR(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_RDCOLERR), v))
00279 /*@}*/
00280 
00281 /*!
00282  * @name Register FTFE_FSTAT, field CCIF[7] (W1C)
00283  *
00284  * The CCIF flag indicates that a FTFE command or EEPROM file system operation
00285  * has completed. The CCIF flag is cleared by writing a 1 to CCIF to launch a
00286  * command, and CCIF stays low until command completion or command violation. The
00287  * CCIF flag is also cleared by a successful write to FlexRAM while enabled for EEE,
00288  * and CCIF stays low until the EEPROM file system has created the associated
00289  * EEPROM data record. The CCIF bit is reset to 0 but is set to 1 by the memory
00290  * controller at the end of the reset initialization sequence. Depending on how
00291  * quickly the read occurs after reset release, the user may or may not see the 0
00292  * hardware reset value.
00293  *
00294  * Values:
00295  * - 0 - FTFE command or EEPROM file system operation in progress
00296  * - 1 - FTFE command or EEPROM file system operation has completed
00297  */
00298 /*@{*/
00299 #define BP_FTFE_FSTAT_CCIF   (7U)          /*!< Bit position for FTFE_FSTAT_CCIF. */
00300 #define BM_FTFE_FSTAT_CCIF   (0x80U)       /*!< Bit mask for FTFE_FSTAT_CCIF. */
00301 #define BS_FTFE_FSTAT_CCIF   (1U)          /*!< Bit field size in bits for FTFE_FSTAT_CCIF. */
00302 
00303 /*! @brief Read current value of the FTFE_FSTAT_CCIF field. */
00304 #define BR_FTFE_FSTAT_CCIF(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_CCIF)))
00305 
00306 /*! @brief Format value for bitfield FTFE_FSTAT_CCIF. */
00307 #define BF_FTFE_FSTAT_CCIF(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FSTAT_CCIF) & BM_FTFE_FSTAT_CCIF)
00308 
00309 /*! @brief Set the CCIF field to a new value. */
00310 #define BW_FTFE_FSTAT_CCIF(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_FTFE_FSTAT_ADDR(x), BP_FTFE_FSTAT_CCIF), v))
00311 /*@}*/
00312 
00313 /*******************************************************************************
00314  * HW_FTFE_FCNFG - Flash Configuration Register
00315  ******************************************************************************/
00316 
00317 /*!
00318  * @brief HW_FTFE_FCNFG - Flash Configuration Register (RW)
00319  *
00320  * Reset value: 0x00U
00321  *
00322  * This register provides information on the current functional state of the
00323  * FTFE module. The erase control bits (ERSAREQ and ERSSUSP) have write
00324  * restrictions. SWAP, PFLSH, RAMRDY, and EEERDY are read-only status bits. The unassigned
00325  * bits read as noted and are not writable. The reset values for the SWAP, PFLSH,
00326  * RAMRDY, and EEERDY bits are determined during the reset sequence.
00327  */
00328 typedef union _hw_ftfe_fcnfg
00329 {
00330     uint8_t U;
00331     struct _hw_ftfe_fcnfg_bitfields
00332     {
00333         uint8_t EEERDY : 1;            /*!< [0]  */
00334         uint8_t RAMRDY : 1;            /*!< [1] RAM Ready */
00335         uint8_t PFLSH : 1;             /*!< [2] FTFE configuration */
00336         uint8_t SWAP : 1;              /*!< [3] Swap */
00337         uint8_t ERSSUSP : 1;           /*!< [4] Erase Suspend */
00338         uint8_t ERSAREQ : 1;           /*!< [5] Erase All Request */
00339         uint8_t RDCOLLIE : 1;          /*!< [6] Read Collision Error Interrupt Enable
00340                                         * */
00341         uint8_t CCIE : 1;              /*!< [7] Command Complete Interrupt Enable */
00342     } B;
00343 } hw_ftfe_fcnfg_t;
00344 
00345 /*!
00346  * @name Constants and macros for entire FTFE_FCNFG register
00347  */
00348 /*@{*/
00349 #define HW_FTFE_FCNFG_ADDR(x)    ((x) + 0x1U)
00350 
00351 #define HW_FTFE_FCNFG(x)         (*(__IO hw_ftfe_fcnfg_t *) HW_FTFE_FCNFG_ADDR(x))
00352 #define HW_FTFE_FCNFG_RD(x)      (ADDRESS_READ(hw_ftfe_fcnfg_t, HW_FTFE_FCNFG_ADDR(x)))
00353 #define HW_FTFE_FCNFG_WR(x, v)   (ADDRESS_WRITE(hw_ftfe_fcnfg_t, HW_FTFE_FCNFG_ADDR(x), v))
00354 #define HW_FTFE_FCNFG_SET(x, v)  (HW_FTFE_FCNFG_WR(x, HW_FTFE_FCNFG_RD(x) |  (v)))
00355 #define HW_FTFE_FCNFG_CLR(x, v)  (HW_FTFE_FCNFG_WR(x, HW_FTFE_FCNFG_RD(x) & ~(v)))
00356 #define HW_FTFE_FCNFG_TOG(x, v)  (HW_FTFE_FCNFG_WR(x, HW_FTFE_FCNFG_RD(x) ^  (v)))
00357 /*@}*/
00358 
00359 /*
00360  * Constants & macros for individual FTFE_FCNFG bitfields
00361  */
00362 
00363 /*!
00364  * @name Register FTFE_FCNFG, field EEERDY[0] (RO)
00365  *
00366  * For devices with FlexNVM: This flag indicates if the EEPROM backup data has
00367  * been copied to the FlexRAM and is therefore available for read access. During
00368  * the reset sequence, the EEERDY flag remains clear while CCIF=0 and only sets if
00369  * the FlexNVM block is partitioned for EEPROM. For devices without FlexNVM:
00370  * This bit is reserved.
00371  *
00372  * Values:
00373  * - 0 - For devices with FlexNVM: FlexRAM is not available for EEPROM operation.
00374  * - 1 - For devices with FlexNVM: FlexRAM is available for EEPROM operations
00375  *     where: reads from the FlexRAM return data previously written to the FlexRAM
00376  *     in EEPROM mode and writes launch an EEPROM operation to store the written
00377  *     data in the FlexRAM and EEPROM backup.
00378  */
00379 /*@{*/
00380 #define BP_FTFE_FCNFG_EEERDY (0U)          /*!< Bit position for FTFE_FCNFG_EEERDY. */
00381 #define BM_FTFE_FCNFG_EEERDY (0x01U)       /*!< Bit mask for FTFE_FCNFG_EEERDY. */
00382 #define BS_FTFE_FCNFG_EEERDY (1U)          /*!< Bit field size in bits for FTFE_FCNFG_EEERDY. */
00383 
00384 /*! @brief Read current value of the FTFE_FCNFG_EEERDY field. */
00385 #define BR_FTFE_FCNFG_EEERDY(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_EEERDY)))
00386 /*@}*/
00387 
00388 /*!
00389  * @name Register FTFE_FCNFG, field RAMRDY[1] (RO)
00390  *
00391  * This flag indicates the current status of the FlexRAM/ programming
00392  * acceleration RAM. For devices with FlexNVM: The state of the RAMRDY flag is normally
00393  * controlled by the Set FlexRAM Function command. During the reset sequence, the
00394  * RAMRDY flag is cleared if the FlexNVM block is partitioned for EEPROM and will
00395  * be set if the FlexNVM block is not partitioned for EEPROM . The RAMRDY flag is
00396  * cleared if the Program Partition command is run to partition the FlexNVM block
00397  * for EEPROM. The RAMRDY flag sets after completion of the Erase All Blocks
00398  * command or execution of the erase-all operation triggered external to the FTFE.
00399  * For devices without FlexNVM: This bit should always be set.
00400  *
00401  * Values:
00402  * - 0 - For devices with FlexNVM: FlexRAM is not available for traditional RAM
00403  *     access. For devices without FlexNVM: Programming acceleration RAM is not
00404  *     available.
00405  * - 1 - For devices with FlexNVM: FlexRAM is available as traditional RAM only;
00406  *     writes to the FlexRAM do not trigger EEPROM operations. For devices
00407  *     without FlexNVM: Programming acceleration RAM is available.
00408  */
00409 /*@{*/
00410 #define BP_FTFE_FCNFG_RAMRDY (1U)          /*!< Bit position for FTFE_FCNFG_RAMRDY. */
00411 #define BM_FTFE_FCNFG_RAMRDY (0x02U)       /*!< Bit mask for FTFE_FCNFG_RAMRDY. */
00412 #define BS_FTFE_FCNFG_RAMRDY (1U)          /*!< Bit field size in bits for FTFE_FCNFG_RAMRDY. */
00413 
00414 /*! @brief Read current value of the FTFE_FCNFG_RAMRDY field. */
00415 #define BR_FTFE_FCNFG_RAMRDY(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_RAMRDY)))
00416 /*@}*/
00417 
00418 /*!
00419  * @name Register FTFE_FCNFG, field PFLSH[2] (RO)
00420  *
00421  * Values:
00422  * - 0 - For devices with FlexNVM: FTFE configuration supports two program flash
00423  *     blocks and two FlexNVM blocks For devices with program flash only:
00424  *     Reserved
00425  * - 1 - For devices with FlexNVM: Reserved For devices with program flash only:
00426  *     FTFE configuration supports four program flash blocks
00427  */
00428 /*@{*/
00429 #define BP_FTFE_FCNFG_PFLSH  (2U)          /*!< Bit position for FTFE_FCNFG_PFLSH. */
00430 #define BM_FTFE_FCNFG_PFLSH  (0x04U)       /*!< Bit mask for FTFE_FCNFG_PFLSH. */
00431 #define BS_FTFE_FCNFG_PFLSH  (1U)          /*!< Bit field size in bits for FTFE_FCNFG_PFLSH. */
00432 
00433 /*! @brief Read current value of the FTFE_FCNFG_PFLSH field. */
00434 #define BR_FTFE_FCNFG_PFLSH(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_PFLSH)))
00435 /*@}*/
00436 
00437 /*!
00438  * @name Register FTFE_FCNFG, field SWAP[3] (RO)
00439  *
00440  * The SWAP flag indicates which half of the program flash space is located at
00441  * relative address 0x0000. The state of the SWAP flag is set by the FTFE during
00442  * the reset sequence. See for information on swap management.
00443  *
00444  * Values:
00445  * - 0 - For devices with FlexNVM: Program flash 0 block is located at relative
00446  *     address 0x0000 For devices with program flash only: Program flash 0 block
00447  *     is located at relative address 0x0000
00448  * - 1 - For devices with FlexNVM: Reserved For devices with program flash only:
00449  *     Program flash 1 block is located at relative address 0x0000
00450  */
00451 /*@{*/
00452 #define BP_FTFE_FCNFG_SWAP   (3U)          /*!< Bit position for FTFE_FCNFG_SWAP. */
00453 #define BM_FTFE_FCNFG_SWAP   (0x08U)       /*!< Bit mask for FTFE_FCNFG_SWAP. */
00454 #define BS_FTFE_FCNFG_SWAP   (1U)          /*!< Bit field size in bits for FTFE_FCNFG_SWAP. */
00455 
00456 /*! @brief Read current value of the FTFE_FCNFG_SWAP field. */
00457 #define BR_FTFE_FCNFG_SWAP(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_SWAP)))
00458 /*@}*/
00459 
00460 /*!
00461  * @name Register FTFE_FCNFG, field ERSSUSP[4] (RW)
00462  *
00463  * The ERSSUSP bit allows the user to suspend (interrupt) the Erase Flash Sector
00464  * command while it is executing.
00465  *
00466  * Values:
00467  * - 0 - No suspend requested
00468  * - 1 - Suspend the current Erase Flash Sector command execution.
00469  */
00470 /*@{*/
00471 #define BP_FTFE_FCNFG_ERSSUSP (4U)         /*!< Bit position for FTFE_FCNFG_ERSSUSP. */
00472 #define BM_FTFE_FCNFG_ERSSUSP (0x10U)      /*!< Bit mask for FTFE_FCNFG_ERSSUSP. */
00473 #define BS_FTFE_FCNFG_ERSSUSP (1U)         /*!< Bit field size in bits for FTFE_FCNFG_ERSSUSP. */
00474 
00475 /*! @brief Read current value of the FTFE_FCNFG_ERSSUSP field. */
00476 #define BR_FTFE_FCNFG_ERSSUSP(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_ERSSUSP)))
00477 
00478 /*! @brief Format value for bitfield FTFE_FCNFG_ERSSUSP. */
00479 #define BF_FTFE_FCNFG_ERSSUSP(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCNFG_ERSSUSP) & BM_FTFE_FCNFG_ERSSUSP)
00480 
00481 /*! @brief Set the ERSSUSP field to a new value. */
00482 #define BW_FTFE_FCNFG_ERSSUSP(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_ERSSUSP), v))
00483 /*@}*/
00484 
00485 /*!
00486  * @name Register FTFE_FCNFG, field ERSAREQ[5] (RO)
00487  *
00488  * This bit issues a request to the memory controller to execute the Erase All
00489  * Blocks command and release security. ERSAREQ is not directly writable but is
00490  * under indirect user control. Refer to the device's Chip Configuration details on
00491  * how to request this command. The ERSAREQ bit sets when an erase all request
00492  * is triggered external to the FTFE and CCIF is set (no command is currently
00493  * being executed). ERSAREQ is cleared by the FTFE when the operation completes.
00494  *
00495  * Values:
00496  * - 0 - No request or request complete
00497  * - 1 - Request to: run the Erase All Blocks command, verify the erased state,
00498  *     program the security byte in the Flash Configuration Field to the unsecure
00499  *     state, and release MCU security by setting the FSEC[SEC] field to the
00500  *     unsecure state.
00501  */
00502 /*@{*/
00503 #define BP_FTFE_FCNFG_ERSAREQ (5U)         /*!< Bit position for FTFE_FCNFG_ERSAREQ. */
00504 #define BM_FTFE_FCNFG_ERSAREQ (0x20U)      /*!< Bit mask for FTFE_FCNFG_ERSAREQ. */
00505 #define BS_FTFE_FCNFG_ERSAREQ (1U)         /*!< Bit field size in bits for FTFE_FCNFG_ERSAREQ. */
00506 
00507 /*! @brief Read current value of the FTFE_FCNFG_ERSAREQ field. */
00508 #define BR_FTFE_FCNFG_ERSAREQ(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_ERSAREQ)))
00509 /*@}*/
00510 
00511 /*!
00512  * @name Register FTFE_FCNFG, field RDCOLLIE[6] (RW)
00513  *
00514  * The RDCOLLIE bit controls interrupt generation when an FTFE read collision
00515  * error occurs.
00516  *
00517  * Values:
00518  * - 0 - Read collision error interrupt disabled
00519  * - 1 - Read collision error interrupt enabled. An interrupt request is
00520  *     generated whenever an FTFE read collision error is detected (see the description
00521  *     of FSTAT[RDCOLERR]).
00522  */
00523 /*@{*/
00524 #define BP_FTFE_FCNFG_RDCOLLIE (6U)        /*!< Bit position for FTFE_FCNFG_RDCOLLIE. */
00525 #define BM_FTFE_FCNFG_RDCOLLIE (0x40U)     /*!< Bit mask for FTFE_FCNFG_RDCOLLIE. */
00526 #define BS_FTFE_FCNFG_RDCOLLIE (1U)        /*!< Bit field size in bits for FTFE_FCNFG_RDCOLLIE. */
00527 
00528 /*! @brief Read current value of the FTFE_FCNFG_RDCOLLIE field. */
00529 #define BR_FTFE_FCNFG_RDCOLLIE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_RDCOLLIE)))
00530 
00531 /*! @brief Format value for bitfield FTFE_FCNFG_RDCOLLIE. */
00532 #define BF_FTFE_FCNFG_RDCOLLIE(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCNFG_RDCOLLIE) & BM_FTFE_FCNFG_RDCOLLIE)
00533 
00534 /*! @brief Set the RDCOLLIE field to a new value. */
00535 #define BW_FTFE_FCNFG_RDCOLLIE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_RDCOLLIE), v))
00536 /*@}*/
00537 
00538 /*!
00539  * @name Register FTFE_FCNFG, field CCIE[7] (RW)
00540  *
00541  * The CCIE bit controls interrupt generation when an FTFE command completes.
00542  *
00543  * Values:
00544  * - 0 - Command complete interrupt disabled
00545  * - 1 - Command complete interrupt enabled. An interrupt request is generated
00546  *     whenever the FSTAT[CCIF] flag is set.
00547  */
00548 /*@{*/
00549 #define BP_FTFE_FCNFG_CCIE   (7U)          /*!< Bit position for FTFE_FCNFG_CCIE. */
00550 #define BM_FTFE_FCNFG_CCIE   (0x80U)       /*!< Bit mask for FTFE_FCNFG_CCIE. */
00551 #define BS_FTFE_FCNFG_CCIE   (1U)          /*!< Bit field size in bits for FTFE_FCNFG_CCIE. */
00552 
00553 /*! @brief Read current value of the FTFE_FCNFG_CCIE field. */
00554 #define BR_FTFE_FCNFG_CCIE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_CCIE)))
00555 
00556 /*! @brief Format value for bitfield FTFE_FCNFG_CCIE. */
00557 #define BF_FTFE_FCNFG_CCIE(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCNFG_CCIE) & BM_FTFE_FCNFG_CCIE)
00558 
00559 /*! @brief Set the CCIE field to a new value. */
00560 #define BW_FTFE_FCNFG_CCIE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_FTFE_FCNFG_ADDR(x), BP_FTFE_FCNFG_CCIE), v))
00561 /*@}*/
00562 
00563 /*******************************************************************************
00564  * HW_FTFE_FSEC - Flash Security Register
00565  ******************************************************************************/
00566 
00567 /*!
00568  * @brief HW_FTFE_FSEC - Flash Security Register (RO)
00569  *
00570  * Reset value: 0x00U
00571  *
00572  * This read-only register holds all bits associated with the security of the
00573  * MCU and FTFE module. During the reset sequence, the register is loaded with the
00574  * contents of the flash security byte in the Flash Configuration Field located
00575  * in program flash memory. The Flash basis for the values is signified by X in
00576  * the reset value.
00577  */
00578 typedef union _hw_ftfe_fsec
00579 {
00580     uint8_t U;
00581     struct _hw_ftfe_fsec_bitfields
00582     {
00583         uint8_t SEC : 2;               /*!< [1:0] Flash Security */
00584         uint8_t FSLACC : 2;            /*!< [3:2] Freescale Failure Analysis Access Code
00585                                         * */
00586         uint8_t MEEN : 2;              /*!< [5:4] Mass Erase Enable Bits */
00587         uint8_t KEYEN : 2;             /*!< [7:6] Backdoor Key Security Enable */
00588     } B;
00589 } hw_ftfe_fsec_t;
00590 
00591 /*!
00592  * @name Constants and macros for entire FTFE_FSEC register
00593  */
00594 /*@{*/
00595 #define HW_FTFE_FSEC_ADDR(x)     ((x) + 0x2U)
00596 
00597 #define HW_FTFE_FSEC(x)          (*(__I hw_ftfe_fsec_t *) HW_FTFE_FSEC_ADDR(x))
00598 #define HW_FTFE_FSEC_RD(x)       (ADDRESS_READ(hw_ftfe_fsec_t, HW_FTFE_FSEC_ADDR(x)))
00599 /*@}*/
00600 
00601 /*
00602  * Constants & macros for individual FTFE_FSEC bitfields
00603  */
00604 
00605 /*!
00606  * @name Register FTFE_FSEC, field SEC[1:0] (RO)
00607  *
00608  * These bits define the security state of the MCU. In the secure state, the MCU
00609  * limits access to FTFE module resources. The limitations are defined per
00610  * device and are detailed in the Chip Configuration details. If the FTFE module is
00611  * unsecured using backdoor key access, the SEC bits are forced to 10b.
00612  *
00613  * Values:
00614  * - 00 - MCU security status is secure
00615  * - 01 - MCU security status is secure
00616  * - 10 - MCU security status is unsecure (The standard shipping condition of
00617  *     the FTFE is unsecure.)
00618  * - 11 - MCU security status is secure
00619  */
00620 /*@{*/
00621 #define BP_FTFE_FSEC_SEC     (0U)          /*!< Bit position for FTFE_FSEC_SEC. */
00622 #define BM_FTFE_FSEC_SEC     (0x03U)       /*!< Bit mask for FTFE_FSEC_SEC. */
00623 #define BS_FTFE_FSEC_SEC     (2U)          /*!< Bit field size in bits for FTFE_FSEC_SEC. */
00624 
00625 /*! @brief Read current value of the FTFE_FSEC_SEC field. */
00626 #define BR_FTFE_FSEC_SEC(x)  (UNION_READ(hw_ftfe_fsec_t, HW_FTFE_FSEC_ADDR(x), U, B.SEC))
00627 /*@}*/
00628 
00629 /*!
00630  * @name Register FTFE_FSEC, field FSLACC[3:2] (RO)
00631  *
00632  * These bits enable or disable access to the flash memory contents during
00633  * returned part failure analysis at Freescale. When SEC is secure and FSLACC is
00634  * denied, access to the program flash contents is denied and any failure analysis
00635  * performed by Freescale factory test must begin with a full erase to unsecure the
00636  * part. When access is granted (SEC is unsecure, or SEC is secure and FSLACC is
00637  * granted), Freescale factory testing has visibility of the current flash
00638  * contents. The state of the FSLACC bits is only relevant when the SEC bits are set to
00639  * secure. When the SEC field is set to unsecure, the FSLACC setting does not
00640  * matter.
00641  *
00642  * Values:
00643  * - 00 - Freescale factory access granted
00644  * - 01 - Freescale factory access denied
00645  * - 10 - Freescale factory access denied
00646  * - 11 - Freescale factory access granted
00647  */
00648 /*@{*/
00649 #define BP_FTFE_FSEC_FSLACC  (2U)          /*!< Bit position for FTFE_FSEC_FSLACC. */
00650 #define BM_FTFE_FSEC_FSLACC  (0x0CU)       /*!< Bit mask for FTFE_FSEC_FSLACC. */
00651 #define BS_FTFE_FSEC_FSLACC  (2U)          /*!< Bit field size in bits for FTFE_FSEC_FSLACC. */
00652 
00653 /*! @brief Read current value of the FTFE_FSEC_FSLACC field. */
00654 #define BR_FTFE_FSEC_FSLACC(x) (UNION_READ(hw_ftfe_fsec_t, HW_FTFE_FSEC_ADDR(x), U, B.FSLACC))
00655 /*@}*/
00656 
00657 /*!
00658  * @name Register FTFE_FSEC, field MEEN[5:4] (RO)
00659  *
00660  * Enables and disables mass erase capability of the FTFE module. The state of
00661  * the MEEN bits is only relevant when the SEC bits are set to secure outside of
00662  * NVM Normal Mode. When the SEC field is set to unsecure, the MEEN setting does
00663  * not matter.
00664  *
00665  * Values:
00666  * - 00 - Mass erase is enabled
00667  * - 01 - Mass erase is enabled
00668  * - 10 - Mass erase is disabled
00669  * - 11 - Mass erase is enabled
00670  */
00671 /*@{*/
00672 #define BP_FTFE_FSEC_MEEN    (4U)          /*!< Bit position for FTFE_FSEC_MEEN. */
00673 #define BM_FTFE_FSEC_MEEN    (0x30U)       /*!< Bit mask for FTFE_FSEC_MEEN. */
00674 #define BS_FTFE_FSEC_MEEN    (2U)          /*!< Bit field size in bits for FTFE_FSEC_MEEN. */
00675 
00676 /*! @brief Read current value of the FTFE_FSEC_MEEN field. */
00677 #define BR_FTFE_FSEC_MEEN(x) (UNION_READ(hw_ftfe_fsec_t, HW_FTFE_FSEC_ADDR(x), U, B.MEEN))
00678 /*@}*/
00679 
00680 /*!
00681  * @name Register FTFE_FSEC, field KEYEN[7:6] (RO)
00682  *
00683  * These bits enable and disable backdoor key access to the FTFE module.
00684  *
00685  * Values:
00686  * - 00 - Backdoor key access disabled
00687  * - 01 - Backdoor key access disabled (preferred KEYEN state to disable
00688  *     backdoor key access)
00689  * - 10 - Backdoor key access enabled
00690  * - 11 - Backdoor key access disabled
00691  */
00692 /*@{*/
00693 #define BP_FTFE_FSEC_KEYEN   (6U)          /*!< Bit position for FTFE_FSEC_KEYEN. */
00694 #define BM_FTFE_FSEC_KEYEN   (0xC0U)       /*!< Bit mask for FTFE_FSEC_KEYEN. */
00695 #define BS_FTFE_FSEC_KEYEN   (2U)          /*!< Bit field size in bits for FTFE_FSEC_KEYEN. */
00696 
00697 /*! @brief Read current value of the FTFE_FSEC_KEYEN field. */
00698 #define BR_FTFE_FSEC_KEYEN(x) (UNION_READ(hw_ftfe_fsec_t, HW_FTFE_FSEC_ADDR(x), U, B.KEYEN))
00699 /*@}*/
00700 
00701 /*******************************************************************************
00702  * HW_FTFE_FOPT - Flash Option Register
00703  ******************************************************************************/
00704 
00705 /*!
00706  * @brief HW_FTFE_FOPT - Flash Option Register (RO)
00707  *
00708  * Reset value: 0x00U
00709  *
00710  * The flash option register allows the MCU to customize its operations by
00711  * examining the state of these read-only bits, which are loaded from NVM at reset.
00712  * The function of the bits is defined in the device's Chip Configuration details.
00713  * All bits in the register are read-only. During the reset sequence, the
00714  * register is loaded from the flash nonvolatile option byte in the Flash Configuration
00715  * Field located in program flash memory. The flash basis for the values is
00716  * signified by X in the reset value.
00717  */
00718 typedef union _hw_ftfe_fopt
00719 {
00720     uint8_t U;
00721     struct _hw_ftfe_fopt_bitfields
00722     {
00723         uint8_t OPT : 8;               /*!< [7:0] Nonvolatile Option */
00724     } B;
00725 } hw_ftfe_fopt_t;
00726 
00727 /*!
00728  * @name Constants and macros for entire FTFE_FOPT register
00729  */
00730 /*@{*/
00731 #define HW_FTFE_FOPT_ADDR(x)     ((x) + 0x3U)
00732 
00733 #define HW_FTFE_FOPT(x)          (*(__I hw_ftfe_fopt_t *) HW_FTFE_FOPT_ADDR(x))
00734 #define HW_FTFE_FOPT_RD(x)       (ADDRESS_READ(hw_ftfe_fopt_t, HW_FTFE_FOPT_ADDR(x)))
00735 /*@}*/
00736 
00737 /*
00738  * Constants & macros for individual FTFE_FOPT bitfields
00739  */
00740 
00741 /*!
00742  * @name Register FTFE_FOPT, field OPT[7:0] (RO)
00743  *
00744  * These bits are loaded from flash to this register at reset. Refer to the
00745  * device's Chip Configuration details for the definition and use of these bits.
00746  */
00747 /*@{*/
00748 #define BP_FTFE_FOPT_OPT     (0U)          /*!< Bit position for FTFE_FOPT_OPT. */
00749 #define BM_FTFE_FOPT_OPT     (0xFFU)       /*!< Bit mask for FTFE_FOPT_OPT. */
00750 #define BS_FTFE_FOPT_OPT     (8U)          /*!< Bit field size in bits for FTFE_FOPT_OPT. */
00751 
00752 /*! @brief Read current value of the FTFE_FOPT_OPT field. */
00753 #define BR_FTFE_FOPT_OPT(x)  (HW_FTFE_FOPT(x).U)
00754 /*@}*/
00755 
00756 /*******************************************************************************
00757  * HW_FTFE_FCCOB3 - Flash Common Command Object Registers
00758  ******************************************************************************/
00759 
00760 /*!
00761  * @brief HW_FTFE_FCCOB3 - Flash Common Command Object Registers (RW)
00762  *
00763  * Reset value: 0x00U
00764  *
00765  * The FCCOB register group provides 12 bytes for command codes and parameters.
00766  * The individual bytes within the set append a 0-B hex identifier to the FCCOB
00767  * register name: FCCOB0, FCCOB1, ..., FCCOBB.
00768  */
00769 typedef union _hw_ftfe_fccob3
00770 {
00771     uint8_t U;
00772     struct _hw_ftfe_fccob3_bitfields
00773     {
00774         uint8_t CCOBn : 8;             /*!< [7:0]  */
00775     } B;
00776 } hw_ftfe_fccob3_t;
00777 
00778 /*!
00779  * @name Constants and macros for entire FTFE_FCCOB3 register
00780  */
00781 /*@{*/
00782 #define HW_FTFE_FCCOB3_ADDR(x)   ((x) + 0x4U)
00783 
00784 #define HW_FTFE_FCCOB3(x)        (*(__IO hw_ftfe_fccob3_t *) HW_FTFE_FCCOB3_ADDR(x))
00785 #define HW_FTFE_FCCOB3_RD(x)     (ADDRESS_READ(hw_ftfe_fccob3_t, HW_FTFE_FCCOB3_ADDR(x)))
00786 #define HW_FTFE_FCCOB3_WR(x, v)  (ADDRESS_WRITE(hw_ftfe_fccob3_t, HW_FTFE_FCCOB3_ADDR(x), v))
00787 #define HW_FTFE_FCCOB3_SET(x, v) (HW_FTFE_FCCOB3_WR(x, HW_FTFE_FCCOB3_RD(x) |  (v)))
00788 #define HW_FTFE_FCCOB3_CLR(x, v) (HW_FTFE_FCCOB3_WR(x, HW_FTFE_FCCOB3_RD(x) & ~(v)))
00789 #define HW_FTFE_FCCOB3_TOG(x, v) (HW_FTFE_FCCOB3_WR(x, HW_FTFE_FCCOB3_RD(x) ^  (v)))
00790 /*@}*/
00791 
00792 /*
00793  * Constants & macros for individual FTFE_FCCOB3 bitfields
00794  */
00795 
00796 /*!
00797  * @name Register FTFE_FCCOB3, field CCOBn[7:0] (RW)
00798  *
00799  * The FCCOB register provides a command code and relevant parameters to the
00800  * memory controller. The individual registers that compose the FCCOB data set can
00801  * be written in any order, but you must provide all needed values, which vary
00802  * from command to command. First, set up all required FCCOB fields and then
00803  * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
00804  * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
00805  * by the user until the command completes (CCIF returns to 1). No command
00806  * buffering or queueing is provided; the next command can be loaded only after the
00807  * current command completes. Some commands return information to the FCCOB
00808  * registers. Any values returned to FCCOB are available for reading after the
00809  * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
00810  * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
00811  * the command code. This 8-bit value defines the command to be executed. The
00812  * command code is followed by the parameters required for this specific FTFE command,
00813  * typically an address and/or data values. The command parameter table is
00814  * written in terms of FCCOB Number (which is equivalent to the byte number). This
00815  * number is a reference to the FCCOB register name and is not the register address.
00816  * FCCOB NumberRefers to FCCOB register name, not register address Typical
00817  * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
00818  * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
00819  * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
00820  * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
00821  * register group uses a big endian addressing convention. For all command parameter
00822  * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
00823  * register number. The FCCOB register group may be read and written as
00824  * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
00825  */
00826 /*@{*/
00827 #define BP_FTFE_FCCOB3_CCOBn (0U)          /*!< Bit position for FTFE_FCCOB3_CCOBn. */
00828 #define BM_FTFE_FCCOB3_CCOBn (0xFFU)       /*!< Bit mask for FTFE_FCCOB3_CCOBn. */
00829 #define BS_FTFE_FCCOB3_CCOBn (8U)          /*!< Bit field size in bits for FTFE_FCCOB3_CCOBn. */
00830 
00831 /*! @brief Read current value of the FTFE_FCCOB3_CCOBn field. */
00832 #define BR_FTFE_FCCOB3_CCOBn(x) (HW_FTFE_FCCOB3(x).U)
00833 
00834 /*! @brief Format value for bitfield FTFE_FCCOB3_CCOBn. */
00835 #define BF_FTFE_FCCOB3_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB3_CCOBn) & BM_FTFE_FCCOB3_CCOBn)
00836 
00837 /*! @brief Set the CCOBn field to a new value. */
00838 #define BW_FTFE_FCCOB3_CCOBn(x, v) (HW_FTFE_FCCOB3_WR(x, v))
00839 /*@}*/
00840 
00841 /*******************************************************************************
00842  * HW_FTFE_FCCOB2 - Flash Common Command Object Registers
00843  ******************************************************************************/
00844 
00845 /*!
00846  * @brief HW_FTFE_FCCOB2 - Flash Common Command Object Registers (RW)
00847  *
00848  * Reset value: 0x00U
00849  *
00850  * The FCCOB register group provides 12 bytes for command codes and parameters.
00851  * The individual bytes within the set append a 0-B hex identifier to the FCCOB
00852  * register name: FCCOB0, FCCOB1, ..., FCCOBB.
00853  */
00854 typedef union _hw_ftfe_fccob2
00855 {
00856     uint8_t U;
00857     struct _hw_ftfe_fccob2_bitfields
00858     {
00859         uint8_t CCOBn : 8;             /*!< [7:0]  */
00860     } B;
00861 } hw_ftfe_fccob2_t;
00862 
00863 /*!
00864  * @name Constants and macros for entire FTFE_FCCOB2 register
00865  */
00866 /*@{*/
00867 #define HW_FTFE_FCCOB2_ADDR(x)   ((x) + 0x5U)
00868 
00869 #define HW_FTFE_FCCOB2(x)        (*(__IO hw_ftfe_fccob2_t *) HW_FTFE_FCCOB2_ADDR(x))
00870 #define HW_FTFE_FCCOB2_RD(x)     (ADDRESS_READ(hw_ftfe_fccob2_t, HW_FTFE_FCCOB2_ADDR(x)))
00871 #define HW_FTFE_FCCOB2_WR(x, v)  (ADDRESS_WRITE(hw_ftfe_fccob2_t, HW_FTFE_FCCOB2_ADDR(x), v))
00872 #define HW_FTFE_FCCOB2_SET(x, v) (HW_FTFE_FCCOB2_WR(x, HW_FTFE_FCCOB2_RD(x) |  (v)))
00873 #define HW_FTFE_FCCOB2_CLR(x, v) (HW_FTFE_FCCOB2_WR(x, HW_FTFE_FCCOB2_RD(x) & ~(v)))
00874 #define HW_FTFE_FCCOB2_TOG(x, v) (HW_FTFE_FCCOB2_WR(x, HW_FTFE_FCCOB2_RD(x) ^  (v)))
00875 /*@}*/
00876 
00877 /*
00878  * Constants & macros for individual FTFE_FCCOB2 bitfields
00879  */
00880 
00881 /*!
00882  * @name Register FTFE_FCCOB2, field CCOBn[7:0] (RW)
00883  *
00884  * The FCCOB register provides a command code and relevant parameters to the
00885  * memory controller. The individual registers that compose the FCCOB data set can
00886  * be written in any order, but you must provide all needed values, which vary
00887  * from command to command. First, set up all required FCCOB fields and then
00888  * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
00889  * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
00890  * by the user until the command completes (CCIF returns to 1). No command
00891  * buffering or queueing is provided; the next command can be loaded only after the
00892  * current command completes. Some commands return information to the FCCOB
00893  * registers. Any values returned to FCCOB are available for reading after the
00894  * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
00895  * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
00896  * the command code. This 8-bit value defines the command to be executed. The
00897  * command code is followed by the parameters required for this specific FTFE command,
00898  * typically an address and/or data values. The command parameter table is
00899  * written in terms of FCCOB Number (which is equivalent to the byte number). This
00900  * number is a reference to the FCCOB register name and is not the register address.
00901  * FCCOB NumberRefers to FCCOB register name, not register address Typical
00902  * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
00903  * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
00904  * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
00905  * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
00906  * register group uses a big endian addressing convention. For all command parameter
00907  * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
00908  * register number. The FCCOB register group may be read and written as
00909  * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
00910  */
00911 /*@{*/
00912 #define BP_FTFE_FCCOB2_CCOBn (0U)          /*!< Bit position for FTFE_FCCOB2_CCOBn. */
00913 #define BM_FTFE_FCCOB2_CCOBn (0xFFU)       /*!< Bit mask for FTFE_FCCOB2_CCOBn. */
00914 #define BS_FTFE_FCCOB2_CCOBn (8U)          /*!< Bit field size in bits for FTFE_FCCOB2_CCOBn. */
00915 
00916 /*! @brief Read current value of the FTFE_FCCOB2_CCOBn field. */
00917 #define BR_FTFE_FCCOB2_CCOBn(x) (HW_FTFE_FCCOB2(x).U)
00918 
00919 /*! @brief Format value for bitfield FTFE_FCCOB2_CCOBn. */
00920 #define BF_FTFE_FCCOB2_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB2_CCOBn) & BM_FTFE_FCCOB2_CCOBn)
00921 
00922 /*! @brief Set the CCOBn field to a new value. */
00923 #define BW_FTFE_FCCOB2_CCOBn(x, v) (HW_FTFE_FCCOB2_WR(x, v))
00924 /*@}*/
00925 
00926 /*******************************************************************************
00927  * HW_FTFE_FCCOB1 - Flash Common Command Object Registers
00928  ******************************************************************************/
00929 
00930 /*!
00931  * @brief HW_FTFE_FCCOB1 - Flash Common Command Object Registers (RW)
00932  *
00933  * Reset value: 0x00U
00934  *
00935  * The FCCOB register group provides 12 bytes for command codes and parameters.
00936  * The individual bytes within the set append a 0-B hex identifier to the FCCOB
00937  * register name: FCCOB0, FCCOB1, ..., FCCOBB.
00938  */
00939 typedef union _hw_ftfe_fccob1
00940 {
00941     uint8_t U;
00942     struct _hw_ftfe_fccob1_bitfields
00943     {
00944         uint8_t CCOBn : 8;             /*!< [7:0]  */
00945     } B;
00946 } hw_ftfe_fccob1_t;
00947 
00948 /*!
00949  * @name Constants and macros for entire FTFE_FCCOB1 register
00950  */
00951 /*@{*/
00952 #define HW_FTFE_FCCOB1_ADDR(x)   ((x) + 0x6U)
00953 
00954 #define HW_FTFE_FCCOB1(x)        (*(__IO hw_ftfe_fccob1_t *) HW_FTFE_FCCOB1_ADDR(x))
00955 #define HW_FTFE_FCCOB1_RD(x)     (ADDRESS_READ(hw_ftfe_fccob1_t, HW_FTFE_FCCOB1_ADDR(x)))
00956 #define HW_FTFE_FCCOB1_WR(x, v)  (ADDRESS_WRITE(hw_ftfe_fccob1_t, HW_FTFE_FCCOB1_ADDR(x), v))
00957 #define HW_FTFE_FCCOB1_SET(x, v) (HW_FTFE_FCCOB1_WR(x, HW_FTFE_FCCOB1_RD(x) |  (v)))
00958 #define HW_FTFE_FCCOB1_CLR(x, v) (HW_FTFE_FCCOB1_WR(x, HW_FTFE_FCCOB1_RD(x) & ~(v)))
00959 #define HW_FTFE_FCCOB1_TOG(x, v) (HW_FTFE_FCCOB1_WR(x, HW_FTFE_FCCOB1_RD(x) ^  (v)))
00960 /*@}*/
00961 
00962 /*
00963  * Constants & macros for individual FTFE_FCCOB1 bitfields
00964  */
00965 
00966 /*!
00967  * @name Register FTFE_FCCOB1, field CCOBn[7:0] (RW)
00968  *
00969  * The FCCOB register provides a command code and relevant parameters to the
00970  * memory controller. The individual registers that compose the FCCOB data set can
00971  * be written in any order, but you must provide all needed values, which vary
00972  * from command to command. First, set up all required FCCOB fields and then
00973  * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
00974  * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
00975  * by the user until the command completes (CCIF returns to 1). No command
00976  * buffering or queueing is provided; the next command can be loaded only after the
00977  * current command completes. Some commands return information to the FCCOB
00978  * registers. Any values returned to FCCOB are available for reading after the
00979  * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
00980  * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
00981  * the command code. This 8-bit value defines the command to be executed. The
00982  * command code is followed by the parameters required for this specific FTFE command,
00983  * typically an address and/or data values. The command parameter table is
00984  * written in terms of FCCOB Number (which is equivalent to the byte number). This
00985  * number is a reference to the FCCOB register name and is not the register address.
00986  * FCCOB NumberRefers to FCCOB register name, not register address Typical
00987  * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
00988  * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
00989  * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
00990  * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
00991  * register group uses a big endian addressing convention. For all command parameter
00992  * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
00993  * register number. The FCCOB register group may be read and written as
00994  * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
00995  */
00996 /*@{*/
00997 #define BP_FTFE_FCCOB1_CCOBn (0U)          /*!< Bit position for FTFE_FCCOB1_CCOBn. */
00998 #define BM_FTFE_FCCOB1_CCOBn (0xFFU)       /*!< Bit mask for FTFE_FCCOB1_CCOBn. */
00999 #define BS_FTFE_FCCOB1_CCOBn (8U)          /*!< Bit field size in bits for FTFE_FCCOB1_CCOBn. */
01000 
01001 /*! @brief Read current value of the FTFE_FCCOB1_CCOBn field. */
01002 #define BR_FTFE_FCCOB1_CCOBn(x) (HW_FTFE_FCCOB1(x).U)
01003 
01004 /*! @brief Format value for bitfield FTFE_FCCOB1_CCOBn. */
01005 #define BF_FTFE_FCCOB1_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB1_CCOBn) & BM_FTFE_FCCOB1_CCOBn)
01006 
01007 /*! @brief Set the CCOBn field to a new value. */
01008 #define BW_FTFE_FCCOB1_CCOBn(x, v) (HW_FTFE_FCCOB1_WR(x, v))
01009 /*@}*/
01010 
01011 /*******************************************************************************
01012  * HW_FTFE_FCCOB0 - Flash Common Command Object Registers
01013  ******************************************************************************/
01014 
01015 /*!
01016  * @brief HW_FTFE_FCCOB0 - Flash Common Command Object Registers (RW)
01017  *
01018  * Reset value: 0x00U
01019  *
01020  * The FCCOB register group provides 12 bytes for command codes and parameters.
01021  * The individual bytes within the set append a 0-B hex identifier to the FCCOB
01022  * register name: FCCOB0, FCCOB1, ..., FCCOBB.
01023  */
01024 typedef union _hw_ftfe_fccob0
01025 {
01026     uint8_t U;
01027     struct _hw_ftfe_fccob0_bitfields
01028     {
01029         uint8_t CCOBn : 8;             /*!< [7:0]  */
01030     } B;
01031 } hw_ftfe_fccob0_t;
01032 
01033 /*!
01034  * @name Constants and macros for entire FTFE_FCCOB0 register
01035  */
01036 /*@{*/
01037 #define HW_FTFE_FCCOB0_ADDR(x)   ((x) + 0x7U)
01038 
01039 #define HW_FTFE_FCCOB0(x)        (*(__IO hw_ftfe_fccob0_t *) HW_FTFE_FCCOB0_ADDR(x))
01040 #define HW_FTFE_FCCOB0_RD(x)     (ADDRESS_READ(hw_ftfe_fccob0_t, HW_FTFE_FCCOB0_ADDR(x)))
01041 #define HW_FTFE_FCCOB0_WR(x, v)  (ADDRESS_WRITE(hw_ftfe_fccob0_t, HW_FTFE_FCCOB0_ADDR(x), v))
01042 #define HW_FTFE_FCCOB0_SET(x, v) (HW_FTFE_FCCOB0_WR(x, HW_FTFE_FCCOB0_RD(x) |  (v)))
01043 #define HW_FTFE_FCCOB0_CLR(x, v) (HW_FTFE_FCCOB0_WR(x, HW_FTFE_FCCOB0_RD(x) & ~(v)))
01044 #define HW_FTFE_FCCOB0_TOG(x, v) (HW_FTFE_FCCOB0_WR(x, HW_FTFE_FCCOB0_RD(x) ^  (v)))
01045 /*@}*/
01046 
01047 /*
01048  * Constants & macros for individual FTFE_FCCOB0 bitfields
01049  */
01050 
01051 /*!
01052  * @name Register FTFE_FCCOB0, field CCOBn[7:0] (RW)
01053  *
01054  * The FCCOB register provides a command code and relevant parameters to the
01055  * memory controller. The individual registers that compose the FCCOB data set can
01056  * be written in any order, but you must provide all needed values, which vary
01057  * from command to command. First, set up all required FCCOB fields and then
01058  * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
01059  * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
01060  * by the user until the command completes (CCIF returns to 1). No command
01061  * buffering or queueing is provided; the next command can be loaded only after the
01062  * current command completes. Some commands return information to the FCCOB
01063  * registers. Any values returned to FCCOB are available for reading after the
01064  * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
01065  * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
01066  * the command code. This 8-bit value defines the command to be executed. The
01067  * command code is followed by the parameters required for this specific FTFE command,
01068  * typically an address and/or data values. The command parameter table is
01069  * written in terms of FCCOB Number (which is equivalent to the byte number). This
01070  * number is a reference to the FCCOB register name and is not the register address.
01071  * FCCOB NumberRefers to FCCOB register name, not register address Typical
01072  * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
01073  * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
01074  * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
01075  * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
01076  * register group uses a big endian addressing convention. For all command parameter
01077  * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
01078  * register number. The FCCOB register group may be read and written as
01079  * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
01080  */
01081 /*@{*/
01082 #define BP_FTFE_FCCOB0_CCOBn (0U)          /*!< Bit position for FTFE_FCCOB0_CCOBn. */
01083 #define BM_FTFE_FCCOB0_CCOBn (0xFFU)       /*!< Bit mask for FTFE_FCCOB0_CCOBn. */
01084 #define BS_FTFE_FCCOB0_CCOBn (8U)          /*!< Bit field size in bits for FTFE_FCCOB0_CCOBn. */
01085 
01086 /*! @brief Read current value of the FTFE_FCCOB0_CCOBn field. */
01087 #define BR_FTFE_FCCOB0_CCOBn(x) (HW_FTFE_FCCOB0(x).U)
01088 
01089 /*! @brief Format value for bitfield FTFE_FCCOB0_CCOBn. */
01090 #define BF_FTFE_FCCOB0_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB0_CCOBn) & BM_FTFE_FCCOB0_CCOBn)
01091 
01092 /*! @brief Set the CCOBn field to a new value. */
01093 #define BW_FTFE_FCCOB0_CCOBn(x, v) (HW_FTFE_FCCOB0_WR(x, v))
01094 /*@}*/
01095 
01096 /*******************************************************************************
01097  * HW_FTFE_FCCOB7 - Flash Common Command Object Registers
01098  ******************************************************************************/
01099 
01100 /*!
01101  * @brief HW_FTFE_FCCOB7 - Flash Common Command Object Registers (RW)
01102  *
01103  * Reset value: 0x00U
01104  *
01105  * The FCCOB register group provides 12 bytes for command codes and parameters.
01106  * The individual bytes within the set append a 0-B hex identifier to the FCCOB
01107  * register name: FCCOB0, FCCOB1, ..., FCCOBB.
01108  */
01109 typedef union _hw_ftfe_fccob7
01110 {
01111     uint8_t U;
01112     struct _hw_ftfe_fccob7_bitfields
01113     {
01114         uint8_t CCOBn : 8;             /*!< [7:0]  */
01115     } B;
01116 } hw_ftfe_fccob7_t;
01117 
01118 /*!
01119  * @name Constants and macros for entire FTFE_FCCOB7 register
01120  */
01121 /*@{*/
01122 #define HW_FTFE_FCCOB7_ADDR(x)   ((x) + 0x8U)
01123 
01124 #define HW_FTFE_FCCOB7(x)        (*(__IO hw_ftfe_fccob7_t *) HW_FTFE_FCCOB7_ADDR(x))
01125 #define HW_FTFE_FCCOB7_RD(x)     (ADDRESS_READ(hw_ftfe_fccob7_t, HW_FTFE_FCCOB7_ADDR(x)))
01126 #define HW_FTFE_FCCOB7_WR(x, v)  (ADDRESS_WRITE(hw_ftfe_fccob7_t, HW_FTFE_FCCOB7_ADDR(x), v))
01127 #define HW_FTFE_FCCOB7_SET(x, v) (HW_FTFE_FCCOB7_WR(x, HW_FTFE_FCCOB7_RD(x) |  (v)))
01128 #define HW_FTFE_FCCOB7_CLR(x, v) (HW_FTFE_FCCOB7_WR(x, HW_FTFE_FCCOB7_RD(x) & ~(v)))
01129 #define HW_FTFE_FCCOB7_TOG(x, v) (HW_FTFE_FCCOB7_WR(x, HW_FTFE_FCCOB7_RD(x) ^  (v)))
01130 /*@}*/
01131 
01132 /*
01133  * Constants & macros for individual FTFE_FCCOB7 bitfields
01134  */
01135 
01136 /*!
01137  * @name Register FTFE_FCCOB7, field CCOBn[7:0] (RW)
01138  *
01139  * The FCCOB register provides a command code and relevant parameters to the
01140  * memory controller. The individual registers that compose the FCCOB data set can
01141  * be written in any order, but you must provide all needed values, which vary
01142  * from command to command. First, set up all required FCCOB fields and then
01143  * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
01144  * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
01145  * by the user until the command completes (CCIF returns to 1). No command
01146  * buffering or queueing is provided; the next command can be loaded only after the
01147  * current command completes. Some commands return information to the FCCOB
01148  * registers. Any values returned to FCCOB are available for reading after the
01149  * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
01150  * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
01151  * the command code. This 8-bit value defines the command to be executed. The
01152  * command code is followed by the parameters required for this specific FTFE command,
01153  * typically an address and/or data values. The command parameter table is
01154  * written in terms of FCCOB Number (which is equivalent to the byte number). This
01155  * number is a reference to the FCCOB register name and is not the register address.
01156  * FCCOB NumberRefers to FCCOB register name, not register address Typical
01157  * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
01158  * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
01159  * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
01160  * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
01161  * register group uses a big endian addressing convention. For all command parameter
01162  * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
01163  * register number. The FCCOB register group may be read and written as
01164  * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
01165  */
01166 /*@{*/
01167 #define BP_FTFE_FCCOB7_CCOBn (0U)          /*!< Bit position for FTFE_FCCOB7_CCOBn. */
01168 #define BM_FTFE_FCCOB7_CCOBn (0xFFU)       /*!< Bit mask for FTFE_FCCOB7_CCOBn. */
01169 #define BS_FTFE_FCCOB7_CCOBn (8U)          /*!< Bit field size in bits for FTFE_FCCOB7_CCOBn. */
01170 
01171 /*! @brief Read current value of the FTFE_FCCOB7_CCOBn field. */
01172 #define BR_FTFE_FCCOB7_CCOBn(x) (HW_FTFE_FCCOB7(x).U)
01173 
01174 /*! @brief Format value for bitfield FTFE_FCCOB7_CCOBn. */
01175 #define BF_FTFE_FCCOB7_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB7_CCOBn) & BM_FTFE_FCCOB7_CCOBn)
01176 
01177 /*! @brief Set the CCOBn field to a new value. */
01178 #define BW_FTFE_FCCOB7_CCOBn(x, v) (HW_FTFE_FCCOB7_WR(x, v))
01179 /*@}*/
01180 
01181 /*******************************************************************************
01182  * HW_FTFE_FCCOB6 - Flash Common Command Object Registers
01183  ******************************************************************************/
01184 
01185 /*!
01186  * @brief HW_FTFE_FCCOB6 - Flash Common Command Object Registers (RW)
01187  *
01188  * Reset value: 0x00U
01189  *
01190  * The FCCOB register group provides 12 bytes for command codes and parameters.
01191  * The individual bytes within the set append a 0-B hex identifier to the FCCOB
01192  * register name: FCCOB0, FCCOB1, ..., FCCOBB.
01193  */
01194 typedef union _hw_ftfe_fccob6
01195 {
01196     uint8_t U;
01197     struct _hw_ftfe_fccob6_bitfields
01198     {
01199         uint8_t CCOBn : 8;             /*!< [7:0]  */
01200     } B;
01201 } hw_ftfe_fccob6_t;
01202 
01203 /*!
01204  * @name Constants and macros for entire FTFE_FCCOB6 register
01205  */
01206 /*@{*/
01207 #define HW_FTFE_FCCOB6_ADDR(x)   ((x) + 0x9U)
01208 
01209 #define HW_FTFE_FCCOB6(x)        (*(__IO hw_ftfe_fccob6_t *) HW_FTFE_FCCOB6_ADDR(x))
01210 #define HW_FTFE_FCCOB6_RD(x)     (ADDRESS_READ(hw_ftfe_fccob6_t, HW_FTFE_FCCOB6_ADDR(x)))
01211 #define HW_FTFE_FCCOB6_WR(x, v)  (ADDRESS_WRITE(hw_ftfe_fccob6_t, HW_FTFE_FCCOB6_ADDR(x), v))
01212 #define HW_FTFE_FCCOB6_SET(x, v) (HW_FTFE_FCCOB6_WR(x, HW_FTFE_FCCOB6_RD(x) |  (v)))
01213 #define HW_FTFE_FCCOB6_CLR(x, v) (HW_FTFE_FCCOB6_WR(x, HW_FTFE_FCCOB6_RD(x) & ~(v)))
01214 #define HW_FTFE_FCCOB6_TOG(x, v) (HW_FTFE_FCCOB6_WR(x, HW_FTFE_FCCOB6_RD(x) ^  (v)))
01215 /*@}*/
01216 
01217 /*
01218  * Constants & macros for individual FTFE_FCCOB6 bitfields
01219  */
01220 
01221 /*!
01222  * @name Register FTFE_FCCOB6, field CCOBn[7:0] (RW)
01223  *
01224  * The FCCOB register provides a command code and relevant parameters to the
01225  * memory controller. The individual registers that compose the FCCOB data set can
01226  * be written in any order, but you must provide all needed values, which vary
01227  * from command to command. First, set up all required FCCOB fields and then
01228  * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
01229  * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
01230  * by the user until the command completes (CCIF returns to 1). No command
01231  * buffering or queueing is provided; the next command can be loaded only after the
01232  * current command completes. Some commands return information to the FCCOB
01233  * registers. Any values returned to FCCOB are available for reading after the
01234  * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
01235  * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
01236  * the command code. This 8-bit value defines the command to be executed. The
01237  * command code is followed by the parameters required for this specific FTFE command,
01238  * typically an address and/or data values. The command parameter table is
01239  * written in terms of FCCOB Number (which is equivalent to the byte number). This
01240  * number is a reference to the FCCOB register name and is not the register address.
01241  * FCCOB NumberRefers to FCCOB register name, not register address Typical
01242  * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
01243  * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
01244  * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
01245  * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
01246  * register group uses a big endian addressing convention. For all command parameter
01247  * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
01248  * register number. The FCCOB register group may be read and written as
01249  * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
01250  */
01251 /*@{*/
01252 #define BP_FTFE_FCCOB6_CCOBn (0U)          /*!< Bit position for FTFE_FCCOB6_CCOBn. */
01253 #define BM_FTFE_FCCOB6_CCOBn (0xFFU)       /*!< Bit mask for FTFE_FCCOB6_CCOBn. */
01254 #define BS_FTFE_FCCOB6_CCOBn (8U)          /*!< Bit field size in bits for FTFE_FCCOB6_CCOBn. */
01255 
01256 /*! @brief Read current value of the FTFE_FCCOB6_CCOBn field. */
01257 #define BR_FTFE_FCCOB6_CCOBn(x) (HW_FTFE_FCCOB6(x).U)
01258 
01259 /*! @brief Format value for bitfield FTFE_FCCOB6_CCOBn. */
01260 #define BF_FTFE_FCCOB6_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB6_CCOBn) & BM_FTFE_FCCOB6_CCOBn)
01261 
01262 /*! @brief Set the CCOBn field to a new value. */
01263 #define BW_FTFE_FCCOB6_CCOBn(x, v) (HW_FTFE_FCCOB6_WR(x, v))
01264 /*@}*/
01265 
01266 /*******************************************************************************
01267  * HW_FTFE_FCCOB5 - Flash Common Command Object Registers
01268  ******************************************************************************/
01269 
01270 /*!
01271  * @brief HW_FTFE_FCCOB5 - Flash Common Command Object Registers (RW)
01272  *
01273  * Reset value: 0x00U
01274  *
01275  * The FCCOB register group provides 12 bytes for command codes and parameters.
01276  * The individual bytes within the set append a 0-B hex identifier to the FCCOB
01277  * register name: FCCOB0, FCCOB1, ..., FCCOBB.
01278  */
01279 typedef union _hw_ftfe_fccob5
01280 {
01281     uint8_t U;
01282     struct _hw_ftfe_fccob5_bitfields
01283     {
01284         uint8_t CCOBn : 8;             /*!< [7:0]  */
01285     } B;
01286 } hw_ftfe_fccob5_t;
01287 
01288 /*!
01289  * @name Constants and macros for entire FTFE_FCCOB5 register
01290  */
01291 /*@{*/
01292 #define HW_FTFE_FCCOB5_ADDR(x)   ((x) + 0xAU)
01293 
01294 #define HW_FTFE_FCCOB5(x)        (*(__IO hw_ftfe_fccob5_t *) HW_FTFE_FCCOB5_ADDR(x))
01295 #define HW_FTFE_FCCOB5_RD(x)     (ADDRESS_READ(hw_ftfe_fccob5_t, HW_FTFE_FCCOB5_ADDR(x)))
01296 #define HW_FTFE_FCCOB5_WR(x, v)  (ADDRESS_WRITE(hw_ftfe_fccob5_t, HW_FTFE_FCCOB5_ADDR(x), v))
01297 #define HW_FTFE_FCCOB5_SET(x, v) (HW_FTFE_FCCOB5_WR(x, HW_FTFE_FCCOB5_RD(x) |  (v)))
01298 #define HW_FTFE_FCCOB5_CLR(x, v) (HW_FTFE_FCCOB5_WR(x, HW_FTFE_FCCOB5_RD(x) & ~(v)))
01299 #define HW_FTFE_FCCOB5_TOG(x, v) (HW_FTFE_FCCOB5_WR(x, HW_FTFE_FCCOB5_RD(x) ^  (v)))
01300 /*@}*/
01301 
01302 /*
01303  * Constants & macros for individual FTFE_FCCOB5 bitfields
01304  */
01305 
01306 /*!
01307  * @name Register FTFE_FCCOB5, field CCOBn[7:0] (RW)
01308  *
01309  * The FCCOB register provides a command code and relevant parameters to the
01310  * memory controller. The individual registers that compose the FCCOB data set can
01311  * be written in any order, but you must provide all needed values, which vary
01312  * from command to command. First, set up all required FCCOB fields and then
01313  * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
01314  * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
01315  * by the user until the command completes (CCIF returns to 1). No command
01316  * buffering or queueing is provided; the next command can be loaded only after the
01317  * current command completes. Some commands return information to the FCCOB
01318  * registers. Any values returned to FCCOB are available for reading after the
01319  * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
01320  * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
01321  * the command code. This 8-bit value defines the command to be executed. The
01322  * command code is followed by the parameters required for this specific FTFE command,
01323  * typically an address and/or data values. The command parameter table is
01324  * written in terms of FCCOB Number (which is equivalent to the byte number). This
01325  * number is a reference to the FCCOB register name and is not the register address.
01326  * FCCOB NumberRefers to FCCOB register name, not register address Typical
01327  * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
01328  * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
01329  * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
01330  * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
01331  * register group uses a big endian addressing convention. For all command parameter
01332  * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
01333  * register number. The FCCOB register group may be read and written as
01334  * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
01335  */
01336 /*@{*/
01337 #define BP_FTFE_FCCOB5_CCOBn (0U)          /*!< Bit position for FTFE_FCCOB5_CCOBn. */
01338 #define BM_FTFE_FCCOB5_CCOBn (0xFFU)       /*!< Bit mask for FTFE_FCCOB5_CCOBn. */
01339 #define BS_FTFE_FCCOB5_CCOBn (8U)          /*!< Bit field size in bits for FTFE_FCCOB5_CCOBn. */
01340 
01341 /*! @brief Read current value of the FTFE_FCCOB5_CCOBn field. */
01342 #define BR_FTFE_FCCOB5_CCOBn(x) (HW_FTFE_FCCOB5(x).U)
01343 
01344 /*! @brief Format value for bitfield FTFE_FCCOB5_CCOBn. */
01345 #define BF_FTFE_FCCOB5_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB5_CCOBn) & BM_FTFE_FCCOB5_CCOBn)
01346 
01347 /*! @brief Set the CCOBn field to a new value. */
01348 #define BW_FTFE_FCCOB5_CCOBn(x, v) (HW_FTFE_FCCOB5_WR(x, v))
01349 /*@}*/
01350 
01351 /*******************************************************************************
01352  * HW_FTFE_FCCOB4 - Flash Common Command Object Registers
01353  ******************************************************************************/
01354 
01355 /*!
01356  * @brief HW_FTFE_FCCOB4 - Flash Common Command Object Registers (RW)
01357  *
01358  * Reset value: 0x00U
01359  *
01360  * The FCCOB register group provides 12 bytes for command codes and parameters.
01361  * The individual bytes within the set append a 0-B hex identifier to the FCCOB
01362  * register name: FCCOB0, FCCOB1, ..., FCCOBB.
01363  */
01364 typedef union _hw_ftfe_fccob4
01365 {
01366     uint8_t U;
01367     struct _hw_ftfe_fccob4_bitfields
01368     {
01369         uint8_t CCOBn : 8;             /*!< [7:0]  */
01370     } B;
01371 } hw_ftfe_fccob4_t;
01372 
01373 /*!
01374  * @name Constants and macros for entire FTFE_FCCOB4 register
01375  */
01376 /*@{*/
01377 #define HW_FTFE_FCCOB4_ADDR(x)   ((x) + 0xBU)
01378 
01379 #define HW_FTFE_FCCOB4(x)        (*(__IO hw_ftfe_fccob4_t *) HW_FTFE_FCCOB4_ADDR(x))
01380 #define HW_FTFE_FCCOB4_RD(x)     (ADDRESS_READ(hw_ftfe_fccob4_t, HW_FTFE_FCCOB4_ADDR(x)))
01381 #define HW_FTFE_FCCOB4_WR(x, v)  (ADDRESS_WRITE(hw_ftfe_fccob4_t, HW_FTFE_FCCOB4_ADDR(x), v))
01382 #define HW_FTFE_FCCOB4_SET(x, v) (HW_FTFE_FCCOB4_WR(x, HW_FTFE_FCCOB4_RD(x) |  (v)))
01383 #define HW_FTFE_FCCOB4_CLR(x, v) (HW_FTFE_FCCOB4_WR(x, HW_FTFE_FCCOB4_RD(x) & ~(v)))
01384 #define HW_FTFE_FCCOB4_TOG(x, v) (HW_FTFE_FCCOB4_WR(x, HW_FTFE_FCCOB4_RD(x) ^  (v)))
01385 /*@}*/
01386 
01387 /*
01388  * Constants & macros for individual FTFE_FCCOB4 bitfields
01389  */
01390 
01391 /*!
01392  * @name Register FTFE_FCCOB4, field CCOBn[7:0] (RW)
01393  *
01394  * The FCCOB register provides a command code and relevant parameters to the
01395  * memory controller. The individual registers that compose the FCCOB data set can
01396  * be written in any order, but you must provide all needed values, which vary
01397  * from command to command. First, set up all required FCCOB fields and then
01398  * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
01399  * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
01400  * by the user until the command completes (CCIF returns to 1). No command
01401  * buffering or queueing is provided; the next command can be loaded only after the
01402  * current command completes. Some commands return information to the FCCOB
01403  * registers. Any values returned to FCCOB are available for reading after the
01404  * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
01405  * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
01406  * the command code. This 8-bit value defines the command to be executed. The
01407  * command code is followed by the parameters required for this specific FTFE command,
01408  * typically an address and/or data values. The command parameter table is
01409  * written in terms of FCCOB Number (which is equivalent to the byte number). This
01410  * number is a reference to the FCCOB register name and is not the register address.
01411  * FCCOB NumberRefers to FCCOB register name, not register address Typical
01412  * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
01413  * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
01414  * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
01415  * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
01416  * register group uses a big endian addressing convention. For all command parameter
01417  * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
01418  * register number. The FCCOB register group may be read and written as
01419  * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
01420  */
01421 /*@{*/
01422 #define BP_FTFE_FCCOB4_CCOBn (0U)          /*!< Bit position for FTFE_FCCOB4_CCOBn. */
01423 #define BM_FTFE_FCCOB4_CCOBn (0xFFU)       /*!< Bit mask for FTFE_FCCOB4_CCOBn. */
01424 #define BS_FTFE_FCCOB4_CCOBn (8U)          /*!< Bit field size in bits for FTFE_FCCOB4_CCOBn. */
01425 
01426 /*! @brief Read current value of the FTFE_FCCOB4_CCOBn field. */
01427 #define BR_FTFE_FCCOB4_CCOBn(x) (HW_FTFE_FCCOB4(x).U)
01428 
01429 /*! @brief Format value for bitfield FTFE_FCCOB4_CCOBn. */
01430 #define BF_FTFE_FCCOB4_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB4_CCOBn) & BM_FTFE_FCCOB4_CCOBn)
01431 
01432 /*! @brief Set the CCOBn field to a new value. */
01433 #define BW_FTFE_FCCOB4_CCOBn(x, v) (HW_FTFE_FCCOB4_WR(x, v))
01434 /*@}*/
01435 
01436 /*******************************************************************************
01437  * HW_FTFE_FCCOBB - Flash Common Command Object Registers
01438  ******************************************************************************/
01439 
01440 /*!
01441  * @brief HW_FTFE_FCCOBB - Flash Common Command Object Registers (RW)
01442  *
01443  * Reset value: 0x00U
01444  *
01445  * The FCCOB register group provides 12 bytes for command codes and parameters.
01446  * The individual bytes within the set append a 0-B hex identifier to the FCCOB
01447  * register name: FCCOB0, FCCOB1, ..., FCCOBB.
01448  */
01449 typedef union _hw_ftfe_fccobb
01450 {
01451     uint8_t U;
01452     struct _hw_ftfe_fccobb_bitfields
01453     {
01454         uint8_t CCOBn : 8;             /*!< [7:0]  */
01455     } B;
01456 } hw_ftfe_fccobb_t;
01457 
01458 /*!
01459  * @name Constants and macros for entire FTFE_FCCOBB register
01460  */
01461 /*@{*/
01462 #define HW_FTFE_FCCOBB_ADDR(x)   ((x) + 0xCU)
01463 
01464 #define HW_FTFE_FCCOBB(x)        (*(__IO hw_ftfe_fccobb_t *) HW_FTFE_FCCOBB_ADDR(x))
01465 #define HW_FTFE_FCCOBB_RD(x)     (ADDRESS_READ(hw_ftfe_fccobb_t, HW_FTFE_FCCOBB_ADDR(x)))
01466 #define HW_FTFE_FCCOBB_WR(x, v)  (ADDRESS_WRITE(hw_ftfe_fccobb_t, HW_FTFE_FCCOBB_ADDR(x), v))
01467 #define HW_FTFE_FCCOBB_SET(x, v) (HW_FTFE_FCCOBB_WR(x, HW_FTFE_FCCOBB_RD(x) |  (v)))
01468 #define HW_FTFE_FCCOBB_CLR(x, v) (HW_FTFE_FCCOBB_WR(x, HW_FTFE_FCCOBB_RD(x) & ~(v)))
01469 #define HW_FTFE_FCCOBB_TOG(x, v) (HW_FTFE_FCCOBB_WR(x, HW_FTFE_FCCOBB_RD(x) ^  (v)))
01470 /*@}*/
01471 
01472 /*
01473  * Constants & macros for individual FTFE_FCCOBB bitfields
01474  */
01475 
01476 /*!
01477  * @name Register FTFE_FCCOBB, field CCOBn[7:0] (RW)
01478  *
01479  * The FCCOB register provides a command code and relevant parameters to the
01480  * memory controller. The individual registers that compose the FCCOB data set can
01481  * be written in any order, but you must provide all needed values, which vary
01482  * from command to command. First, set up all required FCCOB fields and then
01483  * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
01484  * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
01485  * by the user until the command completes (CCIF returns to 1). No command
01486  * buffering or queueing is provided; the next command can be loaded only after the
01487  * current command completes. Some commands return information to the FCCOB
01488  * registers. Any values returned to FCCOB are available for reading after the
01489  * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
01490  * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
01491  * the command code. This 8-bit value defines the command to be executed. The
01492  * command code is followed by the parameters required for this specific FTFE command,
01493  * typically an address and/or data values. The command parameter table is
01494  * written in terms of FCCOB Number (which is equivalent to the byte number). This
01495  * number is a reference to the FCCOB register name and is not the register address.
01496  * FCCOB NumberRefers to FCCOB register name, not register address Typical
01497  * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
01498  * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
01499  * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
01500  * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
01501  * register group uses a big endian addressing convention. For all command parameter
01502  * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
01503  * register number. The FCCOB register group may be read and written as
01504  * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
01505  */
01506 /*@{*/
01507 #define BP_FTFE_FCCOBB_CCOBn (0U)          /*!< Bit position for FTFE_FCCOBB_CCOBn. */
01508 #define BM_FTFE_FCCOBB_CCOBn (0xFFU)       /*!< Bit mask for FTFE_FCCOBB_CCOBn. */
01509 #define BS_FTFE_FCCOBB_CCOBn (8U)          /*!< Bit field size in bits for FTFE_FCCOBB_CCOBn. */
01510 
01511 /*! @brief Read current value of the FTFE_FCCOBB_CCOBn field. */
01512 #define BR_FTFE_FCCOBB_CCOBn(x) (HW_FTFE_FCCOBB(x).U)
01513 
01514 /*! @brief Format value for bitfield FTFE_FCCOBB_CCOBn. */
01515 #define BF_FTFE_FCCOBB_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOBB_CCOBn) & BM_FTFE_FCCOBB_CCOBn)
01516 
01517 /*! @brief Set the CCOBn field to a new value. */
01518 #define BW_FTFE_FCCOBB_CCOBn(x, v) (HW_FTFE_FCCOBB_WR(x, v))
01519 /*@}*/
01520 
01521 /*******************************************************************************
01522  * HW_FTFE_FCCOBA - Flash Common Command Object Registers
01523  ******************************************************************************/
01524 
01525 /*!
01526  * @brief HW_FTFE_FCCOBA - Flash Common Command Object Registers (RW)
01527  *
01528  * Reset value: 0x00U
01529  *
01530  * The FCCOB register group provides 12 bytes for command codes and parameters.
01531  * The individual bytes within the set append a 0-B hex identifier to the FCCOB
01532  * register name: FCCOB0, FCCOB1, ..., FCCOBB.
01533  */
01534 typedef union _hw_ftfe_fccoba
01535 {
01536     uint8_t U;
01537     struct _hw_ftfe_fccoba_bitfields
01538     {
01539         uint8_t CCOBn : 8;             /*!< [7:0]  */
01540     } B;
01541 } hw_ftfe_fccoba_t;
01542 
01543 /*!
01544  * @name Constants and macros for entire FTFE_FCCOBA register
01545  */
01546 /*@{*/
01547 #define HW_FTFE_FCCOBA_ADDR(x)   ((x) + 0xDU)
01548 
01549 #define HW_FTFE_FCCOBA(x)        (*(__IO hw_ftfe_fccoba_t *) HW_FTFE_FCCOBA_ADDR(x))
01550 #define HW_FTFE_FCCOBA_RD(x)     (ADDRESS_READ(hw_ftfe_fccoba_t, HW_FTFE_FCCOBA_ADDR(x)))
01551 #define HW_FTFE_FCCOBA_WR(x, v)  (ADDRESS_WRITE(hw_ftfe_fccoba_t, HW_FTFE_FCCOBA_ADDR(x), v))
01552 #define HW_FTFE_FCCOBA_SET(x, v) (HW_FTFE_FCCOBA_WR(x, HW_FTFE_FCCOBA_RD(x) |  (v)))
01553 #define HW_FTFE_FCCOBA_CLR(x, v) (HW_FTFE_FCCOBA_WR(x, HW_FTFE_FCCOBA_RD(x) & ~(v)))
01554 #define HW_FTFE_FCCOBA_TOG(x, v) (HW_FTFE_FCCOBA_WR(x, HW_FTFE_FCCOBA_RD(x) ^  (v)))
01555 /*@}*/
01556 
01557 /*
01558  * Constants & macros for individual FTFE_FCCOBA bitfields
01559  */
01560 
01561 /*!
01562  * @name Register FTFE_FCCOBA, field CCOBn[7:0] (RW)
01563  *
01564  * The FCCOB register provides a command code and relevant parameters to the
01565  * memory controller. The individual registers that compose the FCCOB data set can
01566  * be written in any order, but you must provide all needed values, which vary
01567  * from command to command. First, set up all required FCCOB fields and then
01568  * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
01569  * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
01570  * by the user until the command completes (CCIF returns to 1). No command
01571  * buffering or queueing is provided; the next command can be loaded only after the
01572  * current command completes. Some commands return information to the FCCOB
01573  * registers. Any values returned to FCCOB are available for reading after the
01574  * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
01575  * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
01576  * the command code. This 8-bit value defines the command to be executed. The
01577  * command code is followed by the parameters required for this specific FTFE command,
01578  * typically an address and/or data values. The command parameter table is
01579  * written in terms of FCCOB Number (which is equivalent to the byte number). This
01580  * number is a reference to the FCCOB register name and is not the register address.
01581  * FCCOB NumberRefers to FCCOB register name, not register address Typical
01582  * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
01583  * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
01584  * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
01585  * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
01586  * register group uses a big endian addressing convention. For all command parameter
01587  * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
01588  * register number. The FCCOB register group may be read and written as
01589  * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
01590  */
01591 /*@{*/
01592 #define BP_FTFE_FCCOBA_CCOBn (0U)          /*!< Bit position for FTFE_FCCOBA_CCOBn. */
01593 #define BM_FTFE_FCCOBA_CCOBn (0xFFU)       /*!< Bit mask for FTFE_FCCOBA_CCOBn. */
01594 #define BS_FTFE_FCCOBA_CCOBn (8U)          /*!< Bit field size in bits for FTFE_FCCOBA_CCOBn. */
01595 
01596 /*! @brief Read current value of the FTFE_FCCOBA_CCOBn field. */
01597 #define BR_FTFE_FCCOBA_CCOBn(x) (HW_FTFE_FCCOBA(x).U)
01598 
01599 /*! @brief Format value for bitfield FTFE_FCCOBA_CCOBn. */
01600 #define BF_FTFE_FCCOBA_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOBA_CCOBn) & BM_FTFE_FCCOBA_CCOBn)
01601 
01602 /*! @brief Set the CCOBn field to a new value. */
01603 #define BW_FTFE_FCCOBA_CCOBn(x, v) (HW_FTFE_FCCOBA_WR(x, v))
01604 /*@}*/
01605 
01606 /*******************************************************************************
01607  * HW_FTFE_FCCOB9 - Flash Common Command Object Registers
01608  ******************************************************************************/
01609 
01610 /*!
01611  * @brief HW_FTFE_FCCOB9 - Flash Common Command Object Registers (RW)
01612  *
01613  * Reset value: 0x00U
01614  *
01615  * The FCCOB register group provides 12 bytes for command codes and parameters.
01616  * The individual bytes within the set append a 0-B hex identifier to the FCCOB
01617  * register name: FCCOB0, FCCOB1, ..., FCCOBB.
01618  */
01619 typedef union _hw_ftfe_fccob9
01620 {
01621     uint8_t U;
01622     struct _hw_ftfe_fccob9_bitfields
01623     {
01624         uint8_t CCOBn : 8;             /*!< [7:0]  */
01625     } B;
01626 } hw_ftfe_fccob9_t;
01627 
01628 /*!
01629  * @name Constants and macros for entire FTFE_FCCOB9 register
01630  */
01631 /*@{*/
01632 #define HW_FTFE_FCCOB9_ADDR(x)   ((x) + 0xEU)
01633 
01634 #define HW_FTFE_FCCOB9(x)        (*(__IO hw_ftfe_fccob9_t *) HW_FTFE_FCCOB9_ADDR(x))
01635 #define HW_FTFE_FCCOB9_RD(x)     (ADDRESS_READ(hw_ftfe_fccob9_t, HW_FTFE_FCCOB9_ADDR(x)))
01636 #define HW_FTFE_FCCOB9_WR(x, v)  (ADDRESS_WRITE(hw_ftfe_fccob9_t, HW_FTFE_FCCOB9_ADDR(x), v))
01637 #define HW_FTFE_FCCOB9_SET(x, v) (HW_FTFE_FCCOB9_WR(x, HW_FTFE_FCCOB9_RD(x) |  (v)))
01638 #define HW_FTFE_FCCOB9_CLR(x, v) (HW_FTFE_FCCOB9_WR(x, HW_FTFE_FCCOB9_RD(x) & ~(v)))
01639 #define HW_FTFE_FCCOB9_TOG(x, v) (HW_FTFE_FCCOB9_WR(x, HW_FTFE_FCCOB9_RD(x) ^  (v)))
01640 /*@}*/
01641 
01642 /*
01643  * Constants & macros for individual FTFE_FCCOB9 bitfields
01644  */
01645 
01646 /*!
01647  * @name Register FTFE_FCCOB9, field CCOBn[7:0] (RW)
01648  *
01649  * The FCCOB register provides a command code and relevant parameters to the
01650  * memory controller. The individual registers that compose the FCCOB data set can
01651  * be written in any order, but you must provide all needed values, which vary
01652  * from command to command. First, set up all required FCCOB fields and then
01653  * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
01654  * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
01655  * by the user until the command completes (CCIF returns to 1). No command
01656  * buffering or queueing is provided; the next command can be loaded only after the
01657  * current command completes. Some commands return information to the FCCOB
01658  * registers. Any values returned to FCCOB are available for reading after the
01659  * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
01660  * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
01661  * the command code. This 8-bit value defines the command to be executed. The
01662  * command code is followed by the parameters required for this specific FTFE command,
01663  * typically an address and/or data values. The command parameter table is
01664  * written in terms of FCCOB Number (which is equivalent to the byte number). This
01665  * number is a reference to the FCCOB register name and is not the register address.
01666  * FCCOB NumberRefers to FCCOB register name, not register address Typical
01667  * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
01668  * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
01669  * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
01670  * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
01671  * register group uses a big endian addressing convention. For all command parameter
01672  * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
01673  * register number. The FCCOB register group may be read and written as
01674  * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
01675  */
01676 /*@{*/
01677 #define BP_FTFE_FCCOB9_CCOBn (0U)          /*!< Bit position for FTFE_FCCOB9_CCOBn. */
01678 #define BM_FTFE_FCCOB9_CCOBn (0xFFU)       /*!< Bit mask for FTFE_FCCOB9_CCOBn. */
01679 #define BS_FTFE_FCCOB9_CCOBn (8U)          /*!< Bit field size in bits for FTFE_FCCOB9_CCOBn. */
01680 
01681 /*! @brief Read current value of the FTFE_FCCOB9_CCOBn field. */
01682 #define BR_FTFE_FCCOB9_CCOBn(x) (HW_FTFE_FCCOB9(x).U)
01683 
01684 /*! @brief Format value for bitfield FTFE_FCCOB9_CCOBn. */
01685 #define BF_FTFE_FCCOB9_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB9_CCOBn) & BM_FTFE_FCCOB9_CCOBn)
01686 
01687 /*! @brief Set the CCOBn field to a new value. */
01688 #define BW_FTFE_FCCOB9_CCOBn(x, v) (HW_FTFE_FCCOB9_WR(x, v))
01689 /*@}*/
01690 
01691 /*******************************************************************************
01692  * HW_FTFE_FCCOB8 - Flash Common Command Object Registers
01693  ******************************************************************************/
01694 
01695 /*!
01696  * @brief HW_FTFE_FCCOB8 - Flash Common Command Object Registers (RW)
01697  *
01698  * Reset value: 0x00U
01699  *
01700  * The FCCOB register group provides 12 bytes for command codes and parameters.
01701  * The individual bytes within the set append a 0-B hex identifier to the FCCOB
01702  * register name: FCCOB0, FCCOB1, ..., FCCOBB.
01703  */
01704 typedef union _hw_ftfe_fccob8
01705 {
01706     uint8_t U;
01707     struct _hw_ftfe_fccob8_bitfields
01708     {
01709         uint8_t CCOBn : 8;             /*!< [7:0]  */
01710     } B;
01711 } hw_ftfe_fccob8_t;
01712 
01713 /*!
01714  * @name Constants and macros for entire FTFE_FCCOB8 register
01715  */
01716 /*@{*/
01717 #define HW_FTFE_FCCOB8_ADDR(x)   ((x) + 0xFU)
01718 
01719 #define HW_FTFE_FCCOB8(x)        (*(__IO hw_ftfe_fccob8_t *) HW_FTFE_FCCOB8_ADDR(x))
01720 #define HW_FTFE_FCCOB8_RD(x)     (ADDRESS_READ(hw_ftfe_fccob8_t, HW_FTFE_FCCOB8_ADDR(x)))
01721 #define HW_FTFE_FCCOB8_WR(x, v)  (ADDRESS_WRITE(hw_ftfe_fccob8_t, HW_FTFE_FCCOB8_ADDR(x), v))
01722 #define HW_FTFE_FCCOB8_SET(x, v) (HW_FTFE_FCCOB8_WR(x, HW_FTFE_FCCOB8_RD(x) |  (v)))
01723 #define HW_FTFE_FCCOB8_CLR(x, v) (HW_FTFE_FCCOB8_WR(x, HW_FTFE_FCCOB8_RD(x) & ~(v)))
01724 #define HW_FTFE_FCCOB8_TOG(x, v) (HW_FTFE_FCCOB8_WR(x, HW_FTFE_FCCOB8_RD(x) ^  (v)))
01725 /*@}*/
01726 
01727 /*
01728  * Constants & macros for individual FTFE_FCCOB8 bitfields
01729  */
01730 
01731 /*!
01732  * @name Register FTFE_FCCOB8, field CCOBn[7:0] (RW)
01733  *
01734  * The FCCOB register provides a command code and relevant parameters to the
01735  * memory controller. The individual registers that compose the FCCOB data set can
01736  * be written in any order, but you must provide all needed values, which vary
01737  * from command to command. First, set up all required FCCOB fields and then
01738  * initiate the command's execution by writing a 1 to the FSTAT[CCIF] bit. This clears
01739  * the CCIF bit, which locks all FCCOB parameter fields and they cannot be changed
01740  * by the user until the command completes (CCIF returns to 1). No command
01741  * buffering or queueing is provided; the next command can be loaded only after the
01742  * current command completes. Some commands return information to the FCCOB
01743  * registers. Any values returned to FCCOB are available for reading after the
01744  * FSTAT[CCIF] flag returns to 1 by the memory controller. The following table shows a
01745  * generic FTFE command format. The first FCCOB register, FCCOB0, always contains
01746  * the command code. This 8-bit value defines the command to be executed. The
01747  * command code is followed by the parameters required for this specific FTFE command,
01748  * typically an address and/or data values. The command parameter table is
01749  * written in terms of FCCOB Number (which is equivalent to the byte number). This
01750  * number is a reference to the FCCOB register name and is not the register address.
01751  * FCCOB NumberRefers to FCCOB register name, not register address Typical
01752  * Command Parameter Contents [7:0] 0 FCMD (a code that defines the FTFE command) 1
01753  * Flash address [23:16] 2 Flash address [15:8] 3 Flash address [7:0] 4 Data Byte 0
01754  * 5 Data Byte 1 6 Data Byte 2 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 A Data
01755  * Byte 6 B Data Byte 7 FCCOB Endianness and Multi-Byte Access: The FCCOB
01756  * register group uses a big endian addressing convention. For all command parameter
01757  * fields larger than 1 byte, the most significant data resides in the lowest FCCOB
01758  * register number. The FCCOB register group may be read and written as
01759  * individual bytes, aligned words (2 bytes) or aligned longwords (4 bytes).
01760  */
01761 /*@{*/
01762 #define BP_FTFE_FCCOB8_CCOBn (0U)          /*!< Bit position for FTFE_FCCOB8_CCOBn. */
01763 #define BM_FTFE_FCCOB8_CCOBn (0xFFU)       /*!< Bit mask for FTFE_FCCOB8_CCOBn. */
01764 #define BS_FTFE_FCCOB8_CCOBn (8U)          /*!< Bit field size in bits for FTFE_FCCOB8_CCOBn. */
01765 
01766 /*! @brief Read current value of the FTFE_FCCOB8_CCOBn field. */
01767 #define BR_FTFE_FCCOB8_CCOBn(x) (HW_FTFE_FCCOB8(x).U)
01768 
01769 /*! @brief Format value for bitfield FTFE_FCCOB8_CCOBn. */
01770 #define BF_FTFE_FCCOB8_CCOBn(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FCCOB8_CCOBn) & BM_FTFE_FCCOB8_CCOBn)
01771 
01772 /*! @brief Set the CCOBn field to a new value. */
01773 #define BW_FTFE_FCCOB8_CCOBn(x, v) (HW_FTFE_FCCOB8_WR(x, v))
01774 /*@}*/
01775 
01776 /*******************************************************************************
01777  * HW_FTFE_FPROT3 - Program Flash Protection Registers
01778  ******************************************************************************/
01779 
01780 /*!
01781  * @brief HW_FTFE_FPROT3 - Program Flash Protection Registers (RW)
01782  *
01783  * Reset value: 0x00U
01784  *
01785  * The FPROT registers define which program flash regions are protected from
01786  * program and erase operations. Protected flash regions cannot have their content
01787  * changed; that is, these regions cannot be programmed and cannot be erased by
01788  * any FTFE command. Unprotected regions can be changed by program and erase
01789  * operations. The four FPROT registers allow up to 32 protectable regions of equal
01790  * memory size. Program flash protection register Program flash protection bits
01791  * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
01792  * the reset sequence, the FPROT registers are loaded with the contents of the
01793  * program flash protection bytes in the Flash Configuration Field as indicated in
01794  * the following table. Program flash protection register Flash Configuration Field
01795  * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
01796  * change the program flash protection that is loaded during the reset sequence,
01797  * unprotect the sector of program flash memory that contains the Flash
01798  * Configuration Field. Then, reprogram the program flash protection byte.
01799  */
01800 typedef union _hw_ftfe_fprot3
01801 {
01802     uint8_t U;
01803     struct _hw_ftfe_fprot3_bitfields
01804     {
01805         uint8_t PROT : 8;              /*!< [7:0] Program Flash Region Protect */
01806     } B;
01807 } hw_ftfe_fprot3_t;
01808 
01809 /*!
01810  * @name Constants and macros for entire FTFE_FPROT3 register
01811  */
01812 /*@{*/
01813 #define HW_FTFE_FPROT3_ADDR(x)   ((x) + 0x10U)
01814 
01815 #define HW_FTFE_FPROT3(x)        (*(__IO hw_ftfe_fprot3_t *) HW_FTFE_FPROT3_ADDR(x))
01816 #define HW_FTFE_FPROT3_RD(x)     (ADDRESS_READ(hw_ftfe_fprot3_t, HW_FTFE_FPROT3_ADDR(x)))
01817 #define HW_FTFE_FPROT3_WR(x, v)  (ADDRESS_WRITE(hw_ftfe_fprot3_t, HW_FTFE_FPROT3_ADDR(x), v))
01818 #define HW_FTFE_FPROT3_SET(x, v) (HW_FTFE_FPROT3_WR(x, HW_FTFE_FPROT3_RD(x) |  (v)))
01819 #define HW_FTFE_FPROT3_CLR(x, v) (HW_FTFE_FPROT3_WR(x, HW_FTFE_FPROT3_RD(x) & ~(v)))
01820 #define HW_FTFE_FPROT3_TOG(x, v) (HW_FTFE_FPROT3_WR(x, HW_FTFE_FPROT3_RD(x) ^  (v)))
01821 /*@}*/
01822 
01823 /*
01824  * Constants & macros for individual FTFE_FPROT3 bitfields
01825  */
01826 
01827 /*!
01828  * @name Register FTFE_FPROT3, field PROT[7:0] (RW)
01829  *
01830  * Each program flash region can be protected from program and erase operations
01831  * by setting the associated PROT bit. In NVM Normal mode: The protection can
01832  * only be increased, meaning that currently unprotected memory can be protected,
01833  * but currently protected memory cannot be unprotected. Since unprotected regions
01834  * are marked with a 1 and protected regions use a 0, only writes changing 1s to
01835  * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
01836  * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
01837  * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
01838  * writable without restriction. Unprotected areas can be protected and protected
01839  * areas can be unprotected. The user must never write to any FPROT register while
01840  * a command is running (CCIF=0). Trying to alter data in any protected area in
01841  * the program flash memory results in a protection violation error and sets the
01842  * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
01843  * if it contains any protected region.
01844  *
01845  * Values:
01846  * - 0 - Program flash region is protected.
01847  * - 1 - Program flash region is not protected
01848  */
01849 /*@{*/
01850 #define BP_FTFE_FPROT3_PROT  (0U)          /*!< Bit position for FTFE_FPROT3_PROT. */
01851 #define BM_FTFE_FPROT3_PROT  (0xFFU)       /*!< Bit mask for FTFE_FPROT3_PROT. */
01852 #define BS_FTFE_FPROT3_PROT  (8U)          /*!< Bit field size in bits for FTFE_FPROT3_PROT. */
01853 
01854 /*! @brief Read current value of the FTFE_FPROT3_PROT field. */
01855 #define BR_FTFE_FPROT3_PROT(x) (HW_FTFE_FPROT3(x).U)
01856 
01857 /*! @brief Format value for bitfield FTFE_FPROT3_PROT. */
01858 #define BF_FTFE_FPROT3_PROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FPROT3_PROT) & BM_FTFE_FPROT3_PROT)
01859 
01860 /*! @brief Set the PROT field to a new value. */
01861 #define BW_FTFE_FPROT3_PROT(x, v) (HW_FTFE_FPROT3_WR(x, v))
01862 /*@}*/
01863 
01864 /*******************************************************************************
01865  * HW_FTFE_FPROT2 - Program Flash Protection Registers
01866  ******************************************************************************/
01867 
01868 /*!
01869  * @brief HW_FTFE_FPROT2 - Program Flash Protection Registers (RW)
01870  *
01871  * Reset value: 0x00U
01872  *
01873  * The FPROT registers define which program flash regions are protected from
01874  * program and erase operations. Protected flash regions cannot have their content
01875  * changed; that is, these regions cannot be programmed and cannot be erased by
01876  * any FTFE command. Unprotected regions can be changed by program and erase
01877  * operations. The four FPROT registers allow up to 32 protectable regions of equal
01878  * memory size. Program flash protection register Program flash protection bits
01879  * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
01880  * the reset sequence, the FPROT registers are loaded with the contents of the
01881  * program flash protection bytes in the Flash Configuration Field as indicated in
01882  * the following table. Program flash protection register Flash Configuration Field
01883  * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
01884  * change the program flash protection that is loaded during the reset sequence,
01885  * unprotect the sector of program flash memory that contains the Flash
01886  * Configuration Field. Then, reprogram the program flash protection byte.
01887  */
01888 typedef union _hw_ftfe_fprot2
01889 {
01890     uint8_t U;
01891     struct _hw_ftfe_fprot2_bitfields
01892     {
01893         uint8_t PROT : 8;              /*!< [7:0] Program Flash Region Protect */
01894     } B;
01895 } hw_ftfe_fprot2_t;
01896 
01897 /*!
01898  * @name Constants and macros for entire FTFE_FPROT2 register
01899  */
01900 /*@{*/
01901 #define HW_FTFE_FPROT2_ADDR(x)   ((x) + 0x11U)
01902 
01903 #define HW_FTFE_FPROT2(x)        (*(__IO hw_ftfe_fprot2_t *) HW_FTFE_FPROT2_ADDR(x))
01904 #define HW_FTFE_FPROT2_RD(x)     (ADDRESS_READ(hw_ftfe_fprot2_t, HW_FTFE_FPROT2_ADDR(x)))
01905 #define HW_FTFE_FPROT2_WR(x, v)  (ADDRESS_WRITE(hw_ftfe_fprot2_t, HW_FTFE_FPROT2_ADDR(x), v))
01906 #define HW_FTFE_FPROT2_SET(x, v) (HW_FTFE_FPROT2_WR(x, HW_FTFE_FPROT2_RD(x) |  (v)))
01907 #define HW_FTFE_FPROT2_CLR(x, v) (HW_FTFE_FPROT2_WR(x, HW_FTFE_FPROT2_RD(x) & ~(v)))
01908 #define HW_FTFE_FPROT2_TOG(x, v) (HW_FTFE_FPROT2_WR(x, HW_FTFE_FPROT2_RD(x) ^  (v)))
01909 /*@}*/
01910 
01911 /*
01912  * Constants & macros for individual FTFE_FPROT2 bitfields
01913  */
01914 
01915 /*!
01916  * @name Register FTFE_FPROT2, field PROT[7:0] (RW)
01917  *
01918  * Each program flash region can be protected from program and erase operations
01919  * by setting the associated PROT bit. In NVM Normal mode: The protection can
01920  * only be increased, meaning that currently unprotected memory can be protected,
01921  * but currently protected memory cannot be unprotected. Since unprotected regions
01922  * are marked with a 1 and protected regions use a 0, only writes changing 1s to
01923  * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
01924  * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
01925  * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
01926  * writable without restriction. Unprotected areas can be protected and protected
01927  * areas can be unprotected. The user must never write to any FPROT register while
01928  * a command is running (CCIF=0). Trying to alter data in any protected area in
01929  * the program flash memory results in a protection violation error and sets the
01930  * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
01931  * if it contains any protected region.
01932  *
01933  * Values:
01934  * - 0 - Program flash region is protected.
01935  * - 1 - Program flash region is not protected
01936  */
01937 /*@{*/
01938 #define BP_FTFE_FPROT2_PROT  (0U)          /*!< Bit position for FTFE_FPROT2_PROT. */
01939 #define BM_FTFE_FPROT2_PROT  (0xFFU)       /*!< Bit mask for FTFE_FPROT2_PROT. */
01940 #define BS_FTFE_FPROT2_PROT  (8U)          /*!< Bit field size in bits for FTFE_FPROT2_PROT. */
01941 
01942 /*! @brief Read current value of the FTFE_FPROT2_PROT field. */
01943 #define BR_FTFE_FPROT2_PROT(x) (HW_FTFE_FPROT2(x).U)
01944 
01945 /*! @brief Format value for bitfield FTFE_FPROT2_PROT. */
01946 #define BF_FTFE_FPROT2_PROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FPROT2_PROT) & BM_FTFE_FPROT2_PROT)
01947 
01948 /*! @brief Set the PROT field to a new value. */
01949 #define BW_FTFE_FPROT2_PROT(x, v) (HW_FTFE_FPROT2_WR(x, v))
01950 /*@}*/
01951 
01952 /*******************************************************************************
01953  * HW_FTFE_FPROT1 - Program Flash Protection Registers
01954  ******************************************************************************/
01955 
01956 /*!
01957  * @brief HW_FTFE_FPROT1 - Program Flash Protection Registers (RW)
01958  *
01959  * Reset value: 0x00U
01960  *
01961  * The FPROT registers define which program flash regions are protected from
01962  * program and erase operations. Protected flash regions cannot have their content
01963  * changed; that is, these regions cannot be programmed and cannot be erased by
01964  * any FTFE command. Unprotected regions can be changed by program and erase
01965  * operations. The four FPROT registers allow up to 32 protectable regions of equal
01966  * memory size. Program flash protection register Program flash protection bits
01967  * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
01968  * the reset sequence, the FPROT registers are loaded with the contents of the
01969  * program flash protection bytes in the Flash Configuration Field as indicated in
01970  * the following table. Program flash protection register Flash Configuration Field
01971  * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
01972  * change the program flash protection that is loaded during the reset sequence,
01973  * unprotect the sector of program flash memory that contains the Flash
01974  * Configuration Field. Then, reprogram the program flash protection byte.
01975  */
01976 typedef union _hw_ftfe_fprot1
01977 {
01978     uint8_t U;
01979     struct _hw_ftfe_fprot1_bitfields
01980     {
01981         uint8_t PROT : 8;              /*!< [7:0] Program Flash Region Protect */
01982     } B;
01983 } hw_ftfe_fprot1_t;
01984 
01985 /*!
01986  * @name Constants and macros for entire FTFE_FPROT1 register
01987  */
01988 /*@{*/
01989 #define HW_FTFE_FPROT1_ADDR(x)   ((x) + 0x12U)
01990 
01991 #define HW_FTFE_FPROT1(x)        (*(__IO hw_ftfe_fprot1_t *) HW_FTFE_FPROT1_ADDR(x))
01992 #define HW_FTFE_FPROT1_RD(x)     (ADDRESS_READ(hw_ftfe_fprot1_t, HW_FTFE_FPROT1_ADDR(x)))
01993 #define HW_FTFE_FPROT1_WR(x, v)  (ADDRESS_WRITE(hw_ftfe_fprot1_t, HW_FTFE_FPROT1_ADDR(x), v))
01994 #define HW_FTFE_FPROT1_SET(x, v) (HW_FTFE_FPROT1_WR(x, HW_FTFE_FPROT1_RD(x) |  (v)))
01995 #define HW_FTFE_FPROT1_CLR(x, v) (HW_FTFE_FPROT1_WR(x, HW_FTFE_FPROT1_RD(x) & ~(v)))
01996 #define HW_FTFE_FPROT1_TOG(x, v) (HW_FTFE_FPROT1_WR(x, HW_FTFE_FPROT1_RD(x) ^  (v)))
01997 /*@}*/
01998 
01999 /*
02000  * Constants & macros for individual FTFE_FPROT1 bitfields
02001  */
02002 
02003 /*!
02004  * @name Register FTFE_FPROT1, field PROT[7:0] (RW)
02005  *
02006  * Each program flash region can be protected from program and erase operations
02007  * by setting the associated PROT bit. In NVM Normal mode: The protection can
02008  * only be increased, meaning that currently unprotected memory can be protected,
02009  * but currently protected memory cannot be unprotected. Since unprotected regions
02010  * are marked with a 1 and protected regions use a 0, only writes changing 1s to
02011  * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
02012  * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
02013  * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
02014  * writable without restriction. Unprotected areas can be protected and protected
02015  * areas can be unprotected. The user must never write to any FPROT register while
02016  * a command is running (CCIF=0). Trying to alter data in any protected area in
02017  * the program flash memory results in a protection violation error and sets the
02018  * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
02019  * if it contains any protected region.
02020  *
02021  * Values:
02022  * - 0 - Program flash region is protected.
02023  * - 1 - Program flash region is not protected
02024  */
02025 /*@{*/
02026 #define BP_FTFE_FPROT1_PROT  (0U)          /*!< Bit position for FTFE_FPROT1_PROT. */
02027 #define BM_FTFE_FPROT1_PROT  (0xFFU)       /*!< Bit mask for FTFE_FPROT1_PROT. */
02028 #define BS_FTFE_FPROT1_PROT  (8U)          /*!< Bit field size in bits for FTFE_FPROT1_PROT. */
02029 
02030 /*! @brief Read current value of the FTFE_FPROT1_PROT field. */
02031 #define BR_FTFE_FPROT1_PROT(x) (HW_FTFE_FPROT1(x).U)
02032 
02033 /*! @brief Format value for bitfield FTFE_FPROT1_PROT. */
02034 #define BF_FTFE_FPROT1_PROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FPROT1_PROT) & BM_FTFE_FPROT1_PROT)
02035 
02036 /*! @brief Set the PROT field to a new value. */
02037 #define BW_FTFE_FPROT1_PROT(x, v) (HW_FTFE_FPROT1_WR(x, v))
02038 /*@}*/
02039 
02040 /*******************************************************************************
02041  * HW_FTFE_FPROT0 - Program Flash Protection Registers
02042  ******************************************************************************/
02043 
02044 /*!
02045  * @brief HW_FTFE_FPROT0 - Program Flash Protection Registers (RW)
02046  *
02047  * Reset value: 0x00U
02048  *
02049  * The FPROT registers define which program flash regions are protected from
02050  * program and erase operations. Protected flash regions cannot have their content
02051  * changed; that is, these regions cannot be programmed and cannot be erased by
02052  * any FTFE command. Unprotected regions can be changed by program and erase
02053  * operations. The four FPROT registers allow up to 32 protectable regions of equal
02054  * memory size. Program flash protection register Program flash protection bits
02055  * FPROT0 PROT[31:24] FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During
02056  * the reset sequence, the FPROT registers are loaded with the contents of the
02057  * program flash protection bytes in the Flash Configuration Field as indicated in
02058  * the following table. Program flash protection register Flash Configuration Field
02059  * offset address FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To
02060  * change the program flash protection that is loaded during the reset sequence,
02061  * unprotect the sector of program flash memory that contains the Flash
02062  * Configuration Field. Then, reprogram the program flash protection byte.
02063  */
02064 typedef union _hw_ftfe_fprot0
02065 {
02066     uint8_t U;
02067     struct _hw_ftfe_fprot0_bitfields
02068     {
02069         uint8_t PROT : 8;              /*!< [7:0] Program Flash Region Protect */
02070     } B;
02071 } hw_ftfe_fprot0_t;
02072 
02073 /*!
02074  * @name Constants and macros for entire FTFE_FPROT0 register
02075  */
02076 /*@{*/
02077 #define HW_FTFE_FPROT0_ADDR(x)   ((x) + 0x13U)
02078 
02079 #define HW_FTFE_FPROT0(x)        (*(__IO hw_ftfe_fprot0_t *) HW_FTFE_FPROT0_ADDR(x))
02080 #define HW_FTFE_FPROT0_RD(x)     (ADDRESS_READ(hw_ftfe_fprot0_t, HW_FTFE_FPROT0_ADDR(x)))
02081 #define HW_FTFE_FPROT0_WR(x, v)  (ADDRESS_WRITE(hw_ftfe_fprot0_t, HW_FTFE_FPROT0_ADDR(x), v))
02082 #define HW_FTFE_FPROT0_SET(x, v) (HW_FTFE_FPROT0_WR(x, HW_FTFE_FPROT0_RD(x) |  (v)))
02083 #define HW_FTFE_FPROT0_CLR(x, v) (HW_FTFE_FPROT0_WR(x, HW_FTFE_FPROT0_RD(x) & ~(v)))
02084 #define HW_FTFE_FPROT0_TOG(x, v) (HW_FTFE_FPROT0_WR(x, HW_FTFE_FPROT0_RD(x) ^  (v)))
02085 /*@}*/
02086 
02087 /*
02088  * Constants & macros for individual FTFE_FPROT0 bitfields
02089  */
02090 
02091 /*!
02092  * @name Register FTFE_FPROT0, field PROT[7:0] (RW)
02093  *
02094  * Each program flash region can be protected from program and erase operations
02095  * by setting the associated PROT bit. In NVM Normal mode: The protection can
02096  * only be increased, meaning that currently unprotected memory can be protected,
02097  * but currently protected memory cannot be unprotected. Since unprotected regions
02098  * are marked with a 1 and protected regions use a 0, only writes changing 1s to
02099  * 0s are accepted. This 1-to-0 transition check is performed on a bit-by-bit
02100  * basis. Those FPROT bits with 1-to-0 transitions are accepted while all bits with
02101  * 0-to-1 transitions are ignored. In NVM Special mode: All bits of FPROT are
02102  * writable without restriction. Unprotected areas can be protected and protected
02103  * areas can be unprotected. The user must never write to any FPROT register while
02104  * a command is running (CCIF=0). Trying to alter data in any protected area in
02105  * the program flash memory results in a protection violation error and sets the
02106  * FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible
02107  * if it contains any protected region.
02108  *
02109  * Values:
02110  * - 0 - Program flash region is protected.
02111  * - 1 - Program flash region is not protected
02112  */
02113 /*@{*/
02114 #define BP_FTFE_FPROT0_PROT  (0U)          /*!< Bit position for FTFE_FPROT0_PROT. */
02115 #define BM_FTFE_FPROT0_PROT  (0xFFU)       /*!< Bit mask for FTFE_FPROT0_PROT. */
02116 #define BS_FTFE_FPROT0_PROT  (8U)          /*!< Bit field size in bits for FTFE_FPROT0_PROT. */
02117 
02118 /*! @brief Read current value of the FTFE_FPROT0_PROT field. */
02119 #define BR_FTFE_FPROT0_PROT(x) (HW_FTFE_FPROT0(x).U)
02120 
02121 /*! @brief Format value for bitfield FTFE_FPROT0_PROT. */
02122 #define BF_FTFE_FPROT0_PROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FPROT0_PROT) & BM_FTFE_FPROT0_PROT)
02123 
02124 /*! @brief Set the PROT field to a new value. */
02125 #define BW_FTFE_FPROT0_PROT(x, v) (HW_FTFE_FPROT0_WR(x, v))
02126 /*@}*/
02127 
02128 /*******************************************************************************
02129  * HW_FTFE_FEPROT - EEPROM Protection Register
02130  ******************************************************************************/
02131 
02132 /*!
02133  * @brief HW_FTFE_FEPROT - EEPROM Protection Register (RW)
02134  *
02135  * Reset value: 0x00U
02136  *
02137  * For devices with FlexNVM: The FEPROT register defines which EEPROM regions of
02138  * the FlexRAM are protected against program and erase operations. Protected
02139  * EEPROM regions cannot have their content changed by writing to it. Unprotected
02140  * regions can be changed by writing to the FlexRAM. For devices with program flash
02141  * only: This register is reserved and not used.
02142  */
02143 typedef union _hw_ftfe_feprot
02144 {
02145     uint8_t U;
02146     struct _hw_ftfe_feprot_bitfields
02147     {
02148         uint8_t EPROT : 8;             /*!< [7:0] EEPROM Region Protect */
02149     } B;
02150 } hw_ftfe_feprot_t;
02151 
02152 /*!
02153  * @name Constants and macros for entire FTFE_FEPROT register
02154  */
02155 /*@{*/
02156 #define HW_FTFE_FEPROT_ADDR(x)   ((x) + 0x16U)
02157 
02158 #define HW_FTFE_FEPROT(x)        (*(__IO hw_ftfe_feprot_t *) HW_FTFE_FEPROT_ADDR(x))
02159 #define HW_FTFE_FEPROT_RD(x)     (ADDRESS_READ(hw_ftfe_feprot_t, HW_FTFE_FEPROT_ADDR(x)))
02160 #define HW_FTFE_FEPROT_WR(x, v)  (ADDRESS_WRITE(hw_ftfe_feprot_t, HW_FTFE_FEPROT_ADDR(x), v))
02161 #define HW_FTFE_FEPROT_SET(x, v) (HW_FTFE_FEPROT_WR(x, HW_FTFE_FEPROT_RD(x) |  (v)))
02162 #define HW_FTFE_FEPROT_CLR(x, v) (HW_FTFE_FEPROT_WR(x, HW_FTFE_FEPROT_RD(x) & ~(v)))
02163 #define HW_FTFE_FEPROT_TOG(x, v) (HW_FTFE_FEPROT_WR(x, HW_FTFE_FEPROT_RD(x) ^  (v)))
02164 /*@}*/
02165 
02166 /*
02167  * Constants & macros for individual FTFE_FEPROT bitfields
02168  */
02169 
02170 /*!
02171  * @name Register FTFE_FEPROT, field EPROT[7:0] (RW)
02172  *
02173  * For devices with program flash only: Reserved For devices with FlexNVM:
02174  * Individual EEPROM regions can be protected from alteration by setting the
02175  * associated EPROT bit. The EPROT bits are not used when the FlexNVM Partition Code is
02176  * set to data flash only. When the FlexNVM Partition Code is set to data flash and
02177  * EEPROM or EEPROM only, each EPROT bit covers one-eighth of the configured
02178  * EEPROM data (see the EEPROM Data Set Size parameter description). In NVM Normal
02179  * mode: The protection can only be increased. This means that
02180  * currently-unprotected memory can be protected, but currently-protected memory cannot be
02181  * unprotected. Since unprotected regions are marked with a 1 and protected regions use a
02182  * 0, only writes changing 1s to 0s are accepted. This 1-to-0 transition check is
02183  * performed on a bit-by-bit basis. Those FEPROT bits with 1-to-0 transitions
02184  * are accepted while all bits with 0-to-1 transitions are ignored. In NVM Special
02185  * mode: All bits of the FEPROT register are writable without restriction.
02186  * Unprotected areas can be protected and protected areas can be unprotected. Never
02187  * write to the FEPROT register while a command is running (CCIF=0). Reset: During
02188  * the reset sequence, the FEPROT register is loaded with the contents of the
02189  * FlexRAM protection byte in the Flash Configuration Field located in program flash.
02190  * The flash basis for the reset values is signified by X in the register
02191  * diagram. To change the EEPROM protection that will be loaded during the reset
02192  * sequence, the sector of program flash that contains the Flash Configuration Field
02193  * must be unprotected; then the EEPROM protection byte must be erased and
02194  * reprogrammed. Trying to alter data by writing to any protected area in the EEPROM
02195  * results in a protection violation error and sets the FSTAT[FPVIOL] bit.
02196  *
02197  * Values:
02198  * - 0 - For devices with program flash only: Reserved For devices with FlexNVM:
02199  *     EEPROM region is protected
02200  * - 1 - For devices with program flash only: Reserved For devices with FlexNVM:
02201  *     EEPROM region is not protected
02202  */
02203 /*@{*/
02204 #define BP_FTFE_FEPROT_EPROT (0U)          /*!< Bit position for FTFE_FEPROT_EPROT. */
02205 #define BM_FTFE_FEPROT_EPROT (0xFFU)       /*!< Bit mask for FTFE_FEPROT_EPROT. */
02206 #define BS_FTFE_FEPROT_EPROT (8U)          /*!< Bit field size in bits for FTFE_FEPROT_EPROT. */
02207 
02208 /*! @brief Read current value of the FTFE_FEPROT_EPROT field. */
02209 #define BR_FTFE_FEPROT_EPROT(x) (HW_FTFE_FEPROT(x).U)
02210 
02211 /*! @brief Format value for bitfield FTFE_FEPROT_EPROT. */
02212 #define BF_FTFE_FEPROT_EPROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FEPROT_EPROT) & BM_FTFE_FEPROT_EPROT)
02213 
02214 /*! @brief Set the EPROT field to a new value. */
02215 #define BW_FTFE_FEPROT_EPROT(x, v) (HW_FTFE_FEPROT_WR(x, v))
02216 /*@}*/
02217 
02218 /*******************************************************************************
02219  * HW_FTFE_FDPROT - Data Flash Protection Register
02220  ******************************************************************************/
02221 
02222 /*!
02223  * @brief HW_FTFE_FDPROT - Data Flash Protection Register (RW)
02224  *
02225  * Reset value: 0x00U
02226  *
02227  * The FDPROT register defines which data flash regions are protected against
02228  * program and erase operations. Protected Flash regions cannot have their content
02229  * changed; that is, these regions cannot be programmed and cannot be erased by
02230  * any FTFE command. Unprotected regions can be changed by both program and erase
02231  * operations.
02232  */
02233 typedef union _hw_ftfe_fdprot
02234 {
02235     uint8_t U;
02236     struct _hw_ftfe_fdprot_bitfields
02237     {
02238         uint8_t DPROT : 8;             /*!< [7:0] Data Flash Region Protect */
02239     } B;
02240 } hw_ftfe_fdprot_t;
02241 
02242 /*!
02243  * @name Constants and macros for entire FTFE_FDPROT register
02244  */
02245 /*@{*/
02246 #define HW_FTFE_FDPROT_ADDR(x)   ((x) + 0x17U)
02247 
02248 #define HW_FTFE_FDPROT(x)        (*(__IO hw_ftfe_fdprot_t *) HW_FTFE_FDPROT_ADDR(x))
02249 #define HW_FTFE_FDPROT_RD(x)     (ADDRESS_READ(hw_ftfe_fdprot_t, HW_FTFE_FDPROT_ADDR(x)))
02250 #define HW_FTFE_FDPROT_WR(x, v)  (ADDRESS_WRITE(hw_ftfe_fdprot_t, HW_FTFE_FDPROT_ADDR(x), v))
02251 #define HW_FTFE_FDPROT_SET(x, v) (HW_FTFE_FDPROT_WR(x, HW_FTFE_FDPROT_RD(x) |  (v)))
02252 #define HW_FTFE_FDPROT_CLR(x, v) (HW_FTFE_FDPROT_WR(x, HW_FTFE_FDPROT_RD(x) & ~(v)))
02253 #define HW_FTFE_FDPROT_TOG(x, v) (HW_FTFE_FDPROT_WR(x, HW_FTFE_FDPROT_RD(x) ^  (v)))
02254 /*@}*/
02255 
02256 /*
02257  * Constants & macros for individual FTFE_FDPROT bitfields
02258  */
02259 
02260 /*!
02261  * @name Register FTFE_FDPROT, field DPROT[7:0] (RW)
02262  *
02263  * Individual data flash regions can be protected from program and erase
02264  * operations by setting the associated DPROT bit. Each DPROT bit protects one-eighth of
02265  * the partitioned data flash memory space. The granularity of data flash
02266  * protection cannot be less than the data flash sector size. If an unused DPROT bit is
02267  * set, the Erase all Blocks command does not execute and sets the FSTAT[FPVIOL]
02268  * bit. In NVM Normal mode: The protection can only be increased, meaning that
02269  * currently unprotected memory can be protected but currently protected memory
02270  * cannot be unprotected. Since unprotected regions are marked with a 1 and
02271  * protected regions use a 0, only writes changing 1s to 0s are accepted. This 1-to-0
02272  * transition check is performed on a bit-by-bit basis. Those FDPROT bits with
02273  * 1-to-0 transitions are accepted while all bits with 0-to-1 transitions are
02274  * ignored. In NVM Special mode: All bits of the FDPROT register are writable without
02275  * restriction. Unprotected areas can be protected and protected areas can be
02276  * unprotected. The user must never write to the FDPROT register while a command is
02277  * running (CCIF=0). Reset: During the reset sequence, the FDPROT register is
02278  * loaded with the contents of the data flash protection byte in the Flash
02279  * Configuration Field located in program flash memory. The flash basis for the reset values
02280  * is signified by X in the register diagram. To change the data flash
02281  * protection that will be loaded during the reset sequence, unprotect the sector of
02282  * program flash that contains the Flash Configuration Field. Then, erase and
02283  * reprogram the data flash protection byte. Trying to alter data with the program and
02284  * erase commands in any protected area in the data flash memory results in a
02285  * protection violation error and sets the FSTAT[FPVIOL] bit. A block erase of any
02286  * data flash memory block (see the Erase Flash Block command description) is not
02287  * possible if the data flash block contains any protected region or if the FlexNVM
02288  * memory has been partitioned for EEPROM.
02289  *
02290  * Values:
02291  * - 0 - Data Flash region is protected
02292  * - 1 - Data Flash region is not protected
02293  */
02294 /*@{*/
02295 #define BP_FTFE_FDPROT_DPROT (0U)          /*!< Bit position for FTFE_FDPROT_DPROT. */
02296 #define BM_FTFE_FDPROT_DPROT (0xFFU)       /*!< Bit mask for FTFE_FDPROT_DPROT. */
02297 #define BS_FTFE_FDPROT_DPROT (8U)          /*!< Bit field size in bits for FTFE_FDPROT_DPROT. */
02298 
02299 /*! @brief Read current value of the FTFE_FDPROT_DPROT field. */
02300 #define BR_FTFE_FDPROT_DPROT(x) (HW_FTFE_FDPROT(x).U)
02301 
02302 /*! @brief Format value for bitfield FTFE_FDPROT_DPROT. */
02303 #define BF_FTFE_FDPROT_DPROT(v) ((uint8_t)((uint8_t)(v) << BP_FTFE_FDPROT_DPROT) & BM_FTFE_FDPROT_DPROT)
02304 
02305 /*! @brief Set the DPROT field to a new value. */
02306 #define BW_FTFE_FDPROT_DPROT(x, v) (HW_FTFE_FDPROT_WR(x, v))
02307 /*@}*/
02308 
02309 /*******************************************************************************
02310  * hw_ftfe_t - module struct
02311  ******************************************************************************/
02312 /*!
02313  * @brief All FTFE module registers.
02314  */
02315 #pragma pack(1)
02316 typedef struct _hw_ftfe
02317 {
02318     __IO hw_ftfe_fstat_t FSTAT ;            /*!< [0x0] Flash Status Register */
02319     __IO hw_ftfe_fcnfg_t FCNFG ;            /*!< [0x1] Flash Configuration Register */
02320     __I hw_ftfe_fsec_t FSEC ;               /*!< [0x2] Flash Security Register */
02321     __I hw_ftfe_fopt_t FOPT ;               /*!< [0x3] Flash Option Register */
02322     __IO hw_ftfe_fccob3_t FCCOB3 ;          /*!< [0x4] Flash Common Command Object Registers */
02323     __IO hw_ftfe_fccob2_t FCCOB2 ;          /*!< [0x5] Flash Common Command Object Registers */
02324     __IO hw_ftfe_fccob1_t FCCOB1 ;          /*!< [0x6] Flash Common Command Object Registers */
02325     __IO hw_ftfe_fccob0_t FCCOB0 ;          /*!< [0x7] Flash Common Command Object Registers */
02326     __IO hw_ftfe_fccob7_t FCCOB7 ;          /*!< [0x8] Flash Common Command Object Registers */
02327     __IO hw_ftfe_fccob6_t FCCOB6 ;          /*!< [0x9] Flash Common Command Object Registers */
02328     __IO hw_ftfe_fccob5_t FCCOB5 ;          /*!< [0xA] Flash Common Command Object Registers */
02329     __IO hw_ftfe_fccob4_t FCCOB4 ;          /*!< [0xB] Flash Common Command Object Registers */
02330     __IO hw_ftfe_fccobb_t FCCOBB ;          /*!< [0xC] Flash Common Command Object Registers */
02331     __IO hw_ftfe_fccoba_t FCCOBA ;          /*!< [0xD] Flash Common Command Object Registers */
02332     __IO hw_ftfe_fccob9_t FCCOB9 ;          /*!< [0xE] Flash Common Command Object Registers */
02333     __IO hw_ftfe_fccob8_t FCCOB8 ;          /*!< [0xF] Flash Common Command Object Registers */
02334     __IO hw_ftfe_fprot3_t FPROT3 ;          /*!< [0x10] Program Flash Protection Registers */
02335     __IO hw_ftfe_fprot2_t FPROT2 ;          /*!< [0x11] Program Flash Protection Registers */
02336     __IO hw_ftfe_fprot1_t FPROT1 ;          /*!< [0x12] Program Flash Protection Registers */
02337     __IO hw_ftfe_fprot0_t FPROT0 ;          /*!< [0x13] Program Flash Protection Registers */
02338     uint8_t _reserved0[2];
02339     __IO hw_ftfe_feprot_t FEPROT ;          /*!< [0x16] EEPROM Protection Register */
02340     __IO hw_ftfe_fdprot_t FDPROT ;          /*!< [0x17] Data Flash Protection Register */
02341 } hw_ftfe_t;
02342 #pragma pack()
02343 
02344 /*! @brief Macro to access all FTFE registers. */
02345 /*! @param x FTFE module instance base address. */
02346 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
02347  *     use the '&' operator, like <code>&HW_FTFE(FTFE_BASE)</code>. */
02348 #define HW_FTFE(x)     (*(hw_ftfe_t *)(x))
02349 
02350 #endif /* __HW_FTFE_REGISTERS_H__ */
02351 /* EOF */