MK64F12_ewm.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_EWM_REGISTERS_H__
00088 #define __HW_EWM_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 EWM
00095  *
00096  * External Watchdog Monitor
00097  *
00098  * Registers defined in this header file:
00099  * - HW_EWM_CTRL - Control Register
00100  * - HW_EWM_SERV - Service Register
00101  * - HW_EWM_CMPL - Compare Low Register
00102  * - HW_EWM_CMPH - Compare High Register
00103  *
00104  * - hw_ewm_t - Struct containing all module registers.
00105  */
00106 
00107 #define HW_EWM_INSTANCE_COUNT (1U) /*!< Number of instances of the EWM module. */
00108 
00109 /*******************************************************************************
00110  * HW_EWM_CTRL - Control Register
00111  ******************************************************************************/
00112 
00113 /*!
00114  * @brief HW_EWM_CTRL - Control Register (RW)
00115  *
00116  * Reset value: 0x00U
00117  *
00118  * The CTRL register is cleared by any reset. INEN, ASSIN and EWMEN bits can be
00119  * written once after a CPU reset. Modifying these bits more than once, generates
00120  * a bus transfer error.
00121  */
00122 typedef union _hw_ewm_ctrl
00123 {
00124     uint8_t U;
00125     struct _hw_ewm_ctrl_bitfields
00126     {
00127         uint8_t EWMEN : 1;             /*!< [0] EWM enable. */
00128         uint8_t ASSIN : 1;             /*!< [1] EWM_in's Assertion State Select. */
00129         uint8_t INEN : 1;              /*!< [2] Input Enable. */
00130         uint8_t INTEN : 1;             /*!< [3] Interrupt Enable. */
00131         uint8_t RESERVED0 : 4;         /*!< [7:4]  */
00132     } B;
00133 } hw_ewm_ctrl_t;
00134 
00135 /*!
00136  * @name Constants and macros for entire EWM_CTRL register
00137  */
00138 /*@{*/
00139 #define HW_EWM_CTRL_ADDR(x)      ((x) + 0x0U)
00140 
00141 #define HW_EWM_CTRL(x)           (*(__IO hw_ewm_ctrl_t *) HW_EWM_CTRL_ADDR(x))
00142 #define HW_EWM_CTRL_RD(x)        (ADDRESS_READ(hw_ewm_ctrl_t, HW_EWM_CTRL_ADDR(x)))
00143 #define HW_EWM_CTRL_WR(x, v)     (ADDRESS_WRITE(hw_ewm_ctrl_t, HW_EWM_CTRL_ADDR(x), v))
00144 #define HW_EWM_CTRL_SET(x, v)    (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) |  (v)))
00145 #define HW_EWM_CTRL_CLR(x, v)    (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) & ~(v)))
00146 #define HW_EWM_CTRL_TOG(x, v)    (HW_EWM_CTRL_WR(x, HW_EWM_CTRL_RD(x) ^  (v)))
00147 /*@}*/
00148 
00149 /*
00150  * Constants & macros for individual EWM_CTRL bitfields
00151  */
00152 
00153 /*!
00154  * @name Register EWM_CTRL, field EWMEN[0] (RW)
00155  *
00156  * This bit when set, enables the EWM module. This resets the EWM counter to
00157  * zero and deasserts the EWM_out signal. Clearing EWMEN bit disables the EWM, and
00158  * therefore it cannot be enabled until a reset occurs, due to the write-once
00159  * nature of this bit.
00160  */
00161 /*@{*/
00162 #define BP_EWM_CTRL_EWMEN    (0U)          /*!< Bit position for EWM_CTRL_EWMEN. */
00163 #define BM_EWM_CTRL_EWMEN    (0x01U)       /*!< Bit mask for EWM_CTRL_EWMEN. */
00164 #define BS_EWM_CTRL_EWMEN    (1U)          /*!< Bit field size in bits for EWM_CTRL_EWMEN. */
00165 
00166 /*! @brief Read current value of the EWM_CTRL_EWMEN field. */
00167 #define BR_EWM_CTRL_EWMEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_EWMEN)))
00168 
00169 /*! @brief Format value for bitfield EWM_CTRL_EWMEN. */
00170 #define BF_EWM_CTRL_EWMEN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_EWMEN) & BM_EWM_CTRL_EWMEN)
00171 
00172 /*! @brief Set the EWMEN field to a new value. */
00173 #define BW_EWM_CTRL_EWMEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_EWMEN), v))
00174 /*@}*/
00175 
00176 /*!
00177  * @name Register EWM_CTRL, field ASSIN[1] (RW)
00178  *
00179  * Default assert state of the EWM_in signal is logic zero. Setting ASSIN bit
00180  * inverts the assert state to a logic one.
00181  */
00182 /*@{*/
00183 #define BP_EWM_CTRL_ASSIN    (1U)          /*!< Bit position for EWM_CTRL_ASSIN. */
00184 #define BM_EWM_CTRL_ASSIN    (0x02U)       /*!< Bit mask for EWM_CTRL_ASSIN. */
00185 #define BS_EWM_CTRL_ASSIN    (1U)          /*!< Bit field size in bits for EWM_CTRL_ASSIN. */
00186 
00187 /*! @brief Read current value of the EWM_CTRL_ASSIN field. */
00188 #define BR_EWM_CTRL_ASSIN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_ASSIN)))
00189 
00190 /*! @brief Format value for bitfield EWM_CTRL_ASSIN. */
00191 #define BF_EWM_CTRL_ASSIN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_ASSIN) & BM_EWM_CTRL_ASSIN)
00192 
00193 /*! @brief Set the ASSIN field to a new value. */
00194 #define BW_EWM_CTRL_ASSIN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_ASSIN), v))
00195 /*@}*/
00196 
00197 /*!
00198  * @name Register EWM_CTRL, field INEN[2] (RW)
00199  *
00200  * This bit when set, enables the EWM_in port.
00201  */
00202 /*@{*/
00203 #define BP_EWM_CTRL_INEN     (2U)          /*!< Bit position for EWM_CTRL_INEN. */
00204 #define BM_EWM_CTRL_INEN     (0x04U)       /*!< Bit mask for EWM_CTRL_INEN. */
00205 #define BS_EWM_CTRL_INEN     (1U)          /*!< Bit field size in bits for EWM_CTRL_INEN. */
00206 
00207 /*! @brief Read current value of the EWM_CTRL_INEN field. */
00208 #define BR_EWM_CTRL_INEN(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INEN)))
00209 
00210 /*! @brief Format value for bitfield EWM_CTRL_INEN. */
00211 #define BF_EWM_CTRL_INEN(v)  ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_INEN) & BM_EWM_CTRL_INEN)
00212 
00213 /*! @brief Set the INEN field to a new value. */
00214 #define BW_EWM_CTRL_INEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INEN), v))
00215 /*@}*/
00216 
00217 /*!
00218  * @name Register EWM_CTRL, field INTEN[3] (RW)
00219  *
00220  * This bit when set and EWM_out is asserted, an interrupt request is generated.
00221  * To de-assert interrupt request, user should clear this bit by writing 0.
00222  */
00223 /*@{*/
00224 #define BP_EWM_CTRL_INTEN    (3U)          /*!< Bit position for EWM_CTRL_INTEN. */
00225 #define BM_EWM_CTRL_INTEN    (0x08U)       /*!< Bit mask for EWM_CTRL_INTEN. */
00226 #define BS_EWM_CTRL_INTEN    (1U)          /*!< Bit field size in bits for EWM_CTRL_INTEN. */
00227 
00228 /*! @brief Read current value of the EWM_CTRL_INTEN field. */
00229 #define BR_EWM_CTRL_INTEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INTEN)))
00230 
00231 /*! @brief Format value for bitfield EWM_CTRL_INTEN. */
00232 #define BF_EWM_CTRL_INTEN(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CTRL_INTEN) & BM_EWM_CTRL_INTEN)
00233 
00234 /*! @brief Set the INTEN field to a new value. */
00235 #define BW_EWM_CTRL_INTEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_EWM_CTRL_ADDR(x), BP_EWM_CTRL_INTEN), v))
00236 /*@}*/
00237 
00238 /*******************************************************************************
00239  * HW_EWM_SERV - Service Register
00240  ******************************************************************************/
00241 
00242 /*!
00243  * @brief HW_EWM_SERV - Service Register (WORZ)
00244  *
00245  * Reset value: 0x00U
00246  *
00247  * The SERV register provides the interface from the CPU to the EWM module. It
00248  * is write-only and reads of this register return zero.
00249  */
00250 typedef union _hw_ewm_serv
00251 {
00252     uint8_t U;
00253     struct _hw_ewm_serv_bitfields
00254     {
00255         uint8_t SERVICE : 8;           /*!< [7:0]  */
00256     } B;
00257 } hw_ewm_serv_t;
00258 
00259 /*!
00260  * @name Constants and macros for entire EWM_SERV register
00261  */
00262 /*@{*/
00263 #define HW_EWM_SERV_ADDR(x)      ((x) + 0x1U)
00264 
00265 #define HW_EWM_SERV(x)           (*(__O hw_ewm_serv_t *) HW_EWM_SERV_ADDR(x))
00266 #define HW_EWM_SERV_RD(x)        (ADDRESS_READ(hw_ewm_serv_t, HW_EWM_SERV_ADDR(x)))
00267 #define HW_EWM_SERV_WR(x, v)     (ADDRESS_WRITE(hw_ewm_serv_t, HW_EWM_SERV_ADDR(x), v))
00268 /*@}*/
00269 
00270 /*
00271  * Constants & macros for individual EWM_SERV bitfields
00272  */
00273 
00274 /*!
00275  * @name Register EWM_SERV, field SERVICE[7:0] (WORZ)
00276  *
00277  * The EWM service mechanism requires the CPU to write two values to the SERV
00278  * register: a first data byte of 0xB4, followed by a second data byte of 0x2C. The
00279  * EWM service is illegal if either of the following conditions is true. The
00280  * first or second data byte is not written correctly. The second data byte is not
00281  * written within a fixed number of peripheral bus cycles of the first data byte.
00282  * This fixed number of cycles is called EWM_service_time.
00283  */
00284 /*@{*/
00285 #define BP_EWM_SERV_SERVICE  (0U)          /*!< Bit position for EWM_SERV_SERVICE. */
00286 #define BM_EWM_SERV_SERVICE  (0xFFU)       /*!< Bit mask for EWM_SERV_SERVICE. */
00287 #define BS_EWM_SERV_SERVICE  (8U)          /*!< Bit field size in bits for EWM_SERV_SERVICE. */
00288 
00289 /*! @brief Format value for bitfield EWM_SERV_SERVICE. */
00290 #define BF_EWM_SERV_SERVICE(v) ((uint8_t)((uint8_t)(v) << BP_EWM_SERV_SERVICE) & BM_EWM_SERV_SERVICE)
00291 
00292 /*! @brief Set the SERVICE field to a new value. */
00293 #define BW_EWM_SERV_SERVICE(x, v) (HW_EWM_SERV_WR(x, v))
00294 /*@}*/
00295 
00296 /*******************************************************************************
00297  * HW_EWM_CMPL - Compare Low Register
00298  ******************************************************************************/
00299 
00300 /*!
00301  * @brief HW_EWM_CMPL - Compare Low Register (RW)
00302  *
00303  * Reset value: 0x00U
00304  *
00305  * The CMPL register is reset to zero after a CPU reset. This provides no
00306  * minimum time for the CPU to service the EWM counter. This register can be written
00307  * only once after a CPU reset. Writing this register more than once generates a
00308  * bus transfer error.
00309  */
00310 typedef union _hw_ewm_cmpl
00311 {
00312     uint8_t U;
00313     struct _hw_ewm_cmpl_bitfields
00314     {
00315         uint8_t COMPAREL : 8;          /*!< [7:0]  */
00316     } B;
00317 } hw_ewm_cmpl_t;
00318 
00319 /*!
00320  * @name Constants and macros for entire EWM_CMPL register
00321  */
00322 /*@{*/
00323 #define HW_EWM_CMPL_ADDR(x)      ((x) + 0x2U)
00324 
00325 #define HW_EWM_CMPL(x)           (*(__IO hw_ewm_cmpl_t *) HW_EWM_CMPL_ADDR(x))
00326 #define HW_EWM_CMPL_RD(x)        (ADDRESS_READ(hw_ewm_cmpl_t, HW_EWM_CMPL_ADDR(x)))
00327 #define HW_EWM_CMPL_WR(x, v)     (ADDRESS_WRITE(hw_ewm_cmpl_t, HW_EWM_CMPL_ADDR(x), v))
00328 #define HW_EWM_CMPL_SET(x, v)    (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) |  (v)))
00329 #define HW_EWM_CMPL_CLR(x, v)    (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) & ~(v)))
00330 #define HW_EWM_CMPL_TOG(x, v)    (HW_EWM_CMPL_WR(x, HW_EWM_CMPL_RD(x) ^  (v)))
00331 /*@}*/
00332 
00333 /*
00334  * Constants & macros for individual EWM_CMPL bitfields
00335  */
00336 
00337 /*!
00338  * @name Register EWM_CMPL, field COMPAREL[7:0] (RW)
00339  *
00340  * To prevent runaway code from changing this field, software should write to
00341  * this field after a CPU reset even if the (default) minimum service time is
00342  * required.
00343  */
00344 /*@{*/
00345 #define BP_EWM_CMPL_COMPAREL (0U)          /*!< Bit position for EWM_CMPL_COMPAREL. */
00346 #define BM_EWM_CMPL_COMPAREL (0xFFU)       /*!< Bit mask for EWM_CMPL_COMPAREL. */
00347 #define BS_EWM_CMPL_COMPAREL (8U)          /*!< Bit field size in bits for EWM_CMPL_COMPAREL. */
00348 
00349 /*! @brief Read current value of the EWM_CMPL_COMPAREL field. */
00350 #define BR_EWM_CMPL_COMPAREL(x) (HW_EWM_CMPL(x).U)
00351 
00352 /*! @brief Format value for bitfield EWM_CMPL_COMPAREL. */
00353 #define BF_EWM_CMPL_COMPAREL(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CMPL_COMPAREL) & BM_EWM_CMPL_COMPAREL)
00354 
00355 /*! @brief Set the COMPAREL field to a new value. */
00356 #define BW_EWM_CMPL_COMPAREL(x, v) (HW_EWM_CMPL_WR(x, v))
00357 /*@}*/
00358 
00359 /*******************************************************************************
00360  * HW_EWM_CMPH - Compare High Register
00361  ******************************************************************************/
00362 
00363 /*!
00364  * @brief HW_EWM_CMPH - Compare High Register (RW)
00365  *
00366  * Reset value: 0xFFU
00367  *
00368  * The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum
00369  * of 256 clocks time, for the CPU to service the EWM counter. This register can
00370  * be written only once after a CPU reset. Writing this register more than once
00371  * generates a bus transfer error. The valid values for CMPH are up to 0xFE
00372  * because the EWM counter never expires when CMPH = 0xFF. The expiration happens only
00373  * if EWM counter is greater than CMPH.
00374  */
00375 typedef union _hw_ewm_cmph
00376 {
00377     uint8_t U;
00378     struct _hw_ewm_cmph_bitfields
00379     {
00380         uint8_t COMPAREH : 8;          /*!< [7:0]  */
00381     } B;
00382 } hw_ewm_cmph_t;
00383 
00384 /*!
00385  * @name Constants and macros for entire EWM_CMPH register
00386  */
00387 /*@{*/
00388 #define HW_EWM_CMPH_ADDR(x)      ((x) + 0x3U)
00389 
00390 #define HW_EWM_CMPH(x)           (*(__IO hw_ewm_cmph_t *) HW_EWM_CMPH_ADDR(x))
00391 #define HW_EWM_CMPH_RD(x)        (ADDRESS_READ(hw_ewm_cmph_t, HW_EWM_CMPH_ADDR(x)))
00392 #define HW_EWM_CMPH_WR(x, v)     (ADDRESS_WRITE(hw_ewm_cmph_t, HW_EWM_CMPH_ADDR(x), v))
00393 #define HW_EWM_CMPH_SET(x, v)    (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) |  (v)))
00394 #define HW_EWM_CMPH_CLR(x, v)    (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) & ~(v)))
00395 #define HW_EWM_CMPH_TOG(x, v)    (HW_EWM_CMPH_WR(x, HW_EWM_CMPH_RD(x) ^  (v)))
00396 /*@}*/
00397 
00398 /*
00399  * Constants & macros for individual EWM_CMPH bitfields
00400  */
00401 
00402 /*!
00403  * @name Register EWM_CMPH, field COMPAREH[7:0] (RW)
00404  *
00405  * To prevent runaway code from changing this field, software should write to
00406  * this field after a CPU reset even if the (default) maximum service time is
00407  * required.
00408  */
00409 /*@{*/
00410 #define BP_EWM_CMPH_COMPAREH (0U)          /*!< Bit position for EWM_CMPH_COMPAREH. */
00411 #define BM_EWM_CMPH_COMPAREH (0xFFU)       /*!< Bit mask for EWM_CMPH_COMPAREH. */
00412 #define BS_EWM_CMPH_COMPAREH (8U)          /*!< Bit field size in bits for EWM_CMPH_COMPAREH. */
00413 
00414 /*! @brief Read current value of the EWM_CMPH_COMPAREH field. */
00415 #define BR_EWM_CMPH_COMPAREH(x) (HW_EWM_CMPH(x).U)
00416 
00417 /*! @brief Format value for bitfield EWM_CMPH_COMPAREH. */
00418 #define BF_EWM_CMPH_COMPAREH(v) ((uint8_t)((uint8_t)(v) << BP_EWM_CMPH_COMPAREH) & BM_EWM_CMPH_COMPAREH)
00419 
00420 /*! @brief Set the COMPAREH field to a new value. */
00421 #define BW_EWM_CMPH_COMPAREH(x, v) (HW_EWM_CMPH_WR(x, v))
00422 /*@}*/
00423 
00424 /*******************************************************************************
00425  * hw_ewm_t - module struct
00426  ******************************************************************************/
00427 /*!
00428  * @brief All EWM module registers.
00429  */
00430 #pragma pack(1)
00431 typedef struct _hw_ewm
00432 {
00433     __IO hw_ewm_ctrl_t CTRL ;               /*!< [0x0] Control Register */
00434     __O hw_ewm_serv_t SERV ;                /*!< [0x1] Service Register */
00435     __IO hw_ewm_cmpl_t CMPL ;               /*!< [0x2] Compare Low Register */
00436     __IO hw_ewm_cmph_t CMPH ;               /*!< [0x3] Compare High Register */
00437 } hw_ewm_t;
00438 #pragma pack()
00439 
00440 /*! @brief Macro to access all EWM registers. */
00441 /*! @param x EWM module instance base address. */
00442 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
00443  *     use the '&' operator, like <code>&HW_EWM(EWM_BASE)</code>. */
00444 #define HW_EWM(x)      (*(hw_ewm_t *)(x))
00445 
00446 #endif /* __HW_EWM_REGISTERS_H__ */
00447 /* EOF */