MK64F12_dac.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_DAC_REGISTERS_H__
00088 #define __HW_DAC_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 DAC
00095  *
00096  * 12-Bit Digital-to-Analog Converter
00097  *
00098  * Registers defined in this header file:
00099  * - HW_DAC_DATnL - DAC Data Low Register
00100  * - HW_DAC_DATnH - DAC Data High Register
00101  * - HW_DAC_SR - DAC Status Register
00102  * - HW_DAC_C0 - DAC Control Register
00103  * - HW_DAC_C1 - DAC Control Register 1
00104  * - HW_DAC_C2 - DAC Control Register 2
00105  *
00106  * - hw_dac_t - Struct containing all module registers.
00107  */
00108 
00109 #define HW_DAC_INSTANCE_COUNT (2U) /*!< Number of instances of the DAC module. */
00110 #define HW_DAC0 (0U) /*!< Instance number for DAC0. */
00111 #define HW_DAC1 (1U) /*!< Instance number for DAC1. */
00112 
00113 /*******************************************************************************
00114  * HW_DAC_DATnL - DAC Data Low Register
00115  ******************************************************************************/
00116 
00117 /*!
00118  * @brief HW_DAC_DATnL - DAC Data Low Register (RW)
00119  *
00120  * Reset value: 0x00U
00121  */
00122 typedef union _hw_dac_datnl
00123 {
00124     uint8_t U;
00125     struct _hw_dac_datnl_bitfields
00126     {
00127         uint8_t DATA0 : 8;             /*!< [7:0]  */
00128     } B;
00129 } hw_dac_datnl_t;
00130 
00131 /*!
00132  * @name Constants and macros for entire DAC_DATnL register
00133  */
00134 /*@{*/
00135 #define HW_DAC_DATnL_COUNT (16U)
00136 
00137 #define HW_DAC_DATnL_ADDR(x, n)  ((x) + 0x0U + (0x2U * (n)))
00138 
00139 #define HW_DAC_DATnL(x, n)       (*(__IO hw_dac_datnl_t *) HW_DAC_DATnL_ADDR(x, n))
00140 #define HW_DAC_DATnL_RD(x, n)    (ADDRESS_READ(hw_dac_datnl_t, HW_DAC_DATnL_ADDR(x, n)))
00141 #define HW_DAC_DATnL_WR(x, n, v) (ADDRESS_WRITE(hw_dac_datnl_t, HW_DAC_DATnL_ADDR(x, n), v))
00142 #define HW_DAC_DATnL_SET(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) |  (v)))
00143 #define HW_DAC_DATnL_CLR(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) & ~(v)))
00144 #define HW_DAC_DATnL_TOG(x, n, v) (HW_DAC_DATnL_WR(x, n, HW_DAC_DATnL_RD(x, n) ^  (v)))
00145 /*@}*/
00146 
00147 /*
00148  * Constants & macros for individual DAC_DATnL bitfields
00149  */
00150 
00151 /*!
00152  * @name Register DAC_DATnL, field DATA0[7:0] (RW)
00153  *
00154  * When the DAC buffer is not enabled, DATA[11:0] controls the output voltage
00155  * based on the following formula: V out = V in * (1 + DACDAT0[11:0])/4096 When the
00156  * DAC buffer is enabled, DATA is mapped to the 16-word buffer.
00157  */
00158 /*@{*/
00159 #define BP_DAC_DATnL_DATA0   (0U)          /*!< Bit position for DAC_DATnL_DATA0. */
00160 #define BM_DAC_DATnL_DATA0   (0xFFU)       /*!< Bit mask for DAC_DATnL_DATA0. */
00161 #define BS_DAC_DATnL_DATA0   (8U)          /*!< Bit field size in bits for DAC_DATnL_DATA0. */
00162 
00163 /*! @brief Read current value of the DAC_DATnL_DATA0 field. */
00164 #define BR_DAC_DATnL_DATA0(x, n) (HW_DAC_DATnL(x, n).U)
00165 
00166 /*! @brief Format value for bitfield DAC_DATnL_DATA0. */
00167 #define BF_DAC_DATnL_DATA0(v) ((uint8_t)((uint8_t)(v) << BP_DAC_DATnL_DATA0) & BM_DAC_DATnL_DATA0)
00168 
00169 /*! @brief Set the DATA0 field to a new value. */
00170 #define BW_DAC_DATnL_DATA0(x, n, v) (HW_DAC_DATnL_WR(x, n, v))
00171 /*@}*/
00172 /*******************************************************************************
00173  * HW_DAC_DATnH - DAC Data High Register
00174  ******************************************************************************/
00175 
00176 /*!
00177  * @brief HW_DAC_DATnH - DAC Data High Register (RW)
00178  *
00179  * Reset value: 0x00U
00180  */
00181 typedef union _hw_dac_datnh
00182 {
00183     uint8_t U;
00184     struct _hw_dac_datnh_bitfields
00185     {
00186         uint8_t DATA1 : 4;             /*!< [3:0]  */
00187         uint8_t RESERVED0 : 4;         /*!< [7:4]  */
00188     } B;
00189 } hw_dac_datnh_t;
00190 
00191 /*!
00192  * @name Constants and macros for entire DAC_DATnH register
00193  */
00194 /*@{*/
00195 #define HW_DAC_DATnH_COUNT (16U)
00196 
00197 #define HW_DAC_DATnH_ADDR(x, n)  ((x) + 0x1U + (0x2U * (n)))
00198 
00199 #define HW_DAC_DATnH(x, n)       (*(__IO hw_dac_datnh_t *) HW_DAC_DATnH_ADDR(x, n))
00200 #define HW_DAC_DATnH_RD(x, n)    (ADDRESS_READ(hw_dac_datnh_t, HW_DAC_DATnH_ADDR(x, n)))
00201 #define HW_DAC_DATnH_WR(x, n, v) (ADDRESS_WRITE(hw_dac_datnh_t, HW_DAC_DATnH_ADDR(x, n), v))
00202 #define HW_DAC_DATnH_SET(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) |  (v)))
00203 #define HW_DAC_DATnH_CLR(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) & ~(v)))
00204 #define HW_DAC_DATnH_TOG(x, n, v) (HW_DAC_DATnH_WR(x, n, HW_DAC_DATnH_RD(x, n) ^  (v)))
00205 /*@}*/
00206 
00207 /*
00208  * Constants & macros for individual DAC_DATnH bitfields
00209  */
00210 
00211 /*!
00212  * @name Register DAC_DATnH, field DATA1[3:0] (RW)
00213  *
00214  * When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage
00215  * based on the following formula. V out = V in * (1 + DACDAT0[11:0])/4096 When the
00216  * DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer.
00217  */
00218 /*@{*/
00219 #define BP_DAC_DATnH_DATA1   (0U)          /*!< Bit position for DAC_DATnH_DATA1. */
00220 #define BM_DAC_DATnH_DATA1   (0x0FU)       /*!< Bit mask for DAC_DATnH_DATA1. */
00221 #define BS_DAC_DATnH_DATA1   (4U)          /*!< Bit field size in bits for DAC_DATnH_DATA1. */
00222 
00223 /*! @brief Read current value of the DAC_DATnH_DATA1 field. */
00224 #define BR_DAC_DATnH_DATA1(x, n) (UNION_READ(hw_dac_datnh_t, HW_DAC_DATnH_ADDR(x, n), U, B.DATA1))
00225 
00226 /*! @brief Format value for bitfield DAC_DATnH_DATA1. */
00227 #define BF_DAC_DATnH_DATA1(v) ((uint8_t)((uint8_t)(v) << BP_DAC_DATnH_DATA1) & BM_DAC_DATnH_DATA1)
00228 
00229 /*! @brief Set the DATA1 field to a new value. */
00230 #define BW_DAC_DATnH_DATA1(x, n, v) (HW_DAC_DATnH_WR(x, n, (HW_DAC_DATnH_RD(x, n) & ~BM_DAC_DATnH_DATA1) | BF_DAC_DATnH_DATA1(v)))
00231 /*@}*/
00232 
00233 /*******************************************************************************
00234  * HW_DAC_SR - DAC Status Register
00235  ******************************************************************************/
00236 
00237 /*!
00238  * @brief HW_DAC_SR - DAC Status Register (RW)
00239  *
00240  * Reset value: 0x02U
00241  *
00242  * If DMA is enabled, the flags can be cleared automatically by DMA when the DMA
00243  * request is done. Writing 0 to a field clears it whereas writing 1 has no
00244  * effect. After reset, DACBFRPTF is set and can be cleared by software, if needed.
00245  * The flags are set only when the data buffer status is changed. Do not use
00246  * 32/16-bit accesses to this register.
00247  */
00248 typedef union _hw_dac_sr
00249 {
00250     uint8_t U;
00251     struct _hw_dac_sr_bitfields
00252     {
00253         uint8_t DACBFRPBF : 1;         /*!< [0] DAC Buffer Read Pointer Bottom
00254                                         * Position Flag */
00255         uint8_t DACBFRPTF : 1;         /*!< [1] DAC Buffer Read Pointer Top Position
00256                                         * Flag */
00257         uint8_t DACBFWMF : 1;          /*!< [2] DAC Buffer Watermark Flag */
00258         uint8_t RESERVED0 : 5;         /*!< [7:3]  */
00259     } B;
00260 } hw_dac_sr_t;
00261 
00262 /*!
00263  * @name Constants and macros for entire DAC_SR register
00264  */
00265 /*@{*/
00266 #define HW_DAC_SR_ADDR(x)        ((x) + 0x20U)
00267 
00268 #define HW_DAC_SR(x)             (*(__IO hw_dac_sr_t *) HW_DAC_SR_ADDR(x))
00269 #define HW_DAC_SR_RD(x)          (ADDRESS_READ(hw_dac_sr_t, HW_DAC_SR_ADDR(x)))
00270 #define HW_DAC_SR_WR(x, v)       (ADDRESS_WRITE(hw_dac_sr_t, HW_DAC_SR_ADDR(x), v))
00271 #define HW_DAC_SR_SET(x, v)      (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) |  (v)))
00272 #define HW_DAC_SR_CLR(x, v)      (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) & ~(v)))
00273 #define HW_DAC_SR_TOG(x, v)      (HW_DAC_SR_WR(x, HW_DAC_SR_RD(x) ^  (v)))
00274 /*@}*/
00275 
00276 /*
00277  * Constants & macros for individual DAC_SR bitfields
00278  */
00279 
00280 /*!
00281  * @name Register DAC_SR, field DACBFRPBF[0] (RW)
00282  *
00283  * Values:
00284  * - 0 - The DAC buffer read pointer is not equal to C2[DACBFUP].
00285  * - 1 - The DAC buffer read pointer is equal to C2[DACBFUP].
00286  */
00287 /*@{*/
00288 #define BP_DAC_SR_DACBFRPBF  (0U)          /*!< Bit position for DAC_SR_DACBFRPBF. */
00289 #define BM_DAC_SR_DACBFRPBF  (0x01U)       /*!< Bit mask for DAC_SR_DACBFRPBF. */
00290 #define BS_DAC_SR_DACBFRPBF  (1U)          /*!< Bit field size in bits for DAC_SR_DACBFRPBF. */
00291 
00292 /*! @brief Read current value of the DAC_SR_DACBFRPBF field. */
00293 #define BR_DAC_SR_DACBFRPBF(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF)))
00294 
00295 /*! @brief Format value for bitfield DAC_SR_DACBFRPBF. */
00296 #define BF_DAC_SR_DACBFRPBF(v) ((uint8_t)((uint8_t)(v) << BP_DAC_SR_DACBFRPBF) & BM_DAC_SR_DACBFRPBF)
00297 
00298 /*! @brief Set the DACBFRPBF field to a new value. */
00299 #define BW_DAC_SR_DACBFRPBF(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPBF), v))
00300 /*@}*/
00301 
00302 /*!
00303  * @name Register DAC_SR, field DACBFRPTF[1] (RW)
00304  *
00305  * Values:
00306  * - 0 - The DAC buffer read pointer is not zero.
00307  * - 1 - The DAC buffer read pointer is zero.
00308  */
00309 /*@{*/
00310 #define BP_DAC_SR_DACBFRPTF  (1U)          /*!< Bit position for DAC_SR_DACBFRPTF. */
00311 #define BM_DAC_SR_DACBFRPTF  (0x02U)       /*!< Bit mask for DAC_SR_DACBFRPTF. */
00312 #define BS_DAC_SR_DACBFRPTF  (1U)          /*!< Bit field size in bits for DAC_SR_DACBFRPTF. */
00313 
00314 /*! @brief Read current value of the DAC_SR_DACBFRPTF field. */
00315 #define BR_DAC_SR_DACBFRPTF(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF)))
00316 
00317 /*! @brief Format value for bitfield DAC_SR_DACBFRPTF. */
00318 #define BF_DAC_SR_DACBFRPTF(v) ((uint8_t)((uint8_t)(v) << BP_DAC_SR_DACBFRPTF) & BM_DAC_SR_DACBFRPTF)
00319 
00320 /*! @brief Set the DACBFRPTF field to a new value. */
00321 #define BW_DAC_SR_DACBFRPTF(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFRPTF), v))
00322 /*@}*/
00323 
00324 /*!
00325  * @name Register DAC_SR, field DACBFWMF[2] (RW)
00326  *
00327  * Values:
00328  * - 0 - The DAC buffer read pointer has not reached the watermark level.
00329  * - 1 - The DAC buffer read pointer has reached the watermark level.
00330  */
00331 /*@{*/
00332 #define BP_DAC_SR_DACBFWMF   (2U)          /*!< Bit position for DAC_SR_DACBFWMF. */
00333 #define BM_DAC_SR_DACBFWMF   (0x04U)       /*!< Bit mask for DAC_SR_DACBFWMF. */
00334 #define BS_DAC_SR_DACBFWMF   (1U)          /*!< Bit field size in bits for DAC_SR_DACBFWMF. */
00335 
00336 /*! @brief Read current value of the DAC_SR_DACBFWMF field. */
00337 #define BR_DAC_SR_DACBFWMF(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF)))
00338 
00339 /*! @brief Format value for bitfield DAC_SR_DACBFWMF. */
00340 #define BF_DAC_SR_DACBFWMF(v) ((uint8_t)((uint8_t)(v) << BP_DAC_SR_DACBFWMF) & BM_DAC_SR_DACBFWMF)
00341 
00342 /*! @brief Set the DACBFWMF field to a new value. */
00343 #define BW_DAC_SR_DACBFWMF(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DAC_SR_ADDR(x), BP_DAC_SR_DACBFWMF), v))
00344 /*@}*/
00345 
00346 /*******************************************************************************
00347  * HW_DAC_C0 - DAC Control Register
00348  ******************************************************************************/
00349 
00350 /*!
00351  * @brief HW_DAC_C0 - DAC Control Register (RW)
00352  *
00353  * Reset value: 0x00U
00354  *
00355  * Do not use 32- or 16-bit accesses to this register.
00356  */
00357 typedef union _hw_dac_c0
00358 {
00359     uint8_t U;
00360     struct _hw_dac_c0_bitfields
00361     {
00362         uint8_t DACBBIEN : 1;          /*!< [0] DAC Buffer Read Pointer Bottom Flag
00363                                         * Interrupt Enable */
00364         uint8_t DACBTIEN : 1;          /*!< [1] DAC Buffer Read Pointer Top Flag
00365                                         * Interrupt Enable */
00366         uint8_t DACBWIEN : 1;          /*!< [2] DAC Buffer Watermark Interrupt Enable
00367                                         * */
00368         uint8_t LPEN : 1;              /*!< [3] DAC Low Power Control */
00369         uint8_t DACSWTRG : 1;          /*!< [4] DAC Software Trigger */
00370         uint8_t DACTRGSEL : 1;         /*!< [5] DAC Trigger Select */
00371         uint8_t DACRFS : 1;            /*!< [6] DAC Reference Select */
00372         uint8_t DACEN : 1;             /*!< [7] DAC Enable */
00373     } B;
00374 } hw_dac_c0_t;
00375 
00376 /*!
00377  * @name Constants and macros for entire DAC_C0 register
00378  */
00379 /*@{*/
00380 #define HW_DAC_C0_ADDR(x)        ((x) + 0x21U)
00381 
00382 #define HW_DAC_C0(x)             (*(__IO hw_dac_c0_t *) HW_DAC_C0_ADDR(x))
00383 #define HW_DAC_C0_RD(x)          (ADDRESS_READ(hw_dac_c0_t, HW_DAC_C0_ADDR(x)))
00384 #define HW_DAC_C0_WR(x, v)       (ADDRESS_WRITE(hw_dac_c0_t, HW_DAC_C0_ADDR(x), v))
00385 #define HW_DAC_C0_SET(x, v)      (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) |  (v)))
00386 #define HW_DAC_C0_CLR(x, v)      (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) & ~(v)))
00387 #define HW_DAC_C0_TOG(x, v)      (HW_DAC_C0_WR(x, HW_DAC_C0_RD(x) ^  (v)))
00388 /*@}*/
00389 
00390 /*
00391  * Constants & macros for individual DAC_C0 bitfields
00392  */
00393 
00394 /*!
00395  * @name Register DAC_C0, field DACBBIEN[0] (RW)
00396  *
00397  * Values:
00398  * - 0 - The DAC buffer read pointer bottom flag interrupt is disabled.
00399  * - 1 - The DAC buffer read pointer bottom flag interrupt is enabled.
00400  */
00401 /*@{*/
00402 #define BP_DAC_C0_DACBBIEN   (0U)          /*!< Bit position for DAC_C0_DACBBIEN. */
00403 #define BM_DAC_C0_DACBBIEN   (0x01U)       /*!< Bit mask for DAC_C0_DACBBIEN. */
00404 #define BS_DAC_C0_DACBBIEN   (1U)          /*!< Bit field size in bits for DAC_C0_DACBBIEN. */
00405 
00406 /*! @brief Read current value of the DAC_C0_DACBBIEN field. */
00407 #define BR_DAC_C0_DACBBIEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN)))
00408 
00409 /*! @brief Format value for bitfield DAC_C0_DACBBIEN. */
00410 #define BF_DAC_C0_DACBBIEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACBBIEN) & BM_DAC_C0_DACBBIEN)
00411 
00412 /*! @brief Set the DACBBIEN field to a new value. */
00413 #define BW_DAC_C0_DACBBIEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBBIEN), v))
00414 /*@}*/
00415 
00416 /*!
00417  * @name Register DAC_C0, field DACBTIEN[1] (RW)
00418  *
00419  * Values:
00420  * - 0 - The DAC buffer read pointer top flag interrupt is disabled.
00421  * - 1 - The DAC buffer read pointer top flag interrupt is enabled.
00422  */
00423 /*@{*/
00424 #define BP_DAC_C0_DACBTIEN   (1U)          /*!< Bit position for DAC_C0_DACBTIEN. */
00425 #define BM_DAC_C0_DACBTIEN   (0x02U)       /*!< Bit mask for DAC_C0_DACBTIEN. */
00426 #define BS_DAC_C0_DACBTIEN   (1U)          /*!< Bit field size in bits for DAC_C0_DACBTIEN. */
00427 
00428 /*! @brief Read current value of the DAC_C0_DACBTIEN field. */
00429 #define BR_DAC_C0_DACBTIEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN)))
00430 
00431 /*! @brief Format value for bitfield DAC_C0_DACBTIEN. */
00432 #define BF_DAC_C0_DACBTIEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACBTIEN) & BM_DAC_C0_DACBTIEN)
00433 
00434 /*! @brief Set the DACBTIEN field to a new value. */
00435 #define BW_DAC_C0_DACBTIEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBTIEN), v))
00436 /*@}*/
00437 
00438 /*!
00439  * @name Register DAC_C0, field DACBWIEN[2] (RW)
00440  *
00441  * Values:
00442  * - 0 - The DAC buffer watermark interrupt is disabled.
00443  * - 1 - The DAC buffer watermark interrupt is enabled.
00444  */
00445 /*@{*/
00446 #define BP_DAC_C0_DACBWIEN   (2U)          /*!< Bit position for DAC_C0_DACBWIEN. */
00447 #define BM_DAC_C0_DACBWIEN   (0x04U)       /*!< Bit mask for DAC_C0_DACBWIEN. */
00448 #define BS_DAC_C0_DACBWIEN   (1U)          /*!< Bit field size in bits for DAC_C0_DACBWIEN. */
00449 
00450 /*! @brief Read current value of the DAC_C0_DACBWIEN field. */
00451 #define BR_DAC_C0_DACBWIEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN)))
00452 
00453 /*! @brief Format value for bitfield DAC_C0_DACBWIEN. */
00454 #define BF_DAC_C0_DACBWIEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACBWIEN) & BM_DAC_C0_DACBWIEN)
00455 
00456 /*! @brief Set the DACBWIEN field to a new value. */
00457 #define BW_DAC_C0_DACBWIEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACBWIEN), v))
00458 /*@}*/
00459 
00460 /*!
00461  * @name Register DAC_C0, field LPEN[3] (RW)
00462  *
00463  * See the 12-bit DAC electrical characteristics of the device data sheet for
00464  * details on the impact of the modes below.
00465  *
00466  * Values:
00467  * - 0 - High-Power mode
00468  * - 1 - Low-Power mode
00469  */
00470 /*@{*/
00471 #define BP_DAC_C0_LPEN       (3U)          /*!< Bit position for DAC_C0_LPEN. */
00472 #define BM_DAC_C0_LPEN       (0x08U)       /*!< Bit mask for DAC_C0_LPEN. */
00473 #define BS_DAC_C0_LPEN       (1U)          /*!< Bit field size in bits for DAC_C0_LPEN. */
00474 
00475 /*! @brief Read current value of the DAC_C0_LPEN field. */
00476 #define BR_DAC_C0_LPEN(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN)))
00477 
00478 /*! @brief Format value for bitfield DAC_C0_LPEN. */
00479 #define BF_DAC_C0_LPEN(v)    ((uint8_t)((uint8_t)(v) << BP_DAC_C0_LPEN) & BM_DAC_C0_LPEN)
00480 
00481 /*! @brief Set the LPEN field to a new value. */
00482 #define BW_DAC_C0_LPEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_LPEN), v))
00483 /*@}*/
00484 
00485 /*!
00486  * @name Register DAC_C0, field DACSWTRG[4] (WORZ)
00487  *
00488  * Active high. This is a write-only field, which always reads 0. If DAC
00489  * software trigger is selected and buffer is enabled, writing 1 to this field will
00490  * advance the buffer read pointer once.
00491  *
00492  * Values:
00493  * - 0 - The DAC soft trigger is not valid.
00494  * - 1 - The DAC soft trigger is valid.
00495  */
00496 /*@{*/
00497 #define BP_DAC_C0_DACSWTRG   (4U)          /*!< Bit position for DAC_C0_DACSWTRG. */
00498 #define BM_DAC_C0_DACSWTRG   (0x10U)       /*!< Bit mask for DAC_C0_DACSWTRG. */
00499 #define BS_DAC_C0_DACSWTRG   (1U)          /*!< Bit field size in bits for DAC_C0_DACSWTRG. */
00500 
00501 /*! @brief Format value for bitfield DAC_C0_DACSWTRG. */
00502 #define BF_DAC_C0_DACSWTRG(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACSWTRG) & BM_DAC_C0_DACSWTRG)
00503 
00504 /*! @brief Set the DACSWTRG field to a new value. */
00505 #define BW_DAC_C0_DACSWTRG(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACSWTRG), v))
00506 /*@}*/
00507 
00508 /*!
00509  * @name Register DAC_C0, field DACTRGSEL[5] (RW)
00510  *
00511  * Values:
00512  * - 0 - The DAC hardware trigger is selected.
00513  * - 1 - The DAC software trigger is selected.
00514  */
00515 /*@{*/
00516 #define BP_DAC_C0_DACTRGSEL  (5U)          /*!< Bit position for DAC_C0_DACTRGSEL. */
00517 #define BM_DAC_C0_DACTRGSEL  (0x20U)       /*!< Bit mask for DAC_C0_DACTRGSEL. */
00518 #define BS_DAC_C0_DACTRGSEL  (1U)          /*!< Bit field size in bits for DAC_C0_DACTRGSEL. */
00519 
00520 /*! @brief Read current value of the DAC_C0_DACTRGSEL field. */
00521 #define BR_DAC_C0_DACTRGSEL(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL)))
00522 
00523 /*! @brief Format value for bitfield DAC_C0_DACTRGSEL. */
00524 #define BF_DAC_C0_DACTRGSEL(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACTRGSEL) & BM_DAC_C0_DACTRGSEL)
00525 
00526 /*! @brief Set the DACTRGSEL field to a new value. */
00527 #define BW_DAC_C0_DACTRGSEL(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACTRGSEL), v))
00528 /*@}*/
00529 
00530 /*!
00531  * @name Register DAC_C0, field DACRFS[6] (RW)
00532  *
00533  * Values:
00534  * - 0 - The DAC selects DACREF_1 as the reference voltage.
00535  * - 1 - The DAC selects DACREF_2 as the reference voltage.
00536  */
00537 /*@{*/
00538 #define BP_DAC_C0_DACRFS     (6U)          /*!< Bit position for DAC_C0_DACRFS. */
00539 #define BM_DAC_C0_DACRFS     (0x40U)       /*!< Bit mask for DAC_C0_DACRFS. */
00540 #define BS_DAC_C0_DACRFS     (1U)          /*!< Bit field size in bits for DAC_C0_DACRFS. */
00541 
00542 /*! @brief Read current value of the DAC_C0_DACRFS field. */
00543 #define BR_DAC_C0_DACRFS(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS)))
00544 
00545 /*! @brief Format value for bitfield DAC_C0_DACRFS. */
00546 #define BF_DAC_C0_DACRFS(v)  ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACRFS) & BM_DAC_C0_DACRFS)
00547 
00548 /*! @brief Set the DACRFS field to a new value. */
00549 #define BW_DAC_C0_DACRFS(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACRFS), v))
00550 /*@}*/
00551 
00552 /*!
00553  * @name Register DAC_C0, field DACEN[7] (RW)
00554  *
00555  * Starts the Programmable Reference Generator operation.
00556  *
00557  * Values:
00558  * - 0 - The DAC system is disabled.
00559  * - 1 - The DAC system is enabled.
00560  */
00561 /*@{*/
00562 #define BP_DAC_C0_DACEN      (7U)          /*!< Bit position for DAC_C0_DACEN. */
00563 #define BM_DAC_C0_DACEN      (0x80U)       /*!< Bit mask for DAC_C0_DACEN. */
00564 #define BS_DAC_C0_DACEN      (1U)          /*!< Bit field size in bits for DAC_C0_DACEN. */
00565 
00566 /*! @brief Read current value of the DAC_C0_DACEN field. */
00567 #define BR_DAC_C0_DACEN(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN)))
00568 
00569 /*! @brief Format value for bitfield DAC_C0_DACEN. */
00570 #define BF_DAC_C0_DACEN(v)   ((uint8_t)((uint8_t)(v) << BP_DAC_C0_DACEN) & BM_DAC_C0_DACEN)
00571 
00572 /*! @brief Set the DACEN field to a new value. */
00573 #define BW_DAC_C0_DACEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DAC_C0_ADDR(x), BP_DAC_C0_DACEN), v))
00574 /*@}*/
00575 
00576 /*******************************************************************************
00577  * HW_DAC_C1 - DAC Control Register 1
00578  ******************************************************************************/
00579 
00580 /*!
00581  * @brief HW_DAC_C1 - DAC Control Register 1 (RW)
00582  *
00583  * Reset value: 0x00U
00584  *
00585  * Do not use 32- or 16-bit accesses to this register.
00586  */
00587 typedef union _hw_dac_c1
00588 {
00589     uint8_t U;
00590     struct _hw_dac_c1_bitfields
00591     {
00592         uint8_t DACBFEN : 1;           /*!< [0] DAC Buffer Enable */
00593         uint8_t DACBFMD : 2;           /*!< [2:1] DAC Buffer Work Mode Select */
00594         uint8_t DACBFWM : 2;           /*!< [4:3] DAC Buffer Watermark Select */
00595         uint8_t RESERVED0 : 2;         /*!< [6:5]  */
00596         uint8_t DMAEN : 1;             /*!< [7] DMA Enable Select */
00597     } B;
00598 } hw_dac_c1_t;
00599 
00600 /*!
00601  * @name Constants and macros for entire DAC_C1 register
00602  */
00603 /*@{*/
00604 #define HW_DAC_C1_ADDR(x)        ((x) + 0x22U)
00605 
00606 #define HW_DAC_C1(x)             (*(__IO hw_dac_c1_t *) HW_DAC_C1_ADDR(x))
00607 #define HW_DAC_C1_RD(x)          (ADDRESS_READ(hw_dac_c1_t, HW_DAC_C1_ADDR(x)))
00608 #define HW_DAC_C1_WR(x, v)       (ADDRESS_WRITE(hw_dac_c1_t, HW_DAC_C1_ADDR(x), v))
00609 #define HW_DAC_C1_SET(x, v)      (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) |  (v)))
00610 #define HW_DAC_C1_CLR(x, v)      (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) & ~(v)))
00611 #define HW_DAC_C1_TOG(x, v)      (HW_DAC_C1_WR(x, HW_DAC_C1_RD(x) ^  (v)))
00612 /*@}*/
00613 
00614 /*
00615  * Constants & macros for individual DAC_C1 bitfields
00616  */
00617 
00618 /*!
00619  * @name Register DAC_C1, field DACBFEN[0] (RW)
00620  *
00621  * Values:
00622  * - 0 - Buffer read pointer is disabled. The converted data is always the first
00623  *     word of the buffer.
00624  * - 1 - Buffer read pointer is enabled. The converted data is the word that the
00625  *     read pointer points to. It means converted data can be from any word of
00626  *     the buffer.
00627  */
00628 /*@{*/
00629 #define BP_DAC_C1_DACBFEN    (0U)          /*!< Bit position for DAC_C1_DACBFEN. */
00630 #define BM_DAC_C1_DACBFEN    (0x01U)       /*!< Bit mask for DAC_C1_DACBFEN. */
00631 #define BS_DAC_C1_DACBFEN    (1U)          /*!< Bit field size in bits for DAC_C1_DACBFEN. */
00632 
00633 /*! @brief Read current value of the DAC_C1_DACBFEN field. */
00634 #define BR_DAC_C1_DACBFEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN)))
00635 
00636 /*! @brief Format value for bitfield DAC_C1_DACBFEN. */
00637 #define BF_DAC_C1_DACBFEN(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DACBFEN) & BM_DAC_C1_DACBFEN)
00638 
00639 /*! @brief Set the DACBFEN field to a new value. */
00640 #define BW_DAC_C1_DACBFEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DACBFEN), v))
00641 /*@}*/
00642 
00643 /*!
00644  * @name Register DAC_C1, field DACBFMD[2:1] (RW)
00645  *
00646  * Values:
00647  * - 00 - Normal mode
00648  * - 01 - Swing mode
00649  * - 10 - One-Time Scan mode
00650  * - 11 - Reserved
00651  */
00652 /*@{*/
00653 #define BP_DAC_C1_DACBFMD    (1U)          /*!< Bit position for DAC_C1_DACBFMD. */
00654 #define BM_DAC_C1_DACBFMD    (0x06U)       /*!< Bit mask for DAC_C1_DACBFMD. */
00655 #define BS_DAC_C1_DACBFMD    (2U)          /*!< Bit field size in bits for DAC_C1_DACBFMD. */
00656 
00657 /*! @brief Read current value of the DAC_C1_DACBFMD field. */
00658 #define BR_DAC_C1_DACBFMD(x) (UNION_READ(hw_dac_c1_t, HW_DAC_C1_ADDR(x), U, B.DACBFMD))
00659 
00660 /*! @brief Format value for bitfield DAC_C1_DACBFMD. */
00661 #define BF_DAC_C1_DACBFMD(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DACBFMD) & BM_DAC_C1_DACBFMD)
00662 
00663 /*! @brief Set the DACBFMD field to a new value. */
00664 #define BW_DAC_C1_DACBFMD(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFMD) | BF_DAC_C1_DACBFMD(v)))
00665 /*@}*/
00666 
00667 /*!
00668  * @name Register DAC_C1, field DACBFWM[4:3] (RW)
00669  *
00670  * Controls when SR[DACBFWMF] is set. When the DAC buffer read pointer reaches
00671  * the word defined by this field, which is 1-4 words away from the upper limit
00672  * (DACBUP), SR[DACBFWMF] will be set. This allows user configuration of the
00673  * watermark interrupt.
00674  *
00675  * Values:
00676  * - 00 - 1 word
00677  * - 01 - 2 words
00678  * - 10 - 3 words
00679  * - 11 - 4 words
00680  */
00681 /*@{*/
00682 #define BP_DAC_C1_DACBFWM    (3U)          /*!< Bit position for DAC_C1_DACBFWM. */
00683 #define BM_DAC_C1_DACBFWM    (0x18U)       /*!< Bit mask for DAC_C1_DACBFWM. */
00684 #define BS_DAC_C1_DACBFWM    (2U)          /*!< Bit field size in bits for DAC_C1_DACBFWM. */
00685 
00686 /*! @brief Read current value of the DAC_C1_DACBFWM field. */
00687 #define BR_DAC_C1_DACBFWM(x) (UNION_READ(hw_dac_c1_t, HW_DAC_C1_ADDR(x), U, B.DACBFWM))
00688 
00689 /*! @brief Format value for bitfield DAC_C1_DACBFWM. */
00690 #define BF_DAC_C1_DACBFWM(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DACBFWM) & BM_DAC_C1_DACBFWM)
00691 
00692 /*! @brief Set the DACBFWM field to a new value. */
00693 #define BW_DAC_C1_DACBFWM(x, v) (HW_DAC_C1_WR(x, (HW_DAC_C1_RD(x) & ~BM_DAC_C1_DACBFWM) | BF_DAC_C1_DACBFWM(v)))
00694 /*@}*/
00695 
00696 /*!
00697  * @name Register DAC_C1, field DMAEN[7] (RW)
00698  *
00699  * Values:
00700  * - 0 - DMA is disabled.
00701  * - 1 - DMA is enabled. When DMA is enabled, the DMA request will be generated
00702  *     by original interrupts. The interrupts will not be presented on this
00703  *     module at the same time.
00704  */
00705 /*@{*/
00706 #define BP_DAC_C1_DMAEN      (7U)          /*!< Bit position for DAC_C1_DMAEN. */
00707 #define BM_DAC_C1_DMAEN      (0x80U)       /*!< Bit mask for DAC_C1_DMAEN. */
00708 #define BS_DAC_C1_DMAEN      (1U)          /*!< Bit field size in bits for DAC_C1_DMAEN. */
00709 
00710 /*! @brief Read current value of the DAC_C1_DMAEN field. */
00711 #define BR_DAC_C1_DMAEN(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN)))
00712 
00713 /*! @brief Format value for bitfield DAC_C1_DMAEN. */
00714 #define BF_DAC_C1_DMAEN(v)   ((uint8_t)((uint8_t)(v) << BP_DAC_C1_DMAEN) & BM_DAC_C1_DMAEN)
00715 
00716 /*! @brief Set the DMAEN field to a new value. */
00717 #define BW_DAC_C1_DMAEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DAC_C1_ADDR(x), BP_DAC_C1_DMAEN), v))
00718 /*@}*/
00719 
00720 /*******************************************************************************
00721  * HW_DAC_C2 - DAC Control Register 2
00722  ******************************************************************************/
00723 
00724 /*!
00725  * @brief HW_DAC_C2 - DAC Control Register 2 (RW)
00726  *
00727  * Reset value: 0x0FU
00728  */
00729 typedef union _hw_dac_c2
00730 {
00731     uint8_t U;
00732     struct _hw_dac_c2_bitfields
00733     {
00734         uint8_t DACBFUP : 4;           /*!< [3:0] DAC Buffer Upper Limit */
00735         uint8_t DACBFRP : 4;           /*!< [7:4] DAC Buffer Read Pointer */
00736     } B;
00737 } hw_dac_c2_t;
00738 
00739 /*!
00740  * @name Constants and macros for entire DAC_C2 register
00741  */
00742 /*@{*/
00743 #define HW_DAC_C2_ADDR(x)        ((x) + 0x23U)
00744 
00745 #define HW_DAC_C2(x)             (*(__IO hw_dac_c2_t *) HW_DAC_C2_ADDR(x))
00746 #define HW_DAC_C2_RD(x)          (ADDRESS_READ(hw_dac_c2_t, HW_DAC_C2_ADDR(x)))
00747 #define HW_DAC_C2_WR(x, v)       (ADDRESS_WRITE(hw_dac_c2_t, HW_DAC_C2_ADDR(x), v))
00748 #define HW_DAC_C2_SET(x, v)      (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) |  (v)))
00749 #define HW_DAC_C2_CLR(x, v)      (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) & ~(v)))
00750 #define HW_DAC_C2_TOG(x, v)      (HW_DAC_C2_WR(x, HW_DAC_C2_RD(x) ^  (v)))
00751 /*@}*/
00752 
00753 /*
00754  * Constants & macros for individual DAC_C2 bitfields
00755  */
00756 
00757 /*!
00758  * @name Register DAC_C2, field DACBFUP[3:0] (RW)
00759  *
00760  * Selects the upper limit of the DAC buffer. The buffer read pointer cannot
00761  * exceed it.
00762  */
00763 /*@{*/
00764 #define BP_DAC_C2_DACBFUP    (0U)          /*!< Bit position for DAC_C2_DACBFUP. */
00765 #define BM_DAC_C2_DACBFUP    (0x0FU)       /*!< Bit mask for DAC_C2_DACBFUP. */
00766 #define BS_DAC_C2_DACBFUP    (4U)          /*!< Bit field size in bits for DAC_C2_DACBFUP. */
00767 
00768 /*! @brief Read current value of the DAC_C2_DACBFUP field. */
00769 #define BR_DAC_C2_DACBFUP(x) (UNION_READ(hw_dac_c2_t, HW_DAC_C2_ADDR(x), U, B.DACBFUP))
00770 
00771 /*! @brief Format value for bitfield DAC_C2_DACBFUP. */
00772 #define BF_DAC_C2_DACBFUP(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C2_DACBFUP) & BM_DAC_C2_DACBFUP)
00773 
00774 /*! @brief Set the DACBFUP field to a new value. */
00775 #define BW_DAC_C2_DACBFUP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFUP) | BF_DAC_C2_DACBFUP(v)))
00776 /*@}*/
00777 
00778 /*!
00779  * @name Register DAC_C2, field DACBFRP[7:4] (RW)
00780  *
00781  * Keeps the current value of the buffer read pointer.
00782  */
00783 /*@{*/
00784 #define BP_DAC_C2_DACBFRP    (4U)          /*!< Bit position for DAC_C2_DACBFRP. */
00785 #define BM_DAC_C2_DACBFRP    (0xF0U)       /*!< Bit mask for DAC_C2_DACBFRP. */
00786 #define BS_DAC_C2_DACBFRP    (4U)          /*!< Bit field size in bits for DAC_C2_DACBFRP. */
00787 
00788 /*! @brief Read current value of the DAC_C2_DACBFRP field. */
00789 #define BR_DAC_C2_DACBFRP(x) (UNION_READ(hw_dac_c2_t, HW_DAC_C2_ADDR(x), U, B.DACBFRP))
00790 
00791 /*! @brief Format value for bitfield DAC_C2_DACBFRP. */
00792 #define BF_DAC_C2_DACBFRP(v) ((uint8_t)((uint8_t)(v) << BP_DAC_C2_DACBFRP) & BM_DAC_C2_DACBFRP)
00793 
00794 /*! @brief Set the DACBFRP field to a new value. */
00795 #define BW_DAC_C2_DACBFRP(x, v) (HW_DAC_C2_WR(x, (HW_DAC_C2_RD(x) & ~BM_DAC_C2_DACBFRP) | BF_DAC_C2_DACBFRP(v)))
00796 /*@}*/
00797 
00798 /*******************************************************************************
00799  * hw_dac_t - module struct
00800  ******************************************************************************/
00801 /*!
00802  * @brief All DAC module registers.
00803  */
00804 #pragma pack(1)
00805 typedef struct _hw_dac
00806 {
00807     struct {
00808         __IO hw_dac_datnl_t DATnL ;         /*!< [0x0] DAC Data Low Register */
00809         __IO hw_dac_datnh_t DATnH ;         /*!< [0x1] DAC Data High Register */
00810     } DAT[16];
00811     __IO hw_dac_sr_t SR ;                   /*!< [0x20] DAC Status Register */
00812     __IO hw_dac_c0_t C0 ;                   /*!< [0x21] DAC Control Register */
00813     __IO hw_dac_c1_t C1 ;                   /*!< [0x22] DAC Control Register 1 */
00814     __IO hw_dac_c2_t C2 ;                   /*!< [0x23] DAC Control Register 2 */
00815 } hw_dac_t;
00816 #pragma pack()
00817 
00818 /*! @brief Macro to access all DAC registers. */
00819 /*! @param x DAC module instance base address. */
00820 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
00821  *     use the '&' operator, like <code>&HW_DAC(DAC0_BASE)</code>. */
00822 #define HW_DAC(x)      (*(hw_dac_t *)(x))
00823 
00824 #endif /* __HW_DAC_REGISTERS_H__ */
00825 /* EOF */