MK64F12_crc.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_CRC_REGISTERS_H__
00088 #define __HW_CRC_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 CRC
00095  *
00096  * Cyclic Redundancy Check
00097  *
00098  * Registers defined in this header file:
00099  * - HW_CRC_DATAL - CRC_DATAL register.
00100  * - HW_CRC_DATAH - CRC_DATAH register.
00101  * - HW_CRC_DATALL - CRC_DATALL register.
00102  * - HW_CRC_DATALU - CRC_DATALU register.
00103  * - HW_CRC_DATAHL - CRC_DATAHL register.
00104  * - HW_CRC_DATAHU - CRC_DATAHU register.
00105  * - HW_CRC_DATA - CRC Data register
00106  * - HW_CRC_GPOLY - CRC Polynomial register
00107  * - HW_CRC_GPOLYL - CRC_GPOLYL register.
00108  * - HW_CRC_GPOLYH - CRC_GPOLYH register.
00109  * - HW_CRC_GPOLYLL - CRC_GPOLYLL register.
00110  * - HW_CRC_GPOLYLU - CRC_GPOLYLU register.
00111  * - HW_CRC_GPOLYHL - CRC_GPOLYHL register.
00112  * - HW_CRC_GPOLYHU - CRC_GPOLYHU register.
00113  * - HW_CRC_CTRL - CRC Control register
00114  * - HW_CRC_CTRLHU - CRC_CTRLHU register.
00115  *
00116  * - hw_crc_t - Struct containing all module registers.
00117  */
00118 
00119 #define HW_CRC_INSTANCE_COUNT (1U) /*!< Number of instances of the CRC module. */
00120 
00121 /*******************************************************************************
00122  * HW_CRC_DATAL - CRC_DATAL register.
00123  ******************************************************************************/
00124 
00125 /*!
00126  * @brief HW_CRC_DATAL - CRC_DATAL register. (RW)
00127  *
00128  * Reset value: 0xFFFFU
00129  */
00130 typedef union _hw_crc_datal
00131 {
00132     uint16_t U;
00133     struct _hw_crc_datal_bitfields
00134     {
00135         uint16_t DATAL : 16;           /*!< [15:0] DATAL stores the lower 16 bits of
00136                                         * the 16/32 bit CRC */
00137     } B;
00138 } hw_crc_datal_t;
00139 
00140 /*!
00141  * @name Constants and macros for entire CRC_DATAL register
00142  */
00143 /*@{*/
00144 #define HW_CRC_DATAL_ADDR(x)     ((x) + 0x0U)
00145 
00146 #define HW_CRC_DATAL(x)          (*(__IO hw_crc_datal_t *) HW_CRC_DATAL_ADDR(x))
00147 #define HW_CRC_DATAL_RD(x)       (ADDRESS_READ(hw_crc_datal_t, HW_CRC_DATAL_ADDR(x)))
00148 #define HW_CRC_DATAL_WR(x, v)    (ADDRESS_WRITE(hw_crc_datal_t, HW_CRC_DATAL_ADDR(x), v))
00149 #define HW_CRC_DATAL_SET(x, v)   (HW_CRC_DATAL_WR(x, HW_CRC_DATAL_RD(x) |  (v)))
00150 #define HW_CRC_DATAL_CLR(x, v)   (HW_CRC_DATAL_WR(x, HW_CRC_DATAL_RD(x) & ~(v)))
00151 #define HW_CRC_DATAL_TOG(x, v)   (HW_CRC_DATAL_WR(x, HW_CRC_DATAL_RD(x) ^  (v)))
00152 /*@}*/
00153 
00154 /*
00155  * Constants & macros for individual CRC_DATAL bitfields
00156  */
00157 
00158 /*!
00159  * @name Register CRC_DATAL, field DATAL[15:0] (RW)
00160  */
00161 /*@{*/
00162 #define BP_CRC_DATAL_DATAL   (0U)          /*!< Bit position for CRC_DATAL_DATAL. */
00163 #define BM_CRC_DATAL_DATAL   (0xFFFFU)     /*!< Bit mask for CRC_DATAL_DATAL. */
00164 #define BS_CRC_DATAL_DATAL   (16U)         /*!< Bit field size in bits for CRC_DATAL_DATAL. */
00165 
00166 /*! @brief Read current value of the CRC_DATAL_DATAL field. */
00167 #define BR_CRC_DATAL_DATAL(x) (HW_CRC_DATAL(x).U)
00168 
00169 /*! @brief Format value for bitfield CRC_DATAL_DATAL. */
00170 #define BF_CRC_DATAL_DATAL(v) ((uint16_t)((uint16_t)(v) << BP_CRC_DATAL_DATAL) & BM_CRC_DATAL_DATAL)
00171 
00172 /*! @brief Set the DATAL field to a new value. */
00173 #define BW_CRC_DATAL_DATAL(x, v) (HW_CRC_DATAL_WR(x, v))
00174 /*@}*/
00175 /*******************************************************************************
00176  * HW_CRC_DATAH - CRC_DATAH register.
00177  ******************************************************************************/
00178 
00179 /*!
00180  * @brief HW_CRC_DATAH - CRC_DATAH register. (RW)
00181  *
00182  * Reset value: 0xFFFFU
00183  */
00184 typedef union _hw_crc_datah
00185 {
00186     uint16_t U;
00187     struct _hw_crc_datah_bitfields
00188     {
00189         uint16_t DATAH : 16;           /*!< [15:0] DATAH stores the high 16 bits of the
00190                                         * 16/32 bit CRC */
00191     } B;
00192 } hw_crc_datah_t;
00193 
00194 /*!
00195  * @name Constants and macros for entire CRC_DATAH register
00196  */
00197 /*@{*/
00198 #define HW_CRC_DATAH_ADDR(x)     ((x) + 0x2U)
00199 
00200 #define HW_CRC_DATAH(x)          (*(__IO hw_crc_datah_t *) HW_CRC_DATAH_ADDR(x))
00201 #define HW_CRC_DATAH_RD(x)       (ADDRESS_READ(hw_crc_datah_t, HW_CRC_DATAH_ADDR(x)))
00202 #define HW_CRC_DATAH_WR(x, v)    (ADDRESS_WRITE(hw_crc_datah_t, HW_CRC_DATAH_ADDR(x), v))
00203 #define HW_CRC_DATAH_SET(x, v)   (HW_CRC_DATAH_WR(x, HW_CRC_DATAH_RD(x) |  (v)))
00204 #define HW_CRC_DATAH_CLR(x, v)   (HW_CRC_DATAH_WR(x, HW_CRC_DATAH_RD(x) & ~(v)))
00205 #define HW_CRC_DATAH_TOG(x, v)   (HW_CRC_DATAH_WR(x, HW_CRC_DATAH_RD(x) ^  (v)))
00206 /*@}*/
00207 
00208 /*
00209  * Constants & macros for individual CRC_DATAH bitfields
00210  */
00211 
00212 /*!
00213  * @name Register CRC_DATAH, field DATAH[15:0] (RW)
00214  */
00215 /*@{*/
00216 #define BP_CRC_DATAH_DATAH   (0U)          /*!< Bit position for CRC_DATAH_DATAH. */
00217 #define BM_CRC_DATAH_DATAH   (0xFFFFU)     /*!< Bit mask for CRC_DATAH_DATAH. */
00218 #define BS_CRC_DATAH_DATAH   (16U)         /*!< Bit field size in bits for CRC_DATAH_DATAH. */
00219 
00220 /*! @brief Read current value of the CRC_DATAH_DATAH field. */
00221 #define BR_CRC_DATAH_DATAH(x) (HW_CRC_DATAH(x).U)
00222 
00223 /*! @brief Format value for bitfield CRC_DATAH_DATAH. */
00224 #define BF_CRC_DATAH_DATAH(v) ((uint16_t)((uint16_t)(v) << BP_CRC_DATAH_DATAH) & BM_CRC_DATAH_DATAH)
00225 
00226 /*! @brief Set the DATAH field to a new value. */
00227 #define BW_CRC_DATAH_DATAH(x, v) (HW_CRC_DATAH_WR(x, v))
00228 /*@}*/
00229 /*******************************************************************************
00230  * HW_CRC_DATALL - CRC_DATALL register.
00231  ******************************************************************************/
00232 
00233 /*!
00234  * @brief HW_CRC_DATALL - CRC_DATALL register. (RW)
00235  *
00236  * Reset value: 0xFFU
00237  */
00238 typedef union _hw_crc_datall
00239 {
00240     uint8_t U;
00241     struct _hw_crc_datall_bitfields
00242     {
00243         uint8_t DATALL : 8;            /*!< [7:0] CRCLL stores the first 8 bits of the
00244                                         * 32 bit DATA */
00245     } B;
00246 } hw_crc_datall_t;
00247 
00248 /*!
00249  * @name Constants and macros for entire CRC_DATALL register
00250  */
00251 /*@{*/
00252 #define HW_CRC_DATALL_ADDR(x)    ((x) + 0x0U)
00253 
00254 #define HW_CRC_DATALL(x)         (*(__IO hw_crc_datall_t *) HW_CRC_DATALL_ADDR(x))
00255 #define HW_CRC_DATALL_RD(x)      (ADDRESS_READ(hw_crc_datall_t, HW_CRC_DATALL_ADDR(x)))
00256 #define HW_CRC_DATALL_WR(x, v)   (ADDRESS_WRITE(hw_crc_datall_t, HW_CRC_DATALL_ADDR(x), v))
00257 #define HW_CRC_DATALL_SET(x, v)  (HW_CRC_DATALL_WR(x, HW_CRC_DATALL_RD(x) |  (v)))
00258 #define HW_CRC_DATALL_CLR(x, v)  (HW_CRC_DATALL_WR(x, HW_CRC_DATALL_RD(x) & ~(v)))
00259 #define HW_CRC_DATALL_TOG(x, v)  (HW_CRC_DATALL_WR(x, HW_CRC_DATALL_RD(x) ^  (v)))
00260 /*@}*/
00261 
00262 /*
00263  * Constants & macros for individual CRC_DATALL bitfields
00264  */
00265 
00266 /*!
00267  * @name Register CRC_DATALL, field DATALL[7:0] (RW)
00268  */
00269 /*@{*/
00270 #define BP_CRC_DATALL_DATALL (0U)          /*!< Bit position for CRC_DATALL_DATALL. */
00271 #define BM_CRC_DATALL_DATALL (0xFFU)       /*!< Bit mask for CRC_DATALL_DATALL. */
00272 #define BS_CRC_DATALL_DATALL (8U)          /*!< Bit field size in bits for CRC_DATALL_DATALL. */
00273 
00274 /*! @brief Read current value of the CRC_DATALL_DATALL field. */
00275 #define BR_CRC_DATALL_DATALL(x) (HW_CRC_DATALL(x).U)
00276 
00277 /*! @brief Format value for bitfield CRC_DATALL_DATALL. */
00278 #define BF_CRC_DATALL_DATALL(v) ((uint8_t)((uint8_t)(v) << BP_CRC_DATALL_DATALL) & BM_CRC_DATALL_DATALL)
00279 
00280 /*! @brief Set the DATALL field to a new value. */
00281 #define BW_CRC_DATALL_DATALL(x, v) (HW_CRC_DATALL_WR(x, v))
00282 /*@}*/
00283 /*******************************************************************************
00284  * HW_CRC_DATALU - CRC_DATALU register.
00285  ******************************************************************************/
00286 
00287 /*!
00288  * @brief HW_CRC_DATALU - CRC_DATALU register. (RW)
00289  *
00290  * Reset value: 0xFFU
00291  */
00292 typedef union _hw_crc_datalu
00293 {
00294     uint8_t U;
00295     struct _hw_crc_datalu_bitfields
00296     {
00297         uint8_t DATALU : 8;            /*!< [7:0] DATALL stores the second 8 bits of the
00298                                         * 32 bit CRC */
00299     } B;
00300 } hw_crc_datalu_t;
00301 
00302 /*!
00303  * @name Constants and macros for entire CRC_DATALU register
00304  */
00305 /*@{*/
00306 #define HW_CRC_DATALU_ADDR(x)    ((x) + 0x1U)
00307 
00308 #define HW_CRC_DATALU(x)         (*(__IO hw_crc_datalu_t *) HW_CRC_DATALU_ADDR(x))
00309 #define HW_CRC_DATALU_RD(x)      (ADDRESS_READ(hw_crc_datalu_t, HW_CRC_DATALU_ADDR(x)))
00310 #define HW_CRC_DATALU_WR(x, v)   (ADDRESS_WRITE(hw_crc_datalu_t, HW_CRC_DATALU_ADDR(x), v))
00311 #define HW_CRC_DATALU_SET(x, v)  (HW_CRC_DATALU_WR(x, HW_CRC_DATALU_RD(x) |  (v)))
00312 #define HW_CRC_DATALU_CLR(x, v)  (HW_CRC_DATALU_WR(x, HW_CRC_DATALU_RD(x) & ~(v)))
00313 #define HW_CRC_DATALU_TOG(x, v)  (HW_CRC_DATALU_WR(x, HW_CRC_DATALU_RD(x) ^  (v)))
00314 /*@}*/
00315 
00316 /*
00317  * Constants & macros for individual CRC_DATALU bitfields
00318  */
00319 
00320 /*!
00321  * @name Register CRC_DATALU, field DATALU[7:0] (RW)
00322  */
00323 /*@{*/
00324 #define BP_CRC_DATALU_DATALU (0U)          /*!< Bit position for CRC_DATALU_DATALU. */
00325 #define BM_CRC_DATALU_DATALU (0xFFU)       /*!< Bit mask for CRC_DATALU_DATALU. */
00326 #define BS_CRC_DATALU_DATALU (8U)          /*!< Bit field size in bits for CRC_DATALU_DATALU. */
00327 
00328 /*! @brief Read current value of the CRC_DATALU_DATALU field. */
00329 #define BR_CRC_DATALU_DATALU(x) (HW_CRC_DATALU(x).U)
00330 
00331 /*! @brief Format value for bitfield CRC_DATALU_DATALU. */
00332 #define BF_CRC_DATALU_DATALU(v) ((uint8_t)((uint8_t)(v) << BP_CRC_DATALU_DATALU) & BM_CRC_DATALU_DATALU)
00333 
00334 /*! @brief Set the DATALU field to a new value. */
00335 #define BW_CRC_DATALU_DATALU(x, v) (HW_CRC_DATALU_WR(x, v))
00336 /*@}*/
00337 /*******************************************************************************
00338  * HW_CRC_DATAHL - CRC_DATAHL register.
00339  ******************************************************************************/
00340 
00341 /*!
00342  * @brief HW_CRC_DATAHL - CRC_DATAHL register. (RW)
00343  *
00344  * Reset value: 0xFFU
00345  */
00346 typedef union _hw_crc_datahl
00347 {
00348     uint8_t U;
00349     struct _hw_crc_datahl_bitfields
00350     {
00351         uint8_t DATAHL : 8;            /*!< [7:0] DATAHL stores the third 8 bits of the
00352                                         * 32 bit CRC */
00353     } B;
00354 } hw_crc_datahl_t;
00355 
00356 /*!
00357  * @name Constants and macros for entire CRC_DATAHL register
00358  */
00359 /*@{*/
00360 #define HW_CRC_DATAHL_ADDR(x)    ((x) + 0x2U)
00361 
00362 #define HW_CRC_DATAHL(x)         (*(__IO hw_crc_datahl_t *) HW_CRC_DATAHL_ADDR(x))
00363 #define HW_CRC_DATAHL_RD(x)      (ADDRESS_READ(hw_crc_datahl_t, HW_CRC_DATAHL_ADDR(x)))
00364 #define HW_CRC_DATAHL_WR(x, v)   (ADDRESS_WRITE(hw_crc_datahl_t, HW_CRC_DATAHL_ADDR(x), v))
00365 #define HW_CRC_DATAHL_SET(x, v)  (HW_CRC_DATAHL_WR(x, HW_CRC_DATAHL_RD(x) |  (v)))
00366 #define HW_CRC_DATAHL_CLR(x, v)  (HW_CRC_DATAHL_WR(x, HW_CRC_DATAHL_RD(x) & ~(v)))
00367 #define HW_CRC_DATAHL_TOG(x, v)  (HW_CRC_DATAHL_WR(x, HW_CRC_DATAHL_RD(x) ^  (v)))
00368 /*@}*/
00369 
00370 /*
00371  * Constants & macros for individual CRC_DATAHL bitfields
00372  */
00373 
00374 /*!
00375  * @name Register CRC_DATAHL, field DATAHL[7:0] (RW)
00376  */
00377 /*@{*/
00378 #define BP_CRC_DATAHL_DATAHL (0U)          /*!< Bit position for CRC_DATAHL_DATAHL. */
00379 #define BM_CRC_DATAHL_DATAHL (0xFFU)       /*!< Bit mask for CRC_DATAHL_DATAHL. */
00380 #define BS_CRC_DATAHL_DATAHL (8U)          /*!< Bit field size in bits for CRC_DATAHL_DATAHL. */
00381 
00382 /*! @brief Read current value of the CRC_DATAHL_DATAHL field. */
00383 #define BR_CRC_DATAHL_DATAHL(x) (HW_CRC_DATAHL(x).U)
00384 
00385 /*! @brief Format value for bitfield CRC_DATAHL_DATAHL. */
00386 #define BF_CRC_DATAHL_DATAHL(v) ((uint8_t)((uint8_t)(v) << BP_CRC_DATAHL_DATAHL) & BM_CRC_DATAHL_DATAHL)
00387 
00388 /*! @brief Set the DATAHL field to a new value. */
00389 #define BW_CRC_DATAHL_DATAHL(x, v) (HW_CRC_DATAHL_WR(x, v))
00390 /*@}*/
00391 /*******************************************************************************
00392  * HW_CRC_DATAHU - CRC_DATAHU register.
00393  ******************************************************************************/
00394 
00395 /*!
00396  * @brief HW_CRC_DATAHU - CRC_DATAHU register. (RW)
00397  *
00398  * Reset value: 0xFFU
00399  */
00400 typedef union _hw_crc_datahu
00401 {
00402     uint8_t U;
00403     struct _hw_crc_datahu_bitfields
00404     {
00405         uint8_t DATAHU : 8;            /*!< [7:0] DATAHU stores the fourth 8 bits of the
00406                                         * 32 bit CRC */
00407     } B;
00408 } hw_crc_datahu_t;
00409 
00410 /*!
00411  * @name Constants and macros for entire CRC_DATAHU register
00412  */
00413 /*@{*/
00414 #define HW_CRC_DATAHU_ADDR(x)    ((x) + 0x3U)
00415 
00416 #define HW_CRC_DATAHU(x)         (*(__IO hw_crc_datahu_t *) HW_CRC_DATAHU_ADDR(x))
00417 #define HW_CRC_DATAHU_RD(x)      (ADDRESS_READ(hw_crc_datahu_t, HW_CRC_DATAHU_ADDR(x)))
00418 #define HW_CRC_DATAHU_WR(x, v)   (ADDRESS_WRITE(hw_crc_datahu_t, HW_CRC_DATAHU_ADDR(x), v))
00419 #define HW_CRC_DATAHU_SET(x, v)  (HW_CRC_DATAHU_WR(x, HW_CRC_DATAHU_RD(x) |  (v)))
00420 #define HW_CRC_DATAHU_CLR(x, v)  (HW_CRC_DATAHU_WR(x, HW_CRC_DATAHU_RD(x) & ~(v)))
00421 #define HW_CRC_DATAHU_TOG(x, v)  (HW_CRC_DATAHU_WR(x, HW_CRC_DATAHU_RD(x) ^  (v)))
00422 /*@}*/
00423 
00424 /*
00425  * Constants & macros for individual CRC_DATAHU bitfields
00426  */
00427 
00428 /*!
00429  * @name Register CRC_DATAHU, field DATAHU[7:0] (RW)
00430  */
00431 /*@{*/
00432 #define BP_CRC_DATAHU_DATAHU (0U)          /*!< Bit position for CRC_DATAHU_DATAHU. */
00433 #define BM_CRC_DATAHU_DATAHU (0xFFU)       /*!< Bit mask for CRC_DATAHU_DATAHU. */
00434 #define BS_CRC_DATAHU_DATAHU (8U)          /*!< Bit field size in bits for CRC_DATAHU_DATAHU. */
00435 
00436 /*! @brief Read current value of the CRC_DATAHU_DATAHU field. */
00437 #define BR_CRC_DATAHU_DATAHU(x) (HW_CRC_DATAHU(x).U)
00438 
00439 /*! @brief Format value for bitfield CRC_DATAHU_DATAHU. */
00440 #define BF_CRC_DATAHU_DATAHU(v) ((uint8_t)((uint8_t)(v) << BP_CRC_DATAHU_DATAHU) & BM_CRC_DATAHU_DATAHU)
00441 
00442 /*! @brief Set the DATAHU field to a new value. */
00443 #define BW_CRC_DATAHU_DATAHU(x, v) (HW_CRC_DATAHU_WR(x, v))
00444 /*@}*/
00445 /*******************************************************************************
00446  * HW_CRC_DATA - CRC Data register
00447  ******************************************************************************/
00448 
00449 /*!
00450  * @brief HW_CRC_DATA - CRC Data register (RW)
00451  *
00452  * Reset value: 0xFFFFFFFFU
00453  *
00454  * The CRC Data register contains the value of the seed, data, and checksum.
00455  * When CTRL[WAS] is set, any write to the data register is regarded as the seed
00456  * value. When CTRL[WAS] is cleared, any write to the data register is regarded as
00457  * data for general CRC computation. In 16-bit CRC mode, the HU and HL fields are
00458  * not used for programming the seed value, and reads of these fields return an
00459  * indeterminate value. In 32-bit CRC mode, all fields are used for programming
00460  * the seed value. When programming data values, the values can be written 8 bits,
00461  * 16 bits, or 32 bits at a time, provided all bytes are contiguous; with MSB of
00462  * data value written first. After all data values are written, the CRC result
00463  * can be read from this data register. In 16-bit CRC mode, the CRC result is
00464  * available in the LU and LL fields. In 32-bit CRC mode, all fields contain the
00465  * result. Reads of this register at any time return the intermediate CRC value,
00466  * provided the CRC module is configured.
00467  */
00468 typedef union _hw_crc_data
00469 {
00470     uint32_t U;
00471     struct _hw_crc_data_bitfields
00472     {
00473         uint32_t LL : 8;               /*!< [7:0] CRC Low Lower Byte */
00474         uint32_t LU : 8;               /*!< [15:8] CRC Low Upper Byte */
00475         uint32_t HL : 8;               /*!< [23:16] CRC High Lower Byte */
00476         uint32_t HU : 8;               /*!< [31:24] CRC High Upper Byte */
00477     } B;
00478 } hw_crc_data_t;
00479 
00480 /*!
00481  * @name Constants and macros for entire CRC_DATA register
00482  */
00483 /*@{*/
00484 #define HW_CRC_DATA_ADDR(x)      ((x) + 0x0U)
00485 
00486 #define HW_CRC_DATA(x)           (*(__IO hw_crc_data_t *) HW_CRC_DATA_ADDR(x))
00487 #define HW_CRC_DATA_RD(x)        (ADDRESS_READ(hw_crc_data_t, HW_CRC_DATA_ADDR(x)))
00488 #define HW_CRC_DATA_WR(x, v)     (ADDRESS_WRITE(hw_crc_data_t, HW_CRC_DATA_ADDR(x), v))
00489 #define HW_CRC_DATA_SET(x, v)    (HW_CRC_DATA_WR(x, HW_CRC_DATA_RD(x) |  (v)))
00490 #define HW_CRC_DATA_CLR(x, v)    (HW_CRC_DATA_WR(x, HW_CRC_DATA_RD(x) & ~(v)))
00491 #define HW_CRC_DATA_TOG(x, v)    (HW_CRC_DATA_WR(x, HW_CRC_DATA_RD(x) ^  (v)))
00492 /*@}*/
00493 
00494 /*
00495  * Constants & macros for individual CRC_DATA bitfields
00496  */
00497 
00498 /*!
00499  * @name Register CRC_DATA, field LL[7:0] (RW)
00500  *
00501  * When CTRL[WAS] is 1, values written to this field are part of the seed value.
00502  * When CTRL[WAS] is 0, data written to this field is used for CRC checksum
00503  * generation.
00504  */
00505 /*@{*/
00506 #define BP_CRC_DATA_LL       (0U)          /*!< Bit position for CRC_DATA_LL. */
00507 #define BM_CRC_DATA_LL       (0x000000FFU) /*!< Bit mask for CRC_DATA_LL. */
00508 #define BS_CRC_DATA_LL       (8U)          /*!< Bit field size in bits for CRC_DATA_LL. */
00509 
00510 /*! @brief Read current value of the CRC_DATA_LL field. */
00511 #define BR_CRC_DATA_LL(x)    (UNION_READ(hw_crc_data_t, HW_CRC_DATA_ADDR(x), U, B.LL))
00512 
00513 /*! @brief Format value for bitfield CRC_DATA_LL. */
00514 #define BF_CRC_DATA_LL(v)    ((uint32_t)((uint32_t)(v) << BP_CRC_DATA_LL) & BM_CRC_DATA_LL)
00515 
00516 /*! @brief Set the LL field to a new value. */
00517 #define BW_CRC_DATA_LL(x, v) (HW_CRC_DATA_WR(x, (HW_CRC_DATA_RD(x) & ~BM_CRC_DATA_LL) | BF_CRC_DATA_LL(v)))
00518 /*@}*/
00519 
00520 /*!
00521  * @name Register CRC_DATA, field LU[15:8] (RW)
00522  *
00523  * When CTRL[WAS] is 1, values written to this field are part of the seed value.
00524  * When CTRL[WAS] is 0, data written to this field is used for CRC checksum
00525  * generation.
00526  */
00527 /*@{*/
00528 #define BP_CRC_DATA_LU       (8U)          /*!< Bit position for CRC_DATA_LU. */
00529 #define BM_CRC_DATA_LU       (0x0000FF00U) /*!< Bit mask for CRC_DATA_LU. */
00530 #define BS_CRC_DATA_LU       (8U)          /*!< Bit field size in bits for CRC_DATA_LU. */
00531 
00532 /*! @brief Read current value of the CRC_DATA_LU field. */
00533 #define BR_CRC_DATA_LU(x)    (UNION_READ(hw_crc_data_t, HW_CRC_DATA_ADDR(x), U, B.LU))
00534 
00535 /*! @brief Format value for bitfield CRC_DATA_LU. */
00536 #define BF_CRC_DATA_LU(v)    ((uint32_t)((uint32_t)(v) << BP_CRC_DATA_LU) & BM_CRC_DATA_LU)
00537 
00538 /*! @brief Set the LU field to a new value. */
00539 #define BW_CRC_DATA_LU(x, v) (HW_CRC_DATA_WR(x, (HW_CRC_DATA_RD(x) & ~BM_CRC_DATA_LU) | BF_CRC_DATA_LU(v)))
00540 /*@}*/
00541 
00542 /*!
00543  * @name Register CRC_DATA, field HL[23:16] (RW)
00544  *
00545  * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming
00546  * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this
00547  * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data
00548  * written to this field is used for CRC checksum generation in both 16-bit and
00549  * 32-bit CRC modes.
00550  */
00551 /*@{*/
00552 #define BP_CRC_DATA_HL       (16U)         /*!< Bit position for CRC_DATA_HL. */
00553 #define BM_CRC_DATA_HL       (0x00FF0000U) /*!< Bit mask for CRC_DATA_HL. */
00554 #define BS_CRC_DATA_HL       (8U)          /*!< Bit field size in bits for CRC_DATA_HL. */
00555 
00556 /*! @brief Read current value of the CRC_DATA_HL field. */
00557 #define BR_CRC_DATA_HL(x)    (UNION_READ(hw_crc_data_t, HW_CRC_DATA_ADDR(x), U, B.HL))
00558 
00559 /*! @brief Format value for bitfield CRC_DATA_HL. */
00560 #define BF_CRC_DATA_HL(v)    ((uint32_t)((uint32_t)(v) << BP_CRC_DATA_HL) & BM_CRC_DATA_HL)
00561 
00562 /*! @brief Set the HL field to a new value. */
00563 #define BW_CRC_DATA_HL(x, v) (HW_CRC_DATA_WR(x, (HW_CRC_DATA_RD(x) & ~BM_CRC_DATA_HL) | BF_CRC_DATA_HL(v)))
00564 /*@}*/
00565 
00566 /*!
00567  * @name Register CRC_DATA, field HU[31:24] (RW)
00568  *
00569  * In 16-bit CRC mode (CTRL[TCRC] is 0), this field is not used for programming
00570  * a seed value. In 32-bit CRC mode (CTRL[TCRC] is 1), values written to this
00571  * field are part of the seed value when CTRL[WAS] is 1. When CTRL[WAS] is 0, data
00572  * written to this field is used for CRC checksum generation in both 16-bit and
00573  * 32-bit CRC modes.
00574  */
00575 /*@{*/
00576 #define BP_CRC_DATA_HU       (24U)         /*!< Bit position for CRC_DATA_HU. */
00577 #define BM_CRC_DATA_HU       (0xFF000000U) /*!< Bit mask for CRC_DATA_HU. */
00578 #define BS_CRC_DATA_HU       (8U)          /*!< Bit field size in bits for CRC_DATA_HU. */
00579 
00580 /*! @brief Read current value of the CRC_DATA_HU field. */
00581 #define BR_CRC_DATA_HU(x)    (UNION_READ(hw_crc_data_t, HW_CRC_DATA_ADDR(x), U, B.HU))
00582 
00583 /*! @brief Format value for bitfield CRC_DATA_HU. */
00584 #define BF_CRC_DATA_HU(v)    ((uint32_t)((uint32_t)(v) << BP_CRC_DATA_HU) & BM_CRC_DATA_HU)
00585 
00586 /*! @brief Set the HU field to a new value. */
00587 #define BW_CRC_DATA_HU(x, v) (HW_CRC_DATA_WR(x, (HW_CRC_DATA_RD(x) & ~BM_CRC_DATA_HU) | BF_CRC_DATA_HU(v)))
00588 /*@}*/
00589 
00590 /*******************************************************************************
00591  * HW_CRC_GPOLY - CRC Polynomial register
00592  ******************************************************************************/
00593 
00594 /*!
00595  * @brief HW_CRC_GPOLY - CRC Polynomial register (RW)
00596  *
00597  * Reset value: 0x00001021U
00598  *
00599  * This register contains the value of the polynomial for the CRC calculation.
00600  * The HIGH field contains the upper 16 bits of the CRC polynomial, which are used
00601  * only in 32-bit CRC mode. Writes to the HIGH field are ignored in 16-bit CRC
00602  * mode. The LOW field contains the lower 16 bits of the CRC polynomial, which are
00603  * used in both 16- and 32-bit CRC modes.
00604  */
00605 typedef union _hw_crc_gpoly
00606 {
00607     uint32_t U;
00608     struct _hw_crc_gpoly_bitfields
00609     {
00610         uint32_t LOW : 16;             /*!< [15:0] Low Polynominal Half-word */
00611         uint32_t HIGH : 16;            /*!< [31:16] High Polynominal Half-word */
00612     } B;
00613 } hw_crc_gpoly_t;
00614 
00615 /*!
00616  * @name Constants and macros for entire CRC_GPOLY register
00617  */
00618 /*@{*/
00619 #define HW_CRC_GPOLY_ADDR(x)     ((x) + 0x4U)
00620 
00621 #define HW_CRC_GPOLY(x)          (*(__IO hw_crc_gpoly_t *) HW_CRC_GPOLY_ADDR(x))
00622 #define HW_CRC_GPOLY_RD(x)       (ADDRESS_READ(hw_crc_gpoly_t, HW_CRC_GPOLY_ADDR(x)))
00623 #define HW_CRC_GPOLY_WR(x, v)    (ADDRESS_WRITE(hw_crc_gpoly_t, HW_CRC_GPOLY_ADDR(x), v))
00624 #define HW_CRC_GPOLY_SET(x, v)   (HW_CRC_GPOLY_WR(x, HW_CRC_GPOLY_RD(x) |  (v)))
00625 #define HW_CRC_GPOLY_CLR(x, v)   (HW_CRC_GPOLY_WR(x, HW_CRC_GPOLY_RD(x) & ~(v)))
00626 #define HW_CRC_GPOLY_TOG(x, v)   (HW_CRC_GPOLY_WR(x, HW_CRC_GPOLY_RD(x) ^  (v)))
00627 /*@}*/
00628 
00629 /*
00630  * Constants & macros for individual CRC_GPOLY bitfields
00631  */
00632 
00633 /*!
00634  * @name Register CRC_GPOLY, field LOW[15:0] (RW)
00635  *
00636  * Writable and readable in both 32-bit and 16-bit CRC modes.
00637  */
00638 /*@{*/
00639 #define BP_CRC_GPOLY_LOW     (0U)          /*!< Bit position for CRC_GPOLY_LOW. */
00640 #define BM_CRC_GPOLY_LOW     (0x0000FFFFU) /*!< Bit mask for CRC_GPOLY_LOW. */
00641 #define BS_CRC_GPOLY_LOW     (16U)         /*!< Bit field size in bits for CRC_GPOLY_LOW. */
00642 
00643 /*! @brief Read current value of the CRC_GPOLY_LOW field. */
00644 #define BR_CRC_GPOLY_LOW(x)  (UNION_READ(hw_crc_gpoly_t, HW_CRC_GPOLY_ADDR(x), U, B.LOW))
00645 
00646 /*! @brief Format value for bitfield CRC_GPOLY_LOW. */
00647 #define BF_CRC_GPOLY_LOW(v)  ((uint32_t)((uint32_t)(v) << BP_CRC_GPOLY_LOW) & BM_CRC_GPOLY_LOW)
00648 
00649 /*! @brief Set the LOW field to a new value. */
00650 #define BW_CRC_GPOLY_LOW(x, v) (HW_CRC_GPOLY_WR(x, (HW_CRC_GPOLY_RD(x) & ~BM_CRC_GPOLY_LOW) | BF_CRC_GPOLY_LOW(v)))
00651 /*@}*/
00652 
00653 /*!
00654  * @name Register CRC_GPOLY, field HIGH[31:16] (RW)
00655  *
00656  * Writable and readable in 32-bit CRC mode (CTRL[TCRC] is 1). This field is not
00657  * writable in 16-bit CRC mode (CTRL[TCRC] is 0).
00658  */
00659 /*@{*/
00660 #define BP_CRC_GPOLY_HIGH    (16U)         /*!< Bit position for CRC_GPOLY_HIGH. */
00661 #define BM_CRC_GPOLY_HIGH    (0xFFFF0000U) /*!< Bit mask for CRC_GPOLY_HIGH. */
00662 #define BS_CRC_GPOLY_HIGH    (16U)         /*!< Bit field size in bits for CRC_GPOLY_HIGH. */
00663 
00664 /*! @brief Read current value of the CRC_GPOLY_HIGH field. */
00665 #define BR_CRC_GPOLY_HIGH(x) (UNION_READ(hw_crc_gpoly_t, HW_CRC_GPOLY_ADDR(x), U, B.HIGH))
00666 
00667 /*! @brief Format value for bitfield CRC_GPOLY_HIGH. */
00668 #define BF_CRC_GPOLY_HIGH(v) ((uint32_t)((uint32_t)(v) << BP_CRC_GPOLY_HIGH) & BM_CRC_GPOLY_HIGH)
00669 
00670 /*! @brief Set the HIGH field to a new value. */
00671 #define BW_CRC_GPOLY_HIGH(x, v) (HW_CRC_GPOLY_WR(x, (HW_CRC_GPOLY_RD(x) & ~BM_CRC_GPOLY_HIGH) | BF_CRC_GPOLY_HIGH(v)))
00672 /*@}*/
00673 /*******************************************************************************
00674  * HW_CRC_GPOLYL - CRC_GPOLYL register.
00675  ******************************************************************************/
00676 
00677 /*!
00678  * @brief HW_CRC_GPOLYL - CRC_GPOLYL register. (RW)
00679  *
00680  * Reset value: 0xFFFFU
00681  */
00682 typedef union _hw_crc_gpolyl
00683 {
00684     uint16_t U;
00685     struct _hw_crc_gpolyl_bitfields
00686     {
00687         uint16_t GPOLYL : 16;          /*!< [15:0] POLYL stores the lower 16 bits of
00688                                         * the 16/32 bit CRC polynomial value */
00689     } B;
00690 } hw_crc_gpolyl_t;
00691 
00692 /*!
00693  * @name Constants and macros for entire CRC_GPOLYL register
00694  */
00695 /*@{*/
00696 #define HW_CRC_GPOLYL_ADDR(x)    ((x) + 0x4U)
00697 
00698 #define HW_CRC_GPOLYL(x)         (*(__IO hw_crc_gpolyl_t *) HW_CRC_GPOLYL_ADDR(x))
00699 #define HW_CRC_GPOLYL_RD(x)      (ADDRESS_READ(hw_crc_gpolyl_t, HW_CRC_GPOLYL_ADDR(x)))
00700 #define HW_CRC_GPOLYL_WR(x, v)   (ADDRESS_WRITE(hw_crc_gpolyl_t, HW_CRC_GPOLYL_ADDR(x), v))
00701 #define HW_CRC_GPOLYL_SET(x, v)  (HW_CRC_GPOLYL_WR(x, HW_CRC_GPOLYL_RD(x) |  (v)))
00702 #define HW_CRC_GPOLYL_CLR(x, v)  (HW_CRC_GPOLYL_WR(x, HW_CRC_GPOLYL_RD(x) & ~(v)))
00703 #define HW_CRC_GPOLYL_TOG(x, v)  (HW_CRC_GPOLYL_WR(x, HW_CRC_GPOLYL_RD(x) ^  (v)))
00704 /*@}*/
00705 
00706 /*
00707  * Constants & macros for individual CRC_GPOLYL bitfields
00708  */
00709 
00710 /*!
00711  * @name Register CRC_GPOLYL, field GPOLYL[15:0] (RW)
00712  */
00713 /*@{*/
00714 #define BP_CRC_GPOLYL_GPOLYL (0U)          /*!< Bit position for CRC_GPOLYL_GPOLYL. */
00715 #define BM_CRC_GPOLYL_GPOLYL (0xFFFFU)     /*!< Bit mask for CRC_GPOLYL_GPOLYL. */
00716 #define BS_CRC_GPOLYL_GPOLYL (16U)         /*!< Bit field size in bits for CRC_GPOLYL_GPOLYL. */
00717 
00718 /*! @brief Read current value of the CRC_GPOLYL_GPOLYL field. */
00719 #define BR_CRC_GPOLYL_GPOLYL(x) (HW_CRC_GPOLYL(x).U)
00720 
00721 /*! @brief Format value for bitfield CRC_GPOLYL_GPOLYL. */
00722 #define BF_CRC_GPOLYL_GPOLYL(v) ((uint16_t)((uint16_t)(v) << BP_CRC_GPOLYL_GPOLYL) & BM_CRC_GPOLYL_GPOLYL)
00723 
00724 /*! @brief Set the GPOLYL field to a new value. */
00725 #define BW_CRC_GPOLYL_GPOLYL(x, v) (HW_CRC_GPOLYL_WR(x, v))
00726 /*@}*/
00727 /*******************************************************************************
00728  * HW_CRC_GPOLYH - CRC_GPOLYH register.
00729  ******************************************************************************/
00730 
00731 /*!
00732  * @brief HW_CRC_GPOLYH - CRC_GPOLYH register. (RW)
00733  *
00734  * Reset value: 0xFFFFU
00735  */
00736 typedef union _hw_crc_gpolyh
00737 {
00738     uint16_t U;
00739     struct _hw_crc_gpolyh_bitfields
00740     {
00741         uint16_t GPOLYH : 16;          /*!< [15:0] POLYH stores the high 16 bits of
00742                                         * the 16/32 bit CRC polynomial value */
00743     } B;
00744 } hw_crc_gpolyh_t;
00745 
00746 /*!
00747  * @name Constants and macros for entire CRC_GPOLYH register
00748  */
00749 /*@{*/
00750 #define HW_CRC_GPOLYH_ADDR(x)    ((x) + 0x6U)
00751 
00752 #define HW_CRC_GPOLYH(x)         (*(__IO hw_crc_gpolyh_t *) HW_CRC_GPOLYH_ADDR(x))
00753 #define HW_CRC_GPOLYH_RD(x)      (ADDRESS_READ(hw_crc_gpolyh_t, HW_CRC_GPOLYH_ADDR(x)))
00754 #define HW_CRC_GPOLYH_WR(x, v)   (ADDRESS_WRITE(hw_crc_gpolyh_t, HW_CRC_GPOLYH_ADDR(x), v))
00755 #define HW_CRC_GPOLYH_SET(x, v)  (HW_CRC_GPOLYH_WR(x, HW_CRC_GPOLYH_RD(x) |  (v)))
00756 #define HW_CRC_GPOLYH_CLR(x, v)  (HW_CRC_GPOLYH_WR(x, HW_CRC_GPOLYH_RD(x) & ~(v)))
00757 #define HW_CRC_GPOLYH_TOG(x, v)  (HW_CRC_GPOLYH_WR(x, HW_CRC_GPOLYH_RD(x) ^  (v)))
00758 /*@}*/
00759 
00760 /*
00761  * Constants & macros for individual CRC_GPOLYH bitfields
00762  */
00763 
00764 /*!
00765  * @name Register CRC_GPOLYH, field GPOLYH[15:0] (RW)
00766  */
00767 /*@{*/
00768 #define BP_CRC_GPOLYH_GPOLYH (0U)          /*!< Bit position for CRC_GPOLYH_GPOLYH. */
00769 #define BM_CRC_GPOLYH_GPOLYH (0xFFFFU)     /*!< Bit mask for CRC_GPOLYH_GPOLYH. */
00770 #define BS_CRC_GPOLYH_GPOLYH (16U)         /*!< Bit field size in bits for CRC_GPOLYH_GPOLYH. */
00771 
00772 /*! @brief Read current value of the CRC_GPOLYH_GPOLYH field. */
00773 #define BR_CRC_GPOLYH_GPOLYH(x) (HW_CRC_GPOLYH(x).U)
00774 
00775 /*! @brief Format value for bitfield CRC_GPOLYH_GPOLYH. */
00776 #define BF_CRC_GPOLYH_GPOLYH(v) ((uint16_t)((uint16_t)(v) << BP_CRC_GPOLYH_GPOLYH) & BM_CRC_GPOLYH_GPOLYH)
00777 
00778 /*! @brief Set the GPOLYH field to a new value. */
00779 #define BW_CRC_GPOLYH_GPOLYH(x, v) (HW_CRC_GPOLYH_WR(x, v))
00780 /*@}*/
00781 /*******************************************************************************
00782  * HW_CRC_GPOLYLL - CRC_GPOLYLL register.
00783  ******************************************************************************/
00784 
00785 /*!
00786  * @brief HW_CRC_GPOLYLL - CRC_GPOLYLL register. (RW)
00787  *
00788  * Reset value: 0xFFU
00789  */
00790 typedef union _hw_crc_gpolyll
00791 {
00792     uint8_t U;
00793     struct _hw_crc_gpolyll_bitfields
00794     {
00795         uint8_t GPOLYLL : 8;           /*!< [7:0] POLYLL stores the first 8 bits of the
00796                                         * 32 bit CRC */
00797     } B;
00798 } hw_crc_gpolyll_t;
00799 
00800 /*!
00801  * @name Constants and macros for entire CRC_GPOLYLL register
00802  */
00803 /*@{*/
00804 #define HW_CRC_GPOLYLL_ADDR(x)   ((x) + 0x4U)
00805 
00806 #define HW_CRC_GPOLYLL(x)        (*(__IO hw_crc_gpolyll_t *) HW_CRC_GPOLYLL_ADDR(x))
00807 #define HW_CRC_GPOLYLL_RD(x)     (ADDRESS_READ(hw_crc_gpolyll_t, HW_CRC_GPOLYLL_ADDR(x)))
00808 #define HW_CRC_GPOLYLL_WR(x, v)  (ADDRESS_WRITE(hw_crc_gpolyll_t, HW_CRC_GPOLYLL_ADDR(x), v))
00809 #define HW_CRC_GPOLYLL_SET(x, v) (HW_CRC_GPOLYLL_WR(x, HW_CRC_GPOLYLL_RD(x) |  (v)))
00810 #define HW_CRC_GPOLYLL_CLR(x, v) (HW_CRC_GPOLYLL_WR(x, HW_CRC_GPOLYLL_RD(x) & ~(v)))
00811 #define HW_CRC_GPOLYLL_TOG(x, v) (HW_CRC_GPOLYLL_WR(x, HW_CRC_GPOLYLL_RD(x) ^  (v)))
00812 /*@}*/
00813 
00814 /*
00815  * Constants & macros for individual CRC_GPOLYLL bitfields
00816  */
00817 
00818 /*!
00819  * @name Register CRC_GPOLYLL, field GPOLYLL[7:0] (RW)
00820  */
00821 /*@{*/
00822 #define BP_CRC_GPOLYLL_GPOLYLL (0U)        /*!< Bit position for CRC_GPOLYLL_GPOLYLL. */
00823 #define BM_CRC_GPOLYLL_GPOLYLL (0xFFU)     /*!< Bit mask for CRC_GPOLYLL_GPOLYLL. */
00824 #define BS_CRC_GPOLYLL_GPOLYLL (8U)        /*!< Bit field size in bits for CRC_GPOLYLL_GPOLYLL. */
00825 
00826 /*! @brief Read current value of the CRC_GPOLYLL_GPOLYLL field. */
00827 #define BR_CRC_GPOLYLL_GPOLYLL(x) (HW_CRC_GPOLYLL(x).U)
00828 
00829 /*! @brief Format value for bitfield CRC_GPOLYLL_GPOLYLL. */
00830 #define BF_CRC_GPOLYLL_GPOLYLL(v) ((uint8_t)((uint8_t)(v) << BP_CRC_GPOLYLL_GPOLYLL) & BM_CRC_GPOLYLL_GPOLYLL)
00831 
00832 /*! @brief Set the GPOLYLL field to a new value. */
00833 #define BW_CRC_GPOLYLL_GPOLYLL(x, v) (HW_CRC_GPOLYLL_WR(x, v))
00834 /*@}*/
00835 /*******************************************************************************
00836  * HW_CRC_GPOLYLU - CRC_GPOLYLU register.
00837  ******************************************************************************/
00838 
00839 /*!
00840  * @brief HW_CRC_GPOLYLU - CRC_GPOLYLU register. (RW)
00841  *
00842  * Reset value: 0xFFU
00843  */
00844 typedef union _hw_crc_gpolylu
00845 {
00846     uint8_t U;
00847     struct _hw_crc_gpolylu_bitfields
00848     {
00849         uint8_t GPOLYLU : 8;           /*!< [7:0] POLYLL stores the second 8 bits of
00850                                         * the 32 bit CRC */
00851     } B;
00852 } hw_crc_gpolylu_t;
00853 
00854 /*!
00855  * @name Constants and macros for entire CRC_GPOLYLU register
00856  */
00857 /*@{*/
00858 #define HW_CRC_GPOLYLU_ADDR(x)   ((x) + 0x5U)
00859 
00860 #define HW_CRC_GPOLYLU(x)        (*(__IO hw_crc_gpolylu_t *) HW_CRC_GPOLYLU_ADDR(x))
00861 #define HW_CRC_GPOLYLU_RD(x)     (ADDRESS_READ(hw_crc_gpolylu_t, HW_CRC_GPOLYLU_ADDR(x)))
00862 #define HW_CRC_GPOLYLU_WR(x, v)  (ADDRESS_WRITE(hw_crc_gpolylu_t, HW_CRC_GPOLYLU_ADDR(x), v))
00863 #define HW_CRC_GPOLYLU_SET(x, v) (HW_CRC_GPOLYLU_WR(x, HW_CRC_GPOLYLU_RD(x) |  (v)))
00864 #define HW_CRC_GPOLYLU_CLR(x, v) (HW_CRC_GPOLYLU_WR(x, HW_CRC_GPOLYLU_RD(x) & ~(v)))
00865 #define HW_CRC_GPOLYLU_TOG(x, v) (HW_CRC_GPOLYLU_WR(x, HW_CRC_GPOLYLU_RD(x) ^  (v)))
00866 /*@}*/
00867 
00868 /*
00869  * Constants & macros for individual CRC_GPOLYLU bitfields
00870  */
00871 
00872 /*!
00873  * @name Register CRC_GPOLYLU, field GPOLYLU[7:0] (RW)
00874  */
00875 /*@{*/
00876 #define BP_CRC_GPOLYLU_GPOLYLU (0U)        /*!< Bit position for CRC_GPOLYLU_GPOLYLU. */
00877 #define BM_CRC_GPOLYLU_GPOLYLU (0xFFU)     /*!< Bit mask for CRC_GPOLYLU_GPOLYLU. */
00878 #define BS_CRC_GPOLYLU_GPOLYLU (8U)        /*!< Bit field size in bits for CRC_GPOLYLU_GPOLYLU. */
00879 
00880 /*! @brief Read current value of the CRC_GPOLYLU_GPOLYLU field. */
00881 #define BR_CRC_GPOLYLU_GPOLYLU(x) (HW_CRC_GPOLYLU(x).U)
00882 
00883 /*! @brief Format value for bitfield CRC_GPOLYLU_GPOLYLU. */
00884 #define BF_CRC_GPOLYLU_GPOLYLU(v) ((uint8_t)((uint8_t)(v) << BP_CRC_GPOLYLU_GPOLYLU) & BM_CRC_GPOLYLU_GPOLYLU)
00885 
00886 /*! @brief Set the GPOLYLU field to a new value. */
00887 #define BW_CRC_GPOLYLU_GPOLYLU(x, v) (HW_CRC_GPOLYLU_WR(x, v))
00888 /*@}*/
00889 /*******************************************************************************
00890  * HW_CRC_GPOLYHL - CRC_GPOLYHL register.
00891  ******************************************************************************/
00892 
00893 /*!
00894  * @brief HW_CRC_GPOLYHL - CRC_GPOLYHL register. (RW)
00895  *
00896  * Reset value: 0xFFU
00897  */
00898 typedef union _hw_crc_gpolyhl
00899 {
00900     uint8_t U;
00901     struct _hw_crc_gpolyhl_bitfields
00902     {
00903         uint8_t GPOLYHL : 8;           /*!< [7:0] POLYHL stores the third 8 bits of the
00904                                         * 32 bit CRC */
00905     } B;
00906 } hw_crc_gpolyhl_t;
00907 
00908 /*!
00909  * @name Constants and macros for entire CRC_GPOLYHL register
00910  */
00911 /*@{*/
00912 #define HW_CRC_GPOLYHL_ADDR(x)   ((x) + 0x6U)
00913 
00914 #define HW_CRC_GPOLYHL(x)        (*(__IO hw_crc_gpolyhl_t *) HW_CRC_GPOLYHL_ADDR(x))
00915 #define HW_CRC_GPOLYHL_RD(x)     (ADDRESS_READ(hw_crc_gpolyhl_t, HW_CRC_GPOLYHL_ADDR(x)))
00916 #define HW_CRC_GPOLYHL_WR(x, v)  (ADDRESS_WRITE(hw_crc_gpolyhl_t, HW_CRC_GPOLYHL_ADDR(x), v))
00917 #define HW_CRC_GPOLYHL_SET(x, v) (HW_CRC_GPOLYHL_WR(x, HW_CRC_GPOLYHL_RD(x) |  (v)))
00918 #define HW_CRC_GPOLYHL_CLR(x, v) (HW_CRC_GPOLYHL_WR(x, HW_CRC_GPOLYHL_RD(x) & ~(v)))
00919 #define HW_CRC_GPOLYHL_TOG(x, v) (HW_CRC_GPOLYHL_WR(x, HW_CRC_GPOLYHL_RD(x) ^  (v)))
00920 /*@}*/
00921 
00922 /*
00923  * Constants & macros for individual CRC_GPOLYHL bitfields
00924  */
00925 
00926 /*!
00927  * @name Register CRC_GPOLYHL, field GPOLYHL[7:0] (RW)
00928  */
00929 /*@{*/
00930 #define BP_CRC_GPOLYHL_GPOLYHL (0U)        /*!< Bit position for CRC_GPOLYHL_GPOLYHL. */
00931 #define BM_CRC_GPOLYHL_GPOLYHL (0xFFU)     /*!< Bit mask for CRC_GPOLYHL_GPOLYHL. */
00932 #define BS_CRC_GPOLYHL_GPOLYHL (8U)        /*!< Bit field size in bits for CRC_GPOLYHL_GPOLYHL. */
00933 
00934 /*! @brief Read current value of the CRC_GPOLYHL_GPOLYHL field. */
00935 #define BR_CRC_GPOLYHL_GPOLYHL(x) (HW_CRC_GPOLYHL(x).U)
00936 
00937 /*! @brief Format value for bitfield CRC_GPOLYHL_GPOLYHL. */
00938 #define BF_CRC_GPOLYHL_GPOLYHL(v) ((uint8_t)((uint8_t)(v) << BP_CRC_GPOLYHL_GPOLYHL) & BM_CRC_GPOLYHL_GPOLYHL)
00939 
00940 /*! @brief Set the GPOLYHL field to a new value. */
00941 #define BW_CRC_GPOLYHL_GPOLYHL(x, v) (HW_CRC_GPOLYHL_WR(x, v))
00942 /*@}*/
00943 /*******************************************************************************
00944  * HW_CRC_GPOLYHU - CRC_GPOLYHU register.
00945  ******************************************************************************/
00946 
00947 /*!
00948  * @brief HW_CRC_GPOLYHU - CRC_GPOLYHU register. (RW)
00949  *
00950  * Reset value: 0xFFU
00951  */
00952 typedef union _hw_crc_gpolyhu
00953 {
00954     uint8_t U;
00955     struct _hw_crc_gpolyhu_bitfields
00956     {
00957         uint8_t GPOLYHU : 8;           /*!< [7:0] POLYHU stores the fourth 8 bits of
00958                                         * the 32 bit CRC */
00959     } B;
00960 } hw_crc_gpolyhu_t;
00961 
00962 /*!
00963  * @name Constants and macros for entire CRC_GPOLYHU register
00964  */
00965 /*@{*/
00966 #define HW_CRC_GPOLYHU_ADDR(x)   ((x) + 0x7U)
00967 
00968 #define HW_CRC_GPOLYHU(x)        (*(__IO hw_crc_gpolyhu_t *) HW_CRC_GPOLYHU_ADDR(x))
00969 #define HW_CRC_GPOLYHU_RD(x)     (ADDRESS_READ(hw_crc_gpolyhu_t, HW_CRC_GPOLYHU_ADDR(x)))
00970 #define HW_CRC_GPOLYHU_WR(x, v)  (ADDRESS_WRITE(hw_crc_gpolyhu_t, HW_CRC_GPOLYHU_ADDR(x), v))
00971 #define HW_CRC_GPOLYHU_SET(x, v) (HW_CRC_GPOLYHU_WR(x, HW_CRC_GPOLYHU_RD(x) |  (v)))
00972 #define HW_CRC_GPOLYHU_CLR(x, v) (HW_CRC_GPOLYHU_WR(x, HW_CRC_GPOLYHU_RD(x) & ~(v)))
00973 #define HW_CRC_GPOLYHU_TOG(x, v) (HW_CRC_GPOLYHU_WR(x, HW_CRC_GPOLYHU_RD(x) ^  (v)))
00974 /*@}*/
00975 
00976 /*
00977  * Constants & macros for individual CRC_GPOLYHU bitfields
00978  */
00979 
00980 /*!
00981  * @name Register CRC_GPOLYHU, field GPOLYHU[7:0] (RW)
00982  */
00983 /*@{*/
00984 #define BP_CRC_GPOLYHU_GPOLYHU (0U)        /*!< Bit position for CRC_GPOLYHU_GPOLYHU. */
00985 #define BM_CRC_GPOLYHU_GPOLYHU (0xFFU)     /*!< Bit mask for CRC_GPOLYHU_GPOLYHU. */
00986 #define BS_CRC_GPOLYHU_GPOLYHU (8U)        /*!< Bit field size in bits for CRC_GPOLYHU_GPOLYHU. */
00987 
00988 /*! @brief Read current value of the CRC_GPOLYHU_GPOLYHU field. */
00989 #define BR_CRC_GPOLYHU_GPOLYHU(x) (HW_CRC_GPOLYHU(x).U)
00990 
00991 /*! @brief Format value for bitfield CRC_GPOLYHU_GPOLYHU. */
00992 #define BF_CRC_GPOLYHU_GPOLYHU(v) ((uint8_t)((uint8_t)(v) << BP_CRC_GPOLYHU_GPOLYHU) & BM_CRC_GPOLYHU_GPOLYHU)
00993 
00994 /*! @brief Set the GPOLYHU field to a new value. */
00995 #define BW_CRC_GPOLYHU_GPOLYHU(x, v) (HW_CRC_GPOLYHU_WR(x, v))
00996 /*@}*/
00997 
00998 /*******************************************************************************
00999  * HW_CRC_CTRL - CRC Control register
01000  ******************************************************************************/
01001 
01002 /*!
01003  * @brief HW_CRC_CTRL - CRC Control register (RW)
01004  *
01005  * Reset value: 0x00000000U
01006  *
01007  * This register controls the configuration and working of the CRC module.
01008  * Appropriate bits must be set before starting a new CRC calculation. A new CRC
01009  * calculation is initialized by asserting CTRL[WAS] and then writing the seed into
01010  * the CRC data register.
01011  */
01012 typedef union _hw_crc_ctrl
01013 {
01014     uint32_t U;
01015     struct _hw_crc_ctrl_bitfields
01016     {
01017         uint32_t RESERVED0 : 24;       /*!< [23:0]  */
01018         uint32_t TCRC : 1;             /*!< [24]  */
01019         uint32_t WAS : 1;              /*!< [25] Write CRC Data Register As Seed */
01020         uint32_t FXOR : 1;             /*!< [26] Complement Read Of CRC Data Register */
01021         uint32_t RESERVED1 : 1;        /*!< [27]  */
01022         uint32_t TOTR : 2;             /*!< [29:28] Type Of Transpose For Read */
01023         uint32_t TOT : 2;              /*!< [31:30] Type Of Transpose For Writes */
01024     } B;
01025 } hw_crc_ctrl_t;
01026 
01027 /*!
01028  * @name Constants and macros for entire CRC_CTRL register
01029  */
01030 /*@{*/
01031 #define HW_CRC_CTRL_ADDR(x)      ((x) + 0x8U)
01032 
01033 #define HW_CRC_CTRL(x)           (*(__IO hw_crc_ctrl_t *) HW_CRC_CTRL_ADDR(x))
01034 #define HW_CRC_CTRL_RD(x)        (ADDRESS_READ(hw_crc_ctrl_t, HW_CRC_CTRL_ADDR(x)))
01035 #define HW_CRC_CTRL_WR(x, v)     (ADDRESS_WRITE(hw_crc_ctrl_t, HW_CRC_CTRL_ADDR(x), v))
01036 #define HW_CRC_CTRL_SET(x, v)    (HW_CRC_CTRL_WR(x, HW_CRC_CTRL_RD(x) |  (v)))
01037 #define HW_CRC_CTRL_CLR(x, v)    (HW_CRC_CTRL_WR(x, HW_CRC_CTRL_RD(x) & ~(v)))
01038 #define HW_CRC_CTRL_TOG(x, v)    (HW_CRC_CTRL_WR(x, HW_CRC_CTRL_RD(x) ^  (v)))
01039 /*@}*/
01040 
01041 /*
01042  * Constants & macros for individual CRC_CTRL bitfields
01043  */
01044 
01045 /*!
01046  * @name Register CRC_CTRL, field TCRC[24] (RW)
01047  *
01048  * Width of CRC protocol.
01049  *
01050  * Values:
01051  * - 0 - 16-bit CRC protocol.
01052  * - 1 - 32-bit CRC protocol.
01053  */
01054 /*@{*/
01055 #define BP_CRC_CTRL_TCRC     (24U)         /*!< Bit position for CRC_CTRL_TCRC. */
01056 #define BM_CRC_CTRL_TCRC     (0x01000000U) /*!< Bit mask for CRC_CTRL_TCRC. */
01057 #define BS_CRC_CTRL_TCRC     (1U)          /*!< Bit field size in bits for CRC_CTRL_TCRC. */
01058 
01059 /*! @brief Read current value of the CRC_CTRL_TCRC field. */
01060 #define BR_CRC_CTRL_TCRC(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_TCRC)))
01061 
01062 /*! @brief Format value for bitfield CRC_CTRL_TCRC. */
01063 #define BF_CRC_CTRL_TCRC(v)  ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_TCRC) & BM_CRC_CTRL_TCRC)
01064 
01065 /*! @brief Set the TCRC field to a new value. */
01066 #define BW_CRC_CTRL_TCRC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_TCRC), v))
01067 /*@}*/
01068 
01069 /*!
01070  * @name Register CRC_CTRL, field WAS[25] (RW)
01071  *
01072  * When asserted, a value written to the CRC data register is considered a seed
01073  * value. When deasserted, a value written to the CRC data register is taken as
01074  * data for CRC computation.
01075  *
01076  * Values:
01077  * - 0 - Writes to the CRC data register are data values.
01078  * - 1 - Writes to the CRC data register are seed values.
01079  */
01080 /*@{*/
01081 #define BP_CRC_CTRL_WAS      (25U)         /*!< Bit position for CRC_CTRL_WAS. */
01082 #define BM_CRC_CTRL_WAS      (0x02000000U) /*!< Bit mask for CRC_CTRL_WAS. */
01083 #define BS_CRC_CTRL_WAS      (1U)          /*!< Bit field size in bits for CRC_CTRL_WAS. */
01084 
01085 /*! @brief Read current value of the CRC_CTRL_WAS field. */
01086 #define BR_CRC_CTRL_WAS(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_WAS)))
01087 
01088 /*! @brief Format value for bitfield CRC_CTRL_WAS. */
01089 #define BF_CRC_CTRL_WAS(v)   ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_WAS) & BM_CRC_CTRL_WAS)
01090 
01091 /*! @brief Set the WAS field to a new value. */
01092 #define BW_CRC_CTRL_WAS(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_WAS), v))
01093 /*@}*/
01094 
01095 /*!
01096  * @name Register CRC_CTRL, field FXOR[26] (RW)
01097  *
01098  * Some CRC protocols require the final checksum to be XORed with 0xFFFFFFFF or
01099  * 0xFFFF. Asserting this bit enables on the fly complementing of read data.
01100  *
01101  * Values:
01102  * - 0 - No XOR on reading.
01103  * - 1 - Invert or complement the read value of the CRC Data register.
01104  */
01105 /*@{*/
01106 #define BP_CRC_CTRL_FXOR     (26U)         /*!< Bit position for CRC_CTRL_FXOR. */
01107 #define BM_CRC_CTRL_FXOR     (0x04000000U) /*!< Bit mask for CRC_CTRL_FXOR. */
01108 #define BS_CRC_CTRL_FXOR     (1U)          /*!< Bit field size in bits for CRC_CTRL_FXOR. */
01109 
01110 /*! @brief Read current value of the CRC_CTRL_FXOR field. */
01111 #define BR_CRC_CTRL_FXOR(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_FXOR)))
01112 
01113 /*! @brief Format value for bitfield CRC_CTRL_FXOR. */
01114 #define BF_CRC_CTRL_FXOR(v)  ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_FXOR) & BM_CRC_CTRL_FXOR)
01115 
01116 /*! @brief Set the FXOR field to a new value. */
01117 #define BW_CRC_CTRL_FXOR(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_CRC_CTRL_ADDR(x), BP_CRC_CTRL_FXOR), v))
01118 /*@}*/
01119 
01120 /*!
01121  * @name Register CRC_CTRL, field TOTR[29:28] (RW)
01122  *
01123  * Identifies the transpose configuration of the value read from the CRC Data
01124  * register. See the description of the transpose feature for the available
01125  * transpose options.
01126  *
01127  * Values:
01128  * - 00 - No transposition.
01129  * - 01 - Bits in bytes are transposed; bytes are not transposed.
01130  * - 10 - Both bits in bytes and bytes are transposed.
01131  * - 11 - Only bytes are transposed; no bits in a byte are transposed.
01132  */
01133 /*@{*/
01134 #define BP_CRC_CTRL_TOTR     (28U)         /*!< Bit position for CRC_CTRL_TOTR. */
01135 #define BM_CRC_CTRL_TOTR     (0x30000000U) /*!< Bit mask for CRC_CTRL_TOTR. */
01136 #define BS_CRC_CTRL_TOTR     (2U)          /*!< Bit field size in bits for CRC_CTRL_TOTR. */
01137 
01138 /*! @brief Read current value of the CRC_CTRL_TOTR field. */
01139 #define BR_CRC_CTRL_TOTR(x)  (UNION_READ(hw_crc_ctrl_t, HW_CRC_CTRL_ADDR(x), U, B.TOTR))
01140 
01141 /*! @brief Format value for bitfield CRC_CTRL_TOTR. */
01142 #define BF_CRC_CTRL_TOTR(v)  ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_TOTR) & BM_CRC_CTRL_TOTR)
01143 
01144 /*! @brief Set the TOTR field to a new value. */
01145 #define BW_CRC_CTRL_TOTR(x, v) (HW_CRC_CTRL_WR(x, (HW_CRC_CTRL_RD(x) & ~BM_CRC_CTRL_TOTR) | BF_CRC_CTRL_TOTR(v)))
01146 /*@}*/
01147 
01148 /*!
01149  * @name Register CRC_CTRL, field TOT[31:30] (RW)
01150  *
01151  * Defines the transpose configuration of the data written to the CRC data
01152  * register. See the description of the transpose feature for the available transpose
01153  * options.
01154  *
01155  * Values:
01156  * - 00 - No transposition.
01157  * - 01 - Bits in bytes are transposed; bytes are not transposed.
01158  * - 10 - Both bits in bytes and bytes are transposed.
01159  * - 11 - Only bytes are transposed; no bits in a byte are transposed.
01160  */
01161 /*@{*/
01162 #define BP_CRC_CTRL_TOT      (30U)         /*!< Bit position for CRC_CTRL_TOT. */
01163 #define BM_CRC_CTRL_TOT      (0xC0000000U) /*!< Bit mask for CRC_CTRL_TOT. */
01164 #define BS_CRC_CTRL_TOT      (2U)          /*!< Bit field size in bits for CRC_CTRL_TOT. */
01165 
01166 /*! @brief Read current value of the CRC_CTRL_TOT field. */
01167 #define BR_CRC_CTRL_TOT(x)   (UNION_READ(hw_crc_ctrl_t, HW_CRC_CTRL_ADDR(x), U, B.TOT))
01168 
01169 /*! @brief Format value for bitfield CRC_CTRL_TOT. */
01170 #define BF_CRC_CTRL_TOT(v)   ((uint32_t)((uint32_t)(v) << BP_CRC_CTRL_TOT) & BM_CRC_CTRL_TOT)
01171 
01172 /*! @brief Set the TOT field to a new value. */
01173 #define BW_CRC_CTRL_TOT(x, v) (HW_CRC_CTRL_WR(x, (HW_CRC_CTRL_RD(x) & ~BM_CRC_CTRL_TOT) | BF_CRC_CTRL_TOT(v)))
01174 /*@}*/
01175 /*******************************************************************************
01176  * HW_CRC_CTRLHU - CRC_CTRLHU register.
01177  ******************************************************************************/
01178 
01179 /*!
01180  * @brief HW_CRC_CTRLHU - CRC_CTRLHU register. (RW)
01181  *
01182  * Reset value: 0x00U
01183  */
01184 typedef union _hw_crc_ctrlhu
01185 {
01186     uint8_t U;
01187     struct _hw_crc_ctrlhu_bitfields
01188     {
01189         uint8_t TCRC : 1;              /*!< [0]  */
01190         uint8_t WAS : 1;               /*!< [1]  */
01191         uint8_t FXOR : 1;              /*!< [2]  */
01192         uint8_t RESERVED0 : 1;         /*!< [3]  */
01193         uint8_t TOTR : 2;              /*!< [5:4]  */
01194         uint8_t TOT : 2;               /*!< [7:6]  */
01195     } B;
01196 } hw_crc_ctrlhu_t;
01197 
01198 /*!
01199  * @name Constants and macros for entire CRC_CTRLHU register
01200  */
01201 /*@{*/
01202 #define HW_CRC_CTRLHU_ADDR(x)    ((x) + 0xBU)
01203 
01204 #define HW_CRC_CTRLHU(x)         (*(__IO hw_crc_ctrlhu_t *) HW_CRC_CTRLHU_ADDR(x))
01205 #define HW_CRC_CTRLHU_RD(x)      (ADDRESS_READ(hw_crc_ctrlhu_t, HW_CRC_CTRLHU_ADDR(x)))
01206 #define HW_CRC_CTRLHU_WR(x, v)   (ADDRESS_WRITE(hw_crc_ctrlhu_t, HW_CRC_CTRLHU_ADDR(x), v))
01207 #define HW_CRC_CTRLHU_SET(x, v)  (HW_CRC_CTRLHU_WR(x, HW_CRC_CTRLHU_RD(x) |  (v)))
01208 #define HW_CRC_CTRLHU_CLR(x, v)  (HW_CRC_CTRLHU_WR(x, HW_CRC_CTRLHU_RD(x) & ~(v)))
01209 #define HW_CRC_CTRLHU_TOG(x, v)  (HW_CRC_CTRLHU_WR(x, HW_CRC_CTRLHU_RD(x) ^  (v)))
01210 /*@}*/
01211 
01212 /*
01213  * Constants & macros for individual CRC_CTRLHU bitfields
01214  */
01215 
01216 /*!
01217  * @name Register CRC_CTRLHU, field TCRC[0] (RW)
01218  *
01219  * Values:
01220  * - 0 - 16-bit CRC protocol.
01221  * - 1 - 32-bit CRC protocol.
01222  */
01223 /*@{*/
01224 #define BP_CRC_CTRLHU_TCRC   (0U)          /*!< Bit position for CRC_CTRLHU_TCRC. */
01225 #define BM_CRC_CTRLHU_TCRC   (0x01U)       /*!< Bit mask for CRC_CTRLHU_TCRC. */
01226 #define BS_CRC_CTRLHU_TCRC   (1U)          /*!< Bit field size in bits for CRC_CTRLHU_TCRC. */
01227 
01228 /*! @brief Read current value of the CRC_CTRLHU_TCRC field. */
01229 #define BR_CRC_CTRLHU_TCRC(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_TCRC)))
01230 
01231 /*! @brief Format value for bitfield CRC_CTRLHU_TCRC. */
01232 #define BF_CRC_CTRLHU_TCRC(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_TCRC) & BM_CRC_CTRLHU_TCRC)
01233 
01234 /*! @brief Set the TCRC field to a new value. */
01235 #define BW_CRC_CTRLHU_TCRC(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_TCRC), v))
01236 /*@}*/
01237 
01238 /*!
01239  * @name Register CRC_CTRLHU, field WAS[1] (RW)
01240  *
01241  * Values:
01242  * - 0 - Writes to CRC data register are data values.
01243  * - 1 - Writes to CRC data reguster are seed values.
01244  */
01245 /*@{*/
01246 #define BP_CRC_CTRLHU_WAS    (1U)          /*!< Bit position for CRC_CTRLHU_WAS. */
01247 #define BM_CRC_CTRLHU_WAS    (0x02U)       /*!< Bit mask for CRC_CTRLHU_WAS. */
01248 #define BS_CRC_CTRLHU_WAS    (1U)          /*!< Bit field size in bits for CRC_CTRLHU_WAS. */
01249 
01250 /*! @brief Read current value of the CRC_CTRLHU_WAS field. */
01251 #define BR_CRC_CTRLHU_WAS(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_WAS)))
01252 
01253 /*! @brief Format value for bitfield CRC_CTRLHU_WAS. */
01254 #define BF_CRC_CTRLHU_WAS(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_WAS) & BM_CRC_CTRLHU_WAS)
01255 
01256 /*! @brief Set the WAS field to a new value. */
01257 #define BW_CRC_CTRLHU_WAS(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_WAS), v))
01258 /*@}*/
01259 
01260 /*!
01261  * @name Register CRC_CTRLHU, field FXOR[2] (RW)
01262  *
01263  * Values:
01264  * - 0 - No XOR on reading.
01265  * - 1 - Invert or complement the read value of CRC data register.
01266  */
01267 /*@{*/
01268 #define BP_CRC_CTRLHU_FXOR   (2U)          /*!< Bit position for CRC_CTRLHU_FXOR. */
01269 #define BM_CRC_CTRLHU_FXOR   (0x04U)       /*!< Bit mask for CRC_CTRLHU_FXOR. */
01270 #define BS_CRC_CTRLHU_FXOR   (1U)          /*!< Bit field size in bits for CRC_CTRLHU_FXOR. */
01271 
01272 /*! @brief Read current value of the CRC_CTRLHU_FXOR field. */
01273 #define BR_CRC_CTRLHU_FXOR(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_FXOR)))
01274 
01275 /*! @brief Format value for bitfield CRC_CTRLHU_FXOR. */
01276 #define BF_CRC_CTRLHU_FXOR(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_FXOR) & BM_CRC_CTRLHU_FXOR)
01277 
01278 /*! @brief Set the FXOR field to a new value. */
01279 #define BW_CRC_CTRLHU_FXOR(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_CRC_CTRLHU_ADDR(x), BP_CRC_CTRLHU_FXOR), v))
01280 /*@}*/
01281 
01282 /*!
01283  * @name Register CRC_CTRLHU, field TOTR[5:4] (RW)
01284  *
01285  * Values:
01286  * - 00 - No Transposition.
01287  * - 01 - Bits in bytes are transposed, bytes are not transposed.
01288  * - 10 - Both bits in bytes and bytes are transposed.
01289  * - 11 - Only bytes are transposed; no bits in a byte are transposed.
01290  */
01291 /*@{*/
01292 #define BP_CRC_CTRLHU_TOTR   (4U)          /*!< Bit position for CRC_CTRLHU_TOTR. */
01293 #define BM_CRC_CTRLHU_TOTR   (0x30U)       /*!< Bit mask for CRC_CTRLHU_TOTR. */
01294 #define BS_CRC_CTRLHU_TOTR   (2U)          /*!< Bit field size in bits for CRC_CTRLHU_TOTR. */
01295 
01296 /*! @brief Read current value of the CRC_CTRLHU_TOTR field. */
01297 #define BR_CRC_CTRLHU_TOTR(x) (UNION_READ(hw_crc_ctrlhu_t, HW_CRC_CTRLHU_ADDR(x), U, B.TOTR))
01298 
01299 /*! @brief Format value for bitfield CRC_CTRLHU_TOTR. */
01300 #define BF_CRC_CTRLHU_TOTR(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_TOTR) & BM_CRC_CTRLHU_TOTR)
01301 
01302 /*! @brief Set the TOTR field to a new value. */
01303 #define BW_CRC_CTRLHU_TOTR(x, v) (HW_CRC_CTRLHU_WR(x, (HW_CRC_CTRLHU_RD(x) & ~BM_CRC_CTRLHU_TOTR) | BF_CRC_CTRLHU_TOTR(v)))
01304 /*@}*/
01305 
01306 /*!
01307  * @name Register CRC_CTRLHU, field TOT[7:6] (RW)
01308  *
01309  * Values:
01310  * - 00 - No Transposition.
01311  * - 01 - Bits in bytes are transposed, bytes are not transposed.
01312  * - 10 - Both bits in bytes and bytes are transposed.
01313  * - 11 - Only bytes are transposed; no bits in a byte are transposed.
01314  */
01315 /*@{*/
01316 #define BP_CRC_CTRLHU_TOT    (6U)          /*!< Bit position for CRC_CTRLHU_TOT. */
01317 #define BM_CRC_CTRLHU_TOT    (0xC0U)       /*!< Bit mask for CRC_CTRLHU_TOT. */
01318 #define BS_CRC_CTRLHU_TOT    (2U)          /*!< Bit field size in bits for CRC_CTRLHU_TOT. */
01319 
01320 /*! @brief Read current value of the CRC_CTRLHU_TOT field. */
01321 #define BR_CRC_CTRLHU_TOT(x) (UNION_READ(hw_crc_ctrlhu_t, HW_CRC_CTRLHU_ADDR(x), U, B.TOT))
01322 
01323 /*! @brief Format value for bitfield CRC_CTRLHU_TOT. */
01324 #define BF_CRC_CTRLHU_TOT(v) ((uint8_t)((uint8_t)(v) << BP_CRC_CTRLHU_TOT) & BM_CRC_CTRLHU_TOT)
01325 
01326 /*! @brief Set the TOT field to a new value. */
01327 #define BW_CRC_CTRLHU_TOT(x, v) (HW_CRC_CTRLHU_WR(x, (HW_CRC_CTRLHU_RD(x) & ~BM_CRC_CTRLHU_TOT) | BF_CRC_CTRLHU_TOT(v)))
01328 /*@}*/
01329 
01330 /*
01331 ** Start of section using anonymous unions
01332 */
01333 
01334 #if defined(__ARMCC_VERSION)
01335   #pragma push
01336   #pragma anon_unions
01337 #elif defined(__CWCC__)
01338   #pragma push
01339   #pragma cpp_extensions on
01340 #elif defined(__GNUC__)
01341   /* anonymous unions are enabled by default */
01342 #elif defined(__IAR_SYSTEMS_ICC__)
01343   #pragma language=extended
01344 #else
01345   #error Not supported compiler type
01346 #endif
01347 
01348 /*******************************************************************************
01349  * hw_crc_t - module struct
01350  ******************************************************************************/
01351 /*!
01352  * @brief All CRC module registers.
01353  */
01354 #pragma pack(1)
01355 typedef struct _hw_crc
01356 {
01357     union {
01358         struct {
01359             __IO hw_crc_datal_t DATAL ;     /*!< [0x0] CRC_DATAL register. */
01360             __IO hw_crc_datah_t DATAH ;     /*!< [0x2] CRC_DATAH register. */
01361         } ACCESS16BIT;
01362         struct {
01363             __IO hw_crc_datall_t DATALL ;   /*!< [0x0] CRC_DATALL register. */
01364             __IO hw_crc_datalu_t DATALU ;   /*!< [0x1] CRC_DATALU register. */
01365             __IO hw_crc_datahl_t DATAHL ;   /*!< [0x2] CRC_DATAHL register. */
01366             __IO hw_crc_datahu_t DATAHU ;   /*!< [0x3] CRC_DATAHU register. */
01367         } ACCESS8BIT;
01368         __IO hw_crc_data_t DATA ;           /*!< [0x0] CRC Data register */
01369     };
01370     union {
01371         __IO hw_crc_gpoly_t GPOLY ;         /*!< [0x4] CRC Polynomial register */
01372         struct {
01373             __IO hw_crc_gpolyl_t GPOLYL ;   /*!< [0x4] CRC_GPOLYL register. */
01374             __IO hw_crc_gpolyh_t GPOLYH ;   /*!< [0x6] CRC_GPOLYH register. */
01375         } GPOLY_ACCESS16BIT;
01376         struct {
01377             __IO hw_crc_gpolyll_t GPOLYLL ; /*!< [0x4] CRC_GPOLYLL register. */
01378             __IO hw_crc_gpolylu_t GPOLYLU ; /*!< [0x5] CRC_GPOLYLU register. */
01379             __IO hw_crc_gpolyhl_t GPOLYHL ; /*!< [0x6] CRC_GPOLYHL register. */
01380             __IO hw_crc_gpolyhu_t GPOLYHU ; /*!< [0x7] CRC_GPOLYHU register. */
01381         } GPOLY_ACCESS8BIT;
01382     };
01383     union {
01384         __IO hw_crc_ctrl_t CTRL ;           /*!< [0x8] CRC Control register */
01385         struct {
01386             uint8_t _reserved0[3];
01387             __IO hw_crc_ctrlhu_t CTRLHU ;   /*!< [0xB] CRC_CTRLHU register. */
01388         } CTRL_ACCESS8BIT;
01389     };
01390 } hw_crc_t;
01391 #pragma pack()
01392 
01393 /*! @brief Macro to access all CRC registers. */
01394 /*! @param x CRC module instance base address. */
01395 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
01396  *     use the '&' operator, like <code>&HW_CRC(CRC_BASE)</code>. */
01397 #define HW_CRC(x)      (*(hw_crc_t *)(x))
01398 
01399 /*
01400 ** End of section using anonymous unions
01401 */
01402 
01403 #if defined(__ARMCC_VERSION)
01404   #pragma pop
01405 #elif defined(__CWCC__)
01406   #pragma pop
01407 #elif defined(__GNUC__)
01408   /* leave anonymous unions enabled */
01409 #elif defined(__IAR_SYSTEMS_ICC__)
01410   #pragma language=default
01411 #else
01412   #error Not supported compiler type
01413 #endif
01414 
01415 #endif /* __HW_CRC_REGISTERS_H__ */
01416 /* EOF */