MK64F12_cmt.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_CMT_REGISTERS_H__
00088 #define __HW_CMT_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 CMT
00095  *
00096  * Carrier Modulator Transmitter
00097  *
00098  * Registers defined in this header file:
00099  * - HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1
00100  * - HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1
00101  * - HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2
00102  * - HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2
00103  * - HW_CMT_OC - CMT Output Control Register
00104  * - HW_CMT_MSC - CMT Modulator Status and Control Register
00105  * - HW_CMT_CMD1 - CMT Modulator Data Register Mark High
00106  * - HW_CMT_CMD2 - CMT Modulator Data Register Mark Low
00107  * - HW_CMT_CMD3 - CMT Modulator Data Register Space High
00108  * - HW_CMT_CMD4 - CMT Modulator Data Register Space Low
00109  * - HW_CMT_PPS - CMT Primary Prescaler Register
00110  * - HW_CMT_DMA - CMT Direct Memory Access Register
00111  *
00112  * - hw_cmt_t - Struct containing all module registers.
00113  */
00114 
00115 #define HW_CMT_INSTANCE_COUNT (1U) /*!< Number of instances of the CMT module. */
00116 
00117 /*******************************************************************************
00118  * HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1
00119  ******************************************************************************/
00120 
00121 /*!
00122  * @brief HW_CMT_CGH1 - CMT Carrier Generator High Data Register 1 (RW)
00123  *
00124  * Reset value: 0x00U
00125  *
00126  * This data register contains the primary high value for generating the carrier
00127  * output.
00128  */
00129 typedef union _hw_cmt_cgh1
00130 {
00131     uint8_t U;
00132     struct _hw_cmt_cgh1_bitfields
00133     {
00134         uint8_t PH : 8;                /*!< [7:0] Primary Carrier High Time Data Value */
00135     } B;
00136 } hw_cmt_cgh1_t;
00137 
00138 /*!
00139  * @name Constants and macros for entire CMT_CGH1 register
00140  */
00141 /*@{*/
00142 #define HW_CMT_CGH1_ADDR(x)      ((x) + 0x0U)
00143 
00144 #define HW_CMT_CGH1(x)           (*(__IO hw_cmt_cgh1_t *) HW_CMT_CGH1_ADDR(x))
00145 #define HW_CMT_CGH1_RD(x)        (ADDRESS_READ(hw_cmt_cgh1_t, HW_CMT_CGH1_ADDR(x)))
00146 #define HW_CMT_CGH1_WR(x, v)     (ADDRESS_WRITE(hw_cmt_cgh1_t, HW_CMT_CGH1_ADDR(x), v))
00147 #define HW_CMT_CGH1_SET(x, v)    (HW_CMT_CGH1_WR(x, HW_CMT_CGH1_RD(x) |  (v)))
00148 #define HW_CMT_CGH1_CLR(x, v)    (HW_CMT_CGH1_WR(x, HW_CMT_CGH1_RD(x) & ~(v)))
00149 #define HW_CMT_CGH1_TOG(x, v)    (HW_CMT_CGH1_WR(x, HW_CMT_CGH1_RD(x) ^  (v)))
00150 /*@}*/
00151 
00152 /*
00153  * Constants & macros for individual CMT_CGH1 bitfields
00154  */
00155 
00156 /*!
00157  * @name Register CMT_CGH1, field PH[7:0] (RW)
00158  *
00159  * Contains the number of input clocks required to generate the carrier high
00160  * time period. When operating in Time mode, this register is always selected. When
00161  * operating in FSK mode, this register and the secondary register pair are
00162  * alternately selected under the control of the modulator. The primary carrier high
00163  * time value is undefined out of reset. This register must be written to nonzero
00164  * values before the carrier generator is enabled to avoid spurious results.
00165  */
00166 /*@{*/
00167 #define BP_CMT_CGH1_PH       (0U)          /*!< Bit position for CMT_CGH1_PH. */
00168 #define BM_CMT_CGH1_PH       (0xFFU)       /*!< Bit mask for CMT_CGH1_PH. */
00169 #define BS_CMT_CGH1_PH       (8U)          /*!< Bit field size in bits for CMT_CGH1_PH. */
00170 
00171 /*! @brief Read current value of the CMT_CGH1_PH field. */
00172 #define BR_CMT_CGH1_PH(x)    (HW_CMT_CGH1(x).U)
00173 
00174 /*! @brief Format value for bitfield CMT_CGH1_PH. */
00175 #define BF_CMT_CGH1_PH(v)    ((uint8_t)((uint8_t)(v) << BP_CMT_CGH1_PH) & BM_CMT_CGH1_PH)
00176 
00177 /*! @brief Set the PH field to a new value. */
00178 #define BW_CMT_CGH1_PH(x, v) (HW_CMT_CGH1_WR(x, v))
00179 /*@}*/
00180 
00181 /*******************************************************************************
00182  * HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1
00183  ******************************************************************************/
00184 
00185 /*!
00186  * @brief HW_CMT_CGL1 - CMT Carrier Generator Low Data Register 1 (RW)
00187  *
00188  * Reset value: 0x00U
00189  *
00190  * This data register contains the primary low value for generating the carrier
00191  * output.
00192  */
00193 typedef union _hw_cmt_cgl1
00194 {
00195     uint8_t U;
00196     struct _hw_cmt_cgl1_bitfields
00197     {
00198         uint8_t PL : 8;                /*!< [7:0] Primary Carrier Low Time Data Value */
00199     } B;
00200 } hw_cmt_cgl1_t;
00201 
00202 /*!
00203  * @name Constants and macros for entire CMT_CGL1 register
00204  */
00205 /*@{*/
00206 #define HW_CMT_CGL1_ADDR(x)      ((x) + 0x1U)
00207 
00208 #define HW_CMT_CGL1(x)           (*(__IO hw_cmt_cgl1_t *) HW_CMT_CGL1_ADDR(x))
00209 #define HW_CMT_CGL1_RD(x)        (ADDRESS_READ(hw_cmt_cgl1_t, HW_CMT_CGL1_ADDR(x)))
00210 #define HW_CMT_CGL1_WR(x, v)     (ADDRESS_WRITE(hw_cmt_cgl1_t, HW_CMT_CGL1_ADDR(x), v))
00211 #define HW_CMT_CGL1_SET(x, v)    (HW_CMT_CGL1_WR(x, HW_CMT_CGL1_RD(x) |  (v)))
00212 #define HW_CMT_CGL1_CLR(x, v)    (HW_CMT_CGL1_WR(x, HW_CMT_CGL1_RD(x) & ~(v)))
00213 #define HW_CMT_CGL1_TOG(x, v)    (HW_CMT_CGL1_WR(x, HW_CMT_CGL1_RD(x) ^  (v)))
00214 /*@}*/
00215 
00216 /*
00217  * Constants & macros for individual CMT_CGL1 bitfields
00218  */
00219 
00220 /*!
00221  * @name Register CMT_CGL1, field PL[7:0] (RW)
00222  *
00223  * Contains the number of input clocks required to generate the carrier low time
00224  * period. When operating in Time mode, this register is always selected. When
00225  * operating in FSK mode, this register and the secondary register pair are
00226  * alternately selected under the control of the modulator. The primary carrier low
00227  * time value is undefined out of reset. This register must be written to nonzero
00228  * values before the carrier generator is enabled to avoid spurious results.
00229  */
00230 /*@{*/
00231 #define BP_CMT_CGL1_PL       (0U)          /*!< Bit position for CMT_CGL1_PL. */
00232 #define BM_CMT_CGL1_PL       (0xFFU)       /*!< Bit mask for CMT_CGL1_PL. */
00233 #define BS_CMT_CGL1_PL       (8U)          /*!< Bit field size in bits for CMT_CGL1_PL. */
00234 
00235 /*! @brief Read current value of the CMT_CGL1_PL field. */
00236 #define BR_CMT_CGL1_PL(x)    (HW_CMT_CGL1(x).U)
00237 
00238 /*! @brief Format value for bitfield CMT_CGL1_PL. */
00239 #define BF_CMT_CGL1_PL(v)    ((uint8_t)((uint8_t)(v) << BP_CMT_CGL1_PL) & BM_CMT_CGL1_PL)
00240 
00241 /*! @brief Set the PL field to a new value. */
00242 #define BW_CMT_CGL1_PL(x, v) (HW_CMT_CGL1_WR(x, v))
00243 /*@}*/
00244 
00245 /*******************************************************************************
00246  * HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2
00247  ******************************************************************************/
00248 
00249 /*!
00250  * @brief HW_CMT_CGH2 - CMT Carrier Generator High Data Register 2 (RW)
00251  *
00252  * Reset value: 0x00U
00253  *
00254  * This data register contains the secondary high value for generating the
00255  * carrier output.
00256  */
00257 typedef union _hw_cmt_cgh2
00258 {
00259     uint8_t U;
00260     struct _hw_cmt_cgh2_bitfields
00261     {
00262         uint8_t SH : 8;                /*!< [7:0] Secondary Carrier High Time Data Value */
00263     } B;
00264 } hw_cmt_cgh2_t;
00265 
00266 /*!
00267  * @name Constants and macros for entire CMT_CGH2 register
00268  */
00269 /*@{*/
00270 #define HW_CMT_CGH2_ADDR(x)      ((x) + 0x2U)
00271 
00272 #define HW_CMT_CGH2(x)           (*(__IO hw_cmt_cgh2_t *) HW_CMT_CGH2_ADDR(x))
00273 #define HW_CMT_CGH2_RD(x)        (ADDRESS_READ(hw_cmt_cgh2_t, HW_CMT_CGH2_ADDR(x)))
00274 #define HW_CMT_CGH2_WR(x, v)     (ADDRESS_WRITE(hw_cmt_cgh2_t, HW_CMT_CGH2_ADDR(x), v))
00275 #define HW_CMT_CGH2_SET(x, v)    (HW_CMT_CGH2_WR(x, HW_CMT_CGH2_RD(x) |  (v)))
00276 #define HW_CMT_CGH2_CLR(x, v)    (HW_CMT_CGH2_WR(x, HW_CMT_CGH2_RD(x) & ~(v)))
00277 #define HW_CMT_CGH2_TOG(x, v)    (HW_CMT_CGH2_WR(x, HW_CMT_CGH2_RD(x) ^  (v)))
00278 /*@}*/
00279 
00280 /*
00281  * Constants & macros for individual CMT_CGH2 bitfields
00282  */
00283 
00284 /*!
00285  * @name Register CMT_CGH2, field SH[7:0] (RW)
00286  *
00287  * Contains the number of input clocks required to generate the carrier high
00288  * time period. When operating in Time mode, this register is never selected. When
00289  * operating in FSK mode, this register and the primary register pair are
00290  * alternately selected under control of the modulator. The secondary carrier high time
00291  * value is undefined out of reset. This register must be written to nonzero
00292  * values before the carrier generator is enabled when operating in FSK mode.
00293  */
00294 /*@{*/
00295 #define BP_CMT_CGH2_SH       (0U)          /*!< Bit position for CMT_CGH2_SH. */
00296 #define BM_CMT_CGH2_SH       (0xFFU)       /*!< Bit mask for CMT_CGH2_SH. */
00297 #define BS_CMT_CGH2_SH       (8U)          /*!< Bit field size in bits for CMT_CGH2_SH. */
00298 
00299 /*! @brief Read current value of the CMT_CGH2_SH field. */
00300 #define BR_CMT_CGH2_SH(x)    (HW_CMT_CGH2(x).U)
00301 
00302 /*! @brief Format value for bitfield CMT_CGH2_SH. */
00303 #define BF_CMT_CGH2_SH(v)    ((uint8_t)((uint8_t)(v) << BP_CMT_CGH2_SH) & BM_CMT_CGH2_SH)
00304 
00305 /*! @brief Set the SH field to a new value. */
00306 #define BW_CMT_CGH2_SH(x, v) (HW_CMT_CGH2_WR(x, v))
00307 /*@}*/
00308 
00309 /*******************************************************************************
00310  * HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2
00311  ******************************************************************************/
00312 
00313 /*!
00314  * @brief HW_CMT_CGL2 - CMT Carrier Generator Low Data Register 2 (RW)
00315  *
00316  * Reset value: 0x00U
00317  *
00318  * This data register contains the secondary low value for generating the
00319  * carrier output.
00320  */
00321 typedef union _hw_cmt_cgl2
00322 {
00323     uint8_t U;
00324     struct _hw_cmt_cgl2_bitfields
00325     {
00326         uint8_t SL : 8;                /*!< [7:0] Secondary Carrier Low Time Data Value */
00327     } B;
00328 } hw_cmt_cgl2_t;
00329 
00330 /*!
00331  * @name Constants and macros for entire CMT_CGL2 register
00332  */
00333 /*@{*/
00334 #define HW_CMT_CGL2_ADDR(x)      ((x) + 0x3U)
00335 
00336 #define HW_CMT_CGL2(x)           (*(__IO hw_cmt_cgl2_t *) HW_CMT_CGL2_ADDR(x))
00337 #define HW_CMT_CGL2_RD(x)        (ADDRESS_READ(hw_cmt_cgl2_t, HW_CMT_CGL2_ADDR(x)))
00338 #define HW_CMT_CGL2_WR(x, v)     (ADDRESS_WRITE(hw_cmt_cgl2_t, HW_CMT_CGL2_ADDR(x), v))
00339 #define HW_CMT_CGL2_SET(x, v)    (HW_CMT_CGL2_WR(x, HW_CMT_CGL2_RD(x) |  (v)))
00340 #define HW_CMT_CGL2_CLR(x, v)    (HW_CMT_CGL2_WR(x, HW_CMT_CGL2_RD(x) & ~(v)))
00341 #define HW_CMT_CGL2_TOG(x, v)    (HW_CMT_CGL2_WR(x, HW_CMT_CGL2_RD(x) ^  (v)))
00342 /*@}*/
00343 
00344 /*
00345  * Constants & macros for individual CMT_CGL2 bitfields
00346  */
00347 
00348 /*!
00349  * @name Register CMT_CGL2, field SL[7:0] (RW)
00350  *
00351  * Contains the number of input clocks required to generate the carrier low time
00352  * period. When operating in Time mode, this register is never selected. When
00353  * operating in FSK mode, this register and the primary register pair are
00354  * alternately selected under the control of the modulator. The secondary carrier low time
00355  * value is undefined out of reset. This register must be written to nonzero
00356  * values before the carrier generator is enabled when operating in FSK mode.
00357  */
00358 /*@{*/
00359 #define BP_CMT_CGL2_SL       (0U)          /*!< Bit position for CMT_CGL2_SL. */
00360 #define BM_CMT_CGL2_SL       (0xFFU)       /*!< Bit mask for CMT_CGL2_SL. */
00361 #define BS_CMT_CGL2_SL       (8U)          /*!< Bit field size in bits for CMT_CGL2_SL. */
00362 
00363 /*! @brief Read current value of the CMT_CGL2_SL field. */
00364 #define BR_CMT_CGL2_SL(x)    (HW_CMT_CGL2(x).U)
00365 
00366 /*! @brief Format value for bitfield CMT_CGL2_SL. */
00367 #define BF_CMT_CGL2_SL(v)    ((uint8_t)((uint8_t)(v) << BP_CMT_CGL2_SL) & BM_CMT_CGL2_SL)
00368 
00369 /*! @brief Set the SL field to a new value. */
00370 #define BW_CMT_CGL2_SL(x, v) (HW_CMT_CGL2_WR(x, v))
00371 /*@}*/
00372 
00373 /*******************************************************************************
00374  * HW_CMT_OC - CMT Output Control Register
00375  ******************************************************************************/
00376 
00377 /*!
00378  * @brief HW_CMT_OC - CMT Output Control Register (RW)
00379  *
00380  * Reset value: 0x00U
00381  *
00382  * This register is used to control the IRO signal of the CMT module.
00383  */
00384 typedef union _hw_cmt_oc
00385 {
00386     uint8_t U;
00387     struct _hw_cmt_oc_bitfields
00388     {
00389         uint8_t RESERVED0 : 5;         /*!< [4:0]  */
00390         uint8_t IROPEN : 1;            /*!< [5] IRO Pin Enable */
00391         uint8_t CMTPOL : 1;            /*!< [6] CMT Output Polarity */
00392         uint8_t IROL : 1;              /*!< [7] IRO Latch Control */
00393     } B;
00394 } hw_cmt_oc_t;
00395 
00396 /*!
00397  * @name Constants and macros for entire CMT_OC register
00398  */
00399 /*@{*/
00400 #define HW_CMT_OC_ADDR(x)        ((x) + 0x4U)
00401 
00402 #define HW_CMT_OC(x)             (*(__IO hw_cmt_oc_t *) HW_CMT_OC_ADDR(x))
00403 #define HW_CMT_OC_RD(x)          (ADDRESS_READ(hw_cmt_oc_t, HW_CMT_OC_ADDR(x)))
00404 #define HW_CMT_OC_WR(x, v)       (ADDRESS_WRITE(hw_cmt_oc_t, HW_CMT_OC_ADDR(x), v))
00405 #define HW_CMT_OC_SET(x, v)      (HW_CMT_OC_WR(x, HW_CMT_OC_RD(x) |  (v)))
00406 #define HW_CMT_OC_CLR(x, v)      (HW_CMT_OC_WR(x, HW_CMT_OC_RD(x) & ~(v)))
00407 #define HW_CMT_OC_TOG(x, v)      (HW_CMT_OC_WR(x, HW_CMT_OC_RD(x) ^  (v)))
00408 /*@}*/
00409 
00410 /*
00411  * Constants & macros for individual CMT_OC bitfields
00412  */
00413 
00414 /*!
00415  * @name Register CMT_OC, field IROPEN[5] (RW)
00416  *
00417  * Enables and disables the IRO signal. When the IRO signal is enabled, it is an
00418  * output that drives out either the CMT transmitter output or the state of IROL
00419  * depending on whether MSC[MCGEN] is set or not. Also, the state of output is
00420  * either inverted or non-inverted, depending on the state of CMTPOL. When the IRO
00421  * signal is disabled, it is in a high-impedance state and is unable to draw any
00422  * current. This signal is disabled during reset.
00423  *
00424  * Values:
00425  * - 0 - The IRO signal is disabled.
00426  * - 1 - The IRO signal is enabled as output.
00427  */
00428 /*@{*/
00429 #define BP_CMT_OC_IROPEN     (5U)          /*!< Bit position for CMT_OC_IROPEN. */
00430 #define BM_CMT_OC_IROPEN     (0x20U)       /*!< Bit mask for CMT_OC_IROPEN. */
00431 #define BS_CMT_OC_IROPEN     (1U)          /*!< Bit field size in bits for CMT_OC_IROPEN. */
00432 
00433 /*! @brief Read current value of the CMT_OC_IROPEN field. */
00434 #define BR_CMT_OC_IROPEN(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_IROPEN)))
00435 
00436 /*! @brief Format value for bitfield CMT_OC_IROPEN. */
00437 #define BF_CMT_OC_IROPEN(v)  ((uint8_t)((uint8_t)(v) << BP_CMT_OC_IROPEN) & BM_CMT_OC_IROPEN)
00438 
00439 /*! @brief Set the IROPEN field to a new value. */
00440 #define BW_CMT_OC_IROPEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_IROPEN), v))
00441 /*@}*/
00442 
00443 /*!
00444  * @name Register CMT_OC, field CMTPOL[6] (RW)
00445  *
00446  * Controls the polarity of the IRO signal.
00447  *
00448  * Values:
00449  * - 0 - The IRO signal is active-low.
00450  * - 1 - The IRO signal is active-high.
00451  */
00452 /*@{*/
00453 #define BP_CMT_OC_CMTPOL     (6U)          /*!< Bit position for CMT_OC_CMTPOL. */
00454 #define BM_CMT_OC_CMTPOL     (0x40U)       /*!< Bit mask for CMT_OC_CMTPOL. */
00455 #define BS_CMT_OC_CMTPOL     (1U)          /*!< Bit field size in bits for CMT_OC_CMTPOL. */
00456 
00457 /*! @brief Read current value of the CMT_OC_CMTPOL field. */
00458 #define BR_CMT_OC_CMTPOL(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_CMTPOL)))
00459 
00460 /*! @brief Format value for bitfield CMT_OC_CMTPOL. */
00461 #define BF_CMT_OC_CMTPOL(v)  ((uint8_t)((uint8_t)(v) << BP_CMT_OC_CMTPOL) & BM_CMT_OC_CMTPOL)
00462 
00463 /*! @brief Set the CMTPOL field to a new value. */
00464 #define BW_CMT_OC_CMTPOL(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_CMTPOL), v))
00465 /*@}*/
00466 
00467 /*!
00468  * @name Register CMT_OC, field IROL[7] (RW)
00469  *
00470  * Reads the state of the IRO latch. Writing to IROL changes the state of the
00471  * IRO signal when MSC[MCGEN] is cleared and IROPEN is set.
00472  */
00473 /*@{*/
00474 #define BP_CMT_OC_IROL       (7U)          /*!< Bit position for CMT_OC_IROL. */
00475 #define BM_CMT_OC_IROL       (0x80U)       /*!< Bit mask for CMT_OC_IROL. */
00476 #define BS_CMT_OC_IROL       (1U)          /*!< Bit field size in bits for CMT_OC_IROL. */
00477 
00478 /*! @brief Read current value of the CMT_OC_IROL field. */
00479 #define BR_CMT_OC_IROL(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_IROL)))
00480 
00481 /*! @brief Format value for bitfield CMT_OC_IROL. */
00482 #define BF_CMT_OC_IROL(v)    ((uint8_t)((uint8_t)(v) << BP_CMT_OC_IROL) & BM_CMT_OC_IROL)
00483 
00484 /*! @brief Set the IROL field to a new value. */
00485 #define BW_CMT_OC_IROL(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_CMT_OC_ADDR(x), BP_CMT_OC_IROL), v))
00486 /*@}*/
00487 
00488 /*******************************************************************************
00489  * HW_CMT_MSC - CMT Modulator Status and Control Register
00490  ******************************************************************************/
00491 
00492 /*!
00493  * @brief HW_CMT_MSC - CMT Modulator Status and Control Register (RW)
00494  *
00495  * Reset value: 0x00U
00496  *
00497  * This register contains the modulator and carrier generator enable (MCGEN),
00498  * end of cycle interrupt enable (EOCIE), FSK mode select (FSK), baseband enable
00499  * (BASE), extended space (EXSPC), prescaler (CMTDIV) bits, and the end of cycle
00500  * (EOCF) status bit.
00501  */
00502 typedef union _hw_cmt_msc
00503 {
00504     uint8_t U;
00505     struct _hw_cmt_msc_bitfields
00506     {
00507         uint8_t MCGEN : 1;             /*!< [0] Modulator and Carrier Generator Enable */
00508         uint8_t EOCIE : 1;             /*!< [1] End of Cycle Interrupt Enable */
00509         uint8_t FSK : 1;               /*!< [2] FSK Mode Select */
00510         uint8_t BASE : 1;              /*!< [3] Baseband Enable */
00511         uint8_t EXSPC : 1;             /*!< [4] Extended Space Enable */
00512         uint8_t CMTDIV : 2;            /*!< [6:5] CMT Clock Divide Prescaler */
00513         uint8_t EOCF : 1;              /*!< [7] End Of Cycle Status Flag */
00514     } B;
00515 } hw_cmt_msc_t;
00516 
00517 /*!
00518  * @name Constants and macros for entire CMT_MSC register
00519  */
00520 /*@{*/
00521 #define HW_CMT_MSC_ADDR(x)       ((x) + 0x5U)
00522 
00523 #define HW_CMT_MSC(x)            (*(__IO hw_cmt_msc_t *) HW_CMT_MSC_ADDR(x))
00524 #define HW_CMT_MSC_RD(x)         (ADDRESS_READ(hw_cmt_msc_t, HW_CMT_MSC_ADDR(x)))
00525 #define HW_CMT_MSC_WR(x, v)      (ADDRESS_WRITE(hw_cmt_msc_t, HW_CMT_MSC_ADDR(x), v))
00526 #define HW_CMT_MSC_SET(x, v)     (HW_CMT_MSC_WR(x, HW_CMT_MSC_RD(x) |  (v)))
00527 #define HW_CMT_MSC_CLR(x, v)     (HW_CMT_MSC_WR(x, HW_CMT_MSC_RD(x) & ~(v)))
00528 #define HW_CMT_MSC_TOG(x, v)     (HW_CMT_MSC_WR(x, HW_CMT_MSC_RD(x) ^  (v)))
00529 /*@}*/
00530 
00531 /*
00532  * Constants & macros for individual CMT_MSC bitfields
00533  */
00534 
00535 /*!
00536  * @name Register CMT_MSC, field MCGEN[0] (RW)
00537  *
00538  * Setting MCGEN will initialize the carrier generator and modulator and will
00539  * enable all clocks. When enabled, the carrier generator and modulator will
00540  * function continuously. When MCGEN is cleared, the current modulator cycle will be
00541  * allowed to expire before all carrier and modulator clocks are disabled to save
00542  * power and the modulator output is forced low. To prevent spurious operation,
00543  * the user should initialize all data and control registers before enabling the
00544  * system.
00545  *
00546  * Values:
00547  * - 0 - Modulator and carrier generator disabled
00548  * - 1 - Modulator and carrier generator enabled
00549  */
00550 /*@{*/
00551 #define BP_CMT_MSC_MCGEN     (0U)          /*!< Bit position for CMT_MSC_MCGEN. */
00552 #define BM_CMT_MSC_MCGEN     (0x01U)       /*!< Bit mask for CMT_MSC_MCGEN. */
00553 #define BS_CMT_MSC_MCGEN     (1U)          /*!< Bit field size in bits for CMT_MSC_MCGEN. */
00554 
00555 /*! @brief Read current value of the CMT_MSC_MCGEN field. */
00556 #define BR_CMT_MSC_MCGEN(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_MCGEN)))
00557 
00558 /*! @brief Format value for bitfield CMT_MSC_MCGEN. */
00559 #define BF_CMT_MSC_MCGEN(v)  ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_MCGEN) & BM_CMT_MSC_MCGEN)
00560 
00561 /*! @brief Set the MCGEN field to a new value. */
00562 #define BW_CMT_MSC_MCGEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_MCGEN), v))
00563 /*@}*/
00564 
00565 /*!
00566  * @name Register CMT_MSC, field EOCIE[1] (RW)
00567  *
00568  * Requests to enable a CPU interrupt when EOCF is set if EOCIE is high.
00569  *
00570  * Values:
00571  * - 0 - CPU interrupt is disabled.
00572  * - 1 - CPU interrupt is enabled.
00573  */
00574 /*@{*/
00575 #define BP_CMT_MSC_EOCIE     (1U)          /*!< Bit position for CMT_MSC_EOCIE. */
00576 #define BM_CMT_MSC_EOCIE     (0x02U)       /*!< Bit mask for CMT_MSC_EOCIE. */
00577 #define BS_CMT_MSC_EOCIE     (1U)          /*!< Bit field size in bits for CMT_MSC_EOCIE. */
00578 
00579 /*! @brief Read current value of the CMT_MSC_EOCIE field. */
00580 #define BR_CMT_MSC_EOCIE(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_EOCIE)))
00581 
00582 /*! @brief Format value for bitfield CMT_MSC_EOCIE. */
00583 #define BF_CMT_MSC_EOCIE(v)  ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_EOCIE) & BM_CMT_MSC_EOCIE)
00584 
00585 /*! @brief Set the EOCIE field to a new value. */
00586 #define BW_CMT_MSC_EOCIE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_EOCIE), v))
00587 /*@}*/
00588 
00589 /*!
00590  * @name Register CMT_MSC, field FSK[2] (RW)
00591  *
00592  * Enables FSK operation.
00593  *
00594  * Values:
00595  * - 0 - The CMT operates in Time or Baseband mode.
00596  * - 1 - The CMT operates in FSK mode.
00597  */
00598 /*@{*/
00599 #define BP_CMT_MSC_FSK       (2U)          /*!< Bit position for CMT_MSC_FSK. */
00600 #define BM_CMT_MSC_FSK       (0x04U)       /*!< Bit mask for CMT_MSC_FSK. */
00601 #define BS_CMT_MSC_FSK       (1U)          /*!< Bit field size in bits for CMT_MSC_FSK. */
00602 
00603 /*! @brief Read current value of the CMT_MSC_FSK field. */
00604 #define BR_CMT_MSC_FSK(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_FSK)))
00605 
00606 /*! @brief Format value for bitfield CMT_MSC_FSK. */
00607 #define BF_CMT_MSC_FSK(v)    ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_FSK) & BM_CMT_MSC_FSK)
00608 
00609 /*! @brief Set the FSK field to a new value. */
00610 #define BW_CMT_MSC_FSK(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_FSK), v))
00611 /*@}*/
00612 
00613 /*!
00614  * @name Register CMT_MSC, field BASE[3] (RW)
00615  *
00616  * When set, BASE disables the carrier generator and forces the carrier output
00617  * high for generation of baseband protocols. When BASE is cleared, the carrier
00618  * generator is enabled and the carrier output toggles at the frequency determined
00619  * by values stored in the carrier data registers. This field is cleared by
00620  * reset. This field is not double-buffered and must not be written to during a
00621  * transmission.
00622  *
00623  * Values:
00624  * - 0 - Baseband mode is disabled.
00625  * - 1 - Baseband mode is enabled.
00626  */
00627 /*@{*/
00628 #define BP_CMT_MSC_BASE      (3U)          /*!< Bit position for CMT_MSC_BASE. */
00629 #define BM_CMT_MSC_BASE      (0x08U)       /*!< Bit mask for CMT_MSC_BASE. */
00630 #define BS_CMT_MSC_BASE      (1U)          /*!< Bit field size in bits for CMT_MSC_BASE. */
00631 
00632 /*! @brief Read current value of the CMT_MSC_BASE field. */
00633 #define BR_CMT_MSC_BASE(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_BASE)))
00634 
00635 /*! @brief Format value for bitfield CMT_MSC_BASE. */
00636 #define BF_CMT_MSC_BASE(v)   ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_BASE) & BM_CMT_MSC_BASE)
00637 
00638 /*! @brief Set the BASE field to a new value. */
00639 #define BW_CMT_MSC_BASE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_BASE), v))
00640 /*@}*/
00641 
00642 /*!
00643  * @name Register CMT_MSC, field EXSPC[4] (RW)
00644  *
00645  * Enables the extended space operation.
00646  *
00647  * Values:
00648  * - 0 - Extended space is disabled.
00649  * - 1 - Extended space is enabled.
00650  */
00651 /*@{*/
00652 #define BP_CMT_MSC_EXSPC     (4U)          /*!< Bit position for CMT_MSC_EXSPC. */
00653 #define BM_CMT_MSC_EXSPC     (0x10U)       /*!< Bit mask for CMT_MSC_EXSPC. */
00654 #define BS_CMT_MSC_EXSPC     (1U)          /*!< Bit field size in bits for CMT_MSC_EXSPC. */
00655 
00656 /*! @brief Read current value of the CMT_MSC_EXSPC field. */
00657 #define BR_CMT_MSC_EXSPC(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_EXSPC)))
00658 
00659 /*! @brief Format value for bitfield CMT_MSC_EXSPC. */
00660 #define BF_CMT_MSC_EXSPC(v)  ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_EXSPC) & BM_CMT_MSC_EXSPC)
00661 
00662 /*! @brief Set the EXSPC field to a new value. */
00663 #define BW_CMT_MSC_EXSPC(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_EXSPC), v))
00664 /*@}*/
00665 
00666 /*!
00667  * @name Register CMT_MSC, field CMTDIV[6:5] (RW)
00668  *
00669  * Causes the CMT to be clocked at the IF signal frequency, or the IF frequency
00670  * divided by 2 ,4, or 8 . This field must not be changed during a transmission
00671  * because it is not double-buffered.
00672  *
00673  * Values:
00674  * - 00 - IF * 1
00675  * - 01 - IF * 2
00676  * - 10 - IF * 4
00677  * - 11 - IF * 8
00678  */
00679 /*@{*/
00680 #define BP_CMT_MSC_CMTDIV    (5U)          /*!< Bit position for CMT_MSC_CMTDIV. */
00681 #define BM_CMT_MSC_CMTDIV    (0x60U)       /*!< Bit mask for CMT_MSC_CMTDIV. */
00682 #define BS_CMT_MSC_CMTDIV    (2U)          /*!< Bit field size in bits for CMT_MSC_CMTDIV. */
00683 
00684 /*! @brief Read current value of the CMT_MSC_CMTDIV field. */
00685 #define BR_CMT_MSC_CMTDIV(x) (UNION_READ(hw_cmt_msc_t, HW_CMT_MSC_ADDR(x), U, B.CMTDIV))
00686 
00687 /*! @brief Format value for bitfield CMT_MSC_CMTDIV. */
00688 #define BF_CMT_MSC_CMTDIV(v) ((uint8_t)((uint8_t)(v) << BP_CMT_MSC_CMTDIV) & BM_CMT_MSC_CMTDIV)
00689 
00690 /*! @brief Set the CMTDIV field to a new value. */
00691 #define BW_CMT_MSC_CMTDIV(x, v) (HW_CMT_MSC_WR(x, (HW_CMT_MSC_RD(x) & ~BM_CMT_MSC_CMTDIV) | BF_CMT_MSC_CMTDIV(v)))
00692 /*@}*/
00693 
00694 /*!
00695  * @name Register CMT_MSC, field EOCF[7] (RO)
00696  *
00697  * Sets when: The modulator is not currently active and MCGEN is set to begin
00698  * the initial CMT transmission. At the end of each modulation cycle while MCGEN is
00699  * set. This is recognized when a match occurs between the contents of the space
00700  * period register and the down counter. At this time, the counter is
00701  * initialized with, possibly new contents of the mark period buffer, CMD1 and CMD2, and
00702  * the space period register is loaded with, possibly new contents of the space
00703  * period buffer, CMD3 and CMD4. This flag is cleared by reading MSC followed by an
00704  * access of CMD2 or CMD4, or by the DMA transfer.
00705  *
00706  * Values:
00707  * - 0 - End of modulation cycle has not occured since the flag last cleared.
00708  * - 1 - End of modulator cycle has occurred.
00709  */
00710 /*@{*/
00711 #define BP_CMT_MSC_EOCF      (7U)          /*!< Bit position for CMT_MSC_EOCF. */
00712 #define BM_CMT_MSC_EOCF      (0x80U)       /*!< Bit mask for CMT_MSC_EOCF. */
00713 #define BS_CMT_MSC_EOCF      (1U)          /*!< Bit field size in bits for CMT_MSC_EOCF. */
00714 
00715 /*! @brief Read current value of the CMT_MSC_EOCF field. */
00716 #define BR_CMT_MSC_EOCF(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_CMT_MSC_ADDR(x), BP_CMT_MSC_EOCF)))
00717 /*@}*/
00718 
00719 /*******************************************************************************
00720  * HW_CMT_CMD1 - CMT Modulator Data Register Mark High
00721  ******************************************************************************/
00722 
00723 /*!
00724  * @brief HW_CMT_CMD1 - CMT Modulator Data Register Mark High (RW)
00725  *
00726  * Reset value: 0x00U
00727  *
00728  * The contents of this register are transferred to the modulator down counter
00729  * upon the completion of a modulation period.
00730  */
00731 typedef union _hw_cmt_cmd1
00732 {
00733     uint8_t U;
00734     struct _hw_cmt_cmd1_bitfields
00735     {
00736         uint8_t MB : 8;                /*!< [7:0]  */
00737     } B;
00738 } hw_cmt_cmd1_t;
00739 
00740 /*!
00741  * @name Constants and macros for entire CMT_CMD1 register
00742  */
00743 /*@{*/
00744 #define HW_CMT_CMD1_ADDR(x)      ((x) + 0x6U)
00745 
00746 #define HW_CMT_CMD1(x)           (*(__IO hw_cmt_cmd1_t *) HW_CMT_CMD1_ADDR(x))
00747 #define HW_CMT_CMD1_RD(x)        (ADDRESS_READ(hw_cmt_cmd1_t, HW_CMT_CMD1_ADDR(x)))
00748 #define HW_CMT_CMD1_WR(x, v)     (ADDRESS_WRITE(hw_cmt_cmd1_t, HW_CMT_CMD1_ADDR(x), v))
00749 #define HW_CMT_CMD1_SET(x, v)    (HW_CMT_CMD1_WR(x, HW_CMT_CMD1_RD(x) |  (v)))
00750 #define HW_CMT_CMD1_CLR(x, v)    (HW_CMT_CMD1_WR(x, HW_CMT_CMD1_RD(x) & ~(v)))
00751 #define HW_CMT_CMD1_TOG(x, v)    (HW_CMT_CMD1_WR(x, HW_CMT_CMD1_RD(x) ^  (v)))
00752 /*@}*/
00753 
00754 /*
00755  * Constants & macros for individual CMT_CMD1 bitfields
00756  */
00757 
00758 /*!
00759  * @name Register CMT_CMD1, field MB[7:0] (RW)
00760  *
00761  * Controls the upper mark periods of the modulator for all modes.
00762  */
00763 /*@{*/
00764 #define BP_CMT_CMD1_MB       (0U)          /*!< Bit position for CMT_CMD1_MB. */
00765 #define BM_CMT_CMD1_MB       (0xFFU)       /*!< Bit mask for CMT_CMD1_MB. */
00766 #define BS_CMT_CMD1_MB       (8U)          /*!< Bit field size in bits for CMT_CMD1_MB. */
00767 
00768 /*! @brief Read current value of the CMT_CMD1_MB field. */
00769 #define BR_CMT_CMD1_MB(x)    (HW_CMT_CMD1(x).U)
00770 
00771 /*! @brief Format value for bitfield CMT_CMD1_MB. */
00772 #define BF_CMT_CMD1_MB(v)    ((uint8_t)((uint8_t)(v) << BP_CMT_CMD1_MB) & BM_CMT_CMD1_MB)
00773 
00774 /*! @brief Set the MB field to a new value. */
00775 #define BW_CMT_CMD1_MB(x, v) (HW_CMT_CMD1_WR(x, v))
00776 /*@}*/
00777 
00778 /*******************************************************************************
00779  * HW_CMT_CMD2 - CMT Modulator Data Register Mark Low
00780  ******************************************************************************/
00781 
00782 /*!
00783  * @brief HW_CMT_CMD2 - CMT Modulator Data Register Mark Low (RW)
00784  *
00785  * Reset value: 0x00U
00786  *
00787  * The contents of this register are transferred to the modulator down counter
00788  * upon the completion of a modulation period.
00789  */
00790 typedef union _hw_cmt_cmd2
00791 {
00792     uint8_t U;
00793     struct _hw_cmt_cmd2_bitfields
00794     {
00795         uint8_t MB : 8;                /*!< [7:0]  */
00796     } B;
00797 } hw_cmt_cmd2_t;
00798 
00799 /*!
00800  * @name Constants and macros for entire CMT_CMD2 register
00801  */
00802 /*@{*/
00803 #define HW_CMT_CMD2_ADDR(x)      ((x) + 0x7U)
00804 
00805 #define HW_CMT_CMD2(x)           (*(__IO hw_cmt_cmd2_t *) HW_CMT_CMD2_ADDR(x))
00806 #define HW_CMT_CMD2_RD(x)        (ADDRESS_READ(hw_cmt_cmd2_t, HW_CMT_CMD2_ADDR(x)))
00807 #define HW_CMT_CMD2_WR(x, v)     (ADDRESS_WRITE(hw_cmt_cmd2_t, HW_CMT_CMD2_ADDR(x), v))
00808 #define HW_CMT_CMD2_SET(x, v)    (HW_CMT_CMD2_WR(x, HW_CMT_CMD2_RD(x) |  (v)))
00809 #define HW_CMT_CMD2_CLR(x, v)    (HW_CMT_CMD2_WR(x, HW_CMT_CMD2_RD(x) & ~(v)))
00810 #define HW_CMT_CMD2_TOG(x, v)    (HW_CMT_CMD2_WR(x, HW_CMT_CMD2_RD(x) ^  (v)))
00811 /*@}*/
00812 
00813 /*
00814  * Constants & macros for individual CMT_CMD2 bitfields
00815  */
00816 
00817 /*!
00818  * @name Register CMT_CMD2, field MB[7:0] (RW)
00819  *
00820  * Controls the lower mark periods of the modulator for all modes.
00821  */
00822 /*@{*/
00823 #define BP_CMT_CMD2_MB       (0U)          /*!< Bit position for CMT_CMD2_MB. */
00824 #define BM_CMT_CMD2_MB       (0xFFU)       /*!< Bit mask for CMT_CMD2_MB. */
00825 #define BS_CMT_CMD2_MB       (8U)          /*!< Bit field size in bits for CMT_CMD2_MB. */
00826 
00827 /*! @brief Read current value of the CMT_CMD2_MB field. */
00828 #define BR_CMT_CMD2_MB(x)    (HW_CMT_CMD2(x).U)
00829 
00830 /*! @brief Format value for bitfield CMT_CMD2_MB. */
00831 #define BF_CMT_CMD2_MB(v)    ((uint8_t)((uint8_t)(v) << BP_CMT_CMD2_MB) & BM_CMT_CMD2_MB)
00832 
00833 /*! @brief Set the MB field to a new value. */
00834 #define BW_CMT_CMD2_MB(x, v) (HW_CMT_CMD2_WR(x, v))
00835 /*@}*/
00836 
00837 /*******************************************************************************
00838  * HW_CMT_CMD3 - CMT Modulator Data Register Space High
00839  ******************************************************************************/
00840 
00841 /*!
00842  * @brief HW_CMT_CMD3 - CMT Modulator Data Register Space High (RW)
00843  *
00844  * Reset value: 0x00U
00845  *
00846  * The contents of this register are transferred to the space period register
00847  * upon the completion of a modulation period.
00848  */
00849 typedef union _hw_cmt_cmd3
00850 {
00851     uint8_t U;
00852     struct _hw_cmt_cmd3_bitfields
00853     {
00854         uint8_t SB : 8;                /*!< [7:0]  */
00855     } B;
00856 } hw_cmt_cmd3_t;
00857 
00858 /*!
00859  * @name Constants and macros for entire CMT_CMD3 register
00860  */
00861 /*@{*/
00862 #define HW_CMT_CMD3_ADDR(x)      ((x) + 0x8U)
00863 
00864 #define HW_CMT_CMD3(x)           (*(__IO hw_cmt_cmd3_t *) HW_CMT_CMD3_ADDR(x))
00865 #define HW_CMT_CMD3_RD(x)        (ADDRESS_READ(hw_cmt_cmd3_t, HW_CMT_CMD3_ADDR(x)))
00866 #define HW_CMT_CMD3_WR(x, v)     (ADDRESS_WRITE(hw_cmt_cmd3_t, HW_CMT_CMD3_ADDR(x), v))
00867 #define HW_CMT_CMD3_SET(x, v)    (HW_CMT_CMD3_WR(x, HW_CMT_CMD3_RD(x) |  (v)))
00868 #define HW_CMT_CMD3_CLR(x, v)    (HW_CMT_CMD3_WR(x, HW_CMT_CMD3_RD(x) & ~(v)))
00869 #define HW_CMT_CMD3_TOG(x, v)    (HW_CMT_CMD3_WR(x, HW_CMT_CMD3_RD(x) ^  (v)))
00870 /*@}*/
00871 
00872 /*
00873  * Constants & macros for individual CMT_CMD3 bitfields
00874  */
00875 
00876 /*!
00877  * @name Register CMT_CMD3, field SB[7:0] (RW)
00878  *
00879  * Controls the upper space periods of the modulator for all modes.
00880  */
00881 /*@{*/
00882 #define BP_CMT_CMD3_SB       (0U)          /*!< Bit position for CMT_CMD3_SB. */
00883 #define BM_CMT_CMD3_SB       (0xFFU)       /*!< Bit mask for CMT_CMD3_SB. */
00884 #define BS_CMT_CMD3_SB       (8U)          /*!< Bit field size in bits for CMT_CMD3_SB. */
00885 
00886 /*! @brief Read current value of the CMT_CMD3_SB field. */
00887 #define BR_CMT_CMD3_SB(x)    (HW_CMT_CMD3(x).U)
00888 
00889 /*! @brief Format value for bitfield CMT_CMD3_SB. */
00890 #define BF_CMT_CMD3_SB(v)    ((uint8_t)((uint8_t)(v) << BP_CMT_CMD3_SB) & BM_CMT_CMD3_SB)
00891 
00892 /*! @brief Set the SB field to a new value. */
00893 #define BW_CMT_CMD3_SB(x, v) (HW_CMT_CMD3_WR(x, v))
00894 /*@}*/
00895 
00896 /*******************************************************************************
00897  * HW_CMT_CMD4 - CMT Modulator Data Register Space Low
00898  ******************************************************************************/
00899 
00900 /*!
00901  * @brief HW_CMT_CMD4 - CMT Modulator Data Register Space Low (RW)
00902  *
00903  * Reset value: 0x00U
00904  *
00905  * The contents of this register are transferred to the space period register
00906  * upon the completion of a modulation period.
00907  */
00908 typedef union _hw_cmt_cmd4
00909 {
00910     uint8_t U;
00911     struct _hw_cmt_cmd4_bitfields
00912     {
00913         uint8_t SB : 8;                /*!< [7:0]  */
00914     } B;
00915 } hw_cmt_cmd4_t;
00916 
00917 /*!
00918  * @name Constants and macros for entire CMT_CMD4 register
00919  */
00920 /*@{*/
00921 #define HW_CMT_CMD4_ADDR(x)      ((x) + 0x9U)
00922 
00923 #define HW_CMT_CMD4(x)           (*(__IO hw_cmt_cmd4_t *) HW_CMT_CMD4_ADDR(x))
00924 #define HW_CMT_CMD4_RD(x)        (ADDRESS_READ(hw_cmt_cmd4_t, HW_CMT_CMD4_ADDR(x)))
00925 #define HW_CMT_CMD4_WR(x, v)     (ADDRESS_WRITE(hw_cmt_cmd4_t, HW_CMT_CMD4_ADDR(x), v))
00926 #define HW_CMT_CMD4_SET(x, v)    (HW_CMT_CMD4_WR(x, HW_CMT_CMD4_RD(x) |  (v)))
00927 #define HW_CMT_CMD4_CLR(x, v)    (HW_CMT_CMD4_WR(x, HW_CMT_CMD4_RD(x) & ~(v)))
00928 #define HW_CMT_CMD4_TOG(x, v)    (HW_CMT_CMD4_WR(x, HW_CMT_CMD4_RD(x) ^  (v)))
00929 /*@}*/
00930 
00931 /*
00932  * Constants & macros for individual CMT_CMD4 bitfields
00933  */
00934 
00935 /*!
00936  * @name Register CMT_CMD4, field SB[7:0] (RW)
00937  *
00938  * Controls the lower space periods of the modulator for all modes.
00939  */
00940 /*@{*/
00941 #define BP_CMT_CMD4_SB       (0U)          /*!< Bit position for CMT_CMD4_SB. */
00942 #define BM_CMT_CMD4_SB       (0xFFU)       /*!< Bit mask for CMT_CMD4_SB. */
00943 #define BS_CMT_CMD4_SB       (8U)          /*!< Bit field size in bits for CMT_CMD4_SB. */
00944 
00945 /*! @brief Read current value of the CMT_CMD4_SB field. */
00946 #define BR_CMT_CMD4_SB(x)    (HW_CMT_CMD4(x).U)
00947 
00948 /*! @brief Format value for bitfield CMT_CMD4_SB. */
00949 #define BF_CMT_CMD4_SB(v)    ((uint8_t)((uint8_t)(v) << BP_CMT_CMD4_SB) & BM_CMT_CMD4_SB)
00950 
00951 /*! @brief Set the SB field to a new value. */
00952 #define BW_CMT_CMD4_SB(x, v) (HW_CMT_CMD4_WR(x, v))
00953 /*@}*/
00954 
00955 /*******************************************************************************
00956  * HW_CMT_PPS - CMT Primary Prescaler Register
00957  ******************************************************************************/
00958 
00959 /*!
00960  * @brief HW_CMT_PPS - CMT Primary Prescaler Register (RW)
00961  *
00962  * Reset value: 0x00U
00963  *
00964  * This register is used to set the Primary Prescaler Divider field (PPSDIV).
00965  */
00966 typedef union _hw_cmt_pps
00967 {
00968     uint8_t U;
00969     struct _hw_cmt_pps_bitfields
00970     {
00971         uint8_t PPSDIV : 4;            /*!< [3:0] Primary Prescaler Divider */
00972         uint8_t RESERVED0 : 4;         /*!< [7:4]  */
00973     } B;
00974 } hw_cmt_pps_t;
00975 
00976 /*!
00977  * @name Constants and macros for entire CMT_PPS register
00978  */
00979 /*@{*/
00980 #define HW_CMT_PPS_ADDR(x)       ((x) + 0xAU)
00981 
00982 #define HW_CMT_PPS(x)            (*(__IO hw_cmt_pps_t *) HW_CMT_PPS_ADDR(x))
00983 #define HW_CMT_PPS_RD(x)         (ADDRESS_READ(hw_cmt_pps_t, HW_CMT_PPS_ADDR(x)))
00984 #define HW_CMT_PPS_WR(x, v)      (ADDRESS_WRITE(hw_cmt_pps_t, HW_CMT_PPS_ADDR(x), v))
00985 #define HW_CMT_PPS_SET(x, v)     (HW_CMT_PPS_WR(x, HW_CMT_PPS_RD(x) |  (v)))
00986 #define HW_CMT_PPS_CLR(x, v)     (HW_CMT_PPS_WR(x, HW_CMT_PPS_RD(x) & ~(v)))
00987 #define HW_CMT_PPS_TOG(x, v)     (HW_CMT_PPS_WR(x, HW_CMT_PPS_RD(x) ^  (v)))
00988 /*@}*/
00989 
00990 /*
00991  * Constants & macros for individual CMT_PPS bitfields
00992  */
00993 
00994 /*!
00995  * @name Register CMT_PPS, field PPSDIV[3:0] (RW)
00996  *
00997  * Divides the CMT clock to generate the Intermediate Frequency clock enable to
00998  * the secondary prescaler.
00999  *
01000  * Values:
01001  * - 0000 - Bus clock * 1
01002  * - 0001 - Bus clock * 2
01003  * - 0010 - Bus clock * 3
01004  * - 0011 - Bus clock * 4
01005  * - 0100 - Bus clock * 5
01006  * - 0101 - Bus clock * 6
01007  * - 0110 - Bus clock * 7
01008  * - 0111 - Bus clock * 8
01009  * - 1000 - Bus clock * 9
01010  * - 1001 - Bus clock * 10
01011  * - 1010 - Bus clock * 11
01012  * - 1011 - Bus clock * 12
01013  * - 1100 - Bus clock * 13
01014  * - 1101 - Bus clock * 14
01015  * - 1110 - Bus clock * 15
01016  * - 1111 - Bus clock * 16
01017  */
01018 /*@{*/
01019 #define BP_CMT_PPS_PPSDIV    (0U)          /*!< Bit position for CMT_PPS_PPSDIV. */
01020 #define BM_CMT_PPS_PPSDIV    (0x0FU)       /*!< Bit mask for CMT_PPS_PPSDIV. */
01021 #define BS_CMT_PPS_PPSDIV    (4U)          /*!< Bit field size in bits for CMT_PPS_PPSDIV. */
01022 
01023 /*! @brief Read current value of the CMT_PPS_PPSDIV field. */
01024 #define BR_CMT_PPS_PPSDIV(x) (UNION_READ(hw_cmt_pps_t, HW_CMT_PPS_ADDR(x), U, B.PPSDIV))
01025 
01026 /*! @brief Format value for bitfield CMT_PPS_PPSDIV. */
01027 #define BF_CMT_PPS_PPSDIV(v) ((uint8_t)((uint8_t)(v) << BP_CMT_PPS_PPSDIV) & BM_CMT_PPS_PPSDIV)
01028 
01029 /*! @brief Set the PPSDIV field to a new value. */
01030 #define BW_CMT_PPS_PPSDIV(x, v) (HW_CMT_PPS_WR(x, (HW_CMT_PPS_RD(x) & ~BM_CMT_PPS_PPSDIV) | BF_CMT_PPS_PPSDIV(v)))
01031 /*@}*/
01032 
01033 /*******************************************************************************
01034  * HW_CMT_DMA - CMT Direct Memory Access Register
01035  ******************************************************************************/
01036 
01037 /*!
01038  * @brief HW_CMT_DMA - CMT Direct Memory Access Register (RW)
01039  *
01040  * Reset value: 0x00U
01041  *
01042  * This register is used to enable/disable direct memory access (DMA).
01043  */
01044 typedef union _hw_cmt_dma
01045 {
01046     uint8_t U;
01047     struct _hw_cmt_dma_bitfields
01048     {
01049         uint8_t DMA : 1;               /*!< [0] DMA Enable */
01050         uint8_t RESERVED0 : 7;         /*!< [7:1]  */
01051     } B;
01052 } hw_cmt_dma_t;
01053 
01054 /*!
01055  * @name Constants and macros for entire CMT_DMA register
01056  */
01057 /*@{*/
01058 #define HW_CMT_DMA_ADDR(x)       ((x) + 0xBU)
01059 
01060 #define HW_CMT_DMA(x)            (*(__IO hw_cmt_dma_t *) HW_CMT_DMA_ADDR(x))
01061 #define HW_CMT_DMA_RD(x)         (ADDRESS_READ(hw_cmt_dma_t, HW_CMT_DMA_ADDR(x)))
01062 #define HW_CMT_DMA_WR(x, v)      (ADDRESS_WRITE(hw_cmt_dma_t, HW_CMT_DMA_ADDR(x), v))
01063 #define HW_CMT_DMA_SET(x, v)     (HW_CMT_DMA_WR(x, HW_CMT_DMA_RD(x) |  (v)))
01064 #define HW_CMT_DMA_CLR(x, v)     (HW_CMT_DMA_WR(x, HW_CMT_DMA_RD(x) & ~(v)))
01065 #define HW_CMT_DMA_TOG(x, v)     (HW_CMT_DMA_WR(x, HW_CMT_DMA_RD(x) ^  (v)))
01066 /*@}*/
01067 
01068 /*
01069  * Constants & macros for individual CMT_DMA bitfields
01070  */
01071 
01072 /*!
01073  * @name Register CMT_DMA, field DMA[0] (RW)
01074  *
01075  * Enables the DMA protocol.
01076  *
01077  * Values:
01078  * - 0 - DMA transfer request and done are disabled.
01079  * - 1 - DMA transfer request and done are enabled.
01080  */
01081 /*@{*/
01082 #define BP_CMT_DMA_DMA       (0U)          /*!< Bit position for CMT_DMA_DMA. */
01083 #define BM_CMT_DMA_DMA       (0x01U)       /*!< Bit mask for CMT_DMA_DMA. */
01084 #define BS_CMT_DMA_DMA       (1U)          /*!< Bit field size in bits for CMT_DMA_DMA. */
01085 
01086 /*! @brief Read current value of the CMT_DMA_DMA field. */
01087 #define BR_CMT_DMA_DMA(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_CMT_DMA_ADDR(x), BP_CMT_DMA_DMA)))
01088 
01089 /*! @brief Format value for bitfield CMT_DMA_DMA. */
01090 #define BF_CMT_DMA_DMA(v)    ((uint8_t)((uint8_t)(v) << BP_CMT_DMA_DMA) & BM_CMT_DMA_DMA)
01091 
01092 /*! @brief Set the DMA field to a new value. */
01093 #define BW_CMT_DMA_DMA(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_CMT_DMA_ADDR(x), BP_CMT_DMA_DMA), v))
01094 /*@}*/
01095 
01096 /*******************************************************************************
01097  * hw_cmt_t - module struct
01098  ******************************************************************************/
01099 /*!
01100  * @brief All CMT module registers.
01101  */
01102 #pragma pack(1)
01103 typedef struct _hw_cmt
01104 {
01105     __IO hw_cmt_cgh1_t CGH1 ;               /*!< [0x0] CMT Carrier Generator High Data Register 1 */
01106     __IO hw_cmt_cgl1_t CGL1 ;               /*!< [0x1] CMT Carrier Generator Low Data Register 1 */
01107     __IO hw_cmt_cgh2_t CGH2 ;               /*!< [0x2] CMT Carrier Generator High Data Register 2 */
01108     __IO hw_cmt_cgl2_t CGL2 ;               /*!< [0x3] CMT Carrier Generator Low Data Register 2 */
01109     __IO hw_cmt_oc_t OC ;                   /*!< [0x4] CMT Output Control Register */
01110     __IO hw_cmt_msc_t MSC ;                 /*!< [0x5] CMT Modulator Status and Control Register */
01111     __IO hw_cmt_cmd1_t CMD1 ;               /*!< [0x6] CMT Modulator Data Register Mark High */
01112     __IO hw_cmt_cmd2_t CMD2 ;               /*!< [0x7] CMT Modulator Data Register Mark Low */
01113     __IO hw_cmt_cmd3_t CMD3 ;               /*!< [0x8] CMT Modulator Data Register Space High */
01114     __IO hw_cmt_cmd4_t CMD4 ;               /*!< [0x9] CMT Modulator Data Register Space Low */
01115     __IO hw_cmt_pps_t PPS ;                 /*!< [0xA] CMT Primary Prescaler Register */
01116     __IO hw_cmt_dma_t DMA ;                 /*!< [0xB] CMT Direct Memory Access Register */
01117 } hw_cmt_t;
01118 #pragma pack()
01119 
01120 /*! @brief Macro to access all CMT registers. */
01121 /*! @param x CMT module instance base address. */
01122 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
01123  *     use the '&' operator, like <code>&HW_CMT(CMT_BASE)</code>. */
01124 #define HW_CMT(x)      (*(hw_cmt_t *)(x))
01125 
01126 #endif /* __HW_CMT_REGISTERS_H__ */
01127 /* EOF */