MK64F12_cmp.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_CMP_REGISTERS_H__
00088 #define __HW_CMP_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 CMP
00095  *
00096  * High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
00097  *
00098  * Registers defined in this header file:
00099  * - HW_CMP_CR0 - CMP Control Register 0
00100  * - HW_CMP_CR1 - CMP Control Register 1
00101  * - HW_CMP_FPR - CMP Filter Period Register
00102  * - HW_CMP_SCR - CMP Status and Control Register
00103  * - HW_CMP_DACCR - DAC Control Register
00104  * - HW_CMP_MUXCR - MUX Control Register
00105  *
00106  * - hw_cmp_t - Struct containing all module registers.
00107  */
00108 
00109 #define HW_CMP_INSTANCE_COUNT (3U) /*!< Number of instances of the CMP module. */
00110 #define HW_CMP0 (0U) /*!< Instance number for CMP0. */
00111 #define HW_CMP1 (1U) /*!< Instance number for CMP1. */
00112 #define HW_CMP2 (2U) /*!< Instance number for CMP2. */
00113 
00114 /*******************************************************************************
00115  * HW_CMP_CR0 - CMP Control Register 0
00116  ******************************************************************************/
00117 
00118 /*!
00119  * @brief HW_CMP_CR0 - CMP Control Register 0 (RW)
00120  *
00121  * Reset value: 0x00U
00122  */
00123 typedef union _hw_cmp_cr0
00124 {
00125     uint8_t U;
00126     struct _hw_cmp_cr0_bitfields
00127     {
00128         uint8_t HYSTCTR : 2;           /*!< [1:0] Comparator hard block hysteresis
00129                                         * control */
00130         uint8_t RESERVED0 : 2;         /*!< [3:2]  */
00131         uint8_t FILTER_CNT : 3;        /*!< [6:4] Filter Sample Count */
00132         uint8_t RESERVED1 : 1;         /*!< [7]  */
00133     } B;
00134 } hw_cmp_cr0_t;
00135 
00136 /*!
00137  * @name Constants and macros for entire CMP_CR0 register
00138  */
00139 /*@{*/
00140 #define HW_CMP_CR0_ADDR(x)       ((x) + 0x0U)
00141 
00142 #define HW_CMP_CR0(x)            (*(__IO hw_cmp_cr0_t *) HW_CMP_CR0_ADDR(x))
00143 #define HW_CMP_CR0_RD(x)         (ADDRESS_READ(hw_cmp_cr0_t, HW_CMP_CR0_ADDR(x)))
00144 #define HW_CMP_CR0_WR(x, v)      (ADDRESS_WRITE(hw_cmp_cr0_t, HW_CMP_CR0_ADDR(x), v))
00145 #define HW_CMP_CR0_SET(x, v)     (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) |  (v)))
00146 #define HW_CMP_CR0_CLR(x, v)     (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) & ~(v)))
00147 #define HW_CMP_CR0_TOG(x, v)     (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) ^  (v)))
00148 /*@}*/
00149 
00150 /*
00151  * Constants & macros for individual CMP_CR0 bitfields
00152  */
00153 
00154 /*!
00155  * @name Register CMP_CR0, field HYSTCTR[1:0] (RW)
00156  *
00157  * Defines the programmable hysteresis level. The hysteresis values associated
00158  * with each level are device-specific. See the Data Sheet of the device for the
00159  * exact values.
00160  *
00161  * Values:
00162  * - 00 - Level 0
00163  * - 01 - Level 1
00164  * - 10 - Level 2
00165  * - 11 - Level 3
00166  */
00167 /*@{*/
00168 #define BP_CMP_CR0_HYSTCTR   (0U)          /*!< Bit position for CMP_CR0_HYSTCTR. */
00169 #define BM_CMP_CR0_HYSTCTR   (0x03U)       /*!< Bit mask for CMP_CR0_HYSTCTR. */
00170 #define BS_CMP_CR0_HYSTCTR   (2U)          /*!< Bit field size in bits for CMP_CR0_HYSTCTR. */
00171 
00172 /*! @brief Read current value of the CMP_CR0_HYSTCTR field. */
00173 #define BR_CMP_CR0_HYSTCTR(x) (UNION_READ(hw_cmp_cr0_t, HW_CMP_CR0_ADDR(x), U, B.HYSTCTR))
00174 
00175 /*! @brief Format value for bitfield CMP_CR0_HYSTCTR. */
00176 #define BF_CMP_CR0_HYSTCTR(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR0_HYSTCTR) & BM_CMP_CR0_HYSTCTR)
00177 
00178 /*! @brief Set the HYSTCTR field to a new value. */
00179 #define BW_CMP_CR0_HYSTCTR(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_HYSTCTR) | BF_CMP_CR0_HYSTCTR(v)))
00180 /*@}*/
00181 
00182 /*!
00183  * @name Register CMP_CR0, field FILTER_CNT[6:4] (RW)
00184  *
00185  * Represents the number of consecutive samples that must agree prior to the
00186  * comparator ouput filter accepting a new output state. For information regarding
00187  * filter programming and latency, see the Functional descriptionThe CMP module
00188  * can be used to compare two analog input voltages applied to INP and INM. .
00189  *
00190  * Values:
00191  * - 000 - Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a
00192  *     legal state, and is not recommended. If SE = 0, COUT = COUTA.
00193  * - 001 - One sample must agree. The comparator output is simply sampled.
00194  * - 010 - 2 consecutive samples must agree.
00195  * - 011 - 3 consecutive samples must agree.
00196  * - 100 - 4 consecutive samples must agree.
00197  * - 101 - 5 consecutive samples must agree.
00198  * - 110 - 6 consecutive samples must agree.
00199  * - 111 - 7 consecutive samples must agree.
00200  */
00201 /*@{*/
00202 #define BP_CMP_CR0_FILTER_CNT (4U)         /*!< Bit position for CMP_CR0_FILTER_CNT. */
00203 #define BM_CMP_CR0_FILTER_CNT (0x70U)      /*!< Bit mask for CMP_CR0_FILTER_CNT. */
00204 #define BS_CMP_CR0_FILTER_CNT (3U)         /*!< Bit field size in bits for CMP_CR0_FILTER_CNT. */
00205 
00206 /*! @brief Read current value of the CMP_CR0_FILTER_CNT field. */
00207 #define BR_CMP_CR0_FILTER_CNT(x) (UNION_READ(hw_cmp_cr0_t, HW_CMP_CR0_ADDR(x), U, B.FILTER_CNT))
00208 
00209 /*! @brief Format value for bitfield CMP_CR0_FILTER_CNT. */
00210 #define BF_CMP_CR0_FILTER_CNT(v) ((uint8_t)((uint8_t)(v) << BP_CMP_CR0_FILTER_CNT) & BM_CMP_CR0_FILTER_CNT)
00211 
00212 /*! @brief Set the FILTER_CNT field to a new value. */
00213 #define BW_CMP_CR0_FILTER_CNT(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_FILTER_CNT) | BF_CMP_CR0_FILTER_CNT(v)))
00214 /*@}*/
00215 
00216 /*******************************************************************************
00217  * HW_CMP_CR1 - CMP Control Register 1
00218  ******************************************************************************/
00219 
00220 /*!
00221  * @brief HW_CMP_CR1 - CMP Control Register 1 (RW)
00222  *
00223  * Reset value: 0x00U
00224  */
00225 typedef union _hw_cmp_cr1
00226 {
00227     uint8_t U;
00228     struct _hw_cmp_cr1_bitfields
00229     {
00230         uint8_t EN : 1;                /*!< [0] Comparator Module Enable */
00231         uint8_t OPE : 1;               /*!< [1] Comparator Output Pin Enable */
00232         uint8_t COS : 1;               /*!< [2] Comparator Output Select */
00233         uint8_t INV : 1;               /*!< [3] Comparator INVERT */
00234         uint8_t PMODE : 1;             /*!< [4] Power Mode Select */
00235         uint8_t RESERVED0 : 1;         /*!< [5]  */
00236         uint8_t WE : 1;                /*!< [6] Windowing Enable */
00237         uint8_t SE : 1;                /*!< [7] Sample Enable */
00238     } B;
00239 } hw_cmp_cr1_t;
00240 
00241 /*!
00242  * @name Constants and macros for entire CMP_CR1 register
00243  */
00244 /*@{*/
00245 #define HW_CMP_CR1_ADDR(x)       ((x) + 0x1U)
00246 
00247 #define HW_CMP_CR1(x)            (*(__IO hw_cmp_cr1_t *) HW_CMP_CR1_ADDR(x))
00248 #define HW_CMP_CR1_RD(x)         (ADDRESS_READ(hw_cmp_cr1_t, HW_CMP_CR1_ADDR(x)))
00249 #define HW_CMP_CR1_WR(x, v)      (ADDRESS_WRITE(hw_cmp_cr1_t, HW_CMP_CR1_ADDR(x), v))
00250 #define HW_CMP_CR1_SET(x, v)     (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) |  (v)))
00251 #define HW_CMP_CR1_CLR(x, v)     (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) & ~(v)))
00252 #define HW_CMP_CR1_TOG(x, v)     (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) ^  (v)))
00253 /*@}*/
00254 
00255 /*
00256  * Constants & macros for individual CMP_CR1 bitfields
00257  */
00258 
00259 /*!
00260  * @name Register CMP_CR1, field EN[0] (RW)
00261  *
00262  * Enables the Analog Comparator module. When the module is not enabled, it
00263  * remains in the off state, and consumes no power. When the user selects the same
00264  * input from analog mux to the positive and negative port, the comparator is
00265  * disabled automatically.
00266  *
00267  * Values:
00268  * - 0 - Analog Comparator is disabled.
00269  * - 1 - Analog Comparator is enabled.
00270  */
00271 /*@{*/
00272 #define BP_CMP_CR1_EN        (0U)          /*!< Bit position for CMP_CR1_EN. */
00273 #define BM_CMP_CR1_EN        (0x01U)       /*!< Bit mask for CMP_CR1_EN. */
00274 #define BS_CMP_CR1_EN        (1U)          /*!< Bit field size in bits for CMP_CR1_EN. */
00275 
00276 /*! @brief Read current value of the CMP_CR1_EN field. */
00277 #define BR_CMP_CR1_EN(x)     (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN)))
00278 
00279 /*! @brief Format value for bitfield CMP_CR1_EN. */
00280 #define BF_CMP_CR1_EN(v)     ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_EN) & BM_CMP_CR1_EN)
00281 
00282 /*! @brief Set the EN field to a new value. */
00283 #define BW_CMP_CR1_EN(x, v)  (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN), v))
00284 /*@}*/
00285 
00286 /*!
00287  * @name Register CMP_CR1, field OPE[1] (RW)
00288  *
00289  * Values:
00290  * - 0 - CMPO is not available on the associated CMPO output pin. If the
00291  *     comparator does not own the pin, this field has no effect.
00292  * - 1 - CMPO is available on the associated CMPO output pin. The comparator
00293  *     output (CMPO) is driven out on the associated CMPO output pin if the
00294  *     comparator owns the pin. If the comparator does not own the field, this bit has no
00295  *     effect.
00296  */
00297 /*@{*/
00298 #define BP_CMP_CR1_OPE       (1U)          /*!< Bit position for CMP_CR1_OPE. */
00299 #define BM_CMP_CR1_OPE       (0x02U)       /*!< Bit mask for CMP_CR1_OPE. */
00300 #define BS_CMP_CR1_OPE       (1U)          /*!< Bit field size in bits for CMP_CR1_OPE. */
00301 
00302 /*! @brief Read current value of the CMP_CR1_OPE field. */
00303 #define BR_CMP_CR1_OPE(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE)))
00304 
00305 /*! @brief Format value for bitfield CMP_CR1_OPE. */
00306 #define BF_CMP_CR1_OPE(v)    ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_OPE) & BM_CMP_CR1_OPE)
00307 
00308 /*! @brief Set the OPE field to a new value. */
00309 #define BW_CMP_CR1_OPE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE), v))
00310 /*@}*/
00311 
00312 /*!
00313  * @name Register CMP_CR1, field COS[2] (RW)
00314  *
00315  * Values:
00316  * - 0 - Set the filtered comparator output (CMPO) to equal COUT.
00317  * - 1 - Set the unfiltered comparator output (CMPO) to equal COUTA.
00318  */
00319 /*@{*/
00320 #define BP_CMP_CR1_COS       (2U)          /*!< Bit position for CMP_CR1_COS. */
00321 #define BM_CMP_CR1_COS       (0x04U)       /*!< Bit mask for CMP_CR1_COS. */
00322 #define BS_CMP_CR1_COS       (1U)          /*!< Bit field size in bits for CMP_CR1_COS. */
00323 
00324 /*! @brief Read current value of the CMP_CR1_COS field. */
00325 #define BR_CMP_CR1_COS(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS)))
00326 
00327 /*! @brief Format value for bitfield CMP_CR1_COS. */
00328 #define BF_CMP_CR1_COS(v)    ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_COS) & BM_CMP_CR1_COS)
00329 
00330 /*! @brief Set the COS field to a new value. */
00331 #define BW_CMP_CR1_COS(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS), v))
00332 /*@}*/
00333 
00334 /*!
00335  * @name Register CMP_CR1, field INV[3] (RW)
00336  *
00337  * Allows selection of the polarity of the analog comparator function. It is
00338  * also driven to the COUT output, on both the device pin and as SCR[COUT], when
00339  * OPE=0.
00340  *
00341  * Values:
00342  * - 0 - Does not invert the comparator output.
00343  * - 1 - Inverts the comparator output.
00344  */
00345 /*@{*/
00346 #define BP_CMP_CR1_INV       (3U)          /*!< Bit position for CMP_CR1_INV. */
00347 #define BM_CMP_CR1_INV       (0x08U)       /*!< Bit mask for CMP_CR1_INV. */
00348 #define BS_CMP_CR1_INV       (1U)          /*!< Bit field size in bits for CMP_CR1_INV. */
00349 
00350 /*! @brief Read current value of the CMP_CR1_INV field. */
00351 #define BR_CMP_CR1_INV(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV)))
00352 
00353 /*! @brief Format value for bitfield CMP_CR1_INV. */
00354 #define BF_CMP_CR1_INV(v)    ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_INV) & BM_CMP_CR1_INV)
00355 
00356 /*! @brief Set the INV field to a new value. */
00357 #define BW_CMP_CR1_INV(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV), v))
00358 /*@}*/
00359 
00360 /*!
00361  * @name Register CMP_CR1, field PMODE[4] (RW)
00362  *
00363  * See the electrical specifications table in the device Data Sheet for details.
00364  *
00365  * Values:
00366  * - 0 - Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower
00367  *     output propagation delay and lower current consumption.
00368  * - 1 - High-Speed (HS) Comparison mode selected. In this mode, CMP has faster
00369  *     output propagation delay and higher current consumption.
00370  */
00371 /*@{*/
00372 #define BP_CMP_CR1_PMODE     (4U)          /*!< Bit position for CMP_CR1_PMODE. */
00373 #define BM_CMP_CR1_PMODE     (0x10U)       /*!< Bit mask for CMP_CR1_PMODE. */
00374 #define BS_CMP_CR1_PMODE     (1U)          /*!< Bit field size in bits for CMP_CR1_PMODE. */
00375 
00376 /*! @brief Read current value of the CMP_CR1_PMODE field. */
00377 #define BR_CMP_CR1_PMODE(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE)))
00378 
00379 /*! @brief Format value for bitfield CMP_CR1_PMODE. */
00380 #define BF_CMP_CR1_PMODE(v)  ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_PMODE) & BM_CMP_CR1_PMODE)
00381 
00382 /*! @brief Set the PMODE field to a new value. */
00383 #define BW_CMP_CR1_PMODE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE), v))
00384 /*@}*/
00385 
00386 /*!
00387  * @name Register CMP_CR1, field WE[6] (RW)
00388  *
00389  * At any given time, either SE or WE can be set. If a write to this register
00390  * attempts to set both, then SE is set and WE is cleared. However, avoid writing
00391  * 1s to both field locations because this "11" case is reserved and may change in
00392  * future implementations.
00393  *
00394  * Values:
00395  * - 0 - Windowing mode is not selected.
00396  * - 1 - Windowing mode is selected.
00397  */
00398 /*@{*/
00399 #define BP_CMP_CR1_WE        (6U)          /*!< Bit position for CMP_CR1_WE. */
00400 #define BM_CMP_CR1_WE        (0x40U)       /*!< Bit mask for CMP_CR1_WE. */
00401 #define BS_CMP_CR1_WE        (1U)          /*!< Bit field size in bits for CMP_CR1_WE. */
00402 
00403 /*! @brief Read current value of the CMP_CR1_WE field. */
00404 #define BR_CMP_CR1_WE(x)     (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE)))
00405 
00406 /*! @brief Format value for bitfield CMP_CR1_WE. */
00407 #define BF_CMP_CR1_WE(v)     ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_WE) & BM_CMP_CR1_WE)
00408 
00409 /*! @brief Set the WE field to a new value. */
00410 #define BW_CMP_CR1_WE(x, v)  (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE), v))
00411 /*@}*/
00412 
00413 /*!
00414  * @name Register CMP_CR1, field SE[7] (RW)
00415  *
00416  * At any given time, either SE or WE can be set. If a write to this register
00417  * attempts to set both, then SE is set and WE is cleared. However, avoid writing
00418  * 1s to both field locations because this "11" case is reserved and may change in
00419  * future implementations.
00420  *
00421  * Values:
00422  * - 0 - Sampling mode is not selected.
00423  * - 1 - Sampling mode is selected.
00424  */
00425 /*@{*/
00426 #define BP_CMP_CR1_SE        (7U)          /*!< Bit position for CMP_CR1_SE. */
00427 #define BM_CMP_CR1_SE        (0x80U)       /*!< Bit mask for CMP_CR1_SE. */
00428 #define BS_CMP_CR1_SE        (1U)          /*!< Bit field size in bits for CMP_CR1_SE. */
00429 
00430 /*! @brief Read current value of the CMP_CR1_SE field. */
00431 #define BR_CMP_CR1_SE(x)     (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE)))
00432 
00433 /*! @brief Format value for bitfield CMP_CR1_SE. */
00434 #define BF_CMP_CR1_SE(v)     ((uint8_t)((uint8_t)(v) << BP_CMP_CR1_SE) & BM_CMP_CR1_SE)
00435 
00436 /*! @brief Set the SE field to a new value. */
00437 #define BW_CMP_CR1_SE(x, v)  (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE), v))
00438 /*@}*/
00439 
00440 /*******************************************************************************
00441  * HW_CMP_FPR - CMP Filter Period Register
00442  ******************************************************************************/
00443 
00444 /*!
00445  * @brief HW_CMP_FPR - CMP Filter Period Register (RW)
00446  *
00447  * Reset value: 0x00U
00448  */
00449 typedef union _hw_cmp_fpr
00450 {
00451     uint8_t U;
00452     struct _hw_cmp_fpr_bitfields
00453     {
00454         uint8_t FILT_PER : 8;          /*!< [7:0] Filter Sample Period */
00455     } B;
00456 } hw_cmp_fpr_t;
00457 
00458 /*!
00459  * @name Constants and macros for entire CMP_FPR register
00460  */
00461 /*@{*/
00462 #define HW_CMP_FPR_ADDR(x)       ((x) + 0x2U)
00463 
00464 #define HW_CMP_FPR(x)            (*(__IO hw_cmp_fpr_t *) HW_CMP_FPR_ADDR(x))
00465 #define HW_CMP_FPR_RD(x)         (ADDRESS_READ(hw_cmp_fpr_t, HW_CMP_FPR_ADDR(x)))
00466 #define HW_CMP_FPR_WR(x, v)      (ADDRESS_WRITE(hw_cmp_fpr_t, HW_CMP_FPR_ADDR(x), v))
00467 #define HW_CMP_FPR_SET(x, v)     (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) |  (v)))
00468 #define HW_CMP_FPR_CLR(x, v)     (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) & ~(v)))
00469 #define HW_CMP_FPR_TOG(x, v)     (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) ^  (v)))
00470 /*@}*/
00471 
00472 /*
00473  * Constants & macros for individual CMP_FPR bitfields
00474  */
00475 
00476 /*!
00477  * @name Register CMP_FPR, field FILT_PER[7:0] (RW)
00478  *
00479  * Specifies the sampling period, in bus clock cycles, of the comparator output
00480  * filter, when CR1[SE]=0. Setting FILT_PER to 0x0 disables the filter. Filter
00481  * programming and latency details appear in the Functional descriptionThe CMP
00482  * module can be used to compare two analog input voltages applied to INP and INM. .
00483  * This field has no effect when CR1[SE]=1. In that case, the external SAMPLE
00484  * signal is used to determine the sampling period.
00485  */
00486 /*@{*/
00487 #define BP_CMP_FPR_FILT_PER  (0U)          /*!< Bit position for CMP_FPR_FILT_PER. */
00488 #define BM_CMP_FPR_FILT_PER  (0xFFU)       /*!< Bit mask for CMP_FPR_FILT_PER. */
00489 #define BS_CMP_FPR_FILT_PER  (8U)          /*!< Bit field size in bits for CMP_FPR_FILT_PER. */
00490 
00491 /*! @brief Read current value of the CMP_FPR_FILT_PER field. */
00492 #define BR_CMP_FPR_FILT_PER(x) (HW_CMP_FPR(x).U)
00493 
00494 /*! @brief Format value for bitfield CMP_FPR_FILT_PER. */
00495 #define BF_CMP_FPR_FILT_PER(v) ((uint8_t)((uint8_t)(v) << BP_CMP_FPR_FILT_PER) & BM_CMP_FPR_FILT_PER)
00496 
00497 /*! @brief Set the FILT_PER field to a new value. */
00498 #define BW_CMP_FPR_FILT_PER(x, v) (HW_CMP_FPR_WR(x, v))
00499 /*@}*/
00500 
00501 /*******************************************************************************
00502  * HW_CMP_SCR - CMP Status and Control Register
00503  ******************************************************************************/
00504 
00505 /*!
00506  * @brief HW_CMP_SCR - CMP Status and Control Register (RW)
00507  *
00508  * Reset value: 0x00U
00509  */
00510 typedef union _hw_cmp_scr
00511 {
00512     uint8_t U;
00513     struct _hw_cmp_scr_bitfields
00514     {
00515         uint8_t COUT : 1;              /*!< [0] Analog Comparator Output */
00516         uint8_t CFF : 1;               /*!< [1] Analog Comparator Flag Falling */
00517         uint8_t CFR : 1;               /*!< [2] Analog Comparator Flag Rising */
00518         uint8_t IEF : 1;               /*!< [3] Comparator Interrupt Enable Falling */
00519         uint8_t IER : 1;               /*!< [4] Comparator Interrupt Enable Rising */
00520         uint8_t RESERVED0 : 1;         /*!< [5]  */
00521         uint8_t DMAEN : 1;             /*!< [6] DMA Enable Control */
00522         uint8_t RESERVED1 : 1;         /*!< [7]  */
00523     } B;
00524 } hw_cmp_scr_t;
00525 
00526 /*!
00527  * @name Constants and macros for entire CMP_SCR register
00528  */
00529 /*@{*/
00530 #define HW_CMP_SCR_ADDR(x)       ((x) + 0x3U)
00531 
00532 #define HW_CMP_SCR(x)            (*(__IO hw_cmp_scr_t *) HW_CMP_SCR_ADDR(x))
00533 #define HW_CMP_SCR_RD(x)         (ADDRESS_READ(hw_cmp_scr_t, HW_CMP_SCR_ADDR(x)))
00534 #define HW_CMP_SCR_WR(x, v)      (ADDRESS_WRITE(hw_cmp_scr_t, HW_CMP_SCR_ADDR(x), v))
00535 #define HW_CMP_SCR_SET(x, v)     (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) |  (v)))
00536 #define HW_CMP_SCR_CLR(x, v)     (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) & ~(v)))
00537 #define HW_CMP_SCR_TOG(x, v)     (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) ^  (v)))
00538 /*@}*/
00539 
00540 /*
00541  * Constants & macros for individual CMP_SCR bitfields
00542  */
00543 
00544 /*!
00545  * @name Register CMP_SCR, field COUT[0] (RO)
00546  *
00547  * Returns the current value of the Analog Comparator output, when read. The
00548  * field is reset to 0 and will read as CR1[INV] when the Analog Comparator module
00549  * is disabled, that is, when CR1[EN] = 0. Writes to this field are ignored.
00550  */
00551 /*@{*/
00552 #define BP_CMP_SCR_COUT      (0U)          /*!< Bit position for CMP_SCR_COUT. */
00553 #define BM_CMP_SCR_COUT      (0x01U)       /*!< Bit mask for CMP_SCR_COUT. */
00554 #define BS_CMP_SCR_COUT      (1U)          /*!< Bit field size in bits for CMP_SCR_COUT. */
00555 
00556 /*! @brief Read current value of the CMP_SCR_COUT field. */
00557 #define BR_CMP_SCR_COUT(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_COUT)))
00558 /*@}*/
00559 
00560 /*!
00561  * @name Register CMP_SCR, field CFF[1] (W1C)
00562  *
00563  * Detects a falling-edge on COUT, when set, during normal operation. CFF is
00564  * cleared by writing 1 to it. During Stop modes, CFF is level sensitive is edge
00565  * sensitive .
00566  *
00567  * Values:
00568  * - 0 - Falling-edge on COUT has not been detected.
00569  * - 1 - Falling-edge on COUT has occurred.
00570  */
00571 /*@{*/
00572 #define BP_CMP_SCR_CFF       (1U)          /*!< Bit position for CMP_SCR_CFF. */
00573 #define BM_CMP_SCR_CFF       (0x02U)       /*!< Bit mask for CMP_SCR_CFF. */
00574 #define BS_CMP_SCR_CFF       (1U)          /*!< Bit field size in bits for CMP_SCR_CFF. */
00575 
00576 /*! @brief Read current value of the CMP_SCR_CFF field. */
00577 #define BR_CMP_SCR_CFF(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF)))
00578 
00579 /*! @brief Format value for bitfield CMP_SCR_CFF. */
00580 #define BF_CMP_SCR_CFF(v)    ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_CFF) & BM_CMP_SCR_CFF)
00581 
00582 /*! @brief Set the CFF field to a new value. */
00583 #define BW_CMP_SCR_CFF(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF), v))
00584 /*@}*/
00585 
00586 /*!
00587  * @name Register CMP_SCR, field CFR[2] (W1C)
00588  *
00589  * Detects a rising-edge on COUT, when set, during normal operation. CFR is
00590  * cleared by writing 1 to it. During Stop modes, CFR is level sensitive is edge
00591  * sensitive .
00592  *
00593  * Values:
00594  * - 0 - Rising-edge on COUT has not been detected.
00595  * - 1 - Rising-edge on COUT has occurred.
00596  */
00597 /*@{*/
00598 #define BP_CMP_SCR_CFR       (2U)          /*!< Bit position for CMP_SCR_CFR. */
00599 #define BM_CMP_SCR_CFR       (0x04U)       /*!< Bit mask for CMP_SCR_CFR. */
00600 #define BS_CMP_SCR_CFR       (1U)          /*!< Bit field size in bits for CMP_SCR_CFR. */
00601 
00602 /*! @brief Read current value of the CMP_SCR_CFR field. */
00603 #define BR_CMP_SCR_CFR(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR)))
00604 
00605 /*! @brief Format value for bitfield CMP_SCR_CFR. */
00606 #define BF_CMP_SCR_CFR(v)    ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_CFR) & BM_CMP_SCR_CFR)
00607 
00608 /*! @brief Set the CFR field to a new value. */
00609 #define BW_CMP_SCR_CFR(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR), v))
00610 /*@}*/
00611 
00612 /*!
00613  * @name Register CMP_SCR, field IEF[3] (RW)
00614  *
00615  * Enables the CFF interrupt from the CMP. When this field is set, an interrupt
00616  * will be asserted when CFF is set.
00617  *
00618  * Values:
00619  * - 0 - Interrupt is disabled.
00620  * - 1 - Interrupt is enabled.
00621  */
00622 /*@{*/
00623 #define BP_CMP_SCR_IEF       (3U)          /*!< Bit position for CMP_SCR_IEF. */
00624 #define BM_CMP_SCR_IEF       (0x08U)       /*!< Bit mask for CMP_SCR_IEF. */
00625 #define BS_CMP_SCR_IEF       (1U)          /*!< Bit field size in bits for CMP_SCR_IEF. */
00626 
00627 /*! @brief Read current value of the CMP_SCR_IEF field. */
00628 #define BR_CMP_SCR_IEF(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF)))
00629 
00630 /*! @brief Format value for bitfield CMP_SCR_IEF. */
00631 #define BF_CMP_SCR_IEF(v)    ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_IEF) & BM_CMP_SCR_IEF)
00632 
00633 /*! @brief Set the IEF field to a new value. */
00634 #define BW_CMP_SCR_IEF(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF), v))
00635 /*@}*/
00636 
00637 /*!
00638  * @name Register CMP_SCR, field IER[4] (RW)
00639  *
00640  * Enables the CFR interrupt from the CMP. When this field is set, an interrupt
00641  * will be asserted when CFR is set.
00642  *
00643  * Values:
00644  * - 0 - Interrupt is disabled.
00645  * - 1 - Interrupt is enabled.
00646  */
00647 /*@{*/
00648 #define BP_CMP_SCR_IER       (4U)          /*!< Bit position for CMP_SCR_IER. */
00649 #define BM_CMP_SCR_IER       (0x10U)       /*!< Bit mask for CMP_SCR_IER. */
00650 #define BS_CMP_SCR_IER       (1U)          /*!< Bit field size in bits for CMP_SCR_IER. */
00651 
00652 /*! @brief Read current value of the CMP_SCR_IER field. */
00653 #define BR_CMP_SCR_IER(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER)))
00654 
00655 /*! @brief Format value for bitfield CMP_SCR_IER. */
00656 #define BF_CMP_SCR_IER(v)    ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_IER) & BM_CMP_SCR_IER)
00657 
00658 /*! @brief Set the IER field to a new value. */
00659 #define BW_CMP_SCR_IER(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER), v))
00660 /*@}*/
00661 
00662 /*!
00663  * @name Register CMP_SCR, field DMAEN[6] (RW)
00664  *
00665  * Enables the DMA transfer triggered from the CMP module. When this field is
00666  * set, a DMA request is asserted when CFR or CFF is set.
00667  *
00668  * Values:
00669  * - 0 - DMA is disabled.
00670  * - 1 - DMA is enabled.
00671  */
00672 /*@{*/
00673 #define BP_CMP_SCR_DMAEN     (6U)          /*!< Bit position for CMP_SCR_DMAEN. */
00674 #define BM_CMP_SCR_DMAEN     (0x40U)       /*!< Bit mask for CMP_SCR_DMAEN. */
00675 #define BS_CMP_SCR_DMAEN     (1U)          /*!< Bit field size in bits for CMP_SCR_DMAEN. */
00676 
00677 /*! @brief Read current value of the CMP_SCR_DMAEN field. */
00678 #define BR_CMP_SCR_DMAEN(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN)))
00679 
00680 /*! @brief Format value for bitfield CMP_SCR_DMAEN. */
00681 #define BF_CMP_SCR_DMAEN(v)  ((uint8_t)((uint8_t)(v) << BP_CMP_SCR_DMAEN) & BM_CMP_SCR_DMAEN)
00682 
00683 /*! @brief Set the DMAEN field to a new value. */
00684 #define BW_CMP_SCR_DMAEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN), v))
00685 /*@}*/
00686 
00687 /*******************************************************************************
00688  * HW_CMP_DACCR - DAC Control Register
00689  ******************************************************************************/
00690 
00691 /*!
00692  * @brief HW_CMP_DACCR - DAC Control Register (RW)
00693  *
00694  * Reset value: 0x00U
00695  */
00696 typedef union _hw_cmp_daccr
00697 {
00698     uint8_t U;
00699     struct _hw_cmp_daccr_bitfields
00700     {
00701         uint8_t VOSEL : 6;             /*!< [5:0] DAC Output Voltage Select */
00702         uint8_t VRSEL : 1;             /*!< [6] Supply Voltage Reference Source Select */
00703         uint8_t DACEN : 1;             /*!< [7] DAC Enable */
00704     } B;
00705 } hw_cmp_daccr_t;
00706 
00707 /*!
00708  * @name Constants and macros for entire CMP_DACCR register
00709  */
00710 /*@{*/
00711 #define HW_CMP_DACCR_ADDR(x)     ((x) + 0x4U)
00712 
00713 #define HW_CMP_DACCR(x)          (*(__IO hw_cmp_daccr_t *) HW_CMP_DACCR_ADDR(x))
00714 #define HW_CMP_DACCR_RD(x)       (ADDRESS_READ(hw_cmp_daccr_t, HW_CMP_DACCR_ADDR(x)))
00715 #define HW_CMP_DACCR_WR(x, v)    (ADDRESS_WRITE(hw_cmp_daccr_t, HW_CMP_DACCR_ADDR(x), v))
00716 #define HW_CMP_DACCR_SET(x, v)   (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) |  (v)))
00717 #define HW_CMP_DACCR_CLR(x, v)   (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) & ~(v)))
00718 #define HW_CMP_DACCR_TOG(x, v)   (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) ^  (v)))
00719 /*@}*/
00720 
00721 /*
00722  * Constants & macros for individual CMP_DACCR bitfields
00723  */
00724 
00725 /*!
00726  * @name Register CMP_DACCR, field VOSEL[5:0] (RW)
00727  *
00728  * Selects an output voltage from one of 64 distinct levels. DACO = (V in /64) *
00729  * (VOSEL[5:0] + 1) , so the DACO range is from V in /64 to V in .
00730  */
00731 /*@{*/
00732 #define BP_CMP_DACCR_VOSEL   (0U)          /*!< Bit position for CMP_DACCR_VOSEL. */
00733 #define BM_CMP_DACCR_VOSEL   (0x3FU)       /*!< Bit mask for CMP_DACCR_VOSEL. */
00734 #define BS_CMP_DACCR_VOSEL   (6U)          /*!< Bit field size in bits for CMP_DACCR_VOSEL. */
00735 
00736 /*! @brief Read current value of the CMP_DACCR_VOSEL field. */
00737 #define BR_CMP_DACCR_VOSEL(x) (UNION_READ(hw_cmp_daccr_t, HW_CMP_DACCR_ADDR(x), U, B.VOSEL))
00738 
00739 /*! @brief Format value for bitfield CMP_DACCR_VOSEL. */
00740 #define BF_CMP_DACCR_VOSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_VOSEL) & BM_CMP_DACCR_VOSEL)
00741 
00742 /*! @brief Set the VOSEL field to a new value. */
00743 #define BW_CMP_DACCR_VOSEL(x, v) (HW_CMP_DACCR_WR(x, (HW_CMP_DACCR_RD(x) & ~BM_CMP_DACCR_VOSEL) | BF_CMP_DACCR_VOSEL(v)))
00744 /*@}*/
00745 
00746 /*!
00747  * @name Register CMP_DACCR, field VRSEL[6] (RW)
00748  *
00749  * Values:
00750  * - 0 - V is selected as resistor ladder network supply reference V. in1 in
00751  * - 1 - V is selected as resistor ladder network supply reference V. in2 in
00752  */
00753 /*@{*/
00754 #define BP_CMP_DACCR_VRSEL   (6U)          /*!< Bit position for CMP_DACCR_VRSEL. */
00755 #define BM_CMP_DACCR_VRSEL   (0x40U)       /*!< Bit mask for CMP_DACCR_VRSEL. */
00756 #define BS_CMP_DACCR_VRSEL   (1U)          /*!< Bit field size in bits for CMP_DACCR_VRSEL. */
00757 
00758 /*! @brief Read current value of the CMP_DACCR_VRSEL field. */
00759 #define BR_CMP_DACCR_VRSEL(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL)))
00760 
00761 /*! @brief Format value for bitfield CMP_DACCR_VRSEL. */
00762 #define BF_CMP_DACCR_VRSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_VRSEL) & BM_CMP_DACCR_VRSEL)
00763 
00764 /*! @brief Set the VRSEL field to a new value. */
00765 #define BW_CMP_DACCR_VRSEL(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL), v))
00766 /*@}*/
00767 
00768 /*!
00769  * @name Register CMP_DACCR, field DACEN[7] (RW)
00770  *
00771  * Enables the DAC. When the DAC is disabled, it is powered down to conserve
00772  * power.
00773  *
00774  * Values:
00775  * - 0 - DAC is disabled.
00776  * - 1 - DAC is enabled.
00777  */
00778 /*@{*/
00779 #define BP_CMP_DACCR_DACEN   (7U)          /*!< Bit position for CMP_DACCR_DACEN. */
00780 #define BM_CMP_DACCR_DACEN   (0x80U)       /*!< Bit mask for CMP_DACCR_DACEN. */
00781 #define BS_CMP_DACCR_DACEN   (1U)          /*!< Bit field size in bits for CMP_DACCR_DACEN. */
00782 
00783 /*! @brief Read current value of the CMP_DACCR_DACEN field. */
00784 #define BR_CMP_DACCR_DACEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN)))
00785 
00786 /*! @brief Format value for bitfield CMP_DACCR_DACEN. */
00787 #define BF_CMP_DACCR_DACEN(v) ((uint8_t)((uint8_t)(v) << BP_CMP_DACCR_DACEN) & BM_CMP_DACCR_DACEN)
00788 
00789 /*! @brief Set the DACEN field to a new value. */
00790 #define BW_CMP_DACCR_DACEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN), v))
00791 /*@}*/
00792 
00793 /*******************************************************************************
00794  * HW_CMP_MUXCR - MUX Control Register
00795  ******************************************************************************/
00796 
00797 /*!
00798  * @brief HW_CMP_MUXCR - MUX Control Register (RW)
00799  *
00800  * Reset value: 0x00U
00801  */
00802 typedef union _hw_cmp_muxcr
00803 {
00804     uint8_t U;
00805     struct _hw_cmp_muxcr_bitfields
00806     {
00807         uint8_t MSEL : 3;              /*!< [2:0] Minus Input Mux Control */
00808         uint8_t PSEL : 3;              /*!< [5:3] Plus Input Mux Control */
00809         uint8_t RESERVED0 : 1;         /*!< [6]  */
00810         uint8_t PSTM : 1;              /*!< [7] Pass Through Mode Enable */
00811     } B;
00812 } hw_cmp_muxcr_t;
00813 
00814 /*!
00815  * @name Constants and macros for entire CMP_MUXCR register
00816  */
00817 /*@{*/
00818 #define HW_CMP_MUXCR_ADDR(x)     ((x) + 0x5U)
00819 
00820 #define HW_CMP_MUXCR(x)          (*(__IO hw_cmp_muxcr_t *) HW_CMP_MUXCR_ADDR(x))
00821 #define HW_CMP_MUXCR_RD(x)       (ADDRESS_READ(hw_cmp_muxcr_t, HW_CMP_MUXCR_ADDR(x)))
00822 #define HW_CMP_MUXCR_WR(x, v)    (ADDRESS_WRITE(hw_cmp_muxcr_t, HW_CMP_MUXCR_ADDR(x), v))
00823 #define HW_CMP_MUXCR_SET(x, v)   (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) |  (v)))
00824 #define HW_CMP_MUXCR_CLR(x, v)   (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) & ~(v)))
00825 #define HW_CMP_MUXCR_TOG(x, v)   (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) ^  (v)))
00826 /*@}*/
00827 
00828 /*
00829  * Constants & macros for individual CMP_MUXCR bitfields
00830  */
00831 
00832 /*!
00833  * @name Register CMP_MUXCR, field MSEL[2:0] (RW)
00834  *
00835  * Determines which input is selected for the minus input of the comparator. For
00836  * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
00837  * operation selects the same input for both muxes, the comparator automatically
00838  * shuts down to prevent itself from becoming a noise generator.
00839  *
00840  * Values:
00841  * - 000 - IN0
00842  * - 001 - IN1
00843  * - 010 - IN2
00844  * - 011 - IN3
00845  * - 100 - IN4
00846  * - 101 - IN5
00847  * - 110 - IN6
00848  * - 111 - IN7
00849  */
00850 /*@{*/
00851 #define BP_CMP_MUXCR_MSEL    (0U)          /*!< Bit position for CMP_MUXCR_MSEL. */
00852 #define BM_CMP_MUXCR_MSEL    (0x07U)       /*!< Bit mask for CMP_MUXCR_MSEL. */
00853 #define BS_CMP_MUXCR_MSEL    (3U)          /*!< Bit field size in bits for CMP_MUXCR_MSEL. */
00854 
00855 /*! @brief Read current value of the CMP_MUXCR_MSEL field. */
00856 #define BR_CMP_MUXCR_MSEL(x) (UNION_READ(hw_cmp_muxcr_t, HW_CMP_MUXCR_ADDR(x), U, B.MSEL))
00857 
00858 /*! @brief Format value for bitfield CMP_MUXCR_MSEL. */
00859 #define BF_CMP_MUXCR_MSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_MUXCR_MSEL) & BM_CMP_MUXCR_MSEL)
00860 
00861 /*! @brief Set the MSEL field to a new value. */
00862 #define BW_CMP_MUXCR_MSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_MSEL) | BF_CMP_MUXCR_MSEL(v)))
00863 /*@}*/
00864 
00865 /*!
00866  * @name Register CMP_MUXCR, field PSEL[5:3] (RW)
00867  *
00868  * Determines which input is selected for the plus input of the comparator. For
00869  * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
00870  * operation selects the same input for both muxes, the comparator automatically
00871  * shuts down to prevent itself from becoming a noise generator.
00872  *
00873  * Values:
00874  * - 000 - IN0
00875  * - 001 - IN1
00876  * - 010 - IN2
00877  * - 011 - IN3
00878  * - 100 - IN4
00879  * - 101 - IN5
00880  * - 110 - IN6
00881  * - 111 - IN7
00882  */
00883 /*@{*/
00884 #define BP_CMP_MUXCR_PSEL    (3U)          /*!< Bit position for CMP_MUXCR_PSEL. */
00885 #define BM_CMP_MUXCR_PSEL    (0x38U)       /*!< Bit mask for CMP_MUXCR_PSEL. */
00886 #define BS_CMP_MUXCR_PSEL    (3U)          /*!< Bit field size in bits for CMP_MUXCR_PSEL. */
00887 
00888 /*! @brief Read current value of the CMP_MUXCR_PSEL field. */
00889 #define BR_CMP_MUXCR_PSEL(x) (UNION_READ(hw_cmp_muxcr_t, HW_CMP_MUXCR_ADDR(x), U, B.PSEL))
00890 
00891 /*! @brief Format value for bitfield CMP_MUXCR_PSEL. */
00892 #define BF_CMP_MUXCR_PSEL(v) ((uint8_t)((uint8_t)(v) << BP_CMP_MUXCR_PSEL) & BM_CMP_MUXCR_PSEL)
00893 
00894 /*! @brief Set the PSEL field to a new value. */
00895 #define BW_CMP_MUXCR_PSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_PSEL) | BF_CMP_MUXCR_PSEL(v)))
00896 /*@}*/
00897 
00898 /*!
00899  * @name Register CMP_MUXCR, field PSTM[7] (RW)
00900  *
00901  * This bit is used to enable to MUX pass through mode. Pass through mode is
00902  * always available but for some devices this feature must be always disabled due to
00903  * the lack of package pins.
00904  *
00905  * Values:
00906  * - 0 - Pass Through Mode is disabled.
00907  * - 1 - Pass Through Mode is enabled.
00908  */
00909 /*@{*/
00910 #define BP_CMP_MUXCR_PSTM    (7U)          /*!< Bit position for CMP_MUXCR_PSTM. */
00911 #define BM_CMP_MUXCR_PSTM    (0x80U)       /*!< Bit mask for CMP_MUXCR_PSTM. */
00912 #define BS_CMP_MUXCR_PSTM    (1U)          /*!< Bit field size in bits for CMP_MUXCR_PSTM. */
00913 
00914 /*! @brief Read current value of the CMP_MUXCR_PSTM field. */
00915 #define BR_CMP_MUXCR_PSTM(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_CMP_MUXCR_ADDR(x), BP_CMP_MUXCR_PSTM)))
00916 
00917 /*! @brief Format value for bitfield CMP_MUXCR_PSTM. */
00918 #define BF_CMP_MUXCR_PSTM(v) ((uint8_t)((uint8_t)(v) << BP_CMP_MUXCR_PSTM) & BM_CMP_MUXCR_PSTM)
00919 
00920 /*! @brief Set the PSTM field to a new value. */
00921 #define BW_CMP_MUXCR_PSTM(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_CMP_MUXCR_ADDR(x), BP_CMP_MUXCR_PSTM), v))
00922 /*@}*/
00923 
00924 /*******************************************************************************
00925  * hw_cmp_t - module struct
00926  ******************************************************************************/
00927 /*!
00928  * @brief All CMP module registers.
00929  */
00930 #pragma pack(1)
00931 typedef struct _hw_cmp
00932 {
00933     __IO hw_cmp_cr0_t CR0 ;                 /*!< [0x0] CMP Control Register 0 */
00934     __IO hw_cmp_cr1_t CR1 ;                 /*!< [0x1] CMP Control Register 1 */
00935     __IO hw_cmp_fpr_t FPR ;                 /*!< [0x2] CMP Filter Period Register */
00936     __IO hw_cmp_scr_t SCR ;                 /*!< [0x3] CMP Status and Control Register */
00937     __IO hw_cmp_daccr_t DACCR ;             /*!< [0x4] DAC Control Register */
00938     __IO hw_cmp_muxcr_t MUXCR ;             /*!< [0x5] MUX Control Register */
00939 } hw_cmp_t;
00940 #pragma pack()
00941 
00942 /*! @brief Macro to access all CMP registers. */
00943 /*! @param x CMP module instance base address. */
00944 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
00945  *     use the '&' operator, like <code>&HW_CMP(CMP0_BASE)</code>. */
00946 #define HW_CMP(x)      (*(hw_cmp_t *)(x))
00947 
00948 #endif /* __HW_CMP_REGISTERS_H__ */
00949 /* EOF */