MK64F12_cau.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_CAU_REGISTERS_H__
00088 #define __HW_CAU_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 CAU
00095  *
00096  * Memory Mapped Cryptographic Acceleration Unit (MMCAU)
00097  *
00098  * Registers defined in this header file:
00099  * - HW_CAU_DIRECT0 - Direct access register 0
00100  * - HW_CAU_DIRECT1 - Direct access register 1
00101  * - HW_CAU_DIRECT2 - Direct access register 2
00102  * - HW_CAU_DIRECT3 - Direct access register 3
00103  * - HW_CAU_DIRECT4 - Direct access register 4
00104  * - HW_CAU_DIRECT5 - Direct access register 5
00105  * - HW_CAU_DIRECT6 - Direct access register 6
00106  * - HW_CAU_DIRECT7 - Direct access register 7
00107  * - HW_CAU_DIRECT8 - Direct access register 8
00108  * - HW_CAU_DIRECT9 - Direct access register 9
00109  * - HW_CAU_DIRECT10 - Direct access register 10
00110  * - HW_CAU_DIRECT11 - Direct access register 11
00111  * - HW_CAU_DIRECT12 - Direct access register 12
00112  * - HW_CAU_DIRECT13 - Direct access register 13
00113  * - HW_CAU_DIRECT14 - Direct access register 14
00114  * - HW_CAU_DIRECT15 - Direct access register 15
00115  * - HW_CAU_LDR_CASR - Status register  - Load Register command
00116  * - HW_CAU_LDR_CAA - Accumulator register - Load Register command
00117  * - HW_CAU_LDR_CA0 - General Purpose Register 0 - Load Register command
00118  * - HW_CAU_LDR_CA1 - General Purpose Register 1 - Load Register command
00119  * - HW_CAU_LDR_CA2 - General Purpose Register 2 - Load Register command
00120  * - HW_CAU_LDR_CA3 - General Purpose Register 3 - Load Register command
00121  * - HW_CAU_LDR_CA4 - General Purpose Register 4 - Load Register command
00122  * - HW_CAU_LDR_CA5 - General Purpose Register 5 - Load Register command
00123  * - HW_CAU_LDR_CA6 - General Purpose Register 6 - Load Register command
00124  * - HW_CAU_LDR_CA7 - General Purpose Register 7 - Load Register command
00125  * - HW_CAU_LDR_CA8 - General Purpose Register 8 - Load Register command
00126  * - HW_CAU_STR_CASR - Status register  - Store Register command
00127  * - HW_CAU_STR_CAA - Accumulator register - Store Register command
00128  * - HW_CAU_STR_CA0 - General Purpose Register 0 - Store Register command
00129  * - HW_CAU_STR_CA1 - General Purpose Register 1 - Store Register command
00130  * - HW_CAU_STR_CA2 - General Purpose Register 2 - Store Register command
00131  * - HW_CAU_STR_CA3 - General Purpose Register 3 - Store Register command
00132  * - HW_CAU_STR_CA4 - General Purpose Register 4 - Store Register command
00133  * - HW_CAU_STR_CA5 - General Purpose Register 5 - Store Register command
00134  * - HW_CAU_STR_CA6 - General Purpose Register 6 - Store Register command
00135  * - HW_CAU_STR_CA7 - General Purpose Register 7 - Store Register command
00136  * - HW_CAU_STR_CA8 - General Purpose Register 8 - Store Register command
00137  * - HW_CAU_ADR_CASR - Status register  - Add Register command
00138  * - HW_CAU_ADR_CAA - Accumulator register - Add to register command
00139  * - HW_CAU_ADR_CA0 - General Purpose Register 0 - Add to register command
00140  * - HW_CAU_ADR_CA1 - General Purpose Register 1 - Add to register command
00141  * - HW_CAU_ADR_CA2 - General Purpose Register 2 - Add to register command
00142  * - HW_CAU_ADR_CA3 - General Purpose Register 3 - Add to register command
00143  * - HW_CAU_ADR_CA4 - General Purpose Register 4 - Add to register command
00144  * - HW_CAU_ADR_CA5 - General Purpose Register 5 - Add to register command
00145  * - HW_CAU_ADR_CA6 - General Purpose Register 6 - Add to register command
00146  * - HW_CAU_ADR_CA7 - General Purpose Register 7 - Add to register command
00147  * - HW_CAU_ADR_CA8 - General Purpose Register 8 - Add to register command
00148  * - HW_CAU_RADR_CASR - Status register  - Reverse and Add to Register command
00149  * - HW_CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command
00150  * - HW_CAU_RADR_CA0 - General Purpose Register 0 - Reverse and Add to Register command
00151  * - HW_CAU_RADR_CA1 - General Purpose Register 1 - Reverse and Add to Register command
00152  * - HW_CAU_RADR_CA2 - General Purpose Register 2 - Reverse and Add to Register command
00153  * - HW_CAU_RADR_CA3 - General Purpose Register 3 - Reverse and Add to Register command
00154  * - HW_CAU_RADR_CA4 - General Purpose Register 4 - Reverse and Add to Register command
00155  * - HW_CAU_RADR_CA5 - General Purpose Register 5 - Reverse and Add to Register command
00156  * - HW_CAU_RADR_CA6 - General Purpose Register 6 - Reverse and Add to Register command
00157  * - HW_CAU_RADR_CA7 - General Purpose Register 7 - Reverse and Add to Register command
00158  * - HW_CAU_RADR_CA8 - General Purpose Register 8 - Reverse and Add to Register command
00159  * - HW_CAU_XOR_CASR - Status register  - Exclusive Or command
00160  * - HW_CAU_XOR_CAA - Accumulator register - Exclusive Or command
00161  * - HW_CAU_XOR_CA0 - General Purpose Register 0 - Exclusive Or command
00162  * - HW_CAU_XOR_CA1 - General Purpose Register 1 - Exclusive Or command
00163  * - HW_CAU_XOR_CA2 - General Purpose Register 2 - Exclusive Or command
00164  * - HW_CAU_XOR_CA3 - General Purpose Register 3 - Exclusive Or command
00165  * - HW_CAU_XOR_CA4 - General Purpose Register 4 - Exclusive Or command
00166  * - HW_CAU_XOR_CA5 - General Purpose Register 5 - Exclusive Or command
00167  * - HW_CAU_XOR_CA6 - General Purpose Register 6 - Exclusive Or command
00168  * - HW_CAU_XOR_CA7 - General Purpose Register 7 - Exclusive Or command
00169  * - HW_CAU_XOR_CA8 - General Purpose Register 8 - Exclusive Or command
00170  * - HW_CAU_ROTL_CASR - Status register  - Rotate Left command
00171  * - HW_CAU_ROTL_CAA - Accumulator register - Rotate Left command
00172  * - HW_CAU_ROTL_CA0 - General Purpose Register 0 - Rotate Left command
00173  * - HW_CAU_ROTL_CA1 - General Purpose Register 1 - Rotate Left command
00174  * - HW_CAU_ROTL_CA2 - General Purpose Register 2 - Rotate Left command
00175  * - HW_CAU_ROTL_CA3 - General Purpose Register 3 - Rotate Left command
00176  * - HW_CAU_ROTL_CA4 - General Purpose Register 4 - Rotate Left command
00177  * - HW_CAU_ROTL_CA5 - General Purpose Register 5 - Rotate Left command
00178  * - HW_CAU_ROTL_CA6 - General Purpose Register 6 - Rotate Left command
00179  * - HW_CAU_ROTL_CA7 - General Purpose Register 7 - Rotate Left command
00180  * - HW_CAU_ROTL_CA8 - General Purpose Register 8 - Rotate Left command
00181  * - HW_CAU_AESC_CASR - Status register  - AES Column Operation command
00182  * - HW_CAU_AESC_CAA - Accumulator register - AES Column Operation command
00183  * - HW_CAU_AESC_CA0 - General Purpose Register 0 - AES Column Operation command
00184  * - HW_CAU_AESC_CA1 - General Purpose Register 1 - AES Column Operation command
00185  * - HW_CAU_AESC_CA2 - General Purpose Register 2 - AES Column Operation command
00186  * - HW_CAU_AESC_CA3 - General Purpose Register 3 - AES Column Operation command
00187  * - HW_CAU_AESC_CA4 - General Purpose Register 4 - AES Column Operation command
00188  * - HW_CAU_AESC_CA5 - General Purpose Register 5 - AES Column Operation command
00189  * - HW_CAU_AESC_CA6 - General Purpose Register 6 - AES Column Operation command
00190  * - HW_CAU_AESC_CA7 - General Purpose Register 7 - AES Column Operation command
00191  * - HW_CAU_AESC_CA8 - General Purpose Register 8 - AES Column Operation command
00192  * - HW_CAU_AESIC_CASR - Status register  - AES Inverse Column Operation command
00193  * - HW_CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command
00194  * - HW_CAU_AESIC_CA0 - General Purpose Register 0 - AES Inverse Column Operation command
00195  * - HW_CAU_AESIC_CA1 - General Purpose Register 1 - AES Inverse Column Operation command
00196  * - HW_CAU_AESIC_CA2 - General Purpose Register 2 - AES Inverse Column Operation command
00197  * - HW_CAU_AESIC_CA3 - General Purpose Register 3 - AES Inverse Column Operation command
00198  * - HW_CAU_AESIC_CA4 - General Purpose Register 4 - AES Inverse Column Operation command
00199  * - HW_CAU_AESIC_CA5 - General Purpose Register 5 - AES Inverse Column Operation command
00200  * - HW_CAU_AESIC_CA6 - General Purpose Register 6 - AES Inverse Column Operation command
00201  * - HW_CAU_AESIC_CA7 - General Purpose Register 7 - AES Inverse Column Operation command
00202  * - HW_CAU_AESIC_CA8 - General Purpose Register 8 - AES Inverse Column Operation command
00203  *
00204  * - hw_cau_t - Struct containing all module registers.
00205  */
00206 
00207 #define HW_CAU_INSTANCE_COUNT (1U) /*!< Number of instances of the CAU module. */
00208 
00209 /*******************************************************************************
00210  * HW_CAU_DIRECT0 - Direct access register 0
00211  ******************************************************************************/
00212 
00213 /*!
00214  * @brief HW_CAU_DIRECT0 - Direct access register 0 (WO)
00215  *
00216  * Reset value: 0x00000000U
00217  */
00218 typedef union _hw_cau_direct0
00219 {
00220     uint32_t U;
00221     struct _hw_cau_direct0_bitfields
00222     {
00223         uint32_t CAU_DIRECT0b : 32;    /*!< [31:0] Direct register 0 */
00224     } B;
00225 } hw_cau_direct0_t;
00226 
00227 /*!
00228  * @name Constants and macros for entire CAU_DIRECT0 register
00229  */
00230 /*@{*/
00231 #define HW_CAU_DIRECT0_ADDR(x)   ((x) + 0x0U)
00232 
00233 #define HW_CAU_DIRECT0(x)        (*(__O hw_cau_direct0_t *) HW_CAU_DIRECT0_ADDR(x))
00234 #define HW_CAU_DIRECT0_WR(x, v)  (ADDRESS_WRITE(hw_cau_direct0_t, HW_CAU_DIRECT0_ADDR(x), v))
00235 /*@}*/
00236 
00237 /*
00238  * Constants & macros for individual CAU_DIRECT0 bitfields
00239  */
00240 
00241 /*!
00242  * @name Register CAU_DIRECT0, field CAU_DIRECT0[31:0] (WO)
00243  */
00244 /*@{*/
00245 #define BP_CAU_DIRECT0_CAU_DIRECT0 (0U)    /*!< Bit position for CAU_DIRECT0_CAU_DIRECT0. */
00246 #define BM_CAU_DIRECT0_CAU_DIRECT0 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT0_CAU_DIRECT0. */
00247 #define BS_CAU_DIRECT0_CAU_DIRECT0 (32U)   /*!< Bit field size in bits for CAU_DIRECT0_CAU_DIRECT0. */
00248 
00249 /*! @brief Format value for bitfield CAU_DIRECT0_CAU_DIRECT0. */
00250 #define BF_CAU_DIRECT0_CAU_DIRECT0(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT0_CAU_DIRECT0) & BM_CAU_DIRECT0_CAU_DIRECT0)
00251 /*@}*/
00252 
00253 /*******************************************************************************
00254  * HW_CAU_DIRECT1 - Direct access register 1
00255  ******************************************************************************/
00256 
00257 /*!
00258  * @brief HW_CAU_DIRECT1 - Direct access register 1 (WO)
00259  *
00260  * Reset value: 0x00000000U
00261  */
00262 typedef union _hw_cau_direct1
00263 {
00264     uint32_t U;
00265     struct _hw_cau_direct1_bitfields
00266     {
00267         uint32_t CAU_DIRECT1b : 32;    /*!< [31:0] Direct register 1 */
00268     } B;
00269 } hw_cau_direct1_t;
00270 
00271 /*!
00272  * @name Constants and macros for entire CAU_DIRECT1 register
00273  */
00274 /*@{*/
00275 #define HW_CAU_DIRECT1_ADDR(x)   ((x) + 0x4U)
00276 
00277 #define HW_CAU_DIRECT1(x)        (*(__O hw_cau_direct1_t *) HW_CAU_DIRECT1_ADDR(x))
00278 #define HW_CAU_DIRECT1_WR(x, v)  (ADDRESS_WRITE(hw_cau_direct1_t, HW_CAU_DIRECT1_ADDR(x), v))
00279 /*@}*/
00280 
00281 /*
00282  * Constants & macros for individual CAU_DIRECT1 bitfields
00283  */
00284 
00285 /*!
00286  * @name Register CAU_DIRECT1, field CAU_DIRECT1[31:0] (WO)
00287  */
00288 /*@{*/
00289 #define BP_CAU_DIRECT1_CAU_DIRECT1 (0U)    /*!< Bit position for CAU_DIRECT1_CAU_DIRECT1. */
00290 #define BM_CAU_DIRECT1_CAU_DIRECT1 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT1_CAU_DIRECT1. */
00291 #define BS_CAU_DIRECT1_CAU_DIRECT1 (32U)   /*!< Bit field size in bits for CAU_DIRECT1_CAU_DIRECT1. */
00292 
00293 /*! @brief Format value for bitfield CAU_DIRECT1_CAU_DIRECT1. */
00294 #define BF_CAU_DIRECT1_CAU_DIRECT1(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT1_CAU_DIRECT1) & BM_CAU_DIRECT1_CAU_DIRECT1)
00295 /*@}*/
00296 
00297 /*******************************************************************************
00298  * HW_CAU_DIRECT2 - Direct access register 2
00299  ******************************************************************************/
00300 
00301 /*!
00302  * @brief HW_CAU_DIRECT2 - Direct access register 2 (WO)
00303  *
00304  * Reset value: 0x00000000U
00305  */
00306 typedef union _hw_cau_direct2
00307 {
00308     uint32_t U;
00309     struct _hw_cau_direct2_bitfields
00310     {
00311         uint32_t CAU_DIRECT2b : 32;    /*!< [31:0] Direct register 2 */
00312     } B;
00313 } hw_cau_direct2_t;
00314 
00315 /*!
00316  * @name Constants and macros for entire CAU_DIRECT2 register
00317  */
00318 /*@{*/
00319 #define HW_CAU_DIRECT2_ADDR(x)   ((x) + 0x8U)
00320 
00321 #define HW_CAU_DIRECT2(x)        (*(__O hw_cau_direct2_t *) HW_CAU_DIRECT2_ADDR(x))
00322 #define HW_CAU_DIRECT2_WR(x, v)  (ADDRESS_WRITE(hw_cau_direct2_t, HW_CAU_DIRECT2_ADDR(x), v))
00323 /*@}*/
00324 
00325 /*
00326  * Constants & macros for individual CAU_DIRECT2 bitfields
00327  */
00328 
00329 /*!
00330  * @name Register CAU_DIRECT2, field CAU_DIRECT2[31:0] (WO)
00331  */
00332 /*@{*/
00333 #define BP_CAU_DIRECT2_CAU_DIRECT2 (0U)    /*!< Bit position for CAU_DIRECT2_CAU_DIRECT2. */
00334 #define BM_CAU_DIRECT2_CAU_DIRECT2 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT2_CAU_DIRECT2. */
00335 #define BS_CAU_DIRECT2_CAU_DIRECT2 (32U)   /*!< Bit field size in bits for CAU_DIRECT2_CAU_DIRECT2. */
00336 
00337 /*! @brief Format value for bitfield CAU_DIRECT2_CAU_DIRECT2. */
00338 #define BF_CAU_DIRECT2_CAU_DIRECT2(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT2_CAU_DIRECT2) & BM_CAU_DIRECT2_CAU_DIRECT2)
00339 /*@}*/
00340 
00341 /*******************************************************************************
00342  * HW_CAU_DIRECT3 - Direct access register 3
00343  ******************************************************************************/
00344 
00345 /*!
00346  * @brief HW_CAU_DIRECT3 - Direct access register 3 (WO)
00347  *
00348  * Reset value: 0x00000000U
00349  */
00350 typedef union _hw_cau_direct3
00351 {
00352     uint32_t U;
00353     struct _hw_cau_direct3_bitfields
00354     {
00355         uint32_t CAU_DIRECT3b : 32;    /*!< [31:0] Direct register 3 */
00356     } B;
00357 } hw_cau_direct3_t;
00358 
00359 /*!
00360  * @name Constants and macros for entire CAU_DIRECT3 register
00361  */
00362 /*@{*/
00363 #define HW_CAU_DIRECT3_ADDR(x)   ((x) + 0xCU)
00364 
00365 #define HW_CAU_DIRECT3(x)        (*(__O hw_cau_direct3_t *) HW_CAU_DIRECT3_ADDR(x))
00366 #define HW_CAU_DIRECT3_WR(x, v)  (ADDRESS_WRITE(hw_cau_direct3_t, HW_CAU_DIRECT3_ADDR(x), v))
00367 /*@}*/
00368 
00369 /*
00370  * Constants & macros for individual CAU_DIRECT3 bitfields
00371  */
00372 
00373 /*!
00374  * @name Register CAU_DIRECT3, field CAU_DIRECT3[31:0] (WO)
00375  */
00376 /*@{*/
00377 #define BP_CAU_DIRECT3_CAU_DIRECT3 (0U)    /*!< Bit position for CAU_DIRECT3_CAU_DIRECT3. */
00378 #define BM_CAU_DIRECT3_CAU_DIRECT3 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT3_CAU_DIRECT3. */
00379 #define BS_CAU_DIRECT3_CAU_DIRECT3 (32U)   /*!< Bit field size in bits for CAU_DIRECT3_CAU_DIRECT3. */
00380 
00381 /*! @brief Format value for bitfield CAU_DIRECT3_CAU_DIRECT3. */
00382 #define BF_CAU_DIRECT3_CAU_DIRECT3(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT3_CAU_DIRECT3) & BM_CAU_DIRECT3_CAU_DIRECT3)
00383 /*@}*/
00384 
00385 /*******************************************************************************
00386  * HW_CAU_DIRECT4 - Direct access register 4
00387  ******************************************************************************/
00388 
00389 /*!
00390  * @brief HW_CAU_DIRECT4 - Direct access register 4 (WO)
00391  *
00392  * Reset value: 0x00000000U
00393  */
00394 typedef union _hw_cau_direct4
00395 {
00396     uint32_t U;
00397     struct _hw_cau_direct4_bitfields
00398     {
00399         uint32_t CAU_DIRECT4b : 32;    /*!< [31:0] Direct register 4 */
00400     } B;
00401 } hw_cau_direct4_t;
00402 
00403 /*!
00404  * @name Constants and macros for entire CAU_DIRECT4 register
00405  */
00406 /*@{*/
00407 #define HW_CAU_DIRECT4_ADDR(x)   ((x) + 0x10U)
00408 
00409 #define HW_CAU_DIRECT4(x)        (*(__O hw_cau_direct4_t *) HW_CAU_DIRECT4_ADDR(x))
00410 #define HW_CAU_DIRECT4_WR(x, v)  (ADDRESS_WRITE(hw_cau_direct4_t, HW_CAU_DIRECT4_ADDR(x), v))
00411 /*@}*/
00412 
00413 /*
00414  * Constants & macros for individual CAU_DIRECT4 bitfields
00415  */
00416 
00417 /*!
00418  * @name Register CAU_DIRECT4, field CAU_DIRECT4[31:0] (WO)
00419  */
00420 /*@{*/
00421 #define BP_CAU_DIRECT4_CAU_DIRECT4 (0U)    /*!< Bit position for CAU_DIRECT4_CAU_DIRECT4. */
00422 #define BM_CAU_DIRECT4_CAU_DIRECT4 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT4_CAU_DIRECT4. */
00423 #define BS_CAU_DIRECT4_CAU_DIRECT4 (32U)   /*!< Bit field size in bits for CAU_DIRECT4_CAU_DIRECT4. */
00424 
00425 /*! @brief Format value for bitfield CAU_DIRECT4_CAU_DIRECT4. */
00426 #define BF_CAU_DIRECT4_CAU_DIRECT4(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT4_CAU_DIRECT4) & BM_CAU_DIRECT4_CAU_DIRECT4)
00427 /*@}*/
00428 
00429 /*******************************************************************************
00430  * HW_CAU_DIRECT5 - Direct access register 5
00431  ******************************************************************************/
00432 
00433 /*!
00434  * @brief HW_CAU_DIRECT5 - Direct access register 5 (WO)
00435  *
00436  * Reset value: 0x00000000U
00437  */
00438 typedef union _hw_cau_direct5
00439 {
00440     uint32_t U;
00441     struct _hw_cau_direct5_bitfields
00442     {
00443         uint32_t CAU_DIRECT5b : 32;    /*!< [31:0] Direct register 5 */
00444     } B;
00445 } hw_cau_direct5_t;
00446 
00447 /*!
00448  * @name Constants and macros for entire CAU_DIRECT5 register
00449  */
00450 /*@{*/
00451 #define HW_CAU_DIRECT5_ADDR(x)   ((x) + 0x14U)
00452 
00453 #define HW_CAU_DIRECT5(x)        (*(__O hw_cau_direct5_t *) HW_CAU_DIRECT5_ADDR(x))
00454 #define HW_CAU_DIRECT5_WR(x, v)  (ADDRESS_WRITE(hw_cau_direct5_t, HW_CAU_DIRECT5_ADDR(x), v))
00455 /*@}*/
00456 
00457 /*
00458  * Constants & macros for individual CAU_DIRECT5 bitfields
00459  */
00460 
00461 /*!
00462  * @name Register CAU_DIRECT5, field CAU_DIRECT5[31:0] (WO)
00463  */
00464 /*@{*/
00465 #define BP_CAU_DIRECT5_CAU_DIRECT5 (0U)    /*!< Bit position for CAU_DIRECT5_CAU_DIRECT5. */
00466 #define BM_CAU_DIRECT5_CAU_DIRECT5 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT5_CAU_DIRECT5. */
00467 #define BS_CAU_DIRECT5_CAU_DIRECT5 (32U)   /*!< Bit field size in bits for CAU_DIRECT5_CAU_DIRECT5. */
00468 
00469 /*! @brief Format value for bitfield CAU_DIRECT5_CAU_DIRECT5. */
00470 #define BF_CAU_DIRECT5_CAU_DIRECT5(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT5_CAU_DIRECT5) & BM_CAU_DIRECT5_CAU_DIRECT5)
00471 /*@}*/
00472 
00473 /*******************************************************************************
00474  * HW_CAU_DIRECT6 - Direct access register 6
00475  ******************************************************************************/
00476 
00477 /*!
00478  * @brief HW_CAU_DIRECT6 - Direct access register 6 (WO)
00479  *
00480  * Reset value: 0x00000000U
00481  */
00482 typedef union _hw_cau_direct6
00483 {
00484     uint32_t U;
00485     struct _hw_cau_direct6_bitfields
00486     {
00487         uint32_t CAU_DIRECT6b : 32;    /*!< [31:0] Direct register 6 */
00488     } B;
00489 } hw_cau_direct6_t;
00490 
00491 /*!
00492  * @name Constants and macros for entire CAU_DIRECT6 register
00493  */
00494 /*@{*/
00495 #define HW_CAU_DIRECT6_ADDR(x)   ((x) + 0x18U)
00496 
00497 #define HW_CAU_DIRECT6(x)        (*(__O hw_cau_direct6_t *) HW_CAU_DIRECT6_ADDR(x))
00498 #define HW_CAU_DIRECT6_WR(x, v)  (ADDRESS_WRITE(hw_cau_direct6_t, HW_CAU_DIRECT6_ADDR(x), v))
00499 /*@}*/
00500 
00501 /*
00502  * Constants & macros for individual CAU_DIRECT6 bitfields
00503  */
00504 
00505 /*!
00506  * @name Register CAU_DIRECT6, field CAU_DIRECT6[31:0] (WO)
00507  */
00508 /*@{*/
00509 #define BP_CAU_DIRECT6_CAU_DIRECT6 (0U)    /*!< Bit position for CAU_DIRECT6_CAU_DIRECT6. */
00510 #define BM_CAU_DIRECT6_CAU_DIRECT6 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT6_CAU_DIRECT6. */
00511 #define BS_CAU_DIRECT6_CAU_DIRECT6 (32U)   /*!< Bit field size in bits for CAU_DIRECT6_CAU_DIRECT6. */
00512 
00513 /*! @brief Format value for bitfield CAU_DIRECT6_CAU_DIRECT6. */
00514 #define BF_CAU_DIRECT6_CAU_DIRECT6(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT6_CAU_DIRECT6) & BM_CAU_DIRECT6_CAU_DIRECT6)
00515 /*@}*/
00516 
00517 /*******************************************************************************
00518  * HW_CAU_DIRECT7 - Direct access register 7
00519  ******************************************************************************/
00520 
00521 /*!
00522  * @brief HW_CAU_DIRECT7 - Direct access register 7 (WO)
00523  *
00524  * Reset value: 0x00000000U
00525  */
00526 typedef union _hw_cau_direct7
00527 {
00528     uint32_t U;
00529     struct _hw_cau_direct7_bitfields
00530     {
00531         uint32_t CAU_DIRECT7b : 32;    /*!< [31:0] Direct register 7 */
00532     } B;
00533 } hw_cau_direct7_t;
00534 
00535 /*!
00536  * @name Constants and macros for entire CAU_DIRECT7 register
00537  */
00538 /*@{*/
00539 #define HW_CAU_DIRECT7_ADDR(x)   ((x) + 0x1CU)
00540 
00541 #define HW_CAU_DIRECT7(x)        (*(__O hw_cau_direct7_t *) HW_CAU_DIRECT7_ADDR(x))
00542 #define HW_CAU_DIRECT7_WR(x, v)  (ADDRESS_WRITE(hw_cau_direct7_t, HW_CAU_DIRECT7_ADDR(x), v))
00543 /*@}*/
00544 
00545 /*
00546  * Constants & macros for individual CAU_DIRECT7 bitfields
00547  */
00548 
00549 /*!
00550  * @name Register CAU_DIRECT7, field CAU_DIRECT7[31:0] (WO)
00551  */
00552 /*@{*/
00553 #define BP_CAU_DIRECT7_CAU_DIRECT7 (0U)    /*!< Bit position for CAU_DIRECT7_CAU_DIRECT7. */
00554 #define BM_CAU_DIRECT7_CAU_DIRECT7 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT7_CAU_DIRECT7. */
00555 #define BS_CAU_DIRECT7_CAU_DIRECT7 (32U)   /*!< Bit field size in bits for CAU_DIRECT7_CAU_DIRECT7. */
00556 
00557 /*! @brief Format value for bitfield CAU_DIRECT7_CAU_DIRECT7. */
00558 #define BF_CAU_DIRECT7_CAU_DIRECT7(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT7_CAU_DIRECT7) & BM_CAU_DIRECT7_CAU_DIRECT7)
00559 /*@}*/
00560 
00561 /*******************************************************************************
00562  * HW_CAU_DIRECT8 - Direct access register 8
00563  ******************************************************************************/
00564 
00565 /*!
00566  * @brief HW_CAU_DIRECT8 - Direct access register 8 (WO)
00567  *
00568  * Reset value: 0x00000000U
00569  */
00570 typedef union _hw_cau_direct8
00571 {
00572     uint32_t U;
00573     struct _hw_cau_direct8_bitfields
00574     {
00575         uint32_t CAU_DIRECT8b : 32;    /*!< [31:0] Direct register 8 */
00576     } B;
00577 } hw_cau_direct8_t;
00578 
00579 /*!
00580  * @name Constants and macros for entire CAU_DIRECT8 register
00581  */
00582 /*@{*/
00583 #define HW_CAU_DIRECT8_ADDR(x)   ((x) + 0x20U)
00584 
00585 #define HW_CAU_DIRECT8(x)        (*(__O hw_cau_direct8_t *) HW_CAU_DIRECT8_ADDR(x))
00586 #define HW_CAU_DIRECT8_WR(x, v)  (ADDRESS_WRITE(hw_cau_direct8_t, HW_CAU_DIRECT8_ADDR(x), v))
00587 /*@}*/
00588 
00589 /*
00590  * Constants & macros for individual CAU_DIRECT8 bitfields
00591  */
00592 
00593 /*!
00594  * @name Register CAU_DIRECT8, field CAU_DIRECT8[31:0] (WO)
00595  */
00596 /*@{*/
00597 #define BP_CAU_DIRECT8_CAU_DIRECT8 (0U)    /*!< Bit position for CAU_DIRECT8_CAU_DIRECT8. */
00598 #define BM_CAU_DIRECT8_CAU_DIRECT8 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT8_CAU_DIRECT8. */
00599 #define BS_CAU_DIRECT8_CAU_DIRECT8 (32U)   /*!< Bit field size in bits for CAU_DIRECT8_CAU_DIRECT8. */
00600 
00601 /*! @brief Format value for bitfield CAU_DIRECT8_CAU_DIRECT8. */
00602 #define BF_CAU_DIRECT8_CAU_DIRECT8(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT8_CAU_DIRECT8) & BM_CAU_DIRECT8_CAU_DIRECT8)
00603 /*@}*/
00604 
00605 /*******************************************************************************
00606  * HW_CAU_DIRECT9 - Direct access register 9
00607  ******************************************************************************/
00608 
00609 /*!
00610  * @brief HW_CAU_DIRECT9 - Direct access register 9 (WO)
00611  *
00612  * Reset value: 0x00000000U
00613  */
00614 typedef union _hw_cau_direct9
00615 {
00616     uint32_t U;
00617     struct _hw_cau_direct9_bitfields
00618     {
00619         uint32_t CAU_DIRECT9b : 32;    /*!< [31:0] Direct register 9 */
00620     } B;
00621 } hw_cau_direct9_t;
00622 
00623 /*!
00624  * @name Constants and macros for entire CAU_DIRECT9 register
00625  */
00626 /*@{*/
00627 #define HW_CAU_DIRECT9_ADDR(x)   ((x) + 0x24U)
00628 
00629 #define HW_CAU_DIRECT9(x)        (*(__O hw_cau_direct9_t *) HW_CAU_DIRECT9_ADDR(x))
00630 #define HW_CAU_DIRECT9_WR(x, v)  (ADDRESS_WRITE(hw_cau_direct9_t, HW_CAU_DIRECT9_ADDR(x), v))
00631 /*@}*/
00632 
00633 /*
00634  * Constants & macros for individual CAU_DIRECT9 bitfields
00635  */
00636 
00637 /*!
00638  * @name Register CAU_DIRECT9, field CAU_DIRECT9[31:0] (WO)
00639  */
00640 /*@{*/
00641 #define BP_CAU_DIRECT9_CAU_DIRECT9 (0U)    /*!< Bit position for CAU_DIRECT9_CAU_DIRECT9. */
00642 #define BM_CAU_DIRECT9_CAU_DIRECT9 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT9_CAU_DIRECT9. */
00643 #define BS_CAU_DIRECT9_CAU_DIRECT9 (32U)   /*!< Bit field size in bits for CAU_DIRECT9_CAU_DIRECT9. */
00644 
00645 /*! @brief Format value for bitfield CAU_DIRECT9_CAU_DIRECT9. */
00646 #define BF_CAU_DIRECT9_CAU_DIRECT9(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT9_CAU_DIRECT9) & BM_CAU_DIRECT9_CAU_DIRECT9)
00647 /*@}*/
00648 
00649 /*******************************************************************************
00650  * HW_CAU_DIRECT10 - Direct access register 10
00651  ******************************************************************************/
00652 
00653 /*!
00654  * @brief HW_CAU_DIRECT10 - Direct access register 10 (WO)
00655  *
00656  * Reset value: 0x00000000U
00657  */
00658 typedef union _hw_cau_direct10
00659 {
00660     uint32_t U;
00661     struct _hw_cau_direct10_bitfields
00662     {
00663         uint32_t CAU_DIRECT10b : 32;   /*!< [31:0] Direct register 10 */
00664     } B;
00665 } hw_cau_direct10_t;
00666 
00667 /*!
00668  * @name Constants and macros for entire CAU_DIRECT10 register
00669  */
00670 /*@{*/
00671 #define HW_CAU_DIRECT10_ADDR(x)  ((x) + 0x28U)
00672 
00673 #define HW_CAU_DIRECT10(x)       (*(__O hw_cau_direct10_t *) HW_CAU_DIRECT10_ADDR(x))
00674 #define HW_CAU_DIRECT10_WR(x, v) (ADDRESS_WRITE(hw_cau_direct10_t, HW_CAU_DIRECT10_ADDR(x), v))
00675 /*@}*/
00676 
00677 /*
00678  * Constants & macros for individual CAU_DIRECT10 bitfields
00679  */
00680 
00681 /*!
00682  * @name Register CAU_DIRECT10, field CAU_DIRECT10[31:0] (WO)
00683  */
00684 /*@{*/
00685 #define BP_CAU_DIRECT10_CAU_DIRECT10 (0U)  /*!< Bit position for CAU_DIRECT10_CAU_DIRECT10. */
00686 #define BM_CAU_DIRECT10_CAU_DIRECT10 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT10_CAU_DIRECT10. */
00687 #define BS_CAU_DIRECT10_CAU_DIRECT10 (32U) /*!< Bit field size in bits for CAU_DIRECT10_CAU_DIRECT10. */
00688 
00689 /*! @brief Format value for bitfield CAU_DIRECT10_CAU_DIRECT10. */
00690 #define BF_CAU_DIRECT10_CAU_DIRECT10(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT10_CAU_DIRECT10) & BM_CAU_DIRECT10_CAU_DIRECT10)
00691 /*@}*/
00692 
00693 /*******************************************************************************
00694  * HW_CAU_DIRECT11 - Direct access register 11
00695  ******************************************************************************/
00696 
00697 /*!
00698  * @brief HW_CAU_DIRECT11 - Direct access register 11 (WO)
00699  *
00700  * Reset value: 0x00000000U
00701  */
00702 typedef union _hw_cau_direct11
00703 {
00704     uint32_t U;
00705     struct _hw_cau_direct11_bitfields
00706     {
00707         uint32_t CAU_DIRECT11b : 32;   /*!< [31:0] Direct register 11 */
00708     } B;
00709 } hw_cau_direct11_t;
00710 
00711 /*!
00712  * @name Constants and macros for entire CAU_DIRECT11 register
00713  */
00714 /*@{*/
00715 #define HW_CAU_DIRECT11_ADDR(x)  ((x) + 0x2CU)
00716 
00717 #define HW_CAU_DIRECT11(x)       (*(__O hw_cau_direct11_t *) HW_CAU_DIRECT11_ADDR(x))
00718 #define HW_CAU_DIRECT11_WR(x, v) (ADDRESS_WRITE(hw_cau_direct11_t, HW_CAU_DIRECT11_ADDR(x), v))
00719 /*@}*/
00720 
00721 /*
00722  * Constants & macros for individual CAU_DIRECT11 bitfields
00723  */
00724 
00725 /*!
00726  * @name Register CAU_DIRECT11, field CAU_DIRECT11[31:0] (WO)
00727  */
00728 /*@{*/
00729 #define BP_CAU_DIRECT11_CAU_DIRECT11 (0U)  /*!< Bit position for CAU_DIRECT11_CAU_DIRECT11. */
00730 #define BM_CAU_DIRECT11_CAU_DIRECT11 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT11_CAU_DIRECT11. */
00731 #define BS_CAU_DIRECT11_CAU_DIRECT11 (32U) /*!< Bit field size in bits for CAU_DIRECT11_CAU_DIRECT11. */
00732 
00733 /*! @brief Format value for bitfield CAU_DIRECT11_CAU_DIRECT11. */
00734 #define BF_CAU_DIRECT11_CAU_DIRECT11(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT11_CAU_DIRECT11) & BM_CAU_DIRECT11_CAU_DIRECT11)
00735 /*@}*/
00736 
00737 /*******************************************************************************
00738  * HW_CAU_DIRECT12 - Direct access register 12
00739  ******************************************************************************/
00740 
00741 /*!
00742  * @brief HW_CAU_DIRECT12 - Direct access register 12 (WO)
00743  *
00744  * Reset value: 0x00000000U
00745  */
00746 typedef union _hw_cau_direct12
00747 {
00748     uint32_t U;
00749     struct _hw_cau_direct12_bitfields
00750     {
00751         uint32_t CAU_DIRECT12b : 32;   /*!< [31:0] Direct register 12 */
00752     } B;
00753 } hw_cau_direct12_t;
00754 
00755 /*!
00756  * @name Constants and macros for entire CAU_DIRECT12 register
00757  */
00758 /*@{*/
00759 #define HW_CAU_DIRECT12_ADDR(x)  ((x) + 0x30U)
00760 
00761 #define HW_CAU_DIRECT12(x)       (*(__O hw_cau_direct12_t *) HW_CAU_DIRECT12_ADDR(x))
00762 #define HW_CAU_DIRECT12_WR(x, v) (ADDRESS_WRITE(hw_cau_direct12_t, HW_CAU_DIRECT12_ADDR(x), v))
00763 /*@}*/
00764 
00765 /*
00766  * Constants & macros for individual CAU_DIRECT12 bitfields
00767  */
00768 
00769 /*!
00770  * @name Register CAU_DIRECT12, field CAU_DIRECT12[31:0] (WO)
00771  */
00772 /*@{*/
00773 #define BP_CAU_DIRECT12_CAU_DIRECT12 (0U)  /*!< Bit position for CAU_DIRECT12_CAU_DIRECT12. */
00774 #define BM_CAU_DIRECT12_CAU_DIRECT12 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT12_CAU_DIRECT12. */
00775 #define BS_CAU_DIRECT12_CAU_DIRECT12 (32U) /*!< Bit field size in bits for CAU_DIRECT12_CAU_DIRECT12. */
00776 
00777 /*! @brief Format value for bitfield CAU_DIRECT12_CAU_DIRECT12. */
00778 #define BF_CAU_DIRECT12_CAU_DIRECT12(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT12_CAU_DIRECT12) & BM_CAU_DIRECT12_CAU_DIRECT12)
00779 /*@}*/
00780 
00781 /*******************************************************************************
00782  * HW_CAU_DIRECT13 - Direct access register 13
00783  ******************************************************************************/
00784 
00785 /*!
00786  * @brief HW_CAU_DIRECT13 - Direct access register 13 (WO)
00787  *
00788  * Reset value: 0x00000000U
00789  */
00790 typedef union _hw_cau_direct13
00791 {
00792     uint32_t U;
00793     struct _hw_cau_direct13_bitfields
00794     {
00795         uint32_t CAU_DIRECT13b : 32;   /*!< [31:0] Direct register 13 */
00796     } B;
00797 } hw_cau_direct13_t;
00798 
00799 /*!
00800  * @name Constants and macros for entire CAU_DIRECT13 register
00801  */
00802 /*@{*/
00803 #define HW_CAU_DIRECT13_ADDR(x)  ((x) + 0x34U)
00804 
00805 #define HW_CAU_DIRECT13(x)       (*(__O hw_cau_direct13_t *) HW_CAU_DIRECT13_ADDR(x))
00806 #define HW_CAU_DIRECT13_WR(x, v) (ADDRESS_WRITE(hw_cau_direct13_t, HW_CAU_DIRECT13_ADDR(x), v))
00807 /*@}*/
00808 
00809 /*
00810  * Constants & macros for individual CAU_DIRECT13 bitfields
00811  */
00812 
00813 /*!
00814  * @name Register CAU_DIRECT13, field CAU_DIRECT13[31:0] (WO)
00815  */
00816 /*@{*/
00817 #define BP_CAU_DIRECT13_CAU_DIRECT13 (0U)  /*!< Bit position for CAU_DIRECT13_CAU_DIRECT13. */
00818 #define BM_CAU_DIRECT13_CAU_DIRECT13 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT13_CAU_DIRECT13. */
00819 #define BS_CAU_DIRECT13_CAU_DIRECT13 (32U) /*!< Bit field size in bits for CAU_DIRECT13_CAU_DIRECT13. */
00820 
00821 /*! @brief Format value for bitfield CAU_DIRECT13_CAU_DIRECT13. */
00822 #define BF_CAU_DIRECT13_CAU_DIRECT13(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT13_CAU_DIRECT13) & BM_CAU_DIRECT13_CAU_DIRECT13)
00823 /*@}*/
00824 
00825 /*******************************************************************************
00826  * HW_CAU_DIRECT14 - Direct access register 14
00827  ******************************************************************************/
00828 
00829 /*!
00830  * @brief HW_CAU_DIRECT14 - Direct access register 14 (WO)
00831  *
00832  * Reset value: 0x00000000U
00833  */
00834 typedef union _hw_cau_direct14
00835 {
00836     uint32_t U;
00837     struct _hw_cau_direct14_bitfields
00838     {
00839         uint32_t CAU_DIRECT14b : 32;   /*!< [31:0] Direct register 14 */
00840     } B;
00841 } hw_cau_direct14_t;
00842 
00843 /*!
00844  * @name Constants and macros for entire CAU_DIRECT14 register
00845  */
00846 /*@{*/
00847 #define HW_CAU_DIRECT14_ADDR(x)  ((x) + 0x38U)
00848 
00849 #define HW_CAU_DIRECT14(x)       (*(__O hw_cau_direct14_t *) HW_CAU_DIRECT14_ADDR(x))
00850 #define HW_CAU_DIRECT14_WR(x, v) (ADDRESS_WRITE(hw_cau_direct14_t, HW_CAU_DIRECT14_ADDR(x), v))
00851 /*@}*/
00852 
00853 /*
00854  * Constants & macros for individual CAU_DIRECT14 bitfields
00855  */
00856 
00857 /*!
00858  * @name Register CAU_DIRECT14, field CAU_DIRECT14[31:0] (WO)
00859  */
00860 /*@{*/
00861 #define BP_CAU_DIRECT14_CAU_DIRECT14 (0U)  /*!< Bit position for CAU_DIRECT14_CAU_DIRECT14. */
00862 #define BM_CAU_DIRECT14_CAU_DIRECT14 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT14_CAU_DIRECT14. */
00863 #define BS_CAU_DIRECT14_CAU_DIRECT14 (32U) /*!< Bit field size in bits for CAU_DIRECT14_CAU_DIRECT14. */
00864 
00865 /*! @brief Format value for bitfield CAU_DIRECT14_CAU_DIRECT14. */
00866 #define BF_CAU_DIRECT14_CAU_DIRECT14(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT14_CAU_DIRECT14) & BM_CAU_DIRECT14_CAU_DIRECT14)
00867 /*@}*/
00868 
00869 /*******************************************************************************
00870  * HW_CAU_DIRECT15 - Direct access register 15
00871  ******************************************************************************/
00872 
00873 /*!
00874  * @brief HW_CAU_DIRECT15 - Direct access register 15 (WO)
00875  *
00876  * Reset value: 0x00000000U
00877  */
00878 typedef union _hw_cau_direct15
00879 {
00880     uint32_t U;
00881     struct _hw_cau_direct15_bitfields
00882     {
00883         uint32_t CAU_DIRECT15b : 32;   /*!< [31:0] Direct register 15 */
00884     } B;
00885 } hw_cau_direct15_t;
00886 
00887 /*!
00888  * @name Constants and macros for entire CAU_DIRECT15 register
00889  */
00890 /*@{*/
00891 #define HW_CAU_DIRECT15_ADDR(x)  ((x) + 0x3CU)
00892 
00893 #define HW_CAU_DIRECT15(x)       (*(__O hw_cau_direct15_t *) HW_CAU_DIRECT15_ADDR(x))
00894 #define HW_CAU_DIRECT15_WR(x, v) (ADDRESS_WRITE(hw_cau_direct15_t, HW_CAU_DIRECT15_ADDR(x), v))
00895 /*@}*/
00896 
00897 /*
00898  * Constants & macros for individual CAU_DIRECT15 bitfields
00899  */
00900 
00901 /*!
00902  * @name Register CAU_DIRECT15, field CAU_DIRECT15[31:0] (WO)
00903  */
00904 /*@{*/
00905 #define BP_CAU_DIRECT15_CAU_DIRECT15 (0U)  /*!< Bit position for CAU_DIRECT15_CAU_DIRECT15. */
00906 #define BM_CAU_DIRECT15_CAU_DIRECT15 (0xFFFFFFFFU) /*!< Bit mask for CAU_DIRECT15_CAU_DIRECT15. */
00907 #define BS_CAU_DIRECT15_CAU_DIRECT15 (32U) /*!< Bit field size in bits for CAU_DIRECT15_CAU_DIRECT15. */
00908 
00909 /*! @brief Format value for bitfield CAU_DIRECT15_CAU_DIRECT15. */
00910 #define BF_CAU_DIRECT15_CAU_DIRECT15(v) ((uint32_t)((uint32_t)(v) << BP_CAU_DIRECT15_CAU_DIRECT15) & BM_CAU_DIRECT15_CAU_DIRECT15)
00911 /*@}*/
00912 
00913 /*******************************************************************************
00914  * HW_CAU_LDR_CASR - Status register  - Load Register command
00915  ******************************************************************************/
00916 
00917 /*!
00918  * @brief HW_CAU_LDR_CASR - Status register  - Load Register command (WO)
00919  *
00920  * Reset value: 0x20000000U
00921  */
00922 typedef union _hw_cau_ldr_casr
00923 {
00924     uint32_t U;
00925     struct _hw_cau_ldr_casr_bitfields
00926     {
00927         uint32_t IC : 1;               /*!< [0]  */
00928         uint32_t DPE : 1;              /*!< [1]  */
00929         uint32_t RESERVED0 : 26;       /*!< [27:2]  */
00930         uint32_t VER : 4;              /*!< [31:28] CAU version */
00931     } B;
00932 } hw_cau_ldr_casr_t;
00933 
00934 /*!
00935  * @name Constants and macros for entire CAU_LDR_CASR register
00936  */
00937 /*@{*/
00938 #define HW_CAU_LDR_CASR_ADDR(x)  ((x) + 0x840U)
00939 
00940 #define HW_CAU_LDR_CASR(x)       (*(__O hw_cau_ldr_casr_t *) HW_CAU_LDR_CASR_ADDR(x))
00941 #define HW_CAU_LDR_CASR_WR(x, v) (ADDRESS_WRITE(hw_cau_ldr_casr_t, HW_CAU_LDR_CASR_ADDR(x), v))
00942 /*@}*/
00943 
00944 /*
00945  * Constants & macros for individual CAU_LDR_CASR bitfields
00946  */
00947 
00948 /*!
00949  * @name Register CAU_LDR_CASR, field IC[0] (WO)
00950  *
00951  * Values:
00952  * - 0 - No illegal commands issued
00953  * - 1 - Illegal command issued
00954  */
00955 /*@{*/
00956 #define BP_CAU_LDR_CASR_IC   (0U)          /*!< Bit position for CAU_LDR_CASR_IC. */
00957 #define BM_CAU_LDR_CASR_IC   (0x00000001U) /*!< Bit mask for CAU_LDR_CASR_IC. */
00958 #define BS_CAU_LDR_CASR_IC   (1U)          /*!< Bit field size in bits for CAU_LDR_CASR_IC. */
00959 
00960 /*! @brief Format value for bitfield CAU_LDR_CASR_IC. */
00961 #define BF_CAU_LDR_CASR_IC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CASR_IC) & BM_CAU_LDR_CASR_IC)
00962 /*@}*/
00963 
00964 /*!
00965  * @name Register CAU_LDR_CASR, field DPE[1] (WO)
00966  *
00967  * Values:
00968  * - 0 - No error detected
00969  * - 1 - DES key parity error detected
00970  */
00971 /*@{*/
00972 #define BP_CAU_LDR_CASR_DPE  (1U)          /*!< Bit position for CAU_LDR_CASR_DPE. */
00973 #define BM_CAU_LDR_CASR_DPE  (0x00000002U) /*!< Bit mask for CAU_LDR_CASR_DPE. */
00974 #define BS_CAU_LDR_CASR_DPE  (1U)          /*!< Bit field size in bits for CAU_LDR_CASR_DPE. */
00975 
00976 /*! @brief Format value for bitfield CAU_LDR_CASR_DPE. */
00977 #define BF_CAU_LDR_CASR_DPE(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CASR_DPE) & BM_CAU_LDR_CASR_DPE)
00978 /*@}*/
00979 
00980 /*!
00981  * @name Register CAU_LDR_CASR, field VER[31:28] (WO)
00982  *
00983  * Values:
00984  * - 0001 - Initial CAU version
00985  * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
00986  *     value on this device)
00987  */
00988 /*@{*/
00989 #define BP_CAU_LDR_CASR_VER  (28U)         /*!< Bit position for CAU_LDR_CASR_VER. */
00990 #define BM_CAU_LDR_CASR_VER  (0xF0000000U) /*!< Bit mask for CAU_LDR_CASR_VER. */
00991 #define BS_CAU_LDR_CASR_VER  (4U)          /*!< Bit field size in bits for CAU_LDR_CASR_VER. */
00992 
00993 /*! @brief Format value for bitfield CAU_LDR_CASR_VER. */
00994 #define BF_CAU_LDR_CASR_VER(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CASR_VER) & BM_CAU_LDR_CASR_VER)
00995 /*@}*/
00996 
00997 /*******************************************************************************
00998  * HW_CAU_LDR_CAA - Accumulator register - Load Register command
00999  ******************************************************************************/
01000 
01001 /*!
01002  * @brief HW_CAU_LDR_CAA - Accumulator register - Load Register command (WO)
01003  *
01004  * Reset value: 0x00000000U
01005  */
01006 typedef union _hw_cau_ldr_caa
01007 {
01008     uint32_t U;
01009     struct _hw_cau_ldr_caa_bitfields
01010     {
01011         uint32_t ACC : 32;             /*!< [31:0] ACC */
01012     } B;
01013 } hw_cau_ldr_caa_t;
01014 
01015 /*!
01016  * @name Constants and macros for entire CAU_LDR_CAA register
01017  */
01018 /*@{*/
01019 #define HW_CAU_LDR_CAA_ADDR(x)   ((x) + 0x844U)
01020 
01021 #define HW_CAU_LDR_CAA(x)        (*(__O hw_cau_ldr_caa_t *) HW_CAU_LDR_CAA_ADDR(x))
01022 #define HW_CAU_LDR_CAA_WR(x, v)  (ADDRESS_WRITE(hw_cau_ldr_caa_t, HW_CAU_LDR_CAA_ADDR(x), v))
01023 /*@}*/
01024 
01025 /*
01026  * Constants & macros for individual CAU_LDR_CAA bitfields
01027  */
01028 
01029 /*!
01030  * @name Register CAU_LDR_CAA, field ACC[31:0] (WO)
01031  */
01032 /*@{*/
01033 #define BP_CAU_LDR_CAA_ACC   (0U)          /*!< Bit position for CAU_LDR_CAA_ACC. */
01034 #define BM_CAU_LDR_CAA_ACC   (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CAA_ACC. */
01035 #define BS_CAU_LDR_CAA_ACC   (32U)         /*!< Bit field size in bits for CAU_LDR_CAA_ACC. */
01036 
01037 /*! @brief Format value for bitfield CAU_LDR_CAA_ACC. */
01038 #define BF_CAU_LDR_CAA_ACC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CAA_ACC) & BM_CAU_LDR_CAA_ACC)
01039 /*@}*/
01040 
01041 /*******************************************************************************
01042  * HW_CAU_LDR_CA0 - General Purpose Register 0 - Load Register command
01043  ******************************************************************************/
01044 
01045 /*!
01046  * @brief HW_CAU_LDR_CA0 - General Purpose Register 0 - Load Register command (WO)
01047  *
01048  * Reset value: 0x00000000U
01049  */
01050 typedef union _hw_cau_ldr_ca0
01051 {
01052     uint32_t U;
01053     struct _hw_cau_ldr_ca0_bitfields
01054     {
01055         uint32_t CA0 : 32;             /*!< [31:0] CA0 */
01056     } B;
01057 } hw_cau_ldr_ca0_t;
01058 
01059 /*!
01060  * @name Constants and macros for entire CAU_LDR_CA0 register
01061  */
01062 /*@{*/
01063 #define HW_CAU_LDR_CA0_ADDR(x)   ((x) + 0x848U)
01064 
01065 #define HW_CAU_LDR_CA0(x)        (*(__O hw_cau_ldr_ca0_t *) HW_CAU_LDR_CA0_ADDR(x))
01066 #define HW_CAU_LDR_CA0_WR(x, v)  (ADDRESS_WRITE(hw_cau_ldr_ca0_t, HW_CAU_LDR_CA0_ADDR(x), v))
01067 /*@}*/
01068 
01069 /*
01070  * Constants & macros for individual CAU_LDR_CA0 bitfields
01071  */
01072 
01073 /*!
01074  * @name Register CAU_LDR_CA0, field CA0[31:0] (WO)
01075  */
01076 /*@{*/
01077 #define BP_CAU_LDR_CA0_CA0   (0U)          /*!< Bit position for CAU_LDR_CA0_CA0. */
01078 #define BM_CAU_LDR_CA0_CA0   (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CA0_CA0. */
01079 #define BS_CAU_LDR_CA0_CA0   (32U)         /*!< Bit field size in bits for CAU_LDR_CA0_CA0. */
01080 
01081 /*! @brief Format value for bitfield CAU_LDR_CA0_CA0. */
01082 #define BF_CAU_LDR_CA0_CA0(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CA0_CA0) & BM_CAU_LDR_CA0_CA0)
01083 /*@}*/
01084 
01085 /*******************************************************************************
01086  * HW_CAU_LDR_CA1 - General Purpose Register 1 - Load Register command
01087  ******************************************************************************/
01088 
01089 /*!
01090  * @brief HW_CAU_LDR_CA1 - General Purpose Register 1 - Load Register command (WO)
01091  *
01092  * Reset value: 0x00000000U
01093  */
01094 typedef union _hw_cau_ldr_ca1
01095 {
01096     uint32_t U;
01097     struct _hw_cau_ldr_ca1_bitfields
01098     {
01099         uint32_t CA1 : 32;             /*!< [31:0] CA1 */
01100     } B;
01101 } hw_cau_ldr_ca1_t;
01102 
01103 /*!
01104  * @name Constants and macros for entire CAU_LDR_CA1 register
01105  */
01106 /*@{*/
01107 #define HW_CAU_LDR_CA1_ADDR(x)   ((x) + 0x84CU)
01108 
01109 #define HW_CAU_LDR_CA1(x)        (*(__O hw_cau_ldr_ca1_t *) HW_CAU_LDR_CA1_ADDR(x))
01110 #define HW_CAU_LDR_CA1_WR(x, v)  (ADDRESS_WRITE(hw_cau_ldr_ca1_t, HW_CAU_LDR_CA1_ADDR(x), v))
01111 /*@}*/
01112 
01113 /*
01114  * Constants & macros for individual CAU_LDR_CA1 bitfields
01115  */
01116 
01117 /*!
01118  * @name Register CAU_LDR_CA1, field CA1[31:0] (WO)
01119  */
01120 /*@{*/
01121 #define BP_CAU_LDR_CA1_CA1   (0U)          /*!< Bit position for CAU_LDR_CA1_CA1. */
01122 #define BM_CAU_LDR_CA1_CA1   (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CA1_CA1. */
01123 #define BS_CAU_LDR_CA1_CA1   (32U)         /*!< Bit field size in bits for CAU_LDR_CA1_CA1. */
01124 
01125 /*! @brief Format value for bitfield CAU_LDR_CA1_CA1. */
01126 #define BF_CAU_LDR_CA1_CA1(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CA1_CA1) & BM_CAU_LDR_CA1_CA1)
01127 /*@}*/
01128 
01129 /*******************************************************************************
01130  * HW_CAU_LDR_CA2 - General Purpose Register 2 - Load Register command
01131  ******************************************************************************/
01132 
01133 /*!
01134  * @brief HW_CAU_LDR_CA2 - General Purpose Register 2 - Load Register command (WO)
01135  *
01136  * Reset value: 0x00000000U
01137  */
01138 typedef union _hw_cau_ldr_ca2
01139 {
01140     uint32_t U;
01141     struct _hw_cau_ldr_ca2_bitfields
01142     {
01143         uint32_t CA2 : 32;             /*!< [31:0] CA2 */
01144     } B;
01145 } hw_cau_ldr_ca2_t;
01146 
01147 /*!
01148  * @name Constants and macros for entire CAU_LDR_CA2 register
01149  */
01150 /*@{*/
01151 #define HW_CAU_LDR_CA2_ADDR(x)   ((x) + 0x850U)
01152 
01153 #define HW_CAU_LDR_CA2(x)        (*(__O hw_cau_ldr_ca2_t *) HW_CAU_LDR_CA2_ADDR(x))
01154 #define HW_CAU_LDR_CA2_WR(x, v)  (ADDRESS_WRITE(hw_cau_ldr_ca2_t, HW_CAU_LDR_CA2_ADDR(x), v))
01155 /*@}*/
01156 
01157 /*
01158  * Constants & macros for individual CAU_LDR_CA2 bitfields
01159  */
01160 
01161 /*!
01162  * @name Register CAU_LDR_CA2, field CA2[31:0] (WO)
01163  */
01164 /*@{*/
01165 #define BP_CAU_LDR_CA2_CA2   (0U)          /*!< Bit position for CAU_LDR_CA2_CA2. */
01166 #define BM_CAU_LDR_CA2_CA2   (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CA2_CA2. */
01167 #define BS_CAU_LDR_CA2_CA2   (32U)         /*!< Bit field size in bits for CAU_LDR_CA2_CA2. */
01168 
01169 /*! @brief Format value for bitfield CAU_LDR_CA2_CA2. */
01170 #define BF_CAU_LDR_CA2_CA2(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CA2_CA2) & BM_CAU_LDR_CA2_CA2)
01171 /*@}*/
01172 
01173 /*******************************************************************************
01174  * HW_CAU_LDR_CA3 - General Purpose Register 3 - Load Register command
01175  ******************************************************************************/
01176 
01177 /*!
01178  * @brief HW_CAU_LDR_CA3 - General Purpose Register 3 - Load Register command (WO)
01179  *
01180  * Reset value: 0x00000000U
01181  */
01182 typedef union _hw_cau_ldr_ca3
01183 {
01184     uint32_t U;
01185     struct _hw_cau_ldr_ca3_bitfields
01186     {
01187         uint32_t CA3 : 32;             /*!< [31:0] CA3 */
01188     } B;
01189 } hw_cau_ldr_ca3_t;
01190 
01191 /*!
01192  * @name Constants and macros for entire CAU_LDR_CA3 register
01193  */
01194 /*@{*/
01195 #define HW_CAU_LDR_CA3_ADDR(x)   ((x) + 0x854U)
01196 
01197 #define HW_CAU_LDR_CA3(x)        (*(__O hw_cau_ldr_ca3_t *) HW_CAU_LDR_CA3_ADDR(x))
01198 #define HW_CAU_LDR_CA3_WR(x, v)  (ADDRESS_WRITE(hw_cau_ldr_ca3_t, HW_CAU_LDR_CA3_ADDR(x), v))
01199 /*@}*/
01200 
01201 /*
01202  * Constants & macros for individual CAU_LDR_CA3 bitfields
01203  */
01204 
01205 /*!
01206  * @name Register CAU_LDR_CA3, field CA3[31:0] (WO)
01207  */
01208 /*@{*/
01209 #define BP_CAU_LDR_CA3_CA3   (0U)          /*!< Bit position for CAU_LDR_CA3_CA3. */
01210 #define BM_CAU_LDR_CA3_CA3   (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CA3_CA3. */
01211 #define BS_CAU_LDR_CA3_CA3   (32U)         /*!< Bit field size in bits for CAU_LDR_CA3_CA3. */
01212 
01213 /*! @brief Format value for bitfield CAU_LDR_CA3_CA3. */
01214 #define BF_CAU_LDR_CA3_CA3(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CA3_CA3) & BM_CAU_LDR_CA3_CA3)
01215 /*@}*/
01216 
01217 /*******************************************************************************
01218  * HW_CAU_LDR_CA4 - General Purpose Register 4 - Load Register command
01219  ******************************************************************************/
01220 
01221 /*!
01222  * @brief HW_CAU_LDR_CA4 - General Purpose Register 4 - Load Register command (WO)
01223  *
01224  * Reset value: 0x00000000U
01225  */
01226 typedef union _hw_cau_ldr_ca4
01227 {
01228     uint32_t U;
01229     struct _hw_cau_ldr_ca4_bitfields
01230     {
01231         uint32_t CA4 : 32;             /*!< [31:0] CA4 */
01232     } B;
01233 } hw_cau_ldr_ca4_t;
01234 
01235 /*!
01236  * @name Constants and macros for entire CAU_LDR_CA4 register
01237  */
01238 /*@{*/
01239 #define HW_CAU_LDR_CA4_ADDR(x)   ((x) + 0x858U)
01240 
01241 #define HW_CAU_LDR_CA4(x)        (*(__O hw_cau_ldr_ca4_t *) HW_CAU_LDR_CA4_ADDR(x))
01242 #define HW_CAU_LDR_CA4_WR(x, v)  (ADDRESS_WRITE(hw_cau_ldr_ca4_t, HW_CAU_LDR_CA4_ADDR(x), v))
01243 /*@}*/
01244 
01245 /*
01246  * Constants & macros for individual CAU_LDR_CA4 bitfields
01247  */
01248 
01249 /*!
01250  * @name Register CAU_LDR_CA4, field CA4[31:0] (WO)
01251  */
01252 /*@{*/
01253 #define BP_CAU_LDR_CA4_CA4   (0U)          /*!< Bit position for CAU_LDR_CA4_CA4. */
01254 #define BM_CAU_LDR_CA4_CA4   (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CA4_CA4. */
01255 #define BS_CAU_LDR_CA4_CA4   (32U)         /*!< Bit field size in bits for CAU_LDR_CA4_CA4. */
01256 
01257 /*! @brief Format value for bitfield CAU_LDR_CA4_CA4. */
01258 #define BF_CAU_LDR_CA4_CA4(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CA4_CA4) & BM_CAU_LDR_CA4_CA4)
01259 /*@}*/
01260 
01261 /*******************************************************************************
01262  * HW_CAU_LDR_CA5 - General Purpose Register 5 - Load Register command
01263  ******************************************************************************/
01264 
01265 /*!
01266  * @brief HW_CAU_LDR_CA5 - General Purpose Register 5 - Load Register command (WO)
01267  *
01268  * Reset value: 0x00000000U
01269  */
01270 typedef union _hw_cau_ldr_ca5
01271 {
01272     uint32_t U;
01273     struct _hw_cau_ldr_ca5_bitfields
01274     {
01275         uint32_t CA5 : 32;             /*!< [31:0] CA5 */
01276     } B;
01277 } hw_cau_ldr_ca5_t;
01278 
01279 /*!
01280  * @name Constants and macros for entire CAU_LDR_CA5 register
01281  */
01282 /*@{*/
01283 #define HW_CAU_LDR_CA5_ADDR(x)   ((x) + 0x85CU)
01284 
01285 #define HW_CAU_LDR_CA5(x)        (*(__O hw_cau_ldr_ca5_t *) HW_CAU_LDR_CA5_ADDR(x))
01286 #define HW_CAU_LDR_CA5_WR(x, v)  (ADDRESS_WRITE(hw_cau_ldr_ca5_t, HW_CAU_LDR_CA5_ADDR(x), v))
01287 /*@}*/
01288 
01289 /*
01290  * Constants & macros for individual CAU_LDR_CA5 bitfields
01291  */
01292 
01293 /*!
01294  * @name Register CAU_LDR_CA5, field CA5[31:0] (WO)
01295  */
01296 /*@{*/
01297 #define BP_CAU_LDR_CA5_CA5   (0U)          /*!< Bit position for CAU_LDR_CA5_CA5. */
01298 #define BM_CAU_LDR_CA5_CA5   (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CA5_CA5. */
01299 #define BS_CAU_LDR_CA5_CA5   (32U)         /*!< Bit field size in bits for CAU_LDR_CA5_CA5. */
01300 
01301 /*! @brief Format value for bitfield CAU_LDR_CA5_CA5. */
01302 #define BF_CAU_LDR_CA5_CA5(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CA5_CA5) & BM_CAU_LDR_CA5_CA5)
01303 /*@}*/
01304 
01305 /*******************************************************************************
01306  * HW_CAU_LDR_CA6 - General Purpose Register 6 - Load Register command
01307  ******************************************************************************/
01308 
01309 /*!
01310  * @brief HW_CAU_LDR_CA6 - General Purpose Register 6 - Load Register command (WO)
01311  *
01312  * Reset value: 0x00000000U
01313  */
01314 typedef union _hw_cau_ldr_ca6
01315 {
01316     uint32_t U;
01317     struct _hw_cau_ldr_ca6_bitfields
01318     {
01319         uint32_t CA6 : 32;             /*!< [31:0] CA6 */
01320     } B;
01321 } hw_cau_ldr_ca6_t;
01322 
01323 /*!
01324  * @name Constants and macros for entire CAU_LDR_CA6 register
01325  */
01326 /*@{*/
01327 #define HW_CAU_LDR_CA6_ADDR(x)   ((x) + 0x860U)
01328 
01329 #define HW_CAU_LDR_CA6(x)        (*(__O hw_cau_ldr_ca6_t *) HW_CAU_LDR_CA6_ADDR(x))
01330 #define HW_CAU_LDR_CA6_WR(x, v)  (ADDRESS_WRITE(hw_cau_ldr_ca6_t, HW_CAU_LDR_CA6_ADDR(x), v))
01331 /*@}*/
01332 
01333 /*
01334  * Constants & macros for individual CAU_LDR_CA6 bitfields
01335  */
01336 
01337 /*!
01338  * @name Register CAU_LDR_CA6, field CA6[31:0] (WO)
01339  */
01340 /*@{*/
01341 #define BP_CAU_LDR_CA6_CA6   (0U)          /*!< Bit position for CAU_LDR_CA6_CA6. */
01342 #define BM_CAU_LDR_CA6_CA6   (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CA6_CA6. */
01343 #define BS_CAU_LDR_CA6_CA6   (32U)         /*!< Bit field size in bits for CAU_LDR_CA6_CA6. */
01344 
01345 /*! @brief Format value for bitfield CAU_LDR_CA6_CA6. */
01346 #define BF_CAU_LDR_CA6_CA6(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CA6_CA6) & BM_CAU_LDR_CA6_CA6)
01347 /*@}*/
01348 
01349 /*******************************************************************************
01350  * HW_CAU_LDR_CA7 - General Purpose Register 7 - Load Register command
01351  ******************************************************************************/
01352 
01353 /*!
01354  * @brief HW_CAU_LDR_CA7 - General Purpose Register 7 - Load Register command (WO)
01355  *
01356  * Reset value: 0x00000000U
01357  */
01358 typedef union _hw_cau_ldr_ca7
01359 {
01360     uint32_t U;
01361     struct _hw_cau_ldr_ca7_bitfields
01362     {
01363         uint32_t CA7 : 32;             /*!< [31:0] CA7 */
01364     } B;
01365 } hw_cau_ldr_ca7_t;
01366 
01367 /*!
01368  * @name Constants and macros for entire CAU_LDR_CA7 register
01369  */
01370 /*@{*/
01371 #define HW_CAU_LDR_CA7_ADDR(x)   ((x) + 0x864U)
01372 
01373 #define HW_CAU_LDR_CA7(x)        (*(__O hw_cau_ldr_ca7_t *) HW_CAU_LDR_CA7_ADDR(x))
01374 #define HW_CAU_LDR_CA7_WR(x, v)  (ADDRESS_WRITE(hw_cau_ldr_ca7_t, HW_CAU_LDR_CA7_ADDR(x), v))
01375 /*@}*/
01376 
01377 /*
01378  * Constants & macros for individual CAU_LDR_CA7 bitfields
01379  */
01380 
01381 /*!
01382  * @name Register CAU_LDR_CA7, field CA7[31:0] (WO)
01383  */
01384 /*@{*/
01385 #define BP_CAU_LDR_CA7_CA7   (0U)          /*!< Bit position for CAU_LDR_CA7_CA7. */
01386 #define BM_CAU_LDR_CA7_CA7   (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CA7_CA7. */
01387 #define BS_CAU_LDR_CA7_CA7   (32U)         /*!< Bit field size in bits for CAU_LDR_CA7_CA7. */
01388 
01389 /*! @brief Format value for bitfield CAU_LDR_CA7_CA7. */
01390 #define BF_CAU_LDR_CA7_CA7(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CA7_CA7) & BM_CAU_LDR_CA7_CA7)
01391 /*@}*/
01392 
01393 /*******************************************************************************
01394  * HW_CAU_LDR_CA8 - General Purpose Register 8 - Load Register command
01395  ******************************************************************************/
01396 
01397 /*!
01398  * @brief HW_CAU_LDR_CA8 - General Purpose Register 8 - Load Register command (WO)
01399  *
01400  * Reset value: 0x00000000U
01401  */
01402 typedef union _hw_cau_ldr_ca8
01403 {
01404     uint32_t U;
01405     struct _hw_cau_ldr_ca8_bitfields
01406     {
01407         uint32_t CA8 : 32;             /*!< [31:0] CA8 */
01408     } B;
01409 } hw_cau_ldr_ca8_t;
01410 
01411 /*!
01412  * @name Constants and macros for entire CAU_LDR_CA8 register
01413  */
01414 /*@{*/
01415 #define HW_CAU_LDR_CA8_ADDR(x)   ((x) + 0x868U)
01416 
01417 #define HW_CAU_LDR_CA8(x)        (*(__O hw_cau_ldr_ca8_t *) HW_CAU_LDR_CA8_ADDR(x))
01418 #define HW_CAU_LDR_CA8_WR(x, v)  (ADDRESS_WRITE(hw_cau_ldr_ca8_t, HW_CAU_LDR_CA8_ADDR(x), v))
01419 /*@}*/
01420 
01421 /*
01422  * Constants & macros for individual CAU_LDR_CA8 bitfields
01423  */
01424 
01425 /*!
01426  * @name Register CAU_LDR_CA8, field CA8[31:0] (WO)
01427  */
01428 /*@{*/
01429 #define BP_CAU_LDR_CA8_CA8   (0U)          /*!< Bit position for CAU_LDR_CA8_CA8. */
01430 #define BM_CAU_LDR_CA8_CA8   (0xFFFFFFFFU) /*!< Bit mask for CAU_LDR_CA8_CA8. */
01431 #define BS_CAU_LDR_CA8_CA8   (32U)         /*!< Bit field size in bits for CAU_LDR_CA8_CA8. */
01432 
01433 /*! @brief Format value for bitfield CAU_LDR_CA8_CA8. */
01434 #define BF_CAU_LDR_CA8_CA8(v) ((uint32_t)((uint32_t)(v) << BP_CAU_LDR_CA8_CA8) & BM_CAU_LDR_CA8_CA8)
01435 /*@}*/
01436 
01437 /*******************************************************************************
01438  * HW_CAU_STR_CASR - Status register  - Store Register command
01439  ******************************************************************************/
01440 
01441 /*!
01442  * @brief HW_CAU_STR_CASR - Status register  - Store Register command (RO)
01443  *
01444  * Reset value: 0x20000000U
01445  */
01446 typedef union _hw_cau_str_casr
01447 {
01448     uint32_t U;
01449     struct _hw_cau_str_casr_bitfields
01450     {
01451         uint32_t IC : 1;               /*!< [0]  */
01452         uint32_t DPE : 1;              /*!< [1]  */
01453         uint32_t RESERVED0 : 26;       /*!< [27:2]  */
01454         uint32_t VER : 4;              /*!< [31:28] CAU version */
01455     } B;
01456 } hw_cau_str_casr_t;
01457 
01458 /*!
01459  * @name Constants and macros for entire CAU_STR_CASR register
01460  */
01461 /*@{*/
01462 #define HW_CAU_STR_CASR_ADDR(x)  ((x) + 0x880U)
01463 
01464 #define HW_CAU_STR_CASR(x)       (*(__I hw_cau_str_casr_t *) HW_CAU_STR_CASR_ADDR(x))
01465 #define HW_CAU_STR_CASR_RD(x)    (ADDRESS_READ(hw_cau_str_casr_t, HW_CAU_STR_CASR_ADDR(x)))
01466 /*@}*/
01467 
01468 /*
01469  * Constants & macros for individual CAU_STR_CASR bitfields
01470  */
01471 
01472 /*!
01473  * @name Register CAU_STR_CASR, field IC[0] (RO)
01474  *
01475  * Values:
01476  * - 0 - No illegal commands issued
01477  * - 1 - Illegal command issued
01478  */
01479 /*@{*/
01480 #define BP_CAU_STR_CASR_IC   (0U)          /*!< Bit position for CAU_STR_CASR_IC. */
01481 #define BM_CAU_STR_CASR_IC   (0x00000001U) /*!< Bit mask for CAU_STR_CASR_IC. */
01482 #define BS_CAU_STR_CASR_IC   (1U)          /*!< Bit field size in bits for CAU_STR_CASR_IC. */
01483 
01484 /*! @brief Read current value of the CAU_STR_CASR_IC field. */
01485 #define BR_CAU_STR_CASR_IC(x) (UNION_READ(hw_cau_str_casr_t, HW_CAU_STR_CASR_ADDR(x), U, B.IC))
01486 /*@}*/
01487 
01488 /*!
01489  * @name Register CAU_STR_CASR, field DPE[1] (RO)
01490  *
01491  * Values:
01492  * - 0 - No error detected
01493  * - 1 - DES key parity error detected
01494  */
01495 /*@{*/
01496 #define BP_CAU_STR_CASR_DPE  (1U)          /*!< Bit position for CAU_STR_CASR_DPE. */
01497 #define BM_CAU_STR_CASR_DPE  (0x00000002U) /*!< Bit mask for CAU_STR_CASR_DPE. */
01498 #define BS_CAU_STR_CASR_DPE  (1U)          /*!< Bit field size in bits for CAU_STR_CASR_DPE. */
01499 
01500 /*! @brief Read current value of the CAU_STR_CASR_DPE field. */
01501 #define BR_CAU_STR_CASR_DPE(x) (UNION_READ(hw_cau_str_casr_t, HW_CAU_STR_CASR_ADDR(x), U, B.DPE))
01502 /*@}*/
01503 
01504 /*!
01505  * @name Register CAU_STR_CASR, field VER[31:28] (RO)
01506  *
01507  * Values:
01508  * - 0001 - Initial CAU version
01509  * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
01510  *     value on this device)
01511  */
01512 /*@{*/
01513 #define BP_CAU_STR_CASR_VER  (28U)         /*!< Bit position for CAU_STR_CASR_VER. */
01514 #define BM_CAU_STR_CASR_VER  (0xF0000000U) /*!< Bit mask for CAU_STR_CASR_VER. */
01515 #define BS_CAU_STR_CASR_VER  (4U)          /*!< Bit field size in bits for CAU_STR_CASR_VER. */
01516 
01517 /*! @brief Read current value of the CAU_STR_CASR_VER field. */
01518 #define BR_CAU_STR_CASR_VER(x) (UNION_READ(hw_cau_str_casr_t, HW_CAU_STR_CASR_ADDR(x), U, B.VER))
01519 /*@}*/
01520 
01521 /*******************************************************************************
01522  * HW_CAU_STR_CAA - Accumulator register - Store Register command
01523  ******************************************************************************/
01524 
01525 /*!
01526  * @brief HW_CAU_STR_CAA - Accumulator register - Store Register command (RO)
01527  *
01528  * Reset value: 0x00000000U
01529  */
01530 typedef union _hw_cau_str_caa
01531 {
01532     uint32_t U;
01533     struct _hw_cau_str_caa_bitfields
01534     {
01535         uint32_t ACC : 32;             /*!< [31:0] ACC */
01536     } B;
01537 } hw_cau_str_caa_t;
01538 
01539 /*!
01540  * @name Constants and macros for entire CAU_STR_CAA register
01541  */
01542 /*@{*/
01543 #define HW_CAU_STR_CAA_ADDR(x)   ((x) + 0x884U)
01544 
01545 #define HW_CAU_STR_CAA(x)        (*(__I hw_cau_str_caa_t *) HW_CAU_STR_CAA_ADDR(x))
01546 #define HW_CAU_STR_CAA_RD(x)     (ADDRESS_READ(hw_cau_str_caa_t, HW_CAU_STR_CAA_ADDR(x)))
01547 /*@}*/
01548 
01549 /*
01550  * Constants & macros for individual CAU_STR_CAA bitfields
01551  */
01552 
01553 /*!
01554  * @name Register CAU_STR_CAA, field ACC[31:0] (RO)
01555  */
01556 /*@{*/
01557 #define BP_CAU_STR_CAA_ACC   (0U)          /*!< Bit position for CAU_STR_CAA_ACC. */
01558 #define BM_CAU_STR_CAA_ACC   (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CAA_ACC. */
01559 #define BS_CAU_STR_CAA_ACC   (32U)         /*!< Bit field size in bits for CAU_STR_CAA_ACC. */
01560 
01561 /*! @brief Read current value of the CAU_STR_CAA_ACC field. */
01562 #define BR_CAU_STR_CAA_ACC(x) (HW_CAU_STR_CAA(x).U)
01563 /*@}*/
01564 
01565 /*******************************************************************************
01566  * HW_CAU_STR_CA0 - General Purpose Register 0 - Store Register command
01567  ******************************************************************************/
01568 
01569 /*!
01570  * @brief HW_CAU_STR_CA0 - General Purpose Register 0 - Store Register command (RO)
01571  *
01572  * Reset value: 0x00000000U
01573  */
01574 typedef union _hw_cau_str_ca0
01575 {
01576     uint32_t U;
01577     struct _hw_cau_str_ca0_bitfields
01578     {
01579         uint32_t CA0 : 32;             /*!< [31:0] CA0 */
01580     } B;
01581 } hw_cau_str_ca0_t;
01582 
01583 /*!
01584  * @name Constants and macros for entire CAU_STR_CA0 register
01585  */
01586 /*@{*/
01587 #define HW_CAU_STR_CA0_ADDR(x)   ((x) + 0x888U)
01588 
01589 #define HW_CAU_STR_CA0(x)        (*(__I hw_cau_str_ca0_t *) HW_CAU_STR_CA0_ADDR(x))
01590 #define HW_CAU_STR_CA0_RD(x)     (ADDRESS_READ(hw_cau_str_ca0_t, HW_CAU_STR_CA0_ADDR(x)))
01591 /*@}*/
01592 
01593 /*
01594  * Constants & macros for individual CAU_STR_CA0 bitfields
01595  */
01596 
01597 /*!
01598  * @name Register CAU_STR_CA0, field CA0[31:0] (RO)
01599  */
01600 /*@{*/
01601 #define BP_CAU_STR_CA0_CA0   (0U)          /*!< Bit position for CAU_STR_CA0_CA0. */
01602 #define BM_CAU_STR_CA0_CA0   (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CA0_CA0. */
01603 #define BS_CAU_STR_CA0_CA0   (32U)         /*!< Bit field size in bits for CAU_STR_CA0_CA0. */
01604 
01605 /*! @brief Read current value of the CAU_STR_CA0_CA0 field. */
01606 #define BR_CAU_STR_CA0_CA0(x) (HW_CAU_STR_CA0(x).U)
01607 /*@}*/
01608 
01609 /*******************************************************************************
01610  * HW_CAU_STR_CA1 - General Purpose Register 1 - Store Register command
01611  ******************************************************************************/
01612 
01613 /*!
01614  * @brief HW_CAU_STR_CA1 - General Purpose Register 1 - Store Register command (RO)
01615  *
01616  * Reset value: 0x00000000U
01617  */
01618 typedef union _hw_cau_str_ca1
01619 {
01620     uint32_t U;
01621     struct _hw_cau_str_ca1_bitfields
01622     {
01623         uint32_t CA1 : 32;             /*!< [31:0] CA1 */
01624     } B;
01625 } hw_cau_str_ca1_t;
01626 
01627 /*!
01628  * @name Constants and macros for entire CAU_STR_CA1 register
01629  */
01630 /*@{*/
01631 #define HW_CAU_STR_CA1_ADDR(x)   ((x) + 0x88CU)
01632 
01633 #define HW_CAU_STR_CA1(x)        (*(__I hw_cau_str_ca1_t *) HW_CAU_STR_CA1_ADDR(x))
01634 #define HW_CAU_STR_CA1_RD(x)     (ADDRESS_READ(hw_cau_str_ca1_t, HW_CAU_STR_CA1_ADDR(x)))
01635 /*@}*/
01636 
01637 /*
01638  * Constants & macros for individual CAU_STR_CA1 bitfields
01639  */
01640 
01641 /*!
01642  * @name Register CAU_STR_CA1, field CA1[31:0] (RO)
01643  */
01644 /*@{*/
01645 #define BP_CAU_STR_CA1_CA1   (0U)          /*!< Bit position for CAU_STR_CA1_CA1. */
01646 #define BM_CAU_STR_CA1_CA1   (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CA1_CA1. */
01647 #define BS_CAU_STR_CA1_CA1   (32U)         /*!< Bit field size in bits for CAU_STR_CA1_CA1. */
01648 
01649 /*! @brief Read current value of the CAU_STR_CA1_CA1 field. */
01650 #define BR_CAU_STR_CA1_CA1(x) (HW_CAU_STR_CA1(x).U)
01651 /*@}*/
01652 
01653 /*******************************************************************************
01654  * HW_CAU_STR_CA2 - General Purpose Register 2 - Store Register command
01655  ******************************************************************************/
01656 
01657 /*!
01658  * @brief HW_CAU_STR_CA2 - General Purpose Register 2 - Store Register command (RO)
01659  *
01660  * Reset value: 0x00000000U
01661  */
01662 typedef union _hw_cau_str_ca2
01663 {
01664     uint32_t U;
01665     struct _hw_cau_str_ca2_bitfields
01666     {
01667         uint32_t CA2 : 32;             /*!< [31:0] CA2 */
01668     } B;
01669 } hw_cau_str_ca2_t;
01670 
01671 /*!
01672  * @name Constants and macros for entire CAU_STR_CA2 register
01673  */
01674 /*@{*/
01675 #define HW_CAU_STR_CA2_ADDR(x)   ((x) + 0x890U)
01676 
01677 #define HW_CAU_STR_CA2(x)        (*(__I hw_cau_str_ca2_t *) HW_CAU_STR_CA2_ADDR(x))
01678 #define HW_CAU_STR_CA2_RD(x)     (ADDRESS_READ(hw_cau_str_ca2_t, HW_CAU_STR_CA2_ADDR(x)))
01679 /*@}*/
01680 
01681 /*
01682  * Constants & macros for individual CAU_STR_CA2 bitfields
01683  */
01684 
01685 /*!
01686  * @name Register CAU_STR_CA2, field CA2[31:0] (RO)
01687  */
01688 /*@{*/
01689 #define BP_CAU_STR_CA2_CA2   (0U)          /*!< Bit position for CAU_STR_CA2_CA2. */
01690 #define BM_CAU_STR_CA2_CA2   (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CA2_CA2. */
01691 #define BS_CAU_STR_CA2_CA2   (32U)         /*!< Bit field size in bits for CAU_STR_CA2_CA2. */
01692 
01693 /*! @brief Read current value of the CAU_STR_CA2_CA2 field. */
01694 #define BR_CAU_STR_CA2_CA2(x) (HW_CAU_STR_CA2(x).U)
01695 /*@}*/
01696 
01697 /*******************************************************************************
01698  * HW_CAU_STR_CA3 - General Purpose Register 3 - Store Register command
01699  ******************************************************************************/
01700 
01701 /*!
01702  * @brief HW_CAU_STR_CA3 - General Purpose Register 3 - Store Register command (RO)
01703  *
01704  * Reset value: 0x00000000U
01705  */
01706 typedef union _hw_cau_str_ca3
01707 {
01708     uint32_t U;
01709     struct _hw_cau_str_ca3_bitfields
01710     {
01711         uint32_t CA3 : 32;             /*!< [31:0] CA3 */
01712     } B;
01713 } hw_cau_str_ca3_t;
01714 
01715 /*!
01716  * @name Constants and macros for entire CAU_STR_CA3 register
01717  */
01718 /*@{*/
01719 #define HW_CAU_STR_CA3_ADDR(x)   ((x) + 0x894U)
01720 
01721 #define HW_CAU_STR_CA3(x)        (*(__I hw_cau_str_ca3_t *) HW_CAU_STR_CA3_ADDR(x))
01722 #define HW_CAU_STR_CA3_RD(x)     (ADDRESS_READ(hw_cau_str_ca3_t, HW_CAU_STR_CA3_ADDR(x)))
01723 /*@}*/
01724 
01725 /*
01726  * Constants & macros for individual CAU_STR_CA3 bitfields
01727  */
01728 
01729 /*!
01730  * @name Register CAU_STR_CA3, field CA3[31:0] (RO)
01731  */
01732 /*@{*/
01733 #define BP_CAU_STR_CA3_CA3   (0U)          /*!< Bit position for CAU_STR_CA3_CA3. */
01734 #define BM_CAU_STR_CA3_CA3   (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CA3_CA3. */
01735 #define BS_CAU_STR_CA3_CA3   (32U)         /*!< Bit field size in bits for CAU_STR_CA3_CA3. */
01736 
01737 /*! @brief Read current value of the CAU_STR_CA3_CA3 field. */
01738 #define BR_CAU_STR_CA3_CA3(x) (HW_CAU_STR_CA3(x).U)
01739 /*@}*/
01740 
01741 /*******************************************************************************
01742  * HW_CAU_STR_CA4 - General Purpose Register 4 - Store Register command
01743  ******************************************************************************/
01744 
01745 /*!
01746  * @brief HW_CAU_STR_CA4 - General Purpose Register 4 - Store Register command (RO)
01747  *
01748  * Reset value: 0x00000000U
01749  */
01750 typedef union _hw_cau_str_ca4
01751 {
01752     uint32_t U;
01753     struct _hw_cau_str_ca4_bitfields
01754     {
01755         uint32_t CA4 : 32;             /*!< [31:0] CA4 */
01756     } B;
01757 } hw_cau_str_ca4_t;
01758 
01759 /*!
01760  * @name Constants and macros for entire CAU_STR_CA4 register
01761  */
01762 /*@{*/
01763 #define HW_CAU_STR_CA4_ADDR(x)   ((x) + 0x898U)
01764 
01765 #define HW_CAU_STR_CA4(x)        (*(__I hw_cau_str_ca4_t *) HW_CAU_STR_CA4_ADDR(x))
01766 #define HW_CAU_STR_CA4_RD(x)     (ADDRESS_READ(hw_cau_str_ca4_t, HW_CAU_STR_CA4_ADDR(x)))
01767 /*@}*/
01768 
01769 /*
01770  * Constants & macros for individual CAU_STR_CA4 bitfields
01771  */
01772 
01773 /*!
01774  * @name Register CAU_STR_CA4, field CA4[31:0] (RO)
01775  */
01776 /*@{*/
01777 #define BP_CAU_STR_CA4_CA4   (0U)          /*!< Bit position for CAU_STR_CA4_CA4. */
01778 #define BM_CAU_STR_CA4_CA4   (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CA4_CA4. */
01779 #define BS_CAU_STR_CA4_CA4   (32U)         /*!< Bit field size in bits for CAU_STR_CA4_CA4. */
01780 
01781 /*! @brief Read current value of the CAU_STR_CA4_CA4 field. */
01782 #define BR_CAU_STR_CA4_CA4(x) (HW_CAU_STR_CA4(x).U)
01783 /*@}*/
01784 
01785 /*******************************************************************************
01786  * HW_CAU_STR_CA5 - General Purpose Register 5 - Store Register command
01787  ******************************************************************************/
01788 
01789 /*!
01790  * @brief HW_CAU_STR_CA5 - General Purpose Register 5 - Store Register command (RO)
01791  *
01792  * Reset value: 0x00000000U
01793  */
01794 typedef union _hw_cau_str_ca5
01795 {
01796     uint32_t U;
01797     struct _hw_cau_str_ca5_bitfields
01798     {
01799         uint32_t CA5 : 32;             /*!< [31:0] CA5 */
01800     } B;
01801 } hw_cau_str_ca5_t;
01802 
01803 /*!
01804  * @name Constants and macros for entire CAU_STR_CA5 register
01805  */
01806 /*@{*/
01807 #define HW_CAU_STR_CA5_ADDR(x)   ((x) + 0x89CU)
01808 
01809 #define HW_CAU_STR_CA5(x)        (*(__I hw_cau_str_ca5_t *) HW_CAU_STR_CA5_ADDR(x))
01810 #define HW_CAU_STR_CA5_RD(x)     (ADDRESS_READ(hw_cau_str_ca5_t, HW_CAU_STR_CA5_ADDR(x)))
01811 /*@}*/
01812 
01813 /*
01814  * Constants & macros for individual CAU_STR_CA5 bitfields
01815  */
01816 
01817 /*!
01818  * @name Register CAU_STR_CA5, field CA5[31:0] (RO)
01819  */
01820 /*@{*/
01821 #define BP_CAU_STR_CA5_CA5   (0U)          /*!< Bit position for CAU_STR_CA5_CA5. */
01822 #define BM_CAU_STR_CA5_CA5   (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CA5_CA5. */
01823 #define BS_CAU_STR_CA5_CA5   (32U)         /*!< Bit field size in bits for CAU_STR_CA5_CA5. */
01824 
01825 /*! @brief Read current value of the CAU_STR_CA5_CA5 field. */
01826 #define BR_CAU_STR_CA5_CA5(x) (HW_CAU_STR_CA5(x).U)
01827 /*@}*/
01828 
01829 /*******************************************************************************
01830  * HW_CAU_STR_CA6 - General Purpose Register 6 - Store Register command
01831  ******************************************************************************/
01832 
01833 /*!
01834  * @brief HW_CAU_STR_CA6 - General Purpose Register 6 - Store Register command (RO)
01835  *
01836  * Reset value: 0x00000000U
01837  */
01838 typedef union _hw_cau_str_ca6
01839 {
01840     uint32_t U;
01841     struct _hw_cau_str_ca6_bitfields
01842     {
01843         uint32_t CA6 : 32;             /*!< [31:0] CA6 */
01844     } B;
01845 } hw_cau_str_ca6_t;
01846 
01847 /*!
01848  * @name Constants and macros for entire CAU_STR_CA6 register
01849  */
01850 /*@{*/
01851 #define HW_CAU_STR_CA6_ADDR(x)   ((x) + 0x8A0U)
01852 
01853 #define HW_CAU_STR_CA6(x)        (*(__I hw_cau_str_ca6_t *) HW_CAU_STR_CA6_ADDR(x))
01854 #define HW_CAU_STR_CA6_RD(x)     (ADDRESS_READ(hw_cau_str_ca6_t, HW_CAU_STR_CA6_ADDR(x)))
01855 /*@}*/
01856 
01857 /*
01858  * Constants & macros for individual CAU_STR_CA6 bitfields
01859  */
01860 
01861 /*!
01862  * @name Register CAU_STR_CA6, field CA6[31:0] (RO)
01863  */
01864 /*@{*/
01865 #define BP_CAU_STR_CA6_CA6   (0U)          /*!< Bit position for CAU_STR_CA6_CA6. */
01866 #define BM_CAU_STR_CA6_CA6   (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CA6_CA6. */
01867 #define BS_CAU_STR_CA6_CA6   (32U)         /*!< Bit field size in bits for CAU_STR_CA6_CA6. */
01868 
01869 /*! @brief Read current value of the CAU_STR_CA6_CA6 field. */
01870 #define BR_CAU_STR_CA6_CA6(x) (HW_CAU_STR_CA6(x).U)
01871 /*@}*/
01872 
01873 /*******************************************************************************
01874  * HW_CAU_STR_CA7 - General Purpose Register 7 - Store Register command
01875  ******************************************************************************/
01876 
01877 /*!
01878  * @brief HW_CAU_STR_CA7 - General Purpose Register 7 - Store Register command (RO)
01879  *
01880  * Reset value: 0x00000000U
01881  */
01882 typedef union _hw_cau_str_ca7
01883 {
01884     uint32_t U;
01885     struct _hw_cau_str_ca7_bitfields
01886     {
01887         uint32_t CA7 : 32;             /*!< [31:0] CA7 */
01888     } B;
01889 } hw_cau_str_ca7_t;
01890 
01891 /*!
01892  * @name Constants and macros for entire CAU_STR_CA7 register
01893  */
01894 /*@{*/
01895 #define HW_CAU_STR_CA7_ADDR(x)   ((x) + 0x8A4U)
01896 
01897 #define HW_CAU_STR_CA7(x)        (*(__I hw_cau_str_ca7_t *) HW_CAU_STR_CA7_ADDR(x))
01898 #define HW_CAU_STR_CA7_RD(x)     (ADDRESS_READ(hw_cau_str_ca7_t, HW_CAU_STR_CA7_ADDR(x)))
01899 /*@}*/
01900 
01901 /*
01902  * Constants & macros for individual CAU_STR_CA7 bitfields
01903  */
01904 
01905 /*!
01906  * @name Register CAU_STR_CA7, field CA7[31:0] (RO)
01907  */
01908 /*@{*/
01909 #define BP_CAU_STR_CA7_CA7   (0U)          /*!< Bit position for CAU_STR_CA7_CA7. */
01910 #define BM_CAU_STR_CA7_CA7   (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CA7_CA7. */
01911 #define BS_CAU_STR_CA7_CA7   (32U)         /*!< Bit field size in bits for CAU_STR_CA7_CA7. */
01912 
01913 /*! @brief Read current value of the CAU_STR_CA7_CA7 field. */
01914 #define BR_CAU_STR_CA7_CA7(x) (HW_CAU_STR_CA7(x).U)
01915 /*@}*/
01916 
01917 /*******************************************************************************
01918  * HW_CAU_STR_CA8 - General Purpose Register 8 - Store Register command
01919  ******************************************************************************/
01920 
01921 /*!
01922  * @brief HW_CAU_STR_CA8 - General Purpose Register 8 - Store Register command (RO)
01923  *
01924  * Reset value: 0x00000000U
01925  */
01926 typedef union _hw_cau_str_ca8
01927 {
01928     uint32_t U;
01929     struct _hw_cau_str_ca8_bitfields
01930     {
01931         uint32_t CA8 : 32;             /*!< [31:0] CA8 */
01932     } B;
01933 } hw_cau_str_ca8_t;
01934 
01935 /*!
01936  * @name Constants and macros for entire CAU_STR_CA8 register
01937  */
01938 /*@{*/
01939 #define HW_CAU_STR_CA8_ADDR(x)   ((x) + 0x8A8U)
01940 
01941 #define HW_CAU_STR_CA8(x)        (*(__I hw_cau_str_ca8_t *) HW_CAU_STR_CA8_ADDR(x))
01942 #define HW_CAU_STR_CA8_RD(x)     (ADDRESS_READ(hw_cau_str_ca8_t, HW_CAU_STR_CA8_ADDR(x)))
01943 /*@}*/
01944 
01945 /*
01946  * Constants & macros for individual CAU_STR_CA8 bitfields
01947  */
01948 
01949 /*!
01950  * @name Register CAU_STR_CA8, field CA8[31:0] (RO)
01951  */
01952 /*@{*/
01953 #define BP_CAU_STR_CA8_CA8   (0U)          /*!< Bit position for CAU_STR_CA8_CA8. */
01954 #define BM_CAU_STR_CA8_CA8   (0xFFFFFFFFU) /*!< Bit mask for CAU_STR_CA8_CA8. */
01955 #define BS_CAU_STR_CA8_CA8   (32U)         /*!< Bit field size in bits for CAU_STR_CA8_CA8. */
01956 
01957 /*! @brief Read current value of the CAU_STR_CA8_CA8 field. */
01958 #define BR_CAU_STR_CA8_CA8(x) (HW_CAU_STR_CA8(x).U)
01959 /*@}*/
01960 
01961 /*******************************************************************************
01962  * HW_CAU_ADR_CASR - Status register  - Add Register command
01963  ******************************************************************************/
01964 
01965 /*!
01966  * @brief HW_CAU_ADR_CASR - Status register  - Add Register command (WO)
01967  *
01968  * Reset value: 0x20000000U
01969  */
01970 typedef union _hw_cau_adr_casr
01971 {
01972     uint32_t U;
01973     struct _hw_cau_adr_casr_bitfields
01974     {
01975         uint32_t IC : 1;               /*!< [0]  */
01976         uint32_t DPE : 1;              /*!< [1]  */
01977         uint32_t RESERVED0 : 26;       /*!< [27:2]  */
01978         uint32_t VER : 4;              /*!< [31:28] CAU version */
01979     } B;
01980 } hw_cau_adr_casr_t;
01981 
01982 /*!
01983  * @name Constants and macros for entire CAU_ADR_CASR register
01984  */
01985 /*@{*/
01986 #define HW_CAU_ADR_CASR_ADDR(x)  ((x) + 0x8C0U)
01987 
01988 #define HW_CAU_ADR_CASR(x)       (*(__O hw_cau_adr_casr_t *) HW_CAU_ADR_CASR_ADDR(x))
01989 #define HW_CAU_ADR_CASR_WR(x, v) (ADDRESS_WRITE(hw_cau_adr_casr_t, HW_CAU_ADR_CASR_ADDR(x), v))
01990 /*@}*/
01991 
01992 /*
01993  * Constants & macros for individual CAU_ADR_CASR bitfields
01994  */
01995 
01996 /*!
01997  * @name Register CAU_ADR_CASR, field IC[0] (WO)
01998  *
01999  * Values:
02000  * - 0 - No illegal commands issued
02001  * - 1 - Illegal command issued
02002  */
02003 /*@{*/
02004 #define BP_CAU_ADR_CASR_IC   (0U)          /*!< Bit position for CAU_ADR_CASR_IC. */
02005 #define BM_CAU_ADR_CASR_IC   (0x00000001U) /*!< Bit mask for CAU_ADR_CASR_IC. */
02006 #define BS_CAU_ADR_CASR_IC   (1U)          /*!< Bit field size in bits for CAU_ADR_CASR_IC. */
02007 
02008 /*! @brief Format value for bitfield CAU_ADR_CASR_IC. */
02009 #define BF_CAU_ADR_CASR_IC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CASR_IC) & BM_CAU_ADR_CASR_IC)
02010 /*@}*/
02011 
02012 /*!
02013  * @name Register CAU_ADR_CASR, field DPE[1] (WO)
02014  *
02015  * Values:
02016  * - 0 - No error detected
02017  * - 1 - DES key parity error detected
02018  */
02019 /*@{*/
02020 #define BP_CAU_ADR_CASR_DPE  (1U)          /*!< Bit position for CAU_ADR_CASR_DPE. */
02021 #define BM_CAU_ADR_CASR_DPE  (0x00000002U) /*!< Bit mask for CAU_ADR_CASR_DPE. */
02022 #define BS_CAU_ADR_CASR_DPE  (1U)          /*!< Bit field size in bits for CAU_ADR_CASR_DPE. */
02023 
02024 /*! @brief Format value for bitfield CAU_ADR_CASR_DPE. */
02025 #define BF_CAU_ADR_CASR_DPE(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CASR_DPE) & BM_CAU_ADR_CASR_DPE)
02026 /*@}*/
02027 
02028 /*!
02029  * @name Register CAU_ADR_CASR, field VER[31:28] (WO)
02030  *
02031  * Values:
02032  * - 0001 - Initial CAU version
02033  * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
02034  *     value on this device)
02035  */
02036 /*@{*/
02037 #define BP_CAU_ADR_CASR_VER  (28U)         /*!< Bit position for CAU_ADR_CASR_VER. */
02038 #define BM_CAU_ADR_CASR_VER  (0xF0000000U) /*!< Bit mask for CAU_ADR_CASR_VER. */
02039 #define BS_CAU_ADR_CASR_VER  (4U)          /*!< Bit field size in bits for CAU_ADR_CASR_VER. */
02040 
02041 /*! @brief Format value for bitfield CAU_ADR_CASR_VER. */
02042 #define BF_CAU_ADR_CASR_VER(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CASR_VER) & BM_CAU_ADR_CASR_VER)
02043 /*@}*/
02044 
02045 /*******************************************************************************
02046  * HW_CAU_ADR_CAA - Accumulator register - Add to register command
02047  ******************************************************************************/
02048 
02049 /*!
02050  * @brief HW_CAU_ADR_CAA - Accumulator register - Add to register command (WO)
02051  *
02052  * Reset value: 0x00000000U
02053  */
02054 typedef union _hw_cau_adr_caa
02055 {
02056     uint32_t U;
02057     struct _hw_cau_adr_caa_bitfields
02058     {
02059         uint32_t ACC : 32;             /*!< [31:0] ACC */
02060     } B;
02061 } hw_cau_adr_caa_t;
02062 
02063 /*!
02064  * @name Constants and macros for entire CAU_ADR_CAA register
02065  */
02066 /*@{*/
02067 #define HW_CAU_ADR_CAA_ADDR(x)   ((x) + 0x8C4U)
02068 
02069 #define HW_CAU_ADR_CAA(x)        (*(__O hw_cau_adr_caa_t *) HW_CAU_ADR_CAA_ADDR(x))
02070 #define HW_CAU_ADR_CAA_WR(x, v)  (ADDRESS_WRITE(hw_cau_adr_caa_t, HW_CAU_ADR_CAA_ADDR(x), v))
02071 /*@}*/
02072 
02073 /*
02074  * Constants & macros for individual CAU_ADR_CAA bitfields
02075  */
02076 
02077 /*!
02078  * @name Register CAU_ADR_CAA, field ACC[31:0] (WO)
02079  */
02080 /*@{*/
02081 #define BP_CAU_ADR_CAA_ACC   (0U)          /*!< Bit position for CAU_ADR_CAA_ACC. */
02082 #define BM_CAU_ADR_CAA_ACC   (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CAA_ACC. */
02083 #define BS_CAU_ADR_CAA_ACC   (32U)         /*!< Bit field size in bits for CAU_ADR_CAA_ACC. */
02084 
02085 /*! @brief Format value for bitfield CAU_ADR_CAA_ACC. */
02086 #define BF_CAU_ADR_CAA_ACC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CAA_ACC) & BM_CAU_ADR_CAA_ACC)
02087 /*@}*/
02088 
02089 /*******************************************************************************
02090  * HW_CAU_ADR_CA0 - General Purpose Register 0 - Add to register command
02091  ******************************************************************************/
02092 
02093 /*!
02094  * @brief HW_CAU_ADR_CA0 - General Purpose Register 0 - Add to register command (WO)
02095  *
02096  * Reset value: 0x00000000U
02097  */
02098 typedef union _hw_cau_adr_ca0
02099 {
02100     uint32_t U;
02101     struct _hw_cau_adr_ca0_bitfields
02102     {
02103         uint32_t CA0 : 32;             /*!< [31:0] CA0 */
02104     } B;
02105 } hw_cau_adr_ca0_t;
02106 
02107 /*!
02108  * @name Constants and macros for entire CAU_ADR_CA0 register
02109  */
02110 /*@{*/
02111 #define HW_CAU_ADR_CA0_ADDR(x)   ((x) + 0x8C8U)
02112 
02113 #define HW_CAU_ADR_CA0(x)        (*(__O hw_cau_adr_ca0_t *) HW_CAU_ADR_CA0_ADDR(x))
02114 #define HW_CAU_ADR_CA0_WR(x, v)  (ADDRESS_WRITE(hw_cau_adr_ca0_t, HW_CAU_ADR_CA0_ADDR(x), v))
02115 /*@}*/
02116 
02117 /*
02118  * Constants & macros for individual CAU_ADR_CA0 bitfields
02119  */
02120 
02121 /*!
02122  * @name Register CAU_ADR_CA0, field CA0[31:0] (WO)
02123  */
02124 /*@{*/
02125 #define BP_CAU_ADR_CA0_CA0   (0U)          /*!< Bit position for CAU_ADR_CA0_CA0. */
02126 #define BM_CAU_ADR_CA0_CA0   (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CA0_CA0. */
02127 #define BS_CAU_ADR_CA0_CA0   (32U)         /*!< Bit field size in bits for CAU_ADR_CA0_CA0. */
02128 
02129 /*! @brief Format value for bitfield CAU_ADR_CA0_CA0. */
02130 #define BF_CAU_ADR_CA0_CA0(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CA0_CA0) & BM_CAU_ADR_CA0_CA0)
02131 /*@}*/
02132 
02133 /*******************************************************************************
02134  * HW_CAU_ADR_CA1 - General Purpose Register 1 - Add to register command
02135  ******************************************************************************/
02136 
02137 /*!
02138  * @brief HW_CAU_ADR_CA1 - General Purpose Register 1 - Add to register command (WO)
02139  *
02140  * Reset value: 0x00000000U
02141  */
02142 typedef union _hw_cau_adr_ca1
02143 {
02144     uint32_t U;
02145     struct _hw_cau_adr_ca1_bitfields
02146     {
02147         uint32_t CA1 : 32;             /*!< [31:0] CA1 */
02148     } B;
02149 } hw_cau_adr_ca1_t;
02150 
02151 /*!
02152  * @name Constants and macros for entire CAU_ADR_CA1 register
02153  */
02154 /*@{*/
02155 #define HW_CAU_ADR_CA1_ADDR(x)   ((x) + 0x8CCU)
02156 
02157 #define HW_CAU_ADR_CA1(x)        (*(__O hw_cau_adr_ca1_t *) HW_CAU_ADR_CA1_ADDR(x))
02158 #define HW_CAU_ADR_CA1_WR(x, v)  (ADDRESS_WRITE(hw_cau_adr_ca1_t, HW_CAU_ADR_CA1_ADDR(x), v))
02159 /*@}*/
02160 
02161 /*
02162  * Constants & macros for individual CAU_ADR_CA1 bitfields
02163  */
02164 
02165 /*!
02166  * @name Register CAU_ADR_CA1, field CA1[31:0] (WO)
02167  */
02168 /*@{*/
02169 #define BP_CAU_ADR_CA1_CA1   (0U)          /*!< Bit position for CAU_ADR_CA1_CA1. */
02170 #define BM_CAU_ADR_CA1_CA1   (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CA1_CA1. */
02171 #define BS_CAU_ADR_CA1_CA1   (32U)         /*!< Bit field size in bits for CAU_ADR_CA1_CA1. */
02172 
02173 /*! @brief Format value for bitfield CAU_ADR_CA1_CA1. */
02174 #define BF_CAU_ADR_CA1_CA1(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CA1_CA1) & BM_CAU_ADR_CA1_CA1)
02175 /*@}*/
02176 
02177 /*******************************************************************************
02178  * HW_CAU_ADR_CA2 - General Purpose Register 2 - Add to register command
02179  ******************************************************************************/
02180 
02181 /*!
02182  * @brief HW_CAU_ADR_CA2 - General Purpose Register 2 - Add to register command (WO)
02183  *
02184  * Reset value: 0x00000000U
02185  */
02186 typedef union _hw_cau_adr_ca2
02187 {
02188     uint32_t U;
02189     struct _hw_cau_adr_ca2_bitfields
02190     {
02191         uint32_t CA2 : 32;             /*!< [31:0] CA2 */
02192     } B;
02193 } hw_cau_adr_ca2_t;
02194 
02195 /*!
02196  * @name Constants and macros for entire CAU_ADR_CA2 register
02197  */
02198 /*@{*/
02199 #define HW_CAU_ADR_CA2_ADDR(x)   ((x) + 0x8D0U)
02200 
02201 #define HW_CAU_ADR_CA2(x)        (*(__O hw_cau_adr_ca2_t *) HW_CAU_ADR_CA2_ADDR(x))
02202 #define HW_CAU_ADR_CA2_WR(x, v)  (ADDRESS_WRITE(hw_cau_adr_ca2_t, HW_CAU_ADR_CA2_ADDR(x), v))
02203 /*@}*/
02204 
02205 /*
02206  * Constants & macros for individual CAU_ADR_CA2 bitfields
02207  */
02208 
02209 /*!
02210  * @name Register CAU_ADR_CA2, field CA2[31:0] (WO)
02211  */
02212 /*@{*/
02213 #define BP_CAU_ADR_CA2_CA2   (0U)          /*!< Bit position for CAU_ADR_CA2_CA2. */
02214 #define BM_CAU_ADR_CA2_CA2   (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CA2_CA2. */
02215 #define BS_CAU_ADR_CA2_CA2   (32U)         /*!< Bit field size in bits for CAU_ADR_CA2_CA2. */
02216 
02217 /*! @brief Format value for bitfield CAU_ADR_CA2_CA2. */
02218 #define BF_CAU_ADR_CA2_CA2(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CA2_CA2) & BM_CAU_ADR_CA2_CA2)
02219 /*@}*/
02220 
02221 /*******************************************************************************
02222  * HW_CAU_ADR_CA3 - General Purpose Register 3 - Add to register command
02223  ******************************************************************************/
02224 
02225 /*!
02226  * @brief HW_CAU_ADR_CA3 - General Purpose Register 3 - Add to register command (WO)
02227  *
02228  * Reset value: 0x00000000U
02229  */
02230 typedef union _hw_cau_adr_ca3
02231 {
02232     uint32_t U;
02233     struct _hw_cau_adr_ca3_bitfields
02234     {
02235         uint32_t CA3 : 32;             /*!< [31:0] CA3 */
02236     } B;
02237 } hw_cau_adr_ca3_t;
02238 
02239 /*!
02240  * @name Constants and macros for entire CAU_ADR_CA3 register
02241  */
02242 /*@{*/
02243 #define HW_CAU_ADR_CA3_ADDR(x)   ((x) + 0x8D4U)
02244 
02245 #define HW_CAU_ADR_CA3(x)        (*(__O hw_cau_adr_ca3_t *) HW_CAU_ADR_CA3_ADDR(x))
02246 #define HW_CAU_ADR_CA3_WR(x, v)  (ADDRESS_WRITE(hw_cau_adr_ca3_t, HW_CAU_ADR_CA3_ADDR(x), v))
02247 /*@}*/
02248 
02249 /*
02250  * Constants & macros for individual CAU_ADR_CA3 bitfields
02251  */
02252 
02253 /*!
02254  * @name Register CAU_ADR_CA3, field CA3[31:0] (WO)
02255  */
02256 /*@{*/
02257 #define BP_CAU_ADR_CA3_CA3   (0U)          /*!< Bit position for CAU_ADR_CA3_CA3. */
02258 #define BM_CAU_ADR_CA3_CA3   (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CA3_CA3. */
02259 #define BS_CAU_ADR_CA3_CA3   (32U)         /*!< Bit field size in bits for CAU_ADR_CA3_CA3. */
02260 
02261 /*! @brief Format value for bitfield CAU_ADR_CA3_CA3. */
02262 #define BF_CAU_ADR_CA3_CA3(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CA3_CA3) & BM_CAU_ADR_CA3_CA3)
02263 /*@}*/
02264 
02265 /*******************************************************************************
02266  * HW_CAU_ADR_CA4 - General Purpose Register 4 - Add to register command
02267  ******************************************************************************/
02268 
02269 /*!
02270  * @brief HW_CAU_ADR_CA4 - General Purpose Register 4 - Add to register command (WO)
02271  *
02272  * Reset value: 0x00000000U
02273  */
02274 typedef union _hw_cau_adr_ca4
02275 {
02276     uint32_t U;
02277     struct _hw_cau_adr_ca4_bitfields
02278     {
02279         uint32_t CA4 : 32;             /*!< [31:0] CA4 */
02280     } B;
02281 } hw_cau_adr_ca4_t;
02282 
02283 /*!
02284  * @name Constants and macros for entire CAU_ADR_CA4 register
02285  */
02286 /*@{*/
02287 #define HW_CAU_ADR_CA4_ADDR(x)   ((x) + 0x8D8U)
02288 
02289 #define HW_CAU_ADR_CA4(x)        (*(__O hw_cau_adr_ca4_t *) HW_CAU_ADR_CA4_ADDR(x))
02290 #define HW_CAU_ADR_CA4_WR(x, v)  (ADDRESS_WRITE(hw_cau_adr_ca4_t, HW_CAU_ADR_CA4_ADDR(x), v))
02291 /*@}*/
02292 
02293 /*
02294  * Constants & macros for individual CAU_ADR_CA4 bitfields
02295  */
02296 
02297 /*!
02298  * @name Register CAU_ADR_CA4, field CA4[31:0] (WO)
02299  */
02300 /*@{*/
02301 #define BP_CAU_ADR_CA4_CA4   (0U)          /*!< Bit position for CAU_ADR_CA4_CA4. */
02302 #define BM_CAU_ADR_CA4_CA4   (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CA4_CA4. */
02303 #define BS_CAU_ADR_CA4_CA4   (32U)         /*!< Bit field size in bits for CAU_ADR_CA4_CA4. */
02304 
02305 /*! @brief Format value for bitfield CAU_ADR_CA4_CA4. */
02306 #define BF_CAU_ADR_CA4_CA4(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CA4_CA4) & BM_CAU_ADR_CA4_CA4)
02307 /*@}*/
02308 
02309 /*******************************************************************************
02310  * HW_CAU_ADR_CA5 - General Purpose Register 5 - Add to register command
02311  ******************************************************************************/
02312 
02313 /*!
02314  * @brief HW_CAU_ADR_CA5 - General Purpose Register 5 - Add to register command (WO)
02315  *
02316  * Reset value: 0x00000000U
02317  */
02318 typedef union _hw_cau_adr_ca5
02319 {
02320     uint32_t U;
02321     struct _hw_cau_adr_ca5_bitfields
02322     {
02323         uint32_t CA5 : 32;             /*!< [31:0] CA5 */
02324     } B;
02325 } hw_cau_adr_ca5_t;
02326 
02327 /*!
02328  * @name Constants and macros for entire CAU_ADR_CA5 register
02329  */
02330 /*@{*/
02331 #define HW_CAU_ADR_CA5_ADDR(x)   ((x) + 0x8DCU)
02332 
02333 #define HW_CAU_ADR_CA5(x)        (*(__O hw_cau_adr_ca5_t *) HW_CAU_ADR_CA5_ADDR(x))
02334 #define HW_CAU_ADR_CA5_WR(x, v)  (ADDRESS_WRITE(hw_cau_adr_ca5_t, HW_CAU_ADR_CA5_ADDR(x), v))
02335 /*@}*/
02336 
02337 /*
02338  * Constants & macros for individual CAU_ADR_CA5 bitfields
02339  */
02340 
02341 /*!
02342  * @name Register CAU_ADR_CA5, field CA5[31:0] (WO)
02343  */
02344 /*@{*/
02345 #define BP_CAU_ADR_CA5_CA5   (0U)          /*!< Bit position for CAU_ADR_CA5_CA5. */
02346 #define BM_CAU_ADR_CA5_CA5   (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CA5_CA5. */
02347 #define BS_CAU_ADR_CA5_CA5   (32U)         /*!< Bit field size in bits for CAU_ADR_CA5_CA5. */
02348 
02349 /*! @brief Format value for bitfield CAU_ADR_CA5_CA5. */
02350 #define BF_CAU_ADR_CA5_CA5(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CA5_CA5) & BM_CAU_ADR_CA5_CA5)
02351 /*@}*/
02352 
02353 /*******************************************************************************
02354  * HW_CAU_ADR_CA6 - General Purpose Register 6 - Add to register command
02355  ******************************************************************************/
02356 
02357 /*!
02358  * @brief HW_CAU_ADR_CA6 - General Purpose Register 6 - Add to register command (WO)
02359  *
02360  * Reset value: 0x00000000U
02361  */
02362 typedef union _hw_cau_adr_ca6
02363 {
02364     uint32_t U;
02365     struct _hw_cau_adr_ca6_bitfields
02366     {
02367         uint32_t CA6 : 32;             /*!< [31:0] CA6 */
02368     } B;
02369 } hw_cau_adr_ca6_t;
02370 
02371 /*!
02372  * @name Constants and macros for entire CAU_ADR_CA6 register
02373  */
02374 /*@{*/
02375 #define HW_CAU_ADR_CA6_ADDR(x)   ((x) + 0x8E0U)
02376 
02377 #define HW_CAU_ADR_CA6(x)        (*(__O hw_cau_adr_ca6_t *) HW_CAU_ADR_CA6_ADDR(x))
02378 #define HW_CAU_ADR_CA6_WR(x, v)  (ADDRESS_WRITE(hw_cau_adr_ca6_t, HW_CAU_ADR_CA6_ADDR(x), v))
02379 /*@}*/
02380 
02381 /*
02382  * Constants & macros for individual CAU_ADR_CA6 bitfields
02383  */
02384 
02385 /*!
02386  * @name Register CAU_ADR_CA6, field CA6[31:0] (WO)
02387  */
02388 /*@{*/
02389 #define BP_CAU_ADR_CA6_CA6   (0U)          /*!< Bit position for CAU_ADR_CA6_CA6. */
02390 #define BM_CAU_ADR_CA6_CA6   (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CA6_CA6. */
02391 #define BS_CAU_ADR_CA6_CA6   (32U)         /*!< Bit field size in bits for CAU_ADR_CA6_CA6. */
02392 
02393 /*! @brief Format value for bitfield CAU_ADR_CA6_CA6. */
02394 #define BF_CAU_ADR_CA6_CA6(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CA6_CA6) & BM_CAU_ADR_CA6_CA6)
02395 /*@}*/
02396 
02397 /*******************************************************************************
02398  * HW_CAU_ADR_CA7 - General Purpose Register 7 - Add to register command
02399  ******************************************************************************/
02400 
02401 /*!
02402  * @brief HW_CAU_ADR_CA7 - General Purpose Register 7 - Add to register command (WO)
02403  *
02404  * Reset value: 0x00000000U
02405  */
02406 typedef union _hw_cau_adr_ca7
02407 {
02408     uint32_t U;
02409     struct _hw_cau_adr_ca7_bitfields
02410     {
02411         uint32_t CA7 : 32;             /*!< [31:0] CA7 */
02412     } B;
02413 } hw_cau_adr_ca7_t;
02414 
02415 /*!
02416  * @name Constants and macros for entire CAU_ADR_CA7 register
02417  */
02418 /*@{*/
02419 #define HW_CAU_ADR_CA7_ADDR(x)   ((x) + 0x8E4U)
02420 
02421 #define HW_CAU_ADR_CA7(x)        (*(__O hw_cau_adr_ca7_t *) HW_CAU_ADR_CA7_ADDR(x))
02422 #define HW_CAU_ADR_CA7_WR(x, v)  (ADDRESS_WRITE(hw_cau_adr_ca7_t, HW_CAU_ADR_CA7_ADDR(x), v))
02423 /*@}*/
02424 
02425 /*
02426  * Constants & macros for individual CAU_ADR_CA7 bitfields
02427  */
02428 
02429 /*!
02430  * @name Register CAU_ADR_CA7, field CA7[31:0] (WO)
02431  */
02432 /*@{*/
02433 #define BP_CAU_ADR_CA7_CA7   (0U)          /*!< Bit position for CAU_ADR_CA7_CA7. */
02434 #define BM_CAU_ADR_CA7_CA7   (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CA7_CA7. */
02435 #define BS_CAU_ADR_CA7_CA7   (32U)         /*!< Bit field size in bits for CAU_ADR_CA7_CA7. */
02436 
02437 /*! @brief Format value for bitfield CAU_ADR_CA7_CA7. */
02438 #define BF_CAU_ADR_CA7_CA7(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CA7_CA7) & BM_CAU_ADR_CA7_CA7)
02439 /*@}*/
02440 
02441 /*******************************************************************************
02442  * HW_CAU_ADR_CA8 - General Purpose Register 8 - Add to register command
02443  ******************************************************************************/
02444 
02445 /*!
02446  * @brief HW_CAU_ADR_CA8 - General Purpose Register 8 - Add to register command (WO)
02447  *
02448  * Reset value: 0x00000000U
02449  */
02450 typedef union _hw_cau_adr_ca8
02451 {
02452     uint32_t U;
02453     struct _hw_cau_adr_ca8_bitfields
02454     {
02455         uint32_t CA8 : 32;             /*!< [31:0] CA8 */
02456     } B;
02457 } hw_cau_adr_ca8_t;
02458 
02459 /*!
02460  * @name Constants and macros for entire CAU_ADR_CA8 register
02461  */
02462 /*@{*/
02463 #define HW_CAU_ADR_CA8_ADDR(x)   ((x) + 0x8E8U)
02464 
02465 #define HW_CAU_ADR_CA8(x)        (*(__O hw_cau_adr_ca8_t *) HW_CAU_ADR_CA8_ADDR(x))
02466 #define HW_CAU_ADR_CA8_WR(x, v)  (ADDRESS_WRITE(hw_cau_adr_ca8_t, HW_CAU_ADR_CA8_ADDR(x), v))
02467 /*@}*/
02468 
02469 /*
02470  * Constants & macros for individual CAU_ADR_CA8 bitfields
02471  */
02472 
02473 /*!
02474  * @name Register CAU_ADR_CA8, field CA8[31:0] (WO)
02475  */
02476 /*@{*/
02477 #define BP_CAU_ADR_CA8_CA8   (0U)          /*!< Bit position for CAU_ADR_CA8_CA8. */
02478 #define BM_CAU_ADR_CA8_CA8   (0xFFFFFFFFU) /*!< Bit mask for CAU_ADR_CA8_CA8. */
02479 #define BS_CAU_ADR_CA8_CA8   (32U)         /*!< Bit field size in bits for CAU_ADR_CA8_CA8. */
02480 
02481 /*! @brief Format value for bitfield CAU_ADR_CA8_CA8. */
02482 #define BF_CAU_ADR_CA8_CA8(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ADR_CA8_CA8) & BM_CAU_ADR_CA8_CA8)
02483 /*@}*/
02484 
02485 /*******************************************************************************
02486  * HW_CAU_RADR_CASR - Status register  - Reverse and Add to Register command
02487  ******************************************************************************/
02488 
02489 /*!
02490  * @brief HW_CAU_RADR_CASR - Status register  - Reverse and Add to Register command (WO)
02491  *
02492  * Reset value: 0x20000000U
02493  */
02494 typedef union _hw_cau_radr_casr
02495 {
02496     uint32_t U;
02497     struct _hw_cau_radr_casr_bitfields
02498     {
02499         uint32_t IC : 1;               /*!< [0]  */
02500         uint32_t DPE : 1;              /*!< [1]  */
02501         uint32_t RESERVED0 : 26;       /*!< [27:2]  */
02502         uint32_t VER : 4;              /*!< [31:28] CAU version */
02503     } B;
02504 } hw_cau_radr_casr_t;
02505 
02506 /*!
02507  * @name Constants and macros for entire CAU_RADR_CASR register
02508  */
02509 /*@{*/
02510 #define HW_CAU_RADR_CASR_ADDR(x) ((x) + 0x900U)
02511 
02512 #define HW_CAU_RADR_CASR(x)      (*(__O hw_cau_radr_casr_t *) HW_CAU_RADR_CASR_ADDR(x))
02513 #define HW_CAU_RADR_CASR_WR(x, v) (ADDRESS_WRITE(hw_cau_radr_casr_t, HW_CAU_RADR_CASR_ADDR(x), v))
02514 /*@}*/
02515 
02516 /*
02517  * Constants & macros for individual CAU_RADR_CASR bitfields
02518  */
02519 
02520 /*!
02521  * @name Register CAU_RADR_CASR, field IC[0] (WO)
02522  *
02523  * Values:
02524  * - 0 - No illegal commands issued
02525  * - 1 - Illegal command issued
02526  */
02527 /*@{*/
02528 #define BP_CAU_RADR_CASR_IC  (0U)          /*!< Bit position for CAU_RADR_CASR_IC. */
02529 #define BM_CAU_RADR_CASR_IC  (0x00000001U) /*!< Bit mask for CAU_RADR_CASR_IC. */
02530 #define BS_CAU_RADR_CASR_IC  (1U)          /*!< Bit field size in bits for CAU_RADR_CASR_IC. */
02531 
02532 /*! @brief Format value for bitfield CAU_RADR_CASR_IC. */
02533 #define BF_CAU_RADR_CASR_IC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CASR_IC) & BM_CAU_RADR_CASR_IC)
02534 /*@}*/
02535 
02536 /*!
02537  * @name Register CAU_RADR_CASR, field DPE[1] (WO)
02538  *
02539  * Values:
02540  * - 0 - No error detected
02541  * - 1 - DES key parity error detected
02542  */
02543 /*@{*/
02544 #define BP_CAU_RADR_CASR_DPE (1U)          /*!< Bit position for CAU_RADR_CASR_DPE. */
02545 #define BM_CAU_RADR_CASR_DPE (0x00000002U) /*!< Bit mask for CAU_RADR_CASR_DPE. */
02546 #define BS_CAU_RADR_CASR_DPE (1U)          /*!< Bit field size in bits for CAU_RADR_CASR_DPE. */
02547 
02548 /*! @brief Format value for bitfield CAU_RADR_CASR_DPE. */
02549 #define BF_CAU_RADR_CASR_DPE(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CASR_DPE) & BM_CAU_RADR_CASR_DPE)
02550 /*@}*/
02551 
02552 /*!
02553  * @name Register CAU_RADR_CASR, field VER[31:28] (WO)
02554  *
02555  * Values:
02556  * - 0001 - Initial CAU version
02557  * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
02558  *     value on this device)
02559  */
02560 /*@{*/
02561 #define BP_CAU_RADR_CASR_VER (28U)         /*!< Bit position for CAU_RADR_CASR_VER. */
02562 #define BM_CAU_RADR_CASR_VER (0xF0000000U) /*!< Bit mask for CAU_RADR_CASR_VER. */
02563 #define BS_CAU_RADR_CASR_VER (4U)          /*!< Bit field size in bits for CAU_RADR_CASR_VER. */
02564 
02565 /*! @brief Format value for bitfield CAU_RADR_CASR_VER. */
02566 #define BF_CAU_RADR_CASR_VER(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CASR_VER) & BM_CAU_RADR_CASR_VER)
02567 /*@}*/
02568 
02569 /*******************************************************************************
02570  * HW_CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command
02571  ******************************************************************************/
02572 
02573 /*!
02574  * @brief HW_CAU_RADR_CAA - Accumulator register - Reverse and Add to Register command (WO)
02575  *
02576  * Reset value: 0x00000000U
02577  */
02578 typedef union _hw_cau_radr_caa
02579 {
02580     uint32_t U;
02581     struct _hw_cau_radr_caa_bitfields
02582     {
02583         uint32_t ACC : 32;             /*!< [31:0] ACC */
02584     } B;
02585 } hw_cau_radr_caa_t;
02586 
02587 /*!
02588  * @name Constants and macros for entire CAU_RADR_CAA register
02589  */
02590 /*@{*/
02591 #define HW_CAU_RADR_CAA_ADDR(x)  ((x) + 0x904U)
02592 
02593 #define HW_CAU_RADR_CAA(x)       (*(__O hw_cau_radr_caa_t *) HW_CAU_RADR_CAA_ADDR(x))
02594 #define HW_CAU_RADR_CAA_WR(x, v) (ADDRESS_WRITE(hw_cau_radr_caa_t, HW_CAU_RADR_CAA_ADDR(x), v))
02595 /*@}*/
02596 
02597 /*
02598  * Constants & macros for individual CAU_RADR_CAA bitfields
02599  */
02600 
02601 /*!
02602  * @name Register CAU_RADR_CAA, field ACC[31:0] (WO)
02603  */
02604 /*@{*/
02605 #define BP_CAU_RADR_CAA_ACC  (0U)          /*!< Bit position for CAU_RADR_CAA_ACC. */
02606 #define BM_CAU_RADR_CAA_ACC  (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CAA_ACC. */
02607 #define BS_CAU_RADR_CAA_ACC  (32U)         /*!< Bit field size in bits for CAU_RADR_CAA_ACC. */
02608 
02609 /*! @brief Format value for bitfield CAU_RADR_CAA_ACC. */
02610 #define BF_CAU_RADR_CAA_ACC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CAA_ACC) & BM_CAU_RADR_CAA_ACC)
02611 /*@}*/
02612 
02613 /*******************************************************************************
02614  * HW_CAU_RADR_CA0 - General Purpose Register 0 - Reverse and Add to Register command
02615  ******************************************************************************/
02616 
02617 /*!
02618  * @brief HW_CAU_RADR_CA0 - General Purpose Register 0 - Reverse and Add to Register command (WO)
02619  *
02620  * Reset value: 0x00000000U
02621  */
02622 typedef union _hw_cau_radr_ca0
02623 {
02624     uint32_t U;
02625     struct _hw_cau_radr_ca0_bitfields
02626     {
02627         uint32_t CA0 : 32;             /*!< [31:0] CA0 */
02628     } B;
02629 } hw_cau_radr_ca0_t;
02630 
02631 /*!
02632  * @name Constants and macros for entire CAU_RADR_CA0 register
02633  */
02634 /*@{*/
02635 #define HW_CAU_RADR_CA0_ADDR(x)  ((x) + 0x908U)
02636 
02637 #define HW_CAU_RADR_CA0(x)       (*(__O hw_cau_radr_ca0_t *) HW_CAU_RADR_CA0_ADDR(x))
02638 #define HW_CAU_RADR_CA0_WR(x, v) (ADDRESS_WRITE(hw_cau_radr_ca0_t, HW_CAU_RADR_CA0_ADDR(x), v))
02639 /*@}*/
02640 
02641 /*
02642  * Constants & macros for individual CAU_RADR_CA0 bitfields
02643  */
02644 
02645 /*!
02646  * @name Register CAU_RADR_CA0, field CA0[31:0] (WO)
02647  */
02648 /*@{*/
02649 #define BP_CAU_RADR_CA0_CA0  (0U)          /*!< Bit position for CAU_RADR_CA0_CA0. */
02650 #define BM_CAU_RADR_CA0_CA0  (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CA0_CA0. */
02651 #define BS_CAU_RADR_CA0_CA0  (32U)         /*!< Bit field size in bits for CAU_RADR_CA0_CA0. */
02652 
02653 /*! @brief Format value for bitfield CAU_RADR_CA0_CA0. */
02654 #define BF_CAU_RADR_CA0_CA0(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CA0_CA0) & BM_CAU_RADR_CA0_CA0)
02655 /*@}*/
02656 
02657 /*******************************************************************************
02658  * HW_CAU_RADR_CA1 - General Purpose Register 1 - Reverse and Add to Register command
02659  ******************************************************************************/
02660 
02661 /*!
02662  * @brief HW_CAU_RADR_CA1 - General Purpose Register 1 - Reverse and Add to Register command (WO)
02663  *
02664  * Reset value: 0x00000000U
02665  */
02666 typedef union _hw_cau_radr_ca1
02667 {
02668     uint32_t U;
02669     struct _hw_cau_radr_ca1_bitfields
02670     {
02671         uint32_t CA1 : 32;             /*!< [31:0] CA1 */
02672     } B;
02673 } hw_cau_radr_ca1_t;
02674 
02675 /*!
02676  * @name Constants and macros for entire CAU_RADR_CA1 register
02677  */
02678 /*@{*/
02679 #define HW_CAU_RADR_CA1_ADDR(x)  ((x) + 0x90CU)
02680 
02681 #define HW_CAU_RADR_CA1(x)       (*(__O hw_cau_radr_ca1_t *) HW_CAU_RADR_CA1_ADDR(x))
02682 #define HW_CAU_RADR_CA1_WR(x, v) (ADDRESS_WRITE(hw_cau_radr_ca1_t, HW_CAU_RADR_CA1_ADDR(x), v))
02683 /*@}*/
02684 
02685 /*
02686  * Constants & macros for individual CAU_RADR_CA1 bitfields
02687  */
02688 
02689 /*!
02690  * @name Register CAU_RADR_CA1, field CA1[31:0] (WO)
02691  */
02692 /*@{*/
02693 #define BP_CAU_RADR_CA1_CA1  (0U)          /*!< Bit position for CAU_RADR_CA1_CA1. */
02694 #define BM_CAU_RADR_CA1_CA1  (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CA1_CA1. */
02695 #define BS_CAU_RADR_CA1_CA1  (32U)         /*!< Bit field size in bits for CAU_RADR_CA1_CA1. */
02696 
02697 /*! @brief Format value for bitfield CAU_RADR_CA1_CA1. */
02698 #define BF_CAU_RADR_CA1_CA1(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CA1_CA1) & BM_CAU_RADR_CA1_CA1)
02699 /*@}*/
02700 
02701 /*******************************************************************************
02702  * HW_CAU_RADR_CA2 - General Purpose Register 2 - Reverse and Add to Register command
02703  ******************************************************************************/
02704 
02705 /*!
02706  * @brief HW_CAU_RADR_CA2 - General Purpose Register 2 - Reverse and Add to Register command (WO)
02707  *
02708  * Reset value: 0x00000000U
02709  */
02710 typedef union _hw_cau_radr_ca2
02711 {
02712     uint32_t U;
02713     struct _hw_cau_radr_ca2_bitfields
02714     {
02715         uint32_t CA2 : 32;             /*!< [31:0] CA2 */
02716     } B;
02717 } hw_cau_radr_ca2_t;
02718 
02719 /*!
02720  * @name Constants and macros for entire CAU_RADR_CA2 register
02721  */
02722 /*@{*/
02723 #define HW_CAU_RADR_CA2_ADDR(x)  ((x) + 0x910U)
02724 
02725 #define HW_CAU_RADR_CA2(x)       (*(__O hw_cau_radr_ca2_t *) HW_CAU_RADR_CA2_ADDR(x))
02726 #define HW_CAU_RADR_CA2_WR(x, v) (ADDRESS_WRITE(hw_cau_radr_ca2_t, HW_CAU_RADR_CA2_ADDR(x), v))
02727 /*@}*/
02728 
02729 /*
02730  * Constants & macros for individual CAU_RADR_CA2 bitfields
02731  */
02732 
02733 /*!
02734  * @name Register CAU_RADR_CA2, field CA2[31:0] (WO)
02735  */
02736 /*@{*/
02737 #define BP_CAU_RADR_CA2_CA2  (0U)          /*!< Bit position for CAU_RADR_CA2_CA2. */
02738 #define BM_CAU_RADR_CA2_CA2  (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CA2_CA2. */
02739 #define BS_CAU_RADR_CA2_CA2  (32U)         /*!< Bit field size in bits for CAU_RADR_CA2_CA2. */
02740 
02741 /*! @brief Format value for bitfield CAU_RADR_CA2_CA2. */
02742 #define BF_CAU_RADR_CA2_CA2(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CA2_CA2) & BM_CAU_RADR_CA2_CA2)
02743 /*@}*/
02744 
02745 /*******************************************************************************
02746  * HW_CAU_RADR_CA3 - General Purpose Register 3 - Reverse and Add to Register command
02747  ******************************************************************************/
02748 
02749 /*!
02750  * @brief HW_CAU_RADR_CA3 - General Purpose Register 3 - Reverse and Add to Register command (WO)
02751  *
02752  * Reset value: 0x00000000U
02753  */
02754 typedef union _hw_cau_radr_ca3
02755 {
02756     uint32_t U;
02757     struct _hw_cau_radr_ca3_bitfields
02758     {
02759         uint32_t CA3 : 32;             /*!< [31:0] CA3 */
02760     } B;
02761 } hw_cau_radr_ca3_t;
02762 
02763 /*!
02764  * @name Constants and macros for entire CAU_RADR_CA3 register
02765  */
02766 /*@{*/
02767 #define HW_CAU_RADR_CA3_ADDR(x)  ((x) + 0x914U)
02768 
02769 #define HW_CAU_RADR_CA3(x)       (*(__O hw_cau_radr_ca3_t *) HW_CAU_RADR_CA3_ADDR(x))
02770 #define HW_CAU_RADR_CA3_WR(x, v) (ADDRESS_WRITE(hw_cau_radr_ca3_t, HW_CAU_RADR_CA3_ADDR(x), v))
02771 /*@}*/
02772 
02773 /*
02774  * Constants & macros for individual CAU_RADR_CA3 bitfields
02775  */
02776 
02777 /*!
02778  * @name Register CAU_RADR_CA3, field CA3[31:0] (WO)
02779  */
02780 /*@{*/
02781 #define BP_CAU_RADR_CA3_CA3  (0U)          /*!< Bit position for CAU_RADR_CA3_CA3. */
02782 #define BM_CAU_RADR_CA3_CA3  (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CA3_CA3. */
02783 #define BS_CAU_RADR_CA3_CA3  (32U)         /*!< Bit field size in bits for CAU_RADR_CA3_CA3. */
02784 
02785 /*! @brief Format value for bitfield CAU_RADR_CA3_CA3. */
02786 #define BF_CAU_RADR_CA3_CA3(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CA3_CA3) & BM_CAU_RADR_CA3_CA3)
02787 /*@}*/
02788 
02789 /*******************************************************************************
02790  * HW_CAU_RADR_CA4 - General Purpose Register 4 - Reverse and Add to Register command
02791  ******************************************************************************/
02792 
02793 /*!
02794  * @brief HW_CAU_RADR_CA4 - General Purpose Register 4 - Reverse and Add to Register command (WO)
02795  *
02796  * Reset value: 0x00000000U
02797  */
02798 typedef union _hw_cau_radr_ca4
02799 {
02800     uint32_t U;
02801     struct _hw_cau_radr_ca4_bitfields
02802     {
02803         uint32_t CA4 : 32;             /*!< [31:0] CA4 */
02804     } B;
02805 } hw_cau_radr_ca4_t;
02806 
02807 /*!
02808  * @name Constants and macros for entire CAU_RADR_CA4 register
02809  */
02810 /*@{*/
02811 #define HW_CAU_RADR_CA4_ADDR(x)  ((x) + 0x918U)
02812 
02813 #define HW_CAU_RADR_CA4(x)       (*(__O hw_cau_radr_ca4_t *) HW_CAU_RADR_CA4_ADDR(x))
02814 #define HW_CAU_RADR_CA4_WR(x, v) (ADDRESS_WRITE(hw_cau_radr_ca4_t, HW_CAU_RADR_CA4_ADDR(x), v))
02815 /*@}*/
02816 
02817 /*
02818  * Constants & macros for individual CAU_RADR_CA4 bitfields
02819  */
02820 
02821 /*!
02822  * @name Register CAU_RADR_CA4, field CA4[31:0] (WO)
02823  */
02824 /*@{*/
02825 #define BP_CAU_RADR_CA4_CA4  (0U)          /*!< Bit position for CAU_RADR_CA4_CA4. */
02826 #define BM_CAU_RADR_CA4_CA4  (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CA4_CA4. */
02827 #define BS_CAU_RADR_CA4_CA4  (32U)         /*!< Bit field size in bits for CAU_RADR_CA4_CA4. */
02828 
02829 /*! @brief Format value for bitfield CAU_RADR_CA4_CA4. */
02830 #define BF_CAU_RADR_CA4_CA4(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CA4_CA4) & BM_CAU_RADR_CA4_CA4)
02831 /*@}*/
02832 
02833 /*******************************************************************************
02834  * HW_CAU_RADR_CA5 - General Purpose Register 5 - Reverse and Add to Register command
02835  ******************************************************************************/
02836 
02837 /*!
02838  * @brief HW_CAU_RADR_CA5 - General Purpose Register 5 - Reverse and Add to Register command (WO)
02839  *
02840  * Reset value: 0x00000000U
02841  */
02842 typedef union _hw_cau_radr_ca5
02843 {
02844     uint32_t U;
02845     struct _hw_cau_radr_ca5_bitfields
02846     {
02847         uint32_t CA5 : 32;             /*!< [31:0] CA5 */
02848     } B;
02849 } hw_cau_radr_ca5_t;
02850 
02851 /*!
02852  * @name Constants and macros for entire CAU_RADR_CA5 register
02853  */
02854 /*@{*/
02855 #define HW_CAU_RADR_CA5_ADDR(x)  ((x) + 0x91CU)
02856 
02857 #define HW_CAU_RADR_CA5(x)       (*(__O hw_cau_radr_ca5_t *) HW_CAU_RADR_CA5_ADDR(x))
02858 #define HW_CAU_RADR_CA5_WR(x, v) (ADDRESS_WRITE(hw_cau_radr_ca5_t, HW_CAU_RADR_CA5_ADDR(x), v))
02859 /*@}*/
02860 
02861 /*
02862  * Constants & macros for individual CAU_RADR_CA5 bitfields
02863  */
02864 
02865 /*!
02866  * @name Register CAU_RADR_CA5, field CA5[31:0] (WO)
02867  */
02868 /*@{*/
02869 #define BP_CAU_RADR_CA5_CA5  (0U)          /*!< Bit position for CAU_RADR_CA5_CA5. */
02870 #define BM_CAU_RADR_CA5_CA5  (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CA5_CA5. */
02871 #define BS_CAU_RADR_CA5_CA5  (32U)         /*!< Bit field size in bits for CAU_RADR_CA5_CA5. */
02872 
02873 /*! @brief Format value for bitfield CAU_RADR_CA5_CA5. */
02874 #define BF_CAU_RADR_CA5_CA5(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CA5_CA5) & BM_CAU_RADR_CA5_CA5)
02875 /*@}*/
02876 
02877 /*******************************************************************************
02878  * HW_CAU_RADR_CA6 - General Purpose Register 6 - Reverse and Add to Register command
02879  ******************************************************************************/
02880 
02881 /*!
02882  * @brief HW_CAU_RADR_CA6 - General Purpose Register 6 - Reverse and Add to Register command (WO)
02883  *
02884  * Reset value: 0x00000000U
02885  */
02886 typedef union _hw_cau_radr_ca6
02887 {
02888     uint32_t U;
02889     struct _hw_cau_radr_ca6_bitfields
02890     {
02891         uint32_t CA6 : 32;             /*!< [31:0] CA6 */
02892     } B;
02893 } hw_cau_radr_ca6_t;
02894 
02895 /*!
02896  * @name Constants and macros for entire CAU_RADR_CA6 register
02897  */
02898 /*@{*/
02899 #define HW_CAU_RADR_CA6_ADDR(x)  ((x) + 0x920U)
02900 
02901 #define HW_CAU_RADR_CA6(x)       (*(__O hw_cau_radr_ca6_t *) HW_CAU_RADR_CA6_ADDR(x))
02902 #define HW_CAU_RADR_CA6_WR(x, v) (ADDRESS_WRITE(hw_cau_radr_ca6_t, HW_CAU_RADR_CA6_ADDR(x), v))
02903 /*@}*/
02904 
02905 /*
02906  * Constants & macros for individual CAU_RADR_CA6 bitfields
02907  */
02908 
02909 /*!
02910  * @name Register CAU_RADR_CA6, field CA6[31:0] (WO)
02911  */
02912 /*@{*/
02913 #define BP_CAU_RADR_CA6_CA6  (0U)          /*!< Bit position for CAU_RADR_CA6_CA6. */
02914 #define BM_CAU_RADR_CA6_CA6  (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CA6_CA6. */
02915 #define BS_CAU_RADR_CA6_CA6  (32U)         /*!< Bit field size in bits for CAU_RADR_CA6_CA6. */
02916 
02917 /*! @brief Format value for bitfield CAU_RADR_CA6_CA6. */
02918 #define BF_CAU_RADR_CA6_CA6(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CA6_CA6) & BM_CAU_RADR_CA6_CA6)
02919 /*@}*/
02920 
02921 /*******************************************************************************
02922  * HW_CAU_RADR_CA7 - General Purpose Register 7 - Reverse and Add to Register command
02923  ******************************************************************************/
02924 
02925 /*!
02926  * @brief HW_CAU_RADR_CA7 - General Purpose Register 7 - Reverse and Add to Register command (WO)
02927  *
02928  * Reset value: 0x00000000U
02929  */
02930 typedef union _hw_cau_radr_ca7
02931 {
02932     uint32_t U;
02933     struct _hw_cau_radr_ca7_bitfields
02934     {
02935         uint32_t CA7 : 32;             /*!< [31:0] CA7 */
02936     } B;
02937 } hw_cau_radr_ca7_t;
02938 
02939 /*!
02940  * @name Constants and macros for entire CAU_RADR_CA7 register
02941  */
02942 /*@{*/
02943 #define HW_CAU_RADR_CA7_ADDR(x)  ((x) + 0x924U)
02944 
02945 #define HW_CAU_RADR_CA7(x)       (*(__O hw_cau_radr_ca7_t *) HW_CAU_RADR_CA7_ADDR(x))
02946 #define HW_CAU_RADR_CA7_WR(x, v) (ADDRESS_WRITE(hw_cau_radr_ca7_t, HW_CAU_RADR_CA7_ADDR(x), v))
02947 /*@}*/
02948 
02949 /*
02950  * Constants & macros for individual CAU_RADR_CA7 bitfields
02951  */
02952 
02953 /*!
02954  * @name Register CAU_RADR_CA7, field CA7[31:0] (WO)
02955  */
02956 /*@{*/
02957 #define BP_CAU_RADR_CA7_CA7  (0U)          /*!< Bit position for CAU_RADR_CA7_CA7. */
02958 #define BM_CAU_RADR_CA7_CA7  (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CA7_CA7. */
02959 #define BS_CAU_RADR_CA7_CA7  (32U)         /*!< Bit field size in bits for CAU_RADR_CA7_CA7. */
02960 
02961 /*! @brief Format value for bitfield CAU_RADR_CA7_CA7. */
02962 #define BF_CAU_RADR_CA7_CA7(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CA7_CA7) & BM_CAU_RADR_CA7_CA7)
02963 /*@}*/
02964 
02965 /*******************************************************************************
02966  * HW_CAU_RADR_CA8 - General Purpose Register 8 - Reverse and Add to Register command
02967  ******************************************************************************/
02968 
02969 /*!
02970  * @brief HW_CAU_RADR_CA8 - General Purpose Register 8 - Reverse and Add to Register command (WO)
02971  *
02972  * Reset value: 0x00000000U
02973  */
02974 typedef union _hw_cau_radr_ca8
02975 {
02976     uint32_t U;
02977     struct _hw_cau_radr_ca8_bitfields
02978     {
02979         uint32_t CA8 : 32;             /*!< [31:0] CA8 */
02980     } B;
02981 } hw_cau_radr_ca8_t;
02982 
02983 /*!
02984  * @name Constants and macros for entire CAU_RADR_CA8 register
02985  */
02986 /*@{*/
02987 #define HW_CAU_RADR_CA8_ADDR(x)  ((x) + 0x928U)
02988 
02989 #define HW_CAU_RADR_CA8(x)       (*(__O hw_cau_radr_ca8_t *) HW_CAU_RADR_CA8_ADDR(x))
02990 #define HW_CAU_RADR_CA8_WR(x, v) (ADDRESS_WRITE(hw_cau_radr_ca8_t, HW_CAU_RADR_CA8_ADDR(x), v))
02991 /*@}*/
02992 
02993 /*
02994  * Constants & macros for individual CAU_RADR_CA8 bitfields
02995  */
02996 
02997 /*!
02998  * @name Register CAU_RADR_CA8, field CA8[31:0] (WO)
02999  */
03000 /*@{*/
03001 #define BP_CAU_RADR_CA8_CA8  (0U)          /*!< Bit position for CAU_RADR_CA8_CA8. */
03002 #define BM_CAU_RADR_CA8_CA8  (0xFFFFFFFFU) /*!< Bit mask for CAU_RADR_CA8_CA8. */
03003 #define BS_CAU_RADR_CA8_CA8  (32U)         /*!< Bit field size in bits for CAU_RADR_CA8_CA8. */
03004 
03005 /*! @brief Format value for bitfield CAU_RADR_CA8_CA8. */
03006 #define BF_CAU_RADR_CA8_CA8(v) ((uint32_t)((uint32_t)(v) << BP_CAU_RADR_CA8_CA8) & BM_CAU_RADR_CA8_CA8)
03007 /*@}*/
03008 
03009 /*******************************************************************************
03010  * HW_CAU_XOR_CASR - Status register  - Exclusive Or command
03011  ******************************************************************************/
03012 
03013 /*!
03014  * @brief HW_CAU_XOR_CASR - Status register  - Exclusive Or command (WO)
03015  *
03016  * Reset value: 0x20000000U
03017  */
03018 typedef union _hw_cau_xor_casr
03019 {
03020     uint32_t U;
03021     struct _hw_cau_xor_casr_bitfields
03022     {
03023         uint32_t IC : 1;               /*!< [0]  */
03024         uint32_t DPE : 1;              /*!< [1]  */
03025         uint32_t RESERVED0 : 26;       /*!< [27:2]  */
03026         uint32_t VER : 4;              /*!< [31:28] CAU version */
03027     } B;
03028 } hw_cau_xor_casr_t;
03029 
03030 /*!
03031  * @name Constants and macros for entire CAU_XOR_CASR register
03032  */
03033 /*@{*/
03034 #define HW_CAU_XOR_CASR_ADDR(x)  ((x) + 0x980U)
03035 
03036 #define HW_CAU_XOR_CASR(x)       (*(__O hw_cau_xor_casr_t *) HW_CAU_XOR_CASR_ADDR(x))
03037 #define HW_CAU_XOR_CASR_WR(x, v) (ADDRESS_WRITE(hw_cau_xor_casr_t, HW_CAU_XOR_CASR_ADDR(x), v))
03038 /*@}*/
03039 
03040 /*
03041  * Constants & macros for individual CAU_XOR_CASR bitfields
03042  */
03043 
03044 /*!
03045  * @name Register CAU_XOR_CASR, field IC[0] (WO)
03046  *
03047  * Values:
03048  * - 0 - No illegal commands issued
03049  * - 1 - Illegal command issued
03050  */
03051 /*@{*/
03052 #define BP_CAU_XOR_CASR_IC   (0U)          /*!< Bit position for CAU_XOR_CASR_IC. */
03053 #define BM_CAU_XOR_CASR_IC   (0x00000001U) /*!< Bit mask for CAU_XOR_CASR_IC. */
03054 #define BS_CAU_XOR_CASR_IC   (1U)          /*!< Bit field size in bits for CAU_XOR_CASR_IC. */
03055 
03056 /*! @brief Format value for bitfield CAU_XOR_CASR_IC. */
03057 #define BF_CAU_XOR_CASR_IC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CASR_IC) & BM_CAU_XOR_CASR_IC)
03058 /*@}*/
03059 
03060 /*!
03061  * @name Register CAU_XOR_CASR, field DPE[1] (WO)
03062  *
03063  * Values:
03064  * - 0 - No error detected
03065  * - 1 - DES key parity error detected
03066  */
03067 /*@{*/
03068 #define BP_CAU_XOR_CASR_DPE  (1U)          /*!< Bit position for CAU_XOR_CASR_DPE. */
03069 #define BM_CAU_XOR_CASR_DPE  (0x00000002U) /*!< Bit mask for CAU_XOR_CASR_DPE. */
03070 #define BS_CAU_XOR_CASR_DPE  (1U)          /*!< Bit field size in bits for CAU_XOR_CASR_DPE. */
03071 
03072 /*! @brief Format value for bitfield CAU_XOR_CASR_DPE. */
03073 #define BF_CAU_XOR_CASR_DPE(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CASR_DPE) & BM_CAU_XOR_CASR_DPE)
03074 /*@}*/
03075 
03076 /*!
03077  * @name Register CAU_XOR_CASR, field VER[31:28] (WO)
03078  *
03079  * Values:
03080  * - 0001 - Initial CAU version
03081  * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
03082  *     value on this device)
03083  */
03084 /*@{*/
03085 #define BP_CAU_XOR_CASR_VER  (28U)         /*!< Bit position for CAU_XOR_CASR_VER. */
03086 #define BM_CAU_XOR_CASR_VER  (0xF0000000U) /*!< Bit mask for CAU_XOR_CASR_VER. */
03087 #define BS_CAU_XOR_CASR_VER  (4U)          /*!< Bit field size in bits for CAU_XOR_CASR_VER. */
03088 
03089 /*! @brief Format value for bitfield CAU_XOR_CASR_VER. */
03090 #define BF_CAU_XOR_CASR_VER(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CASR_VER) & BM_CAU_XOR_CASR_VER)
03091 /*@}*/
03092 
03093 /*******************************************************************************
03094  * HW_CAU_XOR_CAA - Accumulator register - Exclusive Or command
03095  ******************************************************************************/
03096 
03097 /*!
03098  * @brief HW_CAU_XOR_CAA - Accumulator register - Exclusive Or command (WO)
03099  *
03100  * Reset value: 0x00000000U
03101  */
03102 typedef union _hw_cau_xor_caa
03103 {
03104     uint32_t U;
03105     struct _hw_cau_xor_caa_bitfields
03106     {
03107         uint32_t ACC : 32;             /*!< [31:0] ACC */
03108     } B;
03109 } hw_cau_xor_caa_t;
03110 
03111 /*!
03112  * @name Constants and macros for entire CAU_XOR_CAA register
03113  */
03114 /*@{*/
03115 #define HW_CAU_XOR_CAA_ADDR(x)   ((x) + 0x984U)
03116 
03117 #define HW_CAU_XOR_CAA(x)        (*(__O hw_cau_xor_caa_t *) HW_CAU_XOR_CAA_ADDR(x))
03118 #define HW_CAU_XOR_CAA_WR(x, v)  (ADDRESS_WRITE(hw_cau_xor_caa_t, HW_CAU_XOR_CAA_ADDR(x), v))
03119 /*@}*/
03120 
03121 /*
03122  * Constants & macros for individual CAU_XOR_CAA bitfields
03123  */
03124 
03125 /*!
03126  * @name Register CAU_XOR_CAA, field ACC[31:0] (WO)
03127  */
03128 /*@{*/
03129 #define BP_CAU_XOR_CAA_ACC   (0U)          /*!< Bit position for CAU_XOR_CAA_ACC. */
03130 #define BM_CAU_XOR_CAA_ACC   (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CAA_ACC. */
03131 #define BS_CAU_XOR_CAA_ACC   (32U)         /*!< Bit field size in bits for CAU_XOR_CAA_ACC. */
03132 
03133 /*! @brief Format value for bitfield CAU_XOR_CAA_ACC. */
03134 #define BF_CAU_XOR_CAA_ACC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CAA_ACC) & BM_CAU_XOR_CAA_ACC)
03135 /*@}*/
03136 
03137 /*******************************************************************************
03138  * HW_CAU_XOR_CA0 - General Purpose Register 0 - Exclusive Or command
03139  ******************************************************************************/
03140 
03141 /*!
03142  * @brief HW_CAU_XOR_CA0 - General Purpose Register 0 - Exclusive Or command (WO)
03143  *
03144  * Reset value: 0x00000000U
03145  */
03146 typedef union _hw_cau_xor_ca0
03147 {
03148     uint32_t U;
03149     struct _hw_cau_xor_ca0_bitfields
03150     {
03151         uint32_t CA0 : 32;             /*!< [31:0] CA0 */
03152     } B;
03153 } hw_cau_xor_ca0_t;
03154 
03155 /*!
03156  * @name Constants and macros for entire CAU_XOR_CA0 register
03157  */
03158 /*@{*/
03159 #define HW_CAU_XOR_CA0_ADDR(x)   ((x) + 0x988U)
03160 
03161 #define HW_CAU_XOR_CA0(x)        (*(__O hw_cau_xor_ca0_t *) HW_CAU_XOR_CA0_ADDR(x))
03162 #define HW_CAU_XOR_CA0_WR(x, v)  (ADDRESS_WRITE(hw_cau_xor_ca0_t, HW_CAU_XOR_CA0_ADDR(x), v))
03163 /*@}*/
03164 
03165 /*
03166  * Constants & macros for individual CAU_XOR_CA0 bitfields
03167  */
03168 
03169 /*!
03170  * @name Register CAU_XOR_CA0, field CA0[31:0] (WO)
03171  */
03172 /*@{*/
03173 #define BP_CAU_XOR_CA0_CA0   (0U)          /*!< Bit position for CAU_XOR_CA0_CA0. */
03174 #define BM_CAU_XOR_CA0_CA0   (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CA0_CA0. */
03175 #define BS_CAU_XOR_CA0_CA0   (32U)         /*!< Bit field size in bits for CAU_XOR_CA0_CA0. */
03176 
03177 /*! @brief Format value for bitfield CAU_XOR_CA0_CA0. */
03178 #define BF_CAU_XOR_CA0_CA0(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CA0_CA0) & BM_CAU_XOR_CA0_CA0)
03179 /*@}*/
03180 
03181 /*******************************************************************************
03182  * HW_CAU_XOR_CA1 - General Purpose Register 1 - Exclusive Or command
03183  ******************************************************************************/
03184 
03185 /*!
03186  * @brief HW_CAU_XOR_CA1 - General Purpose Register 1 - Exclusive Or command (WO)
03187  *
03188  * Reset value: 0x00000000U
03189  */
03190 typedef union _hw_cau_xor_ca1
03191 {
03192     uint32_t U;
03193     struct _hw_cau_xor_ca1_bitfields
03194     {
03195         uint32_t CA1 : 32;             /*!< [31:0] CA1 */
03196     } B;
03197 } hw_cau_xor_ca1_t;
03198 
03199 /*!
03200  * @name Constants and macros for entire CAU_XOR_CA1 register
03201  */
03202 /*@{*/
03203 #define HW_CAU_XOR_CA1_ADDR(x)   ((x) + 0x98CU)
03204 
03205 #define HW_CAU_XOR_CA1(x)        (*(__O hw_cau_xor_ca1_t *) HW_CAU_XOR_CA1_ADDR(x))
03206 #define HW_CAU_XOR_CA1_WR(x, v)  (ADDRESS_WRITE(hw_cau_xor_ca1_t, HW_CAU_XOR_CA1_ADDR(x), v))
03207 /*@}*/
03208 
03209 /*
03210  * Constants & macros for individual CAU_XOR_CA1 bitfields
03211  */
03212 
03213 /*!
03214  * @name Register CAU_XOR_CA1, field CA1[31:0] (WO)
03215  */
03216 /*@{*/
03217 #define BP_CAU_XOR_CA1_CA1   (0U)          /*!< Bit position for CAU_XOR_CA1_CA1. */
03218 #define BM_CAU_XOR_CA1_CA1   (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CA1_CA1. */
03219 #define BS_CAU_XOR_CA1_CA1   (32U)         /*!< Bit field size in bits for CAU_XOR_CA1_CA1. */
03220 
03221 /*! @brief Format value for bitfield CAU_XOR_CA1_CA1. */
03222 #define BF_CAU_XOR_CA1_CA1(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CA1_CA1) & BM_CAU_XOR_CA1_CA1)
03223 /*@}*/
03224 
03225 /*******************************************************************************
03226  * HW_CAU_XOR_CA2 - General Purpose Register 2 - Exclusive Or command
03227  ******************************************************************************/
03228 
03229 /*!
03230  * @brief HW_CAU_XOR_CA2 - General Purpose Register 2 - Exclusive Or command (WO)
03231  *
03232  * Reset value: 0x00000000U
03233  */
03234 typedef union _hw_cau_xor_ca2
03235 {
03236     uint32_t U;
03237     struct _hw_cau_xor_ca2_bitfields
03238     {
03239         uint32_t CA2 : 32;             /*!< [31:0] CA2 */
03240     } B;
03241 } hw_cau_xor_ca2_t;
03242 
03243 /*!
03244  * @name Constants and macros for entire CAU_XOR_CA2 register
03245  */
03246 /*@{*/
03247 #define HW_CAU_XOR_CA2_ADDR(x)   ((x) + 0x990U)
03248 
03249 #define HW_CAU_XOR_CA2(x)        (*(__O hw_cau_xor_ca2_t *) HW_CAU_XOR_CA2_ADDR(x))
03250 #define HW_CAU_XOR_CA2_WR(x, v)  (ADDRESS_WRITE(hw_cau_xor_ca2_t, HW_CAU_XOR_CA2_ADDR(x), v))
03251 /*@}*/
03252 
03253 /*
03254  * Constants & macros for individual CAU_XOR_CA2 bitfields
03255  */
03256 
03257 /*!
03258  * @name Register CAU_XOR_CA2, field CA2[31:0] (WO)
03259  */
03260 /*@{*/
03261 #define BP_CAU_XOR_CA2_CA2   (0U)          /*!< Bit position for CAU_XOR_CA2_CA2. */
03262 #define BM_CAU_XOR_CA2_CA2   (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CA2_CA2. */
03263 #define BS_CAU_XOR_CA2_CA2   (32U)         /*!< Bit field size in bits for CAU_XOR_CA2_CA2. */
03264 
03265 /*! @brief Format value for bitfield CAU_XOR_CA2_CA2. */
03266 #define BF_CAU_XOR_CA2_CA2(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CA2_CA2) & BM_CAU_XOR_CA2_CA2)
03267 /*@}*/
03268 
03269 /*******************************************************************************
03270  * HW_CAU_XOR_CA3 - General Purpose Register 3 - Exclusive Or command
03271  ******************************************************************************/
03272 
03273 /*!
03274  * @brief HW_CAU_XOR_CA3 - General Purpose Register 3 - Exclusive Or command (WO)
03275  *
03276  * Reset value: 0x00000000U
03277  */
03278 typedef union _hw_cau_xor_ca3
03279 {
03280     uint32_t U;
03281     struct _hw_cau_xor_ca3_bitfields
03282     {
03283         uint32_t CA3 : 32;             /*!< [31:0] CA3 */
03284     } B;
03285 } hw_cau_xor_ca3_t;
03286 
03287 /*!
03288  * @name Constants and macros for entire CAU_XOR_CA3 register
03289  */
03290 /*@{*/
03291 #define HW_CAU_XOR_CA3_ADDR(x)   ((x) + 0x994U)
03292 
03293 #define HW_CAU_XOR_CA3(x)        (*(__O hw_cau_xor_ca3_t *) HW_CAU_XOR_CA3_ADDR(x))
03294 #define HW_CAU_XOR_CA3_WR(x, v)  (ADDRESS_WRITE(hw_cau_xor_ca3_t, HW_CAU_XOR_CA3_ADDR(x), v))
03295 /*@}*/
03296 
03297 /*
03298  * Constants & macros for individual CAU_XOR_CA3 bitfields
03299  */
03300 
03301 /*!
03302  * @name Register CAU_XOR_CA3, field CA3[31:0] (WO)
03303  */
03304 /*@{*/
03305 #define BP_CAU_XOR_CA3_CA3   (0U)          /*!< Bit position for CAU_XOR_CA3_CA3. */
03306 #define BM_CAU_XOR_CA3_CA3   (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CA3_CA3. */
03307 #define BS_CAU_XOR_CA3_CA3   (32U)         /*!< Bit field size in bits for CAU_XOR_CA3_CA3. */
03308 
03309 /*! @brief Format value for bitfield CAU_XOR_CA3_CA3. */
03310 #define BF_CAU_XOR_CA3_CA3(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CA3_CA3) & BM_CAU_XOR_CA3_CA3)
03311 /*@}*/
03312 
03313 /*******************************************************************************
03314  * HW_CAU_XOR_CA4 - General Purpose Register 4 - Exclusive Or command
03315  ******************************************************************************/
03316 
03317 /*!
03318  * @brief HW_CAU_XOR_CA4 - General Purpose Register 4 - Exclusive Or command (WO)
03319  *
03320  * Reset value: 0x00000000U
03321  */
03322 typedef union _hw_cau_xor_ca4
03323 {
03324     uint32_t U;
03325     struct _hw_cau_xor_ca4_bitfields
03326     {
03327         uint32_t CA4 : 32;             /*!< [31:0] CA4 */
03328     } B;
03329 } hw_cau_xor_ca4_t;
03330 
03331 /*!
03332  * @name Constants and macros for entire CAU_XOR_CA4 register
03333  */
03334 /*@{*/
03335 #define HW_CAU_XOR_CA4_ADDR(x)   ((x) + 0x998U)
03336 
03337 #define HW_CAU_XOR_CA4(x)        (*(__O hw_cau_xor_ca4_t *) HW_CAU_XOR_CA4_ADDR(x))
03338 #define HW_CAU_XOR_CA4_WR(x, v)  (ADDRESS_WRITE(hw_cau_xor_ca4_t, HW_CAU_XOR_CA4_ADDR(x), v))
03339 /*@}*/
03340 
03341 /*
03342  * Constants & macros for individual CAU_XOR_CA4 bitfields
03343  */
03344 
03345 /*!
03346  * @name Register CAU_XOR_CA4, field CA4[31:0] (WO)
03347  */
03348 /*@{*/
03349 #define BP_CAU_XOR_CA4_CA4   (0U)          /*!< Bit position for CAU_XOR_CA4_CA4. */
03350 #define BM_CAU_XOR_CA4_CA4   (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CA4_CA4. */
03351 #define BS_CAU_XOR_CA4_CA4   (32U)         /*!< Bit field size in bits for CAU_XOR_CA4_CA4. */
03352 
03353 /*! @brief Format value for bitfield CAU_XOR_CA4_CA4. */
03354 #define BF_CAU_XOR_CA4_CA4(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CA4_CA4) & BM_CAU_XOR_CA4_CA4)
03355 /*@}*/
03356 
03357 /*******************************************************************************
03358  * HW_CAU_XOR_CA5 - General Purpose Register 5 - Exclusive Or command
03359  ******************************************************************************/
03360 
03361 /*!
03362  * @brief HW_CAU_XOR_CA5 - General Purpose Register 5 - Exclusive Or command (WO)
03363  *
03364  * Reset value: 0x00000000U
03365  */
03366 typedef union _hw_cau_xor_ca5
03367 {
03368     uint32_t U;
03369     struct _hw_cau_xor_ca5_bitfields
03370     {
03371         uint32_t CA5 : 32;             /*!< [31:0] CA5 */
03372     } B;
03373 } hw_cau_xor_ca5_t;
03374 
03375 /*!
03376  * @name Constants and macros for entire CAU_XOR_CA5 register
03377  */
03378 /*@{*/
03379 #define HW_CAU_XOR_CA5_ADDR(x)   ((x) + 0x99CU)
03380 
03381 #define HW_CAU_XOR_CA5(x)        (*(__O hw_cau_xor_ca5_t *) HW_CAU_XOR_CA5_ADDR(x))
03382 #define HW_CAU_XOR_CA5_WR(x, v)  (ADDRESS_WRITE(hw_cau_xor_ca5_t, HW_CAU_XOR_CA5_ADDR(x), v))
03383 /*@}*/
03384 
03385 /*
03386  * Constants & macros for individual CAU_XOR_CA5 bitfields
03387  */
03388 
03389 /*!
03390  * @name Register CAU_XOR_CA5, field CA5[31:0] (WO)
03391  */
03392 /*@{*/
03393 #define BP_CAU_XOR_CA5_CA5   (0U)          /*!< Bit position for CAU_XOR_CA5_CA5. */
03394 #define BM_CAU_XOR_CA5_CA5   (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CA5_CA5. */
03395 #define BS_CAU_XOR_CA5_CA5   (32U)         /*!< Bit field size in bits for CAU_XOR_CA5_CA5. */
03396 
03397 /*! @brief Format value for bitfield CAU_XOR_CA5_CA5. */
03398 #define BF_CAU_XOR_CA5_CA5(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CA5_CA5) & BM_CAU_XOR_CA5_CA5)
03399 /*@}*/
03400 
03401 /*******************************************************************************
03402  * HW_CAU_XOR_CA6 - General Purpose Register 6 - Exclusive Or command
03403  ******************************************************************************/
03404 
03405 /*!
03406  * @brief HW_CAU_XOR_CA6 - General Purpose Register 6 - Exclusive Or command (WO)
03407  *
03408  * Reset value: 0x00000000U
03409  */
03410 typedef union _hw_cau_xor_ca6
03411 {
03412     uint32_t U;
03413     struct _hw_cau_xor_ca6_bitfields
03414     {
03415         uint32_t CA6 : 32;             /*!< [31:0] CA6 */
03416     } B;
03417 } hw_cau_xor_ca6_t;
03418 
03419 /*!
03420  * @name Constants and macros for entire CAU_XOR_CA6 register
03421  */
03422 /*@{*/
03423 #define HW_CAU_XOR_CA6_ADDR(x)   ((x) + 0x9A0U)
03424 
03425 #define HW_CAU_XOR_CA6(x)        (*(__O hw_cau_xor_ca6_t *) HW_CAU_XOR_CA6_ADDR(x))
03426 #define HW_CAU_XOR_CA6_WR(x, v)  (ADDRESS_WRITE(hw_cau_xor_ca6_t, HW_CAU_XOR_CA6_ADDR(x), v))
03427 /*@}*/
03428 
03429 /*
03430  * Constants & macros for individual CAU_XOR_CA6 bitfields
03431  */
03432 
03433 /*!
03434  * @name Register CAU_XOR_CA6, field CA6[31:0] (WO)
03435  */
03436 /*@{*/
03437 #define BP_CAU_XOR_CA6_CA6   (0U)          /*!< Bit position for CAU_XOR_CA6_CA6. */
03438 #define BM_CAU_XOR_CA6_CA6   (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CA6_CA6. */
03439 #define BS_CAU_XOR_CA6_CA6   (32U)         /*!< Bit field size in bits for CAU_XOR_CA6_CA6. */
03440 
03441 /*! @brief Format value for bitfield CAU_XOR_CA6_CA6. */
03442 #define BF_CAU_XOR_CA6_CA6(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CA6_CA6) & BM_CAU_XOR_CA6_CA6)
03443 /*@}*/
03444 
03445 /*******************************************************************************
03446  * HW_CAU_XOR_CA7 - General Purpose Register 7 - Exclusive Or command
03447  ******************************************************************************/
03448 
03449 /*!
03450  * @brief HW_CAU_XOR_CA7 - General Purpose Register 7 - Exclusive Or command (WO)
03451  *
03452  * Reset value: 0x00000000U
03453  */
03454 typedef union _hw_cau_xor_ca7
03455 {
03456     uint32_t U;
03457     struct _hw_cau_xor_ca7_bitfields
03458     {
03459         uint32_t CA7 : 32;             /*!< [31:0] CA7 */
03460     } B;
03461 } hw_cau_xor_ca7_t;
03462 
03463 /*!
03464  * @name Constants and macros for entire CAU_XOR_CA7 register
03465  */
03466 /*@{*/
03467 #define HW_CAU_XOR_CA7_ADDR(x)   ((x) + 0x9A4U)
03468 
03469 #define HW_CAU_XOR_CA7(x)        (*(__O hw_cau_xor_ca7_t *) HW_CAU_XOR_CA7_ADDR(x))
03470 #define HW_CAU_XOR_CA7_WR(x, v)  (ADDRESS_WRITE(hw_cau_xor_ca7_t, HW_CAU_XOR_CA7_ADDR(x), v))
03471 /*@}*/
03472 
03473 /*
03474  * Constants & macros for individual CAU_XOR_CA7 bitfields
03475  */
03476 
03477 /*!
03478  * @name Register CAU_XOR_CA7, field CA7[31:0] (WO)
03479  */
03480 /*@{*/
03481 #define BP_CAU_XOR_CA7_CA7   (0U)          /*!< Bit position for CAU_XOR_CA7_CA7. */
03482 #define BM_CAU_XOR_CA7_CA7   (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CA7_CA7. */
03483 #define BS_CAU_XOR_CA7_CA7   (32U)         /*!< Bit field size in bits for CAU_XOR_CA7_CA7. */
03484 
03485 /*! @brief Format value for bitfield CAU_XOR_CA7_CA7. */
03486 #define BF_CAU_XOR_CA7_CA7(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CA7_CA7) & BM_CAU_XOR_CA7_CA7)
03487 /*@}*/
03488 
03489 /*******************************************************************************
03490  * HW_CAU_XOR_CA8 - General Purpose Register 8 - Exclusive Or command
03491  ******************************************************************************/
03492 
03493 /*!
03494  * @brief HW_CAU_XOR_CA8 - General Purpose Register 8 - Exclusive Or command (WO)
03495  *
03496  * Reset value: 0x00000000U
03497  */
03498 typedef union _hw_cau_xor_ca8
03499 {
03500     uint32_t U;
03501     struct _hw_cau_xor_ca8_bitfields
03502     {
03503         uint32_t CA8 : 32;             /*!< [31:0] CA8 */
03504     } B;
03505 } hw_cau_xor_ca8_t;
03506 
03507 /*!
03508  * @name Constants and macros for entire CAU_XOR_CA8 register
03509  */
03510 /*@{*/
03511 #define HW_CAU_XOR_CA8_ADDR(x)   ((x) + 0x9A8U)
03512 
03513 #define HW_CAU_XOR_CA8(x)        (*(__O hw_cau_xor_ca8_t *) HW_CAU_XOR_CA8_ADDR(x))
03514 #define HW_CAU_XOR_CA8_WR(x, v)  (ADDRESS_WRITE(hw_cau_xor_ca8_t, HW_CAU_XOR_CA8_ADDR(x), v))
03515 /*@}*/
03516 
03517 /*
03518  * Constants & macros for individual CAU_XOR_CA8 bitfields
03519  */
03520 
03521 /*!
03522  * @name Register CAU_XOR_CA8, field CA8[31:0] (WO)
03523  */
03524 /*@{*/
03525 #define BP_CAU_XOR_CA8_CA8   (0U)          /*!< Bit position for CAU_XOR_CA8_CA8. */
03526 #define BM_CAU_XOR_CA8_CA8   (0xFFFFFFFFU) /*!< Bit mask for CAU_XOR_CA8_CA8. */
03527 #define BS_CAU_XOR_CA8_CA8   (32U)         /*!< Bit field size in bits for CAU_XOR_CA8_CA8. */
03528 
03529 /*! @brief Format value for bitfield CAU_XOR_CA8_CA8. */
03530 #define BF_CAU_XOR_CA8_CA8(v) ((uint32_t)((uint32_t)(v) << BP_CAU_XOR_CA8_CA8) & BM_CAU_XOR_CA8_CA8)
03531 /*@}*/
03532 
03533 /*******************************************************************************
03534  * HW_CAU_ROTL_CASR - Status register  - Rotate Left command
03535  ******************************************************************************/
03536 
03537 /*!
03538  * @brief HW_CAU_ROTL_CASR - Status register  - Rotate Left command (WO)
03539  *
03540  * Reset value: 0x20000000U
03541  */
03542 typedef union _hw_cau_rotl_casr
03543 {
03544     uint32_t U;
03545     struct _hw_cau_rotl_casr_bitfields
03546     {
03547         uint32_t IC : 1;               /*!< [0]  */
03548         uint32_t DPE : 1;              /*!< [1]  */
03549         uint32_t RESERVED0 : 26;       /*!< [27:2]  */
03550         uint32_t VER : 4;              /*!< [31:28] CAU version */
03551     } B;
03552 } hw_cau_rotl_casr_t;
03553 
03554 /*!
03555  * @name Constants and macros for entire CAU_ROTL_CASR register
03556  */
03557 /*@{*/
03558 #define HW_CAU_ROTL_CASR_ADDR(x) ((x) + 0x9C0U)
03559 
03560 #define HW_CAU_ROTL_CASR(x)      (*(__O hw_cau_rotl_casr_t *) HW_CAU_ROTL_CASR_ADDR(x))
03561 #define HW_CAU_ROTL_CASR_WR(x, v) (ADDRESS_WRITE(hw_cau_rotl_casr_t, HW_CAU_ROTL_CASR_ADDR(x), v))
03562 /*@}*/
03563 
03564 /*
03565  * Constants & macros for individual CAU_ROTL_CASR bitfields
03566  */
03567 
03568 /*!
03569  * @name Register CAU_ROTL_CASR, field IC[0] (WO)
03570  *
03571  * Values:
03572  * - 0 - No illegal commands issued
03573  * - 1 - Illegal command issued
03574  */
03575 /*@{*/
03576 #define BP_CAU_ROTL_CASR_IC  (0U)          /*!< Bit position for CAU_ROTL_CASR_IC. */
03577 #define BM_CAU_ROTL_CASR_IC  (0x00000001U) /*!< Bit mask for CAU_ROTL_CASR_IC. */
03578 #define BS_CAU_ROTL_CASR_IC  (1U)          /*!< Bit field size in bits for CAU_ROTL_CASR_IC. */
03579 
03580 /*! @brief Format value for bitfield CAU_ROTL_CASR_IC. */
03581 #define BF_CAU_ROTL_CASR_IC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CASR_IC) & BM_CAU_ROTL_CASR_IC)
03582 /*@}*/
03583 
03584 /*!
03585  * @name Register CAU_ROTL_CASR, field DPE[1] (WO)
03586  *
03587  * Values:
03588  * - 0 - No error detected
03589  * - 1 - DES key parity error detected
03590  */
03591 /*@{*/
03592 #define BP_CAU_ROTL_CASR_DPE (1U)          /*!< Bit position for CAU_ROTL_CASR_DPE. */
03593 #define BM_CAU_ROTL_CASR_DPE (0x00000002U) /*!< Bit mask for CAU_ROTL_CASR_DPE. */
03594 #define BS_CAU_ROTL_CASR_DPE (1U)          /*!< Bit field size in bits for CAU_ROTL_CASR_DPE. */
03595 
03596 /*! @brief Format value for bitfield CAU_ROTL_CASR_DPE. */
03597 #define BF_CAU_ROTL_CASR_DPE(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CASR_DPE) & BM_CAU_ROTL_CASR_DPE)
03598 /*@}*/
03599 
03600 /*!
03601  * @name Register CAU_ROTL_CASR, field VER[31:28] (WO)
03602  *
03603  * Values:
03604  * - 0001 - Initial CAU version
03605  * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
03606  *     value on this device)
03607  */
03608 /*@{*/
03609 #define BP_CAU_ROTL_CASR_VER (28U)         /*!< Bit position for CAU_ROTL_CASR_VER. */
03610 #define BM_CAU_ROTL_CASR_VER (0xF0000000U) /*!< Bit mask for CAU_ROTL_CASR_VER. */
03611 #define BS_CAU_ROTL_CASR_VER (4U)          /*!< Bit field size in bits for CAU_ROTL_CASR_VER. */
03612 
03613 /*! @brief Format value for bitfield CAU_ROTL_CASR_VER. */
03614 #define BF_CAU_ROTL_CASR_VER(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CASR_VER) & BM_CAU_ROTL_CASR_VER)
03615 /*@}*/
03616 
03617 /*******************************************************************************
03618  * HW_CAU_ROTL_CAA - Accumulator register - Rotate Left command
03619  ******************************************************************************/
03620 
03621 /*!
03622  * @brief HW_CAU_ROTL_CAA - Accumulator register - Rotate Left command (WO)
03623  *
03624  * Reset value: 0x00000000U
03625  */
03626 typedef union _hw_cau_rotl_caa
03627 {
03628     uint32_t U;
03629     struct _hw_cau_rotl_caa_bitfields
03630     {
03631         uint32_t ACC : 32;             /*!< [31:0] ACC */
03632     } B;
03633 } hw_cau_rotl_caa_t;
03634 
03635 /*!
03636  * @name Constants and macros for entire CAU_ROTL_CAA register
03637  */
03638 /*@{*/
03639 #define HW_CAU_ROTL_CAA_ADDR(x)  ((x) + 0x9C4U)
03640 
03641 #define HW_CAU_ROTL_CAA(x)       (*(__O hw_cau_rotl_caa_t *) HW_CAU_ROTL_CAA_ADDR(x))
03642 #define HW_CAU_ROTL_CAA_WR(x, v) (ADDRESS_WRITE(hw_cau_rotl_caa_t, HW_CAU_ROTL_CAA_ADDR(x), v))
03643 /*@}*/
03644 
03645 /*
03646  * Constants & macros for individual CAU_ROTL_CAA bitfields
03647  */
03648 
03649 /*!
03650  * @name Register CAU_ROTL_CAA, field ACC[31:0] (WO)
03651  */
03652 /*@{*/
03653 #define BP_CAU_ROTL_CAA_ACC  (0U)          /*!< Bit position for CAU_ROTL_CAA_ACC. */
03654 #define BM_CAU_ROTL_CAA_ACC  (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CAA_ACC. */
03655 #define BS_CAU_ROTL_CAA_ACC  (32U)         /*!< Bit field size in bits for CAU_ROTL_CAA_ACC. */
03656 
03657 /*! @brief Format value for bitfield CAU_ROTL_CAA_ACC. */
03658 #define BF_CAU_ROTL_CAA_ACC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CAA_ACC) & BM_CAU_ROTL_CAA_ACC)
03659 /*@}*/
03660 
03661 /*******************************************************************************
03662  * HW_CAU_ROTL_CA0 - General Purpose Register 0 - Rotate Left command
03663  ******************************************************************************/
03664 
03665 /*!
03666  * @brief HW_CAU_ROTL_CA0 - General Purpose Register 0 - Rotate Left command (WO)
03667  *
03668  * Reset value: 0x00000000U
03669  */
03670 typedef union _hw_cau_rotl_ca0
03671 {
03672     uint32_t U;
03673     struct _hw_cau_rotl_ca0_bitfields
03674     {
03675         uint32_t CA0 : 32;             /*!< [31:0] CA0 */
03676     } B;
03677 } hw_cau_rotl_ca0_t;
03678 
03679 /*!
03680  * @name Constants and macros for entire CAU_ROTL_CA0 register
03681  */
03682 /*@{*/
03683 #define HW_CAU_ROTL_CA0_ADDR(x)  ((x) + 0x9C8U)
03684 
03685 #define HW_CAU_ROTL_CA0(x)       (*(__O hw_cau_rotl_ca0_t *) HW_CAU_ROTL_CA0_ADDR(x))
03686 #define HW_CAU_ROTL_CA0_WR(x, v) (ADDRESS_WRITE(hw_cau_rotl_ca0_t, HW_CAU_ROTL_CA0_ADDR(x), v))
03687 /*@}*/
03688 
03689 /*
03690  * Constants & macros for individual CAU_ROTL_CA0 bitfields
03691  */
03692 
03693 /*!
03694  * @name Register CAU_ROTL_CA0, field CA0[31:0] (WO)
03695  */
03696 /*@{*/
03697 #define BP_CAU_ROTL_CA0_CA0  (0U)          /*!< Bit position for CAU_ROTL_CA0_CA0. */
03698 #define BM_CAU_ROTL_CA0_CA0  (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CA0_CA0. */
03699 #define BS_CAU_ROTL_CA0_CA0  (32U)         /*!< Bit field size in bits for CAU_ROTL_CA0_CA0. */
03700 
03701 /*! @brief Format value for bitfield CAU_ROTL_CA0_CA0. */
03702 #define BF_CAU_ROTL_CA0_CA0(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CA0_CA0) & BM_CAU_ROTL_CA0_CA0)
03703 /*@}*/
03704 
03705 /*******************************************************************************
03706  * HW_CAU_ROTL_CA1 - General Purpose Register 1 - Rotate Left command
03707  ******************************************************************************/
03708 
03709 /*!
03710  * @brief HW_CAU_ROTL_CA1 - General Purpose Register 1 - Rotate Left command (WO)
03711  *
03712  * Reset value: 0x00000000U
03713  */
03714 typedef union _hw_cau_rotl_ca1
03715 {
03716     uint32_t U;
03717     struct _hw_cau_rotl_ca1_bitfields
03718     {
03719         uint32_t CA1 : 32;             /*!< [31:0] CA1 */
03720     } B;
03721 } hw_cau_rotl_ca1_t;
03722 
03723 /*!
03724  * @name Constants and macros for entire CAU_ROTL_CA1 register
03725  */
03726 /*@{*/
03727 #define HW_CAU_ROTL_CA1_ADDR(x)  ((x) + 0x9CCU)
03728 
03729 #define HW_CAU_ROTL_CA1(x)       (*(__O hw_cau_rotl_ca1_t *) HW_CAU_ROTL_CA1_ADDR(x))
03730 #define HW_CAU_ROTL_CA1_WR(x, v) (ADDRESS_WRITE(hw_cau_rotl_ca1_t, HW_CAU_ROTL_CA1_ADDR(x), v))
03731 /*@}*/
03732 
03733 /*
03734  * Constants & macros for individual CAU_ROTL_CA1 bitfields
03735  */
03736 
03737 /*!
03738  * @name Register CAU_ROTL_CA1, field CA1[31:0] (WO)
03739  */
03740 /*@{*/
03741 #define BP_CAU_ROTL_CA1_CA1  (0U)          /*!< Bit position for CAU_ROTL_CA1_CA1. */
03742 #define BM_CAU_ROTL_CA1_CA1  (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CA1_CA1. */
03743 #define BS_CAU_ROTL_CA1_CA1  (32U)         /*!< Bit field size in bits for CAU_ROTL_CA1_CA1. */
03744 
03745 /*! @brief Format value for bitfield CAU_ROTL_CA1_CA1. */
03746 #define BF_CAU_ROTL_CA1_CA1(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CA1_CA1) & BM_CAU_ROTL_CA1_CA1)
03747 /*@}*/
03748 
03749 /*******************************************************************************
03750  * HW_CAU_ROTL_CA2 - General Purpose Register 2 - Rotate Left command
03751  ******************************************************************************/
03752 
03753 /*!
03754  * @brief HW_CAU_ROTL_CA2 - General Purpose Register 2 - Rotate Left command (WO)
03755  *
03756  * Reset value: 0x00000000U
03757  */
03758 typedef union _hw_cau_rotl_ca2
03759 {
03760     uint32_t U;
03761     struct _hw_cau_rotl_ca2_bitfields
03762     {
03763         uint32_t CA2 : 32;             /*!< [31:0] CA2 */
03764     } B;
03765 } hw_cau_rotl_ca2_t;
03766 
03767 /*!
03768  * @name Constants and macros for entire CAU_ROTL_CA2 register
03769  */
03770 /*@{*/
03771 #define HW_CAU_ROTL_CA2_ADDR(x)  ((x) + 0x9D0U)
03772 
03773 #define HW_CAU_ROTL_CA2(x)       (*(__O hw_cau_rotl_ca2_t *) HW_CAU_ROTL_CA2_ADDR(x))
03774 #define HW_CAU_ROTL_CA2_WR(x, v) (ADDRESS_WRITE(hw_cau_rotl_ca2_t, HW_CAU_ROTL_CA2_ADDR(x), v))
03775 /*@}*/
03776 
03777 /*
03778  * Constants & macros for individual CAU_ROTL_CA2 bitfields
03779  */
03780 
03781 /*!
03782  * @name Register CAU_ROTL_CA2, field CA2[31:0] (WO)
03783  */
03784 /*@{*/
03785 #define BP_CAU_ROTL_CA2_CA2  (0U)          /*!< Bit position for CAU_ROTL_CA2_CA2. */
03786 #define BM_CAU_ROTL_CA2_CA2  (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CA2_CA2. */
03787 #define BS_CAU_ROTL_CA2_CA2  (32U)         /*!< Bit field size in bits for CAU_ROTL_CA2_CA2. */
03788 
03789 /*! @brief Format value for bitfield CAU_ROTL_CA2_CA2. */
03790 #define BF_CAU_ROTL_CA2_CA2(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CA2_CA2) & BM_CAU_ROTL_CA2_CA2)
03791 /*@}*/
03792 
03793 /*******************************************************************************
03794  * HW_CAU_ROTL_CA3 - General Purpose Register 3 - Rotate Left command
03795  ******************************************************************************/
03796 
03797 /*!
03798  * @brief HW_CAU_ROTL_CA3 - General Purpose Register 3 - Rotate Left command (WO)
03799  *
03800  * Reset value: 0x00000000U
03801  */
03802 typedef union _hw_cau_rotl_ca3
03803 {
03804     uint32_t U;
03805     struct _hw_cau_rotl_ca3_bitfields
03806     {
03807         uint32_t CA3 : 32;             /*!< [31:0] CA3 */
03808     } B;
03809 } hw_cau_rotl_ca3_t;
03810 
03811 /*!
03812  * @name Constants and macros for entire CAU_ROTL_CA3 register
03813  */
03814 /*@{*/
03815 #define HW_CAU_ROTL_CA3_ADDR(x)  ((x) + 0x9D4U)
03816 
03817 #define HW_CAU_ROTL_CA3(x)       (*(__O hw_cau_rotl_ca3_t *) HW_CAU_ROTL_CA3_ADDR(x))
03818 #define HW_CAU_ROTL_CA3_WR(x, v) (ADDRESS_WRITE(hw_cau_rotl_ca3_t, HW_CAU_ROTL_CA3_ADDR(x), v))
03819 /*@}*/
03820 
03821 /*
03822  * Constants & macros for individual CAU_ROTL_CA3 bitfields
03823  */
03824 
03825 /*!
03826  * @name Register CAU_ROTL_CA3, field CA3[31:0] (WO)
03827  */
03828 /*@{*/
03829 #define BP_CAU_ROTL_CA3_CA3  (0U)          /*!< Bit position for CAU_ROTL_CA3_CA3. */
03830 #define BM_CAU_ROTL_CA3_CA3  (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CA3_CA3. */
03831 #define BS_CAU_ROTL_CA3_CA3  (32U)         /*!< Bit field size in bits for CAU_ROTL_CA3_CA3. */
03832 
03833 /*! @brief Format value for bitfield CAU_ROTL_CA3_CA3. */
03834 #define BF_CAU_ROTL_CA3_CA3(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CA3_CA3) & BM_CAU_ROTL_CA3_CA3)
03835 /*@}*/
03836 
03837 /*******************************************************************************
03838  * HW_CAU_ROTL_CA4 - General Purpose Register 4 - Rotate Left command
03839  ******************************************************************************/
03840 
03841 /*!
03842  * @brief HW_CAU_ROTL_CA4 - General Purpose Register 4 - Rotate Left command (WO)
03843  *
03844  * Reset value: 0x00000000U
03845  */
03846 typedef union _hw_cau_rotl_ca4
03847 {
03848     uint32_t U;
03849     struct _hw_cau_rotl_ca4_bitfields
03850     {
03851         uint32_t CA4 : 32;             /*!< [31:0] CA4 */
03852     } B;
03853 } hw_cau_rotl_ca4_t;
03854 
03855 /*!
03856  * @name Constants and macros for entire CAU_ROTL_CA4 register
03857  */
03858 /*@{*/
03859 #define HW_CAU_ROTL_CA4_ADDR(x)  ((x) + 0x9D8U)
03860 
03861 #define HW_CAU_ROTL_CA4(x)       (*(__O hw_cau_rotl_ca4_t *) HW_CAU_ROTL_CA4_ADDR(x))
03862 #define HW_CAU_ROTL_CA4_WR(x, v) (ADDRESS_WRITE(hw_cau_rotl_ca4_t, HW_CAU_ROTL_CA4_ADDR(x), v))
03863 /*@}*/
03864 
03865 /*
03866  * Constants & macros for individual CAU_ROTL_CA4 bitfields
03867  */
03868 
03869 /*!
03870  * @name Register CAU_ROTL_CA4, field CA4[31:0] (WO)
03871  */
03872 /*@{*/
03873 #define BP_CAU_ROTL_CA4_CA4  (0U)          /*!< Bit position for CAU_ROTL_CA4_CA4. */
03874 #define BM_CAU_ROTL_CA4_CA4  (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CA4_CA4. */
03875 #define BS_CAU_ROTL_CA4_CA4  (32U)         /*!< Bit field size in bits for CAU_ROTL_CA4_CA4. */
03876 
03877 /*! @brief Format value for bitfield CAU_ROTL_CA4_CA4. */
03878 #define BF_CAU_ROTL_CA4_CA4(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CA4_CA4) & BM_CAU_ROTL_CA4_CA4)
03879 /*@}*/
03880 
03881 /*******************************************************************************
03882  * HW_CAU_ROTL_CA5 - General Purpose Register 5 - Rotate Left command
03883  ******************************************************************************/
03884 
03885 /*!
03886  * @brief HW_CAU_ROTL_CA5 - General Purpose Register 5 - Rotate Left command (WO)
03887  *
03888  * Reset value: 0x00000000U
03889  */
03890 typedef union _hw_cau_rotl_ca5
03891 {
03892     uint32_t U;
03893     struct _hw_cau_rotl_ca5_bitfields
03894     {
03895         uint32_t CA5 : 32;             /*!< [31:0] CA5 */
03896     } B;
03897 } hw_cau_rotl_ca5_t;
03898 
03899 /*!
03900  * @name Constants and macros for entire CAU_ROTL_CA5 register
03901  */
03902 /*@{*/
03903 #define HW_CAU_ROTL_CA5_ADDR(x)  ((x) + 0x9DCU)
03904 
03905 #define HW_CAU_ROTL_CA5(x)       (*(__O hw_cau_rotl_ca5_t *) HW_CAU_ROTL_CA5_ADDR(x))
03906 #define HW_CAU_ROTL_CA5_WR(x, v) (ADDRESS_WRITE(hw_cau_rotl_ca5_t, HW_CAU_ROTL_CA5_ADDR(x), v))
03907 /*@}*/
03908 
03909 /*
03910  * Constants & macros for individual CAU_ROTL_CA5 bitfields
03911  */
03912 
03913 /*!
03914  * @name Register CAU_ROTL_CA5, field CA5[31:0] (WO)
03915  */
03916 /*@{*/
03917 #define BP_CAU_ROTL_CA5_CA5  (0U)          /*!< Bit position for CAU_ROTL_CA5_CA5. */
03918 #define BM_CAU_ROTL_CA5_CA5  (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CA5_CA5. */
03919 #define BS_CAU_ROTL_CA5_CA5  (32U)         /*!< Bit field size in bits for CAU_ROTL_CA5_CA5. */
03920 
03921 /*! @brief Format value for bitfield CAU_ROTL_CA5_CA5. */
03922 #define BF_CAU_ROTL_CA5_CA5(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CA5_CA5) & BM_CAU_ROTL_CA5_CA5)
03923 /*@}*/
03924 
03925 /*******************************************************************************
03926  * HW_CAU_ROTL_CA6 - General Purpose Register 6 - Rotate Left command
03927  ******************************************************************************/
03928 
03929 /*!
03930  * @brief HW_CAU_ROTL_CA6 - General Purpose Register 6 - Rotate Left command (WO)
03931  *
03932  * Reset value: 0x00000000U
03933  */
03934 typedef union _hw_cau_rotl_ca6
03935 {
03936     uint32_t U;
03937     struct _hw_cau_rotl_ca6_bitfields
03938     {
03939         uint32_t CA6 : 32;             /*!< [31:0] CA6 */
03940     } B;
03941 } hw_cau_rotl_ca6_t;
03942 
03943 /*!
03944  * @name Constants and macros for entire CAU_ROTL_CA6 register
03945  */
03946 /*@{*/
03947 #define HW_CAU_ROTL_CA6_ADDR(x)  ((x) + 0x9E0U)
03948 
03949 #define HW_CAU_ROTL_CA6(x)       (*(__O hw_cau_rotl_ca6_t *) HW_CAU_ROTL_CA6_ADDR(x))
03950 #define HW_CAU_ROTL_CA6_WR(x, v) (ADDRESS_WRITE(hw_cau_rotl_ca6_t, HW_CAU_ROTL_CA6_ADDR(x), v))
03951 /*@}*/
03952 
03953 /*
03954  * Constants & macros for individual CAU_ROTL_CA6 bitfields
03955  */
03956 
03957 /*!
03958  * @name Register CAU_ROTL_CA6, field CA6[31:0] (WO)
03959  */
03960 /*@{*/
03961 #define BP_CAU_ROTL_CA6_CA6  (0U)          /*!< Bit position for CAU_ROTL_CA6_CA6. */
03962 #define BM_CAU_ROTL_CA6_CA6  (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CA6_CA6. */
03963 #define BS_CAU_ROTL_CA6_CA6  (32U)         /*!< Bit field size in bits for CAU_ROTL_CA6_CA6. */
03964 
03965 /*! @brief Format value for bitfield CAU_ROTL_CA6_CA6. */
03966 #define BF_CAU_ROTL_CA6_CA6(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CA6_CA6) & BM_CAU_ROTL_CA6_CA6)
03967 /*@}*/
03968 
03969 /*******************************************************************************
03970  * HW_CAU_ROTL_CA7 - General Purpose Register 7 - Rotate Left command
03971  ******************************************************************************/
03972 
03973 /*!
03974  * @brief HW_CAU_ROTL_CA7 - General Purpose Register 7 - Rotate Left command (WO)
03975  *
03976  * Reset value: 0x00000000U
03977  */
03978 typedef union _hw_cau_rotl_ca7
03979 {
03980     uint32_t U;
03981     struct _hw_cau_rotl_ca7_bitfields
03982     {
03983         uint32_t CA7 : 32;             /*!< [31:0] CA7 */
03984     } B;
03985 } hw_cau_rotl_ca7_t;
03986 
03987 /*!
03988  * @name Constants and macros for entire CAU_ROTL_CA7 register
03989  */
03990 /*@{*/
03991 #define HW_CAU_ROTL_CA7_ADDR(x)  ((x) + 0x9E4U)
03992 
03993 #define HW_CAU_ROTL_CA7(x)       (*(__O hw_cau_rotl_ca7_t *) HW_CAU_ROTL_CA7_ADDR(x))
03994 #define HW_CAU_ROTL_CA7_WR(x, v) (ADDRESS_WRITE(hw_cau_rotl_ca7_t, HW_CAU_ROTL_CA7_ADDR(x), v))
03995 /*@}*/
03996 
03997 /*
03998  * Constants & macros for individual CAU_ROTL_CA7 bitfields
03999  */
04000 
04001 /*!
04002  * @name Register CAU_ROTL_CA7, field CA7[31:0] (WO)
04003  */
04004 /*@{*/
04005 #define BP_CAU_ROTL_CA7_CA7  (0U)          /*!< Bit position for CAU_ROTL_CA7_CA7. */
04006 #define BM_CAU_ROTL_CA7_CA7  (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CA7_CA7. */
04007 #define BS_CAU_ROTL_CA7_CA7  (32U)         /*!< Bit field size in bits for CAU_ROTL_CA7_CA7. */
04008 
04009 /*! @brief Format value for bitfield CAU_ROTL_CA7_CA7. */
04010 #define BF_CAU_ROTL_CA7_CA7(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CA7_CA7) & BM_CAU_ROTL_CA7_CA7)
04011 /*@}*/
04012 
04013 /*******************************************************************************
04014  * HW_CAU_ROTL_CA8 - General Purpose Register 8 - Rotate Left command
04015  ******************************************************************************/
04016 
04017 /*!
04018  * @brief HW_CAU_ROTL_CA8 - General Purpose Register 8 - Rotate Left command (WO)
04019  *
04020  * Reset value: 0x00000000U
04021  */
04022 typedef union _hw_cau_rotl_ca8
04023 {
04024     uint32_t U;
04025     struct _hw_cau_rotl_ca8_bitfields
04026     {
04027         uint32_t CA8 : 32;             /*!< [31:0] CA8 */
04028     } B;
04029 } hw_cau_rotl_ca8_t;
04030 
04031 /*!
04032  * @name Constants and macros for entire CAU_ROTL_CA8 register
04033  */
04034 /*@{*/
04035 #define HW_CAU_ROTL_CA8_ADDR(x)  ((x) + 0x9E8U)
04036 
04037 #define HW_CAU_ROTL_CA8(x)       (*(__O hw_cau_rotl_ca8_t *) HW_CAU_ROTL_CA8_ADDR(x))
04038 #define HW_CAU_ROTL_CA8_WR(x, v) (ADDRESS_WRITE(hw_cau_rotl_ca8_t, HW_CAU_ROTL_CA8_ADDR(x), v))
04039 /*@}*/
04040 
04041 /*
04042  * Constants & macros for individual CAU_ROTL_CA8 bitfields
04043  */
04044 
04045 /*!
04046  * @name Register CAU_ROTL_CA8, field CA8[31:0] (WO)
04047  */
04048 /*@{*/
04049 #define BP_CAU_ROTL_CA8_CA8  (0U)          /*!< Bit position for CAU_ROTL_CA8_CA8. */
04050 #define BM_CAU_ROTL_CA8_CA8  (0xFFFFFFFFU) /*!< Bit mask for CAU_ROTL_CA8_CA8. */
04051 #define BS_CAU_ROTL_CA8_CA8  (32U)         /*!< Bit field size in bits for CAU_ROTL_CA8_CA8. */
04052 
04053 /*! @brief Format value for bitfield CAU_ROTL_CA8_CA8. */
04054 #define BF_CAU_ROTL_CA8_CA8(v) ((uint32_t)((uint32_t)(v) << BP_CAU_ROTL_CA8_CA8) & BM_CAU_ROTL_CA8_CA8)
04055 /*@}*/
04056 
04057 /*******************************************************************************
04058  * HW_CAU_AESC_CASR - Status register  - AES Column Operation command
04059  ******************************************************************************/
04060 
04061 /*!
04062  * @brief HW_CAU_AESC_CASR - Status register  - AES Column Operation command (WO)
04063  *
04064  * Reset value: 0x20000000U
04065  */
04066 typedef union _hw_cau_aesc_casr
04067 {
04068     uint32_t U;
04069     struct _hw_cau_aesc_casr_bitfields
04070     {
04071         uint32_t IC : 1;               /*!< [0]  */
04072         uint32_t DPE : 1;              /*!< [1]  */
04073         uint32_t RESERVED0 : 26;       /*!< [27:2]  */
04074         uint32_t VER : 4;              /*!< [31:28] CAU version */
04075     } B;
04076 } hw_cau_aesc_casr_t;
04077 
04078 /*!
04079  * @name Constants and macros for entire CAU_AESC_CASR register
04080  */
04081 /*@{*/
04082 #define HW_CAU_AESC_CASR_ADDR(x) ((x) + 0xB00U)
04083 
04084 #define HW_CAU_AESC_CASR(x)      (*(__O hw_cau_aesc_casr_t *) HW_CAU_AESC_CASR_ADDR(x))
04085 #define HW_CAU_AESC_CASR_WR(x, v) (ADDRESS_WRITE(hw_cau_aesc_casr_t, HW_CAU_AESC_CASR_ADDR(x), v))
04086 /*@}*/
04087 
04088 /*
04089  * Constants & macros for individual CAU_AESC_CASR bitfields
04090  */
04091 
04092 /*!
04093  * @name Register CAU_AESC_CASR, field IC[0] (WO)
04094  *
04095  * Values:
04096  * - 0 - No illegal commands issued
04097  * - 1 - Illegal command issued
04098  */
04099 /*@{*/
04100 #define BP_CAU_AESC_CASR_IC  (0U)          /*!< Bit position for CAU_AESC_CASR_IC. */
04101 #define BM_CAU_AESC_CASR_IC  (0x00000001U) /*!< Bit mask for CAU_AESC_CASR_IC. */
04102 #define BS_CAU_AESC_CASR_IC  (1U)          /*!< Bit field size in bits for CAU_AESC_CASR_IC. */
04103 
04104 /*! @brief Format value for bitfield CAU_AESC_CASR_IC. */
04105 #define BF_CAU_AESC_CASR_IC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CASR_IC) & BM_CAU_AESC_CASR_IC)
04106 /*@}*/
04107 
04108 /*!
04109  * @name Register CAU_AESC_CASR, field DPE[1] (WO)
04110  *
04111  * Values:
04112  * - 0 - No error detected
04113  * - 1 - DES key parity error detected
04114  */
04115 /*@{*/
04116 #define BP_CAU_AESC_CASR_DPE (1U)          /*!< Bit position for CAU_AESC_CASR_DPE. */
04117 #define BM_CAU_AESC_CASR_DPE (0x00000002U) /*!< Bit mask for CAU_AESC_CASR_DPE. */
04118 #define BS_CAU_AESC_CASR_DPE (1U)          /*!< Bit field size in bits for CAU_AESC_CASR_DPE. */
04119 
04120 /*! @brief Format value for bitfield CAU_AESC_CASR_DPE. */
04121 #define BF_CAU_AESC_CASR_DPE(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CASR_DPE) & BM_CAU_AESC_CASR_DPE)
04122 /*@}*/
04123 
04124 /*!
04125  * @name Register CAU_AESC_CASR, field VER[31:28] (WO)
04126  *
04127  * Values:
04128  * - 0001 - Initial CAU version
04129  * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
04130  *     value on this device)
04131  */
04132 /*@{*/
04133 #define BP_CAU_AESC_CASR_VER (28U)         /*!< Bit position for CAU_AESC_CASR_VER. */
04134 #define BM_CAU_AESC_CASR_VER (0xF0000000U) /*!< Bit mask for CAU_AESC_CASR_VER. */
04135 #define BS_CAU_AESC_CASR_VER (4U)          /*!< Bit field size in bits for CAU_AESC_CASR_VER. */
04136 
04137 /*! @brief Format value for bitfield CAU_AESC_CASR_VER. */
04138 #define BF_CAU_AESC_CASR_VER(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CASR_VER) & BM_CAU_AESC_CASR_VER)
04139 /*@}*/
04140 
04141 /*******************************************************************************
04142  * HW_CAU_AESC_CAA - Accumulator register - AES Column Operation command
04143  ******************************************************************************/
04144 
04145 /*!
04146  * @brief HW_CAU_AESC_CAA - Accumulator register - AES Column Operation command (WO)
04147  *
04148  * Reset value: 0x00000000U
04149  */
04150 typedef union _hw_cau_aesc_caa
04151 {
04152     uint32_t U;
04153     struct _hw_cau_aesc_caa_bitfields
04154     {
04155         uint32_t ACC : 32;             /*!< [31:0] ACC */
04156     } B;
04157 } hw_cau_aesc_caa_t;
04158 
04159 /*!
04160  * @name Constants and macros for entire CAU_AESC_CAA register
04161  */
04162 /*@{*/
04163 #define HW_CAU_AESC_CAA_ADDR(x)  ((x) + 0xB04U)
04164 
04165 #define HW_CAU_AESC_CAA(x)       (*(__O hw_cau_aesc_caa_t *) HW_CAU_AESC_CAA_ADDR(x))
04166 #define HW_CAU_AESC_CAA_WR(x, v) (ADDRESS_WRITE(hw_cau_aesc_caa_t, HW_CAU_AESC_CAA_ADDR(x), v))
04167 /*@}*/
04168 
04169 /*
04170  * Constants & macros for individual CAU_AESC_CAA bitfields
04171  */
04172 
04173 /*!
04174  * @name Register CAU_AESC_CAA, field ACC[31:0] (WO)
04175  */
04176 /*@{*/
04177 #define BP_CAU_AESC_CAA_ACC  (0U)          /*!< Bit position for CAU_AESC_CAA_ACC. */
04178 #define BM_CAU_AESC_CAA_ACC  (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CAA_ACC. */
04179 #define BS_CAU_AESC_CAA_ACC  (32U)         /*!< Bit field size in bits for CAU_AESC_CAA_ACC. */
04180 
04181 /*! @brief Format value for bitfield CAU_AESC_CAA_ACC. */
04182 #define BF_CAU_AESC_CAA_ACC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CAA_ACC) & BM_CAU_AESC_CAA_ACC)
04183 /*@}*/
04184 
04185 /*******************************************************************************
04186  * HW_CAU_AESC_CA0 - General Purpose Register 0 - AES Column Operation command
04187  ******************************************************************************/
04188 
04189 /*!
04190  * @brief HW_CAU_AESC_CA0 - General Purpose Register 0 - AES Column Operation command (WO)
04191  *
04192  * Reset value: 0x00000000U
04193  */
04194 typedef union _hw_cau_aesc_ca0
04195 {
04196     uint32_t U;
04197     struct _hw_cau_aesc_ca0_bitfields
04198     {
04199         uint32_t CA0 : 32;             /*!< [31:0] CA0 */
04200     } B;
04201 } hw_cau_aesc_ca0_t;
04202 
04203 /*!
04204  * @name Constants and macros for entire CAU_AESC_CA0 register
04205  */
04206 /*@{*/
04207 #define HW_CAU_AESC_CA0_ADDR(x)  ((x) + 0xB08U)
04208 
04209 #define HW_CAU_AESC_CA0(x)       (*(__O hw_cau_aesc_ca0_t *) HW_CAU_AESC_CA0_ADDR(x))
04210 #define HW_CAU_AESC_CA0_WR(x, v) (ADDRESS_WRITE(hw_cau_aesc_ca0_t, HW_CAU_AESC_CA0_ADDR(x), v))
04211 /*@}*/
04212 
04213 /*
04214  * Constants & macros for individual CAU_AESC_CA0 bitfields
04215  */
04216 
04217 /*!
04218  * @name Register CAU_AESC_CA0, field CA0[31:0] (WO)
04219  */
04220 /*@{*/
04221 #define BP_CAU_AESC_CA0_CA0  (0U)          /*!< Bit position for CAU_AESC_CA0_CA0. */
04222 #define BM_CAU_AESC_CA0_CA0  (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CA0_CA0. */
04223 #define BS_CAU_AESC_CA0_CA0  (32U)         /*!< Bit field size in bits for CAU_AESC_CA0_CA0. */
04224 
04225 /*! @brief Format value for bitfield CAU_AESC_CA0_CA0. */
04226 #define BF_CAU_AESC_CA0_CA0(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CA0_CA0) & BM_CAU_AESC_CA0_CA0)
04227 /*@}*/
04228 
04229 /*******************************************************************************
04230  * HW_CAU_AESC_CA1 - General Purpose Register 1 - AES Column Operation command
04231  ******************************************************************************/
04232 
04233 /*!
04234  * @brief HW_CAU_AESC_CA1 - General Purpose Register 1 - AES Column Operation command (WO)
04235  *
04236  * Reset value: 0x00000000U
04237  */
04238 typedef union _hw_cau_aesc_ca1
04239 {
04240     uint32_t U;
04241     struct _hw_cau_aesc_ca1_bitfields
04242     {
04243         uint32_t CA1 : 32;             /*!< [31:0] CA1 */
04244     } B;
04245 } hw_cau_aesc_ca1_t;
04246 
04247 /*!
04248  * @name Constants and macros for entire CAU_AESC_CA1 register
04249  */
04250 /*@{*/
04251 #define HW_CAU_AESC_CA1_ADDR(x)  ((x) + 0xB0CU)
04252 
04253 #define HW_CAU_AESC_CA1(x)       (*(__O hw_cau_aesc_ca1_t *) HW_CAU_AESC_CA1_ADDR(x))
04254 #define HW_CAU_AESC_CA1_WR(x, v) (ADDRESS_WRITE(hw_cau_aesc_ca1_t, HW_CAU_AESC_CA1_ADDR(x), v))
04255 /*@}*/
04256 
04257 /*
04258  * Constants & macros for individual CAU_AESC_CA1 bitfields
04259  */
04260 
04261 /*!
04262  * @name Register CAU_AESC_CA1, field CA1[31:0] (WO)
04263  */
04264 /*@{*/
04265 #define BP_CAU_AESC_CA1_CA1  (0U)          /*!< Bit position for CAU_AESC_CA1_CA1. */
04266 #define BM_CAU_AESC_CA1_CA1  (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CA1_CA1. */
04267 #define BS_CAU_AESC_CA1_CA1  (32U)         /*!< Bit field size in bits for CAU_AESC_CA1_CA1. */
04268 
04269 /*! @brief Format value for bitfield CAU_AESC_CA1_CA1. */
04270 #define BF_CAU_AESC_CA1_CA1(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CA1_CA1) & BM_CAU_AESC_CA1_CA1)
04271 /*@}*/
04272 
04273 /*******************************************************************************
04274  * HW_CAU_AESC_CA2 - General Purpose Register 2 - AES Column Operation command
04275  ******************************************************************************/
04276 
04277 /*!
04278  * @brief HW_CAU_AESC_CA2 - General Purpose Register 2 - AES Column Operation command (WO)
04279  *
04280  * Reset value: 0x00000000U
04281  */
04282 typedef union _hw_cau_aesc_ca2
04283 {
04284     uint32_t U;
04285     struct _hw_cau_aesc_ca2_bitfields
04286     {
04287         uint32_t CA2 : 32;             /*!< [31:0] CA2 */
04288     } B;
04289 } hw_cau_aesc_ca2_t;
04290 
04291 /*!
04292  * @name Constants and macros for entire CAU_AESC_CA2 register
04293  */
04294 /*@{*/
04295 #define HW_CAU_AESC_CA2_ADDR(x)  ((x) + 0xB10U)
04296 
04297 #define HW_CAU_AESC_CA2(x)       (*(__O hw_cau_aesc_ca2_t *) HW_CAU_AESC_CA2_ADDR(x))
04298 #define HW_CAU_AESC_CA2_WR(x, v) (ADDRESS_WRITE(hw_cau_aesc_ca2_t, HW_CAU_AESC_CA2_ADDR(x), v))
04299 /*@}*/
04300 
04301 /*
04302  * Constants & macros for individual CAU_AESC_CA2 bitfields
04303  */
04304 
04305 /*!
04306  * @name Register CAU_AESC_CA2, field CA2[31:0] (WO)
04307  */
04308 /*@{*/
04309 #define BP_CAU_AESC_CA2_CA2  (0U)          /*!< Bit position for CAU_AESC_CA2_CA2. */
04310 #define BM_CAU_AESC_CA2_CA2  (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CA2_CA2. */
04311 #define BS_CAU_AESC_CA2_CA2  (32U)         /*!< Bit field size in bits for CAU_AESC_CA2_CA2. */
04312 
04313 /*! @brief Format value for bitfield CAU_AESC_CA2_CA2. */
04314 #define BF_CAU_AESC_CA2_CA2(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CA2_CA2) & BM_CAU_AESC_CA2_CA2)
04315 /*@}*/
04316 
04317 /*******************************************************************************
04318  * HW_CAU_AESC_CA3 - General Purpose Register 3 - AES Column Operation command
04319  ******************************************************************************/
04320 
04321 /*!
04322  * @brief HW_CAU_AESC_CA3 - General Purpose Register 3 - AES Column Operation command (WO)
04323  *
04324  * Reset value: 0x00000000U
04325  */
04326 typedef union _hw_cau_aesc_ca3
04327 {
04328     uint32_t U;
04329     struct _hw_cau_aesc_ca3_bitfields
04330     {
04331         uint32_t CA3 : 32;             /*!< [31:0] CA3 */
04332     } B;
04333 } hw_cau_aesc_ca3_t;
04334 
04335 /*!
04336  * @name Constants and macros for entire CAU_AESC_CA3 register
04337  */
04338 /*@{*/
04339 #define HW_CAU_AESC_CA3_ADDR(x)  ((x) + 0xB14U)
04340 
04341 #define HW_CAU_AESC_CA3(x)       (*(__O hw_cau_aesc_ca3_t *) HW_CAU_AESC_CA3_ADDR(x))
04342 #define HW_CAU_AESC_CA3_WR(x, v) (ADDRESS_WRITE(hw_cau_aesc_ca3_t, HW_CAU_AESC_CA3_ADDR(x), v))
04343 /*@}*/
04344 
04345 /*
04346  * Constants & macros for individual CAU_AESC_CA3 bitfields
04347  */
04348 
04349 /*!
04350  * @name Register CAU_AESC_CA3, field CA3[31:0] (WO)
04351  */
04352 /*@{*/
04353 #define BP_CAU_AESC_CA3_CA3  (0U)          /*!< Bit position for CAU_AESC_CA3_CA3. */
04354 #define BM_CAU_AESC_CA3_CA3  (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CA3_CA3. */
04355 #define BS_CAU_AESC_CA3_CA3  (32U)         /*!< Bit field size in bits for CAU_AESC_CA3_CA3. */
04356 
04357 /*! @brief Format value for bitfield CAU_AESC_CA3_CA3. */
04358 #define BF_CAU_AESC_CA3_CA3(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CA3_CA3) & BM_CAU_AESC_CA3_CA3)
04359 /*@}*/
04360 
04361 /*******************************************************************************
04362  * HW_CAU_AESC_CA4 - General Purpose Register 4 - AES Column Operation command
04363  ******************************************************************************/
04364 
04365 /*!
04366  * @brief HW_CAU_AESC_CA4 - General Purpose Register 4 - AES Column Operation command (WO)
04367  *
04368  * Reset value: 0x00000000U
04369  */
04370 typedef union _hw_cau_aesc_ca4
04371 {
04372     uint32_t U;
04373     struct _hw_cau_aesc_ca4_bitfields
04374     {
04375         uint32_t CA4 : 32;             /*!< [31:0] CA4 */
04376     } B;
04377 } hw_cau_aesc_ca4_t;
04378 
04379 /*!
04380  * @name Constants and macros for entire CAU_AESC_CA4 register
04381  */
04382 /*@{*/
04383 #define HW_CAU_AESC_CA4_ADDR(x)  ((x) + 0xB18U)
04384 
04385 #define HW_CAU_AESC_CA4(x)       (*(__O hw_cau_aesc_ca4_t *) HW_CAU_AESC_CA4_ADDR(x))
04386 #define HW_CAU_AESC_CA4_WR(x, v) (ADDRESS_WRITE(hw_cau_aesc_ca4_t, HW_CAU_AESC_CA4_ADDR(x), v))
04387 /*@}*/
04388 
04389 /*
04390  * Constants & macros for individual CAU_AESC_CA4 bitfields
04391  */
04392 
04393 /*!
04394  * @name Register CAU_AESC_CA4, field CA4[31:0] (WO)
04395  */
04396 /*@{*/
04397 #define BP_CAU_AESC_CA4_CA4  (0U)          /*!< Bit position for CAU_AESC_CA4_CA4. */
04398 #define BM_CAU_AESC_CA4_CA4  (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CA4_CA4. */
04399 #define BS_CAU_AESC_CA4_CA4  (32U)         /*!< Bit field size in bits for CAU_AESC_CA4_CA4. */
04400 
04401 /*! @brief Format value for bitfield CAU_AESC_CA4_CA4. */
04402 #define BF_CAU_AESC_CA4_CA4(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CA4_CA4) & BM_CAU_AESC_CA4_CA4)
04403 /*@}*/
04404 
04405 /*******************************************************************************
04406  * HW_CAU_AESC_CA5 - General Purpose Register 5 - AES Column Operation command
04407  ******************************************************************************/
04408 
04409 /*!
04410  * @brief HW_CAU_AESC_CA5 - General Purpose Register 5 - AES Column Operation command (WO)
04411  *
04412  * Reset value: 0x00000000U
04413  */
04414 typedef union _hw_cau_aesc_ca5
04415 {
04416     uint32_t U;
04417     struct _hw_cau_aesc_ca5_bitfields
04418     {
04419         uint32_t CA5 : 32;             /*!< [31:0] CA5 */
04420     } B;
04421 } hw_cau_aesc_ca5_t;
04422 
04423 /*!
04424  * @name Constants and macros for entire CAU_AESC_CA5 register
04425  */
04426 /*@{*/
04427 #define HW_CAU_AESC_CA5_ADDR(x)  ((x) + 0xB1CU)
04428 
04429 #define HW_CAU_AESC_CA5(x)       (*(__O hw_cau_aesc_ca5_t *) HW_CAU_AESC_CA5_ADDR(x))
04430 #define HW_CAU_AESC_CA5_WR(x, v) (ADDRESS_WRITE(hw_cau_aesc_ca5_t, HW_CAU_AESC_CA5_ADDR(x), v))
04431 /*@}*/
04432 
04433 /*
04434  * Constants & macros for individual CAU_AESC_CA5 bitfields
04435  */
04436 
04437 /*!
04438  * @name Register CAU_AESC_CA5, field CA5[31:0] (WO)
04439  */
04440 /*@{*/
04441 #define BP_CAU_AESC_CA5_CA5  (0U)          /*!< Bit position for CAU_AESC_CA5_CA5. */
04442 #define BM_CAU_AESC_CA5_CA5  (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CA5_CA5. */
04443 #define BS_CAU_AESC_CA5_CA5  (32U)         /*!< Bit field size in bits for CAU_AESC_CA5_CA5. */
04444 
04445 /*! @brief Format value for bitfield CAU_AESC_CA5_CA5. */
04446 #define BF_CAU_AESC_CA5_CA5(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CA5_CA5) & BM_CAU_AESC_CA5_CA5)
04447 /*@}*/
04448 
04449 /*******************************************************************************
04450  * HW_CAU_AESC_CA6 - General Purpose Register 6 - AES Column Operation command
04451  ******************************************************************************/
04452 
04453 /*!
04454  * @brief HW_CAU_AESC_CA6 - General Purpose Register 6 - AES Column Operation command (WO)
04455  *
04456  * Reset value: 0x00000000U
04457  */
04458 typedef union _hw_cau_aesc_ca6
04459 {
04460     uint32_t U;
04461     struct _hw_cau_aesc_ca6_bitfields
04462     {
04463         uint32_t CA6 : 32;             /*!< [31:0] CA6 */
04464     } B;
04465 } hw_cau_aesc_ca6_t;
04466 
04467 /*!
04468  * @name Constants and macros for entire CAU_AESC_CA6 register
04469  */
04470 /*@{*/
04471 #define HW_CAU_AESC_CA6_ADDR(x)  ((x) + 0xB20U)
04472 
04473 #define HW_CAU_AESC_CA6(x)       (*(__O hw_cau_aesc_ca6_t *) HW_CAU_AESC_CA6_ADDR(x))
04474 #define HW_CAU_AESC_CA6_WR(x, v) (ADDRESS_WRITE(hw_cau_aesc_ca6_t, HW_CAU_AESC_CA6_ADDR(x), v))
04475 /*@}*/
04476 
04477 /*
04478  * Constants & macros for individual CAU_AESC_CA6 bitfields
04479  */
04480 
04481 /*!
04482  * @name Register CAU_AESC_CA6, field CA6[31:0] (WO)
04483  */
04484 /*@{*/
04485 #define BP_CAU_AESC_CA6_CA6  (0U)          /*!< Bit position for CAU_AESC_CA6_CA6. */
04486 #define BM_CAU_AESC_CA6_CA6  (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CA6_CA6. */
04487 #define BS_CAU_AESC_CA6_CA6  (32U)         /*!< Bit field size in bits for CAU_AESC_CA6_CA6. */
04488 
04489 /*! @brief Format value for bitfield CAU_AESC_CA6_CA6. */
04490 #define BF_CAU_AESC_CA6_CA6(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CA6_CA6) & BM_CAU_AESC_CA6_CA6)
04491 /*@}*/
04492 
04493 /*******************************************************************************
04494  * HW_CAU_AESC_CA7 - General Purpose Register 7 - AES Column Operation command
04495  ******************************************************************************/
04496 
04497 /*!
04498  * @brief HW_CAU_AESC_CA7 - General Purpose Register 7 - AES Column Operation command (WO)
04499  *
04500  * Reset value: 0x00000000U
04501  */
04502 typedef union _hw_cau_aesc_ca7
04503 {
04504     uint32_t U;
04505     struct _hw_cau_aesc_ca7_bitfields
04506     {
04507         uint32_t CA7 : 32;             /*!< [31:0] CA7 */
04508     } B;
04509 } hw_cau_aesc_ca7_t;
04510 
04511 /*!
04512  * @name Constants and macros for entire CAU_AESC_CA7 register
04513  */
04514 /*@{*/
04515 #define HW_CAU_AESC_CA7_ADDR(x)  ((x) + 0xB24U)
04516 
04517 #define HW_CAU_AESC_CA7(x)       (*(__O hw_cau_aesc_ca7_t *) HW_CAU_AESC_CA7_ADDR(x))
04518 #define HW_CAU_AESC_CA7_WR(x, v) (ADDRESS_WRITE(hw_cau_aesc_ca7_t, HW_CAU_AESC_CA7_ADDR(x), v))
04519 /*@}*/
04520 
04521 /*
04522  * Constants & macros for individual CAU_AESC_CA7 bitfields
04523  */
04524 
04525 /*!
04526  * @name Register CAU_AESC_CA7, field CA7[31:0] (WO)
04527  */
04528 /*@{*/
04529 #define BP_CAU_AESC_CA7_CA7  (0U)          /*!< Bit position for CAU_AESC_CA7_CA7. */
04530 #define BM_CAU_AESC_CA7_CA7  (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CA7_CA7. */
04531 #define BS_CAU_AESC_CA7_CA7  (32U)         /*!< Bit field size in bits for CAU_AESC_CA7_CA7. */
04532 
04533 /*! @brief Format value for bitfield CAU_AESC_CA7_CA7. */
04534 #define BF_CAU_AESC_CA7_CA7(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CA7_CA7) & BM_CAU_AESC_CA7_CA7)
04535 /*@}*/
04536 
04537 /*******************************************************************************
04538  * HW_CAU_AESC_CA8 - General Purpose Register 8 - AES Column Operation command
04539  ******************************************************************************/
04540 
04541 /*!
04542  * @brief HW_CAU_AESC_CA8 - General Purpose Register 8 - AES Column Operation command (WO)
04543  *
04544  * Reset value: 0x00000000U
04545  */
04546 typedef union _hw_cau_aesc_ca8
04547 {
04548     uint32_t U;
04549     struct _hw_cau_aesc_ca8_bitfields
04550     {
04551         uint32_t CA8 : 32;             /*!< [31:0] CA8 */
04552     } B;
04553 } hw_cau_aesc_ca8_t;
04554 
04555 /*!
04556  * @name Constants and macros for entire CAU_AESC_CA8 register
04557  */
04558 /*@{*/
04559 #define HW_CAU_AESC_CA8_ADDR(x)  ((x) + 0xB28U)
04560 
04561 #define HW_CAU_AESC_CA8(x)       (*(__O hw_cau_aesc_ca8_t *) HW_CAU_AESC_CA8_ADDR(x))
04562 #define HW_CAU_AESC_CA8_WR(x, v) (ADDRESS_WRITE(hw_cau_aesc_ca8_t, HW_CAU_AESC_CA8_ADDR(x), v))
04563 /*@}*/
04564 
04565 /*
04566  * Constants & macros for individual CAU_AESC_CA8 bitfields
04567  */
04568 
04569 /*!
04570  * @name Register CAU_AESC_CA8, field CA8[31:0] (WO)
04571  */
04572 /*@{*/
04573 #define BP_CAU_AESC_CA8_CA8  (0U)          /*!< Bit position for CAU_AESC_CA8_CA8. */
04574 #define BM_CAU_AESC_CA8_CA8  (0xFFFFFFFFU) /*!< Bit mask for CAU_AESC_CA8_CA8. */
04575 #define BS_CAU_AESC_CA8_CA8  (32U)         /*!< Bit field size in bits for CAU_AESC_CA8_CA8. */
04576 
04577 /*! @brief Format value for bitfield CAU_AESC_CA8_CA8. */
04578 #define BF_CAU_AESC_CA8_CA8(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESC_CA8_CA8) & BM_CAU_AESC_CA8_CA8)
04579 /*@}*/
04580 
04581 /*******************************************************************************
04582  * HW_CAU_AESIC_CASR - Status register  - AES Inverse Column Operation command
04583  ******************************************************************************/
04584 
04585 /*!
04586  * @brief HW_CAU_AESIC_CASR - Status register  - AES Inverse Column Operation command (WO)
04587  *
04588  * Reset value: 0x20000000U
04589  */
04590 typedef union _hw_cau_aesic_casr
04591 {
04592     uint32_t U;
04593     struct _hw_cau_aesic_casr_bitfields
04594     {
04595         uint32_t IC : 1;               /*!< [0]  */
04596         uint32_t DPE : 1;              /*!< [1]  */
04597         uint32_t RESERVED0 : 26;       /*!< [27:2]  */
04598         uint32_t VER : 4;              /*!< [31:28] CAU version */
04599     } B;
04600 } hw_cau_aesic_casr_t;
04601 
04602 /*!
04603  * @name Constants and macros for entire CAU_AESIC_CASR register
04604  */
04605 /*@{*/
04606 #define HW_CAU_AESIC_CASR_ADDR(x) ((x) + 0xB40U)
04607 
04608 #define HW_CAU_AESIC_CASR(x)     (*(__O hw_cau_aesic_casr_t *) HW_CAU_AESIC_CASR_ADDR(x))
04609 #define HW_CAU_AESIC_CASR_WR(x, v) (ADDRESS_WRITE(hw_cau_aesic_casr_t, HW_CAU_AESIC_CASR_ADDR(x), v))
04610 /*@}*/
04611 
04612 /*
04613  * Constants & macros for individual CAU_AESIC_CASR bitfields
04614  */
04615 
04616 /*!
04617  * @name Register CAU_AESIC_CASR, field IC[0] (WO)
04618  *
04619  * Values:
04620  * - 0 - No illegal commands issued
04621  * - 1 - Illegal command issued
04622  */
04623 /*@{*/
04624 #define BP_CAU_AESIC_CASR_IC (0U)          /*!< Bit position for CAU_AESIC_CASR_IC. */
04625 #define BM_CAU_AESIC_CASR_IC (0x00000001U) /*!< Bit mask for CAU_AESIC_CASR_IC. */
04626 #define BS_CAU_AESIC_CASR_IC (1U)          /*!< Bit field size in bits for CAU_AESIC_CASR_IC. */
04627 
04628 /*! @brief Format value for bitfield CAU_AESIC_CASR_IC. */
04629 #define BF_CAU_AESIC_CASR_IC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CASR_IC) & BM_CAU_AESIC_CASR_IC)
04630 /*@}*/
04631 
04632 /*!
04633  * @name Register CAU_AESIC_CASR, field DPE[1] (WO)
04634  *
04635  * Values:
04636  * - 0 - No error detected
04637  * - 1 - DES key parity error detected
04638  */
04639 /*@{*/
04640 #define BP_CAU_AESIC_CASR_DPE (1U)         /*!< Bit position for CAU_AESIC_CASR_DPE. */
04641 #define BM_CAU_AESIC_CASR_DPE (0x00000002U) /*!< Bit mask for CAU_AESIC_CASR_DPE. */
04642 #define BS_CAU_AESIC_CASR_DPE (1U)         /*!< Bit field size in bits for CAU_AESIC_CASR_DPE. */
04643 
04644 /*! @brief Format value for bitfield CAU_AESIC_CASR_DPE. */
04645 #define BF_CAU_AESIC_CASR_DPE(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CASR_DPE) & BM_CAU_AESIC_CASR_DPE)
04646 /*@}*/
04647 
04648 /*!
04649  * @name Register CAU_AESIC_CASR, field VER[31:28] (WO)
04650  *
04651  * Values:
04652  * - 0001 - Initial CAU version
04653  * - 0010 - Second version, added support for SHA-256 algorithm.(This is the
04654  *     value on this device)
04655  */
04656 /*@{*/
04657 #define BP_CAU_AESIC_CASR_VER (28U)        /*!< Bit position for CAU_AESIC_CASR_VER. */
04658 #define BM_CAU_AESIC_CASR_VER (0xF0000000U) /*!< Bit mask for CAU_AESIC_CASR_VER. */
04659 #define BS_CAU_AESIC_CASR_VER (4U)         /*!< Bit field size in bits for CAU_AESIC_CASR_VER. */
04660 
04661 /*! @brief Format value for bitfield CAU_AESIC_CASR_VER. */
04662 #define BF_CAU_AESIC_CASR_VER(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CASR_VER) & BM_CAU_AESIC_CASR_VER)
04663 /*@}*/
04664 
04665 /*******************************************************************************
04666  * HW_CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command
04667  ******************************************************************************/
04668 
04669 /*!
04670  * @brief HW_CAU_AESIC_CAA - Accumulator register - AES Inverse Column Operation command (WO)
04671  *
04672  * Reset value: 0x00000000U
04673  */
04674 typedef union _hw_cau_aesic_caa
04675 {
04676     uint32_t U;
04677     struct _hw_cau_aesic_caa_bitfields
04678     {
04679         uint32_t ACC : 32;             /*!< [31:0] ACC */
04680     } B;
04681 } hw_cau_aesic_caa_t;
04682 
04683 /*!
04684  * @name Constants and macros for entire CAU_AESIC_CAA register
04685  */
04686 /*@{*/
04687 #define HW_CAU_AESIC_CAA_ADDR(x) ((x) + 0xB44U)
04688 
04689 #define HW_CAU_AESIC_CAA(x)      (*(__O hw_cau_aesic_caa_t *) HW_CAU_AESIC_CAA_ADDR(x))
04690 #define HW_CAU_AESIC_CAA_WR(x, v) (ADDRESS_WRITE(hw_cau_aesic_caa_t, HW_CAU_AESIC_CAA_ADDR(x), v))
04691 /*@}*/
04692 
04693 /*
04694  * Constants & macros for individual CAU_AESIC_CAA bitfields
04695  */
04696 
04697 /*!
04698  * @name Register CAU_AESIC_CAA, field ACC[31:0] (WO)
04699  */
04700 /*@{*/
04701 #define BP_CAU_AESIC_CAA_ACC (0U)          /*!< Bit position for CAU_AESIC_CAA_ACC. */
04702 #define BM_CAU_AESIC_CAA_ACC (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CAA_ACC. */
04703 #define BS_CAU_AESIC_CAA_ACC (32U)         /*!< Bit field size in bits for CAU_AESIC_CAA_ACC. */
04704 
04705 /*! @brief Format value for bitfield CAU_AESIC_CAA_ACC. */
04706 #define BF_CAU_AESIC_CAA_ACC(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CAA_ACC) & BM_CAU_AESIC_CAA_ACC)
04707 /*@}*/
04708 
04709 /*******************************************************************************
04710  * HW_CAU_AESIC_CA0 - General Purpose Register 0 - AES Inverse Column Operation command
04711  ******************************************************************************/
04712 
04713 /*!
04714  * @brief HW_CAU_AESIC_CA0 - General Purpose Register 0 - AES Inverse Column Operation command (WO)
04715  *
04716  * Reset value: 0x00000000U
04717  */
04718 typedef union _hw_cau_aesic_ca0
04719 {
04720     uint32_t U;
04721     struct _hw_cau_aesic_ca0_bitfields
04722     {
04723         uint32_t CA0 : 32;             /*!< [31:0] CA0 */
04724     } B;
04725 } hw_cau_aesic_ca0_t;
04726 
04727 /*!
04728  * @name Constants and macros for entire CAU_AESIC_CA0 register
04729  */
04730 /*@{*/
04731 #define HW_CAU_AESIC_CA0_ADDR(x) ((x) + 0xB48U)
04732 
04733 #define HW_CAU_AESIC_CA0(x)      (*(__O hw_cau_aesic_ca0_t *) HW_CAU_AESIC_CA0_ADDR(x))
04734 #define HW_CAU_AESIC_CA0_WR(x, v) (ADDRESS_WRITE(hw_cau_aesic_ca0_t, HW_CAU_AESIC_CA0_ADDR(x), v))
04735 /*@}*/
04736 
04737 /*
04738  * Constants & macros for individual CAU_AESIC_CA0 bitfields
04739  */
04740 
04741 /*!
04742  * @name Register CAU_AESIC_CA0, field CA0[31:0] (WO)
04743  */
04744 /*@{*/
04745 #define BP_CAU_AESIC_CA0_CA0 (0U)          /*!< Bit position for CAU_AESIC_CA0_CA0. */
04746 #define BM_CAU_AESIC_CA0_CA0 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CA0_CA0. */
04747 #define BS_CAU_AESIC_CA0_CA0 (32U)         /*!< Bit field size in bits for CAU_AESIC_CA0_CA0. */
04748 
04749 /*! @brief Format value for bitfield CAU_AESIC_CA0_CA0. */
04750 #define BF_CAU_AESIC_CA0_CA0(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CA0_CA0) & BM_CAU_AESIC_CA0_CA0)
04751 /*@}*/
04752 
04753 /*******************************************************************************
04754  * HW_CAU_AESIC_CA1 - General Purpose Register 1 - AES Inverse Column Operation command
04755  ******************************************************************************/
04756 
04757 /*!
04758  * @brief HW_CAU_AESIC_CA1 - General Purpose Register 1 - AES Inverse Column Operation command (WO)
04759  *
04760  * Reset value: 0x00000000U
04761  */
04762 typedef union _hw_cau_aesic_ca1
04763 {
04764     uint32_t U;
04765     struct _hw_cau_aesic_ca1_bitfields
04766     {
04767         uint32_t CA1 : 32;             /*!< [31:0] CA1 */
04768     } B;
04769 } hw_cau_aesic_ca1_t;
04770 
04771 /*!
04772  * @name Constants and macros for entire CAU_AESIC_CA1 register
04773  */
04774 /*@{*/
04775 #define HW_CAU_AESIC_CA1_ADDR(x) ((x) + 0xB4CU)
04776 
04777 #define HW_CAU_AESIC_CA1(x)      (*(__O hw_cau_aesic_ca1_t *) HW_CAU_AESIC_CA1_ADDR(x))
04778 #define HW_CAU_AESIC_CA1_WR(x, v) (ADDRESS_WRITE(hw_cau_aesic_ca1_t, HW_CAU_AESIC_CA1_ADDR(x), v))
04779 /*@}*/
04780 
04781 /*
04782  * Constants & macros for individual CAU_AESIC_CA1 bitfields
04783  */
04784 
04785 /*!
04786  * @name Register CAU_AESIC_CA1, field CA1[31:0] (WO)
04787  */
04788 /*@{*/
04789 #define BP_CAU_AESIC_CA1_CA1 (0U)          /*!< Bit position for CAU_AESIC_CA1_CA1. */
04790 #define BM_CAU_AESIC_CA1_CA1 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CA1_CA1. */
04791 #define BS_CAU_AESIC_CA1_CA1 (32U)         /*!< Bit field size in bits for CAU_AESIC_CA1_CA1. */
04792 
04793 /*! @brief Format value for bitfield CAU_AESIC_CA1_CA1. */
04794 #define BF_CAU_AESIC_CA1_CA1(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CA1_CA1) & BM_CAU_AESIC_CA1_CA1)
04795 /*@}*/
04796 
04797 /*******************************************************************************
04798  * HW_CAU_AESIC_CA2 - General Purpose Register 2 - AES Inverse Column Operation command
04799  ******************************************************************************/
04800 
04801 /*!
04802  * @brief HW_CAU_AESIC_CA2 - General Purpose Register 2 - AES Inverse Column Operation command (WO)
04803  *
04804  * Reset value: 0x00000000U
04805  */
04806 typedef union _hw_cau_aesic_ca2
04807 {
04808     uint32_t U;
04809     struct _hw_cau_aesic_ca2_bitfields
04810     {
04811         uint32_t CA2 : 32;             /*!< [31:0] CA2 */
04812     } B;
04813 } hw_cau_aesic_ca2_t;
04814 
04815 /*!
04816  * @name Constants and macros for entire CAU_AESIC_CA2 register
04817  */
04818 /*@{*/
04819 #define HW_CAU_AESIC_CA2_ADDR(x) ((x) + 0xB50U)
04820 
04821 #define HW_CAU_AESIC_CA2(x)      (*(__O hw_cau_aesic_ca2_t *) HW_CAU_AESIC_CA2_ADDR(x))
04822 #define HW_CAU_AESIC_CA2_WR(x, v) (ADDRESS_WRITE(hw_cau_aesic_ca2_t, HW_CAU_AESIC_CA2_ADDR(x), v))
04823 /*@}*/
04824 
04825 /*
04826  * Constants & macros for individual CAU_AESIC_CA2 bitfields
04827  */
04828 
04829 /*!
04830  * @name Register CAU_AESIC_CA2, field CA2[31:0] (WO)
04831  */
04832 /*@{*/
04833 #define BP_CAU_AESIC_CA2_CA2 (0U)          /*!< Bit position for CAU_AESIC_CA2_CA2. */
04834 #define BM_CAU_AESIC_CA2_CA2 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CA2_CA2. */
04835 #define BS_CAU_AESIC_CA2_CA2 (32U)         /*!< Bit field size in bits for CAU_AESIC_CA2_CA2. */
04836 
04837 /*! @brief Format value for bitfield CAU_AESIC_CA2_CA2. */
04838 #define BF_CAU_AESIC_CA2_CA2(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CA2_CA2) & BM_CAU_AESIC_CA2_CA2)
04839 /*@}*/
04840 
04841 /*******************************************************************************
04842  * HW_CAU_AESIC_CA3 - General Purpose Register 3 - AES Inverse Column Operation command
04843  ******************************************************************************/
04844 
04845 /*!
04846  * @brief HW_CAU_AESIC_CA3 - General Purpose Register 3 - AES Inverse Column Operation command (WO)
04847  *
04848  * Reset value: 0x00000000U
04849  */
04850 typedef union _hw_cau_aesic_ca3
04851 {
04852     uint32_t U;
04853     struct _hw_cau_aesic_ca3_bitfields
04854     {
04855         uint32_t CA3 : 32;             /*!< [31:0] CA3 */
04856     } B;
04857 } hw_cau_aesic_ca3_t;
04858 
04859 /*!
04860  * @name Constants and macros for entire CAU_AESIC_CA3 register
04861  */
04862 /*@{*/
04863 #define HW_CAU_AESIC_CA3_ADDR(x) ((x) + 0xB54U)
04864 
04865 #define HW_CAU_AESIC_CA3(x)      (*(__O hw_cau_aesic_ca3_t *) HW_CAU_AESIC_CA3_ADDR(x))
04866 #define HW_CAU_AESIC_CA3_WR(x, v) (ADDRESS_WRITE(hw_cau_aesic_ca3_t, HW_CAU_AESIC_CA3_ADDR(x), v))
04867 /*@}*/
04868 
04869 /*
04870  * Constants & macros for individual CAU_AESIC_CA3 bitfields
04871  */
04872 
04873 /*!
04874  * @name Register CAU_AESIC_CA3, field CA3[31:0] (WO)
04875  */
04876 /*@{*/
04877 #define BP_CAU_AESIC_CA3_CA3 (0U)          /*!< Bit position for CAU_AESIC_CA3_CA3. */
04878 #define BM_CAU_AESIC_CA3_CA3 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CA3_CA3. */
04879 #define BS_CAU_AESIC_CA3_CA3 (32U)         /*!< Bit field size in bits for CAU_AESIC_CA3_CA3. */
04880 
04881 /*! @brief Format value for bitfield CAU_AESIC_CA3_CA3. */
04882 #define BF_CAU_AESIC_CA3_CA3(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CA3_CA3) & BM_CAU_AESIC_CA3_CA3)
04883 /*@}*/
04884 
04885 /*******************************************************************************
04886  * HW_CAU_AESIC_CA4 - General Purpose Register 4 - AES Inverse Column Operation command
04887  ******************************************************************************/
04888 
04889 /*!
04890  * @brief HW_CAU_AESIC_CA4 - General Purpose Register 4 - AES Inverse Column Operation command (WO)
04891  *
04892  * Reset value: 0x00000000U
04893  */
04894 typedef union _hw_cau_aesic_ca4
04895 {
04896     uint32_t U;
04897     struct _hw_cau_aesic_ca4_bitfields
04898     {
04899         uint32_t CA4 : 32;             /*!< [31:0] CA4 */
04900     } B;
04901 } hw_cau_aesic_ca4_t;
04902 
04903 /*!
04904  * @name Constants and macros for entire CAU_AESIC_CA4 register
04905  */
04906 /*@{*/
04907 #define HW_CAU_AESIC_CA4_ADDR(x) ((x) + 0xB58U)
04908 
04909 #define HW_CAU_AESIC_CA4(x)      (*(__O hw_cau_aesic_ca4_t *) HW_CAU_AESIC_CA4_ADDR(x))
04910 #define HW_CAU_AESIC_CA4_WR(x, v) (ADDRESS_WRITE(hw_cau_aesic_ca4_t, HW_CAU_AESIC_CA4_ADDR(x), v))
04911 /*@}*/
04912 
04913 /*
04914  * Constants & macros for individual CAU_AESIC_CA4 bitfields
04915  */
04916 
04917 /*!
04918  * @name Register CAU_AESIC_CA4, field CA4[31:0] (WO)
04919  */
04920 /*@{*/
04921 #define BP_CAU_AESIC_CA4_CA4 (0U)          /*!< Bit position for CAU_AESIC_CA4_CA4. */
04922 #define BM_CAU_AESIC_CA4_CA4 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CA4_CA4. */
04923 #define BS_CAU_AESIC_CA4_CA4 (32U)         /*!< Bit field size in bits for CAU_AESIC_CA4_CA4. */
04924 
04925 /*! @brief Format value for bitfield CAU_AESIC_CA4_CA4. */
04926 #define BF_CAU_AESIC_CA4_CA4(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CA4_CA4) & BM_CAU_AESIC_CA4_CA4)
04927 /*@}*/
04928 
04929 /*******************************************************************************
04930  * HW_CAU_AESIC_CA5 - General Purpose Register 5 - AES Inverse Column Operation command
04931  ******************************************************************************/
04932 
04933 /*!
04934  * @brief HW_CAU_AESIC_CA5 - General Purpose Register 5 - AES Inverse Column Operation command (WO)
04935  *
04936  * Reset value: 0x00000000U
04937  */
04938 typedef union _hw_cau_aesic_ca5
04939 {
04940     uint32_t U;
04941     struct _hw_cau_aesic_ca5_bitfields
04942     {
04943         uint32_t CA5 : 32;             /*!< [31:0] CA5 */
04944     } B;
04945 } hw_cau_aesic_ca5_t;
04946 
04947 /*!
04948  * @name Constants and macros for entire CAU_AESIC_CA5 register
04949  */
04950 /*@{*/
04951 #define HW_CAU_AESIC_CA5_ADDR(x) ((x) + 0xB5CU)
04952 
04953 #define HW_CAU_AESIC_CA5(x)      (*(__O hw_cau_aesic_ca5_t *) HW_CAU_AESIC_CA5_ADDR(x))
04954 #define HW_CAU_AESIC_CA5_WR(x, v) (ADDRESS_WRITE(hw_cau_aesic_ca5_t, HW_CAU_AESIC_CA5_ADDR(x), v))
04955 /*@}*/
04956 
04957 /*
04958  * Constants & macros for individual CAU_AESIC_CA5 bitfields
04959  */
04960 
04961 /*!
04962  * @name Register CAU_AESIC_CA5, field CA5[31:0] (WO)
04963  */
04964 /*@{*/
04965 #define BP_CAU_AESIC_CA5_CA5 (0U)          /*!< Bit position for CAU_AESIC_CA5_CA5. */
04966 #define BM_CAU_AESIC_CA5_CA5 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CA5_CA5. */
04967 #define BS_CAU_AESIC_CA5_CA5 (32U)         /*!< Bit field size in bits for CAU_AESIC_CA5_CA5. */
04968 
04969 /*! @brief Format value for bitfield CAU_AESIC_CA5_CA5. */
04970 #define BF_CAU_AESIC_CA5_CA5(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CA5_CA5) & BM_CAU_AESIC_CA5_CA5)
04971 /*@}*/
04972 
04973 /*******************************************************************************
04974  * HW_CAU_AESIC_CA6 - General Purpose Register 6 - AES Inverse Column Operation command
04975  ******************************************************************************/
04976 
04977 /*!
04978  * @brief HW_CAU_AESIC_CA6 - General Purpose Register 6 - AES Inverse Column Operation command (WO)
04979  *
04980  * Reset value: 0x00000000U
04981  */
04982 typedef union _hw_cau_aesic_ca6
04983 {
04984     uint32_t U;
04985     struct _hw_cau_aesic_ca6_bitfields
04986     {
04987         uint32_t CA6 : 32;             /*!< [31:0] CA6 */
04988     } B;
04989 } hw_cau_aesic_ca6_t;
04990 
04991 /*!
04992  * @name Constants and macros for entire CAU_AESIC_CA6 register
04993  */
04994 /*@{*/
04995 #define HW_CAU_AESIC_CA6_ADDR(x) ((x) + 0xB60U)
04996 
04997 #define HW_CAU_AESIC_CA6(x)      (*(__O hw_cau_aesic_ca6_t *) HW_CAU_AESIC_CA6_ADDR(x))
04998 #define HW_CAU_AESIC_CA6_WR(x, v) (ADDRESS_WRITE(hw_cau_aesic_ca6_t, HW_CAU_AESIC_CA6_ADDR(x), v))
04999 /*@}*/
05000 
05001 /*
05002  * Constants & macros for individual CAU_AESIC_CA6 bitfields
05003  */
05004 
05005 /*!
05006  * @name Register CAU_AESIC_CA6, field CA6[31:0] (WO)
05007  */
05008 /*@{*/
05009 #define BP_CAU_AESIC_CA6_CA6 (0U)          /*!< Bit position for CAU_AESIC_CA6_CA6. */
05010 #define BM_CAU_AESIC_CA6_CA6 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CA6_CA6. */
05011 #define BS_CAU_AESIC_CA6_CA6 (32U)         /*!< Bit field size in bits for CAU_AESIC_CA6_CA6. */
05012 
05013 /*! @brief Format value for bitfield CAU_AESIC_CA6_CA6. */
05014 #define BF_CAU_AESIC_CA6_CA6(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CA6_CA6) & BM_CAU_AESIC_CA6_CA6)
05015 /*@}*/
05016 
05017 /*******************************************************************************
05018  * HW_CAU_AESIC_CA7 - General Purpose Register 7 - AES Inverse Column Operation command
05019  ******************************************************************************/
05020 
05021 /*!
05022  * @brief HW_CAU_AESIC_CA7 - General Purpose Register 7 - AES Inverse Column Operation command (WO)
05023  *
05024  * Reset value: 0x00000000U
05025  */
05026 typedef union _hw_cau_aesic_ca7
05027 {
05028     uint32_t U;
05029     struct _hw_cau_aesic_ca7_bitfields
05030     {
05031         uint32_t CA7 : 32;             /*!< [31:0] CA7 */
05032     } B;
05033 } hw_cau_aesic_ca7_t;
05034 
05035 /*!
05036  * @name Constants and macros for entire CAU_AESIC_CA7 register
05037  */
05038 /*@{*/
05039 #define HW_CAU_AESIC_CA7_ADDR(x) ((x) + 0xB64U)
05040 
05041 #define HW_CAU_AESIC_CA7(x)      (*(__O hw_cau_aesic_ca7_t *) HW_CAU_AESIC_CA7_ADDR(x))
05042 #define HW_CAU_AESIC_CA7_WR(x, v) (ADDRESS_WRITE(hw_cau_aesic_ca7_t, HW_CAU_AESIC_CA7_ADDR(x), v))
05043 /*@}*/
05044 
05045 /*
05046  * Constants & macros for individual CAU_AESIC_CA7 bitfields
05047  */
05048 
05049 /*!
05050  * @name Register CAU_AESIC_CA7, field CA7[31:0] (WO)
05051  */
05052 /*@{*/
05053 #define BP_CAU_AESIC_CA7_CA7 (0U)          /*!< Bit position for CAU_AESIC_CA7_CA7. */
05054 #define BM_CAU_AESIC_CA7_CA7 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CA7_CA7. */
05055 #define BS_CAU_AESIC_CA7_CA7 (32U)         /*!< Bit field size in bits for CAU_AESIC_CA7_CA7. */
05056 
05057 /*! @brief Format value for bitfield CAU_AESIC_CA7_CA7. */
05058 #define BF_CAU_AESIC_CA7_CA7(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CA7_CA7) & BM_CAU_AESIC_CA7_CA7)
05059 /*@}*/
05060 
05061 /*******************************************************************************
05062  * HW_CAU_AESIC_CA8 - General Purpose Register 8 - AES Inverse Column Operation command
05063  ******************************************************************************/
05064 
05065 /*!
05066  * @brief HW_CAU_AESIC_CA8 - General Purpose Register 8 - AES Inverse Column Operation command (WO)
05067  *
05068  * Reset value: 0x00000000U
05069  */
05070 typedef union _hw_cau_aesic_ca8
05071 {
05072     uint32_t U;
05073     struct _hw_cau_aesic_ca8_bitfields
05074     {
05075         uint32_t CA8 : 32;             /*!< [31:0] CA8 */
05076     } B;
05077 } hw_cau_aesic_ca8_t;
05078 
05079 /*!
05080  * @name Constants and macros for entire CAU_AESIC_CA8 register
05081  */
05082 /*@{*/
05083 #define HW_CAU_AESIC_CA8_ADDR(x) ((x) + 0xB68U)
05084 
05085 #define HW_CAU_AESIC_CA8(x)      (*(__O hw_cau_aesic_ca8_t *) HW_CAU_AESIC_CA8_ADDR(x))
05086 #define HW_CAU_AESIC_CA8_WR(x, v) (ADDRESS_WRITE(hw_cau_aesic_ca8_t, HW_CAU_AESIC_CA8_ADDR(x), v))
05087 /*@}*/
05088 
05089 /*
05090  * Constants & macros for individual CAU_AESIC_CA8 bitfields
05091  */
05092 
05093 /*!
05094  * @name Register CAU_AESIC_CA8, field CA8[31:0] (WO)
05095  */
05096 /*@{*/
05097 #define BP_CAU_AESIC_CA8_CA8 (0U)          /*!< Bit position for CAU_AESIC_CA8_CA8. */
05098 #define BM_CAU_AESIC_CA8_CA8 (0xFFFFFFFFU) /*!< Bit mask for CAU_AESIC_CA8_CA8. */
05099 #define BS_CAU_AESIC_CA8_CA8 (32U)         /*!< Bit field size in bits for CAU_AESIC_CA8_CA8. */
05100 
05101 /*! @brief Format value for bitfield CAU_AESIC_CA8_CA8. */
05102 #define BF_CAU_AESIC_CA8_CA8(v) ((uint32_t)((uint32_t)(v) << BP_CAU_AESIC_CA8_CA8) & BM_CAU_AESIC_CA8_CA8)
05103 /*@}*/
05104 
05105 /*******************************************************************************
05106  * hw_cau_t - module struct
05107  ******************************************************************************/
05108 /*!
05109  * @brief All CAU module registers.
05110  */
05111 #pragma pack(1)
05112 typedef struct _hw_cau
05113 {
05114     __O hw_cau_direct0_t DIRECT0 ;          /*!< [0x0] Direct access register 0 */
05115     __O hw_cau_direct1_t DIRECT1 ;          /*!< [0x4] Direct access register 1 */
05116     __O hw_cau_direct2_t DIRECT2 ;          /*!< [0x8] Direct access register 2 */
05117     __O hw_cau_direct3_t DIRECT3 ;          /*!< [0xC] Direct access register 3 */
05118     __O hw_cau_direct4_t DIRECT4 ;          /*!< [0x10] Direct access register 4 */
05119     __O hw_cau_direct5_t DIRECT5 ;          /*!< [0x14] Direct access register 5 */
05120     __O hw_cau_direct6_t DIRECT6 ;          /*!< [0x18] Direct access register 6 */
05121     __O hw_cau_direct7_t DIRECT7 ;          /*!< [0x1C] Direct access register 7 */
05122     __O hw_cau_direct8_t DIRECT8 ;          /*!< [0x20] Direct access register 8 */
05123     __O hw_cau_direct9_t DIRECT9 ;          /*!< [0x24] Direct access register 9 */
05124     __O hw_cau_direct10_t DIRECT10 ;        /*!< [0x28] Direct access register 10 */
05125     __O hw_cau_direct11_t DIRECT11 ;        /*!< [0x2C] Direct access register 11 */
05126     __O hw_cau_direct12_t DIRECT12 ;        /*!< [0x30] Direct access register 12 */
05127     __O hw_cau_direct13_t DIRECT13 ;        /*!< [0x34] Direct access register 13 */
05128     __O hw_cau_direct14_t DIRECT14 ;        /*!< [0x38] Direct access register 14 */
05129     __O hw_cau_direct15_t DIRECT15 ;        /*!< [0x3C] Direct access register 15 */
05130     uint8_t _reserved0[2048];
05131     __O hw_cau_ldr_casr_t LDR_CASR ;        /*!< [0x840] Status register  - Load Register command */
05132     __O hw_cau_ldr_caa_t LDR_CAA ;          /*!< [0x844] Accumulator register - Load Register command */
05133     __O hw_cau_ldr_ca0_t LDR_CA0 ;          /*!< [0x848] General Purpose Register 0 - Load Register command */
05134     __O hw_cau_ldr_ca1_t LDR_CA1 ;          /*!< [0x84C] General Purpose Register 1 - Load Register command */
05135     __O hw_cau_ldr_ca2_t LDR_CA2 ;          /*!< [0x850] General Purpose Register 2 - Load Register command */
05136     __O hw_cau_ldr_ca3_t LDR_CA3 ;          /*!< [0x854] General Purpose Register 3 - Load Register command */
05137     __O hw_cau_ldr_ca4_t LDR_CA4 ;          /*!< [0x858] General Purpose Register 4 - Load Register command */
05138     __O hw_cau_ldr_ca5_t LDR_CA5 ;          /*!< [0x85C] General Purpose Register 5 - Load Register command */
05139     __O hw_cau_ldr_ca6_t LDR_CA6 ;          /*!< [0x860] General Purpose Register 6 - Load Register command */
05140     __O hw_cau_ldr_ca7_t LDR_CA7 ;          /*!< [0x864] General Purpose Register 7 - Load Register command */
05141     __O hw_cau_ldr_ca8_t LDR_CA8 ;          /*!< [0x868] General Purpose Register 8 - Load Register command */
05142     uint8_t _reserved1[20];
05143     __I hw_cau_str_casr_t STR_CASR ;        /*!< [0x880] Status register  - Store Register command */
05144     __I hw_cau_str_caa_t STR_CAA ;          /*!< [0x884] Accumulator register - Store Register command */
05145     __I hw_cau_str_ca0_t STR_CA0 ;          /*!< [0x888] General Purpose Register 0 - Store Register command */
05146     __I hw_cau_str_ca1_t STR_CA1 ;          /*!< [0x88C] General Purpose Register 1 - Store Register command */
05147     __I hw_cau_str_ca2_t STR_CA2 ;          /*!< [0x890] General Purpose Register 2 - Store Register command */
05148     __I hw_cau_str_ca3_t STR_CA3 ;          /*!< [0x894] General Purpose Register 3 - Store Register command */
05149     __I hw_cau_str_ca4_t STR_CA4 ;          /*!< [0x898] General Purpose Register 4 - Store Register command */
05150     __I hw_cau_str_ca5_t STR_CA5 ;          /*!< [0x89C] General Purpose Register 5 - Store Register command */
05151     __I hw_cau_str_ca6_t STR_CA6 ;          /*!< [0x8A0] General Purpose Register 6 - Store Register command */
05152     __I hw_cau_str_ca7_t STR_CA7 ;          /*!< [0x8A4] General Purpose Register 7 - Store Register command */
05153     __I hw_cau_str_ca8_t STR_CA8 ;          /*!< [0x8A8] General Purpose Register 8 - Store Register command */
05154     uint8_t _reserved2[20];
05155     __O hw_cau_adr_casr_t ADR_CASR ;        /*!< [0x8C0] Status register  - Add Register command */
05156     __O hw_cau_adr_caa_t ADR_CAA ;          /*!< [0x8C4] Accumulator register - Add to register command */
05157     __O hw_cau_adr_ca0_t ADR_CA0 ;          /*!< [0x8C8] General Purpose Register 0 - Add to register command */
05158     __O hw_cau_adr_ca1_t ADR_CA1 ;          /*!< [0x8CC] General Purpose Register 1 - Add to register command */
05159     __O hw_cau_adr_ca2_t ADR_CA2 ;          /*!< [0x8D0] General Purpose Register 2 - Add to register command */
05160     __O hw_cau_adr_ca3_t ADR_CA3 ;          /*!< [0x8D4] General Purpose Register 3 - Add to register command */
05161     __O hw_cau_adr_ca4_t ADR_CA4 ;          /*!< [0x8D8] General Purpose Register 4 - Add to register command */
05162     __O hw_cau_adr_ca5_t ADR_CA5 ;          /*!< [0x8DC] General Purpose Register 5 - Add to register command */
05163     __O hw_cau_adr_ca6_t ADR_CA6 ;          /*!< [0x8E0] General Purpose Register 6 - Add to register command */
05164     __O hw_cau_adr_ca7_t ADR_CA7 ;          /*!< [0x8E4] General Purpose Register 7 - Add to register command */
05165     __O hw_cau_adr_ca8_t ADR_CA8 ;          /*!< [0x8E8] General Purpose Register 8 - Add to register command */
05166     uint8_t _reserved3[20];
05167     __O hw_cau_radr_casr_t RADR_CASR ;      /*!< [0x900] Status register  - Reverse and Add to Register command */
05168     __O hw_cau_radr_caa_t RADR_CAA ;        /*!< [0x904] Accumulator register - Reverse and Add to Register command */
05169     __O hw_cau_radr_ca0_t RADR_CA0 ;        /*!< [0x908] General Purpose Register 0 - Reverse and Add to Register command */
05170     __O hw_cau_radr_ca1_t RADR_CA1 ;        /*!< [0x90C] General Purpose Register 1 - Reverse and Add to Register command */
05171     __O hw_cau_radr_ca2_t RADR_CA2 ;        /*!< [0x910] General Purpose Register 2 - Reverse and Add to Register command */
05172     __O hw_cau_radr_ca3_t RADR_CA3 ;        /*!< [0x914] General Purpose Register 3 - Reverse and Add to Register command */
05173     __O hw_cau_radr_ca4_t RADR_CA4 ;        /*!< [0x918] General Purpose Register 4 - Reverse and Add to Register command */
05174     __O hw_cau_radr_ca5_t RADR_CA5 ;        /*!< [0x91C] General Purpose Register 5 - Reverse and Add to Register command */
05175     __O hw_cau_radr_ca6_t RADR_CA6 ;        /*!< [0x920] General Purpose Register 6 - Reverse and Add to Register command */
05176     __O hw_cau_radr_ca7_t RADR_CA7 ;        /*!< [0x924] General Purpose Register 7 - Reverse and Add to Register command */
05177     __O hw_cau_radr_ca8_t RADR_CA8 ;        /*!< [0x928] General Purpose Register 8 - Reverse and Add to Register command */
05178     uint8_t _reserved4[84];
05179     __O hw_cau_xor_casr_t XOR_CASR ;        /*!< [0x980] Status register  - Exclusive Or command */
05180     __O hw_cau_xor_caa_t XOR_CAA ;          /*!< [0x984] Accumulator register - Exclusive Or command */
05181     __O hw_cau_xor_ca0_t XOR_CA0 ;          /*!< [0x988] General Purpose Register 0 - Exclusive Or command */
05182     __O hw_cau_xor_ca1_t XOR_CA1 ;          /*!< [0x98C] General Purpose Register 1 - Exclusive Or command */
05183     __O hw_cau_xor_ca2_t XOR_CA2 ;          /*!< [0x990] General Purpose Register 2 - Exclusive Or command */
05184     __O hw_cau_xor_ca3_t XOR_CA3 ;          /*!< [0x994] General Purpose Register 3 - Exclusive Or command */
05185     __O hw_cau_xor_ca4_t XOR_CA4 ;          /*!< [0x998] General Purpose Register 4 - Exclusive Or command */
05186     __O hw_cau_xor_ca5_t XOR_CA5 ;          /*!< [0x99C] General Purpose Register 5 - Exclusive Or command */
05187     __O hw_cau_xor_ca6_t XOR_CA6 ;          /*!< [0x9A0] General Purpose Register 6 - Exclusive Or command */
05188     __O hw_cau_xor_ca7_t XOR_CA7 ;          /*!< [0x9A4] General Purpose Register 7 - Exclusive Or command */
05189     __O hw_cau_xor_ca8_t XOR_CA8 ;          /*!< [0x9A8] General Purpose Register 8 - Exclusive Or command */
05190     uint8_t _reserved5[20];
05191     __O hw_cau_rotl_casr_t ROTL_CASR ;      /*!< [0x9C0] Status register  - Rotate Left command */
05192     __O hw_cau_rotl_caa_t ROTL_CAA ;        /*!< [0x9C4] Accumulator register - Rotate Left command */
05193     __O hw_cau_rotl_ca0_t ROTL_CA0 ;        /*!< [0x9C8] General Purpose Register 0 - Rotate Left command */
05194     __O hw_cau_rotl_ca1_t ROTL_CA1 ;        /*!< [0x9CC] General Purpose Register 1 - Rotate Left command */
05195     __O hw_cau_rotl_ca2_t ROTL_CA2 ;        /*!< [0x9D0] General Purpose Register 2 - Rotate Left command */
05196     __O hw_cau_rotl_ca3_t ROTL_CA3 ;        /*!< [0x9D4] General Purpose Register 3 - Rotate Left command */
05197     __O hw_cau_rotl_ca4_t ROTL_CA4 ;        /*!< [0x9D8] General Purpose Register 4 - Rotate Left command */
05198     __O hw_cau_rotl_ca5_t ROTL_CA5 ;        /*!< [0x9DC] General Purpose Register 5 - Rotate Left command */
05199     __O hw_cau_rotl_ca6_t ROTL_CA6 ;        /*!< [0x9E0] General Purpose Register 6 - Rotate Left command */
05200     __O hw_cau_rotl_ca7_t ROTL_CA7 ;        /*!< [0x9E4] General Purpose Register 7 - Rotate Left command */
05201     __O hw_cau_rotl_ca8_t ROTL_CA8 ;        /*!< [0x9E8] General Purpose Register 8 - Rotate Left command */
05202     uint8_t _reserved6[276];
05203     __O hw_cau_aesc_casr_t AESC_CASR ;      /*!< [0xB00] Status register  - AES Column Operation command */
05204     __O hw_cau_aesc_caa_t AESC_CAA ;        /*!< [0xB04] Accumulator register - AES Column Operation command */
05205     __O hw_cau_aesc_ca0_t AESC_CA0 ;        /*!< [0xB08] General Purpose Register 0 - AES Column Operation command */
05206     __O hw_cau_aesc_ca1_t AESC_CA1 ;        /*!< [0xB0C] General Purpose Register 1 - AES Column Operation command */
05207     __O hw_cau_aesc_ca2_t AESC_CA2 ;        /*!< [0xB10] General Purpose Register 2 - AES Column Operation command */
05208     __O hw_cau_aesc_ca3_t AESC_CA3 ;        /*!< [0xB14] General Purpose Register 3 - AES Column Operation command */
05209     __O hw_cau_aesc_ca4_t AESC_CA4 ;        /*!< [0xB18] General Purpose Register 4 - AES Column Operation command */
05210     __O hw_cau_aesc_ca5_t AESC_CA5 ;        /*!< [0xB1C] General Purpose Register 5 - AES Column Operation command */
05211     __O hw_cau_aesc_ca6_t AESC_CA6 ;        /*!< [0xB20] General Purpose Register 6 - AES Column Operation command */
05212     __O hw_cau_aesc_ca7_t AESC_CA7 ;        /*!< [0xB24] General Purpose Register 7 - AES Column Operation command */
05213     __O hw_cau_aesc_ca8_t AESC_CA8 ;        /*!< [0xB28] General Purpose Register 8 - AES Column Operation command */
05214     uint8_t _reserved7[20];
05215     __O hw_cau_aesic_casr_t AESIC_CASR ;    /*!< [0xB40] Status register  - AES Inverse Column Operation command */
05216     __O hw_cau_aesic_caa_t AESIC_CAA ;      /*!< [0xB44] Accumulator register - AES Inverse Column Operation command */
05217     __O hw_cau_aesic_ca0_t AESIC_CA0 ;      /*!< [0xB48] General Purpose Register 0 - AES Inverse Column Operation command */
05218     __O hw_cau_aesic_ca1_t AESIC_CA1 ;      /*!< [0xB4C] General Purpose Register 1 - AES Inverse Column Operation command */
05219     __O hw_cau_aesic_ca2_t AESIC_CA2 ;      /*!< [0xB50] General Purpose Register 2 - AES Inverse Column Operation command */
05220     __O hw_cau_aesic_ca3_t AESIC_CA3 ;      /*!< [0xB54] General Purpose Register 3 - AES Inverse Column Operation command */
05221     __O hw_cau_aesic_ca4_t AESIC_CA4 ;      /*!< [0xB58] General Purpose Register 4 - AES Inverse Column Operation command */
05222     __O hw_cau_aesic_ca5_t AESIC_CA5 ;      /*!< [0xB5C] General Purpose Register 5 - AES Inverse Column Operation command */
05223     __O hw_cau_aesic_ca6_t AESIC_CA6 ;      /*!< [0xB60] General Purpose Register 6 - AES Inverse Column Operation command */
05224     __O hw_cau_aesic_ca7_t AESIC_CA7 ;      /*!< [0xB64] General Purpose Register 7 - AES Inverse Column Operation command */
05225     __O hw_cau_aesic_ca8_t AESIC_CA8 ;      /*!< [0xB68] General Purpose Register 8 - AES Inverse Column Operation command */
05226 } hw_cau_t;
05227 #pragma pack()
05228 
05229 /*! @brief Macro to access all CAU registers. */
05230 /*! @param x CAU module instance base address. */
05231 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
05232  *     use the '&' operator, like <code>&HW_CAU(CAU_BASE)</code>. */
05233 #define HW_CAU(x)      (*(hw_cau_t *)(x))
05234 
05235 #endif /* __HW_CAU_REGISTERS_H__ */
05236 /* EOF */