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target-mcu-k64f
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MK64F12_aips.h
00001 /* 00002 ** ################################################################### 00003 ** Compilers: Keil ARM C/C++ Compiler 00004 ** Freescale C/C++ for Embedded ARM 00005 ** GNU C Compiler 00006 ** IAR ANSI C/C++ Compiler for ARM 00007 ** 00008 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 00009 ** Version: rev. 2.5, 2014-02-10 00010 ** Build: b140604 00011 ** 00012 ** Abstract: 00013 ** Extension to the CMSIS register access layer header. 00014 ** 00015 ** Copyright (c) 2014 Freescale Semiconductor, Inc. 00016 ** All rights reserved. 00017 ** 00018 ** (C) COPYRIGHT 2015-2015 ARM Limited 00019 ** ALL RIGHTS RESERVED 00020 ** 00021 ** Redistribution and use in source and binary forms, with or without modification, 00022 ** are permitted provided that the following conditions are met: 00023 ** 00024 ** o Redistributions of source code must retain the above copyright notice, this list 00025 ** of conditions and the following disclaimer. 00026 ** 00027 ** o Redistributions in binary form must reproduce the above copyright notice, this 00028 ** list of conditions and the following disclaimer in the documentation and/or 00029 ** other materials provided with the distribution. 00030 ** 00031 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its 00032 ** contributors may be used to endorse or promote products derived from this 00033 ** software without specific prior written permission. 00034 ** 00035 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 00036 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 00037 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00038 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 00039 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 00040 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 00041 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 00042 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 00043 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 00044 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00045 ** 00046 ** http: www.freescale.com 00047 ** mail: support@freescale.com 00048 ** 00049 ** Revisions: 00050 ** - rev. 1.0 (2013-08-12) 00051 ** Initial version. 00052 ** - rev. 2.0 (2013-10-29) 00053 ** Register accessor macros added to the memory map. 00054 ** Symbols for Processor Expert memory map compatibility added to the memory map. 00055 ** Startup file for gcc has been updated according to CMSIS 3.2. 00056 ** System initialization updated. 00057 ** MCG - registers updated. 00058 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. 00059 ** - rev. 2.1 (2013-10-30) 00060 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. 00061 ** - rev. 2.2 (2013-12-09) 00062 ** DMA - EARS register removed. 00063 ** AIPS0, AIPS1 - MPRA register updated. 00064 ** - rev. 2.3 (2014-01-24) 00065 ** Update according to reference manual rev. 2 00066 ** ENET, MCG, MCM, SIM, USB - registers updated 00067 ** - rev. 2.4 (2014-02-10) 00068 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h 00069 ** Update of SystemInit() and SystemCoreClockUpdate() functions. 00070 ** - rev. 2.5 (2014-02-10) 00071 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h 00072 ** Update of SystemInit() and SystemCoreClockUpdate() functions. 00073 ** Module access macro module_BASES replaced by module_BASE_PTRS. 00074 ** - rev. 2.6 (2015-08-03) (ARM) 00075 ** All accesses to memory are replaced by equivalent macros; this allows 00076 ** memory read/write operations to be re-defined if needed (for example, 00077 ** to implement new security features 00078 ** 00079 ** ################################################################### 00080 */ 00081 00082 /* 00083 * WARNING! DO NOT EDIT THIS FILE DIRECTLY! 00084 * 00085 * This file was generated automatically and any changes may be lost. 00086 */ 00087 #ifndef __HW_AIPS_REGISTERS_H__ 00088 #define __HW_AIPS_REGISTERS_H__ 00089 00090 #include "MK64F12.h" 00091 #include "fsl_bitaccess.h" 00092 00093 /* 00094 * MK64F12 AIPS 00095 * 00096 * AIPS-Lite Bridge 00097 * 00098 * Registers defined in this header file: 00099 * - HW_AIPS_MPRA - Master Privilege Register A 00100 * - HW_AIPS_PACRA - Peripheral Access Control Register 00101 * - HW_AIPS_PACRB - Peripheral Access Control Register 00102 * - HW_AIPS_PACRC - Peripheral Access Control Register 00103 * - HW_AIPS_PACRD - Peripheral Access Control Register 00104 * - HW_AIPS_PACRE - Peripheral Access Control Register 00105 * - HW_AIPS_PACRF - Peripheral Access Control Register 00106 * - HW_AIPS_PACRG - Peripheral Access Control Register 00107 * - HW_AIPS_PACRH - Peripheral Access Control Register 00108 * - HW_AIPS_PACRI - Peripheral Access Control Register 00109 * - HW_AIPS_PACRJ - Peripheral Access Control Register 00110 * - HW_AIPS_PACRK - Peripheral Access Control Register 00111 * - HW_AIPS_PACRL - Peripheral Access Control Register 00112 * - HW_AIPS_PACRM - Peripheral Access Control Register 00113 * - HW_AIPS_PACRN - Peripheral Access Control Register 00114 * - HW_AIPS_PACRO - Peripheral Access Control Register 00115 * - HW_AIPS_PACRP - Peripheral Access Control Register 00116 * - HW_AIPS_PACRU - Peripheral Access Control Register 00117 * 00118 * - hw_aips_t - Struct containing all module registers. 00119 */ 00120 00121 #define HW_AIPS_INSTANCE_COUNT (2U) /*!< Number of instances of the AIPS module. */ 00122 #define HW_AIPS0 (0U) /*!< Instance number for AIPS0. */ 00123 #define HW_AIPS1 (1U) /*!< Instance number for AIPS1. */ 00124 00125 /******************************************************************************* 00126 * HW_AIPS_MPRA - Master Privilege Register A 00127 ******************************************************************************/ 00128 00129 /*! 00130 * @brief HW_AIPS_MPRA - Master Privilege Register A (RW) 00131 * 00132 * Reset value: 0x77700000U 00133 * 00134 * The MPRA specifies identical 4-bit fields defining the access-privilege level 00135 * associated with a bus master to various peripherals on the chip. The register 00136 * provides one field per bus master. At reset, the default value loaded into 00137 * the MPRA fields is chip-specific. See the chip configuration details for the 00138 * value of a particular device. A register field that maps to an unimplemented 00139 * master or peripheral behaves as read-only-zero. Each master is assigned a logical 00140 * ID from 0 to 15. See the master logical ID assignment table in the 00141 * chip-specific AIPS information. 00142 */ 00143 typedef union _hw_aips_mpra 00144 { 00145 uint32_t U; 00146 struct _hw_aips_mpra_bitfields 00147 { 00148 uint32_t RESERVED0 : 8; /*!< [7:0] */ 00149 uint32_t MPL5 : 1; /*!< [8] Master 5 Privilege Level */ 00150 uint32_t MTW5 : 1; /*!< [9] Master 5 Trusted For Writes */ 00151 uint32_t MTR5 : 1; /*!< [10] Master 5 Trusted For Read */ 00152 uint32_t RESERVED1 : 1; /*!< [11] */ 00153 uint32_t MPL4 : 1; /*!< [12] Master 4 Privilege Level */ 00154 uint32_t MTW4 : 1; /*!< [13] Master 4 Trusted For Writes */ 00155 uint32_t MTR4 : 1; /*!< [14] Master 4 Trusted For Read */ 00156 uint32_t RESERVED2 : 1; /*!< [15] */ 00157 uint32_t MPL3 : 1; /*!< [16] Master 3 Privilege Level */ 00158 uint32_t MTW3 : 1; /*!< [17] Master 3 Trusted For Writes */ 00159 uint32_t MTR3 : 1; /*!< [18] Master 3 Trusted For Read */ 00160 uint32_t RESERVED3 : 1; /*!< [19] */ 00161 uint32_t MPL2 : 1; /*!< [20] Master 2 Privilege Level */ 00162 uint32_t MTW2 : 1; /*!< [21] Master 2 Trusted For Writes */ 00163 uint32_t MTR2 : 1; /*!< [22] Master 2 Trusted For Read */ 00164 uint32_t RESERVED4 : 1; /*!< [23] */ 00165 uint32_t MPL1 : 1; /*!< [24] Master 1 Privilege Level */ 00166 uint32_t MTW1 : 1; /*!< [25] Master 1 Trusted for Writes */ 00167 uint32_t MTR1 : 1; /*!< [26] Master 1 Trusted for Read */ 00168 uint32_t RESERVED5 : 1; /*!< [27] */ 00169 uint32_t MPL0 : 1; /*!< [28] Master 0 Privilege Level */ 00170 uint32_t MTW0 : 1; /*!< [29] Master 0 Trusted For Writes */ 00171 uint32_t MTR0 : 1; /*!< [30] Master 0 Trusted For Read */ 00172 uint32_t RESERVED6 : 1; /*!< [31] */ 00173 } B; 00174 } hw_aips_mpra_t; 00175 00176 /*! 00177 * @name Constants and macros for entire AIPS_MPRA register 00178 */ 00179 /*@{*/ 00180 #define HW_AIPS_MPRA_ADDR(x) ((x) + 0x0U) 00181 00182 #define HW_AIPS_MPRA(x) (*(__IO hw_aips_mpra_t *) HW_AIPS_MPRA_ADDR(x)) 00183 #define HW_AIPS_MPRA_RD(x) (ADDRESS_READ(hw_aips_mpra_t, HW_AIPS_MPRA_ADDR(x))) 00184 #define HW_AIPS_MPRA_WR(x, v) (ADDRESS_WRITE(hw_aips_mpra_t, HW_AIPS_MPRA_ADDR(x), v)) 00185 #define HW_AIPS_MPRA_SET(x, v) (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) | (v))) 00186 #define HW_AIPS_MPRA_CLR(x, v) (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) & ~(v))) 00187 #define HW_AIPS_MPRA_TOG(x, v) (HW_AIPS_MPRA_WR(x, HW_AIPS_MPRA_RD(x) ^ (v))) 00188 /*@}*/ 00189 00190 /* 00191 * Constants & macros for individual AIPS_MPRA bitfields 00192 */ 00193 00194 /*! 00195 * @name Register AIPS_MPRA, field MPL5[8] (RW) 00196 * 00197 * Specifies how the privilege level of the master is determined. 00198 * 00199 * Values: 00200 * - 0 - Accesses from this master are forced to user-mode. 00201 * - 1 - Accesses from this master are not forced to user-mode. 00202 */ 00203 /*@{*/ 00204 #define BP_AIPS_MPRA_MPL5 (8U) /*!< Bit position for AIPS_MPRA_MPL5. */ 00205 #define BM_AIPS_MPRA_MPL5 (0x00000100U) /*!< Bit mask for AIPS_MPRA_MPL5. */ 00206 #define BS_AIPS_MPRA_MPL5 (1U) /*!< Bit field size in bits for AIPS_MPRA_MPL5. */ 00207 00208 /*! @brief Read current value of the AIPS_MPRA_MPL5 field. */ 00209 #define BR_AIPS_MPRA_MPL5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL5))) 00210 00211 /*! @brief Format value for bitfield AIPS_MPRA_MPL5. */ 00212 #define BF_AIPS_MPRA_MPL5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MPL5) & BM_AIPS_MPRA_MPL5) 00213 00214 /*! @brief Set the MPL5 field to a new value. */ 00215 #define BW_AIPS_MPRA_MPL5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL5), v)) 00216 /*@}*/ 00217 00218 /*! 00219 * @name Register AIPS_MPRA, field MTW5[9] (RW) 00220 * 00221 * Determines whether the master is trusted for write accesses. 00222 * 00223 * Values: 00224 * - 0 - This master is not trusted for write accesses. 00225 * - 1 - This master is trusted for write accesses. 00226 */ 00227 /*@{*/ 00228 #define BP_AIPS_MPRA_MTW5 (9U) /*!< Bit position for AIPS_MPRA_MTW5. */ 00229 #define BM_AIPS_MPRA_MTW5 (0x00000200U) /*!< Bit mask for AIPS_MPRA_MTW5. */ 00230 #define BS_AIPS_MPRA_MTW5 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTW5. */ 00231 00232 /*! @brief Read current value of the AIPS_MPRA_MTW5 field. */ 00233 #define BR_AIPS_MPRA_MTW5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW5))) 00234 00235 /*! @brief Format value for bitfield AIPS_MPRA_MTW5. */ 00236 #define BF_AIPS_MPRA_MTW5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTW5) & BM_AIPS_MPRA_MTW5) 00237 00238 /*! @brief Set the MTW5 field to a new value. */ 00239 #define BW_AIPS_MPRA_MTW5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW5), v)) 00240 /*@}*/ 00241 00242 /*! 00243 * @name Register AIPS_MPRA, field MTR5[10] (RW) 00244 * 00245 * Determines whether the master is trusted for read accesses. 00246 * 00247 * Values: 00248 * - 0 - This master is not trusted for read accesses. 00249 * - 1 - This master is trusted for read accesses. 00250 */ 00251 /*@{*/ 00252 #define BP_AIPS_MPRA_MTR5 (10U) /*!< Bit position for AIPS_MPRA_MTR5. */ 00253 #define BM_AIPS_MPRA_MTR5 (0x00000400U) /*!< Bit mask for AIPS_MPRA_MTR5. */ 00254 #define BS_AIPS_MPRA_MTR5 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTR5. */ 00255 00256 /*! @brief Read current value of the AIPS_MPRA_MTR5 field. */ 00257 #define BR_AIPS_MPRA_MTR5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR5))) 00258 00259 /*! @brief Format value for bitfield AIPS_MPRA_MTR5. */ 00260 #define BF_AIPS_MPRA_MTR5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTR5) & BM_AIPS_MPRA_MTR5) 00261 00262 /*! @brief Set the MTR5 field to a new value. */ 00263 #define BW_AIPS_MPRA_MTR5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR5), v)) 00264 /*@}*/ 00265 00266 /*! 00267 * @name Register AIPS_MPRA, field MPL4[12] (RW) 00268 * 00269 * Specifies how the privilege level of the master is determined. 00270 * 00271 * Values: 00272 * - 0 - Accesses from this master are forced to user-mode. 00273 * - 1 - Accesses from this master are not forced to user-mode. 00274 */ 00275 /*@{*/ 00276 #define BP_AIPS_MPRA_MPL4 (12U) /*!< Bit position for AIPS_MPRA_MPL4. */ 00277 #define BM_AIPS_MPRA_MPL4 (0x00001000U) /*!< Bit mask for AIPS_MPRA_MPL4. */ 00278 #define BS_AIPS_MPRA_MPL4 (1U) /*!< Bit field size in bits for AIPS_MPRA_MPL4. */ 00279 00280 /*! @brief Read current value of the AIPS_MPRA_MPL4 field. */ 00281 #define BR_AIPS_MPRA_MPL4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL4))) 00282 00283 /*! @brief Format value for bitfield AIPS_MPRA_MPL4. */ 00284 #define BF_AIPS_MPRA_MPL4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MPL4) & BM_AIPS_MPRA_MPL4) 00285 00286 /*! @brief Set the MPL4 field to a new value. */ 00287 #define BW_AIPS_MPRA_MPL4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL4), v)) 00288 /*@}*/ 00289 00290 /*! 00291 * @name Register AIPS_MPRA, field MTW4[13] (RW) 00292 * 00293 * Determines whether the master is trusted for write accesses. 00294 * 00295 * Values: 00296 * - 0 - This master is not trusted for write accesses. 00297 * - 1 - This master is trusted for write accesses. 00298 */ 00299 /*@{*/ 00300 #define BP_AIPS_MPRA_MTW4 (13U) /*!< Bit position for AIPS_MPRA_MTW4. */ 00301 #define BM_AIPS_MPRA_MTW4 (0x00002000U) /*!< Bit mask for AIPS_MPRA_MTW4. */ 00302 #define BS_AIPS_MPRA_MTW4 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTW4. */ 00303 00304 /*! @brief Read current value of the AIPS_MPRA_MTW4 field. */ 00305 #define BR_AIPS_MPRA_MTW4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW4))) 00306 00307 /*! @brief Format value for bitfield AIPS_MPRA_MTW4. */ 00308 #define BF_AIPS_MPRA_MTW4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTW4) & BM_AIPS_MPRA_MTW4) 00309 00310 /*! @brief Set the MTW4 field to a new value. */ 00311 #define BW_AIPS_MPRA_MTW4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW4), v)) 00312 /*@}*/ 00313 00314 /*! 00315 * @name Register AIPS_MPRA, field MTR4[14] (RW) 00316 * 00317 * Determines whether the master is trusted for read accesses. 00318 * 00319 * Values: 00320 * - 0 - This master is not trusted for read accesses. 00321 * - 1 - This master is trusted for read accesses. 00322 */ 00323 /*@{*/ 00324 #define BP_AIPS_MPRA_MTR4 (14U) /*!< Bit position for AIPS_MPRA_MTR4. */ 00325 #define BM_AIPS_MPRA_MTR4 (0x00004000U) /*!< Bit mask for AIPS_MPRA_MTR4. */ 00326 #define BS_AIPS_MPRA_MTR4 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTR4. */ 00327 00328 /*! @brief Read current value of the AIPS_MPRA_MTR4 field. */ 00329 #define BR_AIPS_MPRA_MTR4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR4))) 00330 00331 /*! @brief Format value for bitfield AIPS_MPRA_MTR4. */ 00332 #define BF_AIPS_MPRA_MTR4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTR4) & BM_AIPS_MPRA_MTR4) 00333 00334 /*! @brief Set the MTR4 field to a new value. */ 00335 #define BW_AIPS_MPRA_MTR4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR4), v)) 00336 /*@}*/ 00337 00338 /*! 00339 * @name Register AIPS_MPRA, field MPL3[16] (RW) 00340 * 00341 * Specifies how the privilege level of the master is determined. 00342 * 00343 * Values: 00344 * - 0 - Accesses from this master are forced to user-mode. 00345 * - 1 - Accesses from this master are not forced to user-mode. 00346 */ 00347 /*@{*/ 00348 #define BP_AIPS_MPRA_MPL3 (16U) /*!< Bit position for AIPS_MPRA_MPL3. */ 00349 #define BM_AIPS_MPRA_MPL3 (0x00010000U) /*!< Bit mask for AIPS_MPRA_MPL3. */ 00350 #define BS_AIPS_MPRA_MPL3 (1U) /*!< Bit field size in bits for AIPS_MPRA_MPL3. */ 00351 00352 /*! @brief Read current value of the AIPS_MPRA_MPL3 field. */ 00353 #define BR_AIPS_MPRA_MPL3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL3))) 00354 00355 /*! @brief Format value for bitfield AIPS_MPRA_MPL3. */ 00356 #define BF_AIPS_MPRA_MPL3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MPL3) & BM_AIPS_MPRA_MPL3) 00357 00358 /*! @brief Set the MPL3 field to a new value. */ 00359 #define BW_AIPS_MPRA_MPL3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL3), v)) 00360 /*@}*/ 00361 00362 /*! 00363 * @name Register AIPS_MPRA, field MTW3[17] (RW) 00364 * 00365 * Determines whether the master is trusted for write accesses. 00366 * 00367 * Values: 00368 * - 0 - This master is not trusted for write accesses. 00369 * - 1 - This master is trusted for write accesses. 00370 */ 00371 /*@{*/ 00372 #define BP_AIPS_MPRA_MTW3 (17U) /*!< Bit position for AIPS_MPRA_MTW3. */ 00373 #define BM_AIPS_MPRA_MTW3 (0x00020000U) /*!< Bit mask for AIPS_MPRA_MTW3. */ 00374 #define BS_AIPS_MPRA_MTW3 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTW3. */ 00375 00376 /*! @brief Read current value of the AIPS_MPRA_MTW3 field. */ 00377 #define BR_AIPS_MPRA_MTW3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW3))) 00378 00379 /*! @brief Format value for bitfield AIPS_MPRA_MTW3. */ 00380 #define BF_AIPS_MPRA_MTW3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTW3) & BM_AIPS_MPRA_MTW3) 00381 00382 /*! @brief Set the MTW3 field to a new value. */ 00383 #define BW_AIPS_MPRA_MTW3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW3), v)) 00384 /*@}*/ 00385 00386 /*! 00387 * @name Register AIPS_MPRA, field MTR3[18] (RW) 00388 * 00389 * Determines whether the master is trusted for read accesses. 00390 * 00391 * Values: 00392 * - 0 - This master is not trusted for read accesses. 00393 * - 1 - This master is trusted for read accesses. 00394 */ 00395 /*@{*/ 00396 #define BP_AIPS_MPRA_MTR3 (18U) /*!< Bit position for AIPS_MPRA_MTR3. */ 00397 #define BM_AIPS_MPRA_MTR3 (0x00040000U) /*!< Bit mask for AIPS_MPRA_MTR3. */ 00398 #define BS_AIPS_MPRA_MTR3 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTR3. */ 00399 00400 /*! @brief Read current value of the AIPS_MPRA_MTR3 field. */ 00401 #define BR_AIPS_MPRA_MTR3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR3))) 00402 00403 /*! @brief Format value for bitfield AIPS_MPRA_MTR3. */ 00404 #define BF_AIPS_MPRA_MTR3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTR3) & BM_AIPS_MPRA_MTR3) 00405 00406 /*! @brief Set the MTR3 field to a new value. */ 00407 #define BW_AIPS_MPRA_MTR3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR3), v)) 00408 /*@}*/ 00409 00410 /*! 00411 * @name Register AIPS_MPRA, field MPL2[20] (RW) 00412 * 00413 * Specifies how the privilege level of the master is determined. 00414 * 00415 * Values: 00416 * - 0 - Accesses from this master are forced to user-mode. 00417 * - 1 - Accesses from this master are not forced to user-mode. 00418 */ 00419 /*@{*/ 00420 #define BP_AIPS_MPRA_MPL2 (20U) /*!< Bit position for AIPS_MPRA_MPL2. */ 00421 #define BM_AIPS_MPRA_MPL2 (0x00100000U) /*!< Bit mask for AIPS_MPRA_MPL2. */ 00422 #define BS_AIPS_MPRA_MPL2 (1U) /*!< Bit field size in bits for AIPS_MPRA_MPL2. */ 00423 00424 /*! @brief Read current value of the AIPS_MPRA_MPL2 field. */ 00425 #define BR_AIPS_MPRA_MPL2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL2))) 00426 00427 /*! @brief Format value for bitfield AIPS_MPRA_MPL2. */ 00428 #define BF_AIPS_MPRA_MPL2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MPL2) & BM_AIPS_MPRA_MPL2) 00429 00430 /*! @brief Set the MPL2 field to a new value. */ 00431 #define BW_AIPS_MPRA_MPL2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL2), v)) 00432 /*@}*/ 00433 00434 /*! 00435 * @name Register AIPS_MPRA, field MTW2[21] (RW) 00436 * 00437 * Determines whether the master is trusted for write accesses. 00438 * 00439 * Values: 00440 * - 0 - This master is not trusted for write accesses. 00441 * - 1 - This master is trusted for write accesses. 00442 */ 00443 /*@{*/ 00444 #define BP_AIPS_MPRA_MTW2 (21U) /*!< Bit position for AIPS_MPRA_MTW2. */ 00445 #define BM_AIPS_MPRA_MTW2 (0x00200000U) /*!< Bit mask for AIPS_MPRA_MTW2. */ 00446 #define BS_AIPS_MPRA_MTW2 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTW2. */ 00447 00448 /*! @brief Read current value of the AIPS_MPRA_MTW2 field. */ 00449 #define BR_AIPS_MPRA_MTW2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW2))) 00450 00451 /*! @brief Format value for bitfield AIPS_MPRA_MTW2. */ 00452 #define BF_AIPS_MPRA_MTW2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTW2) & BM_AIPS_MPRA_MTW2) 00453 00454 /*! @brief Set the MTW2 field to a new value. */ 00455 #define BW_AIPS_MPRA_MTW2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW2), v)) 00456 /*@}*/ 00457 00458 /*! 00459 * @name Register AIPS_MPRA, field MTR2[22] (RW) 00460 * 00461 * Determines whether the master is trusted for read accesses. 00462 * 00463 * Values: 00464 * - 0 - This master is not trusted for read accesses. 00465 * - 1 - This master is trusted for read accesses. 00466 */ 00467 /*@{*/ 00468 #define BP_AIPS_MPRA_MTR2 (22U) /*!< Bit position for AIPS_MPRA_MTR2. */ 00469 #define BM_AIPS_MPRA_MTR2 (0x00400000U) /*!< Bit mask for AIPS_MPRA_MTR2. */ 00470 #define BS_AIPS_MPRA_MTR2 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTR2. */ 00471 00472 /*! @brief Read current value of the AIPS_MPRA_MTR2 field. */ 00473 #define BR_AIPS_MPRA_MTR2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR2))) 00474 00475 /*! @brief Format value for bitfield AIPS_MPRA_MTR2. */ 00476 #define BF_AIPS_MPRA_MTR2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTR2) & BM_AIPS_MPRA_MTR2) 00477 00478 /*! @brief Set the MTR2 field to a new value. */ 00479 #define BW_AIPS_MPRA_MTR2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR2), v)) 00480 /*@}*/ 00481 00482 /*! 00483 * @name Register AIPS_MPRA, field MPL1[24] (RW) 00484 * 00485 * Specifies how the privilege level of the master is determined. 00486 * 00487 * Values: 00488 * - 0 - Accesses from this master are forced to user-mode. 00489 * - 1 - Accesses from this master are not forced to user-mode. 00490 */ 00491 /*@{*/ 00492 #define BP_AIPS_MPRA_MPL1 (24U) /*!< Bit position for AIPS_MPRA_MPL1. */ 00493 #define BM_AIPS_MPRA_MPL1 (0x01000000U) /*!< Bit mask for AIPS_MPRA_MPL1. */ 00494 #define BS_AIPS_MPRA_MPL1 (1U) /*!< Bit field size in bits for AIPS_MPRA_MPL1. */ 00495 00496 /*! @brief Read current value of the AIPS_MPRA_MPL1 field. */ 00497 #define BR_AIPS_MPRA_MPL1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL1))) 00498 00499 /*! @brief Format value for bitfield AIPS_MPRA_MPL1. */ 00500 #define BF_AIPS_MPRA_MPL1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MPL1) & BM_AIPS_MPRA_MPL1) 00501 00502 /*! @brief Set the MPL1 field to a new value. */ 00503 #define BW_AIPS_MPRA_MPL1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL1), v)) 00504 /*@}*/ 00505 00506 /*! 00507 * @name Register AIPS_MPRA, field MTW1[25] (RW) 00508 * 00509 * Determines whether the master is trusted for write accesses. 00510 * 00511 * Values: 00512 * - 0 - This master is not trusted for write accesses. 00513 * - 1 - This master is trusted for write accesses. 00514 */ 00515 /*@{*/ 00516 #define BP_AIPS_MPRA_MTW1 (25U) /*!< Bit position for AIPS_MPRA_MTW1. */ 00517 #define BM_AIPS_MPRA_MTW1 (0x02000000U) /*!< Bit mask for AIPS_MPRA_MTW1. */ 00518 #define BS_AIPS_MPRA_MTW1 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTW1. */ 00519 00520 /*! @brief Read current value of the AIPS_MPRA_MTW1 field. */ 00521 #define BR_AIPS_MPRA_MTW1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW1))) 00522 00523 /*! @brief Format value for bitfield AIPS_MPRA_MTW1. */ 00524 #define BF_AIPS_MPRA_MTW1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTW1) & BM_AIPS_MPRA_MTW1) 00525 00526 /*! @brief Set the MTW1 field to a new value. */ 00527 #define BW_AIPS_MPRA_MTW1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW1), v)) 00528 /*@}*/ 00529 00530 /*! 00531 * @name Register AIPS_MPRA, field MTR1[26] (RW) 00532 * 00533 * Determines whether the master is trusted for read accesses. 00534 * 00535 * Values: 00536 * - 0 - This master is not trusted for read accesses. 00537 * - 1 - This master is trusted for read accesses. 00538 */ 00539 /*@{*/ 00540 #define BP_AIPS_MPRA_MTR1 (26U) /*!< Bit position for AIPS_MPRA_MTR1. */ 00541 #define BM_AIPS_MPRA_MTR1 (0x04000000U) /*!< Bit mask for AIPS_MPRA_MTR1. */ 00542 #define BS_AIPS_MPRA_MTR1 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTR1. */ 00543 00544 /*! @brief Read current value of the AIPS_MPRA_MTR1 field. */ 00545 #define BR_AIPS_MPRA_MTR1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR1))) 00546 00547 /*! @brief Format value for bitfield AIPS_MPRA_MTR1. */ 00548 #define BF_AIPS_MPRA_MTR1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTR1) & BM_AIPS_MPRA_MTR1) 00549 00550 /*! @brief Set the MTR1 field to a new value. */ 00551 #define BW_AIPS_MPRA_MTR1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR1), v)) 00552 /*@}*/ 00553 00554 /*! 00555 * @name Register AIPS_MPRA, field MPL0[28] (RW) 00556 * 00557 * Specifies how the privilege level of the master is determined. 00558 * 00559 * Values: 00560 * - 0 - Accesses from this master are forced to user-mode. 00561 * - 1 - Accesses from this master are not forced to user-mode. 00562 */ 00563 /*@{*/ 00564 #define BP_AIPS_MPRA_MPL0 (28U) /*!< Bit position for AIPS_MPRA_MPL0. */ 00565 #define BM_AIPS_MPRA_MPL0 (0x10000000U) /*!< Bit mask for AIPS_MPRA_MPL0. */ 00566 #define BS_AIPS_MPRA_MPL0 (1U) /*!< Bit field size in bits for AIPS_MPRA_MPL0. */ 00567 00568 /*! @brief Read current value of the AIPS_MPRA_MPL0 field. */ 00569 #define BR_AIPS_MPRA_MPL0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL0))) 00570 00571 /*! @brief Format value for bitfield AIPS_MPRA_MPL0. */ 00572 #define BF_AIPS_MPRA_MPL0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MPL0) & BM_AIPS_MPRA_MPL0) 00573 00574 /*! @brief Set the MPL0 field to a new value. */ 00575 #define BW_AIPS_MPRA_MPL0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MPL0), v)) 00576 /*@}*/ 00577 00578 /*! 00579 * @name Register AIPS_MPRA, field MTW0[29] (RW) 00580 * 00581 * Determines whether the master is trusted for write accesses. 00582 * 00583 * Values: 00584 * - 0 - This master is not trusted for write accesses. 00585 * - 1 - This master is trusted for write accesses. 00586 */ 00587 /*@{*/ 00588 #define BP_AIPS_MPRA_MTW0 (29U) /*!< Bit position for AIPS_MPRA_MTW0. */ 00589 #define BM_AIPS_MPRA_MTW0 (0x20000000U) /*!< Bit mask for AIPS_MPRA_MTW0. */ 00590 #define BS_AIPS_MPRA_MTW0 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTW0. */ 00591 00592 /*! @brief Read current value of the AIPS_MPRA_MTW0 field. */ 00593 #define BR_AIPS_MPRA_MTW0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW0))) 00594 00595 /*! @brief Format value for bitfield AIPS_MPRA_MTW0. */ 00596 #define BF_AIPS_MPRA_MTW0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTW0) & BM_AIPS_MPRA_MTW0) 00597 00598 /*! @brief Set the MTW0 field to a new value. */ 00599 #define BW_AIPS_MPRA_MTW0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTW0), v)) 00600 /*@}*/ 00601 00602 /*! 00603 * @name Register AIPS_MPRA, field MTR0[30] (RW) 00604 * 00605 * Determines whether the master is trusted for read accesses. 00606 * 00607 * Values: 00608 * - 0 - This master is not trusted for read accesses. 00609 * - 1 - This master is trusted for read accesses. 00610 */ 00611 /*@{*/ 00612 #define BP_AIPS_MPRA_MTR0 (30U) /*!< Bit position for AIPS_MPRA_MTR0. */ 00613 #define BM_AIPS_MPRA_MTR0 (0x40000000U) /*!< Bit mask for AIPS_MPRA_MTR0. */ 00614 #define BS_AIPS_MPRA_MTR0 (1U) /*!< Bit field size in bits for AIPS_MPRA_MTR0. */ 00615 00616 /*! @brief Read current value of the AIPS_MPRA_MTR0 field. */ 00617 #define BR_AIPS_MPRA_MTR0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR0))) 00618 00619 /*! @brief Format value for bitfield AIPS_MPRA_MTR0. */ 00620 #define BF_AIPS_MPRA_MTR0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_MPRA_MTR0) & BM_AIPS_MPRA_MTR0) 00621 00622 /*! @brief Set the MTR0 field to a new value. */ 00623 #define BW_AIPS_MPRA_MTR0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_MPRA_ADDR(x), BP_AIPS_MPRA_MTR0), v)) 00624 /*@}*/ 00625 00626 /******************************************************************************* 00627 * HW_AIPS_PACRA - Peripheral Access Control Register 00628 ******************************************************************************/ 00629 00630 /*! 00631 * @brief HW_AIPS_PACRA - Peripheral Access Control Register (RW) 00632 * 00633 * Reset value: 0x50004000U 00634 * 00635 * Each PACR register consists of eight 4-bit PACR fields. Each PACR field 00636 * defines the access levels for a particular peripheral. The mapping between a 00637 * peripheral and its PACR field is shown in the table below. The peripheral assignment 00638 * to each PACR is defined by the memory map slot that the peripheral is 00639 * assigned to. See this chip's memory map for the assignment of a particular 00640 * peripheral. The following table shows the location of each peripheral slot's PACR field 00641 * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] 00642 * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7 00643 * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC 00644 * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24 00645 * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38 00646 * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 00647 * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47 00648 * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH 00649 * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64 00650 * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74 00651 * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83 00652 * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93 00653 * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 00654 * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 00655 * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119 00656 * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80 00657 * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR 00658 * A-D, which control peripheral slots 0-31, are shown below. The following 00659 * section, PACRPeripheral Access Control Register , shows the register field 00660 * descriptions for PACR E-P. All PACR registers are identical. They are divided into two 00661 * sections because they occupy two non-contiguous address spaces. 00662 */ 00663 typedef union _hw_aips_pacra 00664 { 00665 uint32_t U; 00666 struct _hw_aips_pacra_bitfields 00667 { 00668 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 00669 uint32_t WP7 : 1; /*!< [1] Write Protect */ 00670 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 00671 uint32_t RESERVED0 : 1; /*!< [3] */ 00672 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 00673 uint32_t WP6 : 1; /*!< [5] Write Protect */ 00674 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 00675 uint32_t RESERVED1 : 1; /*!< [7] */ 00676 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 00677 uint32_t WP5 : 1; /*!< [9] Write Protect */ 00678 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 00679 uint32_t RESERVED2 : 1; /*!< [11] */ 00680 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 00681 uint32_t WP4 : 1; /*!< [13] Write Protect */ 00682 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 00683 uint32_t RESERVED3 : 1; /*!< [15] */ 00684 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 00685 uint32_t WP3 : 1; /*!< [17] Write Protect */ 00686 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 00687 uint32_t RESERVED4 : 1; /*!< [19] */ 00688 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 00689 uint32_t WP2 : 1; /*!< [21] Write Protect */ 00690 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 00691 uint32_t RESERVED5 : 1; /*!< [23] */ 00692 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 00693 uint32_t WP1 : 1; /*!< [25] Write Protect */ 00694 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 00695 uint32_t RESERVED6 : 1; /*!< [27] */ 00696 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 00697 uint32_t WP0 : 1; /*!< [29] Write Protect */ 00698 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 00699 uint32_t RESERVED7 : 1; /*!< [31] */ 00700 } B; 00701 } hw_aips_pacra_t; 00702 00703 /*! 00704 * @name Constants and macros for entire AIPS_PACRA register 00705 */ 00706 /*@{*/ 00707 #define HW_AIPS_PACRA_ADDR(x) ((x) + 0x20U) 00708 00709 #define HW_AIPS_PACRA(x) (*(__IO hw_aips_pacra_t *) HW_AIPS_PACRA_ADDR(x)) 00710 #define HW_AIPS_PACRA_RD(x) (ADDRESS_READ(hw_aips_pacra_t, HW_AIPS_PACRA_ADDR(x))) 00711 #define HW_AIPS_PACRA_WR(x, v) (ADDRESS_WRITE(hw_aips_pacra_t, HW_AIPS_PACRA_ADDR(x), v)) 00712 #define HW_AIPS_PACRA_SET(x, v) (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) | (v))) 00713 #define HW_AIPS_PACRA_CLR(x, v) (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) & ~(v))) 00714 #define HW_AIPS_PACRA_TOG(x, v) (HW_AIPS_PACRA_WR(x, HW_AIPS_PACRA_RD(x) ^ (v))) 00715 /*@}*/ 00716 00717 /* 00718 * Constants & macros for individual AIPS_PACRA bitfields 00719 */ 00720 00721 /*! 00722 * @name Register AIPS_PACRA, field TP7[0] (RW) 00723 * 00724 * Determines whether the peripheral allows accesses from an untrusted master. 00725 * When this field is set and an access is attempted by an untrusted master, the 00726 * access terminates with an error response and no peripheral access initiates. 00727 * 00728 * Values: 00729 * - 0 - Accesses from an untrusted master are allowed. 00730 * - 1 - Accesses from an untrusted master are not allowed. 00731 */ 00732 /*@{*/ 00733 #define BP_AIPS_PACRA_TP7 (0U) /*!< Bit position for AIPS_PACRA_TP7. */ 00734 #define BM_AIPS_PACRA_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRA_TP7. */ 00735 #define BS_AIPS_PACRA_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP7. */ 00736 00737 /*! @brief Read current value of the AIPS_PACRA_TP7 field. */ 00738 #define BR_AIPS_PACRA_TP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP7))) 00739 00740 /*! @brief Format value for bitfield AIPS_PACRA_TP7. */ 00741 #define BF_AIPS_PACRA_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP7) & BM_AIPS_PACRA_TP7) 00742 00743 /*! @brief Set the TP7 field to a new value. */ 00744 #define BW_AIPS_PACRA_TP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP7), v)) 00745 /*@}*/ 00746 00747 /*! 00748 * @name Register AIPS_PACRA, field WP7[1] (RW) 00749 * 00750 * Determines whether the peripheral allows write accesses. When this field is 00751 * set and a write access is attempted, access terminates with an error response 00752 * and no peripheral access initiates. 00753 * 00754 * Values: 00755 * - 0 - This peripheral allows write accesses. 00756 * - 1 - This peripheral is write protected. 00757 */ 00758 /*@{*/ 00759 #define BP_AIPS_PACRA_WP7 (1U) /*!< Bit position for AIPS_PACRA_WP7. */ 00760 #define BM_AIPS_PACRA_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRA_WP7. */ 00761 #define BS_AIPS_PACRA_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP7. */ 00762 00763 /*! @brief Read current value of the AIPS_PACRA_WP7 field. */ 00764 #define BR_AIPS_PACRA_WP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP7))) 00765 00766 /*! @brief Format value for bitfield AIPS_PACRA_WP7. */ 00767 #define BF_AIPS_PACRA_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP7) & BM_AIPS_PACRA_WP7) 00768 00769 /*! @brief Set the WP7 field to a new value. */ 00770 #define BW_AIPS_PACRA_WP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP7), v)) 00771 /*@}*/ 00772 00773 /*! 00774 * @name Register AIPS_PACRA, field SP7[2] (RW) 00775 * 00776 * Determines whether the peripheral requires supervisor privilege level for 00777 * accesses. When this field is set, the master privilege level must indicate the 00778 * supervisor access attribute, and the MPRx[MPLn] control field for the master 00779 * must be set. If not, access terminates with an error response and no peripheral 00780 * access initiates. 00781 * 00782 * Values: 00783 * - 0 - This peripheral does not require supervisor privilege level for 00784 * accesses. 00785 * - 1 - This peripheral requires supervisor privilege level for accesses. 00786 */ 00787 /*@{*/ 00788 #define BP_AIPS_PACRA_SP7 (2U) /*!< Bit position for AIPS_PACRA_SP7. */ 00789 #define BM_AIPS_PACRA_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRA_SP7. */ 00790 #define BS_AIPS_PACRA_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP7. */ 00791 00792 /*! @brief Read current value of the AIPS_PACRA_SP7 field. */ 00793 #define BR_AIPS_PACRA_SP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP7))) 00794 00795 /*! @brief Format value for bitfield AIPS_PACRA_SP7. */ 00796 #define BF_AIPS_PACRA_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP7) & BM_AIPS_PACRA_SP7) 00797 00798 /*! @brief Set the SP7 field to a new value. */ 00799 #define BW_AIPS_PACRA_SP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP7), v)) 00800 /*@}*/ 00801 00802 /*! 00803 * @name Register AIPS_PACRA, field TP6[4] (RW) 00804 * 00805 * Determines whether the peripheral allows accesses from an untrusted master. 00806 * When this field is set and an access is attempted by an untrusted master, the 00807 * access terminates with an error response and no peripheral access initiates. 00808 * 00809 * Values: 00810 * - 0 - Accesses from an untrusted master are allowed. 00811 * - 1 - Accesses from an untrusted master are not allowed. 00812 */ 00813 /*@{*/ 00814 #define BP_AIPS_PACRA_TP6 (4U) /*!< Bit position for AIPS_PACRA_TP6. */ 00815 #define BM_AIPS_PACRA_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRA_TP6. */ 00816 #define BS_AIPS_PACRA_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP6. */ 00817 00818 /*! @brief Read current value of the AIPS_PACRA_TP6 field. */ 00819 #define BR_AIPS_PACRA_TP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP6))) 00820 00821 /*! @brief Format value for bitfield AIPS_PACRA_TP6. */ 00822 #define BF_AIPS_PACRA_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP6) & BM_AIPS_PACRA_TP6) 00823 00824 /*! @brief Set the TP6 field to a new value. */ 00825 #define BW_AIPS_PACRA_TP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP6), v)) 00826 /*@}*/ 00827 00828 /*! 00829 * @name Register AIPS_PACRA, field WP6[5] (RW) 00830 * 00831 * Determines whether the peripheral allows write accesses. When this field is 00832 * set and a write access is attempted, access terminates with an error response 00833 * and no peripheral access initiates. 00834 * 00835 * Values: 00836 * - 0 - This peripheral allows write accesses. 00837 * - 1 - This peripheral is write protected. 00838 */ 00839 /*@{*/ 00840 #define BP_AIPS_PACRA_WP6 (5U) /*!< Bit position for AIPS_PACRA_WP6. */ 00841 #define BM_AIPS_PACRA_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRA_WP6. */ 00842 #define BS_AIPS_PACRA_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP6. */ 00843 00844 /*! @brief Read current value of the AIPS_PACRA_WP6 field. */ 00845 #define BR_AIPS_PACRA_WP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP6))) 00846 00847 /*! @brief Format value for bitfield AIPS_PACRA_WP6. */ 00848 #define BF_AIPS_PACRA_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP6) & BM_AIPS_PACRA_WP6) 00849 00850 /*! @brief Set the WP6 field to a new value. */ 00851 #define BW_AIPS_PACRA_WP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP6), v)) 00852 /*@}*/ 00853 00854 /*! 00855 * @name Register AIPS_PACRA, field SP6[6] (RW) 00856 * 00857 * Determines whether the peripheral requires supervisor privilege level for 00858 * accesses. When this field is set, the master privilege level must indicate the 00859 * supervisor access attribute, and the MPRx[MPLn] control field for the master 00860 * must be set. If not, access terminates with an error response and no peripheral 00861 * access initiates. 00862 * 00863 * Values: 00864 * - 0 - This peripheral does not require supervisor privilege level for 00865 * accesses. 00866 * - 1 - This peripheral requires supervisor privilege level for accesses. 00867 */ 00868 /*@{*/ 00869 #define BP_AIPS_PACRA_SP6 (6U) /*!< Bit position for AIPS_PACRA_SP6. */ 00870 #define BM_AIPS_PACRA_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRA_SP6. */ 00871 #define BS_AIPS_PACRA_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP6. */ 00872 00873 /*! @brief Read current value of the AIPS_PACRA_SP6 field. */ 00874 #define BR_AIPS_PACRA_SP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP6))) 00875 00876 /*! @brief Format value for bitfield AIPS_PACRA_SP6. */ 00877 #define BF_AIPS_PACRA_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP6) & BM_AIPS_PACRA_SP6) 00878 00879 /*! @brief Set the SP6 field to a new value. */ 00880 #define BW_AIPS_PACRA_SP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP6), v)) 00881 /*@}*/ 00882 00883 /*! 00884 * @name Register AIPS_PACRA, field TP5[8] (RW) 00885 * 00886 * Determines whether the peripheral allows accesses from an untrusted master. 00887 * When this field is set and an access is attempted by an untrusted master, the 00888 * access terminates with an error response and no peripheral access initiates. 00889 * 00890 * Values: 00891 * - 0 - Accesses from an untrusted master are allowed. 00892 * - 1 - Accesses from an untrusted master are not allowed. 00893 */ 00894 /*@{*/ 00895 #define BP_AIPS_PACRA_TP5 (8U) /*!< Bit position for AIPS_PACRA_TP5. */ 00896 #define BM_AIPS_PACRA_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRA_TP5. */ 00897 #define BS_AIPS_PACRA_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP5. */ 00898 00899 /*! @brief Read current value of the AIPS_PACRA_TP5 field. */ 00900 #define BR_AIPS_PACRA_TP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP5))) 00901 00902 /*! @brief Format value for bitfield AIPS_PACRA_TP5. */ 00903 #define BF_AIPS_PACRA_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP5) & BM_AIPS_PACRA_TP5) 00904 00905 /*! @brief Set the TP5 field to a new value. */ 00906 #define BW_AIPS_PACRA_TP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP5), v)) 00907 /*@}*/ 00908 00909 /*! 00910 * @name Register AIPS_PACRA, field WP5[9] (RW) 00911 * 00912 * Determines whether the peripheral allows write accesses. When this field is 00913 * set and a write access is attempted, access terminates with an error response 00914 * and no peripheral access initiates. 00915 * 00916 * Values: 00917 * - 0 - This peripheral allows write accesses. 00918 * - 1 - This peripheral is write protected. 00919 */ 00920 /*@{*/ 00921 #define BP_AIPS_PACRA_WP5 (9U) /*!< Bit position for AIPS_PACRA_WP5. */ 00922 #define BM_AIPS_PACRA_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRA_WP5. */ 00923 #define BS_AIPS_PACRA_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP5. */ 00924 00925 /*! @brief Read current value of the AIPS_PACRA_WP5 field. */ 00926 #define BR_AIPS_PACRA_WP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP5))) 00927 00928 /*! @brief Format value for bitfield AIPS_PACRA_WP5. */ 00929 #define BF_AIPS_PACRA_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP5) & BM_AIPS_PACRA_WP5) 00930 00931 /*! @brief Set the WP5 field to a new value. */ 00932 #define BW_AIPS_PACRA_WP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP5), v)) 00933 /*@}*/ 00934 00935 /*! 00936 * @name Register AIPS_PACRA, field SP5[10] (RW) 00937 * 00938 * Determines whether the peripheral requires supervisor privilege level for 00939 * accesses. When this field is set, the master privilege level must indicate the 00940 * supervisor access attribute, and the MPRx[MPLn] control field for the master 00941 * must be set. If not, access terminates with an error response and no peripheral 00942 * access initiates. 00943 * 00944 * Values: 00945 * - 0 - This peripheral does not require supervisor privilege level for 00946 * accesses. 00947 * - 1 - This peripheral requires supervisor privilege level for accesses. 00948 */ 00949 /*@{*/ 00950 #define BP_AIPS_PACRA_SP5 (10U) /*!< Bit position for AIPS_PACRA_SP5. */ 00951 #define BM_AIPS_PACRA_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRA_SP5. */ 00952 #define BS_AIPS_PACRA_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP5. */ 00953 00954 /*! @brief Read current value of the AIPS_PACRA_SP5 field. */ 00955 #define BR_AIPS_PACRA_SP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP5))) 00956 00957 /*! @brief Format value for bitfield AIPS_PACRA_SP5. */ 00958 #define BF_AIPS_PACRA_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP5) & BM_AIPS_PACRA_SP5) 00959 00960 /*! @brief Set the SP5 field to a new value. */ 00961 #define BW_AIPS_PACRA_SP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP5), v)) 00962 /*@}*/ 00963 00964 /*! 00965 * @name Register AIPS_PACRA, field TP4[12] (RW) 00966 * 00967 * Determines whether the peripheral allows accesses from an untrusted master. 00968 * When this field is set and an access is attempted by an untrusted master, the 00969 * access terminates with an error response and no peripheral access initiates. 00970 * 00971 * Values: 00972 * - 0 - Accesses from an untrusted master are allowed. 00973 * - 1 - Accesses from an untrusted master are not allowed. 00974 */ 00975 /*@{*/ 00976 #define BP_AIPS_PACRA_TP4 (12U) /*!< Bit position for AIPS_PACRA_TP4. */ 00977 #define BM_AIPS_PACRA_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRA_TP4. */ 00978 #define BS_AIPS_PACRA_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP4. */ 00979 00980 /*! @brief Read current value of the AIPS_PACRA_TP4 field. */ 00981 #define BR_AIPS_PACRA_TP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP4))) 00982 00983 /*! @brief Format value for bitfield AIPS_PACRA_TP4. */ 00984 #define BF_AIPS_PACRA_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP4) & BM_AIPS_PACRA_TP4) 00985 00986 /*! @brief Set the TP4 field to a new value. */ 00987 #define BW_AIPS_PACRA_TP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP4), v)) 00988 /*@}*/ 00989 00990 /*! 00991 * @name Register AIPS_PACRA, field WP4[13] (RW) 00992 * 00993 * Determines whether the peripheral allows write accesss. When this bit is set 00994 * and a write access is attempted, access terminates with an error response and 00995 * no peripheral access initiates. 00996 * 00997 * Values: 00998 * - 0 - This peripheral allows write accesses. 00999 * - 1 - This peripheral is write protected. 01000 */ 01001 /*@{*/ 01002 #define BP_AIPS_PACRA_WP4 (13U) /*!< Bit position for AIPS_PACRA_WP4. */ 01003 #define BM_AIPS_PACRA_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRA_WP4. */ 01004 #define BS_AIPS_PACRA_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP4. */ 01005 01006 /*! @brief Read current value of the AIPS_PACRA_WP4 field. */ 01007 #define BR_AIPS_PACRA_WP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP4))) 01008 01009 /*! @brief Format value for bitfield AIPS_PACRA_WP4. */ 01010 #define BF_AIPS_PACRA_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP4) & BM_AIPS_PACRA_WP4) 01011 01012 /*! @brief Set the WP4 field to a new value. */ 01013 #define BW_AIPS_PACRA_WP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP4), v)) 01014 /*@}*/ 01015 01016 /*! 01017 * @name Register AIPS_PACRA, field SP4[14] (RW) 01018 * 01019 * Determines whether the peripheral requires supervisor privilege level for 01020 * accesses. When this field is set, the master privilege level must indicate the 01021 * supervisor access attribute, and the MPRx[MPLn] control field for the master 01022 * must be set. If not, access terminates with an error response and no peripheral 01023 * access initiates. 01024 * 01025 * Values: 01026 * - 0 - This peripheral does not require supervisor privilege level for 01027 * accesses. 01028 * - 1 - This peripheral requires supervisor privilege level for accesses. 01029 */ 01030 /*@{*/ 01031 #define BP_AIPS_PACRA_SP4 (14U) /*!< Bit position for AIPS_PACRA_SP4. */ 01032 #define BM_AIPS_PACRA_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRA_SP4. */ 01033 #define BS_AIPS_PACRA_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP4. */ 01034 01035 /*! @brief Read current value of the AIPS_PACRA_SP4 field. */ 01036 #define BR_AIPS_PACRA_SP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP4))) 01037 01038 /*! @brief Format value for bitfield AIPS_PACRA_SP4. */ 01039 #define BF_AIPS_PACRA_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP4) & BM_AIPS_PACRA_SP4) 01040 01041 /*! @brief Set the SP4 field to a new value. */ 01042 #define BW_AIPS_PACRA_SP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP4), v)) 01043 /*@}*/ 01044 01045 /*! 01046 * @name Register AIPS_PACRA, field TP3[16] (RW) 01047 * 01048 * Determines whether the peripheral allows accesses from an untrusted master. 01049 * When this bit is set and an access is attempted by an untrusted master, the 01050 * access terminates with an error response and no peripheral access initiates. 01051 * 01052 * Values: 01053 * - 0 - Accesses from an untrusted master are allowed. 01054 * - 1 - Accesses from an untrusted master are not allowed. 01055 */ 01056 /*@{*/ 01057 #define BP_AIPS_PACRA_TP3 (16U) /*!< Bit position for AIPS_PACRA_TP3. */ 01058 #define BM_AIPS_PACRA_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRA_TP3. */ 01059 #define BS_AIPS_PACRA_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP3. */ 01060 01061 /*! @brief Read current value of the AIPS_PACRA_TP3 field. */ 01062 #define BR_AIPS_PACRA_TP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP3))) 01063 01064 /*! @brief Format value for bitfield AIPS_PACRA_TP3. */ 01065 #define BF_AIPS_PACRA_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP3) & BM_AIPS_PACRA_TP3) 01066 01067 /*! @brief Set the TP3 field to a new value. */ 01068 #define BW_AIPS_PACRA_TP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP3), v)) 01069 /*@}*/ 01070 01071 /*! 01072 * @name Register AIPS_PACRA, field WP3[17] (RW) 01073 * 01074 * Determines whether the peripheral allows write accesses. When this field is 01075 * set and a write access is attempted, access terminates with an error response 01076 * and no peripheral access initiates. 01077 * 01078 * Values: 01079 * - 0 - This peripheral allows write accesses. 01080 * - 1 - This peripheral is write protected. 01081 */ 01082 /*@{*/ 01083 #define BP_AIPS_PACRA_WP3 (17U) /*!< Bit position for AIPS_PACRA_WP3. */ 01084 #define BM_AIPS_PACRA_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRA_WP3. */ 01085 #define BS_AIPS_PACRA_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP3. */ 01086 01087 /*! @brief Read current value of the AIPS_PACRA_WP3 field. */ 01088 #define BR_AIPS_PACRA_WP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP3))) 01089 01090 /*! @brief Format value for bitfield AIPS_PACRA_WP3. */ 01091 #define BF_AIPS_PACRA_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP3) & BM_AIPS_PACRA_WP3) 01092 01093 /*! @brief Set the WP3 field to a new value. */ 01094 #define BW_AIPS_PACRA_WP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP3), v)) 01095 /*@}*/ 01096 01097 /*! 01098 * @name Register AIPS_PACRA, field SP3[18] (RW) 01099 * 01100 * Determines whether the peripheral requires supervisor privilege level for 01101 * access. When this bit is set, the master privilege level must indicate the 01102 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 01103 * set. If not, access terminates with an error response and no peripheral access 01104 * initiates. 01105 * 01106 * Values: 01107 * - 0 - This peripheral does not require supervisor privilege level for 01108 * accesses. 01109 * - 1 - This peripheral requires supervisor privilege level for accesses. 01110 */ 01111 /*@{*/ 01112 #define BP_AIPS_PACRA_SP3 (18U) /*!< Bit position for AIPS_PACRA_SP3. */ 01113 #define BM_AIPS_PACRA_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRA_SP3. */ 01114 #define BS_AIPS_PACRA_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP3. */ 01115 01116 /*! @brief Read current value of the AIPS_PACRA_SP3 field. */ 01117 #define BR_AIPS_PACRA_SP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP3))) 01118 01119 /*! @brief Format value for bitfield AIPS_PACRA_SP3. */ 01120 #define BF_AIPS_PACRA_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP3) & BM_AIPS_PACRA_SP3) 01121 01122 /*! @brief Set the SP3 field to a new value. */ 01123 #define BW_AIPS_PACRA_SP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP3), v)) 01124 /*@}*/ 01125 01126 /*! 01127 * @name Register AIPS_PACRA, field TP2[20] (RW) 01128 * 01129 * Determines whether the peripheral allows accesses from an untrusted master. 01130 * When this field is set and an access is attempted by an untrusted master, the 01131 * access terminates with an error response and no peripheral access initiates. 01132 * 01133 * Values: 01134 * - 0 - Accesses from an untrusted master are allowed. 01135 * - 1 - Accesses from an untrusted master are not allowed. 01136 */ 01137 /*@{*/ 01138 #define BP_AIPS_PACRA_TP2 (20U) /*!< Bit position for AIPS_PACRA_TP2. */ 01139 #define BM_AIPS_PACRA_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRA_TP2. */ 01140 #define BS_AIPS_PACRA_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP2. */ 01141 01142 /*! @brief Read current value of the AIPS_PACRA_TP2 field. */ 01143 #define BR_AIPS_PACRA_TP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP2))) 01144 01145 /*! @brief Format value for bitfield AIPS_PACRA_TP2. */ 01146 #define BF_AIPS_PACRA_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP2) & BM_AIPS_PACRA_TP2) 01147 01148 /*! @brief Set the TP2 field to a new value. */ 01149 #define BW_AIPS_PACRA_TP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP2), v)) 01150 /*@}*/ 01151 01152 /*! 01153 * @name Register AIPS_PACRA, field WP2[21] (RW) 01154 * 01155 * Determines whether the peripheral allows write accesss. When this bit is set 01156 * and a write access is attempted, access terminates with an error response and 01157 * no peripheral access initiates. 01158 * 01159 * Values: 01160 * - 0 - This peripheral allows write accesses. 01161 * - 1 - This peripheral is write protected. 01162 */ 01163 /*@{*/ 01164 #define BP_AIPS_PACRA_WP2 (21U) /*!< Bit position for AIPS_PACRA_WP2. */ 01165 #define BM_AIPS_PACRA_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRA_WP2. */ 01166 #define BS_AIPS_PACRA_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP2. */ 01167 01168 /*! @brief Read current value of the AIPS_PACRA_WP2 field. */ 01169 #define BR_AIPS_PACRA_WP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP2))) 01170 01171 /*! @brief Format value for bitfield AIPS_PACRA_WP2. */ 01172 #define BF_AIPS_PACRA_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP2) & BM_AIPS_PACRA_WP2) 01173 01174 /*! @brief Set the WP2 field to a new value. */ 01175 #define BW_AIPS_PACRA_WP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP2), v)) 01176 /*@}*/ 01177 01178 /*! 01179 * @name Register AIPS_PACRA, field SP2[22] (RW) 01180 * 01181 * Determines whether the peripheral requires supervisor privilege level for 01182 * accesses. When this field is set, the master privilege level must indicate the 01183 * supervisor access attribute, and the MPRx[MPLn] control field for the master 01184 * must be set. If not, access terminates with an error response and no peripheral 01185 * access initiates. 01186 * 01187 * Values: 01188 * - 0 - This peripheral does not require supervisor privilege level for 01189 * accesses. 01190 * - 1 - This peripheral requires supervisor privilege level for accesses. 01191 */ 01192 /*@{*/ 01193 #define BP_AIPS_PACRA_SP2 (22U) /*!< Bit position for AIPS_PACRA_SP2. */ 01194 #define BM_AIPS_PACRA_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRA_SP2. */ 01195 #define BS_AIPS_PACRA_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP2. */ 01196 01197 /*! @brief Read current value of the AIPS_PACRA_SP2 field. */ 01198 #define BR_AIPS_PACRA_SP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP2))) 01199 01200 /*! @brief Format value for bitfield AIPS_PACRA_SP2. */ 01201 #define BF_AIPS_PACRA_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP2) & BM_AIPS_PACRA_SP2) 01202 01203 /*! @brief Set the SP2 field to a new value. */ 01204 #define BW_AIPS_PACRA_SP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP2), v)) 01205 /*@}*/ 01206 01207 /*! 01208 * @name Register AIPS_PACRA, field TP1[24] (RW) 01209 * 01210 * Determines whether the peripheral allows accesses from an untrusted master. 01211 * When this bit is set and an access is attempted by an untrusted master, the 01212 * access terminates with an error response and no peripheral access initiates. 01213 * 01214 * Values: 01215 * - 0 - Accesses from an untrusted master are allowed. 01216 * - 1 - Accesses from an untrusted master are not allowed. 01217 */ 01218 /*@{*/ 01219 #define BP_AIPS_PACRA_TP1 (24U) /*!< Bit position for AIPS_PACRA_TP1. */ 01220 #define BM_AIPS_PACRA_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRA_TP1. */ 01221 #define BS_AIPS_PACRA_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP1. */ 01222 01223 /*! @brief Read current value of the AIPS_PACRA_TP1 field. */ 01224 #define BR_AIPS_PACRA_TP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP1))) 01225 01226 /*! @brief Format value for bitfield AIPS_PACRA_TP1. */ 01227 #define BF_AIPS_PACRA_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP1) & BM_AIPS_PACRA_TP1) 01228 01229 /*! @brief Set the TP1 field to a new value. */ 01230 #define BW_AIPS_PACRA_TP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP1), v)) 01231 /*@}*/ 01232 01233 /*! 01234 * @name Register AIPS_PACRA, field WP1[25] (RW) 01235 * 01236 * Determines whether the peripheral allows write accesses. When this field is 01237 * set and a write access is attempted, access terminates with an error response 01238 * and no peripheral access initiates. 01239 * 01240 * Values: 01241 * - 0 - This peripheral allows write accesses. 01242 * - 1 - This peripheral is write protected. 01243 */ 01244 /*@{*/ 01245 #define BP_AIPS_PACRA_WP1 (25U) /*!< Bit position for AIPS_PACRA_WP1. */ 01246 #define BM_AIPS_PACRA_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRA_WP1. */ 01247 #define BS_AIPS_PACRA_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP1. */ 01248 01249 /*! @brief Read current value of the AIPS_PACRA_WP1 field. */ 01250 #define BR_AIPS_PACRA_WP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP1))) 01251 01252 /*! @brief Format value for bitfield AIPS_PACRA_WP1. */ 01253 #define BF_AIPS_PACRA_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP1) & BM_AIPS_PACRA_WP1) 01254 01255 /*! @brief Set the WP1 field to a new value. */ 01256 #define BW_AIPS_PACRA_WP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP1), v)) 01257 /*@}*/ 01258 01259 /*! 01260 * @name Register AIPS_PACRA, field SP1[26] (RW) 01261 * 01262 * Determines whether the peripheral requires supervisor privilege level for 01263 * accesses. When this field is set, the master privilege level must indicate the 01264 * supervisor access attribute, and the MPRx[MPLn] control field for the master 01265 * must be set. If not, access terminates with an error response and no peripheral 01266 * access initiates. 01267 * 01268 * Values: 01269 * - 0 - This peripheral does not require supervisor privilege level for 01270 * accesses. 01271 * - 1 - This peripheral requires supervisor privilege level for accesses. 01272 */ 01273 /*@{*/ 01274 #define BP_AIPS_PACRA_SP1 (26U) /*!< Bit position for AIPS_PACRA_SP1. */ 01275 #define BM_AIPS_PACRA_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRA_SP1. */ 01276 #define BS_AIPS_PACRA_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP1. */ 01277 01278 /*! @brief Read current value of the AIPS_PACRA_SP1 field. */ 01279 #define BR_AIPS_PACRA_SP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP1))) 01280 01281 /*! @brief Format value for bitfield AIPS_PACRA_SP1. */ 01282 #define BF_AIPS_PACRA_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP1) & BM_AIPS_PACRA_SP1) 01283 01284 /*! @brief Set the SP1 field to a new value. */ 01285 #define BW_AIPS_PACRA_SP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP1), v)) 01286 /*@}*/ 01287 01288 /*! 01289 * @name Register AIPS_PACRA, field TP0[28] (RW) 01290 * 01291 * Determines whether the peripheral allows accesses from an untrusted master. 01292 * When this field is set and an access is attempted by an untrusted master, the 01293 * access terminates with an error response and no peripheral access initiates. 01294 * 01295 * Values: 01296 * - 0 - Accesses from an untrusted master are allowed. 01297 * - 1 - Accesses from an untrusted master are not allowed. 01298 */ 01299 /*@{*/ 01300 #define BP_AIPS_PACRA_TP0 (28U) /*!< Bit position for AIPS_PACRA_TP0. */ 01301 #define BM_AIPS_PACRA_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRA_TP0. */ 01302 #define BS_AIPS_PACRA_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRA_TP0. */ 01303 01304 /*! @brief Read current value of the AIPS_PACRA_TP0 field. */ 01305 #define BR_AIPS_PACRA_TP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP0))) 01306 01307 /*! @brief Format value for bitfield AIPS_PACRA_TP0. */ 01308 #define BF_AIPS_PACRA_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_TP0) & BM_AIPS_PACRA_TP0) 01309 01310 /*! @brief Set the TP0 field to a new value. */ 01311 #define BW_AIPS_PACRA_TP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_TP0), v)) 01312 /*@}*/ 01313 01314 /*! 01315 * @name Register AIPS_PACRA, field WP0[29] (RW) 01316 * 01317 * Determines whether the peripheral allows write accesss. When this bit is set 01318 * and a write access is attempted, access terminates with an error response and 01319 * no peripheral access initiates. 01320 * 01321 * Values: 01322 * - 0 - This peripheral allows write accesses. 01323 * - 1 - This peripheral is write protected. 01324 */ 01325 /*@{*/ 01326 #define BP_AIPS_PACRA_WP0 (29U) /*!< Bit position for AIPS_PACRA_WP0. */ 01327 #define BM_AIPS_PACRA_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRA_WP0. */ 01328 #define BS_AIPS_PACRA_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRA_WP0. */ 01329 01330 /*! @brief Read current value of the AIPS_PACRA_WP0 field. */ 01331 #define BR_AIPS_PACRA_WP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP0))) 01332 01333 /*! @brief Format value for bitfield AIPS_PACRA_WP0. */ 01334 #define BF_AIPS_PACRA_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_WP0) & BM_AIPS_PACRA_WP0) 01335 01336 /*! @brief Set the WP0 field to a new value. */ 01337 #define BW_AIPS_PACRA_WP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_WP0), v)) 01338 /*@}*/ 01339 01340 /*! 01341 * @name Register AIPS_PACRA, field SP0[30] (RW) 01342 * 01343 * Determines whether the peripheral requires supervisor privilege level for 01344 * accesses. When this field is set, the master privilege level must indicate the 01345 * supervisor access attribute, and the MPRx[MPLn] control field for the master 01346 * must be set. If not, access terminates with an error response and no peripheral 01347 * access initiates. 01348 * 01349 * Values: 01350 * - 0 - This peripheral does not require supervisor privilege level for 01351 * accesses. 01352 * - 1 - This peripheral requires supervisor privilege level for accesses. 01353 */ 01354 /*@{*/ 01355 #define BP_AIPS_PACRA_SP0 (30U) /*!< Bit position for AIPS_PACRA_SP0. */ 01356 #define BM_AIPS_PACRA_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRA_SP0. */ 01357 #define BS_AIPS_PACRA_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRA_SP0. */ 01358 01359 /*! @brief Read current value of the AIPS_PACRA_SP0 field. */ 01360 #define BR_AIPS_PACRA_SP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP0))) 01361 01362 /*! @brief Format value for bitfield AIPS_PACRA_SP0. */ 01363 #define BF_AIPS_PACRA_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRA_SP0) & BM_AIPS_PACRA_SP0) 01364 01365 /*! @brief Set the SP0 field to a new value. */ 01366 #define BW_AIPS_PACRA_SP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRA_ADDR(x), BP_AIPS_PACRA_SP0), v)) 01367 /*@}*/ 01368 01369 /******************************************************************************* 01370 * HW_AIPS_PACRB - Peripheral Access Control Register 01371 ******************************************************************************/ 01372 01373 /*! 01374 * @brief HW_AIPS_PACRB - Peripheral Access Control Register (RW) 01375 * 01376 * Reset value: 0x44004400U 01377 * 01378 * Each PACR register consists of eight 4-bit PACR fields. Each PACR field 01379 * defines the access levels for a particular peripheral. The mapping between a 01380 * peripheral and its PACR field is shown in the table below. The peripheral assignment 01381 * to each PACR is defined by the memory map slot that the peripheral is 01382 * assigned to. See this chip's memory map for the assignment of a particular 01383 * peripheral. The following table shows the location of each peripheral slot's PACR field 01384 * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] 01385 * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7 01386 * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC 01387 * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24 01388 * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38 01389 * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 01390 * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47 01391 * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH 01392 * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64 01393 * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74 01394 * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83 01395 * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93 01396 * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 01397 * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 01398 * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119 01399 * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80 01400 * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR 01401 * A-D, which control peripheral slots 0-31, are shown below. The following 01402 * section, PACRPeripheral Access Control Register , shows the register field 01403 * descriptions for PACR E-P. All PACR registers are identical. They are divided into two 01404 * sections because they occupy two non-contiguous address spaces. 01405 */ 01406 typedef union _hw_aips_pacrb 01407 { 01408 uint32_t U; 01409 struct _hw_aips_pacrb_bitfields 01410 { 01411 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 01412 uint32_t WP7 : 1; /*!< [1] Write Protect */ 01413 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 01414 uint32_t RESERVED0 : 1; /*!< [3] */ 01415 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 01416 uint32_t WP6 : 1; /*!< [5] Write Protect */ 01417 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 01418 uint32_t RESERVED1 : 1; /*!< [7] */ 01419 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 01420 uint32_t WP5 : 1; /*!< [9] Write Protect */ 01421 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 01422 uint32_t RESERVED2 : 1; /*!< [11] */ 01423 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 01424 uint32_t WP4 : 1; /*!< [13] Write Protect */ 01425 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 01426 uint32_t RESERVED3 : 1; /*!< [15] */ 01427 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 01428 uint32_t WP3 : 1; /*!< [17] Write Protect */ 01429 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 01430 uint32_t RESERVED4 : 1; /*!< [19] */ 01431 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 01432 uint32_t WP2 : 1; /*!< [21] Write Protect */ 01433 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 01434 uint32_t RESERVED5 : 1; /*!< [23] */ 01435 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 01436 uint32_t WP1 : 1; /*!< [25] Write Protect */ 01437 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 01438 uint32_t RESERVED6 : 1; /*!< [27] */ 01439 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 01440 uint32_t WP0 : 1; /*!< [29] Write Protect */ 01441 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 01442 uint32_t RESERVED7 : 1; /*!< [31] */ 01443 } B; 01444 } hw_aips_pacrb_t; 01445 01446 /*! 01447 * @name Constants and macros for entire AIPS_PACRB register 01448 */ 01449 /*@{*/ 01450 #define HW_AIPS_PACRB_ADDR(x) ((x) + 0x24U) 01451 01452 #define HW_AIPS_PACRB(x) (*(__IO hw_aips_pacrb_t *) HW_AIPS_PACRB_ADDR(x)) 01453 #define HW_AIPS_PACRB_RD(x) (ADDRESS_READ(hw_aips_pacrb_t, HW_AIPS_PACRB_ADDR(x))) 01454 #define HW_AIPS_PACRB_WR(x, v) (ADDRESS_WRITE(hw_aips_pacrb_t, HW_AIPS_PACRB_ADDR(x), v)) 01455 #define HW_AIPS_PACRB_SET(x, v) (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) | (v))) 01456 #define HW_AIPS_PACRB_CLR(x, v) (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) & ~(v))) 01457 #define HW_AIPS_PACRB_TOG(x, v) (HW_AIPS_PACRB_WR(x, HW_AIPS_PACRB_RD(x) ^ (v))) 01458 /*@}*/ 01459 01460 /* 01461 * Constants & macros for individual AIPS_PACRB bitfields 01462 */ 01463 01464 /*! 01465 * @name Register AIPS_PACRB, field TP7[0] (RW) 01466 * 01467 * Determines whether the peripheral allows accesses from an untrusted master. 01468 * When this field is set and an access is attempted by an untrusted master, the 01469 * access terminates with an error response and no peripheral access initiates. 01470 * 01471 * Values: 01472 * - 0 - Accesses from an untrusted master are allowed. 01473 * - 1 - Accesses from an untrusted master are not allowed. 01474 */ 01475 /*@{*/ 01476 #define BP_AIPS_PACRB_TP7 (0U) /*!< Bit position for AIPS_PACRB_TP7. */ 01477 #define BM_AIPS_PACRB_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRB_TP7. */ 01478 #define BS_AIPS_PACRB_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP7. */ 01479 01480 /*! @brief Read current value of the AIPS_PACRB_TP7 field. */ 01481 #define BR_AIPS_PACRB_TP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP7))) 01482 01483 /*! @brief Format value for bitfield AIPS_PACRB_TP7. */ 01484 #define BF_AIPS_PACRB_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP7) & BM_AIPS_PACRB_TP7) 01485 01486 /*! @brief Set the TP7 field to a new value. */ 01487 #define BW_AIPS_PACRB_TP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP7), v)) 01488 /*@}*/ 01489 01490 /*! 01491 * @name Register AIPS_PACRB, field WP7[1] (RW) 01492 * 01493 * Determines whether the peripheral allows write accesses. When this field is 01494 * set and a write access is attempted, access terminates with an error response 01495 * and no peripheral access initiates. 01496 * 01497 * Values: 01498 * - 0 - This peripheral allows write accesses. 01499 * - 1 - This peripheral is write protected. 01500 */ 01501 /*@{*/ 01502 #define BP_AIPS_PACRB_WP7 (1U) /*!< Bit position for AIPS_PACRB_WP7. */ 01503 #define BM_AIPS_PACRB_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRB_WP7. */ 01504 #define BS_AIPS_PACRB_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP7. */ 01505 01506 /*! @brief Read current value of the AIPS_PACRB_WP7 field. */ 01507 #define BR_AIPS_PACRB_WP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP7))) 01508 01509 /*! @brief Format value for bitfield AIPS_PACRB_WP7. */ 01510 #define BF_AIPS_PACRB_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP7) & BM_AIPS_PACRB_WP7) 01511 01512 /*! @brief Set the WP7 field to a new value. */ 01513 #define BW_AIPS_PACRB_WP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP7), v)) 01514 /*@}*/ 01515 01516 /*! 01517 * @name Register AIPS_PACRB, field SP7[2] (RW) 01518 * 01519 * Determines whether the peripheral requires supervisor privilege level for 01520 * accesses. When this field is set, the master privilege level must indicate the 01521 * supervisor access attribute, and the MPRx[MPLn] control field for the master 01522 * must be set. If not, access terminates with an error response and no peripheral 01523 * access initiates. 01524 * 01525 * Values: 01526 * - 0 - This peripheral does not require supervisor privilege level for 01527 * accesses. 01528 * - 1 - This peripheral requires supervisor privilege level for accesses. 01529 */ 01530 /*@{*/ 01531 #define BP_AIPS_PACRB_SP7 (2U) /*!< Bit position for AIPS_PACRB_SP7. */ 01532 #define BM_AIPS_PACRB_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRB_SP7. */ 01533 #define BS_AIPS_PACRB_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP7. */ 01534 01535 /*! @brief Read current value of the AIPS_PACRB_SP7 field. */ 01536 #define BR_AIPS_PACRB_SP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP7))) 01537 01538 /*! @brief Format value for bitfield AIPS_PACRB_SP7. */ 01539 #define BF_AIPS_PACRB_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP7) & BM_AIPS_PACRB_SP7) 01540 01541 /*! @brief Set the SP7 field to a new value. */ 01542 #define BW_AIPS_PACRB_SP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP7), v)) 01543 /*@}*/ 01544 01545 /*! 01546 * @name Register AIPS_PACRB, field TP6[4] (RW) 01547 * 01548 * Determines whether the peripheral allows accesses from an untrusted master. 01549 * When this field is set and an access is attempted by an untrusted master, the 01550 * access terminates with an error response and no peripheral access initiates. 01551 * 01552 * Values: 01553 * - 0 - Accesses from an untrusted master are allowed. 01554 * - 1 - Accesses from an untrusted master are not allowed. 01555 */ 01556 /*@{*/ 01557 #define BP_AIPS_PACRB_TP6 (4U) /*!< Bit position for AIPS_PACRB_TP6. */ 01558 #define BM_AIPS_PACRB_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRB_TP6. */ 01559 #define BS_AIPS_PACRB_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP6. */ 01560 01561 /*! @brief Read current value of the AIPS_PACRB_TP6 field. */ 01562 #define BR_AIPS_PACRB_TP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP6))) 01563 01564 /*! @brief Format value for bitfield AIPS_PACRB_TP6. */ 01565 #define BF_AIPS_PACRB_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP6) & BM_AIPS_PACRB_TP6) 01566 01567 /*! @brief Set the TP6 field to a new value. */ 01568 #define BW_AIPS_PACRB_TP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP6), v)) 01569 /*@}*/ 01570 01571 /*! 01572 * @name Register AIPS_PACRB, field WP6[5] (RW) 01573 * 01574 * Determines whether the peripheral allows write accesses. When this field is 01575 * set and a write access is attempted, access terminates with an error response 01576 * and no peripheral access initiates. 01577 * 01578 * Values: 01579 * - 0 - This peripheral allows write accesses. 01580 * - 1 - This peripheral is write protected. 01581 */ 01582 /*@{*/ 01583 #define BP_AIPS_PACRB_WP6 (5U) /*!< Bit position for AIPS_PACRB_WP6. */ 01584 #define BM_AIPS_PACRB_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRB_WP6. */ 01585 #define BS_AIPS_PACRB_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP6. */ 01586 01587 /*! @brief Read current value of the AIPS_PACRB_WP6 field. */ 01588 #define BR_AIPS_PACRB_WP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP6))) 01589 01590 /*! @brief Format value for bitfield AIPS_PACRB_WP6. */ 01591 #define BF_AIPS_PACRB_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP6) & BM_AIPS_PACRB_WP6) 01592 01593 /*! @brief Set the WP6 field to a new value. */ 01594 #define BW_AIPS_PACRB_WP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP6), v)) 01595 /*@}*/ 01596 01597 /*! 01598 * @name Register AIPS_PACRB, field SP6[6] (RW) 01599 * 01600 * Determines whether the peripheral requires supervisor privilege level for 01601 * accesses. When this field is set, the master privilege level must indicate the 01602 * supervisor access attribute, and the MPRx[MPLn] control field for the master 01603 * must be set. If not, access terminates with an error response and no peripheral 01604 * access initiates. 01605 * 01606 * Values: 01607 * - 0 - This peripheral does not require supervisor privilege level for 01608 * accesses. 01609 * - 1 - This peripheral requires supervisor privilege level for accesses. 01610 */ 01611 /*@{*/ 01612 #define BP_AIPS_PACRB_SP6 (6U) /*!< Bit position for AIPS_PACRB_SP6. */ 01613 #define BM_AIPS_PACRB_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRB_SP6. */ 01614 #define BS_AIPS_PACRB_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP6. */ 01615 01616 /*! @brief Read current value of the AIPS_PACRB_SP6 field. */ 01617 #define BR_AIPS_PACRB_SP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP6))) 01618 01619 /*! @brief Format value for bitfield AIPS_PACRB_SP6. */ 01620 #define BF_AIPS_PACRB_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP6) & BM_AIPS_PACRB_SP6) 01621 01622 /*! @brief Set the SP6 field to a new value. */ 01623 #define BW_AIPS_PACRB_SP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP6), v)) 01624 /*@}*/ 01625 01626 /*! 01627 * @name Register AIPS_PACRB, field TP5[8] (RW) 01628 * 01629 * Determines whether the peripheral allows accesses from an untrusted master. 01630 * When this field is set and an access is attempted by an untrusted master, the 01631 * access terminates with an error response and no peripheral access initiates. 01632 * 01633 * Values: 01634 * - 0 - Accesses from an untrusted master are allowed. 01635 * - 1 - Accesses from an untrusted master are not allowed. 01636 */ 01637 /*@{*/ 01638 #define BP_AIPS_PACRB_TP5 (8U) /*!< Bit position for AIPS_PACRB_TP5. */ 01639 #define BM_AIPS_PACRB_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRB_TP5. */ 01640 #define BS_AIPS_PACRB_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP5. */ 01641 01642 /*! @brief Read current value of the AIPS_PACRB_TP5 field. */ 01643 #define BR_AIPS_PACRB_TP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP5))) 01644 01645 /*! @brief Format value for bitfield AIPS_PACRB_TP5. */ 01646 #define BF_AIPS_PACRB_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP5) & BM_AIPS_PACRB_TP5) 01647 01648 /*! @brief Set the TP5 field to a new value. */ 01649 #define BW_AIPS_PACRB_TP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP5), v)) 01650 /*@}*/ 01651 01652 /*! 01653 * @name Register AIPS_PACRB, field WP5[9] (RW) 01654 * 01655 * Determines whether the peripheral allows write accesses. When this field is 01656 * set and a write access is attempted, access terminates with an error response 01657 * and no peripheral access initiates. 01658 * 01659 * Values: 01660 * - 0 - This peripheral allows write accesses. 01661 * - 1 - This peripheral is write protected. 01662 */ 01663 /*@{*/ 01664 #define BP_AIPS_PACRB_WP5 (9U) /*!< Bit position for AIPS_PACRB_WP5. */ 01665 #define BM_AIPS_PACRB_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRB_WP5. */ 01666 #define BS_AIPS_PACRB_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP5. */ 01667 01668 /*! @brief Read current value of the AIPS_PACRB_WP5 field. */ 01669 #define BR_AIPS_PACRB_WP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP5))) 01670 01671 /*! @brief Format value for bitfield AIPS_PACRB_WP5. */ 01672 #define BF_AIPS_PACRB_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP5) & BM_AIPS_PACRB_WP5) 01673 01674 /*! @brief Set the WP5 field to a new value. */ 01675 #define BW_AIPS_PACRB_WP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP5), v)) 01676 /*@}*/ 01677 01678 /*! 01679 * @name Register AIPS_PACRB, field SP5[10] (RW) 01680 * 01681 * Determines whether the peripheral requires supervisor privilege level for 01682 * accesses. When this field is set, the master privilege level must indicate the 01683 * supervisor access attribute, and the MPRx[MPLn] control field for the master 01684 * must be set. If not, access terminates with an error response and no peripheral 01685 * access initiates. 01686 * 01687 * Values: 01688 * - 0 - This peripheral does not require supervisor privilege level for 01689 * accesses. 01690 * - 1 - This peripheral requires supervisor privilege level for accesses. 01691 */ 01692 /*@{*/ 01693 #define BP_AIPS_PACRB_SP5 (10U) /*!< Bit position for AIPS_PACRB_SP5. */ 01694 #define BM_AIPS_PACRB_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRB_SP5. */ 01695 #define BS_AIPS_PACRB_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP5. */ 01696 01697 /*! @brief Read current value of the AIPS_PACRB_SP5 field. */ 01698 #define BR_AIPS_PACRB_SP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP5))) 01699 01700 /*! @brief Format value for bitfield AIPS_PACRB_SP5. */ 01701 #define BF_AIPS_PACRB_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP5) & BM_AIPS_PACRB_SP5) 01702 01703 /*! @brief Set the SP5 field to a new value. */ 01704 #define BW_AIPS_PACRB_SP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP5), v)) 01705 /*@}*/ 01706 01707 /*! 01708 * @name Register AIPS_PACRB, field TP4[12] (RW) 01709 * 01710 * Determines whether the peripheral allows accesses from an untrusted master. 01711 * When this field is set and an access is attempted by an untrusted master, the 01712 * access terminates with an error response and no peripheral access initiates. 01713 * 01714 * Values: 01715 * - 0 - Accesses from an untrusted master are allowed. 01716 * - 1 - Accesses from an untrusted master are not allowed. 01717 */ 01718 /*@{*/ 01719 #define BP_AIPS_PACRB_TP4 (12U) /*!< Bit position for AIPS_PACRB_TP4. */ 01720 #define BM_AIPS_PACRB_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRB_TP4. */ 01721 #define BS_AIPS_PACRB_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP4. */ 01722 01723 /*! @brief Read current value of the AIPS_PACRB_TP4 field. */ 01724 #define BR_AIPS_PACRB_TP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP4))) 01725 01726 /*! @brief Format value for bitfield AIPS_PACRB_TP4. */ 01727 #define BF_AIPS_PACRB_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP4) & BM_AIPS_PACRB_TP4) 01728 01729 /*! @brief Set the TP4 field to a new value. */ 01730 #define BW_AIPS_PACRB_TP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP4), v)) 01731 /*@}*/ 01732 01733 /*! 01734 * @name Register AIPS_PACRB, field WP4[13] (RW) 01735 * 01736 * Determines whether the peripheral allows write accesss. When this bit is set 01737 * and a write access is attempted, access terminates with an error response and 01738 * no peripheral access initiates. 01739 * 01740 * Values: 01741 * - 0 - This peripheral allows write accesses. 01742 * - 1 - This peripheral is write protected. 01743 */ 01744 /*@{*/ 01745 #define BP_AIPS_PACRB_WP4 (13U) /*!< Bit position for AIPS_PACRB_WP4. */ 01746 #define BM_AIPS_PACRB_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRB_WP4. */ 01747 #define BS_AIPS_PACRB_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP4. */ 01748 01749 /*! @brief Read current value of the AIPS_PACRB_WP4 field. */ 01750 #define BR_AIPS_PACRB_WP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP4))) 01751 01752 /*! @brief Format value for bitfield AIPS_PACRB_WP4. */ 01753 #define BF_AIPS_PACRB_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP4) & BM_AIPS_PACRB_WP4) 01754 01755 /*! @brief Set the WP4 field to a new value. */ 01756 #define BW_AIPS_PACRB_WP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP4), v)) 01757 /*@}*/ 01758 01759 /*! 01760 * @name Register AIPS_PACRB, field SP4[14] (RW) 01761 * 01762 * Determines whether the peripheral requires supervisor privilege level for 01763 * accesses. When this field is set, the master privilege level must indicate the 01764 * supervisor access attribute, and the MPRx[MPLn] control field for the master 01765 * must be set. If not, access terminates with an error response and no peripheral 01766 * access initiates. 01767 * 01768 * Values: 01769 * - 0 - This peripheral does not require supervisor privilege level for 01770 * accesses. 01771 * - 1 - This peripheral requires supervisor privilege level for accesses. 01772 */ 01773 /*@{*/ 01774 #define BP_AIPS_PACRB_SP4 (14U) /*!< Bit position for AIPS_PACRB_SP4. */ 01775 #define BM_AIPS_PACRB_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRB_SP4. */ 01776 #define BS_AIPS_PACRB_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP4. */ 01777 01778 /*! @brief Read current value of the AIPS_PACRB_SP4 field. */ 01779 #define BR_AIPS_PACRB_SP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP4))) 01780 01781 /*! @brief Format value for bitfield AIPS_PACRB_SP4. */ 01782 #define BF_AIPS_PACRB_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP4) & BM_AIPS_PACRB_SP4) 01783 01784 /*! @brief Set the SP4 field to a new value. */ 01785 #define BW_AIPS_PACRB_SP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP4), v)) 01786 /*@}*/ 01787 01788 /*! 01789 * @name Register AIPS_PACRB, field TP3[16] (RW) 01790 * 01791 * Determines whether the peripheral allows accesses from an untrusted master. 01792 * When this bit is set and an access is attempted by an untrusted master, the 01793 * access terminates with an error response and no peripheral access initiates. 01794 * 01795 * Values: 01796 * - 0 - Accesses from an untrusted master are allowed. 01797 * - 1 - Accesses from an untrusted master are not allowed. 01798 */ 01799 /*@{*/ 01800 #define BP_AIPS_PACRB_TP3 (16U) /*!< Bit position for AIPS_PACRB_TP3. */ 01801 #define BM_AIPS_PACRB_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRB_TP3. */ 01802 #define BS_AIPS_PACRB_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP3. */ 01803 01804 /*! @brief Read current value of the AIPS_PACRB_TP3 field. */ 01805 #define BR_AIPS_PACRB_TP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP3))) 01806 01807 /*! @brief Format value for bitfield AIPS_PACRB_TP3. */ 01808 #define BF_AIPS_PACRB_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP3) & BM_AIPS_PACRB_TP3) 01809 01810 /*! @brief Set the TP3 field to a new value. */ 01811 #define BW_AIPS_PACRB_TP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP3), v)) 01812 /*@}*/ 01813 01814 /*! 01815 * @name Register AIPS_PACRB, field WP3[17] (RW) 01816 * 01817 * Determines whether the peripheral allows write accesses. When this field is 01818 * set and a write access is attempted, access terminates with an error response 01819 * and no peripheral access initiates. 01820 * 01821 * Values: 01822 * - 0 - This peripheral allows write accesses. 01823 * - 1 - This peripheral is write protected. 01824 */ 01825 /*@{*/ 01826 #define BP_AIPS_PACRB_WP3 (17U) /*!< Bit position for AIPS_PACRB_WP3. */ 01827 #define BM_AIPS_PACRB_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRB_WP3. */ 01828 #define BS_AIPS_PACRB_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP3. */ 01829 01830 /*! @brief Read current value of the AIPS_PACRB_WP3 field. */ 01831 #define BR_AIPS_PACRB_WP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP3))) 01832 01833 /*! @brief Format value for bitfield AIPS_PACRB_WP3. */ 01834 #define BF_AIPS_PACRB_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP3) & BM_AIPS_PACRB_WP3) 01835 01836 /*! @brief Set the WP3 field to a new value. */ 01837 #define BW_AIPS_PACRB_WP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP3), v)) 01838 /*@}*/ 01839 01840 /*! 01841 * @name Register AIPS_PACRB, field SP3[18] (RW) 01842 * 01843 * Determines whether the peripheral requires supervisor privilege level for 01844 * access. When this bit is set, the master privilege level must indicate the 01845 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 01846 * set. If not, access terminates with an error response and no peripheral access 01847 * initiates. 01848 * 01849 * Values: 01850 * - 0 - This peripheral does not require supervisor privilege level for 01851 * accesses. 01852 * - 1 - This peripheral requires supervisor privilege level for accesses. 01853 */ 01854 /*@{*/ 01855 #define BP_AIPS_PACRB_SP3 (18U) /*!< Bit position for AIPS_PACRB_SP3. */ 01856 #define BM_AIPS_PACRB_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRB_SP3. */ 01857 #define BS_AIPS_PACRB_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP3. */ 01858 01859 /*! @brief Read current value of the AIPS_PACRB_SP3 field. */ 01860 #define BR_AIPS_PACRB_SP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP3))) 01861 01862 /*! @brief Format value for bitfield AIPS_PACRB_SP3. */ 01863 #define BF_AIPS_PACRB_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP3) & BM_AIPS_PACRB_SP3) 01864 01865 /*! @brief Set the SP3 field to a new value. */ 01866 #define BW_AIPS_PACRB_SP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP3), v)) 01867 /*@}*/ 01868 01869 /*! 01870 * @name Register AIPS_PACRB, field TP2[20] (RW) 01871 * 01872 * Determines whether the peripheral allows accesses from an untrusted master. 01873 * When this field is set and an access is attempted by an untrusted master, the 01874 * access terminates with an error response and no peripheral access initiates. 01875 * 01876 * Values: 01877 * - 0 - Accesses from an untrusted master are allowed. 01878 * - 1 - Accesses from an untrusted master are not allowed. 01879 */ 01880 /*@{*/ 01881 #define BP_AIPS_PACRB_TP2 (20U) /*!< Bit position for AIPS_PACRB_TP2. */ 01882 #define BM_AIPS_PACRB_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRB_TP2. */ 01883 #define BS_AIPS_PACRB_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP2. */ 01884 01885 /*! @brief Read current value of the AIPS_PACRB_TP2 field. */ 01886 #define BR_AIPS_PACRB_TP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP2))) 01887 01888 /*! @brief Format value for bitfield AIPS_PACRB_TP2. */ 01889 #define BF_AIPS_PACRB_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP2) & BM_AIPS_PACRB_TP2) 01890 01891 /*! @brief Set the TP2 field to a new value. */ 01892 #define BW_AIPS_PACRB_TP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP2), v)) 01893 /*@}*/ 01894 01895 /*! 01896 * @name Register AIPS_PACRB, field WP2[21] (RW) 01897 * 01898 * Determines whether the peripheral allows write accesss. When this bit is set 01899 * and a write access is attempted, access terminates with an error response and 01900 * no peripheral access initiates. 01901 * 01902 * Values: 01903 * - 0 - This peripheral allows write accesses. 01904 * - 1 - This peripheral is write protected. 01905 */ 01906 /*@{*/ 01907 #define BP_AIPS_PACRB_WP2 (21U) /*!< Bit position for AIPS_PACRB_WP2. */ 01908 #define BM_AIPS_PACRB_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRB_WP2. */ 01909 #define BS_AIPS_PACRB_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP2. */ 01910 01911 /*! @brief Read current value of the AIPS_PACRB_WP2 field. */ 01912 #define BR_AIPS_PACRB_WP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP2))) 01913 01914 /*! @brief Format value for bitfield AIPS_PACRB_WP2. */ 01915 #define BF_AIPS_PACRB_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP2) & BM_AIPS_PACRB_WP2) 01916 01917 /*! @brief Set the WP2 field to a new value. */ 01918 #define BW_AIPS_PACRB_WP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP2), v)) 01919 /*@}*/ 01920 01921 /*! 01922 * @name Register AIPS_PACRB, field SP2[22] (RW) 01923 * 01924 * Determines whether the peripheral requires supervisor privilege level for 01925 * accesses. When this field is set, the master privilege level must indicate the 01926 * supervisor access attribute, and the MPRx[MPLn] control field for the master 01927 * must be set. If not, access terminates with an error response and no peripheral 01928 * access initiates. 01929 * 01930 * Values: 01931 * - 0 - This peripheral does not require supervisor privilege level for 01932 * accesses. 01933 * - 1 - This peripheral requires supervisor privilege level for accesses. 01934 */ 01935 /*@{*/ 01936 #define BP_AIPS_PACRB_SP2 (22U) /*!< Bit position for AIPS_PACRB_SP2. */ 01937 #define BM_AIPS_PACRB_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRB_SP2. */ 01938 #define BS_AIPS_PACRB_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP2. */ 01939 01940 /*! @brief Read current value of the AIPS_PACRB_SP2 field. */ 01941 #define BR_AIPS_PACRB_SP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP2))) 01942 01943 /*! @brief Format value for bitfield AIPS_PACRB_SP2. */ 01944 #define BF_AIPS_PACRB_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP2) & BM_AIPS_PACRB_SP2) 01945 01946 /*! @brief Set the SP2 field to a new value. */ 01947 #define BW_AIPS_PACRB_SP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP2), v)) 01948 /*@}*/ 01949 01950 /*! 01951 * @name Register AIPS_PACRB, field TP1[24] (RW) 01952 * 01953 * Determines whether the peripheral allows accesses from an untrusted master. 01954 * When this bit is set and an access is attempted by an untrusted master, the 01955 * access terminates with an error response and no peripheral access initiates. 01956 * 01957 * Values: 01958 * - 0 - Accesses from an untrusted master are allowed. 01959 * - 1 - Accesses from an untrusted master are not allowed. 01960 */ 01961 /*@{*/ 01962 #define BP_AIPS_PACRB_TP1 (24U) /*!< Bit position for AIPS_PACRB_TP1. */ 01963 #define BM_AIPS_PACRB_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRB_TP1. */ 01964 #define BS_AIPS_PACRB_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP1. */ 01965 01966 /*! @brief Read current value of the AIPS_PACRB_TP1 field. */ 01967 #define BR_AIPS_PACRB_TP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP1))) 01968 01969 /*! @brief Format value for bitfield AIPS_PACRB_TP1. */ 01970 #define BF_AIPS_PACRB_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP1) & BM_AIPS_PACRB_TP1) 01971 01972 /*! @brief Set the TP1 field to a new value. */ 01973 #define BW_AIPS_PACRB_TP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP1), v)) 01974 /*@}*/ 01975 01976 /*! 01977 * @name Register AIPS_PACRB, field WP1[25] (RW) 01978 * 01979 * Determines whether the peripheral allows write accesses. When this field is 01980 * set and a write access is attempted, access terminates with an error response 01981 * and no peripheral access initiates. 01982 * 01983 * Values: 01984 * - 0 - This peripheral allows write accesses. 01985 * - 1 - This peripheral is write protected. 01986 */ 01987 /*@{*/ 01988 #define BP_AIPS_PACRB_WP1 (25U) /*!< Bit position for AIPS_PACRB_WP1. */ 01989 #define BM_AIPS_PACRB_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRB_WP1. */ 01990 #define BS_AIPS_PACRB_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP1. */ 01991 01992 /*! @brief Read current value of the AIPS_PACRB_WP1 field. */ 01993 #define BR_AIPS_PACRB_WP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP1))) 01994 01995 /*! @brief Format value for bitfield AIPS_PACRB_WP1. */ 01996 #define BF_AIPS_PACRB_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP1) & BM_AIPS_PACRB_WP1) 01997 01998 /*! @brief Set the WP1 field to a new value. */ 01999 #define BW_AIPS_PACRB_WP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP1), v)) 02000 /*@}*/ 02001 02002 /*! 02003 * @name Register AIPS_PACRB, field SP1[26] (RW) 02004 * 02005 * Determines whether the peripheral requires supervisor privilege level for 02006 * accesses. When this field is set, the master privilege level must indicate the 02007 * supervisor access attribute, and the MPRx[MPLn] control field for the master 02008 * must be set. If not, access terminates with an error response and no peripheral 02009 * access initiates. 02010 * 02011 * Values: 02012 * - 0 - This peripheral does not require supervisor privilege level for 02013 * accesses. 02014 * - 1 - This peripheral requires supervisor privilege level for accesses. 02015 */ 02016 /*@{*/ 02017 #define BP_AIPS_PACRB_SP1 (26U) /*!< Bit position for AIPS_PACRB_SP1. */ 02018 #define BM_AIPS_PACRB_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRB_SP1. */ 02019 #define BS_AIPS_PACRB_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP1. */ 02020 02021 /*! @brief Read current value of the AIPS_PACRB_SP1 field. */ 02022 #define BR_AIPS_PACRB_SP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP1))) 02023 02024 /*! @brief Format value for bitfield AIPS_PACRB_SP1. */ 02025 #define BF_AIPS_PACRB_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP1) & BM_AIPS_PACRB_SP1) 02026 02027 /*! @brief Set the SP1 field to a new value. */ 02028 #define BW_AIPS_PACRB_SP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP1), v)) 02029 /*@}*/ 02030 02031 /*! 02032 * @name Register AIPS_PACRB, field TP0[28] (RW) 02033 * 02034 * Determines whether the peripheral allows accesses from an untrusted master. 02035 * When this field is set and an access is attempted by an untrusted master, the 02036 * access terminates with an error response and no peripheral access initiates. 02037 * 02038 * Values: 02039 * - 0 - Accesses from an untrusted master are allowed. 02040 * - 1 - Accesses from an untrusted master are not allowed. 02041 */ 02042 /*@{*/ 02043 #define BP_AIPS_PACRB_TP0 (28U) /*!< Bit position for AIPS_PACRB_TP0. */ 02044 #define BM_AIPS_PACRB_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRB_TP0. */ 02045 #define BS_AIPS_PACRB_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRB_TP0. */ 02046 02047 /*! @brief Read current value of the AIPS_PACRB_TP0 field. */ 02048 #define BR_AIPS_PACRB_TP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP0))) 02049 02050 /*! @brief Format value for bitfield AIPS_PACRB_TP0. */ 02051 #define BF_AIPS_PACRB_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_TP0) & BM_AIPS_PACRB_TP0) 02052 02053 /*! @brief Set the TP0 field to a new value. */ 02054 #define BW_AIPS_PACRB_TP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_TP0), v)) 02055 /*@}*/ 02056 02057 /*! 02058 * @name Register AIPS_PACRB, field WP0[29] (RW) 02059 * 02060 * Determines whether the peripheral allows write accesss. When this bit is set 02061 * and a write access is attempted, access terminates with an error response and 02062 * no peripheral access initiates. 02063 * 02064 * Values: 02065 * - 0 - This peripheral allows write accesses. 02066 * - 1 - This peripheral is write protected. 02067 */ 02068 /*@{*/ 02069 #define BP_AIPS_PACRB_WP0 (29U) /*!< Bit position for AIPS_PACRB_WP0. */ 02070 #define BM_AIPS_PACRB_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRB_WP0. */ 02071 #define BS_AIPS_PACRB_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRB_WP0. */ 02072 02073 /*! @brief Read current value of the AIPS_PACRB_WP0 field. */ 02074 #define BR_AIPS_PACRB_WP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP0))) 02075 02076 /*! @brief Format value for bitfield AIPS_PACRB_WP0. */ 02077 #define BF_AIPS_PACRB_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_WP0) & BM_AIPS_PACRB_WP0) 02078 02079 /*! @brief Set the WP0 field to a new value. */ 02080 #define BW_AIPS_PACRB_WP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_WP0), v)) 02081 /*@}*/ 02082 02083 /*! 02084 * @name Register AIPS_PACRB, field SP0[30] (RW) 02085 * 02086 * Determines whether the peripheral requires supervisor privilege level for 02087 * accesses. When this field is set, the master privilege level must indicate the 02088 * supervisor access attribute, and the MPRx[MPLn] control field for the master 02089 * must be set. If not, access terminates with an error response and no peripheral 02090 * access initiates. 02091 * 02092 * Values: 02093 * - 0 - This peripheral does not require supervisor privilege level for 02094 * accesses. 02095 * - 1 - This peripheral requires supervisor privilege level for accesses. 02096 */ 02097 /*@{*/ 02098 #define BP_AIPS_PACRB_SP0 (30U) /*!< Bit position for AIPS_PACRB_SP0. */ 02099 #define BM_AIPS_PACRB_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRB_SP0. */ 02100 #define BS_AIPS_PACRB_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRB_SP0. */ 02101 02102 /*! @brief Read current value of the AIPS_PACRB_SP0 field. */ 02103 #define BR_AIPS_PACRB_SP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP0))) 02104 02105 /*! @brief Format value for bitfield AIPS_PACRB_SP0. */ 02106 #define BF_AIPS_PACRB_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRB_SP0) & BM_AIPS_PACRB_SP0) 02107 02108 /*! @brief Set the SP0 field to a new value. */ 02109 #define BW_AIPS_PACRB_SP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRB_ADDR(x), BP_AIPS_PACRB_SP0), v)) 02110 /*@}*/ 02111 02112 /******************************************************************************* 02113 * HW_AIPS_PACRC - Peripheral Access Control Register 02114 ******************************************************************************/ 02115 02116 /*! 02117 * @brief HW_AIPS_PACRC - Peripheral Access Control Register (RW) 02118 * 02119 * Reset value: 0x00000000U 02120 * 02121 * Each PACR register consists of eight 4-bit PACR fields. Each PACR field 02122 * defines the access levels for a particular peripheral. The mapping between a 02123 * peripheral and its PACR field is shown in the table below. The peripheral assignment 02124 * to each PACR is defined by the memory map slot that the peripheral is 02125 * assigned to. See this chip's memory map for the assignment of a particular 02126 * peripheral. The following table shows the location of each peripheral slot's PACR field 02127 * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] 02128 * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7 02129 * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC 02130 * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24 02131 * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38 02132 * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 02133 * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47 02134 * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH 02135 * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64 02136 * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74 02137 * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83 02138 * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93 02139 * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 02140 * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 02141 * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119 02142 * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80 02143 * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR 02144 * A-D, which control peripheral slots 0-31, are shown below. The following 02145 * section, PACRPeripheral Access Control Register , shows the register field 02146 * descriptions for PACR E-P. All PACR registers are identical. They are divided into two 02147 * sections because they occupy two non-contiguous address spaces. 02148 */ 02149 typedef union _hw_aips_pacrc 02150 { 02151 uint32_t U; 02152 struct _hw_aips_pacrc_bitfields 02153 { 02154 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 02155 uint32_t WP7 : 1; /*!< [1] Write Protect */ 02156 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 02157 uint32_t RESERVED0 : 1; /*!< [3] */ 02158 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 02159 uint32_t WP6 : 1; /*!< [5] Write Protect */ 02160 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 02161 uint32_t RESERVED1 : 1; /*!< [7] */ 02162 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 02163 uint32_t WP5 : 1; /*!< [9] Write Protect */ 02164 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 02165 uint32_t RESERVED2 : 1; /*!< [11] */ 02166 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 02167 uint32_t WP4 : 1; /*!< [13] Write Protect */ 02168 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 02169 uint32_t RESERVED3 : 1; /*!< [15] */ 02170 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 02171 uint32_t WP3 : 1; /*!< [17] Write Protect */ 02172 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 02173 uint32_t RESERVED4 : 1; /*!< [19] */ 02174 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 02175 uint32_t WP2 : 1; /*!< [21] Write Protect */ 02176 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 02177 uint32_t RESERVED5 : 1; /*!< [23] */ 02178 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 02179 uint32_t WP1 : 1; /*!< [25] Write Protect */ 02180 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 02181 uint32_t RESERVED6 : 1; /*!< [27] */ 02182 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 02183 uint32_t WP0 : 1; /*!< [29] Write Protect */ 02184 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 02185 uint32_t RESERVED7 : 1; /*!< [31] */ 02186 } B; 02187 } hw_aips_pacrc_t; 02188 02189 /*! 02190 * @name Constants and macros for entire AIPS_PACRC register 02191 */ 02192 /*@{*/ 02193 #define HW_AIPS_PACRC_ADDR(x) ((x) + 0x28U) 02194 02195 #define HW_AIPS_PACRC(x) (*(__IO hw_aips_pacrc_t *) HW_AIPS_PACRC_ADDR(x)) 02196 #define HW_AIPS_PACRC_RD(x) (ADDRESS_READ(hw_aips_pacrc_t, HW_AIPS_PACRC_ADDR(x))) 02197 #define HW_AIPS_PACRC_WR(x, v) (ADDRESS_WRITE(hw_aips_pacrc_t, HW_AIPS_PACRC_ADDR(x), v)) 02198 #define HW_AIPS_PACRC_SET(x, v) (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) | (v))) 02199 #define HW_AIPS_PACRC_CLR(x, v) (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) & ~(v))) 02200 #define HW_AIPS_PACRC_TOG(x, v) (HW_AIPS_PACRC_WR(x, HW_AIPS_PACRC_RD(x) ^ (v))) 02201 /*@}*/ 02202 02203 /* 02204 * Constants & macros for individual AIPS_PACRC bitfields 02205 */ 02206 02207 /*! 02208 * @name Register AIPS_PACRC, field TP7[0] (RW) 02209 * 02210 * Determines whether the peripheral allows accesses from an untrusted master. 02211 * When this field is set and an access is attempted by an untrusted master, the 02212 * access terminates with an error response and no peripheral access initiates. 02213 * 02214 * Values: 02215 * - 0 - Accesses from an untrusted master are allowed. 02216 * - 1 - Accesses from an untrusted master are not allowed. 02217 */ 02218 /*@{*/ 02219 #define BP_AIPS_PACRC_TP7 (0U) /*!< Bit position for AIPS_PACRC_TP7. */ 02220 #define BM_AIPS_PACRC_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRC_TP7. */ 02221 #define BS_AIPS_PACRC_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP7. */ 02222 02223 /*! @brief Read current value of the AIPS_PACRC_TP7 field. */ 02224 #define BR_AIPS_PACRC_TP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP7))) 02225 02226 /*! @brief Format value for bitfield AIPS_PACRC_TP7. */ 02227 #define BF_AIPS_PACRC_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP7) & BM_AIPS_PACRC_TP7) 02228 02229 /*! @brief Set the TP7 field to a new value. */ 02230 #define BW_AIPS_PACRC_TP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP7), v)) 02231 /*@}*/ 02232 02233 /*! 02234 * @name Register AIPS_PACRC, field WP7[1] (RW) 02235 * 02236 * Determines whether the peripheral allows write accesses. When this field is 02237 * set and a write access is attempted, access terminates with an error response 02238 * and no peripheral access initiates. 02239 * 02240 * Values: 02241 * - 0 - This peripheral allows write accesses. 02242 * - 1 - This peripheral is write protected. 02243 */ 02244 /*@{*/ 02245 #define BP_AIPS_PACRC_WP7 (1U) /*!< Bit position for AIPS_PACRC_WP7. */ 02246 #define BM_AIPS_PACRC_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRC_WP7. */ 02247 #define BS_AIPS_PACRC_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP7. */ 02248 02249 /*! @brief Read current value of the AIPS_PACRC_WP7 field. */ 02250 #define BR_AIPS_PACRC_WP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP7))) 02251 02252 /*! @brief Format value for bitfield AIPS_PACRC_WP7. */ 02253 #define BF_AIPS_PACRC_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP7) & BM_AIPS_PACRC_WP7) 02254 02255 /*! @brief Set the WP7 field to a new value. */ 02256 #define BW_AIPS_PACRC_WP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP7), v)) 02257 /*@}*/ 02258 02259 /*! 02260 * @name Register AIPS_PACRC, field SP7[2] (RW) 02261 * 02262 * Determines whether the peripheral requires supervisor privilege level for 02263 * accesses. When this field is set, the master privilege level must indicate the 02264 * supervisor access attribute, and the MPRx[MPLn] control field for the master 02265 * must be set. If not, access terminates with an error response and no peripheral 02266 * access initiates. 02267 * 02268 * Values: 02269 * - 0 - This peripheral does not require supervisor privilege level for 02270 * accesses. 02271 * - 1 - This peripheral requires supervisor privilege level for accesses. 02272 */ 02273 /*@{*/ 02274 #define BP_AIPS_PACRC_SP7 (2U) /*!< Bit position for AIPS_PACRC_SP7. */ 02275 #define BM_AIPS_PACRC_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRC_SP7. */ 02276 #define BS_AIPS_PACRC_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP7. */ 02277 02278 /*! @brief Read current value of the AIPS_PACRC_SP7 field. */ 02279 #define BR_AIPS_PACRC_SP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP7))) 02280 02281 /*! @brief Format value for bitfield AIPS_PACRC_SP7. */ 02282 #define BF_AIPS_PACRC_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP7) & BM_AIPS_PACRC_SP7) 02283 02284 /*! @brief Set the SP7 field to a new value. */ 02285 #define BW_AIPS_PACRC_SP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP7), v)) 02286 /*@}*/ 02287 02288 /*! 02289 * @name Register AIPS_PACRC, field TP6[4] (RW) 02290 * 02291 * Determines whether the peripheral allows accesses from an untrusted master. 02292 * When this field is set and an access is attempted by an untrusted master, the 02293 * access terminates with an error response and no peripheral access initiates. 02294 * 02295 * Values: 02296 * - 0 - Accesses from an untrusted master are allowed. 02297 * - 1 - Accesses from an untrusted master are not allowed. 02298 */ 02299 /*@{*/ 02300 #define BP_AIPS_PACRC_TP6 (4U) /*!< Bit position for AIPS_PACRC_TP6. */ 02301 #define BM_AIPS_PACRC_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRC_TP6. */ 02302 #define BS_AIPS_PACRC_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP6. */ 02303 02304 /*! @brief Read current value of the AIPS_PACRC_TP6 field. */ 02305 #define BR_AIPS_PACRC_TP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP6))) 02306 02307 /*! @brief Format value for bitfield AIPS_PACRC_TP6. */ 02308 #define BF_AIPS_PACRC_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP6) & BM_AIPS_PACRC_TP6) 02309 02310 /*! @brief Set the TP6 field to a new value. */ 02311 #define BW_AIPS_PACRC_TP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP6), v)) 02312 /*@}*/ 02313 02314 /*! 02315 * @name Register AIPS_PACRC, field WP6[5] (RW) 02316 * 02317 * Determines whether the peripheral allows write accesses. When this field is 02318 * set and a write access is attempted, access terminates with an error response 02319 * and no peripheral access initiates. 02320 * 02321 * Values: 02322 * - 0 - This peripheral allows write accesses. 02323 * - 1 - This peripheral is write protected. 02324 */ 02325 /*@{*/ 02326 #define BP_AIPS_PACRC_WP6 (5U) /*!< Bit position for AIPS_PACRC_WP6. */ 02327 #define BM_AIPS_PACRC_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRC_WP6. */ 02328 #define BS_AIPS_PACRC_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP6. */ 02329 02330 /*! @brief Read current value of the AIPS_PACRC_WP6 field. */ 02331 #define BR_AIPS_PACRC_WP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP6))) 02332 02333 /*! @brief Format value for bitfield AIPS_PACRC_WP6. */ 02334 #define BF_AIPS_PACRC_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP6) & BM_AIPS_PACRC_WP6) 02335 02336 /*! @brief Set the WP6 field to a new value. */ 02337 #define BW_AIPS_PACRC_WP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP6), v)) 02338 /*@}*/ 02339 02340 /*! 02341 * @name Register AIPS_PACRC, field SP6[6] (RW) 02342 * 02343 * Determines whether the peripheral requires supervisor privilege level for 02344 * accesses. When this field is set, the master privilege level must indicate the 02345 * supervisor access attribute, and the MPRx[MPLn] control field for the master 02346 * must be set. If not, access terminates with an error response and no peripheral 02347 * access initiates. 02348 * 02349 * Values: 02350 * - 0 - This peripheral does not require supervisor privilege level for 02351 * accesses. 02352 * - 1 - This peripheral requires supervisor privilege level for accesses. 02353 */ 02354 /*@{*/ 02355 #define BP_AIPS_PACRC_SP6 (6U) /*!< Bit position for AIPS_PACRC_SP6. */ 02356 #define BM_AIPS_PACRC_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRC_SP6. */ 02357 #define BS_AIPS_PACRC_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP6. */ 02358 02359 /*! @brief Read current value of the AIPS_PACRC_SP6 field. */ 02360 #define BR_AIPS_PACRC_SP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP6))) 02361 02362 /*! @brief Format value for bitfield AIPS_PACRC_SP6. */ 02363 #define BF_AIPS_PACRC_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP6) & BM_AIPS_PACRC_SP6) 02364 02365 /*! @brief Set the SP6 field to a new value. */ 02366 #define BW_AIPS_PACRC_SP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP6), v)) 02367 /*@}*/ 02368 02369 /*! 02370 * @name Register AIPS_PACRC, field TP5[8] (RW) 02371 * 02372 * Determines whether the peripheral allows accesses from an untrusted master. 02373 * When this field is set and an access is attempted by an untrusted master, the 02374 * access terminates with an error response and no peripheral access initiates. 02375 * 02376 * Values: 02377 * - 0 - Accesses from an untrusted master are allowed. 02378 * - 1 - Accesses from an untrusted master are not allowed. 02379 */ 02380 /*@{*/ 02381 #define BP_AIPS_PACRC_TP5 (8U) /*!< Bit position for AIPS_PACRC_TP5. */ 02382 #define BM_AIPS_PACRC_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRC_TP5. */ 02383 #define BS_AIPS_PACRC_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP5. */ 02384 02385 /*! @brief Read current value of the AIPS_PACRC_TP5 field. */ 02386 #define BR_AIPS_PACRC_TP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP5))) 02387 02388 /*! @brief Format value for bitfield AIPS_PACRC_TP5. */ 02389 #define BF_AIPS_PACRC_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP5) & BM_AIPS_PACRC_TP5) 02390 02391 /*! @brief Set the TP5 field to a new value. */ 02392 #define BW_AIPS_PACRC_TP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP5), v)) 02393 /*@}*/ 02394 02395 /*! 02396 * @name Register AIPS_PACRC, field WP5[9] (RW) 02397 * 02398 * Determines whether the peripheral allows write accesses. When this field is 02399 * set and a write access is attempted, access terminates with an error response 02400 * and no peripheral access initiates. 02401 * 02402 * Values: 02403 * - 0 - This peripheral allows write accesses. 02404 * - 1 - This peripheral is write protected. 02405 */ 02406 /*@{*/ 02407 #define BP_AIPS_PACRC_WP5 (9U) /*!< Bit position for AIPS_PACRC_WP5. */ 02408 #define BM_AIPS_PACRC_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRC_WP5. */ 02409 #define BS_AIPS_PACRC_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP5. */ 02410 02411 /*! @brief Read current value of the AIPS_PACRC_WP5 field. */ 02412 #define BR_AIPS_PACRC_WP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP5))) 02413 02414 /*! @brief Format value for bitfield AIPS_PACRC_WP5. */ 02415 #define BF_AIPS_PACRC_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP5) & BM_AIPS_PACRC_WP5) 02416 02417 /*! @brief Set the WP5 field to a new value. */ 02418 #define BW_AIPS_PACRC_WP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP5), v)) 02419 /*@}*/ 02420 02421 /*! 02422 * @name Register AIPS_PACRC, field SP5[10] (RW) 02423 * 02424 * Determines whether the peripheral requires supervisor privilege level for 02425 * accesses. When this field is set, the master privilege level must indicate the 02426 * supervisor access attribute, and the MPRx[MPLn] control field for the master 02427 * must be set. If not, access terminates with an error response and no peripheral 02428 * access initiates. 02429 * 02430 * Values: 02431 * - 0 - This peripheral does not require supervisor privilege level for 02432 * accesses. 02433 * - 1 - This peripheral requires supervisor privilege level for accesses. 02434 */ 02435 /*@{*/ 02436 #define BP_AIPS_PACRC_SP5 (10U) /*!< Bit position for AIPS_PACRC_SP5. */ 02437 #define BM_AIPS_PACRC_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRC_SP5. */ 02438 #define BS_AIPS_PACRC_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP5. */ 02439 02440 /*! @brief Read current value of the AIPS_PACRC_SP5 field. */ 02441 #define BR_AIPS_PACRC_SP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP5))) 02442 02443 /*! @brief Format value for bitfield AIPS_PACRC_SP5. */ 02444 #define BF_AIPS_PACRC_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP5) & BM_AIPS_PACRC_SP5) 02445 02446 /*! @brief Set the SP5 field to a new value. */ 02447 #define BW_AIPS_PACRC_SP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP5), v)) 02448 /*@}*/ 02449 02450 /*! 02451 * @name Register AIPS_PACRC, field TP4[12] (RW) 02452 * 02453 * Determines whether the peripheral allows accesses from an untrusted master. 02454 * When this field is set and an access is attempted by an untrusted master, the 02455 * access terminates with an error response and no peripheral access initiates. 02456 * 02457 * Values: 02458 * - 0 - Accesses from an untrusted master are allowed. 02459 * - 1 - Accesses from an untrusted master are not allowed. 02460 */ 02461 /*@{*/ 02462 #define BP_AIPS_PACRC_TP4 (12U) /*!< Bit position for AIPS_PACRC_TP4. */ 02463 #define BM_AIPS_PACRC_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRC_TP4. */ 02464 #define BS_AIPS_PACRC_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP4. */ 02465 02466 /*! @brief Read current value of the AIPS_PACRC_TP4 field. */ 02467 #define BR_AIPS_PACRC_TP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP4))) 02468 02469 /*! @brief Format value for bitfield AIPS_PACRC_TP4. */ 02470 #define BF_AIPS_PACRC_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP4) & BM_AIPS_PACRC_TP4) 02471 02472 /*! @brief Set the TP4 field to a new value. */ 02473 #define BW_AIPS_PACRC_TP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP4), v)) 02474 /*@}*/ 02475 02476 /*! 02477 * @name Register AIPS_PACRC, field WP4[13] (RW) 02478 * 02479 * Determines whether the peripheral allows write accesss. When this bit is set 02480 * and a write access is attempted, access terminates with an error response and 02481 * no peripheral access initiates. 02482 * 02483 * Values: 02484 * - 0 - This peripheral allows write accesses. 02485 * - 1 - This peripheral is write protected. 02486 */ 02487 /*@{*/ 02488 #define BP_AIPS_PACRC_WP4 (13U) /*!< Bit position for AIPS_PACRC_WP4. */ 02489 #define BM_AIPS_PACRC_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRC_WP4. */ 02490 #define BS_AIPS_PACRC_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP4. */ 02491 02492 /*! @brief Read current value of the AIPS_PACRC_WP4 field. */ 02493 #define BR_AIPS_PACRC_WP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP4))) 02494 02495 /*! @brief Format value for bitfield AIPS_PACRC_WP4. */ 02496 #define BF_AIPS_PACRC_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP4) & BM_AIPS_PACRC_WP4) 02497 02498 /*! @brief Set the WP4 field to a new value. */ 02499 #define BW_AIPS_PACRC_WP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP4), v)) 02500 /*@}*/ 02501 02502 /*! 02503 * @name Register AIPS_PACRC, field SP4[14] (RW) 02504 * 02505 * Determines whether the peripheral requires supervisor privilege level for 02506 * accesses. When this field is set, the master privilege level must indicate the 02507 * supervisor access attribute, and the MPRx[MPLn] control field for the master 02508 * must be set. If not, access terminates with an error response and no peripheral 02509 * access initiates. 02510 * 02511 * Values: 02512 * - 0 - This peripheral does not require supervisor privilege level for 02513 * accesses. 02514 * - 1 - This peripheral requires supervisor privilege level for accesses. 02515 */ 02516 /*@{*/ 02517 #define BP_AIPS_PACRC_SP4 (14U) /*!< Bit position for AIPS_PACRC_SP4. */ 02518 #define BM_AIPS_PACRC_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRC_SP4. */ 02519 #define BS_AIPS_PACRC_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP4. */ 02520 02521 /*! @brief Read current value of the AIPS_PACRC_SP4 field. */ 02522 #define BR_AIPS_PACRC_SP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP4))) 02523 02524 /*! @brief Format value for bitfield AIPS_PACRC_SP4. */ 02525 #define BF_AIPS_PACRC_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP4) & BM_AIPS_PACRC_SP4) 02526 02527 /*! @brief Set the SP4 field to a new value. */ 02528 #define BW_AIPS_PACRC_SP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP4), v)) 02529 /*@}*/ 02530 02531 /*! 02532 * @name Register AIPS_PACRC, field TP3[16] (RW) 02533 * 02534 * Determines whether the peripheral allows accesses from an untrusted master. 02535 * When this bit is set and an access is attempted by an untrusted master, the 02536 * access terminates with an error response and no peripheral access initiates. 02537 * 02538 * Values: 02539 * - 0 - Accesses from an untrusted master are allowed. 02540 * - 1 - Accesses from an untrusted master are not allowed. 02541 */ 02542 /*@{*/ 02543 #define BP_AIPS_PACRC_TP3 (16U) /*!< Bit position for AIPS_PACRC_TP3. */ 02544 #define BM_AIPS_PACRC_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRC_TP3. */ 02545 #define BS_AIPS_PACRC_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP3. */ 02546 02547 /*! @brief Read current value of the AIPS_PACRC_TP3 field. */ 02548 #define BR_AIPS_PACRC_TP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP3))) 02549 02550 /*! @brief Format value for bitfield AIPS_PACRC_TP3. */ 02551 #define BF_AIPS_PACRC_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP3) & BM_AIPS_PACRC_TP3) 02552 02553 /*! @brief Set the TP3 field to a new value. */ 02554 #define BW_AIPS_PACRC_TP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP3), v)) 02555 /*@}*/ 02556 02557 /*! 02558 * @name Register AIPS_PACRC, field WP3[17] (RW) 02559 * 02560 * Determines whether the peripheral allows write accesses. When this field is 02561 * set and a write access is attempted, access terminates with an error response 02562 * and no peripheral access initiates. 02563 * 02564 * Values: 02565 * - 0 - This peripheral allows write accesses. 02566 * - 1 - This peripheral is write protected. 02567 */ 02568 /*@{*/ 02569 #define BP_AIPS_PACRC_WP3 (17U) /*!< Bit position for AIPS_PACRC_WP3. */ 02570 #define BM_AIPS_PACRC_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRC_WP3. */ 02571 #define BS_AIPS_PACRC_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP3. */ 02572 02573 /*! @brief Read current value of the AIPS_PACRC_WP3 field. */ 02574 #define BR_AIPS_PACRC_WP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP3))) 02575 02576 /*! @brief Format value for bitfield AIPS_PACRC_WP3. */ 02577 #define BF_AIPS_PACRC_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP3) & BM_AIPS_PACRC_WP3) 02578 02579 /*! @brief Set the WP3 field to a new value. */ 02580 #define BW_AIPS_PACRC_WP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP3), v)) 02581 /*@}*/ 02582 02583 /*! 02584 * @name Register AIPS_PACRC, field SP3[18] (RW) 02585 * 02586 * Determines whether the peripheral requires supervisor privilege level for 02587 * access. When this bit is set, the master privilege level must indicate the 02588 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 02589 * set. If not, access terminates with an error response and no peripheral access 02590 * initiates. 02591 * 02592 * Values: 02593 * - 0 - This peripheral does not require supervisor privilege level for 02594 * accesses. 02595 * - 1 - This peripheral requires supervisor privilege level for accesses. 02596 */ 02597 /*@{*/ 02598 #define BP_AIPS_PACRC_SP3 (18U) /*!< Bit position for AIPS_PACRC_SP3. */ 02599 #define BM_AIPS_PACRC_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRC_SP3. */ 02600 #define BS_AIPS_PACRC_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP3. */ 02601 02602 /*! @brief Read current value of the AIPS_PACRC_SP3 field. */ 02603 #define BR_AIPS_PACRC_SP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP3))) 02604 02605 /*! @brief Format value for bitfield AIPS_PACRC_SP3. */ 02606 #define BF_AIPS_PACRC_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP3) & BM_AIPS_PACRC_SP3) 02607 02608 /*! @brief Set the SP3 field to a new value. */ 02609 #define BW_AIPS_PACRC_SP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP3), v)) 02610 /*@}*/ 02611 02612 /*! 02613 * @name Register AIPS_PACRC, field TP2[20] (RW) 02614 * 02615 * Determines whether the peripheral allows accesses from an untrusted master. 02616 * When this field is set and an access is attempted by an untrusted master, the 02617 * access terminates with an error response and no peripheral access initiates. 02618 * 02619 * Values: 02620 * - 0 - Accesses from an untrusted master are allowed. 02621 * - 1 - Accesses from an untrusted master are not allowed. 02622 */ 02623 /*@{*/ 02624 #define BP_AIPS_PACRC_TP2 (20U) /*!< Bit position for AIPS_PACRC_TP2. */ 02625 #define BM_AIPS_PACRC_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRC_TP2. */ 02626 #define BS_AIPS_PACRC_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP2. */ 02627 02628 /*! @brief Read current value of the AIPS_PACRC_TP2 field. */ 02629 #define BR_AIPS_PACRC_TP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP2))) 02630 02631 /*! @brief Format value for bitfield AIPS_PACRC_TP2. */ 02632 #define BF_AIPS_PACRC_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP2) & BM_AIPS_PACRC_TP2) 02633 02634 /*! @brief Set the TP2 field to a new value. */ 02635 #define BW_AIPS_PACRC_TP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP2), v)) 02636 /*@}*/ 02637 02638 /*! 02639 * @name Register AIPS_PACRC, field WP2[21] (RW) 02640 * 02641 * Determines whether the peripheral allows write accesss. When this bit is set 02642 * and a write access is attempted, access terminates with an error response and 02643 * no peripheral access initiates. 02644 * 02645 * Values: 02646 * - 0 - This peripheral allows write accesses. 02647 * - 1 - This peripheral is write protected. 02648 */ 02649 /*@{*/ 02650 #define BP_AIPS_PACRC_WP2 (21U) /*!< Bit position for AIPS_PACRC_WP2. */ 02651 #define BM_AIPS_PACRC_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRC_WP2. */ 02652 #define BS_AIPS_PACRC_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP2. */ 02653 02654 /*! @brief Read current value of the AIPS_PACRC_WP2 field. */ 02655 #define BR_AIPS_PACRC_WP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP2))) 02656 02657 /*! @brief Format value for bitfield AIPS_PACRC_WP2. */ 02658 #define BF_AIPS_PACRC_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP2) & BM_AIPS_PACRC_WP2) 02659 02660 /*! @brief Set the WP2 field to a new value. */ 02661 #define BW_AIPS_PACRC_WP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP2), v)) 02662 /*@}*/ 02663 02664 /*! 02665 * @name Register AIPS_PACRC, field SP2[22] (RW) 02666 * 02667 * Determines whether the peripheral requires supervisor privilege level for 02668 * accesses. When this field is set, the master privilege level must indicate the 02669 * supervisor access attribute, and the MPRx[MPLn] control field for the master 02670 * must be set. If not, access terminates with an error response and no peripheral 02671 * access initiates. 02672 * 02673 * Values: 02674 * - 0 - This peripheral does not require supervisor privilege level for 02675 * accesses. 02676 * - 1 - This peripheral requires supervisor privilege level for accesses. 02677 */ 02678 /*@{*/ 02679 #define BP_AIPS_PACRC_SP2 (22U) /*!< Bit position for AIPS_PACRC_SP2. */ 02680 #define BM_AIPS_PACRC_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRC_SP2. */ 02681 #define BS_AIPS_PACRC_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP2. */ 02682 02683 /*! @brief Read current value of the AIPS_PACRC_SP2 field. */ 02684 #define BR_AIPS_PACRC_SP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP2))) 02685 02686 /*! @brief Format value for bitfield AIPS_PACRC_SP2. */ 02687 #define BF_AIPS_PACRC_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP2) & BM_AIPS_PACRC_SP2) 02688 02689 /*! @brief Set the SP2 field to a new value. */ 02690 #define BW_AIPS_PACRC_SP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP2), v)) 02691 /*@}*/ 02692 02693 /*! 02694 * @name Register AIPS_PACRC, field TP1[24] (RW) 02695 * 02696 * Determines whether the peripheral allows accesses from an untrusted master. 02697 * When this bit is set and an access is attempted by an untrusted master, the 02698 * access terminates with an error response and no peripheral access initiates. 02699 * 02700 * Values: 02701 * - 0 - Accesses from an untrusted master are allowed. 02702 * - 1 - Accesses from an untrusted master are not allowed. 02703 */ 02704 /*@{*/ 02705 #define BP_AIPS_PACRC_TP1 (24U) /*!< Bit position for AIPS_PACRC_TP1. */ 02706 #define BM_AIPS_PACRC_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRC_TP1. */ 02707 #define BS_AIPS_PACRC_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP1. */ 02708 02709 /*! @brief Read current value of the AIPS_PACRC_TP1 field. */ 02710 #define BR_AIPS_PACRC_TP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP1))) 02711 02712 /*! @brief Format value for bitfield AIPS_PACRC_TP1. */ 02713 #define BF_AIPS_PACRC_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP1) & BM_AIPS_PACRC_TP1) 02714 02715 /*! @brief Set the TP1 field to a new value. */ 02716 #define BW_AIPS_PACRC_TP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP1), v)) 02717 /*@}*/ 02718 02719 /*! 02720 * @name Register AIPS_PACRC, field WP1[25] (RW) 02721 * 02722 * Determines whether the peripheral allows write accesses. When this field is 02723 * set and a write access is attempted, access terminates with an error response 02724 * and no peripheral access initiates. 02725 * 02726 * Values: 02727 * - 0 - This peripheral allows write accesses. 02728 * - 1 - This peripheral is write protected. 02729 */ 02730 /*@{*/ 02731 #define BP_AIPS_PACRC_WP1 (25U) /*!< Bit position for AIPS_PACRC_WP1. */ 02732 #define BM_AIPS_PACRC_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRC_WP1. */ 02733 #define BS_AIPS_PACRC_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP1. */ 02734 02735 /*! @brief Read current value of the AIPS_PACRC_WP1 field. */ 02736 #define BR_AIPS_PACRC_WP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP1))) 02737 02738 /*! @brief Format value for bitfield AIPS_PACRC_WP1. */ 02739 #define BF_AIPS_PACRC_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP1) & BM_AIPS_PACRC_WP1) 02740 02741 /*! @brief Set the WP1 field to a new value. */ 02742 #define BW_AIPS_PACRC_WP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP1), v)) 02743 /*@}*/ 02744 02745 /*! 02746 * @name Register AIPS_PACRC, field SP1[26] (RW) 02747 * 02748 * Determines whether the peripheral requires supervisor privilege level for 02749 * accesses. When this field is set, the master privilege level must indicate the 02750 * supervisor access attribute, and the MPRx[MPLn] control field for the master 02751 * must be set. If not, access terminates with an error response and no peripheral 02752 * access initiates. 02753 * 02754 * Values: 02755 * - 0 - This peripheral does not require supervisor privilege level for 02756 * accesses. 02757 * - 1 - This peripheral requires supervisor privilege level for accesses. 02758 */ 02759 /*@{*/ 02760 #define BP_AIPS_PACRC_SP1 (26U) /*!< Bit position for AIPS_PACRC_SP1. */ 02761 #define BM_AIPS_PACRC_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRC_SP1. */ 02762 #define BS_AIPS_PACRC_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP1. */ 02763 02764 /*! @brief Read current value of the AIPS_PACRC_SP1 field. */ 02765 #define BR_AIPS_PACRC_SP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP1))) 02766 02767 /*! @brief Format value for bitfield AIPS_PACRC_SP1. */ 02768 #define BF_AIPS_PACRC_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP1) & BM_AIPS_PACRC_SP1) 02769 02770 /*! @brief Set the SP1 field to a new value. */ 02771 #define BW_AIPS_PACRC_SP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP1), v)) 02772 /*@}*/ 02773 02774 /*! 02775 * @name Register AIPS_PACRC, field TP0[28] (RW) 02776 * 02777 * Determines whether the peripheral allows accesses from an untrusted master. 02778 * When this field is set and an access is attempted by an untrusted master, the 02779 * access terminates with an error response and no peripheral access initiates. 02780 * 02781 * Values: 02782 * - 0 - Accesses from an untrusted master are allowed. 02783 * - 1 - Accesses from an untrusted master are not allowed. 02784 */ 02785 /*@{*/ 02786 #define BP_AIPS_PACRC_TP0 (28U) /*!< Bit position for AIPS_PACRC_TP0. */ 02787 #define BM_AIPS_PACRC_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRC_TP0. */ 02788 #define BS_AIPS_PACRC_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRC_TP0. */ 02789 02790 /*! @brief Read current value of the AIPS_PACRC_TP0 field. */ 02791 #define BR_AIPS_PACRC_TP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP0))) 02792 02793 /*! @brief Format value for bitfield AIPS_PACRC_TP0. */ 02794 #define BF_AIPS_PACRC_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_TP0) & BM_AIPS_PACRC_TP0) 02795 02796 /*! @brief Set the TP0 field to a new value. */ 02797 #define BW_AIPS_PACRC_TP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_TP0), v)) 02798 /*@}*/ 02799 02800 /*! 02801 * @name Register AIPS_PACRC, field WP0[29] (RW) 02802 * 02803 * Determines whether the peripheral allows write accesss. When this bit is set 02804 * and a write access is attempted, access terminates with an error response and 02805 * no peripheral access initiates. 02806 * 02807 * Values: 02808 * - 0 - This peripheral allows write accesses. 02809 * - 1 - This peripheral is write protected. 02810 */ 02811 /*@{*/ 02812 #define BP_AIPS_PACRC_WP0 (29U) /*!< Bit position for AIPS_PACRC_WP0. */ 02813 #define BM_AIPS_PACRC_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRC_WP0. */ 02814 #define BS_AIPS_PACRC_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRC_WP0. */ 02815 02816 /*! @brief Read current value of the AIPS_PACRC_WP0 field. */ 02817 #define BR_AIPS_PACRC_WP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP0))) 02818 02819 /*! @brief Format value for bitfield AIPS_PACRC_WP0. */ 02820 #define BF_AIPS_PACRC_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_WP0) & BM_AIPS_PACRC_WP0) 02821 02822 /*! @brief Set the WP0 field to a new value. */ 02823 #define BW_AIPS_PACRC_WP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_WP0), v)) 02824 /*@}*/ 02825 02826 /*! 02827 * @name Register AIPS_PACRC, field SP0[30] (RW) 02828 * 02829 * Determines whether the peripheral requires supervisor privilege level for 02830 * accesses. When this field is set, the master privilege level must indicate the 02831 * supervisor access attribute, and the MPRx[MPLn] control field for the master 02832 * must be set. If not, access terminates with an error response and no peripheral 02833 * access initiates. 02834 * 02835 * Values: 02836 * - 0 - This peripheral does not require supervisor privilege level for 02837 * accesses. 02838 * - 1 - This peripheral requires supervisor privilege level for accesses. 02839 */ 02840 /*@{*/ 02841 #define BP_AIPS_PACRC_SP0 (30U) /*!< Bit position for AIPS_PACRC_SP0. */ 02842 #define BM_AIPS_PACRC_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRC_SP0. */ 02843 #define BS_AIPS_PACRC_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRC_SP0. */ 02844 02845 /*! @brief Read current value of the AIPS_PACRC_SP0 field. */ 02846 #define BR_AIPS_PACRC_SP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP0))) 02847 02848 /*! @brief Format value for bitfield AIPS_PACRC_SP0. */ 02849 #define BF_AIPS_PACRC_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRC_SP0) & BM_AIPS_PACRC_SP0) 02850 02851 /*! @brief Set the SP0 field to a new value. */ 02852 #define BW_AIPS_PACRC_SP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRC_ADDR(x), BP_AIPS_PACRC_SP0), v)) 02853 /*@}*/ 02854 02855 /******************************************************************************* 02856 * HW_AIPS_PACRD - Peripheral Access Control Register 02857 ******************************************************************************/ 02858 02859 /*! 02860 * @brief HW_AIPS_PACRD - Peripheral Access Control Register (RW) 02861 * 02862 * Reset value: 0x00000004U 02863 * 02864 * Each PACR register consists of eight 4-bit PACR fields. Each PACR field 02865 * defines the access levels for a particular peripheral. The mapping between a 02866 * peripheral and its PACR field is shown in the table below. The peripheral assignment 02867 * to each PACR is defined by the memory map slot that the peripheral is 02868 * assigned to. See this chip's memory map for the assignment of a particular 02869 * peripheral. The following table shows the location of each peripheral slot's PACR field 02870 * in the PACR registers. Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] 02871 * [11:8] [7:4] [3:0] 0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7 02872 * 0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15 0x28 PACRC 02873 * PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23 0x2C PACRD PACR24 02874 * PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31 0x30 Reserved 0x34 Reserved 0x38 02875 * Reserved 0x3C Reserved 0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 02876 * PACR38 PACR39 0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47 02877 * 0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55 0x4C PACRH 02878 * PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63 0x50 PACRI PACR64 02879 * PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71 0x54 PACRJ PACR72 PACR73 PACR74 02880 * PACR75 PACR76 PACR77 PACR78 PACR79 0x58 PACRK PACR80 PACR81 PACR82 PACR83 02881 * PACR84 PACR85 PACR86 PACR87 0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93 02882 * PACR94 PACR95 0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 02883 * PACR103 0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 02884 * PACR111 0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119 02885 * 0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127 0x80 02886 * PACRU PACR GBL0 PACR GBL1 Reserved The register field descriptions for PACR 02887 * A-D, which control peripheral slots 0-31, are shown below. The following 02888 * section, PACRPeripheral Access Control Register , shows the register field 02889 * descriptions for PACR E-P. All PACR registers are identical. They are divided into two 02890 * sections because they occupy two non-contiguous address spaces. 02891 */ 02892 typedef union _hw_aips_pacrd 02893 { 02894 uint32_t U; 02895 struct _hw_aips_pacrd_bitfields 02896 { 02897 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 02898 uint32_t WP7 : 1; /*!< [1] Write Protect */ 02899 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 02900 uint32_t RESERVED0 : 1; /*!< [3] */ 02901 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 02902 uint32_t WP6 : 1; /*!< [5] Write Protect */ 02903 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 02904 uint32_t RESERVED1 : 1; /*!< [7] */ 02905 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 02906 uint32_t WP5 : 1; /*!< [9] Write Protect */ 02907 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 02908 uint32_t RESERVED2 : 1; /*!< [11] */ 02909 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 02910 uint32_t WP4 : 1; /*!< [13] Write Protect */ 02911 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 02912 uint32_t RESERVED3 : 1; /*!< [15] */ 02913 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 02914 uint32_t WP3 : 1; /*!< [17] Write Protect */ 02915 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 02916 uint32_t RESERVED4 : 1; /*!< [19] */ 02917 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 02918 uint32_t WP2 : 1; /*!< [21] Write Protect */ 02919 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 02920 uint32_t RESERVED5 : 1; /*!< [23] */ 02921 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 02922 uint32_t WP1 : 1; /*!< [25] Write Protect */ 02923 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 02924 uint32_t RESERVED6 : 1; /*!< [27] */ 02925 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 02926 uint32_t WP0 : 1; /*!< [29] Write Protect */ 02927 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 02928 uint32_t RESERVED7 : 1; /*!< [31] */ 02929 } B; 02930 } hw_aips_pacrd_t; 02931 02932 /*! 02933 * @name Constants and macros for entire AIPS_PACRD register 02934 */ 02935 /*@{*/ 02936 #define HW_AIPS_PACRD_ADDR(x) ((x) + 0x2CU) 02937 02938 #define HW_AIPS_PACRD(x) (*(__IO hw_aips_pacrd_t *) HW_AIPS_PACRD_ADDR(x)) 02939 #define HW_AIPS_PACRD_RD(x) (ADDRESS_READ(hw_aips_pacrd_t, HW_AIPS_PACRD_ADDR(x))) 02940 #define HW_AIPS_PACRD_WR(x, v) (ADDRESS_WRITE(hw_aips_pacrd_t, HW_AIPS_PACRD_ADDR(x), v)) 02941 #define HW_AIPS_PACRD_SET(x, v) (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) | (v))) 02942 #define HW_AIPS_PACRD_CLR(x, v) (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) & ~(v))) 02943 #define HW_AIPS_PACRD_TOG(x, v) (HW_AIPS_PACRD_WR(x, HW_AIPS_PACRD_RD(x) ^ (v))) 02944 /*@}*/ 02945 02946 /* 02947 * Constants & macros for individual AIPS_PACRD bitfields 02948 */ 02949 02950 /*! 02951 * @name Register AIPS_PACRD, field TP7[0] (RW) 02952 * 02953 * Determines whether the peripheral allows accesses from an untrusted master. 02954 * When this field is set and an access is attempted by an untrusted master, the 02955 * access terminates with an error response and no peripheral access initiates. 02956 * 02957 * Values: 02958 * - 0 - Accesses from an untrusted master are allowed. 02959 * - 1 - Accesses from an untrusted master are not allowed. 02960 */ 02961 /*@{*/ 02962 #define BP_AIPS_PACRD_TP7 (0U) /*!< Bit position for AIPS_PACRD_TP7. */ 02963 #define BM_AIPS_PACRD_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRD_TP7. */ 02964 #define BS_AIPS_PACRD_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP7. */ 02965 02966 /*! @brief Read current value of the AIPS_PACRD_TP7 field. */ 02967 #define BR_AIPS_PACRD_TP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP7))) 02968 02969 /*! @brief Format value for bitfield AIPS_PACRD_TP7. */ 02970 #define BF_AIPS_PACRD_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP7) & BM_AIPS_PACRD_TP7) 02971 02972 /*! @brief Set the TP7 field to a new value. */ 02973 #define BW_AIPS_PACRD_TP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP7), v)) 02974 /*@}*/ 02975 02976 /*! 02977 * @name Register AIPS_PACRD, field WP7[1] (RW) 02978 * 02979 * Determines whether the peripheral allows write accesses. When this field is 02980 * set and a write access is attempted, access terminates with an error response 02981 * and no peripheral access initiates. 02982 * 02983 * Values: 02984 * - 0 - This peripheral allows write accesses. 02985 * - 1 - This peripheral is write protected. 02986 */ 02987 /*@{*/ 02988 #define BP_AIPS_PACRD_WP7 (1U) /*!< Bit position for AIPS_PACRD_WP7. */ 02989 #define BM_AIPS_PACRD_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRD_WP7. */ 02990 #define BS_AIPS_PACRD_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP7. */ 02991 02992 /*! @brief Read current value of the AIPS_PACRD_WP7 field. */ 02993 #define BR_AIPS_PACRD_WP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP7))) 02994 02995 /*! @brief Format value for bitfield AIPS_PACRD_WP7. */ 02996 #define BF_AIPS_PACRD_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP7) & BM_AIPS_PACRD_WP7) 02997 02998 /*! @brief Set the WP7 field to a new value. */ 02999 #define BW_AIPS_PACRD_WP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP7), v)) 03000 /*@}*/ 03001 03002 /*! 03003 * @name Register AIPS_PACRD, field SP7[2] (RW) 03004 * 03005 * Determines whether the peripheral requires supervisor privilege level for 03006 * accesses. When this field is set, the master privilege level must indicate the 03007 * supervisor access attribute, and the MPRx[MPLn] control field for the master 03008 * must be set. If not, access terminates with an error response and no peripheral 03009 * access initiates. 03010 * 03011 * Values: 03012 * - 0 - This peripheral does not require supervisor privilege level for 03013 * accesses. 03014 * - 1 - This peripheral requires supervisor privilege level for accesses. 03015 */ 03016 /*@{*/ 03017 #define BP_AIPS_PACRD_SP7 (2U) /*!< Bit position for AIPS_PACRD_SP7. */ 03018 #define BM_AIPS_PACRD_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRD_SP7. */ 03019 #define BS_AIPS_PACRD_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP7. */ 03020 03021 /*! @brief Read current value of the AIPS_PACRD_SP7 field. */ 03022 #define BR_AIPS_PACRD_SP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP7))) 03023 03024 /*! @brief Format value for bitfield AIPS_PACRD_SP7. */ 03025 #define BF_AIPS_PACRD_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP7) & BM_AIPS_PACRD_SP7) 03026 03027 /*! @brief Set the SP7 field to a new value. */ 03028 #define BW_AIPS_PACRD_SP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP7), v)) 03029 /*@}*/ 03030 03031 /*! 03032 * @name Register AIPS_PACRD, field TP6[4] (RW) 03033 * 03034 * Determines whether the peripheral allows accesses from an untrusted master. 03035 * When this field is set and an access is attempted by an untrusted master, the 03036 * access terminates with an error response and no peripheral access initiates. 03037 * 03038 * Values: 03039 * - 0 - Accesses from an untrusted master are allowed. 03040 * - 1 - Accesses from an untrusted master are not allowed. 03041 */ 03042 /*@{*/ 03043 #define BP_AIPS_PACRD_TP6 (4U) /*!< Bit position for AIPS_PACRD_TP6. */ 03044 #define BM_AIPS_PACRD_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRD_TP6. */ 03045 #define BS_AIPS_PACRD_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP6. */ 03046 03047 /*! @brief Read current value of the AIPS_PACRD_TP6 field. */ 03048 #define BR_AIPS_PACRD_TP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP6))) 03049 03050 /*! @brief Format value for bitfield AIPS_PACRD_TP6. */ 03051 #define BF_AIPS_PACRD_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP6) & BM_AIPS_PACRD_TP6) 03052 03053 /*! @brief Set the TP6 field to a new value. */ 03054 #define BW_AIPS_PACRD_TP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP6), v)) 03055 /*@}*/ 03056 03057 /*! 03058 * @name Register AIPS_PACRD, field WP6[5] (RW) 03059 * 03060 * Determines whether the peripheral allows write accesses. When this field is 03061 * set and a write access is attempted, access terminates with an error response 03062 * and no peripheral access initiates. 03063 * 03064 * Values: 03065 * - 0 - This peripheral allows write accesses. 03066 * - 1 - This peripheral is write protected. 03067 */ 03068 /*@{*/ 03069 #define BP_AIPS_PACRD_WP6 (5U) /*!< Bit position for AIPS_PACRD_WP6. */ 03070 #define BM_AIPS_PACRD_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRD_WP6. */ 03071 #define BS_AIPS_PACRD_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP6. */ 03072 03073 /*! @brief Read current value of the AIPS_PACRD_WP6 field. */ 03074 #define BR_AIPS_PACRD_WP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP6))) 03075 03076 /*! @brief Format value for bitfield AIPS_PACRD_WP6. */ 03077 #define BF_AIPS_PACRD_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP6) & BM_AIPS_PACRD_WP6) 03078 03079 /*! @brief Set the WP6 field to a new value. */ 03080 #define BW_AIPS_PACRD_WP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP6), v)) 03081 /*@}*/ 03082 03083 /*! 03084 * @name Register AIPS_PACRD, field SP6[6] (RW) 03085 * 03086 * Determines whether the peripheral requires supervisor privilege level for 03087 * accesses. When this field is set, the master privilege level must indicate the 03088 * supervisor access attribute, and the MPRx[MPLn] control field for the master 03089 * must be set. If not, access terminates with an error response and no peripheral 03090 * access initiates. 03091 * 03092 * Values: 03093 * - 0 - This peripheral does not require supervisor privilege level for 03094 * accesses. 03095 * - 1 - This peripheral requires supervisor privilege level for accesses. 03096 */ 03097 /*@{*/ 03098 #define BP_AIPS_PACRD_SP6 (6U) /*!< Bit position for AIPS_PACRD_SP6. */ 03099 #define BM_AIPS_PACRD_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRD_SP6. */ 03100 #define BS_AIPS_PACRD_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP6. */ 03101 03102 /*! @brief Read current value of the AIPS_PACRD_SP6 field. */ 03103 #define BR_AIPS_PACRD_SP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP6))) 03104 03105 /*! @brief Format value for bitfield AIPS_PACRD_SP6. */ 03106 #define BF_AIPS_PACRD_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP6) & BM_AIPS_PACRD_SP6) 03107 03108 /*! @brief Set the SP6 field to a new value. */ 03109 #define BW_AIPS_PACRD_SP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP6), v)) 03110 /*@}*/ 03111 03112 /*! 03113 * @name Register AIPS_PACRD, field TP5[8] (RW) 03114 * 03115 * Determines whether the peripheral allows accesses from an untrusted master. 03116 * When this field is set and an access is attempted by an untrusted master, the 03117 * access terminates with an error response and no peripheral access initiates. 03118 * 03119 * Values: 03120 * - 0 - Accesses from an untrusted master are allowed. 03121 * - 1 - Accesses from an untrusted master are not allowed. 03122 */ 03123 /*@{*/ 03124 #define BP_AIPS_PACRD_TP5 (8U) /*!< Bit position for AIPS_PACRD_TP5. */ 03125 #define BM_AIPS_PACRD_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRD_TP5. */ 03126 #define BS_AIPS_PACRD_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP5. */ 03127 03128 /*! @brief Read current value of the AIPS_PACRD_TP5 field. */ 03129 #define BR_AIPS_PACRD_TP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP5))) 03130 03131 /*! @brief Format value for bitfield AIPS_PACRD_TP5. */ 03132 #define BF_AIPS_PACRD_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP5) & BM_AIPS_PACRD_TP5) 03133 03134 /*! @brief Set the TP5 field to a new value. */ 03135 #define BW_AIPS_PACRD_TP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP5), v)) 03136 /*@}*/ 03137 03138 /*! 03139 * @name Register AIPS_PACRD, field WP5[9] (RW) 03140 * 03141 * Determines whether the peripheral allows write accesses. When this field is 03142 * set and a write access is attempted, access terminates with an error response 03143 * and no peripheral access initiates. 03144 * 03145 * Values: 03146 * - 0 - This peripheral allows write accesses. 03147 * - 1 - This peripheral is write protected. 03148 */ 03149 /*@{*/ 03150 #define BP_AIPS_PACRD_WP5 (9U) /*!< Bit position for AIPS_PACRD_WP5. */ 03151 #define BM_AIPS_PACRD_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRD_WP5. */ 03152 #define BS_AIPS_PACRD_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP5. */ 03153 03154 /*! @brief Read current value of the AIPS_PACRD_WP5 field. */ 03155 #define BR_AIPS_PACRD_WP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP5))) 03156 03157 /*! @brief Format value for bitfield AIPS_PACRD_WP5. */ 03158 #define BF_AIPS_PACRD_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP5) & BM_AIPS_PACRD_WP5) 03159 03160 /*! @brief Set the WP5 field to a new value. */ 03161 #define BW_AIPS_PACRD_WP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP5), v)) 03162 /*@}*/ 03163 03164 /*! 03165 * @name Register AIPS_PACRD, field SP5[10] (RW) 03166 * 03167 * Determines whether the peripheral requires supervisor privilege level for 03168 * accesses. When this field is set, the master privilege level must indicate the 03169 * supervisor access attribute, and the MPRx[MPLn] control field for the master 03170 * must be set. If not, access terminates with an error response and no peripheral 03171 * access initiates. 03172 * 03173 * Values: 03174 * - 0 - This peripheral does not require supervisor privilege level for 03175 * accesses. 03176 * - 1 - This peripheral requires supervisor privilege level for accesses. 03177 */ 03178 /*@{*/ 03179 #define BP_AIPS_PACRD_SP5 (10U) /*!< Bit position for AIPS_PACRD_SP5. */ 03180 #define BM_AIPS_PACRD_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRD_SP5. */ 03181 #define BS_AIPS_PACRD_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP5. */ 03182 03183 /*! @brief Read current value of the AIPS_PACRD_SP5 field. */ 03184 #define BR_AIPS_PACRD_SP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP5))) 03185 03186 /*! @brief Format value for bitfield AIPS_PACRD_SP5. */ 03187 #define BF_AIPS_PACRD_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP5) & BM_AIPS_PACRD_SP5) 03188 03189 /*! @brief Set the SP5 field to a new value. */ 03190 #define BW_AIPS_PACRD_SP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP5), v)) 03191 /*@}*/ 03192 03193 /*! 03194 * @name Register AIPS_PACRD, field TP4[12] (RW) 03195 * 03196 * Determines whether the peripheral allows accesses from an untrusted master. 03197 * When this field is set and an access is attempted by an untrusted master, the 03198 * access terminates with an error response and no peripheral access initiates. 03199 * 03200 * Values: 03201 * - 0 - Accesses from an untrusted master are allowed. 03202 * - 1 - Accesses from an untrusted master are not allowed. 03203 */ 03204 /*@{*/ 03205 #define BP_AIPS_PACRD_TP4 (12U) /*!< Bit position for AIPS_PACRD_TP4. */ 03206 #define BM_AIPS_PACRD_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRD_TP4. */ 03207 #define BS_AIPS_PACRD_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP4. */ 03208 03209 /*! @brief Read current value of the AIPS_PACRD_TP4 field. */ 03210 #define BR_AIPS_PACRD_TP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP4))) 03211 03212 /*! @brief Format value for bitfield AIPS_PACRD_TP4. */ 03213 #define BF_AIPS_PACRD_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP4) & BM_AIPS_PACRD_TP4) 03214 03215 /*! @brief Set the TP4 field to a new value. */ 03216 #define BW_AIPS_PACRD_TP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP4), v)) 03217 /*@}*/ 03218 03219 /*! 03220 * @name Register AIPS_PACRD, field WP4[13] (RW) 03221 * 03222 * Determines whether the peripheral allows write accesss. When this bit is set 03223 * and a write access is attempted, access terminates with an error response and 03224 * no peripheral access initiates. 03225 * 03226 * Values: 03227 * - 0 - This peripheral allows write accesses. 03228 * - 1 - This peripheral is write protected. 03229 */ 03230 /*@{*/ 03231 #define BP_AIPS_PACRD_WP4 (13U) /*!< Bit position for AIPS_PACRD_WP4. */ 03232 #define BM_AIPS_PACRD_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRD_WP4. */ 03233 #define BS_AIPS_PACRD_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP4. */ 03234 03235 /*! @brief Read current value of the AIPS_PACRD_WP4 field. */ 03236 #define BR_AIPS_PACRD_WP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP4))) 03237 03238 /*! @brief Format value for bitfield AIPS_PACRD_WP4. */ 03239 #define BF_AIPS_PACRD_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP4) & BM_AIPS_PACRD_WP4) 03240 03241 /*! @brief Set the WP4 field to a new value. */ 03242 #define BW_AIPS_PACRD_WP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP4), v)) 03243 /*@}*/ 03244 03245 /*! 03246 * @name Register AIPS_PACRD, field SP4[14] (RW) 03247 * 03248 * Determines whether the peripheral requires supervisor privilege level for 03249 * accesses. When this field is set, the master privilege level must indicate the 03250 * supervisor access attribute, and the MPRx[MPLn] control field for the master 03251 * must be set. If not, access terminates with an error response and no peripheral 03252 * access initiates. 03253 * 03254 * Values: 03255 * - 0 - This peripheral does not require supervisor privilege level for 03256 * accesses. 03257 * - 1 - This peripheral requires supervisor privilege level for accesses. 03258 */ 03259 /*@{*/ 03260 #define BP_AIPS_PACRD_SP4 (14U) /*!< Bit position for AIPS_PACRD_SP4. */ 03261 #define BM_AIPS_PACRD_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRD_SP4. */ 03262 #define BS_AIPS_PACRD_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP4. */ 03263 03264 /*! @brief Read current value of the AIPS_PACRD_SP4 field. */ 03265 #define BR_AIPS_PACRD_SP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP4))) 03266 03267 /*! @brief Format value for bitfield AIPS_PACRD_SP4. */ 03268 #define BF_AIPS_PACRD_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP4) & BM_AIPS_PACRD_SP4) 03269 03270 /*! @brief Set the SP4 field to a new value. */ 03271 #define BW_AIPS_PACRD_SP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP4), v)) 03272 /*@}*/ 03273 03274 /*! 03275 * @name Register AIPS_PACRD, field TP3[16] (RW) 03276 * 03277 * Determines whether the peripheral allows accesses from an untrusted master. 03278 * When this bit is set and an access is attempted by an untrusted master, the 03279 * access terminates with an error response and no peripheral access initiates. 03280 * 03281 * Values: 03282 * - 0 - Accesses from an untrusted master are allowed. 03283 * - 1 - Accesses from an untrusted master are not allowed. 03284 */ 03285 /*@{*/ 03286 #define BP_AIPS_PACRD_TP3 (16U) /*!< Bit position for AIPS_PACRD_TP3. */ 03287 #define BM_AIPS_PACRD_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRD_TP3. */ 03288 #define BS_AIPS_PACRD_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP3. */ 03289 03290 /*! @brief Read current value of the AIPS_PACRD_TP3 field. */ 03291 #define BR_AIPS_PACRD_TP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP3))) 03292 03293 /*! @brief Format value for bitfield AIPS_PACRD_TP3. */ 03294 #define BF_AIPS_PACRD_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP3) & BM_AIPS_PACRD_TP3) 03295 03296 /*! @brief Set the TP3 field to a new value. */ 03297 #define BW_AIPS_PACRD_TP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP3), v)) 03298 /*@}*/ 03299 03300 /*! 03301 * @name Register AIPS_PACRD, field WP3[17] (RW) 03302 * 03303 * Determines whether the peripheral allows write accesses. When this field is 03304 * set and a write access is attempted, access terminates with an error response 03305 * and no peripheral access initiates. 03306 * 03307 * Values: 03308 * - 0 - This peripheral allows write accesses. 03309 * - 1 - This peripheral is write protected. 03310 */ 03311 /*@{*/ 03312 #define BP_AIPS_PACRD_WP3 (17U) /*!< Bit position for AIPS_PACRD_WP3. */ 03313 #define BM_AIPS_PACRD_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRD_WP3. */ 03314 #define BS_AIPS_PACRD_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP3. */ 03315 03316 /*! @brief Read current value of the AIPS_PACRD_WP3 field. */ 03317 #define BR_AIPS_PACRD_WP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP3))) 03318 03319 /*! @brief Format value for bitfield AIPS_PACRD_WP3. */ 03320 #define BF_AIPS_PACRD_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP3) & BM_AIPS_PACRD_WP3) 03321 03322 /*! @brief Set the WP3 field to a new value. */ 03323 #define BW_AIPS_PACRD_WP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP3), v)) 03324 /*@}*/ 03325 03326 /*! 03327 * @name Register AIPS_PACRD, field SP3[18] (RW) 03328 * 03329 * Determines whether the peripheral requires supervisor privilege level for 03330 * access. When this bit is set, the master privilege level must indicate the 03331 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 03332 * set. If not, access terminates with an error response and no peripheral access 03333 * initiates. 03334 * 03335 * Values: 03336 * - 0 - This peripheral does not require supervisor privilege level for 03337 * accesses. 03338 * - 1 - This peripheral requires supervisor privilege level for accesses. 03339 */ 03340 /*@{*/ 03341 #define BP_AIPS_PACRD_SP3 (18U) /*!< Bit position for AIPS_PACRD_SP3. */ 03342 #define BM_AIPS_PACRD_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRD_SP3. */ 03343 #define BS_AIPS_PACRD_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP3. */ 03344 03345 /*! @brief Read current value of the AIPS_PACRD_SP3 field. */ 03346 #define BR_AIPS_PACRD_SP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP3))) 03347 03348 /*! @brief Format value for bitfield AIPS_PACRD_SP3. */ 03349 #define BF_AIPS_PACRD_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP3) & BM_AIPS_PACRD_SP3) 03350 03351 /*! @brief Set the SP3 field to a new value. */ 03352 #define BW_AIPS_PACRD_SP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP3), v)) 03353 /*@}*/ 03354 03355 /*! 03356 * @name Register AIPS_PACRD, field TP2[20] (RW) 03357 * 03358 * Determines whether the peripheral allows accesses from an untrusted master. 03359 * When this field is set and an access is attempted by an untrusted master, the 03360 * access terminates with an error response and no peripheral access initiates. 03361 * 03362 * Values: 03363 * - 0 - Accesses from an untrusted master are allowed. 03364 * - 1 - Accesses from an untrusted master are not allowed. 03365 */ 03366 /*@{*/ 03367 #define BP_AIPS_PACRD_TP2 (20U) /*!< Bit position for AIPS_PACRD_TP2. */ 03368 #define BM_AIPS_PACRD_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRD_TP2. */ 03369 #define BS_AIPS_PACRD_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP2. */ 03370 03371 /*! @brief Read current value of the AIPS_PACRD_TP2 field. */ 03372 #define BR_AIPS_PACRD_TP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP2))) 03373 03374 /*! @brief Format value for bitfield AIPS_PACRD_TP2. */ 03375 #define BF_AIPS_PACRD_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP2) & BM_AIPS_PACRD_TP2) 03376 03377 /*! @brief Set the TP2 field to a new value. */ 03378 #define BW_AIPS_PACRD_TP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP2), v)) 03379 /*@}*/ 03380 03381 /*! 03382 * @name Register AIPS_PACRD, field WP2[21] (RW) 03383 * 03384 * Determines whether the peripheral allows write accesss. When this bit is set 03385 * and a write access is attempted, access terminates with an error response and 03386 * no peripheral access initiates. 03387 * 03388 * Values: 03389 * - 0 - This peripheral allows write accesses. 03390 * - 1 - This peripheral is write protected. 03391 */ 03392 /*@{*/ 03393 #define BP_AIPS_PACRD_WP2 (21U) /*!< Bit position for AIPS_PACRD_WP2. */ 03394 #define BM_AIPS_PACRD_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRD_WP2. */ 03395 #define BS_AIPS_PACRD_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP2. */ 03396 03397 /*! @brief Read current value of the AIPS_PACRD_WP2 field. */ 03398 #define BR_AIPS_PACRD_WP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP2))) 03399 03400 /*! @brief Format value for bitfield AIPS_PACRD_WP2. */ 03401 #define BF_AIPS_PACRD_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP2) & BM_AIPS_PACRD_WP2) 03402 03403 /*! @brief Set the WP2 field to a new value. */ 03404 #define BW_AIPS_PACRD_WP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP2), v)) 03405 /*@}*/ 03406 03407 /*! 03408 * @name Register AIPS_PACRD, field SP2[22] (RW) 03409 * 03410 * Determines whether the peripheral requires supervisor privilege level for 03411 * accesses. When this field is set, the master privilege level must indicate the 03412 * supervisor access attribute, and the MPRx[MPLn] control field for the master 03413 * must be set. If not, access terminates with an error response and no peripheral 03414 * access initiates. 03415 * 03416 * Values: 03417 * - 0 - This peripheral does not require supervisor privilege level for 03418 * accesses. 03419 * - 1 - This peripheral requires supervisor privilege level for accesses. 03420 */ 03421 /*@{*/ 03422 #define BP_AIPS_PACRD_SP2 (22U) /*!< Bit position for AIPS_PACRD_SP2. */ 03423 #define BM_AIPS_PACRD_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRD_SP2. */ 03424 #define BS_AIPS_PACRD_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP2. */ 03425 03426 /*! @brief Read current value of the AIPS_PACRD_SP2 field. */ 03427 #define BR_AIPS_PACRD_SP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP2))) 03428 03429 /*! @brief Format value for bitfield AIPS_PACRD_SP2. */ 03430 #define BF_AIPS_PACRD_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP2) & BM_AIPS_PACRD_SP2) 03431 03432 /*! @brief Set the SP2 field to a new value. */ 03433 #define BW_AIPS_PACRD_SP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP2), v)) 03434 /*@}*/ 03435 03436 /*! 03437 * @name Register AIPS_PACRD, field TP1[24] (RW) 03438 * 03439 * Determines whether the peripheral allows accesses from an untrusted master. 03440 * When this bit is set and an access is attempted by an untrusted master, the 03441 * access terminates with an error response and no peripheral access initiates. 03442 * 03443 * Values: 03444 * - 0 - Accesses from an untrusted master are allowed. 03445 * - 1 - Accesses from an untrusted master are not allowed. 03446 */ 03447 /*@{*/ 03448 #define BP_AIPS_PACRD_TP1 (24U) /*!< Bit position for AIPS_PACRD_TP1. */ 03449 #define BM_AIPS_PACRD_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRD_TP1. */ 03450 #define BS_AIPS_PACRD_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP1. */ 03451 03452 /*! @brief Read current value of the AIPS_PACRD_TP1 field. */ 03453 #define BR_AIPS_PACRD_TP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP1))) 03454 03455 /*! @brief Format value for bitfield AIPS_PACRD_TP1. */ 03456 #define BF_AIPS_PACRD_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP1) & BM_AIPS_PACRD_TP1) 03457 03458 /*! @brief Set the TP1 field to a new value. */ 03459 #define BW_AIPS_PACRD_TP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP1), v)) 03460 /*@}*/ 03461 03462 /*! 03463 * @name Register AIPS_PACRD, field WP1[25] (RW) 03464 * 03465 * Determines whether the peripheral allows write accesses. When this field is 03466 * set and a write access is attempted, access terminates with an error response 03467 * and no peripheral access initiates. 03468 * 03469 * Values: 03470 * - 0 - This peripheral allows write accesses. 03471 * - 1 - This peripheral is write protected. 03472 */ 03473 /*@{*/ 03474 #define BP_AIPS_PACRD_WP1 (25U) /*!< Bit position for AIPS_PACRD_WP1. */ 03475 #define BM_AIPS_PACRD_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRD_WP1. */ 03476 #define BS_AIPS_PACRD_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP1. */ 03477 03478 /*! @brief Read current value of the AIPS_PACRD_WP1 field. */ 03479 #define BR_AIPS_PACRD_WP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP1))) 03480 03481 /*! @brief Format value for bitfield AIPS_PACRD_WP1. */ 03482 #define BF_AIPS_PACRD_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP1) & BM_AIPS_PACRD_WP1) 03483 03484 /*! @brief Set the WP1 field to a new value. */ 03485 #define BW_AIPS_PACRD_WP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP1), v)) 03486 /*@}*/ 03487 03488 /*! 03489 * @name Register AIPS_PACRD, field SP1[26] (RW) 03490 * 03491 * Determines whether the peripheral requires supervisor privilege level for 03492 * accesses. When this field is set, the master privilege level must indicate the 03493 * supervisor access attribute, and the MPRx[MPLn] control field for the master 03494 * must be set. If not, access terminates with an error response and no peripheral 03495 * access initiates. 03496 * 03497 * Values: 03498 * - 0 - This peripheral does not require supervisor privilege level for 03499 * accesses. 03500 * - 1 - This peripheral requires supervisor privilege level for accesses. 03501 */ 03502 /*@{*/ 03503 #define BP_AIPS_PACRD_SP1 (26U) /*!< Bit position for AIPS_PACRD_SP1. */ 03504 #define BM_AIPS_PACRD_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRD_SP1. */ 03505 #define BS_AIPS_PACRD_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP1. */ 03506 03507 /*! @brief Read current value of the AIPS_PACRD_SP1 field. */ 03508 #define BR_AIPS_PACRD_SP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP1))) 03509 03510 /*! @brief Format value for bitfield AIPS_PACRD_SP1. */ 03511 #define BF_AIPS_PACRD_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP1) & BM_AIPS_PACRD_SP1) 03512 03513 /*! @brief Set the SP1 field to a new value. */ 03514 #define BW_AIPS_PACRD_SP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP1), v)) 03515 /*@}*/ 03516 03517 /*! 03518 * @name Register AIPS_PACRD, field TP0[28] (RW) 03519 * 03520 * Determines whether the peripheral allows accesses from an untrusted master. 03521 * When this field is set and an access is attempted by an untrusted master, the 03522 * access terminates with an error response and no peripheral access initiates. 03523 * 03524 * Values: 03525 * - 0 - Accesses from an untrusted master are allowed. 03526 * - 1 - Accesses from an untrusted master are not allowed. 03527 */ 03528 /*@{*/ 03529 #define BP_AIPS_PACRD_TP0 (28U) /*!< Bit position for AIPS_PACRD_TP0. */ 03530 #define BM_AIPS_PACRD_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRD_TP0. */ 03531 #define BS_AIPS_PACRD_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRD_TP0. */ 03532 03533 /*! @brief Read current value of the AIPS_PACRD_TP0 field. */ 03534 #define BR_AIPS_PACRD_TP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP0))) 03535 03536 /*! @brief Format value for bitfield AIPS_PACRD_TP0. */ 03537 #define BF_AIPS_PACRD_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_TP0) & BM_AIPS_PACRD_TP0) 03538 03539 /*! @brief Set the TP0 field to a new value. */ 03540 #define BW_AIPS_PACRD_TP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_TP0), v)) 03541 /*@}*/ 03542 03543 /*! 03544 * @name Register AIPS_PACRD, field WP0[29] (RW) 03545 * 03546 * Determines whether the peripheral allows write accesss. When this bit is set 03547 * and a write access is attempted, access terminates with an error response and 03548 * no peripheral access initiates. 03549 * 03550 * Values: 03551 * - 0 - This peripheral allows write accesses. 03552 * - 1 - This peripheral is write protected. 03553 */ 03554 /*@{*/ 03555 #define BP_AIPS_PACRD_WP0 (29U) /*!< Bit position for AIPS_PACRD_WP0. */ 03556 #define BM_AIPS_PACRD_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRD_WP0. */ 03557 #define BS_AIPS_PACRD_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRD_WP0. */ 03558 03559 /*! @brief Read current value of the AIPS_PACRD_WP0 field. */ 03560 #define BR_AIPS_PACRD_WP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP0))) 03561 03562 /*! @brief Format value for bitfield AIPS_PACRD_WP0. */ 03563 #define BF_AIPS_PACRD_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_WP0) & BM_AIPS_PACRD_WP0) 03564 03565 /*! @brief Set the WP0 field to a new value. */ 03566 #define BW_AIPS_PACRD_WP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_WP0), v)) 03567 /*@}*/ 03568 03569 /*! 03570 * @name Register AIPS_PACRD, field SP0[30] (RW) 03571 * 03572 * Determines whether the peripheral requires supervisor privilege level for 03573 * accesses. When this field is set, the master privilege level must indicate the 03574 * supervisor access attribute, and the MPRx[MPLn] control field for the master 03575 * must be set. If not, access terminates with an error response and no peripheral 03576 * access initiates. 03577 * 03578 * Values: 03579 * - 0 - This peripheral does not require supervisor privilege level for 03580 * accesses. 03581 * - 1 - This peripheral requires supervisor privilege level for accesses. 03582 */ 03583 /*@{*/ 03584 #define BP_AIPS_PACRD_SP0 (30U) /*!< Bit position for AIPS_PACRD_SP0. */ 03585 #define BM_AIPS_PACRD_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRD_SP0. */ 03586 #define BS_AIPS_PACRD_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRD_SP0. */ 03587 03588 /*! @brief Read current value of the AIPS_PACRD_SP0 field. */ 03589 #define BR_AIPS_PACRD_SP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP0))) 03590 03591 /*! @brief Format value for bitfield AIPS_PACRD_SP0. */ 03592 #define BF_AIPS_PACRD_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRD_SP0) & BM_AIPS_PACRD_SP0) 03593 03594 /*! @brief Set the SP0 field to a new value. */ 03595 #define BW_AIPS_PACRD_SP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRD_ADDR(x), BP_AIPS_PACRD_SP0), v)) 03596 /*@}*/ 03597 03598 /******************************************************************************* 03599 * HW_AIPS_PACRE - Peripheral Access Control Register 03600 ******************************************************************************/ 03601 03602 /*! 03603 * @brief HW_AIPS_PACRE - Peripheral Access Control Register (RW) 03604 * 03605 * Reset value: 0x44444444U 03606 * 03607 * This section describes PACR registers E-P, which control peripheral slots 03608 * 32-127. See PACRPeripheral Access Control Register for the description of these 03609 * registers. 03610 */ 03611 typedef union _hw_aips_pacre 03612 { 03613 uint32_t U; 03614 struct _hw_aips_pacre_bitfields 03615 { 03616 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 03617 uint32_t WP7 : 1; /*!< [1] Write Protect */ 03618 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 03619 uint32_t RESERVED0 : 1; /*!< [3] */ 03620 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 03621 uint32_t WP6 : 1; /*!< [5] Write Protect */ 03622 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 03623 uint32_t RESERVED1 : 1; /*!< [7] */ 03624 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 03625 uint32_t WP5 : 1; /*!< [9] Write Protect */ 03626 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 03627 uint32_t RESERVED2 : 1; /*!< [11] */ 03628 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 03629 uint32_t WP4 : 1; /*!< [13] Write Protect */ 03630 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 03631 uint32_t RESERVED3 : 1; /*!< [15] */ 03632 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 03633 uint32_t WP3 : 1; /*!< [17] Write Protect */ 03634 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 03635 uint32_t RESERVED4 : 1; /*!< [19] */ 03636 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 03637 uint32_t WP2 : 1; /*!< [21] Write Protect */ 03638 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 03639 uint32_t RESERVED5 : 1; /*!< [23] */ 03640 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 03641 uint32_t WP1 : 1; /*!< [25] Write Protect */ 03642 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 03643 uint32_t RESERVED6 : 1; /*!< [27] */ 03644 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 03645 uint32_t WP0 : 1; /*!< [29] Write Protect */ 03646 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 03647 uint32_t RESERVED7 : 1; /*!< [31] */ 03648 } B; 03649 } hw_aips_pacre_t; 03650 03651 /*! 03652 * @name Constants and macros for entire AIPS_PACRE register 03653 */ 03654 /*@{*/ 03655 #define HW_AIPS_PACRE_ADDR(x) ((x) + 0x40U) 03656 03657 #define HW_AIPS_PACRE(x) (*(__IO hw_aips_pacre_t *) HW_AIPS_PACRE_ADDR(x)) 03658 #define HW_AIPS_PACRE_RD(x) (ADDRESS_READ(hw_aips_pacre_t, HW_AIPS_PACRE_ADDR(x))) 03659 #define HW_AIPS_PACRE_WR(x, v) (ADDRESS_WRITE(hw_aips_pacre_t, HW_AIPS_PACRE_ADDR(x), v)) 03660 #define HW_AIPS_PACRE_SET(x, v) (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) | (v))) 03661 #define HW_AIPS_PACRE_CLR(x, v) (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) & ~(v))) 03662 #define HW_AIPS_PACRE_TOG(x, v) (HW_AIPS_PACRE_WR(x, HW_AIPS_PACRE_RD(x) ^ (v))) 03663 /*@}*/ 03664 03665 /* 03666 * Constants & macros for individual AIPS_PACRE bitfields 03667 */ 03668 03669 /*! 03670 * @name Register AIPS_PACRE, field TP7[0] (RW) 03671 * 03672 * Determines whether the peripheral allows accesses from an untrusted master. 03673 * When this field is set and an access is attempted by an untrusted master, the 03674 * access terminates with an error response and no peripheral access initiates. 03675 * 03676 * Values: 03677 * - 0 - Accesses from an untrusted master are allowed. 03678 * - 1 - Accesses from an untrusted master are not allowed. 03679 */ 03680 /*@{*/ 03681 #define BP_AIPS_PACRE_TP7 (0U) /*!< Bit position for AIPS_PACRE_TP7. */ 03682 #define BM_AIPS_PACRE_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRE_TP7. */ 03683 #define BS_AIPS_PACRE_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP7. */ 03684 03685 /*! @brief Read current value of the AIPS_PACRE_TP7 field. */ 03686 #define BR_AIPS_PACRE_TP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP7))) 03687 03688 /*! @brief Format value for bitfield AIPS_PACRE_TP7. */ 03689 #define BF_AIPS_PACRE_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP7) & BM_AIPS_PACRE_TP7) 03690 03691 /*! @brief Set the TP7 field to a new value. */ 03692 #define BW_AIPS_PACRE_TP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP7), v)) 03693 /*@}*/ 03694 03695 /*! 03696 * @name Register AIPS_PACRE, field WP7[1] (RW) 03697 * 03698 * Determines whether the peripheral allows write accesses. When this field is 03699 * set and a write access is attempted, access terminates with an error response 03700 * and no peripheral access initiates. 03701 * 03702 * Values: 03703 * - 0 - This peripheral allows write accesses. 03704 * - 1 - This peripheral is write protected. 03705 */ 03706 /*@{*/ 03707 #define BP_AIPS_PACRE_WP7 (1U) /*!< Bit position for AIPS_PACRE_WP7. */ 03708 #define BM_AIPS_PACRE_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRE_WP7. */ 03709 #define BS_AIPS_PACRE_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP7. */ 03710 03711 /*! @brief Read current value of the AIPS_PACRE_WP7 field. */ 03712 #define BR_AIPS_PACRE_WP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP7))) 03713 03714 /*! @brief Format value for bitfield AIPS_PACRE_WP7. */ 03715 #define BF_AIPS_PACRE_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP7) & BM_AIPS_PACRE_WP7) 03716 03717 /*! @brief Set the WP7 field to a new value. */ 03718 #define BW_AIPS_PACRE_WP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP7), v)) 03719 /*@}*/ 03720 03721 /*! 03722 * @name Register AIPS_PACRE, field SP7[2] (RW) 03723 * 03724 * Determines whether the peripheral requires supervisor privilege level for 03725 * accesses. When this field is set, the master privilege level must indicate the 03726 * supervisor access attribute, and the MPRx[MPLn] control field for the master 03727 * must be set. If not, access terminates with an error response and no peripheral 03728 * access initiates. 03729 * 03730 * Values: 03731 * - 0 - This peripheral does not require supervisor privilege level for 03732 * accesses. 03733 * - 1 - This peripheral requires supervisor privilege level for accesses. 03734 */ 03735 /*@{*/ 03736 #define BP_AIPS_PACRE_SP7 (2U) /*!< Bit position for AIPS_PACRE_SP7. */ 03737 #define BM_AIPS_PACRE_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRE_SP7. */ 03738 #define BS_AIPS_PACRE_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP7. */ 03739 03740 /*! @brief Read current value of the AIPS_PACRE_SP7 field. */ 03741 #define BR_AIPS_PACRE_SP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP7))) 03742 03743 /*! @brief Format value for bitfield AIPS_PACRE_SP7. */ 03744 #define BF_AIPS_PACRE_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP7) & BM_AIPS_PACRE_SP7) 03745 03746 /*! @brief Set the SP7 field to a new value. */ 03747 #define BW_AIPS_PACRE_SP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP7), v)) 03748 /*@}*/ 03749 03750 /*! 03751 * @name Register AIPS_PACRE, field TP6[4] (RW) 03752 * 03753 * Determines whether the peripheral allows accesses from an untrusted master. 03754 * When this field is set and an access is attempted by an untrusted master, the 03755 * access terminates with an error response and no peripheral access initiates. 03756 * 03757 * Values: 03758 * - 0 - Accesses from an untrusted master are allowed. 03759 * - 1 - Accesses from an untrusted master are not allowed. 03760 */ 03761 /*@{*/ 03762 #define BP_AIPS_PACRE_TP6 (4U) /*!< Bit position for AIPS_PACRE_TP6. */ 03763 #define BM_AIPS_PACRE_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRE_TP6. */ 03764 #define BS_AIPS_PACRE_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP6. */ 03765 03766 /*! @brief Read current value of the AIPS_PACRE_TP6 field. */ 03767 #define BR_AIPS_PACRE_TP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP6))) 03768 03769 /*! @brief Format value for bitfield AIPS_PACRE_TP6. */ 03770 #define BF_AIPS_PACRE_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP6) & BM_AIPS_PACRE_TP6) 03771 03772 /*! @brief Set the TP6 field to a new value. */ 03773 #define BW_AIPS_PACRE_TP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP6), v)) 03774 /*@}*/ 03775 03776 /*! 03777 * @name Register AIPS_PACRE, field WP6[5] (RW) 03778 * 03779 * Determines whether the peripheral allows write accesses. When this field is 03780 * set and a write access is attempted, access terminates with an error response 03781 * and no peripheral access initiates. 03782 * 03783 * Values: 03784 * - 0 - This peripheral allows write accesses. 03785 * - 1 - This peripheral is write protected. 03786 */ 03787 /*@{*/ 03788 #define BP_AIPS_PACRE_WP6 (5U) /*!< Bit position for AIPS_PACRE_WP6. */ 03789 #define BM_AIPS_PACRE_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRE_WP6. */ 03790 #define BS_AIPS_PACRE_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP6. */ 03791 03792 /*! @brief Read current value of the AIPS_PACRE_WP6 field. */ 03793 #define BR_AIPS_PACRE_WP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP6))) 03794 03795 /*! @brief Format value for bitfield AIPS_PACRE_WP6. */ 03796 #define BF_AIPS_PACRE_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP6) & BM_AIPS_PACRE_WP6) 03797 03798 /*! @brief Set the WP6 field to a new value. */ 03799 #define BW_AIPS_PACRE_WP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP6), v)) 03800 /*@}*/ 03801 03802 /*! 03803 * @name Register AIPS_PACRE, field SP6[6] (RW) 03804 * 03805 * Determines whether the peripheral requires supervisor privilege level for 03806 * accesses. When this field is set, the master privilege level must indicate the 03807 * supervisor access attribute, and the MPRx[MPLn] control field for the master 03808 * must be set. If not, access terminates with an error response and no peripheral 03809 * access initiates. 03810 * 03811 * Values: 03812 * - 0 - This peripheral does not require supervisor privilege level for 03813 * accesses. 03814 * - 1 - This peripheral requires supervisor privilege level for accesses. 03815 */ 03816 /*@{*/ 03817 #define BP_AIPS_PACRE_SP6 (6U) /*!< Bit position for AIPS_PACRE_SP6. */ 03818 #define BM_AIPS_PACRE_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRE_SP6. */ 03819 #define BS_AIPS_PACRE_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP6. */ 03820 03821 /*! @brief Read current value of the AIPS_PACRE_SP6 field. */ 03822 #define BR_AIPS_PACRE_SP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP6))) 03823 03824 /*! @brief Format value for bitfield AIPS_PACRE_SP6. */ 03825 #define BF_AIPS_PACRE_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP6) & BM_AIPS_PACRE_SP6) 03826 03827 /*! @brief Set the SP6 field to a new value. */ 03828 #define BW_AIPS_PACRE_SP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP6), v)) 03829 /*@}*/ 03830 03831 /*! 03832 * @name Register AIPS_PACRE, field TP5[8] (RW) 03833 * 03834 * Determines whether the peripheral allows accesses from an untrusted master. 03835 * When this field is set and an access is attempted by an untrusted master, the 03836 * access terminates with an error response and no peripheral access initiates. 03837 * 03838 * Values: 03839 * - 0 - Accesses from an untrusted master are allowed. 03840 * - 1 - Accesses from an untrusted master are not allowed. 03841 */ 03842 /*@{*/ 03843 #define BP_AIPS_PACRE_TP5 (8U) /*!< Bit position for AIPS_PACRE_TP5. */ 03844 #define BM_AIPS_PACRE_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRE_TP5. */ 03845 #define BS_AIPS_PACRE_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP5. */ 03846 03847 /*! @brief Read current value of the AIPS_PACRE_TP5 field. */ 03848 #define BR_AIPS_PACRE_TP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP5))) 03849 03850 /*! @brief Format value for bitfield AIPS_PACRE_TP5. */ 03851 #define BF_AIPS_PACRE_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP5) & BM_AIPS_PACRE_TP5) 03852 03853 /*! @brief Set the TP5 field to a new value. */ 03854 #define BW_AIPS_PACRE_TP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP5), v)) 03855 /*@}*/ 03856 03857 /*! 03858 * @name Register AIPS_PACRE, field WP5[9] (RW) 03859 * 03860 * Determines whether the peripheral allows write accesses. When this field is 03861 * set and a write access is attempted, access terminates with an error response 03862 * and no peripheral access initiates. 03863 * 03864 * Values: 03865 * - 0 - This peripheral allows write accesses. 03866 * - 1 - This peripheral is write protected. 03867 */ 03868 /*@{*/ 03869 #define BP_AIPS_PACRE_WP5 (9U) /*!< Bit position for AIPS_PACRE_WP5. */ 03870 #define BM_AIPS_PACRE_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRE_WP5. */ 03871 #define BS_AIPS_PACRE_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP5. */ 03872 03873 /*! @brief Read current value of the AIPS_PACRE_WP5 field. */ 03874 #define BR_AIPS_PACRE_WP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP5))) 03875 03876 /*! @brief Format value for bitfield AIPS_PACRE_WP5. */ 03877 #define BF_AIPS_PACRE_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP5) & BM_AIPS_PACRE_WP5) 03878 03879 /*! @brief Set the WP5 field to a new value. */ 03880 #define BW_AIPS_PACRE_WP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP5), v)) 03881 /*@}*/ 03882 03883 /*! 03884 * @name Register AIPS_PACRE, field SP5[10] (RW) 03885 * 03886 * Determines whether the peripheral requires supervisor privilege level for 03887 * accesses. When this field is set, the master privilege level must indicate the 03888 * supervisor access attribute, and the MPRx[MPLn] control field for the master 03889 * must be set. If not, access terminates with an error response and no peripheral 03890 * access initiates. 03891 * 03892 * Values: 03893 * - 0 - This peripheral does not require supervisor privilege level for 03894 * accesses. 03895 * - 1 - This peripheral requires supervisor privilege level for accesses. 03896 */ 03897 /*@{*/ 03898 #define BP_AIPS_PACRE_SP5 (10U) /*!< Bit position for AIPS_PACRE_SP5. */ 03899 #define BM_AIPS_PACRE_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRE_SP5. */ 03900 #define BS_AIPS_PACRE_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP5. */ 03901 03902 /*! @brief Read current value of the AIPS_PACRE_SP5 field. */ 03903 #define BR_AIPS_PACRE_SP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP5))) 03904 03905 /*! @brief Format value for bitfield AIPS_PACRE_SP5. */ 03906 #define BF_AIPS_PACRE_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP5) & BM_AIPS_PACRE_SP5) 03907 03908 /*! @brief Set the SP5 field to a new value. */ 03909 #define BW_AIPS_PACRE_SP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP5), v)) 03910 /*@}*/ 03911 03912 /*! 03913 * @name Register AIPS_PACRE, field TP4[12] (RW) 03914 * 03915 * Determines whether the peripheral allows accesses from an untrusted master. 03916 * When this bit is set and an access is attempted by an untrusted master, the 03917 * access terminates with an error response and no peripheral access initiates. 03918 * 03919 * Values: 03920 * - 0 - Accesses from an untrusted master are allowed. 03921 * - 1 - Accesses from an untrusted master are not allowed. 03922 */ 03923 /*@{*/ 03924 #define BP_AIPS_PACRE_TP4 (12U) /*!< Bit position for AIPS_PACRE_TP4. */ 03925 #define BM_AIPS_PACRE_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRE_TP4. */ 03926 #define BS_AIPS_PACRE_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP4. */ 03927 03928 /*! @brief Read current value of the AIPS_PACRE_TP4 field. */ 03929 #define BR_AIPS_PACRE_TP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP4))) 03930 03931 /*! @brief Format value for bitfield AIPS_PACRE_TP4. */ 03932 #define BF_AIPS_PACRE_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP4) & BM_AIPS_PACRE_TP4) 03933 03934 /*! @brief Set the TP4 field to a new value. */ 03935 #define BW_AIPS_PACRE_TP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP4), v)) 03936 /*@}*/ 03937 03938 /*! 03939 * @name Register AIPS_PACRE, field WP4[13] (RW) 03940 * 03941 * Determines whether the peripheral allows write accesses. When this field is 03942 * set and a write access is attempted, access terminates with an error response 03943 * and no peripheral access initiates. 03944 * 03945 * Values: 03946 * - 0 - This peripheral allows write accesses. 03947 * - 1 - This peripheral is write protected. 03948 */ 03949 /*@{*/ 03950 #define BP_AIPS_PACRE_WP4 (13U) /*!< Bit position for AIPS_PACRE_WP4. */ 03951 #define BM_AIPS_PACRE_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRE_WP4. */ 03952 #define BS_AIPS_PACRE_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP4. */ 03953 03954 /*! @brief Read current value of the AIPS_PACRE_WP4 field. */ 03955 #define BR_AIPS_PACRE_WP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP4))) 03956 03957 /*! @brief Format value for bitfield AIPS_PACRE_WP4. */ 03958 #define BF_AIPS_PACRE_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP4) & BM_AIPS_PACRE_WP4) 03959 03960 /*! @brief Set the WP4 field to a new value. */ 03961 #define BW_AIPS_PACRE_WP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP4), v)) 03962 /*@}*/ 03963 03964 /*! 03965 * @name Register AIPS_PACRE, field SP4[14] (RW) 03966 * 03967 * Determines whether the peripheral requires supervisor privilege level for 03968 * access. When this bit is set, the master privilege level must indicate the 03969 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 03970 * set. If not, access terminates with an error response and no peripheral access 03971 * initiates. 03972 * 03973 * Values: 03974 * - 0 - This peripheral does not require supervisor privilege level for 03975 * accesses. 03976 * - 1 - This peripheral requires supervisor privilege level for accesses. 03977 */ 03978 /*@{*/ 03979 #define BP_AIPS_PACRE_SP4 (14U) /*!< Bit position for AIPS_PACRE_SP4. */ 03980 #define BM_AIPS_PACRE_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRE_SP4. */ 03981 #define BS_AIPS_PACRE_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP4. */ 03982 03983 /*! @brief Read current value of the AIPS_PACRE_SP4 field. */ 03984 #define BR_AIPS_PACRE_SP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP4))) 03985 03986 /*! @brief Format value for bitfield AIPS_PACRE_SP4. */ 03987 #define BF_AIPS_PACRE_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP4) & BM_AIPS_PACRE_SP4) 03988 03989 /*! @brief Set the SP4 field to a new value. */ 03990 #define BW_AIPS_PACRE_SP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP4), v)) 03991 /*@}*/ 03992 03993 /*! 03994 * @name Register AIPS_PACRE, field TP3[16] (RW) 03995 * 03996 * Determines whether the peripheral allows accesses from an untrusted master. 03997 * When this field is set and an access is attempted by an untrusted master, the 03998 * access terminates with an error response and no peripheral access initiates. 03999 * 04000 * Values: 04001 * - 0 - Accesses from an untrusted master are allowed. 04002 * - 1 - Accesses from an untrusted master are not allowed. 04003 */ 04004 /*@{*/ 04005 #define BP_AIPS_PACRE_TP3 (16U) /*!< Bit position for AIPS_PACRE_TP3. */ 04006 #define BM_AIPS_PACRE_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRE_TP3. */ 04007 #define BS_AIPS_PACRE_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP3. */ 04008 04009 /*! @brief Read current value of the AIPS_PACRE_TP3 field. */ 04010 #define BR_AIPS_PACRE_TP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP3))) 04011 04012 /*! @brief Format value for bitfield AIPS_PACRE_TP3. */ 04013 #define BF_AIPS_PACRE_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP3) & BM_AIPS_PACRE_TP3) 04014 04015 /*! @brief Set the TP3 field to a new value. */ 04016 #define BW_AIPS_PACRE_TP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP3), v)) 04017 /*@}*/ 04018 04019 /*! 04020 * @name Register AIPS_PACRE, field WP3[17] (RW) 04021 * 04022 * Determines whether the peripheral allows write accesss. When this bit is set 04023 * and a write access is attempted, access terminates with an error response and 04024 * no peripheral access initiates. 04025 * 04026 * Values: 04027 * - 0 - This peripheral allows write accesses. 04028 * - 1 - This peripheral is write protected. 04029 */ 04030 /*@{*/ 04031 #define BP_AIPS_PACRE_WP3 (17U) /*!< Bit position for AIPS_PACRE_WP3. */ 04032 #define BM_AIPS_PACRE_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRE_WP3. */ 04033 #define BS_AIPS_PACRE_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP3. */ 04034 04035 /*! @brief Read current value of the AIPS_PACRE_WP3 field. */ 04036 #define BR_AIPS_PACRE_WP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP3))) 04037 04038 /*! @brief Format value for bitfield AIPS_PACRE_WP3. */ 04039 #define BF_AIPS_PACRE_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP3) & BM_AIPS_PACRE_WP3) 04040 04041 /*! @brief Set the WP3 field to a new value. */ 04042 #define BW_AIPS_PACRE_WP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP3), v)) 04043 /*@}*/ 04044 04045 /*! 04046 * @name Register AIPS_PACRE, field SP3[18] (RW) 04047 * 04048 * Determines whether the peripheral requires supervisor privilege level for 04049 * accesses. When this field is set, the master privilege level must indicate the 04050 * supervisor access attribute, and the MPRx[MPLn] control field for the master 04051 * must be set. If not, access terminates with an error response and no peripheral 04052 * access initiates. 04053 * 04054 * Values: 04055 * - 0 - This peripheral does not require supervisor privilege level for 04056 * accesses. 04057 * - 1 - This peripheral requires supervisor privilege level for accesses. 04058 */ 04059 /*@{*/ 04060 #define BP_AIPS_PACRE_SP3 (18U) /*!< Bit position for AIPS_PACRE_SP3. */ 04061 #define BM_AIPS_PACRE_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRE_SP3. */ 04062 #define BS_AIPS_PACRE_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP3. */ 04063 04064 /*! @brief Read current value of the AIPS_PACRE_SP3 field. */ 04065 #define BR_AIPS_PACRE_SP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP3))) 04066 04067 /*! @brief Format value for bitfield AIPS_PACRE_SP3. */ 04068 #define BF_AIPS_PACRE_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP3) & BM_AIPS_PACRE_SP3) 04069 04070 /*! @brief Set the SP3 field to a new value. */ 04071 #define BW_AIPS_PACRE_SP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP3), v)) 04072 /*@}*/ 04073 04074 /*! 04075 * @name Register AIPS_PACRE, field TP2[20] (RW) 04076 * 04077 * Determines whether the peripheral allows accesses from an untrusted master. 04078 * When this bit is set and an access is attempted by an untrusted master, the 04079 * access terminates with an error response and no peripheral access initiates. 04080 * 04081 * Values: 04082 * - 0 - Accesses from an untrusted master are allowed. 04083 * - 1 - Accesses from an untrusted master are not allowed. 04084 */ 04085 /*@{*/ 04086 #define BP_AIPS_PACRE_TP2 (20U) /*!< Bit position for AIPS_PACRE_TP2. */ 04087 #define BM_AIPS_PACRE_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRE_TP2. */ 04088 #define BS_AIPS_PACRE_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP2. */ 04089 04090 /*! @brief Read current value of the AIPS_PACRE_TP2 field. */ 04091 #define BR_AIPS_PACRE_TP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP2))) 04092 04093 /*! @brief Format value for bitfield AIPS_PACRE_TP2. */ 04094 #define BF_AIPS_PACRE_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP2) & BM_AIPS_PACRE_TP2) 04095 04096 /*! @brief Set the TP2 field to a new value. */ 04097 #define BW_AIPS_PACRE_TP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP2), v)) 04098 /*@}*/ 04099 04100 /*! 04101 * @name Register AIPS_PACRE, field WP2[21] (RW) 04102 * 04103 * Determines whether the peripheral allows write accesses. When this field is 04104 * set and a write access is attempted, access terminates with an error response 04105 * and no peripheral access initiates. 04106 * 04107 * Values: 04108 * - 0 - This peripheral allows write accesses. 04109 * - 1 - This peripheral is write protected. 04110 */ 04111 /*@{*/ 04112 #define BP_AIPS_PACRE_WP2 (21U) /*!< Bit position for AIPS_PACRE_WP2. */ 04113 #define BM_AIPS_PACRE_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRE_WP2. */ 04114 #define BS_AIPS_PACRE_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP2. */ 04115 04116 /*! @brief Read current value of the AIPS_PACRE_WP2 field. */ 04117 #define BR_AIPS_PACRE_WP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP2))) 04118 04119 /*! @brief Format value for bitfield AIPS_PACRE_WP2. */ 04120 #define BF_AIPS_PACRE_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP2) & BM_AIPS_PACRE_WP2) 04121 04122 /*! @brief Set the WP2 field to a new value. */ 04123 #define BW_AIPS_PACRE_WP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP2), v)) 04124 /*@}*/ 04125 04126 /*! 04127 * @name Register AIPS_PACRE, field SP2[22] (RW) 04128 * 04129 * Determines whether the peripheral requires supervisor privilege level for 04130 * access. When this bit is set, the master privilege level must indicate the 04131 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 04132 * set. If not, access terminates with an error response and no peripheral access 04133 * initiates. 04134 * 04135 * Values: 04136 * - 0 - This peripheral does not require supervisor privilege level for 04137 * accesses. 04138 * - 1 - This peripheral requires supervisor privilege level for accesses. 04139 */ 04140 /*@{*/ 04141 #define BP_AIPS_PACRE_SP2 (22U) /*!< Bit position for AIPS_PACRE_SP2. */ 04142 #define BM_AIPS_PACRE_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRE_SP2. */ 04143 #define BS_AIPS_PACRE_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP2. */ 04144 04145 /*! @brief Read current value of the AIPS_PACRE_SP2 field. */ 04146 #define BR_AIPS_PACRE_SP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP2))) 04147 04148 /*! @brief Format value for bitfield AIPS_PACRE_SP2. */ 04149 #define BF_AIPS_PACRE_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP2) & BM_AIPS_PACRE_SP2) 04150 04151 /*! @brief Set the SP2 field to a new value. */ 04152 #define BW_AIPS_PACRE_SP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP2), v)) 04153 /*@}*/ 04154 04155 /*! 04156 * @name Register AIPS_PACRE, field TP1[24] (RW) 04157 * 04158 * Determines whether the peripheral allows accesses from an untrusted master. 04159 * When this field is set and an access is attempted by an untrusted master, the 04160 * access terminates with an error response and no peripheral access initiates. 04161 * 04162 * Values: 04163 * - 0 - Accesses from an untrusted master are allowed. 04164 * - 1 - Accesses from an untrusted master are not allowed. 04165 */ 04166 /*@{*/ 04167 #define BP_AIPS_PACRE_TP1 (24U) /*!< Bit position for AIPS_PACRE_TP1. */ 04168 #define BM_AIPS_PACRE_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRE_TP1. */ 04169 #define BS_AIPS_PACRE_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP1. */ 04170 04171 /*! @brief Read current value of the AIPS_PACRE_TP1 field. */ 04172 #define BR_AIPS_PACRE_TP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP1))) 04173 04174 /*! @brief Format value for bitfield AIPS_PACRE_TP1. */ 04175 #define BF_AIPS_PACRE_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP1) & BM_AIPS_PACRE_TP1) 04176 04177 /*! @brief Set the TP1 field to a new value. */ 04178 #define BW_AIPS_PACRE_TP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP1), v)) 04179 /*@}*/ 04180 04181 /*! 04182 * @name Register AIPS_PACRE, field WP1[25] (RW) 04183 * 04184 * Determines whether the peripheral allows write accesses. When this field is 04185 * set and a write access is attempted, access terminates with an error response 04186 * and no peripheral access initiates. 04187 * 04188 * Values: 04189 * - 0 - This peripheral allows write accesses. 04190 * - 1 - This peripheral is write protected. 04191 */ 04192 /*@{*/ 04193 #define BP_AIPS_PACRE_WP1 (25U) /*!< Bit position for AIPS_PACRE_WP1. */ 04194 #define BM_AIPS_PACRE_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRE_WP1. */ 04195 #define BS_AIPS_PACRE_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP1. */ 04196 04197 /*! @brief Read current value of the AIPS_PACRE_WP1 field. */ 04198 #define BR_AIPS_PACRE_WP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP1))) 04199 04200 /*! @brief Format value for bitfield AIPS_PACRE_WP1. */ 04201 #define BF_AIPS_PACRE_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP1) & BM_AIPS_PACRE_WP1) 04202 04203 /*! @brief Set the WP1 field to a new value. */ 04204 #define BW_AIPS_PACRE_WP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP1), v)) 04205 /*@}*/ 04206 04207 /*! 04208 * @name Register AIPS_PACRE, field SP1[26] (RW) 04209 * 04210 * Determines whether the peripheral requires supervisor privilege level for 04211 * access. When this field is set, the master privilege level must indicate the 04212 * supervisor access attribute, and the MPRx[MPLn] control field for the master must 04213 * be set. If not, access terminates with an error response and no peripheral 04214 * access initiates. 04215 * 04216 * Values: 04217 * - 0 - This peripheral does not require supervisor privilege level for 04218 * accesses. 04219 * - 1 - This peripheral requires supervisor privilege level for accesses. 04220 */ 04221 /*@{*/ 04222 #define BP_AIPS_PACRE_SP1 (26U) /*!< Bit position for AIPS_PACRE_SP1. */ 04223 #define BM_AIPS_PACRE_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRE_SP1. */ 04224 #define BS_AIPS_PACRE_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP1. */ 04225 04226 /*! @brief Read current value of the AIPS_PACRE_SP1 field. */ 04227 #define BR_AIPS_PACRE_SP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP1))) 04228 04229 /*! @brief Format value for bitfield AIPS_PACRE_SP1. */ 04230 #define BF_AIPS_PACRE_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP1) & BM_AIPS_PACRE_SP1) 04231 04232 /*! @brief Set the SP1 field to a new value. */ 04233 #define BW_AIPS_PACRE_SP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP1), v)) 04234 /*@}*/ 04235 04236 /*! 04237 * @name Register AIPS_PACRE, field TP0[28] (RW) 04238 * 04239 * Determines whether the peripheral allows accesses from an untrusted master. 04240 * When this bit is set and an access is attempted by an untrusted master, the 04241 * access terminates with an error response and no peripheral access initiates. 04242 * 04243 * Values: 04244 * - 0 - Accesses from an untrusted master are allowed. 04245 * - 1 - Accesses from an untrusted master are not allowed. 04246 */ 04247 /*@{*/ 04248 #define BP_AIPS_PACRE_TP0 (28U) /*!< Bit position for AIPS_PACRE_TP0. */ 04249 #define BM_AIPS_PACRE_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRE_TP0. */ 04250 #define BS_AIPS_PACRE_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRE_TP0. */ 04251 04252 /*! @brief Read current value of the AIPS_PACRE_TP0 field. */ 04253 #define BR_AIPS_PACRE_TP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP0))) 04254 04255 /*! @brief Format value for bitfield AIPS_PACRE_TP0. */ 04256 #define BF_AIPS_PACRE_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_TP0) & BM_AIPS_PACRE_TP0) 04257 04258 /*! @brief Set the TP0 field to a new value. */ 04259 #define BW_AIPS_PACRE_TP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_TP0), v)) 04260 /*@}*/ 04261 04262 /*! 04263 * @name Register AIPS_PACRE, field WP0[29] (RW) 04264 * 04265 * Determines whether the peripheral allows write accesses. When this field is 04266 * set and a write access is attempted, access terminates with an error response 04267 * and no peripheral access initiates. 04268 * 04269 * Values: 04270 * - 0 - This peripheral allows write accesses. 04271 * - 1 - This peripheral is write protected. 04272 */ 04273 /*@{*/ 04274 #define BP_AIPS_PACRE_WP0 (29U) /*!< Bit position for AIPS_PACRE_WP0. */ 04275 #define BM_AIPS_PACRE_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRE_WP0. */ 04276 #define BS_AIPS_PACRE_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRE_WP0. */ 04277 04278 /*! @brief Read current value of the AIPS_PACRE_WP0 field. */ 04279 #define BR_AIPS_PACRE_WP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP0))) 04280 04281 /*! @brief Format value for bitfield AIPS_PACRE_WP0. */ 04282 #define BF_AIPS_PACRE_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_WP0) & BM_AIPS_PACRE_WP0) 04283 04284 /*! @brief Set the WP0 field to a new value. */ 04285 #define BW_AIPS_PACRE_WP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_WP0), v)) 04286 /*@}*/ 04287 04288 /*! 04289 * @name Register AIPS_PACRE, field SP0[30] (RW) 04290 * 04291 * Determines whether the peripheral requires supervisor privilege level for 04292 * accesses. When this field is set, the master privilege level must indicate the 04293 * supervisor access attribute, and the MPRx[MPLn] control field for the master 04294 * must be set. If not, access terminates with an error response and no peripheral 04295 * access initiates. 04296 * 04297 * Values: 04298 * - 0 - This peripheral does not require supervisor privilege level for 04299 * accesses. 04300 * - 1 - This peripheral requires supervisor privilege level for accesses. 04301 */ 04302 /*@{*/ 04303 #define BP_AIPS_PACRE_SP0 (30U) /*!< Bit position for AIPS_PACRE_SP0. */ 04304 #define BM_AIPS_PACRE_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRE_SP0. */ 04305 #define BS_AIPS_PACRE_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRE_SP0. */ 04306 04307 /*! @brief Read current value of the AIPS_PACRE_SP0 field. */ 04308 #define BR_AIPS_PACRE_SP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP0))) 04309 04310 /*! @brief Format value for bitfield AIPS_PACRE_SP0. */ 04311 #define BF_AIPS_PACRE_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRE_SP0) & BM_AIPS_PACRE_SP0) 04312 04313 /*! @brief Set the SP0 field to a new value. */ 04314 #define BW_AIPS_PACRE_SP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRE_ADDR(x), BP_AIPS_PACRE_SP0), v)) 04315 /*@}*/ 04316 04317 /******************************************************************************* 04318 * HW_AIPS_PACRF - Peripheral Access Control Register 04319 ******************************************************************************/ 04320 04321 /*! 04322 * @brief HW_AIPS_PACRF - Peripheral Access Control Register (RW) 04323 * 04324 * Reset value: 0x44444444U 04325 * 04326 * This section describes PACR registers E-P, which control peripheral slots 04327 * 32-127. See PACRPeripheral Access Control Register for the description of these 04328 * registers. 04329 */ 04330 typedef union _hw_aips_pacrf 04331 { 04332 uint32_t U; 04333 struct _hw_aips_pacrf_bitfields 04334 { 04335 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 04336 uint32_t WP7 : 1; /*!< [1] Write Protect */ 04337 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 04338 uint32_t RESERVED0 : 1; /*!< [3] */ 04339 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 04340 uint32_t WP6 : 1; /*!< [5] Write Protect */ 04341 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 04342 uint32_t RESERVED1 : 1; /*!< [7] */ 04343 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 04344 uint32_t WP5 : 1; /*!< [9] Write Protect */ 04345 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 04346 uint32_t RESERVED2 : 1; /*!< [11] */ 04347 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 04348 uint32_t WP4 : 1; /*!< [13] Write Protect */ 04349 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 04350 uint32_t RESERVED3 : 1; /*!< [15] */ 04351 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 04352 uint32_t WP3 : 1; /*!< [17] Write Protect */ 04353 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 04354 uint32_t RESERVED4 : 1; /*!< [19] */ 04355 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 04356 uint32_t WP2 : 1; /*!< [21] Write Protect */ 04357 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 04358 uint32_t RESERVED5 : 1; /*!< [23] */ 04359 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 04360 uint32_t WP1 : 1; /*!< [25] Write Protect */ 04361 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 04362 uint32_t RESERVED6 : 1; /*!< [27] */ 04363 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 04364 uint32_t WP0 : 1; /*!< [29] Write Protect */ 04365 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 04366 uint32_t RESERVED7 : 1; /*!< [31] */ 04367 } B; 04368 } hw_aips_pacrf_t; 04369 04370 /*! 04371 * @name Constants and macros for entire AIPS_PACRF register 04372 */ 04373 /*@{*/ 04374 #define HW_AIPS_PACRF_ADDR(x) ((x) + 0x44U) 04375 04376 #define HW_AIPS_PACRF(x) (*(__IO hw_aips_pacrf_t *) HW_AIPS_PACRF_ADDR(x)) 04377 #define HW_AIPS_PACRF_RD(x) (ADDRESS_READ(hw_aips_pacrf_t, HW_AIPS_PACRF_ADDR(x))) 04378 #define HW_AIPS_PACRF_WR(x, v) (ADDRESS_WRITE(hw_aips_pacrf_t, HW_AIPS_PACRF_ADDR(x), v)) 04379 #define HW_AIPS_PACRF_SET(x, v) (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) | (v))) 04380 #define HW_AIPS_PACRF_CLR(x, v) (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) & ~(v))) 04381 #define HW_AIPS_PACRF_TOG(x, v) (HW_AIPS_PACRF_WR(x, HW_AIPS_PACRF_RD(x) ^ (v))) 04382 /*@}*/ 04383 04384 /* 04385 * Constants & macros for individual AIPS_PACRF bitfields 04386 */ 04387 04388 /*! 04389 * @name Register AIPS_PACRF, field TP7[0] (RW) 04390 * 04391 * Determines whether the peripheral allows accesses from an untrusted master. 04392 * When this field is set and an access is attempted by an untrusted master, the 04393 * access terminates with an error response and no peripheral access initiates. 04394 * 04395 * Values: 04396 * - 0 - Accesses from an untrusted master are allowed. 04397 * - 1 - Accesses from an untrusted master are not allowed. 04398 */ 04399 /*@{*/ 04400 #define BP_AIPS_PACRF_TP7 (0U) /*!< Bit position for AIPS_PACRF_TP7. */ 04401 #define BM_AIPS_PACRF_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRF_TP7. */ 04402 #define BS_AIPS_PACRF_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP7. */ 04403 04404 /*! @brief Read current value of the AIPS_PACRF_TP7 field. */ 04405 #define BR_AIPS_PACRF_TP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP7))) 04406 04407 /*! @brief Format value for bitfield AIPS_PACRF_TP7. */ 04408 #define BF_AIPS_PACRF_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP7) & BM_AIPS_PACRF_TP7) 04409 04410 /*! @brief Set the TP7 field to a new value. */ 04411 #define BW_AIPS_PACRF_TP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP7), v)) 04412 /*@}*/ 04413 04414 /*! 04415 * @name Register AIPS_PACRF, field WP7[1] (RW) 04416 * 04417 * Determines whether the peripheral allows write accesses. When this field is 04418 * set and a write access is attempted, access terminates with an error response 04419 * and no peripheral access initiates. 04420 * 04421 * Values: 04422 * - 0 - This peripheral allows write accesses. 04423 * - 1 - This peripheral is write protected. 04424 */ 04425 /*@{*/ 04426 #define BP_AIPS_PACRF_WP7 (1U) /*!< Bit position for AIPS_PACRF_WP7. */ 04427 #define BM_AIPS_PACRF_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRF_WP7. */ 04428 #define BS_AIPS_PACRF_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP7. */ 04429 04430 /*! @brief Read current value of the AIPS_PACRF_WP7 field. */ 04431 #define BR_AIPS_PACRF_WP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP7))) 04432 04433 /*! @brief Format value for bitfield AIPS_PACRF_WP7. */ 04434 #define BF_AIPS_PACRF_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP7) & BM_AIPS_PACRF_WP7) 04435 04436 /*! @brief Set the WP7 field to a new value. */ 04437 #define BW_AIPS_PACRF_WP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP7), v)) 04438 /*@}*/ 04439 04440 /*! 04441 * @name Register AIPS_PACRF, field SP7[2] (RW) 04442 * 04443 * Determines whether the peripheral requires supervisor privilege level for 04444 * accesses. When this field is set, the master privilege level must indicate the 04445 * supervisor access attribute, and the MPRx[MPLn] control field for the master 04446 * must be set. If not, access terminates with an error response and no peripheral 04447 * access initiates. 04448 * 04449 * Values: 04450 * - 0 - This peripheral does not require supervisor privilege level for 04451 * accesses. 04452 * - 1 - This peripheral requires supervisor privilege level for accesses. 04453 */ 04454 /*@{*/ 04455 #define BP_AIPS_PACRF_SP7 (2U) /*!< Bit position for AIPS_PACRF_SP7. */ 04456 #define BM_AIPS_PACRF_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRF_SP7. */ 04457 #define BS_AIPS_PACRF_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP7. */ 04458 04459 /*! @brief Read current value of the AIPS_PACRF_SP7 field. */ 04460 #define BR_AIPS_PACRF_SP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP7))) 04461 04462 /*! @brief Format value for bitfield AIPS_PACRF_SP7. */ 04463 #define BF_AIPS_PACRF_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP7) & BM_AIPS_PACRF_SP7) 04464 04465 /*! @brief Set the SP7 field to a new value. */ 04466 #define BW_AIPS_PACRF_SP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP7), v)) 04467 /*@}*/ 04468 04469 /*! 04470 * @name Register AIPS_PACRF, field TP6[4] (RW) 04471 * 04472 * Determines whether the peripheral allows accesses from an untrusted master. 04473 * When this field is set and an access is attempted by an untrusted master, the 04474 * access terminates with an error response and no peripheral access initiates. 04475 * 04476 * Values: 04477 * - 0 - Accesses from an untrusted master are allowed. 04478 * - 1 - Accesses from an untrusted master are not allowed. 04479 */ 04480 /*@{*/ 04481 #define BP_AIPS_PACRF_TP6 (4U) /*!< Bit position for AIPS_PACRF_TP6. */ 04482 #define BM_AIPS_PACRF_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRF_TP6. */ 04483 #define BS_AIPS_PACRF_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP6. */ 04484 04485 /*! @brief Read current value of the AIPS_PACRF_TP6 field. */ 04486 #define BR_AIPS_PACRF_TP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP6))) 04487 04488 /*! @brief Format value for bitfield AIPS_PACRF_TP6. */ 04489 #define BF_AIPS_PACRF_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP6) & BM_AIPS_PACRF_TP6) 04490 04491 /*! @brief Set the TP6 field to a new value. */ 04492 #define BW_AIPS_PACRF_TP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP6), v)) 04493 /*@}*/ 04494 04495 /*! 04496 * @name Register AIPS_PACRF, field WP6[5] (RW) 04497 * 04498 * Determines whether the peripheral allows write accesses. When this field is 04499 * set and a write access is attempted, access terminates with an error response 04500 * and no peripheral access initiates. 04501 * 04502 * Values: 04503 * - 0 - This peripheral allows write accesses. 04504 * - 1 - This peripheral is write protected. 04505 */ 04506 /*@{*/ 04507 #define BP_AIPS_PACRF_WP6 (5U) /*!< Bit position for AIPS_PACRF_WP6. */ 04508 #define BM_AIPS_PACRF_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRF_WP6. */ 04509 #define BS_AIPS_PACRF_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP6. */ 04510 04511 /*! @brief Read current value of the AIPS_PACRF_WP6 field. */ 04512 #define BR_AIPS_PACRF_WP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP6))) 04513 04514 /*! @brief Format value for bitfield AIPS_PACRF_WP6. */ 04515 #define BF_AIPS_PACRF_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP6) & BM_AIPS_PACRF_WP6) 04516 04517 /*! @brief Set the WP6 field to a new value. */ 04518 #define BW_AIPS_PACRF_WP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP6), v)) 04519 /*@}*/ 04520 04521 /*! 04522 * @name Register AIPS_PACRF, field SP6[6] (RW) 04523 * 04524 * Determines whether the peripheral requires supervisor privilege level for 04525 * accesses. When this field is set, the master privilege level must indicate the 04526 * supervisor access attribute, and the MPRx[MPLn] control field for the master 04527 * must be set. If not, access terminates with an error response and no peripheral 04528 * access initiates. 04529 * 04530 * Values: 04531 * - 0 - This peripheral does not require supervisor privilege level for 04532 * accesses. 04533 * - 1 - This peripheral requires supervisor privilege level for accesses. 04534 */ 04535 /*@{*/ 04536 #define BP_AIPS_PACRF_SP6 (6U) /*!< Bit position for AIPS_PACRF_SP6. */ 04537 #define BM_AIPS_PACRF_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRF_SP6. */ 04538 #define BS_AIPS_PACRF_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP6. */ 04539 04540 /*! @brief Read current value of the AIPS_PACRF_SP6 field. */ 04541 #define BR_AIPS_PACRF_SP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP6))) 04542 04543 /*! @brief Format value for bitfield AIPS_PACRF_SP6. */ 04544 #define BF_AIPS_PACRF_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP6) & BM_AIPS_PACRF_SP6) 04545 04546 /*! @brief Set the SP6 field to a new value. */ 04547 #define BW_AIPS_PACRF_SP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP6), v)) 04548 /*@}*/ 04549 04550 /*! 04551 * @name Register AIPS_PACRF, field TP5[8] (RW) 04552 * 04553 * Determines whether the peripheral allows accesses from an untrusted master. 04554 * When this field is set and an access is attempted by an untrusted master, the 04555 * access terminates with an error response and no peripheral access initiates. 04556 * 04557 * Values: 04558 * - 0 - Accesses from an untrusted master are allowed. 04559 * - 1 - Accesses from an untrusted master are not allowed. 04560 */ 04561 /*@{*/ 04562 #define BP_AIPS_PACRF_TP5 (8U) /*!< Bit position for AIPS_PACRF_TP5. */ 04563 #define BM_AIPS_PACRF_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRF_TP5. */ 04564 #define BS_AIPS_PACRF_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP5. */ 04565 04566 /*! @brief Read current value of the AIPS_PACRF_TP5 field. */ 04567 #define BR_AIPS_PACRF_TP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP5))) 04568 04569 /*! @brief Format value for bitfield AIPS_PACRF_TP5. */ 04570 #define BF_AIPS_PACRF_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP5) & BM_AIPS_PACRF_TP5) 04571 04572 /*! @brief Set the TP5 field to a new value. */ 04573 #define BW_AIPS_PACRF_TP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP5), v)) 04574 /*@}*/ 04575 04576 /*! 04577 * @name Register AIPS_PACRF, field WP5[9] (RW) 04578 * 04579 * Determines whether the peripheral allows write accesses. When this field is 04580 * set and a write access is attempted, access terminates with an error response 04581 * and no peripheral access initiates. 04582 * 04583 * Values: 04584 * - 0 - This peripheral allows write accesses. 04585 * - 1 - This peripheral is write protected. 04586 */ 04587 /*@{*/ 04588 #define BP_AIPS_PACRF_WP5 (9U) /*!< Bit position for AIPS_PACRF_WP5. */ 04589 #define BM_AIPS_PACRF_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRF_WP5. */ 04590 #define BS_AIPS_PACRF_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP5. */ 04591 04592 /*! @brief Read current value of the AIPS_PACRF_WP5 field. */ 04593 #define BR_AIPS_PACRF_WP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP5))) 04594 04595 /*! @brief Format value for bitfield AIPS_PACRF_WP5. */ 04596 #define BF_AIPS_PACRF_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP5) & BM_AIPS_PACRF_WP5) 04597 04598 /*! @brief Set the WP5 field to a new value. */ 04599 #define BW_AIPS_PACRF_WP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP5), v)) 04600 /*@}*/ 04601 04602 /*! 04603 * @name Register AIPS_PACRF, field SP5[10] (RW) 04604 * 04605 * Determines whether the peripheral requires supervisor privilege level for 04606 * accesses. When this field is set, the master privilege level must indicate the 04607 * supervisor access attribute, and the MPRx[MPLn] control field for the master 04608 * must be set. If not, access terminates with an error response and no peripheral 04609 * access initiates. 04610 * 04611 * Values: 04612 * - 0 - This peripheral does not require supervisor privilege level for 04613 * accesses. 04614 * - 1 - This peripheral requires supervisor privilege level for accesses. 04615 */ 04616 /*@{*/ 04617 #define BP_AIPS_PACRF_SP5 (10U) /*!< Bit position for AIPS_PACRF_SP5. */ 04618 #define BM_AIPS_PACRF_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRF_SP5. */ 04619 #define BS_AIPS_PACRF_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP5. */ 04620 04621 /*! @brief Read current value of the AIPS_PACRF_SP5 field. */ 04622 #define BR_AIPS_PACRF_SP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP5))) 04623 04624 /*! @brief Format value for bitfield AIPS_PACRF_SP5. */ 04625 #define BF_AIPS_PACRF_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP5) & BM_AIPS_PACRF_SP5) 04626 04627 /*! @brief Set the SP5 field to a new value. */ 04628 #define BW_AIPS_PACRF_SP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP5), v)) 04629 /*@}*/ 04630 04631 /*! 04632 * @name Register AIPS_PACRF, field TP4[12] (RW) 04633 * 04634 * Determines whether the peripheral allows accesses from an untrusted master. 04635 * When this bit is set and an access is attempted by an untrusted master, the 04636 * access terminates with an error response and no peripheral access initiates. 04637 * 04638 * Values: 04639 * - 0 - Accesses from an untrusted master are allowed. 04640 * - 1 - Accesses from an untrusted master are not allowed. 04641 */ 04642 /*@{*/ 04643 #define BP_AIPS_PACRF_TP4 (12U) /*!< Bit position for AIPS_PACRF_TP4. */ 04644 #define BM_AIPS_PACRF_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRF_TP4. */ 04645 #define BS_AIPS_PACRF_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP4. */ 04646 04647 /*! @brief Read current value of the AIPS_PACRF_TP4 field. */ 04648 #define BR_AIPS_PACRF_TP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP4))) 04649 04650 /*! @brief Format value for bitfield AIPS_PACRF_TP4. */ 04651 #define BF_AIPS_PACRF_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP4) & BM_AIPS_PACRF_TP4) 04652 04653 /*! @brief Set the TP4 field to a new value. */ 04654 #define BW_AIPS_PACRF_TP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP4), v)) 04655 /*@}*/ 04656 04657 /*! 04658 * @name Register AIPS_PACRF, field WP4[13] (RW) 04659 * 04660 * Determines whether the peripheral allows write accesses. When this field is 04661 * set and a write access is attempted, access terminates with an error response 04662 * and no peripheral access initiates. 04663 * 04664 * Values: 04665 * - 0 - This peripheral allows write accesses. 04666 * - 1 - This peripheral is write protected. 04667 */ 04668 /*@{*/ 04669 #define BP_AIPS_PACRF_WP4 (13U) /*!< Bit position for AIPS_PACRF_WP4. */ 04670 #define BM_AIPS_PACRF_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRF_WP4. */ 04671 #define BS_AIPS_PACRF_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP4. */ 04672 04673 /*! @brief Read current value of the AIPS_PACRF_WP4 field. */ 04674 #define BR_AIPS_PACRF_WP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP4))) 04675 04676 /*! @brief Format value for bitfield AIPS_PACRF_WP4. */ 04677 #define BF_AIPS_PACRF_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP4) & BM_AIPS_PACRF_WP4) 04678 04679 /*! @brief Set the WP4 field to a new value. */ 04680 #define BW_AIPS_PACRF_WP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP4), v)) 04681 /*@}*/ 04682 04683 /*! 04684 * @name Register AIPS_PACRF, field SP4[14] (RW) 04685 * 04686 * Determines whether the peripheral requires supervisor privilege level for 04687 * access. When this bit is set, the master privilege level must indicate the 04688 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 04689 * set. If not, access terminates with an error response and no peripheral access 04690 * initiates. 04691 * 04692 * Values: 04693 * - 0 - This peripheral does not require supervisor privilege level for 04694 * accesses. 04695 * - 1 - This peripheral requires supervisor privilege level for accesses. 04696 */ 04697 /*@{*/ 04698 #define BP_AIPS_PACRF_SP4 (14U) /*!< Bit position for AIPS_PACRF_SP4. */ 04699 #define BM_AIPS_PACRF_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRF_SP4. */ 04700 #define BS_AIPS_PACRF_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP4. */ 04701 04702 /*! @brief Read current value of the AIPS_PACRF_SP4 field. */ 04703 #define BR_AIPS_PACRF_SP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP4))) 04704 04705 /*! @brief Format value for bitfield AIPS_PACRF_SP4. */ 04706 #define BF_AIPS_PACRF_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP4) & BM_AIPS_PACRF_SP4) 04707 04708 /*! @brief Set the SP4 field to a new value. */ 04709 #define BW_AIPS_PACRF_SP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP4), v)) 04710 /*@}*/ 04711 04712 /*! 04713 * @name Register AIPS_PACRF, field TP3[16] (RW) 04714 * 04715 * Determines whether the peripheral allows accesses from an untrusted master. 04716 * When this field is set and an access is attempted by an untrusted master, the 04717 * access terminates with an error response and no peripheral access initiates. 04718 * 04719 * Values: 04720 * - 0 - Accesses from an untrusted master are allowed. 04721 * - 1 - Accesses from an untrusted master are not allowed. 04722 */ 04723 /*@{*/ 04724 #define BP_AIPS_PACRF_TP3 (16U) /*!< Bit position for AIPS_PACRF_TP3. */ 04725 #define BM_AIPS_PACRF_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRF_TP3. */ 04726 #define BS_AIPS_PACRF_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP3. */ 04727 04728 /*! @brief Read current value of the AIPS_PACRF_TP3 field. */ 04729 #define BR_AIPS_PACRF_TP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP3))) 04730 04731 /*! @brief Format value for bitfield AIPS_PACRF_TP3. */ 04732 #define BF_AIPS_PACRF_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP3) & BM_AIPS_PACRF_TP3) 04733 04734 /*! @brief Set the TP3 field to a new value. */ 04735 #define BW_AIPS_PACRF_TP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP3), v)) 04736 /*@}*/ 04737 04738 /*! 04739 * @name Register AIPS_PACRF, field WP3[17] (RW) 04740 * 04741 * Determines whether the peripheral allows write accesss. When this bit is set 04742 * and a write access is attempted, access terminates with an error response and 04743 * no peripheral access initiates. 04744 * 04745 * Values: 04746 * - 0 - This peripheral allows write accesses. 04747 * - 1 - This peripheral is write protected. 04748 */ 04749 /*@{*/ 04750 #define BP_AIPS_PACRF_WP3 (17U) /*!< Bit position for AIPS_PACRF_WP3. */ 04751 #define BM_AIPS_PACRF_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRF_WP3. */ 04752 #define BS_AIPS_PACRF_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP3. */ 04753 04754 /*! @brief Read current value of the AIPS_PACRF_WP3 field. */ 04755 #define BR_AIPS_PACRF_WP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP3))) 04756 04757 /*! @brief Format value for bitfield AIPS_PACRF_WP3. */ 04758 #define BF_AIPS_PACRF_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP3) & BM_AIPS_PACRF_WP3) 04759 04760 /*! @brief Set the WP3 field to a new value. */ 04761 #define BW_AIPS_PACRF_WP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP3), v)) 04762 /*@}*/ 04763 04764 /*! 04765 * @name Register AIPS_PACRF, field SP3[18] (RW) 04766 * 04767 * Determines whether the peripheral requires supervisor privilege level for 04768 * accesses. When this field is set, the master privilege level must indicate the 04769 * supervisor access attribute, and the MPRx[MPLn] control field for the master 04770 * must be set. If not, access terminates with an error response and no peripheral 04771 * access initiates. 04772 * 04773 * Values: 04774 * - 0 - This peripheral does not require supervisor privilege level for 04775 * accesses. 04776 * - 1 - This peripheral requires supervisor privilege level for accesses. 04777 */ 04778 /*@{*/ 04779 #define BP_AIPS_PACRF_SP3 (18U) /*!< Bit position for AIPS_PACRF_SP3. */ 04780 #define BM_AIPS_PACRF_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRF_SP3. */ 04781 #define BS_AIPS_PACRF_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP3. */ 04782 04783 /*! @brief Read current value of the AIPS_PACRF_SP3 field. */ 04784 #define BR_AIPS_PACRF_SP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP3))) 04785 04786 /*! @brief Format value for bitfield AIPS_PACRF_SP3. */ 04787 #define BF_AIPS_PACRF_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP3) & BM_AIPS_PACRF_SP3) 04788 04789 /*! @brief Set the SP3 field to a new value. */ 04790 #define BW_AIPS_PACRF_SP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP3), v)) 04791 /*@}*/ 04792 04793 /*! 04794 * @name Register AIPS_PACRF, field TP2[20] (RW) 04795 * 04796 * Determines whether the peripheral allows accesses from an untrusted master. 04797 * When this bit is set and an access is attempted by an untrusted master, the 04798 * access terminates with an error response and no peripheral access initiates. 04799 * 04800 * Values: 04801 * - 0 - Accesses from an untrusted master are allowed. 04802 * - 1 - Accesses from an untrusted master are not allowed. 04803 */ 04804 /*@{*/ 04805 #define BP_AIPS_PACRF_TP2 (20U) /*!< Bit position for AIPS_PACRF_TP2. */ 04806 #define BM_AIPS_PACRF_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRF_TP2. */ 04807 #define BS_AIPS_PACRF_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP2. */ 04808 04809 /*! @brief Read current value of the AIPS_PACRF_TP2 field. */ 04810 #define BR_AIPS_PACRF_TP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP2))) 04811 04812 /*! @brief Format value for bitfield AIPS_PACRF_TP2. */ 04813 #define BF_AIPS_PACRF_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP2) & BM_AIPS_PACRF_TP2) 04814 04815 /*! @brief Set the TP2 field to a new value. */ 04816 #define BW_AIPS_PACRF_TP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP2), v)) 04817 /*@}*/ 04818 04819 /*! 04820 * @name Register AIPS_PACRF, field WP2[21] (RW) 04821 * 04822 * Determines whether the peripheral allows write accesses. When this field is 04823 * set and a write access is attempted, access terminates with an error response 04824 * and no peripheral access initiates. 04825 * 04826 * Values: 04827 * - 0 - This peripheral allows write accesses. 04828 * - 1 - This peripheral is write protected. 04829 */ 04830 /*@{*/ 04831 #define BP_AIPS_PACRF_WP2 (21U) /*!< Bit position for AIPS_PACRF_WP2. */ 04832 #define BM_AIPS_PACRF_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRF_WP2. */ 04833 #define BS_AIPS_PACRF_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP2. */ 04834 04835 /*! @brief Read current value of the AIPS_PACRF_WP2 field. */ 04836 #define BR_AIPS_PACRF_WP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP2))) 04837 04838 /*! @brief Format value for bitfield AIPS_PACRF_WP2. */ 04839 #define BF_AIPS_PACRF_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP2) & BM_AIPS_PACRF_WP2) 04840 04841 /*! @brief Set the WP2 field to a new value. */ 04842 #define BW_AIPS_PACRF_WP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP2), v)) 04843 /*@}*/ 04844 04845 /*! 04846 * @name Register AIPS_PACRF, field SP2[22] (RW) 04847 * 04848 * Determines whether the peripheral requires supervisor privilege level for 04849 * access. When this bit is set, the master privilege level must indicate the 04850 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 04851 * set. If not, access terminates with an error response and no peripheral access 04852 * initiates. 04853 * 04854 * Values: 04855 * - 0 - This peripheral does not require supervisor privilege level for 04856 * accesses. 04857 * - 1 - This peripheral requires supervisor privilege level for accesses. 04858 */ 04859 /*@{*/ 04860 #define BP_AIPS_PACRF_SP2 (22U) /*!< Bit position for AIPS_PACRF_SP2. */ 04861 #define BM_AIPS_PACRF_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRF_SP2. */ 04862 #define BS_AIPS_PACRF_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP2. */ 04863 04864 /*! @brief Read current value of the AIPS_PACRF_SP2 field. */ 04865 #define BR_AIPS_PACRF_SP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP2))) 04866 04867 /*! @brief Format value for bitfield AIPS_PACRF_SP2. */ 04868 #define BF_AIPS_PACRF_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP2) & BM_AIPS_PACRF_SP2) 04869 04870 /*! @brief Set the SP2 field to a new value. */ 04871 #define BW_AIPS_PACRF_SP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP2), v)) 04872 /*@}*/ 04873 04874 /*! 04875 * @name Register AIPS_PACRF, field TP1[24] (RW) 04876 * 04877 * Determines whether the peripheral allows accesses from an untrusted master. 04878 * When this field is set and an access is attempted by an untrusted master, the 04879 * access terminates with an error response and no peripheral access initiates. 04880 * 04881 * Values: 04882 * - 0 - Accesses from an untrusted master are allowed. 04883 * - 1 - Accesses from an untrusted master are not allowed. 04884 */ 04885 /*@{*/ 04886 #define BP_AIPS_PACRF_TP1 (24U) /*!< Bit position for AIPS_PACRF_TP1. */ 04887 #define BM_AIPS_PACRF_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRF_TP1. */ 04888 #define BS_AIPS_PACRF_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP1. */ 04889 04890 /*! @brief Read current value of the AIPS_PACRF_TP1 field. */ 04891 #define BR_AIPS_PACRF_TP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP1))) 04892 04893 /*! @brief Format value for bitfield AIPS_PACRF_TP1. */ 04894 #define BF_AIPS_PACRF_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP1) & BM_AIPS_PACRF_TP1) 04895 04896 /*! @brief Set the TP1 field to a new value. */ 04897 #define BW_AIPS_PACRF_TP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP1), v)) 04898 /*@}*/ 04899 04900 /*! 04901 * @name Register AIPS_PACRF, field WP1[25] (RW) 04902 * 04903 * Determines whether the peripheral allows write accesses. When this field is 04904 * set and a write access is attempted, access terminates with an error response 04905 * and no peripheral access initiates. 04906 * 04907 * Values: 04908 * - 0 - This peripheral allows write accesses. 04909 * - 1 - This peripheral is write protected. 04910 */ 04911 /*@{*/ 04912 #define BP_AIPS_PACRF_WP1 (25U) /*!< Bit position for AIPS_PACRF_WP1. */ 04913 #define BM_AIPS_PACRF_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRF_WP1. */ 04914 #define BS_AIPS_PACRF_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP1. */ 04915 04916 /*! @brief Read current value of the AIPS_PACRF_WP1 field. */ 04917 #define BR_AIPS_PACRF_WP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP1))) 04918 04919 /*! @brief Format value for bitfield AIPS_PACRF_WP1. */ 04920 #define BF_AIPS_PACRF_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP1) & BM_AIPS_PACRF_WP1) 04921 04922 /*! @brief Set the WP1 field to a new value. */ 04923 #define BW_AIPS_PACRF_WP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP1), v)) 04924 /*@}*/ 04925 04926 /*! 04927 * @name Register AIPS_PACRF, field SP1[26] (RW) 04928 * 04929 * Determines whether the peripheral requires supervisor privilege level for 04930 * access. When this field is set, the master privilege level must indicate the 04931 * supervisor access attribute, and the MPRx[MPLn] control field for the master must 04932 * be set. If not, access terminates with an error response and no peripheral 04933 * access initiates. 04934 * 04935 * Values: 04936 * - 0 - This peripheral does not require supervisor privilege level for 04937 * accesses. 04938 * - 1 - This peripheral requires supervisor privilege level for accesses. 04939 */ 04940 /*@{*/ 04941 #define BP_AIPS_PACRF_SP1 (26U) /*!< Bit position for AIPS_PACRF_SP1. */ 04942 #define BM_AIPS_PACRF_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRF_SP1. */ 04943 #define BS_AIPS_PACRF_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP1. */ 04944 04945 /*! @brief Read current value of the AIPS_PACRF_SP1 field. */ 04946 #define BR_AIPS_PACRF_SP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP1))) 04947 04948 /*! @brief Format value for bitfield AIPS_PACRF_SP1. */ 04949 #define BF_AIPS_PACRF_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP1) & BM_AIPS_PACRF_SP1) 04950 04951 /*! @brief Set the SP1 field to a new value. */ 04952 #define BW_AIPS_PACRF_SP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP1), v)) 04953 /*@}*/ 04954 04955 /*! 04956 * @name Register AIPS_PACRF, field TP0[28] (RW) 04957 * 04958 * Determines whether the peripheral allows accesses from an untrusted master. 04959 * When this bit is set and an access is attempted by an untrusted master, the 04960 * access terminates with an error response and no peripheral access initiates. 04961 * 04962 * Values: 04963 * - 0 - Accesses from an untrusted master are allowed. 04964 * - 1 - Accesses from an untrusted master are not allowed. 04965 */ 04966 /*@{*/ 04967 #define BP_AIPS_PACRF_TP0 (28U) /*!< Bit position for AIPS_PACRF_TP0. */ 04968 #define BM_AIPS_PACRF_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRF_TP0. */ 04969 #define BS_AIPS_PACRF_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRF_TP0. */ 04970 04971 /*! @brief Read current value of the AIPS_PACRF_TP0 field. */ 04972 #define BR_AIPS_PACRF_TP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP0))) 04973 04974 /*! @brief Format value for bitfield AIPS_PACRF_TP0. */ 04975 #define BF_AIPS_PACRF_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_TP0) & BM_AIPS_PACRF_TP0) 04976 04977 /*! @brief Set the TP0 field to a new value. */ 04978 #define BW_AIPS_PACRF_TP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_TP0), v)) 04979 /*@}*/ 04980 04981 /*! 04982 * @name Register AIPS_PACRF, field WP0[29] (RW) 04983 * 04984 * Determines whether the peripheral allows write accesses. When this field is 04985 * set and a write access is attempted, access terminates with an error response 04986 * and no peripheral access initiates. 04987 * 04988 * Values: 04989 * - 0 - This peripheral allows write accesses. 04990 * - 1 - This peripheral is write protected. 04991 */ 04992 /*@{*/ 04993 #define BP_AIPS_PACRF_WP0 (29U) /*!< Bit position for AIPS_PACRF_WP0. */ 04994 #define BM_AIPS_PACRF_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRF_WP0. */ 04995 #define BS_AIPS_PACRF_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRF_WP0. */ 04996 04997 /*! @brief Read current value of the AIPS_PACRF_WP0 field. */ 04998 #define BR_AIPS_PACRF_WP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP0))) 04999 05000 /*! @brief Format value for bitfield AIPS_PACRF_WP0. */ 05001 #define BF_AIPS_PACRF_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_WP0) & BM_AIPS_PACRF_WP0) 05002 05003 /*! @brief Set the WP0 field to a new value. */ 05004 #define BW_AIPS_PACRF_WP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_WP0), v)) 05005 /*@}*/ 05006 05007 /*! 05008 * @name Register AIPS_PACRF, field SP0[30] (RW) 05009 * 05010 * Determines whether the peripheral requires supervisor privilege level for 05011 * accesses. When this field is set, the master privilege level must indicate the 05012 * supervisor access attribute, and the MPRx[MPLn] control field for the master 05013 * must be set. If not, access terminates with an error response and no peripheral 05014 * access initiates. 05015 * 05016 * Values: 05017 * - 0 - This peripheral does not require supervisor privilege level for 05018 * accesses. 05019 * - 1 - This peripheral requires supervisor privilege level for accesses. 05020 */ 05021 /*@{*/ 05022 #define BP_AIPS_PACRF_SP0 (30U) /*!< Bit position for AIPS_PACRF_SP0. */ 05023 #define BM_AIPS_PACRF_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRF_SP0. */ 05024 #define BS_AIPS_PACRF_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRF_SP0. */ 05025 05026 /*! @brief Read current value of the AIPS_PACRF_SP0 field. */ 05027 #define BR_AIPS_PACRF_SP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP0))) 05028 05029 /*! @brief Format value for bitfield AIPS_PACRF_SP0. */ 05030 #define BF_AIPS_PACRF_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRF_SP0) & BM_AIPS_PACRF_SP0) 05031 05032 /*! @brief Set the SP0 field to a new value. */ 05033 #define BW_AIPS_PACRF_SP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRF_ADDR(x), BP_AIPS_PACRF_SP0), v)) 05034 /*@}*/ 05035 05036 /******************************************************************************* 05037 * HW_AIPS_PACRG - Peripheral Access Control Register 05038 ******************************************************************************/ 05039 05040 /*! 05041 * @brief HW_AIPS_PACRG - Peripheral Access Control Register (RW) 05042 * 05043 * Reset value: 0x44444444U 05044 * 05045 * This section describes PACR registers E-P, which control peripheral slots 05046 * 32-127. See PACRPeripheral Access Control Register for the description of these 05047 * registers. 05048 */ 05049 typedef union _hw_aips_pacrg 05050 { 05051 uint32_t U; 05052 struct _hw_aips_pacrg_bitfields 05053 { 05054 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 05055 uint32_t WP7 : 1; /*!< [1] Write Protect */ 05056 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 05057 uint32_t RESERVED0 : 1; /*!< [3] */ 05058 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 05059 uint32_t WP6 : 1; /*!< [5] Write Protect */ 05060 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 05061 uint32_t RESERVED1 : 1; /*!< [7] */ 05062 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 05063 uint32_t WP5 : 1; /*!< [9] Write Protect */ 05064 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 05065 uint32_t RESERVED2 : 1; /*!< [11] */ 05066 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 05067 uint32_t WP4 : 1; /*!< [13] Write Protect */ 05068 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 05069 uint32_t RESERVED3 : 1; /*!< [15] */ 05070 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 05071 uint32_t WP3 : 1; /*!< [17] Write Protect */ 05072 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 05073 uint32_t RESERVED4 : 1; /*!< [19] */ 05074 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 05075 uint32_t WP2 : 1; /*!< [21] Write Protect */ 05076 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 05077 uint32_t RESERVED5 : 1; /*!< [23] */ 05078 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 05079 uint32_t WP1 : 1; /*!< [25] Write Protect */ 05080 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 05081 uint32_t RESERVED6 : 1; /*!< [27] */ 05082 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 05083 uint32_t WP0 : 1; /*!< [29] Write Protect */ 05084 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 05085 uint32_t RESERVED7 : 1; /*!< [31] */ 05086 } B; 05087 } hw_aips_pacrg_t; 05088 05089 /*! 05090 * @name Constants and macros for entire AIPS_PACRG register 05091 */ 05092 /*@{*/ 05093 #define HW_AIPS_PACRG_ADDR(x) ((x) + 0x48U) 05094 05095 #define HW_AIPS_PACRG(x) (*(__IO hw_aips_pacrg_t *) HW_AIPS_PACRG_ADDR(x)) 05096 #define HW_AIPS_PACRG_RD(x) (ADDRESS_READ(hw_aips_pacrg_t, HW_AIPS_PACRG_ADDR(x))) 05097 #define HW_AIPS_PACRG_WR(x, v) (ADDRESS_WRITE(hw_aips_pacrg_t, HW_AIPS_PACRG_ADDR(x), v)) 05098 #define HW_AIPS_PACRG_SET(x, v) (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) | (v))) 05099 #define HW_AIPS_PACRG_CLR(x, v) (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) & ~(v))) 05100 #define HW_AIPS_PACRG_TOG(x, v) (HW_AIPS_PACRG_WR(x, HW_AIPS_PACRG_RD(x) ^ (v))) 05101 /*@}*/ 05102 05103 /* 05104 * Constants & macros for individual AIPS_PACRG bitfields 05105 */ 05106 05107 /*! 05108 * @name Register AIPS_PACRG, field TP7[0] (RW) 05109 * 05110 * Determines whether the peripheral allows accesses from an untrusted master. 05111 * When this field is set and an access is attempted by an untrusted master, the 05112 * access terminates with an error response and no peripheral access initiates. 05113 * 05114 * Values: 05115 * - 0 - Accesses from an untrusted master are allowed. 05116 * - 1 - Accesses from an untrusted master are not allowed. 05117 */ 05118 /*@{*/ 05119 #define BP_AIPS_PACRG_TP7 (0U) /*!< Bit position for AIPS_PACRG_TP7. */ 05120 #define BM_AIPS_PACRG_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRG_TP7. */ 05121 #define BS_AIPS_PACRG_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP7. */ 05122 05123 /*! @brief Read current value of the AIPS_PACRG_TP7 field. */ 05124 #define BR_AIPS_PACRG_TP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP7))) 05125 05126 /*! @brief Format value for bitfield AIPS_PACRG_TP7. */ 05127 #define BF_AIPS_PACRG_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP7) & BM_AIPS_PACRG_TP7) 05128 05129 /*! @brief Set the TP7 field to a new value. */ 05130 #define BW_AIPS_PACRG_TP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP7), v)) 05131 /*@}*/ 05132 05133 /*! 05134 * @name Register AIPS_PACRG, field WP7[1] (RW) 05135 * 05136 * Determines whether the peripheral allows write accesses. When this field is 05137 * set and a write access is attempted, access terminates with an error response 05138 * and no peripheral access initiates. 05139 * 05140 * Values: 05141 * - 0 - This peripheral allows write accesses. 05142 * - 1 - This peripheral is write protected. 05143 */ 05144 /*@{*/ 05145 #define BP_AIPS_PACRG_WP7 (1U) /*!< Bit position for AIPS_PACRG_WP7. */ 05146 #define BM_AIPS_PACRG_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRG_WP7. */ 05147 #define BS_AIPS_PACRG_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP7. */ 05148 05149 /*! @brief Read current value of the AIPS_PACRG_WP7 field. */ 05150 #define BR_AIPS_PACRG_WP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP7))) 05151 05152 /*! @brief Format value for bitfield AIPS_PACRG_WP7. */ 05153 #define BF_AIPS_PACRG_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP7) & BM_AIPS_PACRG_WP7) 05154 05155 /*! @brief Set the WP7 field to a new value. */ 05156 #define BW_AIPS_PACRG_WP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP7), v)) 05157 /*@}*/ 05158 05159 /*! 05160 * @name Register AIPS_PACRG, field SP7[2] (RW) 05161 * 05162 * Determines whether the peripheral requires supervisor privilege level for 05163 * accesses. When this field is set, the master privilege level must indicate the 05164 * supervisor access attribute, and the MPRx[MPLn] control field for the master 05165 * must be set. If not, access terminates with an error response and no peripheral 05166 * access initiates. 05167 * 05168 * Values: 05169 * - 0 - This peripheral does not require supervisor privilege level for 05170 * accesses. 05171 * - 1 - This peripheral requires supervisor privilege level for accesses. 05172 */ 05173 /*@{*/ 05174 #define BP_AIPS_PACRG_SP7 (2U) /*!< Bit position for AIPS_PACRG_SP7. */ 05175 #define BM_AIPS_PACRG_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRG_SP7. */ 05176 #define BS_AIPS_PACRG_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP7. */ 05177 05178 /*! @brief Read current value of the AIPS_PACRG_SP7 field. */ 05179 #define BR_AIPS_PACRG_SP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP7))) 05180 05181 /*! @brief Format value for bitfield AIPS_PACRG_SP7. */ 05182 #define BF_AIPS_PACRG_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP7) & BM_AIPS_PACRG_SP7) 05183 05184 /*! @brief Set the SP7 field to a new value. */ 05185 #define BW_AIPS_PACRG_SP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP7), v)) 05186 /*@}*/ 05187 05188 /*! 05189 * @name Register AIPS_PACRG, field TP6[4] (RW) 05190 * 05191 * Determines whether the peripheral allows accesses from an untrusted master. 05192 * When this field is set and an access is attempted by an untrusted master, the 05193 * access terminates with an error response and no peripheral access initiates. 05194 * 05195 * Values: 05196 * - 0 - Accesses from an untrusted master are allowed. 05197 * - 1 - Accesses from an untrusted master are not allowed. 05198 */ 05199 /*@{*/ 05200 #define BP_AIPS_PACRG_TP6 (4U) /*!< Bit position for AIPS_PACRG_TP6. */ 05201 #define BM_AIPS_PACRG_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRG_TP6. */ 05202 #define BS_AIPS_PACRG_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP6. */ 05203 05204 /*! @brief Read current value of the AIPS_PACRG_TP6 field. */ 05205 #define BR_AIPS_PACRG_TP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP6))) 05206 05207 /*! @brief Format value for bitfield AIPS_PACRG_TP6. */ 05208 #define BF_AIPS_PACRG_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP6) & BM_AIPS_PACRG_TP6) 05209 05210 /*! @brief Set the TP6 field to a new value. */ 05211 #define BW_AIPS_PACRG_TP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP6), v)) 05212 /*@}*/ 05213 05214 /*! 05215 * @name Register AIPS_PACRG, field WP6[5] (RW) 05216 * 05217 * Determines whether the peripheral allows write accesses. When this field is 05218 * set and a write access is attempted, access terminates with an error response 05219 * and no peripheral access initiates. 05220 * 05221 * Values: 05222 * - 0 - This peripheral allows write accesses. 05223 * - 1 - This peripheral is write protected. 05224 */ 05225 /*@{*/ 05226 #define BP_AIPS_PACRG_WP6 (5U) /*!< Bit position for AIPS_PACRG_WP6. */ 05227 #define BM_AIPS_PACRG_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRG_WP6. */ 05228 #define BS_AIPS_PACRG_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP6. */ 05229 05230 /*! @brief Read current value of the AIPS_PACRG_WP6 field. */ 05231 #define BR_AIPS_PACRG_WP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP6))) 05232 05233 /*! @brief Format value for bitfield AIPS_PACRG_WP6. */ 05234 #define BF_AIPS_PACRG_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP6) & BM_AIPS_PACRG_WP6) 05235 05236 /*! @brief Set the WP6 field to a new value. */ 05237 #define BW_AIPS_PACRG_WP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP6), v)) 05238 /*@}*/ 05239 05240 /*! 05241 * @name Register AIPS_PACRG, field SP6[6] (RW) 05242 * 05243 * Determines whether the peripheral requires supervisor privilege level for 05244 * accesses. When this field is set, the master privilege level must indicate the 05245 * supervisor access attribute, and the MPRx[MPLn] control field for the master 05246 * must be set. If not, access terminates with an error response and no peripheral 05247 * access initiates. 05248 * 05249 * Values: 05250 * - 0 - This peripheral does not require supervisor privilege level for 05251 * accesses. 05252 * - 1 - This peripheral requires supervisor privilege level for accesses. 05253 */ 05254 /*@{*/ 05255 #define BP_AIPS_PACRG_SP6 (6U) /*!< Bit position for AIPS_PACRG_SP6. */ 05256 #define BM_AIPS_PACRG_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRG_SP6. */ 05257 #define BS_AIPS_PACRG_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP6. */ 05258 05259 /*! @brief Read current value of the AIPS_PACRG_SP6 field. */ 05260 #define BR_AIPS_PACRG_SP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP6))) 05261 05262 /*! @brief Format value for bitfield AIPS_PACRG_SP6. */ 05263 #define BF_AIPS_PACRG_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP6) & BM_AIPS_PACRG_SP6) 05264 05265 /*! @brief Set the SP6 field to a new value. */ 05266 #define BW_AIPS_PACRG_SP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP6), v)) 05267 /*@}*/ 05268 05269 /*! 05270 * @name Register AIPS_PACRG, field TP5[8] (RW) 05271 * 05272 * Determines whether the peripheral allows accesses from an untrusted master. 05273 * When this field is set and an access is attempted by an untrusted master, the 05274 * access terminates with an error response and no peripheral access initiates. 05275 * 05276 * Values: 05277 * - 0 - Accesses from an untrusted master are allowed. 05278 * - 1 - Accesses from an untrusted master are not allowed. 05279 */ 05280 /*@{*/ 05281 #define BP_AIPS_PACRG_TP5 (8U) /*!< Bit position for AIPS_PACRG_TP5. */ 05282 #define BM_AIPS_PACRG_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRG_TP5. */ 05283 #define BS_AIPS_PACRG_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP5. */ 05284 05285 /*! @brief Read current value of the AIPS_PACRG_TP5 field. */ 05286 #define BR_AIPS_PACRG_TP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP5))) 05287 05288 /*! @brief Format value for bitfield AIPS_PACRG_TP5. */ 05289 #define BF_AIPS_PACRG_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP5) & BM_AIPS_PACRG_TP5) 05290 05291 /*! @brief Set the TP5 field to a new value. */ 05292 #define BW_AIPS_PACRG_TP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP5), v)) 05293 /*@}*/ 05294 05295 /*! 05296 * @name Register AIPS_PACRG, field WP5[9] (RW) 05297 * 05298 * Determines whether the peripheral allows write accesses. When this field is 05299 * set and a write access is attempted, access terminates with an error response 05300 * and no peripheral access initiates. 05301 * 05302 * Values: 05303 * - 0 - This peripheral allows write accesses. 05304 * - 1 - This peripheral is write protected. 05305 */ 05306 /*@{*/ 05307 #define BP_AIPS_PACRG_WP5 (9U) /*!< Bit position for AIPS_PACRG_WP5. */ 05308 #define BM_AIPS_PACRG_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRG_WP5. */ 05309 #define BS_AIPS_PACRG_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP5. */ 05310 05311 /*! @brief Read current value of the AIPS_PACRG_WP5 field. */ 05312 #define BR_AIPS_PACRG_WP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP5))) 05313 05314 /*! @brief Format value for bitfield AIPS_PACRG_WP5. */ 05315 #define BF_AIPS_PACRG_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP5) & BM_AIPS_PACRG_WP5) 05316 05317 /*! @brief Set the WP5 field to a new value. */ 05318 #define BW_AIPS_PACRG_WP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP5), v)) 05319 /*@}*/ 05320 05321 /*! 05322 * @name Register AIPS_PACRG, field SP5[10] (RW) 05323 * 05324 * Determines whether the peripheral requires supervisor privilege level for 05325 * accesses. When this field is set, the master privilege level must indicate the 05326 * supervisor access attribute, and the MPRx[MPLn] control field for the master 05327 * must be set. If not, access terminates with an error response and no peripheral 05328 * access initiates. 05329 * 05330 * Values: 05331 * - 0 - This peripheral does not require supervisor privilege level for 05332 * accesses. 05333 * - 1 - This peripheral requires supervisor privilege level for accesses. 05334 */ 05335 /*@{*/ 05336 #define BP_AIPS_PACRG_SP5 (10U) /*!< Bit position for AIPS_PACRG_SP5. */ 05337 #define BM_AIPS_PACRG_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRG_SP5. */ 05338 #define BS_AIPS_PACRG_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP5. */ 05339 05340 /*! @brief Read current value of the AIPS_PACRG_SP5 field. */ 05341 #define BR_AIPS_PACRG_SP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP5))) 05342 05343 /*! @brief Format value for bitfield AIPS_PACRG_SP5. */ 05344 #define BF_AIPS_PACRG_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP5) & BM_AIPS_PACRG_SP5) 05345 05346 /*! @brief Set the SP5 field to a new value. */ 05347 #define BW_AIPS_PACRG_SP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP5), v)) 05348 /*@}*/ 05349 05350 /*! 05351 * @name Register AIPS_PACRG, field TP4[12] (RW) 05352 * 05353 * Determines whether the peripheral allows accesses from an untrusted master. 05354 * When this bit is set and an access is attempted by an untrusted master, the 05355 * access terminates with an error response and no peripheral access initiates. 05356 * 05357 * Values: 05358 * - 0 - Accesses from an untrusted master are allowed. 05359 * - 1 - Accesses from an untrusted master are not allowed. 05360 */ 05361 /*@{*/ 05362 #define BP_AIPS_PACRG_TP4 (12U) /*!< Bit position for AIPS_PACRG_TP4. */ 05363 #define BM_AIPS_PACRG_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRG_TP4. */ 05364 #define BS_AIPS_PACRG_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP4. */ 05365 05366 /*! @brief Read current value of the AIPS_PACRG_TP4 field. */ 05367 #define BR_AIPS_PACRG_TP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP4))) 05368 05369 /*! @brief Format value for bitfield AIPS_PACRG_TP4. */ 05370 #define BF_AIPS_PACRG_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP4) & BM_AIPS_PACRG_TP4) 05371 05372 /*! @brief Set the TP4 field to a new value. */ 05373 #define BW_AIPS_PACRG_TP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP4), v)) 05374 /*@}*/ 05375 05376 /*! 05377 * @name Register AIPS_PACRG, field WP4[13] (RW) 05378 * 05379 * Determines whether the peripheral allows write accesses. When this field is 05380 * set and a write access is attempted, access terminates with an error response 05381 * and no peripheral access initiates. 05382 * 05383 * Values: 05384 * - 0 - This peripheral allows write accesses. 05385 * - 1 - This peripheral is write protected. 05386 */ 05387 /*@{*/ 05388 #define BP_AIPS_PACRG_WP4 (13U) /*!< Bit position for AIPS_PACRG_WP4. */ 05389 #define BM_AIPS_PACRG_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRG_WP4. */ 05390 #define BS_AIPS_PACRG_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP4. */ 05391 05392 /*! @brief Read current value of the AIPS_PACRG_WP4 field. */ 05393 #define BR_AIPS_PACRG_WP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP4))) 05394 05395 /*! @brief Format value for bitfield AIPS_PACRG_WP4. */ 05396 #define BF_AIPS_PACRG_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP4) & BM_AIPS_PACRG_WP4) 05397 05398 /*! @brief Set the WP4 field to a new value. */ 05399 #define BW_AIPS_PACRG_WP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP4), v)) 05400 /*@}*/ 05401 05402 /*! 05403 * @name Register AIPS_PACRG, field SP4[14] (RW) 05404 * 05405 * Determines whether the peripheral requires supervisor privilege level for 05406 * access. When this bit is set, the master privilege level must indicate the 05407 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 05408 * set. If not, access terminates with an error response and no peripheral access 05409 * initiates. 05410 * 05411 * Values: 05412 * - 0 - This peripheral does not require supervisor privilege level for 05413 * accesses. 05414 * - 1 - This peripheral requires supervisor privilege level for accesses. 05415 */ 05416 /*@{*/ 05417 #define BP_AIPS_PACRG_SP4 (14U) /*!< Bit position for AIPS_PACRG_SP4. */ 05418 #define BM_AIPS_PACRG_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRG_SP4. */ 05419 #define BS_AIPS_PACRG_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP4. */ 05420 05421 /*! @brief Read current value of the AIPS_PACRG_SP4 field. */ 05422 #define BR_AIPS_PACRG_SP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP4))) 05423 05424 /*! @brief Format value for bitfield AIPS_PACRG_SP4. */ 05425 #define BF_AIPS_PACRG_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP4) & BM_AIPS_PACRG_SP4) 05426 05427 /*! @brief Set the SP4 field to a new value. */ 05428 #define BW_AIPS_PACRG_SP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP4), v)) 05429 /*@}*/ 05430 05431 /*! 05432 * @name Register AIPS_PACRG, field TP3[16] (RW) 05433 * 05434 * Determines whether the peripheral allows accesses from an untrusted master. 05435 * When this field is set and an access is attempted by an untrusted master, the 05436 * access terminates with an error response and no peripheral access initiates. 05437 * 05438 * Values: 05439 * - 0 - Accesses from an untrusted master are allowed. 05440 * - 1 - Accesses from an untrusted master are not allowed. 05441 */ 05442 /*@{*/ 05443 #define BP_AIPS_PACRG_TP3 (16U) /*!< Bit position for AIPS_PACRG_TP3. */ 05444 #define BM_AIPS_PACRG_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRG_TP3. */ 05445 #define BS_AIPS_PACRG_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP3. */ 05446 05447 /*! @brief Read current value of the AIPS_PACRG_TP3 field. */ 05448 #define BR_AIPS_PACRG_TP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP3))) 05449 05450 /*! @brief Format value for bitfield AIPS_PACRG_TP3. */ 05451 #define BF_AIPS_PACRG_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP3) & BM_AIPS_PACRG_TP3) 05452 05453 /*! @brief Set the TP3 field to a new value. */ 05454 #define BW_AIPS_PACRG_TP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP3), v)) 05455 /*@}*/ 05456 05457 /*! 05458 * @name Register AIPS_PACRG, field WP3[17] (RW) 05459 * 05460 * Determines whether the peripheral allows write accesss. When this bit is set 05461 * and a write access is attempted, access terminates with an error response and 05462 * no peripheral access initiates. 05463 * 05464 * Values: 05465 * - 0 - This peripheral allows write accesses. 05466 * - 1 - This peripheral is write protected. 05467 */ 05468 /*@{*/ 05469 #define BP_AIPS_PACRG_WP3 (17U) /*!< Bit position for AIPS_PACRG_WP3. */ 05470 #define BM_AIPS_PACRG_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRG_WP3. */ 05471 #define BS_AIPS_PACRG_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP3. */ 05472 05473 /*! @brief Read current value of the AIPS_PACRG_WP3 field. */ 05474 #define BR_AIPS_PACRG_WP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP3))) 05475 05476 /*! @brief Format value for bitfield AIPS_PACRG_WP3. */ 05477 #define BF_AIPS_PACRG_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP3) & BM_AIPS_PACRG_WP3) 05478 05479 /*! @brief Set the WP3 field to a new value. */ 05480 #define BW_AIPS_PACRG_WP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP3), v)) 05481 /*@}*/ 05482 05483 /*! 05484 * @name Register AIPS_PACRG, field SP3[18] (RW) 05485 * 05486 * Determines whether the peripheral requires supervisor privilege level for 05487 * accesses. When this field is set, the master privilege level must indicate the 05488 * supervisor access attribute, and the MPRx[MPLn] control field for the master 05489 * must be set. If not, access terminates with an error response and no peripheral 05490 * access initiates. 05491 * 05492 * Values: 05493 * - 0 - This peripheral does not require supervisor privilege level for 05494 * accesses. 05495 * - 1 - This peripheral requires supervisor privilege level for accesses. 05496 */ 05497 /*@{*/ 05498 #define BP_AIPS_PACRG_SP3 (18U) /*!< Bit position for AIPS_PACRG_SP3. */ 05499 #define BM_AIPS_PACRG_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRG_SP3. */ 05500 #define BS_AIPS_PACRG_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP3. */ 05501 05502 /*! @brief Read current value of the AIPS_PACRG_SP3 field. */ 05503 #define BR_AIPS_PACRG_SP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP3))) 05504 05505 /*! @brief Format value for bitfield AIPS_PACRG_SP3. */ 05506 #define BF_AIPS_PACRG_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP3) & BM_AIPS_PACRG_SP3) 05507 05508 /*! @brief Set the SP3 field to a new value. */ 05509 #define BW_AIPS_PACRG_SP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP3), v)) 05510 /*@}*/ 05511 05512 /*! 05513 * @name Register AIPS_PACRG, field TP2[20] (RW) 05514 * 05515 * Determines whether the peripheral allows accesses from an untrusted master. 05516 * When this bit is set and an access is attempted by an untrusted master, the 05517 * access terminates with an error response and no peripheral access initiates. 05518 * 05519 * Values: 05520 * - 0 - Accesses from an untrusted master are allowed. 05521 * - 1 - Accesses from an untrusted master are not allowed. 05522 */ 05523 /*@{*/ 05524 #define BP_AIPS_PACRG_TP2 (20U) /*!< Bit position for AIPS_PACRG_TP2. */ 05525 #define BM_AIPS_PACRG_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRG_TP2. */ 05526 #define BS_AIPS_PACRG_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP2. */ 05527 05528 /*! @brief Read current value of the AIPS_PACRG_TP2 field. */ 05529 #define BR_AIPS_PACRG_TP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP2))) 05530 05531 /*! @brief Format value for bitfield AIPS_PACRG_TP2. */ 05532 #define BF_AIPS_PACRG_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP2) & BM_AIPS_PACRG_TP2) 05533 05534 /*! @brief Set the TP2 field to a new value. */ 05535 #define BW_AIPS_PACRG_TP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP2), v)) 05536 /*@}*/ 05537 05538 /*! 05539 * @name Register AIPS_PACRG, field WP2[21] (RW) 05540 * 05541 * Determines whether the peripheral allows write accesses. When this field is 05542 * set and a write access is attempted, access terminates with an error response 05543 * and no peripheral access initiates. 05544 * 05545 * Values: 05546 * - 0 - This peripheral allows write accesses. 05547 * - 1 - This peripheral is write protected. 05548 */ 05549 /*@{*/ 05550 #define BP_AIPS_PACRG_WP2 (21U) /*!< Bit position for AIPS_PACRG_WP2. */ 05551 #define BM_AIPS_PACRG_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRG_WP2. */ 05552 #define BS_AIPS_PACRG_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP2. */ 05553 05554 /*! @brief Read current value of the AIPS_PACRG_WP2 field. */ 05555 #define BR_AIPS_PACRG_WP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP2))) 05556 05557 /*! @brief Format value for bitfield AIPS_PACRG_WP2. */ 05558 #define BF_AIPS_PACRG_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP2) & BM_AIPS_PACRG_WP2) 05559 05560 /*! @brief Set the WP2 field to a new value. */ 05561 #define BW_AIPS_PACRG_WP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP2), v)) 05562 /*@}*/ 05563 05564 /*! 05565 * @name Register AIPS_PACRG, field SP2[22] (RW) 05566 * 05567 * Determines whether the peripheral requires supervisor privilege level for 05568 * access. When this bit is set, the master privilege level must indicate the 05569 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 05570 * set. If not, access terminates with an error response and no peripheral access 05571 * initiates. 05572 * 05573 * Values: 05574 * - 0 - This peripheral does not require supervisor privilege level for 05575 * accesses. 05576 * - 1 - This peripheral requires supervisor privilege level for accesses. 05577 */ 05578 /*@{*/ 05579 #define BP_AIPS_PACRG_SP2 (22U) /*!< Bit position for AIPS_PACRG_SP2. */ 05580 #define BM_AIPS_PACRG_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRG_SP2. */ 05581 #define BS_AIPS_PACRG_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP2. */ 05582 05583 /*! @brief Read current value of the AIPS_PACRG_SP2 field. */ 05584 #define BR_AIPS_PACRG_SP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP2))) 05585 05586 /*! @brief Format value for bitfield AIPS_PACRG_SP2. */ 05587 #define BF_AIPS_PACRG_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP2) & BM_AIPS_PACRG_SP2) 05588 05589 /*! @brief Set the SP2 field to a new value. */ 05590 #define BW_AIPS_PACRG_SP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP2), v)) 05591 /*@}*/ 05592 05593 /*! 05594 * @name Register AIPS_PACRG, field TP1[24] (RW) 05595 * 05596 * Determines whether the peripheral allows accesses from an untrusted master. 05597 * When this field is set and an access is attempted by an untrusted master, the 05598 * access terminates with an error response and no peripheral access initiates. 05599 * 05600 * Values: 05601 * - 0 - Accesses from an untrusted master are allowed. 05602 * - 1 - Accesses from an untrusted master are not allowed. 05603 */ 05604 /*@{*/ 05605 #define BP_AIPS_PACRG_TP1 (24U) /*!< Bit position for AIPS_PACRG_TP1. */ 05606 #define BM_AIPS_PACRG_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRG_TP1. */ 05607 #define BS_AIPS_PACRG_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP1. */ 05608 05609 /*! @brief Read current value of the AIPS_PACRG_TP1 field. */ 05610 #define BR_AIPS_PACRG_TP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP1))) 05611 05612 /*! @brief Format value for bitfield AIPS_PACRG_TP1. */ 05613 #define BF_AIPS_PACRG_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP1) & BM_AIPS_PACRG_TP1) 05614 05615 /*! @brief Set the TP1 field to a new value. */ 05616 #define BW_AIPS_PACRG_TP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP1), v)) 05617 /*@}*/ 05618 05619 /*! 05620 * @name Register AIPS_PACRG, field WP1[25] (RW) 05621 * 05622 * Determines whether the peripheral allows write accesses. When this field is 05623 * set and a write access is attempted, access terminates with an error response 05624 * and no peripheral access initiates. 05625 * 05626 * Values: 05627 * - 0 - This peripheral allows write accesses. 05628 * - 1 - This peripheral is write protected. 05629 */ 05630 /*@{*/ 05631 #define BP_AIPS_PACRG_WP1 (25U) /*!< Bit position for AIPS_PACRG_WP1. */ 05632 #define BM_AIPS_PACRG_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRG_WP1. */ 05633 #define BS_AIPS_PACRG_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP1. */ 05634 05635 /*! @brief Read current value of the AIPS_PACRG_WP1 field. */ 05636 #define BR_AIPS_PACRG_WP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP1))) 05637 05638 /*! @brief Format value for bitfield AIPS_PACRG_WP1. */ 05639 #define BF_AIPS_PACRG_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP1) & BM_AIPS_PACRG_WP1) 05640 05641 /*! @brief Set the WP1 field to a new value. */ 05642 #define BW_AIPS_PACRG_WP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP1), v)) 05643 /*@}*/ 05644 05645 /*! 05646 * @name Register AIPS_PACRG, field SP1[26] (RW) 05647 * 05648 * Determines whether the peripheral requires supervisor privilege level for 05649 * access. When this field is set, the master privilege level must indicate the 05650 * supervisor access attribute, and the MPRx[MPLn] control field for the master must 05651 * be set. If not, access terminates with an error response and no peripheral 05652 * access initiates. 05653 * 05654 * Values: 05655 * - 0 - This peripheral does not require supervisor privilege level for 05656 * accesses. 05657 * - 1 - This peripheral requires supervisor privilege level for accesses. 05658 */ 05659 /*@{*/ 05660 #define BP_AIPS_PACRG_SP1 (26U) /*!< Bit position for AIPS_PACRG_SP1. */ 05661 #define BM_AIPS_PACRG_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRG_SP1. */ 05662 #define BS_AIPS_PACRG_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP1. */ 05663 05664 /*! @brief Read current value of the AIPS_PACRG_SP1 field. */ 05665 #define BR_AIPS_PACRG_SP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP1))) 05666 05667 /*! @brief Format value for bitfield AIPS_PACRG_SP1. */ 05668 #define BF_AIPS_PACRG_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP1) & BM_AIPS_PACRG_SP1) 05669 05670 /*! @brief Set the SP1 field to a new value. */ 05671 #define BW_AIPS_PACRG_SP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP1), v)) 05672 /*@}*/ 05673 05674 /*! 05675 * @name Register AIPS_PACRG, field TP0[28] (RW) 05676 * 05677 * Determines whether the peripheral allows accesses from an untrusted master. 05678 * When this bit is set and an access is attempted by an untrusted master, the 05679 * access terminates with an error response and no peripheral access initiates. 05680 * 05681 * Values: 05682 * - 0 - Accesses from an untrusted master are allowed. 05683 * - 1 - Accesses from an untrusted master are not allowed. 05684 */ 05685 /*@{*/ 05686 #define BP_AIPS_PACRG_TP0 (28U) /*!< Bit position for AIPS_PACRG_TP0. */ 05687 #define BM_AIPS_PACRG_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRG_TP0. */ 05688 #define BS_AIPS_PACRG_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRG_TP0. */ 05689 05690 /*! @brief Read current value of the AIPS_PACRG_TP0 field. */ 05691 #define BR_AIPS_PACRG_TP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP0))) 05692 05693 /*! @brief Format value for bitfield AIPS_PACRG_TP0. */ 05694 #define BF_AIPS_PACRG_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_TP0) & BM_AIPS_PACRG_TP0) 05695 05696 /*! @brief Set the TP0 field to a new value. */ 05697 #define BW_AIPS_PACRG_TP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_TP0), v)) 05698 /*@}*/ 05699 05700 /*! 05701 * @name Register AIPS_PACRG, field WP0[29] (RW) 05702 * 05703 * Determines whether the peripheral allows write accesses. When this field is 05704 * set and a write access is attempted, access terminates with an error response 05705 * and no peripheral access initiates. 05706 * 05707 * Values: 05708 * - 0 - This peripheral allows write accesses. 05709 * - 1 - This peripheral is write protected. 05710 */ 05711 /*@{*/ 05712 #define BP_AIPS_PACRG_WP0 (29U) /*!< Bit position for AIPS_PACRG_WP0. */ 05713 #define BM_AIPS_PACRG_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRG_WP0. */ 05714 #define BS_AIPS_PACRG_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRG_WP0. */ 05715 05716 /*! @brief Read current value of the AIPS_PACRG_WP0 field. */ 05717 #define BR_AIPS_PACRG_WP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP0))) 05718 05719 /*! @brief Format value for bitfield AIPS_PACRG_WP0. */ 05720 #define BF_AIPS_PACRG_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_WP0) & BM_AIPS_PACRG_WP0) 05721 05722 /*! @brief Set the WP0 field to a new value. */ 05723 #define BW_AIPS_PACRG_WP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_WP0), v)) 05724 /*@}*/ 05725 05726 /*! 05727 * @name Register AIPS_PACRG, field SP0[30] (RW) 05728 * 05729 * Determines whether the peripheral requires supervisor privilege level for 05730 * accesses. When this field is set, the master privilege level must indicate the 05731 * supervisor access attribute, and the MPRx[MPLn] control field for the master 05732 * must be set. If not, access terminates with an error response and no peripheral 05733 * access initiates. 05734 * 05735 * Values: 05736 * - 0 - This peripheral does not require supervisor privilege level for 05737 * accesses. 05738 * - 1 - This peripheral requires supervisor privilege level for accesses. 05739 */ 05740 /*@{*/ 05741 #define BP_AIPS_PACRG_SP0 (30U) /*!< Bit position for AIPS_PACRG_SP0. */ 05742 #define BM_AIPS_PACRG_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRG_SP0. */ 05743 #define BS_AIPS_PACRG_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRG_SP0. */ 05744 05745 /*! @brief Read current value of the AIPS_PACRG_SP0 field. */ 05746 #define BR_AIPS_PACRG_SP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP0))) 05747 05748 /*! @brief Format value for bitfield AIPS_PACRG_SP0. */ 05749 #define BF_AIPS_PACRG_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRG_SP0) & BM_AIPS_PACRG_SP0) 05750 05751 /*! @brief Set the SP0 field to a new value. */ 05752 #define BW_AIPS_PACRG_SP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRG_ADDR(x), BP_AIPS_PACRG_SP0), v)) 05753 /*@}*/ 05754 05755 /******************************************************************************* 05756 * HW_AIPS_PACRH - Peripheral Access Control Register 05757 ******************************************************************************/ 05758 05759 /*! 05760 * @brief HW_AIPS_PACRH - Peripheral Access Control Register (RW) 05761 * 05762 * Reset value: 0x44444444U 05763 * 05764 * This section describes PACR registers E-P, which control peripheral slots 05765 * 32-127. See PACRPeripheral Access Control Register for the description of these 05766 * registers. 05767 */ 05768 typedef union _hw_aips_pacrh 05769 { 05770 uint32_t U; 05771 struct _hw_aips_pacrh_bitfields 05772 { 05773 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 05774 uint32_t WP7 : 1; /*!< [1] Write Protect */ 05775 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 05776 uint32_t RESERVED0 : 1; /*!< [3] */ 05777 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 05778 uint32_t WP6 : 1; /*!< [5] Write Protect */ 05779 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 05780 uint32_t RESERVED1 : 1; /*!< [7] */ 05781 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 05782 uint32_t WP5 : 1; /*!< [9] Write Protect */ 05783 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 05784 uint32_t RESERVED2 : 1; /*!< [11] */ 05785 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 05786 uint32_t WP4 : 1; /*!< [13] Write Protect */ 05787 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 05788 uint32_t RESERVED3 : 1; /*!< [15] */ 05789 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 05790 uint32_t WP3 : 1; /*!< [17] Write Protect */ 05791 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 05792 uint32_t RESERVED4 : 1; /*!< [19] */ 05793 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 05794 uint32_t WP2 : 1; /*!< [21] Write Protect */ 05795 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 05796 uint32_t RESERVED5 : 1; /*!< [23] */ 05797 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 05798 uint32_t WP1 : 1; /*!< [25] Write Protect */ 05799 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 05800 uint32_t RESERVED6 : 1; /*!< [27] */ 05801 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 05802 uint32_t WP0 : 1; /*!< [29] Write Protect */ 05803 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 05804 uint32_t RESERVED7 : 1; /*!< [31] */ 05805 } B; 05806 } hw_aips_pacrh_t; 05807 05808 /*! 05809 * @name Constants and macros for entire AIPS_PACRH register 05810 */ 05811 /*@{*/ 05812 #define HW_AIPS_PACRH_ADDR(x) ((x) + 0x4CU) 05813 05814 #define HW_AIPS_PACRH(x) (*(__IO hw_aips_pacrh_t *) HW_AIPS_PACRH_ADDR(x)) 05815 #define HW_AIPS_PACRH_RD(x) (ADDRESS_READ(hw_aips_pacrh_t, HW_AIPS_PACRH_ADDR(x))) 05816 #define HW_AIPS_PACRH_WR(x, v) (ADDRESS_WRITE(hw_aips_pacrh_t, HW_AIPS_PACRH_ADDR(x), v)) 05817 #define HW_AIPS_PACRH_SET(x, v) (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) | (v))) 05818 #define HW_AIPS_PACRH_CLR(x, v) (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) & ~(v))) 05819 #define HW_AIPS_PACRH_TOG(x, v) (HW_AIPS_PACRH_WR(x, HW_AIPS_PACRH_RD(x) ^ (v))) 05820 /*@}*/ 05821 05822 /* 05823 * Constants & macros for individual AIPS_PACRH bitfields 05824 */ 05825 05826 /*! 05827 * @name Register AIPS_PACRH, field TP7[0] (RW) 05828 * 05829 * Determines whether the peripheral allows accesses from an untrusted master. 05830 * When this field is set and an access is attempted by an untrusted master, the 05831 * access terminates with an error response and no peripheral access initiates. 05832 * 05833 * Values: 05834 * - 0 - Accesses from an untrusted master are allowed. 05835 * - 1 - Accesses from an untrusted master are not allowed. 05836 */ 05837 /*@{*/ 05838 #define BP_AIPS_PACRH_TP7 (0U) /*!< Bit position for AIPS_PACRH_TP7. */ 05839 #define BM_AIPS_PACRH_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRH_TP7. */ 05840 #define BS_AIPS_PACRH_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP7. */ 05841 05842 /*! @brief Read current value of the AIPS_PACRH_TP7 field. */ 05843 #define BR_AIPS_PACRH_TP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP7))) 05844 05845 /*! @brief Format value for bitfield AIPS_PACRH_TP7. */ 05846 #define BF_AIPS_PACRH_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP7) & BM_AIPS_PACRH_TP7) 05847 05848 /*! @brief Set the TP7 field to a new value. */ 05849 #define BW_AIPS_PACRH_TP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP7), v)) 05850 /*@}*/ 05851 05852 /*! 05853 * @name Register AIPS_PACRH, field WP7[1] (RW) 05854 * 05855 * Determines whether the peripheral allows write accesses. When this field is 05856 * set and a write access is attempted, access terminates with an error response 05857 * and no peripheral access initiates. 05858 * 05859 * Values: 05860 * - 0 - This peripheral allows write accesses. 05861 * - 1 - This peripheral is write protected. 05862 */ 05863 /*@{*/ 05864 #define BP_AIPS_PACRH_WP7 (1U) /*!< Bit position for AIPS_PACRH_WP7. */ 05865 #define BM_AIPS_PACRH_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRH_WP7. */ 05866 #define BS_AIPS_PACRH_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP7. */ 05867 05868 /*! @brief Read current value of the AIPS_PACRH_WP7 field. */ 05869 #define BR_AIPS_PACRH_WP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP7))) 05870 05871 /*! @brief Format value for bitfield AIPS_PACRH_WP7. */ 05872 #define BF_AIPS_PACRH_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP7) & BM_AIPS_PACRH_WP7) 05873 05874 /*! @brief Set the WP7 field to a new value. */ 05875 #define BW_AIPS_PACRH_WP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP7), v)) 05876 /*@}*/ 05877 05878 /*! 05879 * @name Register AIPS_PACRH, field SP7[2] (RW) 05880 * 05881 * Determines whether the peripheral requires supervisor privilege level for 05882 * accesses. When this field is set, the master privilege level must indicate the 05883 * supervisor access attribute, and the MPRx[MPLn] control field for the master 05884 * must be set. If not, access terminates with an error response and no peripheral 05885 * access initiates. 05886 * 05887 * Values: 05888 * - 0 - This peripheral does not require supervisor privilege level for 05889 * accesses. 05890 * - 1 - This peripheral requires supervisor privilege level for accesses. 05891 */ 05892 /*@{*/ 05893 #define BP_AIPS_PACRH_SP7 (2U) /*!< Bit position for AIPS_PACRH_SP7. */ 05894 #define BM_AIPS_PACRH_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRH_SP7. */ 05895 #define BS_AIPS_PACRH_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP7. */ 05896 05897 /*! @brief Read current value of the AIPS_PACRH_SP7 field. */ 05898 #define BR_AIPS_PACRH_SP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP7))) 05899 05900 /*! @brief Format value for bitfield AIPS_PACRH_SP7. */ 05901 #define BF_AIPS_PACRH_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP7) & BM_AIPS_PACRH_SP7) 05902 05903 /*! @brief Set the SP7 field to a new value. */ 05904 #define BW_AIPS_PACRH_SP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP7), v)) 05905 /*@}*/ 05906 05907 /*! 05908 * @name Register AIPS_PACRH, field TP6[4] (RW) 05909 * 05910 * Determines whether the peripheral allows accesses from an untrusted master. 05911 * When this field is set and an access is attempted by an untrusted master, the 05912 * access terminates with an error response and no peripheral access initiates. 05913 * 05914 * Values: 05915 * - 0 - Accesses from an untrusted master are allowed. 05916 * - 1 - Accesses from an untrusted master are not allowed. 05917 */ 05918 /*@{*/ 05919 #define BP_AIPS_PACRH_TP6 (4U) /*!< Bit position for AIPS_PACRH_TP6. */ 05920 #define BM_AIPS_PACRH_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRH_TP6. */ 05921 #define BS_AIPS_PACRH_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP6. */ 05922 05923 /*! @brief Read current value of the AIPS_PACRH_TP6 field. */ 05924 #define BR_AIPS_PACRH_TP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP6))) 05925 05926 /*! @brief Format value for bitfield AIPS_PACRH_TP6. */ 05927 #define BF_AIPS_PACRH_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP6) & BM_AIPS_PACRH_TP6) 05928 05929 /*! @brief Set the TP6 field to a new value. */ 05930 #define BW_AIPS_PACRH_TP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP6), v)) 05931 /*@}*/ 05932 05933 /*! 05934 * @name Register AIPS_PACRH, field WP6[5] (RW) 05935 * 05936 * Determines whether the peripheral allows write accesses. When this field is 05937 * set and a write access is attempted, access terminates with an error response 05938 * and no peripheral access initiates. 05939 * 05940 * Values: 05941 * - 0 - This peripheral allows write accesses. 05942 * - 1 - This peripheral is write protected. 05943 */ 05944 /*@{*/ 05945 #define BP_AIPS_PACRH_WP6 (5U) /*!< Bit position for AIPS_PACRH_WP6. */ 05946 #define BM_AIPS_PACRH_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRH_WP6. */ 05947 #define BS_AIPS_PACRH_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP6. */ 05948 05949 /*! @brief Read current value of the AIPS_PACRH_WP6 field. */ 05950 #define BR_AIPS_PACRH_WP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP6))) 05951 05952 /*! @brief Format value for bitfield AIPS_PACRH_WP6. */ 05953 #define BF_AIPS_PACRH_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP6) & BM_AIPS_PACRH_WP6) 05954 05955 /*! @brief Set the WP6 field to a new value. */ 05956 #define BW_AIPS_PACRH_WP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP6), v)) 05957 /*@}*/ 05958 05959 /*! 05960 * @name Register AIPS_PACRH, field SP6[6] (RW) 05961 * 05962 * Determines whether the peripheral requires supervisor privilege level for 05963 * accesses. When this field is set, the master privilege level must indicate the 05964 * supervisor access attribute, and the MPRx[MPLn] control field for the master 05965 * must be set. If not, access terminates with an error response and no peripheral 05966 * access initiates. 05967 * 05968 * Values: 05969 * - 0 - This peripheral does not require supervisor privilege level for 05970 * accesses. 05971 * - 1 - This peripheral requires supervisor privilege level for accesses. 05972 */ 05973 /*@{*/ 05974 #define BP_AIPS_PACRH_SP6 (6U) /*!< Bit position for AIPS_PACRH_SP6. */ 05975 #define BM_AIPS_PACRH_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRH_SP6. */ 05976 #define BS_AIPS_PACRH_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP6. */ 05977 05978 /*! @brief Read current value of the AIPS_PACRH_SP6 field. */ 05979 #define BR_AIPS_PACRH_SP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP6))) 05980 05981 /*! @brief Format value for bitfield AIPS_PACRH_SP6. */ 05982 #define BF_AIPS_PACRH_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP6) & BM_AIPS_PACRH_SP6) 05983 05984 /*! @brief Set the SP6 field to a new value. */ 05985 #define BW_AIPS_PACRH_SP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP6), v)) 05986 /*@}*/ 05987 05988 /*! 05989 * @name Register AIPS_PACRH, field TP5[8] (RW) 05990 * 05991 * Determines whether the peripheral allows accesses from an untrusted master. 05992 * When this field is set and an access is attempted by an untrusted master, the 05993 * access terminates with an error response and no peripheral access initiates. 05994 * 05995 * Values: 05996 * - 0 - Accesses from an untrusted master are allowed. 05997 * - 1 - Accesses from an untrusted master are not allowed. 05998 */ 05999 /*@{*/ 06000 #define BP_AIPS_PACRH_TP5 (8U) /*!< Bit position for AIPS_PACRH_TP5. */ 06001 #define BM_AIPS_PACRH_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRH_TP5. */ 06002 #define BS_AIPS_PACRH_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP5. */ 06003 06004 /*! @brief Read current value of the AIPS_PACRH_TP5 field. */ 06005 #define BR_AIPS_PACRH_TP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP5))) 06006 06007 /*! @brief Format value for bitfield AIPS_PACRH_TP5. */ 06008 #define BF_AIPS_PACRH_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP5) & BM_AIPS_PACRH_TP5) 06009 06010 /*! @brief Set the TP5 field to a new value. */ 06011 #define BW_AIPS_PACRH_TP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP5), v)) 06012 /*@}*/ 06013 06014 /*! 06015 * @name Register AIPS_PACRH, field WP5[9] (RW) 06016 * 06017 * Determines whether the peripheral allows write accesses. When this field is 06018 * set and a write access is attempted, access terminates with an error response 06019 * and no peripheral access initiates. 06020 * 06021 * Values: 06022 * - 0 - This peripheral allows write accesses. 06023 * - 1 - This peripheral is write protected. 06024 */ 06025 /*@{*/ 06026 #define BP_AIPS_PACRH_WP5 (9U) /*!< Bit position for AIPS_PACRH_WP5. */ 06027 #define BM_AIPS_PACRH_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRH_WP5. */ 06028 #define BS_AIPS_PACRH_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP5. */ 06029 06030 /*! @brief Read current value of the AIPS_PACRH_WP5 field. */ 06031 #define BR_AIPS_PACRH_WP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP5))) 06032 06033 /*! @brief Format value for bitfield AIPS_PACRH_WP5. */ 06034 #define BF_AIPS_PACRH_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP5) & BM_AIPS_PACRH_WP5) 06035 06036 /*! @brief Set the WP5 field to a new value. */ 06037 #define BW_AIPS_PACRH_WP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP5), v)) 06038 /*@}*/ 06039 06040 /*! 06041 * @name Register AIPS_PACRH, field SP5[10] (RW) 06042 * 06043 * Determines whether the peripheral requires supervisor privilege level for 06044 * accesses. When this field is set, the master privilege level must indicate the 06045 * supervisor access attribute, and the MPRx[MPLn] control field for the master 06046 * must be set. If not, access terminates with an error response and no peripheral 06047 * access initiates. 06048 * 06049 * Values: 06050 * - 0 - This peripheral does not require supervisor privilege level for 06051 * accesses. 06052 * - 1 - This peripheral requires supervisor privilege level for accesses. 06053 */ 06054 /*@{*/ 06055 #define BP_AIPS_PACRH_SP5 (10U) /*!< Bit position for AIPS_PACRH_SP5. */ 06056 #define BM_AIPS_PACRH_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRH_SP5. */ 06057 #define BS_AIPS_PACRH_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP5. */ 06058 06059 /*! @brief Read current value of the AIPS_PACRH_SP5 field. */ 06060 #define BR_AIPS_PACRH_SP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP5))) 06061 06062 /*! @brief Format value for bitfield AIPS_PACRH_SP5. */ 06063 #define BF_AIPS_PACRH_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP5) & BM_AIPS_PACRH_SP5) 06064 06065 /*! @brief Set the SP5 field to a new value. */ 06066 #define BW_AIPS_PACRH_SP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP5), v)) 06067 /*@}*/ 06068 06069 /*! 06070 * @name Register AIPS_PACRH, field TP4[12] (RW) 06071 * 06072 * Determines whether the peripheral allows accesses from an untrusted master. 06073 * When this bit is set and an access is attempted by an untrusted master, the 06074 * access terminates with an error response and no peripheral access initiates. 06075 * 06076 * Values: 06077 * - 0 - Accesses from an untrusted master are allowed. 06078 * - 1 - Accesses from an untrusted master are not allowed. 06079 */ 06080 /*@{*/ 06081 #define BP_AIPS_PACRH_TP4 (12U) /*!< Bit position for AIPS_PACRH_TP4. */ 06082 #define BM_AIPS_PACRH_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRH_TP4. */ 06083 #define BS_AIPS_PACRH_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP4. */ 06084 06085 /*! @brief Read current value of the AIPS_PACRH_TP4 field. */ 06086 #define BR_AIPS_PACRH_TP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP4))) 06087 06088 /*! @brief Format value for bitfield AIPS_PACRH_TP4. */ 06089 #define BF_AIPS_PACRH_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP4) & BM_AIPS_PACRH_TP4) 06090 06091 /*! @brief Set the TP4 field to a new value. */ 06092 #define BW_AIPS_PACRH_TP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP4), v)) 06093 /*@}*/ 06094 06095 /*! 06096 * @name Register AIPS_PACRH, field WP4[13] (RW) 06097 * 06098 * Determines whether the peripheral allows write accesses. When this field is 06099 * set and a write access is attempted, access terminates with an error response 06100 * and no peripheral access initiates. 06101 * 06102 * Values: 06103 * - 0 - This peripheral allows write accesses. 06104 * - 1 - This peripheral is write protected. 06105 */ 06106 /*@{*/ 06107 #define BP_AIPS_PACRH_WP4 (13U) /*!< Bit position for AIPS_PACRH_WP4. */ 06108 #define BM_AIPS_PACRH_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRH_WP4. */ 06109 #define BS_AIPS_PACRH_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP4. */ 06110 06111 /*! @brief Read current value of the AIPS_PACRH_WP4 field. */ 06112 #define BR_AIPS_PACRH_WP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP4))) 06113 06114 /*! @brief Format value for bitfield AIPS_PACRH_WP4. */ 06115 #define BF_AIPS_PACRH_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP4) & BM_AIPS_PACRH_WP4) 06116 06117 /*! @brief Set the WP4 field to a new value. */ 06118 #define BW_AIPS_PACRH_WP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP4), v)) 06119 /*@}*/ 06120 06121 /*! 06122 * @name Register AIPS_PACRH, field SP4[14] (RW) 06123 * 06124 * Determines whether the peripheral requires supervisor privilege level for 06125 * access. When this bit is set, the master privilege level must indicate the 06126 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 06127 * set. If not, access terminates with an error response and no peripheral access 06128 * initiates. 06129 * 06130 * Values: 06131 * - 0 - This peripheral does not require supervisor privilege level for 06132 * accesses. 06133 * - 1 - This peripheral requires supervisor privilege level for accesses. 06134 */ 06135 /*@{*/ 06136 #define BP_AIPS_PACRH_SP4 (14U) /*!< Bit position for AIPS_PACRH_SP4. */ 06137 #define BM_AIPS_PACRH_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRH_SP4. */ 06138 #define BS_AIPS_PACRH_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP4. */ 06139 06140 /*! @brief Read current value of the AIPS_PACRH_SP4 field. */ 06141 #define BR_AIPS_PACRH_SP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP4))) 06142 06143 /*! @brief Format value for bitfield AIPS_PACRH_SP4. */ 06144 #define BF_AIPS_PACRH_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP4) & BM_AIPS_PACRH_SP4) 06145 06146 /*! @brief Set the SP4 field to a new value. */ 06147 #define BW_AIPS_PACRH_SP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP4), v)) 06148 /*@}*/ 06149 06150 /*! 06151 * @name Register AIPS_PACRH, field TP3[16] (RW) 06152 * 06153 * Determines whether the peripheral allows accesses from an untrusted master. 06154 * When this field is set and an access is attempted by an untrusted master, the 06155 * access terminates with an error response and no peripheral access initiates. 06156 * 06157 * Values: 06158 * - 0 - Accesses from an untrusted master are allowed. 06159 * - 1 - Accesses from an untrusted master are not allowed. 06160 */ 06161 /*@{*/ 06162 #define BP_AIPS_PACRH_TP3 (16U) /*!< Bit position for AIPS_PACRH_TP3. */ 06163 #define BM_AIPS_PACRH_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRH_TP3. */ 06164 #define BS_AIPS_PACRH_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP3. */ 06165 06166 /*! @brief Read current value of the AIPS_PACRH_TP3 field. */ 06167 #define BR_AIPS_PACRH_TP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP3))) 06168 06169 /*! @brief Format value for bitfield AIPS_PACRH_TP3. */ 06170 #define BF_AIPS_PACRH_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP3) & BM_AIPS_PACRH_TP3) 06171 06172 /*! @brief Set the TP3 field to a new value. */ 06173 #define BW_AIPS_PACRH_TP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP3), v)) 06174 /*@}*/ 06175 06176 /*! 06177 * @name Register AIPS_PACRH, field WP3[17] (RW) 06178 * 06179 * Determines whether the peripheral allows write accesss. When this bit is set 06180 * and a write access is attempted, access terminates with an error response and 06181 * no peripheral access initiates. 06182 * 06183 * Values: 06184 * - 0 - This peripheral allows write accesses. 06185 * - 1 - This peripheral is write protected. 06186 */ 06187 /*@{*/ 06188 #define BP_AIPS_PACRH_WP3 (17U) /*!< Bit position for AIPS_PACRH_WP3. */ 06189 #define BM_AIPS_PACRH_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRH_WP3. */ 06190 #define BS_AIPS_PACRH_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP3. */ 06191 06192 /*! @brief Read current value of the AIPS_PACRH_WP3 field. */ 06193 #define BR_AIPS_PACRH_WP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP3))) 06194 06195 /*! @brief Format value for bitfield AIPS_PACRH_WP3. */ 06196 #define BF_AIPS_PACRH_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP3) & BM_AIPS_PACRH_WP3) 06197 06198 /*! @brief Set the WP3 field to a new value. */ 06199 #define BW_AIPS_PACRH_WP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP3), v)) 06200 /*@}*/ 06201 06202 /*! 06203 * @name Register AIPS_PACRH, field SP3[18] (RW) 06204 * 06205 * Determines whether the peripheral requires supervisor privilege level for 06206 * accesses. When this field is set, the master privilege level must indicate the 06207 * supervisor access attribute, and the MPRx[MPLn] control field for the master 06208 * must be set. If not, access terminates with an error response and no peripheral 06209 * access initiates. 06210 * 06211 * Values: 06212 * - 0 - This peripheral does not require supervisor privilege level for 06213 * accesses. 06214 * - 1 - This peripheral requires supervisor privilege level for accesses. 06215 */ 06216 /*@{*/ 06217 #define BP_AIPS_PACRH_SP3 (18U) /*!< Bit position for AIPS_PACRH_SP3. */ 06218 #define BM_AIPS_PACRH_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRH_SP3. */ 06219 #define BS_AIPS_PACRH_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP3. */ 06220 06221 /*! @brief Read current value of the AIPS_PACRH_SP3 field. */ 06222 #define BR_AIPS_PACRH_SP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP3))) 06223 06224 /*! @brief Format value for bitfield AIPS_PACRH_SP3. */ 06225 #define BF_AIPS_PACRH_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP3) & BM_AIPS_PACRH_SP3) 06226 06227 /*! @brief Set the SP3 field to a new value. */ 06228 #define BW_AIPS_PACRH_SP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP3), v)) 06229 /*@}*/ 06230 06231 /*! 06232 * @name Register AIPS_PACRH, field TP2[20] (RW) 06233 * 06234 * Determines whether the peripheral allows accesses from an untrusted master. 06235 * When this bit is set and an access is attempted by an untrusted master, the 06236 * access terminates with an error response and no peripheral access initiates. 06237 * 06238 * Values: 06239 * - 0 - Accesses from an untrusted master are allowed. 06240 * - 1 - Accesses from an untrusted master are not allowed. 06241 */ 06242 /*@{*/ 06243 #define BP_AIPS_PACRH_TP2 (20U) /*!< Bit position for AIPS_PACRH_TP2. */ 06244 #define BM_AIPS_PACRH_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRH_TP2. */ 06245 #define BS_AIPS_PACRH_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP2. */ 06246 06247 /*! @brief Read current value of the AIPS_PACRH_TP2 field. */ 06248 #define BR_AIPS_PACRH_TP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP2))) 06249 06250 /*! @brief Format value for bitfield AIPS_PACRH_TP2. */ 06251 #define BF_AIPS_PACRH_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP2) & BM_AIPS_PACRH_TP2) 06252 06253 /*! @brief Set the TP2 field to a new value. */ 06254 #define BW_AIPS_PACRH_TP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP2), v)) 06255 /*@}*/ 06256 06257 /*! 06258 * @name Register AIPS_PACRH, field WP2[21] (RW) 06259 * 06260 * Determines whether the peripheral allows write accesses. When this field is 06261 * set and a write access is attempted, access terminates with an error response 06262 * and no peripheral access initiates. 06263 * 06264 * Values: 06265 * - 0 - This peripheral allows write accesses. 06266 * - 1 - This peripheral is write protected. 06267 */ 06268 /*@{*/ 06269 #define BP_AIPS_PACRH_WP2 (21U) /*!< Bit position for AIPS_PACRH_WP2. */ 06270 #define BM_AIPS_PACRH_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRH_WP2. */ 06271 #define BS_AIPS_PACRH_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP2. */ 06272 06273 /*! @brief Read current value of the AIPS_PACRH_WP2 field. */ 06274 #define BR_AIPS_PACRH_WP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP2))) 06275 06276 /*! @brief Format value for bitfield AIPS_PACRH_WP2. */ 06277 #define BF_AIPS_PACRH_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP2) & BM_AIPS_PACRH_WP2) 06278 06279 /*! @brief Set the WP2 field to a new value. */ 06280 #define BW_AIPS_PACRH_WP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP2), v)) 06281 /*@}*/ 06282 06283 /*! 06284 * @name Register AIPS_PACRH, field SP2[22] (RW) 06285 * 06286 * Determines whether the peripheral requires supervisor privilege level for 06287 * access. When this bit is set, the master privilege level must indicate the 06288 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 06289 * set. If not, access terminates with an error response and no peripheral access 06290 * initiates. 06291 * 06292 * Values: 06293 * - 0 - This peripheral does not require supervisor privilege level for 06294 * accesses. 06295 * - 1 - This peripheral requires supervisor privilege level for accesses. 06296 */ 06297 /*@{*/ 06298 #define BP_AIPS_PACRH_SP2 (22U) /*!< Bit position for AIPS_PACRH_SP2. */ 06299 #define BM_AIPS_PACRH_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRH_SP2. */ 06300 #define BS_AIPS_PACRH_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP2. */ 06301 06302 /*! @brief Read current value of the AIPS_PACRH_SP2 field. */ 06303 #define BR_AIPS_PACRH_SP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP2))) 06304 06305 /*! @brief Format value for bitfield AIPS_PACRH_SP2. */ 06306 #define BF_AIPS_PACRH_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP2) & BM_AIPS_PACRH_SP2) 06307 06308 /*! @brief Set the SP2 field to a new value. */ 06309 #define BW_AIPS_PACRH_SP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP2), v)) 06310 /*@}*/ 06311 06312 /*! 06313 * @name Register AIPS_PACRH, field TP1[24] (RW) 06314 * 06315 * Determines whether the peripheral allows accesses from an untrusted master. 06316 * When this field is set and an access is attempted by an untrusted master, the 06317 * access terminates with an error response and no peripheral access initiates. 06318 * 06319 * Values: 06320 * - 0 - Accesses from an untrusted master are allowed. 06321 * - 1 - Accesses from an untrusted master are not allowed. 06322 */ 06323 /*@{*/ 06324 #define BP_AIPS_PACRH_TP1 (24U) /*!< Bit position for AIPS_PACRH_TP1. */ 06325 #define BM_AIPS_PACRH_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRH_TP1. */ 06326 #define BS_AIPS_PACRH_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP1. */ 06327 06328 /*! @brief Read current value of the AIPS_PACRH_TP1 field. */ 06329 #define BR_AIPS_PACRH_TP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP1))) 06330 06331 /*! @brief Format value for bitfield AIPS_PACRH_TP1. */ 06332 #define BF_AIPS_PACRH_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP1) & BM_AIPS_PACRH_TP1) 06333 06334 /*! @brief Set the TP1 field to a new value. */ 06335 #define BW_AIPS_PACRH_TP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP1), v)) 06336 /*@}*/ 06337 06338 /*! 06339 * @name Register AIPS_PACRH, field WP1[25] (RW) 06340 * 06341 * Determines whether the peripheral allows write accesses. When this field is 06342 * set and a write access is attempted, access terminates with an error response 06343 * and no peripheral access initiates. 06344 * 06345 * Values: 06346 * - 0 - This peripheral allows write accesses. 06347 * - 1 - This peripheral is write protected. 06348 */ 06349 /*@{*/ 06350 #define BP_AIPS_PACRH_WP1 (25U) /*!< Bit position for AIPS_PACRH_WP1. */ 06351 #define BM_AIPS_PACRH_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRH_WP1. */ 06352 #define BS_AIPS_PACRH_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP1. */ 06353 06354 /*! @brief Read current value of the AIPS_PACRH_WP1 field. */ 06355 #define BR_AIPS_PACRH_WP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP1))) 06356 06357 /*! @brief Format value for bitfield AIPS_PACRH_WP1. */ 06358 #define BF_AIPS_PACRH_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP1) & BM_AIPS_PACRH_WP1) 06359 06360 /*! @brief Set the WP1 field to a new value. */ 06361 #define BW_AIPS_PACRH_WP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP1), v)) 06362 /*@}*/ 06363 06364 /*! 06365 * @name Register AIPS_PACRH, field SP1[26] (RW) 06366 * 06367 * Determines whether the peripheral requires supervisor privilege level for 06368 * access. When this field is set, the master privilege level must indicate the 06369 * supervisor access attribute, and the MPRx[MPLn] control field for the master must 06370 * be set. If not, access terminates with an error response and no peripheral 06371 * access initiates. 06372 * 06373 * Values: 06374 * - 0 - This peripheral does not require supervisor privilege level for 06375 * accesses. 06376 * - 1 - This peripheral requires supervisor privilege level for accesses. 06377 */ 06378 /*@{*/ 06379 #define BP_AIPS_PACRH_SP1 (26U) /*!< Bit position for AIPS_PACRH_SP1. */ 06380 #define BM_AIPS_PACRH_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRH_SP1. */ 06381 #define BS_AIPS_PACRH_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP1. */ 06382 06383 /*! @brief Read current value of the AIPS_PACRH_SP1 field. */ 06384 #define BR_AIPS_PACRH_SP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP1))) 06385 06386 /*! @brief Format value for bitfield AIPS_PACRH_SP1. */ 06387 #define BF_AIPS_PACRH_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP1) & BM_AIPS_PACRH_SP1) 06388 06389 /*! @brief Set the SP1 field to a new value. */ 06390 #define BW_AIPS_PACRH_SP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP1), v)) 06391 /*@}*/ 06392 06393 /*! 06394 * @name Register AIPS_PACRH, field TP0[28] (RW) 06395 * 06396 * Determines whether the peripheral allows accesses from an untrusted master. 06397 * When this bit is set and an access is attempted by an untrusted master, the 06398 * access terminates with an error response and no peripheral access initiates. 06399 * 06400 * Values: 06401 * - 0 - Accesses from an untrusted master are allowed. 06402 * - 1 - Accesses from an untrusted master are not allowed. 06403 */ 06404 /*@{*/ 06405 #define BP_AIPS_PACRH_TP0 (28U) /*!< Bit position for AIPS_PACRH_TP0. */ 06406 #define BM_AIPS_PACRH_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRH_TP0. */ 06407 #define BS_AIPS_PACRH_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRH_TP0. */ 06408 06409 /*! @brief Read current value of the AIPS_PACRH_TP0 field. */ 06410 #define BR_AIPS_PACRH_TP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP0))) 06411 06412 /*! @brief Format value for bitfield AIPS_PACRH_TP0. */ 06413 #define BF_AIPS_PACRH_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_TP0) & BM_AIPS_PACRH_TP0) 06414 06415 /*! @brief Set the TP0 field to a new value. */ 06416 #define BW_AIPS_PACRH_TP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_TP0), v)) 06417 /*@}*/ 06418 06419 /*! 06420 * @name Register AIPS_PACRH, field WP0[29] (RW) 06421 * 06422 * Determines whether the peripheral allows write accesses. When this field is 06423 * set and a write access is attempted, access terminates with an error response 06424 * and no peripheral access initiates. 06425 * 06426 * Values: 06427 * - 0 - This peripheral allows write accesses. 06428 * - 1 - This peripheral is write protected. 06429 */ 06430 /*@{*/ 06431 #define BP_AIPS_PACRH_WP0 (29U) /*!< Bit position for AIPS_PACRH_WP0. */ 06432 #define BM_AIPS_PACRH_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRH_WP0. */ 06433 #define BS_AIPS_PACRH_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRH_WP0. */ 06434 06435 /*! @brief Read current value of the AIPS_PACRH_WP0 field. */ 06436 #define BR_AIPS_PACRH_WP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP0))) 06437 06438 /*! @brief Format value for bitfield AIPS_PACRH_WP0. */ 06439 #define BF_AIPS_PACRH_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_WP0) & BM_AIPS_PACRH_WP0) 06440 06441 /*! @brief Set the WP0 field to a new value. */ 06442 #define BW_AIPS_PACRH_WP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_WP0), v)) 06443 /*@}*/ 06444 06445 /*! 06446 * @name Register AIPS_PACRH, field SP0[30] (RW) 06447 * 06448 * Determines whether the peripheral requires supervisor privilege level for 06449 * accesses. When this field is set, the master privilege level must indicate the 06450 * supervisor access attribute, and the MPRx[MPLn] control field for the master 06451 * must be set. If not, access terminates with an error response and no peripheral 06452 * access initiates. 06453 * 06454 * Values: 06455 * - 0 - This peripheral does not require supervisor privilege level for 06456 * accesses. 06457 * - 1 - This peripheral requires supervisor privilege level for accesses. 06458 */ 06459 /*@{*/ 06460 #define BP_AIPS_PACRH_SP0 (30U) /*!< Bit position for AIPS_PACRH_SP0. */ 06461 #define BM_AIPS_PACRH_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRH_SP0. */ 06462 #define BS_AIPS_PACRH_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRH_SP0. */ 06463 06464 /*! @brief Read current value of the AIPS_PACRH_SP0 field. */ 06465 #define BR_AIPS_PACRH_SP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP0))) 06466 06467 /*! @brief Format value for bitfield AIPS_PACRH_SP0. */ 06468 #define BF_AIPS_PACRH_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRH_SP0) & BM_AIPS_PACRH_SP0) 06469 06470 /*! @brief Set the SP0 field to a new value. */ 06471 #define BW_AIPS_PACRH_SP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRH_ADDR(x), BP_AIPS_PACRH_SP0), v)) 06472 /*@}*/ 06473 06474 /******************************************************************************* 06475 * HW_AIPS_PACRI - Peripheral Access Control Register 06476 ******************************************************************************/ 06477 06478 /*! 06479 * @brief HW_AIPS_PACRI - Peripheral Access Control Register (RW) 06480 * 06481 * Reset value: 0x44444444U 06482 * 06483 * This section describes PACR registers E-P, which control peripheral slots 06484 * 32-127. See PACRPeripheral Access Control Register for the description of these 06485 * registers. 06486 */ 06487 typedef union _hw_aips_pacri 06488 { 06489 uint32_t U; 06490 struct _hw_aips_pacri_bitfields 06491 { 06492 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 06493 uint32_t WP7 : 1; /*!< [1] Write Protect */ 06494 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 06495 uint32_t RESERVED0 : 1; /*!< [3] */ 06496 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 06497 uint32_t WP6 : 1; /*!< [5] Write Protect */ 06498 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 06499 uint32_t RESERVED1 : 1; /*!< [7] */ 06500 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 06501 uint32_t WP5 : 1; /*!< [9] Write Protect */ 06502 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 06503 uint32_t RESERVED2 : 1; /*!< [11] */ 06504 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 06505 uint32_t WP4 : 1; /*!< [13] Write Protect */ 06506 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 06507 uint32_t RESERVED3 : 1; /*!< [15] */ 06508 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 06509 uint32_t WP3 : 1; /*!< [17] Write Protect */ 06510 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 06511 uint32_t RESERVED4 : 1; /*!< [19] */ 06512 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 06513 uint32_t WP2 : 1; /*!< [21] Write Protect */ 06514 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 06515 uint32_t RESERVED5 : 1; /*!< [23] */ 06516 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 06517 uint32_t WP1 : 1; /*!< [25] Write Protect */ 06518 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 06519 uint32_t RESERVED6 : 1; /*!< [27] */ 06520 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 06521 uint32_t WP0 : 1; /*!< [29] Write Protect */ 06522 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 06523 uint32_t RESERVED7 : 1; /*!< [31] */ 06524 } B; 06525 } hw_aips_pacri_t; 06526 06527 /*! 06528 * @name Constants and macros for entire AIPS_PACRI register 06529 */ 06530 /*@{*/ 06531 #define HW_AIPS_PACRI_ADDR(x) ((x) + 0x50U) 06532 06533 #define HW_AIPS_PACRI(x) (*(__IO hw_aips_pacri_t *) HW_AIPS_PACRI_ADDR(x)) 06534 #define HW_AIPS_PACRI_RD(x) (ADDRESS_READ(hw_aips_pacri_t, HW_AIPS_PACRI_ADDR(x))) 06535 #define HW_AIPS_PACRI_WR(x, v) (ADDRESS_WRITE(hw_aips_pacri_t, HW_AIPS_PACRI_ADDR(x), v)) 06536 #define HW_AIPS_PACRI_SET(x, v) (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) | (v))) 06537 #define HW_AIPS_PACRI_CLR(x, v) (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) & ~(v))) 06538 #define HW_AIPS_PACRI_TOG(x, v) (HW_AIPS_PACRI_WR(x, HW_AIPS_PACRI_RD(x) ^ (v))) 06539 /*@}*/ 06540 06541 /* 06542 * Constants & macros for individual AIPS_PACRI bitfields 06543 */ 06544 06545 /*! 06546 * @name Register AIPS_PACRI, field TP7[0] (RW) 06547 * 06548 * Determines whether the peripheral allows accesses from an untrusted master. 06549 * When this field is set and an access is attempted by an untrusted master, the 06550 * access terminates with an error response and no peripheral access initiates. 06551 * 06552 * Values: 06553 * - 0 - Accesses from an untrusted master are allowed. 06554 * - 1 - Accesses from an untrusted master are not allowed. 06555 */ 06556 /*@{*/ 06557 #define BP_AIPS_PACRI_TP7 (0U) /*!< Bit position for AIPS_PACRI_TP7. */ 06558 #define BM_AIPS_PACRI_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRI_TP7. */ 06559 #define BS_AIPS_PACRI_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP7. */ 06560 06561 /*! @brief Read current value of the AIPS_PACRI_TP7 field. */ 06562 #define BR_AIPS_PACRI_TP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP7))) 06563 06564 /*! @brief Format value for bitfield AIPS_PACRI_TP7. */ 06565 #define BF_AIPS_PACRI_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP7) & BM_AIPS_PACRI_TP7) 06566 06567 /*! @brief Set the TP7 field to a new value. */ 06568 #define BW_AIPS_PACRI_TP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP7), v)) 06569 /*@}*/ 06570 06571 /*! 06572 * @name Register AIPS_PACRI, field WP7[1] (RW) 06573 * 06574 * Determines whether the peripheral allows write accesses. When this field is 06575 * set and a write access is attempted, access terminates with an error response 06576 * and no peripheral access initiates. 06577 * 06578 * Values: 06579 * - 0 - This peripheral allows write accesses. 06580 * - 1 - This peripheral is write protected. 06581 */ 06582 /*@{*/ 06583 #define BP_AIPS_PACRI_WP7 (1U) /*!< Bit position for AIPS_PACRI_WP7. */ 06584 #define BM_AIPS_PACRI_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRI_WP7. */ 06585 #define BS_AIPS_PACRI_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP7. */ 06586 06587 /*! @brief Read current value of the AIPS_PACRI_WP7 field. */ 06588 #define BR_AIPS_PACRI_WP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP7))) 06589 06590 /*! @brief Format value for bitfield AIPS_PACRI_WP7. */ 06591 #define BF_AIPS_PACRI_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP7) & BM_AIPS_PACRI_WP7) 06592 06593 /*! @brief Set the WP7 field to a new value. */ 06594 #define BW_AIPS_PACRI_WP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP7), v)) 06595 /*@}*/ 06596 06597 /*! 06598 * @name Register AIPS_PACRI, field SP7[2] (RW) 06599 * 06600 * Determines whether the peripheral requires supervisor privilege level for 06601 * accesses. When this field is set, the master privilege level must indicate the 06602 * supervisor access attribute, and the MPRx[MPLn] control field for the master 06603 * must be set. If not, access terminates with an error response and no peripheral 06604 * access initiates. 06605 * 06606 * Values: 06607 * - 0 - This peripheral does not require supervisor privilege level for 06608 * accesses. 06609 * - 1 - This peripheral requires supervisor privilege level for accesses. 06610 */ 06611 /*@{*/ 06612 #define BP_AIPS_PACRI_SP7 (2U) /*!< Bit position for AIPS_PACRI_SP7. */ 06613 #define BM_AIPS_PACRI_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRI_SP7. */ 06614 #define BS_AIPS_PACRI_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP7. */ 06615 06616 /*! @brief Read current value of the AIPS_PACRI_SP7 field. */ 06617 #define BR_AIPS_PACRI_SP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP7))) 06618 06619 /*! @brief Format value for bitfield AIPS_PACRI_SP7. */ 06620 #define BF_AIPS_PACRI_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP7) & BM_AIPS_PACRI_SP7) 06621 06622 /*! @brief Set the SP7 field to a new value. */ 06623 #define BW_AIPS_PACRI_SP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP7), v)) 06624 /*@}*/ 06625 06626 /*! 06627 * @name Register AIPS_PACRI, field TP6[4] (RW) 06628 * 06629 * Determines whether the peripheral allows accesses from an untrusted master. 06630 * When this field is set and an access is attempted by an untrusted master, the 06631 * access terminates with an error response and no peripheral access initiates. 06632 * 06633 * Values: 06634 * - 0 - Accesses from an untrusted master are allowed. 06635 * - 1 - Accesses from an untrusted master are not allowed. 06636 */ 06637 /*@{*/ 06638 #define BP_AIPS_PACRI_TP6 (4U) /*!< Bit position for AIPS_PACRI_TP6. */ 06639 #define BM_AIPS_PACRI_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRI_TP6. */ 06640 #define BS_AIPS_PACRI_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP6. */ 06641 06642 /*! @brief Read current value of the AIPS_PACRI_TP6 field. */ 06643 #define BR_AIPS_PACRI_TP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP6))) 06644 06645 /*! @brief Format value for bitfield AIPS_PACRI_TP6. */ 06646 #define BF_AIPS_PACRI_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP6) & BM_AIPS_PACRI_TP6) 06647 06648 /*! @brief Set the TP6 field to a new value. */ 06649 #define BW_AIPS_PACRI_TP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP6), v)) 06650 /*@}*/ 06651 06652 /*! 06653 * @name Register AIPS_PACRI, field WP6[5] (RW) 06654 * 06655 * Determines whether the peripheral allows write accesses. When this field is 06656 * set and a write access is attempted, access terminates with an error response 06657 * and no peripheral access initiates. 06658 * 06659 * Values: 06660 * - 0 - This peripheral allows write accesses. 06661 * - 1 - This peripheral is write protected. 06662 */ 06663 /*@{*/ 06664 #define BP_AIPS_PACRI_WP6 (5U) /*!< Bit position for AIPS_PACRI_WP6. */ 06665 #define BM_AIPS_PACRI_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRI_WP6. */ 06666 #define BS_AIPS_PACRI_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP6. */ 06667 06668 /*! @brief Read current value of the AIPS_PACRI_WP6 field. */ 06669 #define BR_AIPS_PACRI_WP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP6))) 06670 06671 /*! @brief Format value for bitfield AIPS_PACRI_WP6. */ 06672 #define BF_AIPS_PACRI_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP6) & BM_AIPS_PACRI_WP6) 06673 06674 /*! @brief Set the WP6 field to a new value. */ 06675 #define BW_AIPS_PACRI_WP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP6), v)) 06676 /*@}*/ 06677 06678 /*! 06679 * @name Register AIPS_PACRI, field SP6[6] (RW) 06680 * 06681 * Determines whether the peripheral requires supervisor privilege level for 06682 * accesses. When this field is set, the master privilege level must indicate the 06683 * supervisor access attribute, and the MPRx[MPLn] control field for the master 06684 * must be set. If not, access terminates with an error response and no peripheral 06685 * access initiates. 06686 * 06687 * Values: 06688 * - 0 - This peripheral does not require supervisor privilege level for 06689 * accesses. 06690 * - 1 - This peripheral requires supervisor privilege level for accesses. 06691 */ 06692 /*@{*/ 06693 #define BP_AIPS_PACRI_SP6 (6U) /*!< Bit position for AIPS_PACRI_SP6. */ 06694 #define BM_AIPS_PACRI_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRI_SP6. */ 06695 #define BS_AIPS_PACRI_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP6. */ 06696 06697 /*! @brief Read current value of the AIPS_PACRI_SP6 field. */ 06698 #define BR_AIPS_PACRI_SP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP6))) 06699 06700 /*! @brief Format value for bitfield AIPS_PACRI_SP6. */ 06701 #define BF_AIPS_PACRI_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP6) & BM_AIPS_PACRI_SP6) 06702 06703 /*! @brief Set the SP6 field to a new value. */ 06704 #define BW_AIPS_PACRI_SP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP6), v)) 06705 /*@}*/ 06706 06707 /*! 06708 * @name Register AIPS_PACRI, field TP5[8] (RW) 06709 * 06710 * Determines whether the peripheral allows accesses from an untrusted master. 06711 * When this field is set and an access is attempted by an untrusted master, the 06712 * access terminates with an error response and no peripheral access initiates. 06713 * 06714 * Values: 06715 * - 0 - Accesses from an untrusted master are allowed. 06716 * - 1 - Accesses from an untrusted master are not allowed. 06717 */ 06718 /*@{*/ 06719 #define BP_AIPS_PACRI_TP5 (8U) /*!< Bit position for AIPS_PACRI_TP5. */ 06720 #define BM_AIPS_PACRI_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRI_TP5. */ 06721 #define BS_AIPS_PACRI_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP5. */ 06722 06723 /*! @brief Read current value of the AIPS_PACRI_TP5 field. */ 06724 #define BR_AIPS_PACRI_TP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP5))) 06725 06726 /*! @brief Format value for bitfield AIPS_PACRI_TP5. */ 06727 #define BF_AIPS_PACRI_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP5) & BM_AIPS_PACRI_TP5) 06728 06729 /*! @brief Set the TP5 field to a new value. */ 06730 #define BW_AIPS_PACRI_TP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP5), v)) 06731 /*@}*/ 06732 06733 /*! 06734 * @name Register AIPS_PACRI, field WP5[9] (RW) 06735 * 06736 * Determines whether the peripheral allows write accesses. When this field is 06737 * set and a write access is attempted, access terminates with an error response 06738 * and no peripheral access initiates. 06739 * 06740 * Values: 06741 * - 0 - This peripheral allows write accesses. 06742 * - 1 - This peripheral is write protected. 06743 */ 06744 /*@{*/ 06745 #define BP_AIPS_PACRI_WP5 (9U) /*!< Bit position for AIPS_PACRI_WP5. */ 06746 #define BM_AIPS_PACRI_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRI_WP5. */ 06747 #define BS_AIPS_PACRI_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP5. */ 06748 06749 /*! @brief Read current value of the AIPS_PACRI_WP5 field. */ 06750 #define BR_AIPS_PACRI_WP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP5))) 06751 06752 /*! @brief Format value for bitfield AIPS_PACRI_WP5. */ 06753 #define BF_AIPS_PACRI_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP5) & BM_AIPS_PACRI_WP5) 06754 06755 /*! @brief Set the WP5 field to a new value. */ 06756 #define BW_AIPS_PACRI_WP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP5), v)) 06757 /*@}*/ 06758 06759 /*! 06760 * @name Register AIPS_PACRI, field SP5[10] (RW) 06761 * 06762 * Determines whether the peripheral requires supervisor privilege level for 06763 * accesses. When this field is set, the master privilege level must indicate the 06764 * supervisor access attribute, and the MPRx[MPLn] control field for the master 06765 * must be set. If not, access terminates with an error response and no peripheral 06766 * access initiates. 06767 * 06768 * Values: 06769 * - 0 - This peripheral does not require supervisor privilege level for 06770 * accesses. 06771 * - 1 - This peripheral requires supervisor privilege level for accesses. 06772 */ 06773 /*@{*/ 06774 #define BP_AIPS_PACRI_SP5 (10U) /*!< Bit position for AIPS_PACRI_SP5. */ 06775 #define BM_AIPS_PACRI_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRI_SP5. */ 06776 #define BS_AIPS_PACRI_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP5. */ 06777 06778 /*! @brief Read current value of the AIPS_PACRI_SP5 field. */ 06779 #define BR_AIPS_PACRI_SP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP5))) 06780 06781 /*! @brief Format value for bitfield AIPS_PACRI_SP5. */ 06782 #define BF_AIPS_PACRI_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP5) & BM_AIPS_PACRI_SP5) 06783 06784 /*! @brief Set the SP5 field to a new value. */ 06785 #define BW_AIPS_PACRI_SP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP5), v)) 06786 /*@}*/ 06787 06788 /*! 06789 * @name Register AIPS_PACRI, field TP4[12] (RW) 06790 * 06791 * Determines whether the peripheral allows accesses from an untrusted master. 06792 * When this bit is set and an access is attempted by an untrusted master, the 06793 * access terminates with an error response and no peripheral access initiates. 06794 * 06795 * Values: 06796 * - 0 - Accesses from an untrusted master are allowed. 06797 * - 1 - Accesses from an untrusted master are not allowed. 06798 */ 06799 /*@{*/ 06800 #define BP_AIPS_PACRI_TP4 (12U) /*!< Bit position for AIPS_PACRI_TP4. */ 06801 #define BM_AIPS_PACRI_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRI_TP4. */ 06802 #define BS_AIPS_PACRI_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP4. */ 06803 06804 /*! @brief Read current value of the AIPS_PACRI_TP4 field. */ 06805 #define BR_AIPS_PACRI_TP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP4))) 06806 06807 /*! @brief Format value for bitfield AIPS_PACRI_TP4. */ 06808 #define BF_AIPS_PACRI_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP4) & BM_AIPS_PACRI_TP4) 06809 06810 /*! @brief Set the TP4 field to a new value. */ 06811 #define BW_AIPS_PACRI_TP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP4), v)) 06812 /*@}*/ 06813 06814 /*! 06815 * @name Register AIPS_PACRI, field WP4[13] (RW) 06816 * 06817 * Determines whether the peripheral allows write accesses. When this field is 06818 * set and a write access is attempted, access terminates with an error response 06819 * and no peripheral access initiates. 06820 * 06821 * Values: 06822 * - 0 - This peripheral allows write accesses. 06823 * - 1 - This peripheral is write protected. 06824 */ 06825 /*@{*/ 06826 #define BP_AIPS_PACRI_WP4 (13U) /*!< Bit position for AIPS_PACRI_WP4. */ 06827 #define BM_AIPS_PACRI_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRI_WP4. */ 06828 #define BS_AIPS_PACRI_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP4. */ 06829 06830 /*! @brief Read current value of the AIPS_PACRI_WP4 field. */ 06831 #define BR_AIPS_PACRI_WP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP4))) 06832 06833 /*! @brief Format value for bitfield AIPS_PACRI_WP4. */ 06834 #define BF_AIPS_PACRI_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP4) & BM_AIPS_PACRI_WP4) 06835 06836 /*! @brief Set the WP4 field to a new value. */ 06837 #define BW_AIPS_PACRI_WP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP4), v)) 06838 /*@}*/ 06839 06840 /*! 06841 * @name Register AIPS_PACRI, field SP4[14] (RW) 06842 * 06843 * Determines whether the peripheral requires supervisor privilege level for 06844 * access. When this bit is set, the master privilege level must indicate the 06845 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 06846 * set. If not, access terminates with an error response and no peripheral access 06847 * initiates. 06848 * 06849 * Values: 06850 * - 0 - This peripheral does not require supervisor privilege level for 06851 * accesses. 06852 * - 1 - This peripheral requires supervisor privilege level for accesses. 06853 */ 06854 /*@{*/ 06855 #define BP_AIPS_PACRI_SP4 (14U) /*!< Bit position for AIPS_PACRI_SP4. */ 06856 #define BM_AIPS_PACRI_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRI_SP4. */ 06857 #define BS_AIPS_PACRI_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP4. */ 06858 06859 /*! @brief Read current value of the AIPS_PACRI_SP4 field. */ 06860 #define BR_AIPS_PACRI_SP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP4))) 06861 06862 /*! @brief Format value for bitfield AIPS_PACRI_SP4. */ 06863 #define BF_AIPS_PACRI_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP4) & BM_AIPS_PACRI_SP4) 06864 06865 /*! @brief Set the SP4 field to a new value. */ 06866 #define BW_AIPS_PACRI_SP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP4), v)) 06867 /*@}*/ 06868 06869 /*! 06870 * @name Register AIPS_PACRI, field TP3[16] (RW) 06871 * 06872 * Determines whether the peripheral allows accesses from an untrusted master. 06873 * When this field is set and an access is attempted by an untrusted master, the 06874 * access terminates with an error response and no peripheral access initiates. 06875 * 06876 * Values: 06877 * - 0 - Accesses from an untrusted master are allowed. 06878 * - 1 - Accesses from an untrusted master are not allowed. 06879 */ 06880 /*@{*/ 06881 #define BP_AIPS_PACRI_TP3 (16U) /*!< Bit position for AIPS_PACRI_TP3. */ 06882 #define BM_AIPS_PACRI_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRI_TP3. */ 06883 #define BS_AIPS_PACRI_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP3. */ 06884 06885 /*! @brief Read current value of the AIPS_PACRI_TP3 field. */ 06886 #define BR_AIPS_PACRI_TP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP3))) 06887 06888 /*! @brief Format value for bitfield AIPS_PACRI_TP3. */ 06889 #define BF_AIPS_PACRI_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP3) & BM_AIPS_PACRI_TP3) 06890 06891 /*! @brief Set the TP3 field to a new value. */ 06892 #define BW_AIPS_PACRI_TP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP3), v)) 06893 /*@}*/ 06894 06895 /*! 06896 * @name Register AIPS_PACRI, field WP3[17] (RW) 06897 * 06898 * Determines whether the peripheral allows write accesss. When this bit is set 06899 * and a write access is attempted, access terminates with an error response and 06900 * no peripheral access initiates. 06901 * 06902 * Values: 06903 * - 0 - This peripheral allows write accesses. 06904 * - 1 - This peripheral is write protected. 06905 */ 06906 /*@{*/ 06907 #define BP_AIPS_PACRI_WP3 (17U) /*!< Bit position for AIPS_PACRI_WP3. */ 06908 #define BM_AIPS_PACRI_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRI_WP3. */ 06909 #define BS_AIPS_PACRI_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP3. */ 06910 06911 /*! @brief Read current value of the AIPS_PACRI_WP3 field. */ 06912 #define BR_AIPS_PACRI_WP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP3))) 06913 06914 /*! @brief Format value for bitfield AIPS_PACRI_WP3. */ 06915 #define BF_AIPS_PACRI_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP3) & BM_AIPS_PACRI_WP3) 06916 06917 /*! @brief Set the WP3 field to a new value. */ 06918 #define BW_AIPS_PACRI_WP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP3), v)) 06919 /*@}*/ 06920 06921 /*! 06922 * @name Register AIPS_PACRI, field SP3[18] (RW) 06923 * 06924 * Determines whether the peripheral requires supervisor privilege level for 06925 * accesses. When this field is set, the master privilege level must indicate the 06926 * supervisor access attribute, and the MPRx[MPLn] control field for the master 06927 * must be set. If not, access terminates with an error response and no peripheral 06928 * access initiates. 06929 * 06930 * Values: 06931 * - 0 - This peripheral does not require supervisor privilege level for 06932 * accesses. 06933 * - 1 - This peripheral requires supervisor privilege level for accesses. 06934 */ 06935 /*@{*/ 06936 #define BP_AIPS_PACRI_SP3 (18U) /*!< Bit position for AIPS_PACRI_SP3. */ 06937 #define BM_AIPS_PACRI_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRI_SP3. */ 06938 #define BS_AIPS_PACRI_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP3. */ 06939 06940 /*! @brief Read current value of the AIPS_PACRI_SP3 field. */ 06941 #define BR_AIPS_PACRI_SP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP3))) 06942 06943 /*! @brief Format value for bitfield AIPS_PACRI_SP3. */ 06944 #define BF_AIPS_PACRI_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP3) & BM_AIPS_PACRI_SP3) 06945 06946 /*! @brief Set the SP3 field to a new value. */ 06947 #define BW_AIPS_PACRI_SP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP3), v)) 06948 /*@}*/ 06949 06950 /*! 06951 * @name Register AIPS_PACRI, field TP2[20] (RW) 06952 * 06953 * Determines whether the peripheral allows accesses from an untrusted master. 06954 * When this bit is set and an access is attempted by an untrusted master, the 06955 * access terminates with an error response and no peripheral access initiates. 06956 * 06957 * Values: 06958 * - 0 - Accesses from an untrusted master are allowed. 06959 * - 1 - Accesses from an untrusted master are not allowed. 06960 */ 06961 /*@{*/ 06962 #define BP_AIPS_PACRI_TP2 (20U) /*!< Bit position for AIPS_PACRI_TP2. */ 06963 #define BM_AIPS_PACRI_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRI_TP2. */ 06964 #define BS_AIPS_PACRI_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP2. */ 06965 06966 /*! @brief Read current value of the AIPS_PACRI_TP2 field. */ 06967 #define BR_AIPS_PACRI_TP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP2))) 06968 06969 /*! @brief Format value for bitfield AIPS_PACRI_TP2. */ 06970 #define BF_AIPS_PACRI_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP2) & BM_AIPS_PACRI_TP2) 06971 06972 /*! @brief Set the TP2 field to a new value. */ 06973 #define BW_AIPS_PACRI_TP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP2), v)) 06974 /*@}*/ 06975 06976 /*! 06977 * @name Register AIPS_PACRI, field WP2[21] (RW) 06978 * 06979 * Determines whether the peripheral allows write accesses. When this field is 06980 * set and a write access is attempted, access terminates with an error response 06981 * and no peripheral access initiates. 06982 * 06983 * Values: 06984 * - 0 - This peripheral allows write accesses. 06985 * - 1 - This peripheral is write protected. 06986 */ 06987 /*@{*/ 06988 #define BP_AIPS_PACRI_WP2 (21U) /*!< Bit position for AIPS_PACRI_WP2. */ 06989 #define BM_AIPS_PACRI_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRI_WP2. */ 06990 #define BS_AIPS_PACRI_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP2. */ 06991 06992 /*! @brief Read current value of the AIPS_PACRI_WP2 field. */ 06993 #define BR_AIPS_PACRI_WP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP2))) 06994 06995 /*! @brief Format value for bitfield AIPS_PACRI_WP2. */ 06996 #define BF_AIPS_PACRI_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP2) & BM_AIPS_PACRI_WP2) 06997 06998 /*! @brief Set the WP2 field to a new value. */ 06999 #define BW_AIPS_PACRI_WP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP2), v)) 07000 /*@}*/ 07001 07002 /*! 07003 * @name Register AIPS_PACRI, field SP2[22] (RW) 07004 * 07005 * Determines whether the peripheral requires supervisor privilege level for 07006 * access. When this bit is set, the master privilege level must indicate the 07007 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 07008 * set. If not, access terminates with an error response and no peripheral access 07009 * initiates. 07010 * 07011 * Values: 07012 * - 0 - This peripheral does not require supervisor privilege level for 07013 * accesses. 07014 * - 1 - This peripheral requires supervisor privilege level for accesses. 07015 */ 07016 /*@{*/ 07017 #define BP_AIPS_PACRI_SP2 (22U) /*!< Bit position for AIPS_PACRI_SP2. */ 07018 #define BM_AIPS_PACRI_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRI_SP2. */ 07019 #define BS_AIPS_PACRI_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP2. */ 07020 07021 /*! @brief Read current value of the AIPS_PACRI_SP2 field. */ 07022 #define BR_AIPS_PACRI_SP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP2))) 07023 07024 /*! @brief Format value for bitfield AIPS_PACRI_SP2. */ 07025 #define BF_AIPS_PACRI_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP2) & BM_AIPS_PACRI_SP2) 07026 07027 /*! @brief Set the SP2 field to a new value. */ 07028 #define BW_AIPS_PACRI_SP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP2), v)) 07029 /*@}*/ 07030 07031 /*! 07032 * @name Register AIPS_PACRI, field TP1[24] (RW) 07033 * 07034 * Determines whether the peripheral allows accesses from an untrusted master. 07035 * When this field is set and an access is attempted by an untrusted master, the 07036 * access terminates with an error response and no peripheral access initiates. 07037 * 07038 * Values: 07039 * - 0 - Accesses from an untrusted master are allowed. 07040 * - 1 - Accesses from an untrusted master are not allowed. 07041 */ 07042 /*@{*/ 07043 #define BP_AIPS_PACRI_TP1 (24U) /*!< Bit position for AIPS_PACRI_TP1. */ 07044 #define BM_AIPS_PACRI_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRI_TP1. */ 07045 #define BS_AIPS_PACRI_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP1. */ 07046 07047 /*! @brief Read current value of the AIPS_PACRI_TP1 field. */ 07048 #define BR_AIPS_PACRI_TP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP1))) 07049 07050 /*! @brief Format value for bitfield AIPS_PACRI_TP1. */ 07051 #define BF_AIPS_PACRI_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP1) & BM_AIPS_PACRI_TP1) 07052 07053 /*! @brief Set the TP1 field to a new value. */ 07054 #define BW_AIPS_PACRI_TP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP1), v)) 07055 /*@}*/ 07056 07057 /*! 07058 * @name Register AIPS_PACRI, field WP1[25] (RW) 07059 * 07060 * Determines whether the peripheral allows write accesses. When this field is 07061 * set and a write access is attempted, access terminates with an error response 07062 * and no peripheral access initiates. 07063 * 07064 * Values: 07065 * - 0 - This peripheral allows write accesses. 07066 * - 1 - This peripheral is write protected. 07067 */ 07068 /*@{*/ 07069 #define BP_AIPS_PACRI_WP1 (25U) /*!< Bit position for AIPS_PACRI_WP1. */ 07070 #define BM_AIPS_PACRI_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRI_WP1. */ 07071 #define BS_AIPS_PACRI_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP1. */ 07072 07073 /*! @brief Read current value of the AIPS_PACRI_WP1 field. */ 07074 #define BR_AIPS_PACRI_WP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP1))) 07075 07076 /*! @brief Format value for bitfield AIPS_PACRI_WP1. */ 07077 #define BF_AIPS_PACRI_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP1) & BM_AIPS_PACRI_WP1) 07078 07079 /*! @brief Set the WP1 field to a new value. */ 07080 #define BW_AIPS_PACRI_WP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP1), v)) 07081 /*@}*/ 07082 07083 /*! 07084 * @name Register AIPS_PACRI, field SP1[26] (RW) 07085 * 07086 * Determines whether the peripheral requires supervisor privilege level for 07087 * access. When this field is set, the master privilege level must indicate the 07088 * supervisor access attribute, and the MPRx[MPLn] control field for the master must 07089 * be set. If not, access terminates with an error response and no peripheral 07090 * access initiates. 07091 * 07092 * Values: 07093 * - 0 - This peripheral does not require supervisor privilege level for 07094 * accesses. 07095 * - 1 - This peripheral requires supervisor privilege level for accesses. 07096 */ 07097 /*@{*/ 07098 #define BP_AIPS_PACRI_SP1 (26U) /*!< Bit position for AIPS_PACRI_SP1. */ 07099 #define BM_AIPS_PACRI_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRI_SP1. */ 07100 #define BS_AIPS_PACRI_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP1. */ 07101 07102 /*! @brief Read current value of the AIPS_PACRI_SP1 field. */ 07103 #define BR_AIPS_PACRI_SP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP1))) 07104 07105 /*! @brief Format value for bitfield AIPS_PACRI_SP1. */ 07106 #define BF_AIPS_PACRI_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP1) & BM_AIPS_PACRI_SP1) 07107 07108 /*! @brief Set the SP1 field to a new value. */ 07109 #define BW_AIPS_PACRI_SP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP1), v)) 07110 /*@}*/ 07111 07112 /*! 07113 * @name Register AIPS_PACRI, field TP0[28] (RW) 07114 * 07115 * Determines whether the peripheral allows accesses from an untrusted master. 07116 * When this bit is set and an access is attempted by an untrusted master, the 07117 * access terminates with an error response and no peripheral access initiates. 07118 * 07119 * Values: 07120 * - 0 - Accesses from an untrusted master are allowed. 07121 * - 1 - Accesses from an untrusted master are not allowed. 07122 */ 07123 /*@{*/ 07124 #define BP_AIPS_PACRI_TP0 (28U) /*!< Bit position for AIPS_PACRI_TP0. */ 07125 #define BM_AIPS_PACRI_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRI_TP0. */ 07126 #define BS_AIPS_PACRI_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRI_TP0. */ 07127 07128 /*! @brief Read current value of the AIPS_PACRI_TP0 field. */ 07129 #define BR_AIPS_PACRI_TP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP0))) 07130 07131 /*! @brief Format value for bitfield AIPS_PACRI_TP0. */ 07132 #define BF_AIPS_PACRI_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_TP0) & BM_AIPS_PACRI_TP0) 07133 07134 /*! @brief Set the TP0 field to a new value. */ 07135 #define BW_AIPS_PACRI_TP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_TP0), v)) 07136 /*@}*/ 07137 07138 /*! 07139 * @name Register AIPS_PACRI, field WP0[29] (RW) 07140 * 07141 * Determines whether the peripheral allows write accesses. When this field is 07142 * set and a write access is attempted, access terminates with an error response 07143 * and no peripheral access initiates. 07144 * 07145 * Values: 07146 * - 0 - This peripheral allows write accesses. 07147 * - 1 - This peripheral is write protected. 07148 */ 07149 /*@{*/ 07150 #define BP_AIPS_PACRI_WP0 (29U) /*!< Bit position for AIPS_PACRI_WP0. */ 07151 #define BM_AIPS_PACRI_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRI_WP0. */ 07152 #define BS_AIPS_PACRI_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRI_WP0. */ 07153 07154 /*! @brief Read current value of the AIPS_PACRI_WP0 field. */ 07155 #define BR_AIPS_PACRI_WP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP0))) 07156 07157 /*! @brief Format value for bitfield AIPS_PACRI_WP0. */ 07158 #define BF_AIPS_PACRI_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_WP0) & BM_AIPS_PACRI_WP0) 07159 07160 /*! @brief Set the WP0 field to a new value. */ 07161 #define BW_AIPS_PACRI_WP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_WP0), v)) 07162 /*@}*/ 07163 07164 /*! 07165 * @name Register AIPS_PACRI, field SP0[30] (RW) 07166 * 07167 * Determines whether the peripheral requires supervisor privilege level for 07168 * accesses. When this field is set, the master privilege level must indicate the 07169 * supervisor access attribute, and the MPRx[MPLn] control field for the master 07170 * must be set. If not, access terminates with an error response and no peripheral 07171 * access initiates. 07172 * 07173 * Values: 07174 * - 0 - This peripheral does not require supervisor privilege level for 07175 * accesses. 07176 * - 1 - This peripheral requires supervisor privilege level for accesses. 07177 */ 07178 /*@{*/ 07179 #define BP_AIPS_PACRI_SP0 (30U) /*!< Bit position for AIPS_PACRI_SP0. */ 07180 #define BM_AIPS_PACRI_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRI_SP0. */ 07181 #define BS_AIPS_PACRI_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRI_SP0. */ 07182 07183 /*! @brief Read current value of the AIPS_PACRI_SP0 field. */ 07184 #define BR_AIPS_PACRI_SP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP0))) 07185 07186 /*! @brief Format value for bitfield AIPS_PACRI_SP0. */ 07187 #define BF_AIPS_PACRI_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRI_SP0) & BM_AIPS_PACRI_SP0) 07188 07189 /*! @brief Set the SP0 field to a new value. */ 07190 #define BW_AIPS_PACRI_SP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRI_ADDR(x), BP_AIPS_PACRI_SP0), v)) 07191 /*@}*/ 07192 07193 /******************************************************************************* 07194 * HW_AIPS_PACRJ - Peripheral Access Control Register 07195 ******************************************************************************/ 07196 07197 /*! 07198 * @brief HW_AIPS_PACRJ - Peripheral Access Control Register (RW) 07199 * 07200 * Reset value: 0x44444444U 07201 * 07202 * This section describes PACR registers E-P, which control peripheral slots 07203 * 32-127. See PACRPeripheral Access Control Register for the description of these 07204 * registers. 07205 */ 07206 typedef union _hw_aips_pacrj 07207 { 07208 uint32_t U; 07209 struct _hw_aips_pacrj_bitfields 07210 { 07211 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 07212 uint32_t WP7 : 1; /*!< [1] Write Protect */ 07213 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 07214 uint32_t RESERVED0 : 1; /*!< [3] */ 07215 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 07216 uint32_t WP6 : 1; /*!< [5] Write Protect */ 07217 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 07218 uint32_t RESERVED1 : 1; /*!< [7] */ 07219 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 07220 uint32_t WP5 : 1; /*!< [9] Write Protect */ 07221 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 07222 uint32_t RESERVED2 : 1; /*!< [11] */ 07223 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 07224 uint32_t WP4 : 1; /*!< [13] Write Protect */ 07225 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 07226 uint32_t RESERVED3 : 1; /*!< [15] */ 07227 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 07228 uint32_t WP3 : 1; /*!< [17] Write Protect */ 07229 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 07230 uint32_t RESERVED4 : 1; /*!< [19] */ 07231 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 07232 uint32_t WP2 : 1; /*!< [21] Write Protect */ 07233 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 07234 uint32_t RESERVED5 : 1; /*!< [23] */ 07235 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 07236 uint32_t WP1 : 1; /*!< [25] Write Protect */ 07237 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 07238 uint32_t RESERVED6 : 1; /*!< [27] */ 07239 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 07240 uint32_t WP0 : 1; /*!< [29] Write Protect */ 07241 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 07242 uint32_t RESERVED7 : 1; /*!< [31] */ 07243 } B; 07244 } hw_aips_pacrj_t; 07245 07246 /*! 07247 * @name Constants and macros for entire AIPS_PACRJ register 07248 */ 07249 /*@{*/ 07250 #define HW_AIPS_PACRJ_ADDR(x) ((x) + 0x54U) 07251 07252 #define HW_AIPS_PACRJ(x) (*(__IO hw_aips_pacrj_t *) HW_AIPS_PACRJ_ADDR(x)) 07253 #define HW_AIPS_PACRJ_RD(x) (ADDRESS_READ(hw_aips_pacrj_t, HW_AIPS_PACRJ_ADDR(x))) 07254 #define HW_AIPS_PACRJ_WR(x, v) (ADDRESS_WRITE(hw_aips_pacrj_t, HW_AIPS_PACRJ_ADDR(x), v)) 07255 #define HW_AIPS_PACRJ_SET(x, v) (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) | (v))) 07256 #define HW_AIPS_PACRJ_CLR(x, v) (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) & ~(v))) 07257 #define HW_AIPS_PACRJ_TOG(x, v) (HW_AIPS_PACRJ_WR(x, HW_AIPS_PACRJ_RD(x) ^ (v))) 07258 /*@}*/ 07259 07260 /* 07261 * Constants & macros for individual AIPS_PACRJ bitfields 07262 */ 07263 07264 /*! 07265 * @name Register AIPS_PACRJ, field TP7[0] (RW) 07266 * 07267 * Determines whether the peripheral allows accesses from an untrusted master. 07268 * When this field is set and an access is attempted by an untrusted master, the 07269 * access terminates with an error response and no peripheral access initiates. 07270 * 07271 * Values: 07272 * - 0 - Accesses from an untrusted master are allowed. 07273 * - 1 - Accesses from an untrusted master are not allowed. 07274 */ 07275 /*@{*/ 07276 #define BP_AIPS_PACRJ_TP7 (0U) /*!< Bit position for AIPS_PACRJ_TP7. */ 07277 #define BM_AIPS_PACRJ_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRJ_TP7. */ 07278 #define BS_AIPS_PACRJ_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP7. */ 07279 07280 /*! @brief Read current value of the AIPS_PACRJ_TP7 field. */ 07281 #define BR_AIPS_PACRJ_TP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP7))) 07282 07283 /*! @brief Format value for bitfield AIPS_PACRJ_TP7. */ 07284 #define BF_AIPS_PACRJ_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP7) & BM_AIPS_PACRJ_TP7) 07285 07286 /*! @brief Set the TP7 field to a new value. */ 07287 #define BW_AIPS_PACRJ_TP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP7), v)) 07288 /*@}*/ 07289 07290 /*! 07291 * @name Register AIPS_PACRJ, field WP7[1] (RW) 07292 * 07293 * Determines whether the peripheral allows write accesses. When this field is 07294 * set and a write access is attempted, access terminates with an error response 07295 * and no peripheral access initiates. 07296 * 07297 * Values: 07298 * - 0 - This peripheral allows write accesses. 07299 * - 1 - This peripheral is write protected. 07300 */ 07301 /*@{*/ 07302 #define BP_AIPS_PACRJ_WP7 (1U) /*!< Bit position for AIPS_PACRJ_WP7. */ 07303 #define BM_AIPS_PACRJ_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRJ_WP7. */ 07304 #define BS_AIPS_PACRJ_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP7. */ 07305 07306 /*! @brief Read current value of the AIPS_PACRJ_WP7 field. */ 07307 #define BR_AIPS_PACRJ_WP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP7))) 07308 07309 /*! @brief Format value for bitfield AIPS_PACRJ_WP7. */ 07310 #define BF_AIPS_PACRJ_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP7) & BM_AIPS_PACRJ_WP7) 07311 07312 /*! @brief Set the WP7 field to a new value. */ 07313 #define BW_AIPS_PACRJ_WP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP7), v)) 07314 /*@}*/ 07315 07316 /*! 07317 * @name Register AIPS_PACRJ, field SP7[2] (RW) 07318 * 07319 * Determines whether the peripheral requires supervisor privilege level for 07320 * accesses. When this field is set, the master privilege level must indicate the 07321 * supervisor access attribute, and the MPRx[MPLn] control field for the master 07322 * must be set. If not, access terminates with an error response and no peripheral 07323 * access initiates. 07324 * 07325 * Values: 07326 * - 0 - This peripheral does not require supervisor privilege level for 07327 * accesses. 07328 * - 1 - This peripheral requires supervisor privilege level for accesses. 07329 */ 07330 /*@{*/ 07331 #define BP_AIPS_PACRJ_SP7 (2U) /*!< Bit position for AIPS_PACRJ_SP7. */ 07332 #define BM_AIPS_PACRJ_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRJ_SP7. */ 07333 #define BS_AIPS_PACRJ_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP7. */ 07334 07335 /*! @brief Read current value of the AIPS_PACRJ_SP7 field. */ 07336 #define BR_AIPS_PACRJ_SP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP7))) 07337 07338 /*! @brief Format value for bitfield AIPS_PACRJ_SP7. */ 07339 #define BF_AIPS_PACRJ_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP7) & BM_AIPS_PACRJ_SP7) 07340 07341 /*! @brief Set the SP7 field to a new value. */ 07342 #define BW_AIPS_PACRJ_SP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP7), v)) 07343 /*@}*/ 07344 07345 /*! 07346 * @name Register AIPS_PACRJ, field TP6[4] (RW) 07347 * 07348 * Determines whether the peripheral allows accesses from an untrusted master. 07349 * When this field is set and an access is attempted by an untrusted master, the 07350 * access terminates with an error response and no peripheral access initiates. 07351 * 07352 * Values: 07353 * - 0 - Accesses from an untrusted master are allowed. 07354 * - 1 - Accesses from an untrusted master are not allowed. 07355 */ 07356 /*@{*/ 07357 #define BP_AIPS_PACRJ_TP6 (4U) /*!< Bit position for AIPS_PACRJ_TP6. */ 07358 #define BM_AIPS_PACRJ_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRJ_TP6. */ 07359 #define BS_AIPS_PACRJ_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP6. */ 07360 07361 /*! @brief Read current value of the AIPS_PACRJ_TP6 field. */ 07362 #define BR_AIPS_PACRJ_TP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP6))) 07363 07364 /*! @brief Format value for bitfield AIPS_PACRJ_TP6. */ 07365 #define BF_AIPS_PACRJ_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP6) & BM_AIPS_PACRJ_TP6) 07366 07367 /*! @brief Set the TP6 field to a new value. */ 07368 #define BW_AIPS_PACRJ_TP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP6), v)) 07369 /*@}*/ 07370 07371 /*! 07372 * @name Register AIPS_PACRJ, field WP6[5] (RW) 07373 * 07374 * Determines whether the peripheral allows write accesses. When this field is 07375 * set and a write access is attempted, access terminates with an error response 07376 * and no peripheral access initiates. 07377 * 07378 * Values: 07379 * - 0 - This peripheral allows write accesses. 07380 * - 1 - This peripheral is write protected. 07381 */ 07382 /*@{*/ 07383 #define BP_AIPS_PACRJ_WP6 (5U) /*!< Bit position for AIPS_PACRJ_WP6. */ 07384 #define BM_AIPS_PACRJ_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRJ_WP6. */ 07385 #define BS_AIPS_PACRJ_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP6. */ 07386 07387 /*! @brief Read current value of the AIPS_PACRJ_WP6 field. */ 07388 #define BR_AIPS_PACRJ_WP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP6))) 07389 07390 /*! @brief Format value for bitfield AIPS_PACRJ_WP6. */ 07391 #define BF_AIPS_PACRJ_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP6) & BM_AIPS_PACRJ_WP6) 07392 07393 /*! @brief Set the WP6 field to a new value. */ 07394 #define BW_AIPS_PACRJ_WP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP6), v)) 07395 /*@}*/ 07396 07397 /*! 07398 * @name Register AIPS_PACRJ, field SP6[6] (RW) 07399 * 07400 * Determines whether the peripheral requires supervisor privilege level for 07401 * accesses. When this field is set, the master privilege level must indicate the 07402 * supervisor access attribute, and the MPRx[MPLn] control field for the master 07403 * must be set. If not, access terminates with an error response and no peripheral 07404 * access initiates. 07405 * 07406 * Values: 07407 * - 0 - This peripheral does not require supervisor privilege level for 07408 * accesses. 07409 * - 1 - This peripheral requires supervisor privilege level for accesses. 07410 */ 07411 /*@{*/ 07412 #define BP_AIPS_PACRJ_SP6 (6U) /*!< Bit position for AIPS_PACRJ_SP6. */ 07413 #define BM_AIPS_PACRJ_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRJ_SP6. */ 07414 #define BS_AIPS_PACRJ_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP6. */ 07415 07416 /*! @brief Read current value of the AIPS_PACRJ_SP6 field. */ 07417 #define BR_AIPS_PACRJ_SP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP6))) 07418 07419 /*! @brief Format value for bitfield AIPS_PACRJ_SP6. */ 07420 #define BF_AIPS_PACRJ_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP6) & BM_AIPS_PACRJ_SP6) 07421 07422 /*! @brief Set the SP6 field to a new value. */ 07423 #define BW_AIPS_PACRJ_SP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP6), v)) 07424 /*@}*/ 07425 07426 /*! 07427 * @name Register AIPS_PACRJ, field TP5[8] (RW) 07428 * 07429 * Determines whether the peripheral allows accesses from an untrusted master. 07430 * When this field is set and an access is attempted by an untrusted master, the 07431 * access terminates with an error response and no peripheral access initiates. 07432 * 07433 * Values: 07434 * - 0 - Accesses from an untrusted master are allowed. 07435 * - 1 - Accesses from an untrusted master are not allowed. 07436 */ 07437 /*@{*/ 07438 #define BP_AIPS_PACRJ_TP5 (8U) /*!< Bit position for AIPS_PACRJ_TP5. */ 07439 #define BM_AIPS_PACRJ_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRJ_TP5. */ 07440 #define BS_AIPS_PACRJ_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP5. */ 07441 07442 /*! @brief Read current value of the AIPS_PACRJ_TP5 field. */ 07443 #define BR_AIPS_PACRJ_TP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP5))) 07444 07445 /*! @brief Format value for bitfield AIPS_PACRJ_TP5. */ 07446 #define BF_AIPS_PACRJ_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP5) & BM_AIPS_PACRJ_TP5) 07447 07448 /*! @brief Set the TP5 field to a new value. */ 07449 #define BW_AIPS_PACRJ_TP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP5), v)) 07450 /*@}*/ 07451 07452 /*! 07453 * @name Register AIPS_PACRJ, field WP5[9] (RW) 07454 * 07455 * Determines whether the peripheral allows write accesses. When this field is 07456 * set and a write access is attempted, access terminates with an error response 07457 * and no peripheral access initiates. 07458 * 07459 * Values: 07460 * - 0 - This peripheral allows write accesses. 07461 * - 1 - This peripheral is write protected. 07462 */ 07463 /*@{*/ 07464 #define BP_AIPS_PACRJ_WP5 (9U) /*!< Bit position for AIPS_PACRJ_WP5. */ 07465 #define BM_AIPS_PACRJ_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRJ_WP5. */ 07466 #define BS_AIPS_PACRJ_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP5. */ 07467 07468 /*! @brief Read current value of the AIPS_PACRJ_WP5 field. */ 07469 #define BR_AIPS_PACRJ_WP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP5))) 07470 07471 /*! @brief Format value for bitfield AIPS_PACRJ_WP5. */ 07472 #define BF_AIPS_PACRJ_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP5) & BM_AIPS_PACRJ_WP5) 07473 07474 /*! @brief Set the WP5 field to a new value. */ 07475 #define BW_AIPS_PACRJ_WP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP5), v)) 07476 /*@}*/ 07477 07478 /*! 07479 * @name Register AIPS_PACRJ, field SP5[10] (RW) 07480 * 07481 * Determines whether the peripheral requires supervisor privilege level for 07482 * accesses. When this field is set, the master privilege level must indicate the 07483 * supervisor access attribute, and the MPRx[MPLn] control field for the master 07484 * must be set. If not, access terminates with an error response and no peripheral 07485 * access initiates. 07486 * 07487 * Values: 07488 * - 0 - This peripheral does not require supervisor privilege level for 07489 * accesses. 07490 * - 1 - This peripheral requires supervisor privilege level for accesses. 07491 */ 07492 /*@{*/ 07493 #define BP_AIPS_PACRJ_SP5 (10U) /*!< Bit position for AIPS_PACRJ_SP5. */ 07494 #define BM_AIPS_PACRJ_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRJ_SP5. */ 07495 #define BS_AIPS_PACRJ_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP5. */ 07496 07497 /*! @brief Read current value of the AIPS_PACRJ_SP5 field. */ 07498 #define BR_AIPS_PACRJ_SP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP5))) 07499 07500 /*! @brief Format value for bitfield AIPS_PACRJ_SP5. */ 07501 #define BF_AIPS_PACRJ_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP5) & BM_AIPS_PACRJ_SP5) 07502 07503 /*! @brief Set the SP5 field to a new value. */ 07504 #define BW_AIPS_PACRJ_SP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP5), v)) 07505 /*@}*/ 07506 07507 /*! 07508 * @name Register AIPS_PACRJ, field TP4[12] (RW) 07509 * 07510 * Determines whether the peripheral allows accesses from an untrusted master. 07511 * When this bit is set and an access is attempted by an untrusted master, the 07512 * access terminates with an error response and no peripheral access initiates. 07513 * 07514 * Values: 07515 * - 0 - Accesses from an untrusted master are allowed. 07516 * - 1 - Accesses from an untrusted master are not allowed. 07517 */ 07518 /*@{*/ 07519 #define BP_AIPS_PACRJ_TP4 (12U) /*!< Bit position for AIPS_PACRJ_TP4. */ 07520 #define BM_AIPS_PACRJ_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRJ_TP4. */ 07521 #define BS_AIPS_PACRJ_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP4. */ 07522 07523 /*! @brief Read current value of the AIPS_PACRJ_TP4 field. */ 07524 #define BR_AIPS_PACRJ_TP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP4))) 07525 07526 /*! @brief Format value for bitfield AIPS_PACRJ_TP4. */ 07527 #define BF_AIPS_PACRJ_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP4) & BM_AIPS_PACRJ_TP4) 07528 07529 /*! @brief Set the TP4 field to a new value. */ 07530 #define BW_AIPS_PACRJ_TP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP4), v)) 07531 /*@}*/ 07532 07533 /*! 07534 * @name Register AIPS_PACRJ, field WP4[13] (RW) 07535 * 07536 * Determines whether the peripheral allows write accesses. When this field is 07537 * set and a write access is attempted, access terminates with an error response 07538 * and no peripheral access initiates. 07539 * 07540 * Values: 07541 * - 0 - This peripheral allows write accesses. 07542 * - 1 - This peripheral is write protected. 07543 */ 07544 /*@{*/ 07545 #define BP_AIPS_PACRJ_WP4 (13U) /*!< Bit position for AIPS_PACRJ_WP4. */ 07546 #define BM_AIPS_PACRJ_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRJ_WP4. */ 07547 #define BS_AIPS_PACRJ_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP4. */ 07548 07549 /*! @brief Read current value of the AIPS_PACRJ_WP4 field. */ 07550 #define BR_AIPS_PACRJ_WP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP4))) 07551 07552 /*! @brief Format value for bitfield AIPS_PACRJ_WP4. */ 07553 #define BF_AIPS_PACRJ_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP4) & BM_AIPS_PACRJ_WP4) 07554 07555 /*! @brief Set the WP4 field to a new value. */ 07556 #define BW_AIPS_PACRJ_WP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP4), v)) 07557 /*@}*/ 07558 07559 /*! 07560 * @name Register AIPS_PACRJ, field SP4[14] (RW) 07561 * 07562 * Determines whether the peripheral requires supervisor privilege level for 07563 * access. When this bit is set, the master privilege level must indicate the 07564 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 07565 * set. If not, access terminates with an error response and no peripheral access 07566 * initiates. 07567 * 07568 * Values: 07569 * - 0 - This peripheral does not require supervisor privilege level for 07570 * accesses. 07571 * - 1 - This peripheral requires supervisor privilege level for accesses. 07572 */ 07573 /*@{*/ 07574 #define BP_AIPS_PACRJ_SP4 (14U) /*!< Bit position for AIPS_PACRJ_SP4. */ 07575 #define BM_AIPS_PACRJ_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRJ_SP4. */ 07576 #define BS_AIPS_PACRJ_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP4. */ 07577 07578 /*! @brief Read current value of the AIPS_PACRJ_SP4 field. */ 07579 #define BR_AIPS_PACRJ_SP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP4))) 07580 07581 /*! @brief Format value for bitfield AIPS_PACRJ_SP4. */ 07582 #define BF_AIPS_PACRJ_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP4) & BM_AIPS_PACRJ_SP4) 07583 07584 /*! @brief Set the SP4 field to a new value. */ 07585 #define BW_AIPS_PACRJ_SP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP4), v)) 07586 /*@}*/ 07587 07588 /*! 07589 * @name Register AIPS_PACRJ, field TP3[16] (RW) 07590 * 07591 * Determines whether the peripheral allows accesses from an untrusted master. 07592 * When this field is set and an access is attempted by an untrusted master, the 07593 * access terminates with an error response and no peripheral access initiates. 07594 * 07595 * Values: 07596 * - 0 - Accesses from an untrusted master are allowed. 07597 * - 1 - Accesses from an untrusted master are not allowed. 07598 */ 07599 /*@{*/ 07600 #define BP_AIPS_PACRJ_TP3 (16U) /*!< Bit position for AIPS_PACRJ_TP3. */ 07601 #define BM_AIPS_PACRJ_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRJ_TP3. */ 07602 #define BS_AIPS_PACRJ_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP3. */ 07603 07604 /*! @brief Read current value of the AIPS_PACRJ_TP3 field. */ 07605 #define BR_AIPS_PACRJ_TP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP3))) 07606 07607 /*! @brief Format value for bitfield AIPS_PACRJ_TP3. */ 07608 #define BF_AIPS_PACRJ_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP3) & BM_AIPS_PACRJ_TP3) 07609 07610 /*! @brief Set the TP3 field to a new value. */ 07611 #define BW_AIPS_PACRJ_TP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP3), v)) 07612 /*@}*/ 07613 07614 /*! 07615 * @name Register AIPS_PACRJ, field WP3[17] (RW) 07616 * 07617 * Determines whether the peripheral allows write accesss. When this bit is set 07618 * and a write access is attempted, access terminates with an error response and 07619 * no peripheral access initiates. 07620 * 07621 * Values: 07622 * - 0 - This peripheral allows write accesses. 07623 * - 1 - This peripheral is write protected. 07624 */ 07625 /*@{*/ 07626 #define BP_AIPS_PACRJ_WP3 (17U) /*!< Bit position for AIPS_PACRJ_WP3. */ 07627 #define BM_AIPS_PACRJ_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRJ_WP3. */ 07628 #define BS_AIPS_PACRJ_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP3. */ 07629 07630 /*! @brief Read current value of the AIPS_PACRJ_WP3 field. */ 07631 #define BR_AIPS_PACRJ_WP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP3))) 07632 07633 /*! @brief Format value for bitfield AIPS_PACRJ_WP3. */ 07634 #define BF_AIPS_PACRJ_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP3) & BM_AIPS_PACRJ_WP3) 07635 07636 /*! @brief Set the WP3 field to a new value. */ 07637 #define BW_AIPS_PACRJ_WP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP3), v)) 07638 /*@}*/ 07639 07640 /*! 07641 * @name Register AIPS_PACRJ, field SP3[18] (RW) 07642 * 07643 * Determines whether the peripheral requires supervisor privilege level for 07644 * accesses. When this field is set, the master privilege level must indicate the 07645 * supervisor access attribute, and the MPRx[MPLn] control field for the master 07646 * must be set. If not, access terminates with an error response and no peripheral 07647 * access initiates. 07648 * 07649 * Values: 07650 * - 0 - This peripheral does not require supervisor privilege level for 07651 * accesses. 07652 * - 1 - This peripheral requires supervisor privilege level for accesses. 07653 */ 07654 /*@{*/ 07655 #define BP_AIPS_PACRJ_SP3 (18U) /*!< Bit position for AIPS_PACRJ_SP3. */ 07656 #define BM_AIPS_PACRJ_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRJ_SP3. */ 07657 #define BS_AIPS_PACRJ_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP3. */ 07658 07659 /*! @brief Read current value of the AIPS_PACRJ_SP3 field. */ 07660 #define BR_AIPS_PACRJ_SP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP3))) 07661 07662 /*! @brief Format value for bitfield AIPS_PACRJ_SP3. */ 07663 #define BF_AIPS_PACRJ_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP3) & BM_AIPS_PACRJ_SP3) 07664 07665 /*! @brief Set the SP3 field to a new value. */ 07666 #define BW_AIPS_PACRJ_SP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP3), v)) 07667 /*@}*/ 07668 07669 /*! 07670 * @name Register AIPS_PACRJ, field TP2[20] (RW) 07671 * 07672 * Determines whether the peripheral allows accesses from an untrusted master. 07673 * When this bit is set and an access is attempted by an untrusted master, the 07674 * access terminates with an error response and no peripheral access initiates. 07675 * 07676 * Values: 07677 * - 0 - Accesses from an untrusted master are allowed. 07678 * - 1 - Accesses from an untrusted master are not allowed. 07679 */ 07680 /*@{*/ 07681 #define BP_AIPS_PACRJ_TP2 (20U) /*!< Bit position for AIPS_PACRJ_TP2. */ 07682 #define BM_AIPS_PACRJ_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRJ_TP2. */ 07683 #define BS_AIPS_PACRJ_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP2. */ 07684 07685 /*! @brief Read current value of the AIPS_PACRJ_TP2 field. */ 07686 #define BR_AIPS_PACRJ_TP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP2))) 07687 07688 /*! @brief Format value for bitfield AIPS_PACRJ_TP2. */ 07689 #define BF_AIPS_PACRJ_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP2) & BM_AIPS_PACRJ_TP2) 07690 07691 /*! @brief Set the TP2 field to a new value. */ 07692 #define BW_AIPS_PACRJ_TP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP2), v)) 07693 /*@}*/ 07694 07695 /*! 07696 * @name Register AIPS_PACRJ, field WP2[21] (RW) 07697 * 07698 * Determines whether the peripheral allows write accesses. When this field is 07699 * set and a write access is attempted, access terminates with an error response 07700 * and no peripheral access initiates. 07701 * 07702 * Values: 07703 * - 0 - This peripheral allows write accesses. 07704 * - 1 - This peripheral is write protected. 07705 */ 07706 /*@{*/ 07707 #define BP_AIPS_PACRJ_WP2 (21U) /*!< Bit position for AIPS_PACRJ_WP2. */ 07708 #define BM_AIPS_PACRJ_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRJ_WP2. */ 07709 #define BS_AIPS_PACRJ_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP2. */ 07710 07711 /*! @brief Read current value of the AIPS_PACRJ_WP2 field. */ 07712 #define BR_AIPS_PACRJ_WP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP2))) 07713 07714 /*! @brief Format value for bitfield AIPS_PACRJ_WP2. */ 07715 #define BF_AIPS_PACRJ_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP2) & BM_AIPS_PACRJ_WP2) 07716 07717 /*! @brief Set the WP2 field to a new value. */ 07718 #define BW_AIPS_PACRJ_WP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP2), v)) 07719 /*@}*/ 07720 07721 /*! 07722 * @name Register AIPS_PACRJ, field SP2[22] (RW) 07723 * 07724 * Determines whether the peripheral requires supervisor privilege level for 07725 * access. When this bit is set, the master privilege level must indicate the 07726 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 07727 * set. If not, access terminates with an error response and no peripheral access 07728 * initiates. 07729 * 07730 * Values: 07731 * - 0 - This peripheral does not require supervisor privilege level for 07732 * accesses. 07733 * - 1 - This peripheral requires supervisor privilege level for accesses. 07734 */ 07735 /*@{*/ 07736 #define BP_AIPS_PACRJ_SP2 (22U) /*!< Bit position for AIPS_PACRJ_SP2. */ 07737 #define BM_AIPS_PACRJ_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRJ_SP2. */ 07738 #define BS_AIPS_PACRJ_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP2. */ 07739 07740 /*! @brief Read current value of the AIPS_PACRJ_SP2 field. */ 07741 #define BR_AIPS_PACRJ_SP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP2))) 07742 07743 /*! @brief Format value for bitfield AIPS_PACRJ_SP2. */ 07744 #define BF_AIPS_PACRJ_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP2) & BM_AIPS_PACRJ_SP2) 07745 07746 /*! @brief Set the SP2 field to a new value. */ 07747 #define BW_AIPS_PACRJ_SP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP2), v)) 07748 /*@}*/ 07749 07750 /*! 07751 * @name Register AIPS_PACRJ, field TP1[24] (RW) 07752 * 07753 * Determines whether the peripheral allows accesses from an untrusted master. 07754 * When this field is set and an access is attempted by an untrusted master, the 07755 * access terminates with an error response and no peripheral access initiates. 07756 * 07757 * Values: 07758 * - 0 - Accesses from an untrusted master are allowed. 07759 * - 1 - Accesses from an untrusted master are not allowed. 07760 */ 07761 /*@{*/ 07762 #define BP_AIPS_PACRJ_TP1 (24U) /*!< Bit position for AIPS_PACRJ_TP1. */ 07763 #define BM_AIPS_PACRJ_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRJ_TP1. */ 07764 #define BS_AIPS_PACRJ_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP1. */ 07765 07766 /*! @brief Read current value of the AIPS_PACRJ_TP1 field. */ 07767 #define BR_AIPS_PACRJ_TP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP1))) 07768 07769 /*! @brief Format value for bitfield AIPS_PACRJ_TP1. */ 07770 #define BF_AIPS_PACRJ_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP1) & BM_AIPS_PACRJ_TP1) 07771 07772 /*! @brief Set the TP1 field to a new value. */ 07773 #define BW_AIPS_PACRJ_TP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP1), v)) 07774 /*@}*/ 07775 07776 /*! 07777 * @name Register AIPS_PACRJ, field WP1[25] (RW) 07778 * 07779 * Determines whether the peripheral allows write accesses. When this field is 07780 * set and a write access is attempted, access terminates with an error response 07781 * and no peripheral access initiates. 07782 * 07783 * Values: 07784 * - 0 - This peripheral allows write accesses. 07785 * - 1 - This peripheral is write protected. 07786 */ 07787 /*@{*/ 07788 #define BP_AIPS_PACRJ_WP1 (25U) /*!< Bit position for AIPS_PACRJ_WP1. */ 07789 #define BM_AIPS_PACRJ_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRJ_WP1. */ 07790 #define BS_AIPS_PACRJ_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP1. */ 07791 07792 /*! @brief Read current value of the AIPS_PACRJ_WP1 field. */ 07793 #define BR_AIPS_PACRJ_WP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP1))) 07794 07795 /*! @brief Format value for bitfield AIPS_PACRJ_WP1. */ 07796 #define BF_AIPS_PACRJ_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP1) & BM_AIPS_PACRJ_WP1) 07797 07798 /*! @brief Set the WP1 field to a new value. */ 07799 #define BW_AIPS_PACRJ_WP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP1), v)) 07800 /*@}*/ 07801 07802 /*! 07803 * @name Register AIPS_PACRJ, field SP1[26] (RW) 07804 * 07805 * Determines whether the peripheral requires supervisor privilege level for 07806 * access. When this field is set, the master privilege level must indicate the 07807 * supervisor access attribute, and the MPRx[MPLn] control field for the master must 07808 * be set. If not, access terminates with an error response and no peripheral 07809 * access initiates. 07810 * 07811 * Values: 07812 * - 0 - This peripheral does not require supervisor privilege level for 07813 * accesses. 07814 * - 1 - This peripheral requires supervisor privilege level for accesses. 07815 */ 07816 /*@{*/ 07817 #define BP_AIPS_PACRJ_SP1 (26U) /*!< Bit position for AIPS_PACRJ_SP1. */ 07818 #define BM_AIPS_PACRJ_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRJ_SP1. */ 07819 #define BS_AIPS_PACRJ_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP1. */ 07820 07821 /*! @brief Read current value of the AIPS_PACRJ_SP1 field. */ 07822 #define BR_AIPS_PACRJ_SP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP1))) 07823 07824 /*! @brief Format value for bitfield AIPS_PACRJ_SP1. */ 07825 #define BF_AIPS_PACRJ_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP1) & BM_AIPS_PACRJ_SP1) 07826 07827 /*! @brief Set the SP1 field to a new value. */ 07828 #define BW_AIPS_PACRJ_SP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP1), v)) 07829 /*@}*/ 07830 07831 /*! 07832 * @name Register AIPS_PACRJ, field TP0[28] (RW) 07833 * 07834 * Determines whether the peripheral allows accesses from an untrusted master. 07835 * When this bit is set and an access is attempted by an untrusted master, the 07836 * access terminates with an error response and no peripheral access initiates. 07837 * 07838 * Values: 07839 * - 0 - Accesses from an untrusted master are allowed. 07840 * - 1 - Accesses from an untrusted master are not allowed. 07841 */ 07842 /*@{*/ 07843 #define BP_AIPS_PACRJ_TP0 (28U) /*!< Bit position for AIPS_PACRJ_TP0. */ 07844 #define BM_AIPS_PACRJ_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRJ_TP0. */ 07845 #define BS_AIPS_PACRJ_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRJ_TP0. */ 07846 07847 /*! @brief Read current value of the AIPS_PACRJ_TP0 field. */ 07848 #define BR_AIPS_PACRJ_TP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP0))) 07849 07850 /*! @brief Format value for bitfield AIPS_PACRJ_TP0. */ 07851 #define BF_AIPS_PACRJ_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_TP0) & BM_AIPS_PACRJ_TP0) 07852 07853 /*! @brief Set the TP0 field to a new value. */ 07854 #define BW_AIPS_PACRJ_TP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_TP0), v)) 07855 /*@}*/ 07856 07857 /*! 07858 * @name Register AIPS_PACRJ, field WP0[29] (RW) 07859 * 07860 * Determines whether the peripheral allows write accesses. When this field is 07861 * set and a write access is attempted, access terminates with an error response 07862 * and no peripheral access initiates. 07863 * 07864 * Values: 07865 * - 0 - This peripheral allows write accesses. 07866 * - 1 - This peripheral is write protected. 07867 */ 07868 /*@{*/ 07869 #define BP_AIPS_PACRJ_WP0 (29U) /*!< Bit position for AIPS_PACRJ_WP0. */ 07870 #define BM_AIPS_PACRJ_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRJ_WP0. */ 07871 #define BS_AIPS_PACRJ_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRJ_WP0. */ 07872 07873 /*! @brief Read current value of the AIPS_PACRJ_WP0 field. */ 07874 #define BR_AIPS_PACRJ_WP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP0))) 07875 07876 /*! @brief Format value for bitfield AIPS_PACRJ_WP0. */ 07877 #define BF_AIPS_PACRJ_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_WP0) & BM_AIPS_PACRJ_WP0) 07878 07879 /*! @brief Set the WP0 field to a new value. */ 07880 #define BW_AIPS_PACRJ_WP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_WP0), v)) 07881 /*@}*/ 07882 07883 /*! 07884 * @name Register AIPS_PACRJ, field SP0[30] (RW) 07885 * 07886 * Determines whether the peripheral requires supervisor privilege level for 07887 * accesses. When this field is set, the master privilege level must indicate the 07888 * supervisor access attribute, and the MPRx[MPLn] control field for the master 07889 * must be set. If not, access terminates with an error response and no peripheral 07890 * access initiates. 07891 * 07892 * Values: 07893 * - 0 - This peripheral does not require supervisor privilege level for 07894 * accesses. 07895 * - 1 - This peripheral requires supervisor privilege level for accesses. 07896 */ 07897 /*@{*/ 07898 #define BP_AIPS_PACRJ_SP0 (30U) /*!< Bit position for AIPS_PACRJ_SP0. */ 07899 #define BM_AIPS_PACRJ_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRJ_SP0. */ 07900 #define BS_AIPS_PACRJ_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRJ_SP0. */ 07901 07902 /*! @brief Read current value of the AIPS_PACRJ_SP0 field. */ 07903 #define BR_AIPS_PACRJ_SP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP0))) 07904 07905 /*! @brief Format value for bitfield AIPS_PACRJ_SP0. */ 07906 #define BF_AIPS_PACRJ_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRJ_SP0) & BM_AIPS_PACRJ_SP0) 07907 07908 /*! @brief Set the SP0 field to a new value. */ 07909 #define BW_AIPS_PACRJ_SP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRJ_ADDR(x), BP_AIPS_PACRJ_SP0), v)) 07910 /*@}*/ 07911 07912 /******************************************************************************* 07913 * HW_AIPS_PACRK - Peripheral Access Control Register 07914 ******************************************************************************/ 07915 07916 /*! 07917 * @brief HW_AIPS_PACRK - Peripheral Access Control Register (RW) 07918 * 07919 * Reset value: 0x44444444U 07920 * 07921 * This section describes PACR registers E-P, which control peripheral slots 07922 * 32-127. See PACRPeripheral Access Control Register for the description of these 07923 * registers. 07924 */ 07925 typedef union _hw_aips_pacrk 07926 { 07927 uint32_t U; 07928 struct _hw_aips_pacrk_bitfields 07929 { 07930 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 07931 uint32_t WP7 : 1; /*!< [1] Write Protect */ 07932 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 07933 uint32_t RESERVED0 : 1; /*!< [3] */ 07934 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 07935 uint32_t WP6 : 1; /*!< [5] Write Protect */ 07936 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 07937 uint32_t RESERVED1 : 1; /*!< [7] */ 07938 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 07939 uint32_t WP5 : 1; /*!< [9] Write Protect */ 07940 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 07941 uint32_t RESERVED2 : 1; /*!< [11] */ 07942 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 07943 uint32_t WP4 : 1; /*!< [13] Write Protect */ 07944 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 07945 uint32_t RESERVED3 : 1; /*!< [15] */ 07946 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 07947 uint32_t WP3 : 1; /*!< [17] Write Protect */ 07948 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 07949 uint32_t RESERVED4 : 1; /*!< [19] */ 07950 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 07951 uint32_t WP2 : 1; /*!< [21] Write Protect */ 07952 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 07953 uint32_t RESERVED5 : 1; /*!< [23] */ 07954 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 07955 uint32_t WP1 : 1; /*!< [25] Write Protect */ 07956 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 07957 uint32_t RESERVED6 : 1; /*!< [27] */ 07958 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 07959 uint32_t WP0 : 1; /*!< [29] Write Protect */ 07960 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 07961 uint32_t RESERVED7 : 1; /*!< [31] */ 07962 } B; 07963 } hw_aips_pacrk_t; 07964 07965 /*! 07966 * @name Constants and macros for entire AIPS_PACRK register 07967 */ 07968 /*@{*/ 07969 #define HW_AIPS_PACRK_ADDR(x) ((x) + 0x58U) 07970 07971 #define HW_AIPS_PACRK(x) (*(__IO hw_aips_pacrk_t *) HW_AIPS_PACRK_ADDR(x)) 07972 #define HW_AIPS_PACRK_RD(x) (ADDRESS_READ(hw_aips_pacrk_t, HW_AIPS_PACRK_ADDR(x))) 07973 #define HW_AIPS_PACRK_WR(x, v) (ADDRESS_WRITE(hw_aips_pacrk_t, HW_AIPS_PACRK_ADDR(x), v)) 07974 #define HW_AIPS_PACRK_SET(x, v) (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) | (v))) 07975 #define HW_AIPS_PACRK_CLR(x, v) (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) & ~(v))) 07976 #define HW_AIPS_PACRK_TOG(x, v) (HW_AIPS_PACRK_WR(x, HW_AIPS_PACRK_RD(x) ^ (v))) 07977 /*@}*/ 07978 07979 /* 07980 * Constants & macros for individual AIPS_PACRK bitfields 07981 */ 07982 07983 /*! 07984 * @name Register AIPS_PACRK, field TP7[0] (RW) 07985 * 07986 * Determines whether the peripheral allows accesses from an untrusted master. 07987 * When this field is set and an access is attempted by an untrusted master, the 07988 * access terminates with an error response and no peripheral access initiates. 07989 * 07990 * Values: 07991 * - 0 - Accesses from an untrusted master are allowed. 07992 * - 1 - Accesses from an untrusted master are not allowed. 07993 */ 07994 /*@{*/ 07995 #define BP_AIPS_PACRK_TP7 (0U) /*!< Bit position for AIPS_PACRK_TP7. */ 07996 #define BM_AIPS_PACRK_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRK_TP7. */ 07997 #define BS_AIPS_PACRK_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP7. */ 07998 07999 /*! @brief Read current value of the AIPS_PACRK_TP7 field. */ 08000 #define BR_AIPS_PACRK_TP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP7))) 08001 08002 /*! @brief Format value for bitfield AIPS_PACRK_TP7. */ 08003 #define BF_AIPS_PACRK_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP7) & BM_AIPS_PACRK_TP7) 08004 08005 /*! @brief Set the TP7 field to a new value. */ 08006 #define BW_AIPS_PACRK_TP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP7), v)) 08007 /*@}*/ 08008 08009 /*! 08010 * @name Register AIPS_PACRK, field WP7[1] (RW) 08011 * 08012 * Determines whether the peripheral allows write accesses. When this field is 08013 * set and a write access is attempted, access terminates with an error response 08014 * and no peripheral access initiates. 08015 * 08016 * Values: 08017 * - 0 - This peripheral allows write accesses. 08018 * - 1 - This peripheral is write protected. 08019 */ 08020 /*@{*/ 08021 #define BP_AIPS_PACRK_WP7 (1U) /*!< Bit position for AIPS_PACRK_WP7. */ 08022 #define BM_AIPS_PACRK_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRK_WP7. */ 08023 #define BS_AIPS_PACRK_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP7. */ 08024 08025 /*! @brief Read current value of the AIPS_PACRK_WP7 field. */ 08026 #define BR_AIPS_PACRK_WP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP7))) 08027 08028 /*! @brief Format value for bitfield AIPS_PACRK_WP7. */ 08029 #define BF_AIPS_PACRK_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP7) & BM_AIPS_PACRK_WP7) 08030 08031 /*! @brief Set the WP7 field to a new value. */ 08032 #define BW_AIPS_PACRK_WP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP7), v)) 08033 /*@}*/ 08034 08035 /*! 08036 * @name Register AIPS_PACRK, field SP7[2] (RW) 08037 * 08038 * Determines whether the peripheral requires supervisor privilege level for 08039 * accesses. When this field is set, the master privilege level must indicate the 08040 * supervisor access attribute, and the MPRx[MPLn] control field for the master 08041 * must be set. If not, access terminates with an error response and no peripheral 08042 * access initiates. 08043 * 08044 * Values: 08045 * - 0 - This peripheral does not require supervisor privilege level for 08046 * accesses. 08047 * - 1 - This peripheral requires supervisor privilege level for accesses. 08048 */ 08049 /*@{*/ 08050 #define BP_AIPS_PACRK_SP7 (2U) /*!< Bit position for AIPS_PACRK_SP7. */ 08051 #define BM_AIPS_PACRK_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRK_SP7. */ 08052 #define BS_AIPS_PACRK_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP7. */ 08053 08054 /*! @brief Read current value of the AIPS_PACRK_SP7 field. */ 08055 #define BR_AIPS_PACRK_SP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP7))) 08056 08057 /*! @brief Format value for bitfield AIPS_PACRK_SP7. */ 08058 #define BF_AIPS_PACRK_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP7) & BM_AIPS_PACRK_SP7) 08059 08060 /*! @brief Set the SP7 field to a new value. */ 08061 #define BW_AIPS_PACRK_SP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP7), v)) 08062 /*@}*/ 08063 08064 /*! 08065 * @name Register AIPS_PACRK, field TP6[4] (RW) 08066 * 08067 * Determines whether the peripheral allows accesses from an untrusted master. 08068 * When this field is set and an access is attempted by an untrusted master, the 08069 * access terminates with an error response and no peripheral access initiates. 08070 * 08071 * Values: 08072 * - 0 - Accesses from an untrusted master are allowed. 08073 * - 1 - Accesses from an untrusted master are not allowed. 08074 */ 08075 /*@{*/ 08076 #define BP_AIPS_PACRK_TP6 (4U) /*!< Bit position for AIPS_PACRK_TP6. */ 08077 #define BM_AIPS_PACRK_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRK_TP6. */ 08078 #define BS_AIPS_PACRK_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP6. */ 08079 08080 /*! @brief Read current value of the AIPS_PACRK_TP6 field. */ 08081 #define BR_AIPS_PACRK_TP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP6))) 08082 08083 /*! @brief Format value for bitfield AIPS_PACRK_TP6. */ 08084 #define BF_AIPS_PACRK_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP6) & BM_AIPS_PACRK_TP6) 08085 08086 /*! @brief Set the TP6 field to a new value. */ 08087 #define BW_AIPS_PACRK_TP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP6), v)) 08088 /*@}*/ 08089 08090 /*! 08091 * @name Register AIPS_PACRK, field WP6[5] (RW) 08092 * 08093 * Determines whether the peripheral allows write accesses. When this field is 08094 * set and a write access is attempted, access terminates with an error response 08095 * and no peripheral access initiates. 08096 * 08097 * Values: 08098 * - 0 - This peripheral allows write accesses. 08099 * - 1 - This peripheral is write protected. 08100 */ 08101 /*@{*/ 08102 #define BP_AIPS_PACRK_WP6 (5U) /*!< Bit position for AIPS_PACRK_WP6. */ 08103 #define BM_AIPS_PACRK_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRK_WP6. */ 08104 #define BS_AIPS_PACRK_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP6. */ 08105 08106 /*! @brief Read current value of the AIPS_PACRK_WP6 field. */ 08107 #define BR_AIPS_PACRK_WP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP6))) 08108 08109 /*! @brief Format value for bitfield AIPS_PACRK_WP6. */ 08110 #define BF_AIPS_PACRK_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP6) & BM_AIPS_PACRK_WP6) 08111 08112 /*! @brief Set the WP6 field to a new value. */ 08113 #define BW_AIPS_PACRK_WP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP6), v)) 08114 /*@}*/ 08115 08116 /*! 08117 * @name Register AIPS_PACRK, field SP6[6] (RW) 08118 * 08119 * Determines whether the peripheral requires supervisor privilege level for 08120 * accesses. When this field is set, the master privilege level must indicate the 08121 * supervisor access attribute, and the MPRx[MPLn] control field for the master 08122 * must be set. If not, access terminates with an error response and no peripheral 08123 * access initiates. 08124 * 08125 * Values: 08126 * - 0 - This peripheral does not require supervisor privilege level for 08127 * accesses. 08128 * - 1 - This peripheral requires supervisor privilege level for accesses. 08129 */ 08130 /*@{*/ 08131 #define BP_AIPS_PACRK_SP6 (6U) /*!< Bit position for AIPS_PACRK_SP6. */ 08132 #define BM_AIPS_PACRK_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRK_SP6. */ 08133 #define BS_AIPS_PACRK_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP6. */ 08134 08135 /*! @brief Read current value of the AIPS_PACRK_SP6 field. */ 08136 #define BR_AIPS_PACRK_SP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP6))) 08137 08138 /*! @brief Format value for bitfield AIPS_PACRK_SP6. */ 08139 #define BF_AIPS_PACRK_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP6) & BM_AIPS_PACRK_SP6) 08140 08141 /*! @brief Set the SP6 field to a new value. */ 08142 #define BW_AIPS_PACRK_SP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP6), v)) 08143 /*@}*/ 08144 08145 /*! 08146 * @name Register AIPS_PACRK, field TP5[8] (RW) 08147 * 08148 * Determines whether the peripheral allows accesses from an untrusted master. 08149 * When this field is set and an access is attempted by an untrusted master, the 08150 * access terminates with an error response and no peripheral access initiates. 08151 * 08152 * Values: 08153 * - 0 - Accesses from an untrusted master are allowed. 08154 * - 1 - Accesses from an untrusted master are not allowed. 08155 */ 08156 /*@{*/ 08157 #define BP_AIPS_PACRK_TP5 (8U) /*!< Bit position for AIPS_PACRK_TP5. */ 08158 #define BM_AIPS_PACRK_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRK_TP5. */ 08159 #define BS_AIPS_PACRK_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP5. */ 08160 08161 /*! @brief Read current value of the AIPS_PACRK_TP5 field. */ 08162 #define BR_AIPS_PACRK_TP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP5))) 08163 08164 /*! @brief Format value for bitfield AIPS_PACRK_TP5. */ 08165 #define BF_AIPS_PACRK_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP5) & BM_AIPS_PACRK_TP5) 08166 08167 /*! @brief Set the TP5 field to a new value. */ 08168 #define BW_AIPS_PACRK_TP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP5), v)) 08169 /*@}*/ 08170 08171 /*! 08172 * @name Register AIPS_PACRK, field WP5[9] (RW) 08173 * 08174 * Determines whether the peripheral allows write accesses. When this field is 08175 * set and a write access is attempted, access terminates with an error response 08176 * and no peripheral access initiates. 08177 * 08178 * Values: 08179 * - 0 - This peripheral allows write accesses. 08180 * - 1 - This peripheral is write protected. 08181 */ 08182 /*@{*/ 08183 #define BP_AIPS_PACRK_WP5 (9U) /*!< Bit position for AIPS_PACRK_WP5. */ 08184 #define BM_AIPS_PACRK_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRK_WP5. */ 08185 #define BS_AIPS_PACRK_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP5. */ 08186 08187 /*! @brief Read current value of the AIPS_PACRK_WP5 field. */ 08188 #define BR_AIPS_PACRK_WP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP5))) 08189 08190 /*! @brief Format value for bitfield AIPS_PACRK_WP5. */ 08191 #define BF_AIPS_PACRK_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP5) & BM_AIPS_PACRK_WP5) 08192 08193 /*! @brief Set the WP5 field to a new value. */ 08194 #define BW_AIPS_PACRK_WP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP5), v)) 08195 /*@}*/ 08196 08197 /*! 08198 * @name Register AIPS_PACRK, field SP5[10] (RW) 08199 * 08200 * Determines whether the peripheral requires supervisor privilege level for 08201 * accesses. When this field is set, the master privilege level must indicate the 08202 * supervisor access attribute, and the MPRx[MPLn] control field for the master 08203 * must be set. If not, access terminates with an error response and no peripheral 08204 * access initiates. 08205 * 08206 * Values: 08207 * - 0 - This peripheral does not require supervisor privilege level for 08208 * accesses. 08209 * - 1 - This peripheral requires supervisor privilege level for accesses. 08210 */ 08211 /*@{*/ 08212 #define BP_AIPS_PACRK_SP5 (10U) /*!< Bit position for AIPS_PACRK_SP5. */ 08213 #define BM_AIPS_PACRK_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRK_SP5. */ 08214 #define BS_AIPS_PACRK_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP5. */ 08215 08216 /*! @brief Read current value of the AIPS_PACRK_SP5 field. */ 08217 #define BR_AIPS_PACRK_SP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP5))) 08218 08219 /*! @brief Format value for bitfield AIPS_PACRK_SP5. */ 08220 #define BF_AIPS_PACRK_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP5) & BM_AIPS_PACRK_SP5) 08221 08222 /*! @brief Set the SP5 field to a new value. */ 08223 #define BW_AIPS_PACRK_SP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP5), v)) 08224 /*@}*/ 08225 08226 /*! 08227 * @name Register AIPS_PACRK, field TP4[12] (RW) 08228 * 08229 * Determines whether the peripheral allows accesses from an untrusted master. 08230 * When this bit is set and an access is attempted by an untrusted master, the 08231 * access terminates with an error response and no peripheral access initiates. 08232 * 08233 * Values: 08234 * - 0 - Accesses from an untrusted master are allowed. 08235 * - 1 - Accesses from an untrusted master are not allowed. 08236 */ 08237 /*@{*/ 08238 #define BP_AIPS_PACRK_TP4 (12U) /*!< Bit position for AIPS_PACRK_TP4. */ 08239 #define BM_AIPS_PACRK_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRK_TP4. */ 08240 #define BS_AIPS_PACRK_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP4. */ 08241 08242 /*! @brief Read current value of the AIPS_PACRK_TP4 field. */ 08243 #define BR_AIPS_PACRK_TP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP4))) 08244 08245 /*! @brief Format value for bitfield AIPS_PACRK_TP4. */ 08246 #define BF_AIPS_PACRK_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP4) & BM_AIPS_PACRK_TP4) 08247 08248 /*! @brief Set the TP4 field to a new value. */ 08249 #define BW_AIPS_PACRK_TP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP4), v)) 08250 /*@}*/ 08251 08252 /*! 08253 * @name Register AIPS_PACRK, field WP4[13] (RW) 08254 * 08255 * Determines whether the peripheral allows write accesses. When this field is 08256 * set and a write access is attempted, access terminates with an error response 08257 * and no peripheral access initiates. 08258 * 08259 * Values: 08260 * - 0 - This peripheral allows write accesses. 08261 * - 1 - This peripheral is write protected. 08262 */ 08263 /*@{*/ 08264 #define BP_AIPS_PACRK_WP4 (13U) /*!< Bit position for AIPS_PACRK_WP4. */ 08265 #define BM_AIPS_PACRK_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRK_WP4. */ 08266 #define BS_AIPS_PACRK_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP4. */ 08267 08268 /*! @brief Read current value of the AIPS_PACRK_WP4 field. */ 08269 #define BR_AIPS_PACRK_WP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP4))) 08270 08271 /*! @brief Format value for bitfield AIPS_PACRK_WP4. */ 08272 #define BF_AIPS_PACRK_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP4) & BM_AIPS_PACRK_WP4) 08273 08274 /*! @brief Set the WP4 field to a new value. */ 08275 #define BW_AIPS_PACRK_WP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP4), v)) 08276 /*@}*/ 08277 08278 /*! 08279 * @name Register AIPS_PACRK, field SP4[14] (RW) 08280 * 08281 * Determines whether the peripheral requires supervisor privilege level for 08282 * access. When this bit is set, the master privilege level must indicate the 08283 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 08284 * set. If not, access terminates with an error response and no peripheral access 08285 * initiates. 08286 * 08287 * Values: 08288 * - 0 - This peripheral does not require supervisor privilege level for 08289 * accesses. 08290 * - 1 - This peripheral requires supervisor privilege level for accesses. 08291 */ 08292 /*@{*/ 08293 #define BP_AIPS_PACRK_SP4 (14U) /*!< Bit position for AIPS_PACRK_SP4. */ 08294 #define BM_AIPS_PACRK_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRK_SP4. */ 08295 #define BS_AIPS_PACRK_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP4. */ 08296 08297 /*! @brief Read current value of the AIPS_PACRK_SP4 field. */ 08298 #define BR_AIPS_PACRK_SP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP4))) 08299 08300 /*! @brief Format value for bitfield AIPS_PACRK_SP4. */ 08301 #define BF_AIPS_PACRK_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP4) & BM_AIPS_PACRK_SP4) 08302 08303 /*! @brief Set the SP4 field to a new value. */ 08304 #define BW_AIPS_PACRK_SP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP4), v)) 08305 /*@}*/ 08306 08307 /*! 08308 * @name Register AIPS_PACRK, field TP3[16] (RW) 08309 * 08310 * Determines whether the peripheral allows accesses from an untrusted master. 08311 * When this field is set and an access is attempted by an untrusted master, the 08312 * access terminates with an error response and no peripheral access initiates. 08313 * 08314 * Values: 08315 * - 0 - Accesses from an untrusted master are allowed. 08316 * - 1 - Accesses from an untrusted master are not allowed. 08317 */ 08318 /*@{*/ 08319 #define BP_AIPS_PACRK_TP3 (16U) /*!< Bit position for AIPS_PACRK_TP3. */ 08320 #define BM_AIPS_PACRK_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRK_TP3. */ 08321 #define BS_AIPS_PACRK_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP3. */ 08322 08323 /*! @brief Read current value of the AIPS_PACRK_TP3 field. */ 08324 #define BR_AIPS_PACRK_TP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP3))) 08325 08326 /*! @brief Format value for bitfield AIPS_PACRK_TP3. */ 08327 #define BF_AIPS_PACRK_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP3) & BM_AIPS_PACRK_TP3) 08328 08329 /*! @brief Set the TP3 field to a new value. */ 08330 #define BW_AIPS_PACRK_TP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP3), v)) 08331 /*@}*/ 08332 08333 /*! 08334 * @name Register AIPS_PACRK, field WP3[17] (RW) 08335 * 08336 * Determines whether the peripheral allows write accesss. When this bit is set 08337 * and a write access is attempted, access terminates with an error response and 08338 * no peripheral access initiates. 08339 * 08340 * Values: 08341 * - 0 - This peripheral allows write accesses. 08342 * - 1 - This peripheral is write protected. 08343 */ 08344 /*@{*/ 08345 #define BP_AIPS_PACRK_WP3 (17U) /*!< Bit position for AIPS_PACRK_WP3. */ 08346 #define BM_AIPS_PACRK_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRK_WP3. */ 08347 #define BS_AIPS_PACRK_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP3. */ 08348 08349 /*! @brief Read current value of the AIPS_PACRK_WP3 field. */ 08350 #define BR_AIPS_PACRK_WP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP3))) 08351 08352 /*! @brief Format value for bitfield AIPS_PACRK_WP3. */ 08353 #define BF_AIPS_PACRK_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP3) & BM_AIPS_PACRK_WP3) 08354 08355 /*! @brief Set the WP3 field to a new value. */ 08356 #define BW_AIPS_PACRK_WP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP3), v)) 08357 /*@}*/ 08358 08359 /*! 08360 * @name Register AIPS_PACRK, field SP3[18] (RW) 08361 * 08362 * Determines whether the peripheral requires supervisor privilege level for 08363 * accesses. When this field is set, the master privilege level must indicate the 08364 * supervisor access attribute, and the MPRx[MPLn] control field for the master 08365 * must be set. If not, access terminates with an error response and no peripheral 08366 * access initiates. 08367 * 08368 * Values: 08369 * - 0 - This peripheral does not require supervisor privilege level for 08370 * accesses. 08371 * - 1 - This peripheral requires supervisor privilege level for accesses. 08372 */ 08373 /*@{*/ 08374 #define BP_AIPS_PACRK_SP3 (18U) /*!< Bit position for AIPS_PACRK_SP3. */ 08375 #define BM_AIPS_PACRK_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRK_SP3. */ 08376 #define BS_AIPS_PACRK_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP3. */ 08377 08378 /*! @brief Read current value of the AIPS_PACRK_SP3 field. */ 08379 #define BR_AIPS_PACRK_SP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP3))) 08380 08381 /*! @brief Format value for bitfield AIPS_PACRK_SP3. */ 08382 #define BF_AIPS_PACRK_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP3) & BM_AIPS_PACRK_SP3) 08383 08384 /*! @brief Set the SP3 field to a new value. */ 08385 #define BW_AIPS_PACRK_SP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP3), v)) 08386 /*@}*/ 08387 08388 /*! 08389 * @name Register AIPS_PACRK, field TP2[20] (RW) 08390 * 08391 * Determines whether the peripheral allows accesses from an untrusted master. 08392 * When this bit is set and an access is attempted by an untrusted master, the 08393 * access terminates with an error response and no peripheral access initiates. 08394 * 08395 * Values: 08396 * - 0 - Accesses from an untrusted master are allowed. 08397 * - 1 - Accesses from an untrusted master are not allowed. 08398 */ 08399 /*@{*/ 08400 #define BP_AIPS_PACRK_TP2 (20U) /*!< Bit position for AIPS_PACRK_TP2. */ 08401 #define BM_AIPS_PACRK_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRK_TP2. */ 08402 #define BS_AIPS_PACRK_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP2. */ 08403 08404 /*! @brief Read current value of the AIPS_PACRK_TP2 field. */ 08405 #define BR_AIPS_PACRK_TP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP2))) 08406 08407 /*! @brief Format value for bitfield AIPS_PACRK_TP2. */ 08408 #define BF_AIPS_PACRK_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP2) & BM_AIPS_PACRK_TP2) 08409 08410 /*! @brief Set the TP2 field to a new value. */ 08411 #define BW_AIPS_PACRK_TP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP2), v)) 08412 /*@}*/ 08413 08414 /*! 08415 * @name Register AIPS_PACRK, field WP2[21] (RW) 08416 * 08417 * Determines whether the peripheral allows write accesses. When this field is 08418 * set and a write access is attempted, access terminates with an error response 08419 * and no peripheral access initiates. 08420 * 08421 * Values: 08422 * - 0 - This peripheral allows write accesses. 08423 * - 1 - This peripheral is write protected. 08424 */ 08425 /*@{*/ 08426 #define BP_AIPS_PACRK_WP2 (21U) /*!< Bit position for AIPS_PACRK_WP2. */ 08427 #define BM_AIPS_PACRK_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRK_WP2. */ 08428 #define BS_AIPS_PACRK_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP2. */ 08429 08430 /*! @brief Read current value of the AIPS_PACRK_WP2 field. */ 08431 #define BR_AIPS_PACRK_WP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP2))) 08432 08433 /*! @brief Format value for bitfield AIPS_PACRK_WP2. */ 08434 #define BF_AIPS_PACRK_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP2) & BM_AIPS_PACRK_WP2) 08435 08436 /*! @brief Set the WP2 field to a new value. */ 08437 #define BW_AIPS_PACRK_WP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP2), v)) 08438 /*@}*/ 08439 08440 /*! 08441 * @name Register AIPS_PACRK, field SP2[22] (RW) 08442 * 08443 * Determines whether the peripheral requires supervisor privilege level for 08444 * access. When this bit is set, the master privilege level must indicate the 08445 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 08446 * set. If not, access terminates with an error response and no peripheral access 08447 * initiates. 08448 * 08449 * Values: 08450 * - 0 - This peripheral does not require supervisor privilege level for 08451 * accesses. 08452 * - 1 - This peripheral requires supervisor privilege level for accesses. 08453 */ 08454 /*@{*/ 08455 #define BP_AIPS_PACRK_SP2 (22U) /*!< Bit position for AIPS_PACRK_SP2. */ 08456 #define BM_AIPS_PACRK_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRK_SP2. */ 08457 #define BS_AIPS_PACRK_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP2. */ 08458 08459 /*! @brief Read current value of the AIPS_PACRK_SP2 field. */ 08460 #define BR_AIPS_PACRK_SP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP2))) 08461 08462 /*! @brief Format value for bitfield AIPS_PACRK_SP2. */ 08463 #define BF_AIPS_PACRK_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP2) & BM_AIPS_PACRK_SP2) 08464 08465 /*! @brief Set the SP2 field to a new value. */ 08466 #define BW_AIPS_PACRK_SP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP2), v)) 08467 /*@}*/ 08468 08469 /*! 08470 * @name Register AIPS_PACRK, field TP1[24] (RW) 08471 * 08472 * Determines whether the peripheral allows accesses from an untrusted master. 08473 * When this field is set and an access is attempted by an untrusted master, the 08474 * access terminates with an error response and no peripheral access initiates. 08475 * 08476 * Values: 08477 * - 0 - Accesses from an untrusted master are allowed. 08478 * - 1 - Accesses from an untrusted master are not allowed. 08479 */ 08480 /*@{*/ 08481 #define BP_AIPS_PACRK_TP1 (24U) /*!< Bit position for AIPS_PACRK_TP1. */ 08482 #define BM_AIPS_PACRK_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRK_TP1. */ 08483 #define BS_AIPS_PACRK_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP1. */ 08484 08485 /*! @brief Read current value of the AIPS_PACRK_TP1 field. */ 08486 #define BR_AIPS_PACRK_TP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP1))) 08487 08488 /*! @brief Format value for bitfield AIPS_PACRK_TP1. */ 08489 #define BF_AIPS_PACRK_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP1) & BM_AIPS_PACRK_TP1) 08490 08491 /*! @brief Set the TP1 field to a new value. */ 08492 #define BW_AIPS_PACRK_TP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP1), v)) 08493 /*@}*/ 08494 08495 /*! 08496 * @name Register AIPS_PACRK, field WP1[25] (RW) 08497 * 08498 * Determines whether the peripheral allows write accesses. When this field is 08499 * set and a write access is attempted, access terminates with an error response 08500 * and no peripheral access initiates. 08501 * 08502 * Values: 08503 * - 0 - This peripheral allows write accesses. 08504 * - 1 - This peripheral is write protected. 08505 */ 08506 /*@{*/ 08507 #define BP_AIPS_PACRK_WP1 (25U) /*!< Bit position for AIPS_PACRK_WP1. */ 08508 #define BM_AIPS_PACRK_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRK_WP1. */ 08509 #define BS_AIPS_PACRK_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP1. */ 08510 08511 /*! @brief Read current value of the AIPS_PACRK_WP1 field. */ 08512 #define BR_AIPS_PACRK_WP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP1))) 08513 08514 /*! @brief Format value for bitfield AIPS_PACRK_WP1. */ 08515 #define BF_AIPS_PACRK_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP1) & BM_AIPS_PACRK_WP1) 08516 08517 /*! @brief Set the WP1 field to a new value. */ 08518 #define BW_AIPS_PACRK_WP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP1), v)) 08519 /*@}*/ 08520 08521 /*! 08522 * @name Register AIPS_PACRK, field SP1[26] (RW) 08523 * 08524 * Determines whether the peripheral requires supervisor privilege level for 08525 * access. When this field is set, the master privilege level must indicate the 08526 * supervisor access attribute, and the MPRx[MPLn] control field for the master must 08527 * be set. If not, access terminates with an error response and no peripheral 08528 * access initiates. 08529 * 08530 * Values: 08531 * - 0 - This peripheral does not require supervisor privilege level for 08532 * accesses. 08533 * - 1 - This peripheral requires supervisor privilege level for accesses. 08534 */ 08535 /*@{*/ 08536 #define BP_AIPS_PACRK_SP1 (26U) /*!< Bit position for AIPS_PACRK_SP1. */ 08537 #define BM_AIPS_PACRK_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRK_SP1. */ 08538 #define BS_AIPS_PACRK_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP1. */ 08539 08540 /*! @brief Read current value of the AIPS_PACRK_SP1 field. */ 08541 #define BR_AIPS_PACRK_SP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP1))) 08542 08543 /*! @brief Format value for bitfield AIPS_PACRK_SP1. */ 08544 #define BF_AIPS_PACRK_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP1) & BM_AIPS_PACRK_SP1) 08545 08546 /*! @brief Set the SP1 field to a new value. */ 08547 #define BW_AIPS_PACRK_SP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP1), v)) 08548 /*@}*/ 08549 08550 /*! 08551 * @name Register AIPS_PACRK, field TP0[28] (RW) 08552 * 08553 * Determines whether the peripheral allows accesses from an untrusted master. 08554 * When this bit is set and an access is attempted by an untrusted master, the 08555 * access terminates with an error response and no peripheral access initiates. 08556 * 08557 * Values: 08558 * - 0 - Accesses from an untrusted master are allowed. 08559 * - 1 - Accesses from an untrusted master are not allowed. 08560 */ 08561 /*@{*/ 08562 #define BP_AIPS_PACRK_TP0 (28U) /*!< Bit position for AIPS_PACRK_TP0. */ 08563 #define BM_AIPS_PACRK_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRK_TP0. */ 08564 #define BS_AIPS_PACRK_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRK_TP0. */ 08565 08566 /*! @brief Read current value of the AIPS_PACRK_TP0 field. */ 08567 #define BR_AIPS_PACRK_TP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP0))) 08568 08569 /*! @brief Format value for bitfield AIPS_PACRK_TP0. */ 08570 #define BF_AIPS_PACRK_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_TP0) & BM_AIPS_PACRK_TP0) 08571 08572 /*! @brief Set the TP0 field to a new value. */ 08573 #define BW_AIPS_PACRK_TP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_TP0), v)) 08574 /*@}*/ 08575 08576 /*! 08577 * @name Register AIPS_PACRK, field WP0[29] (RW) 08578 * 08579 * Determines whether the peripheral allows write accesses. When this field is 08580 * set and a write access is attempted, access terminates with an error response 08581 * and no peripheral access initiates. 08582 * 08583 * Values: 08584 * - 0 - This peripheral allows write accesses. 08585 * - 1 - This peripheral is write protected. 08586 */ 08587 /*@{*/ 08588 #define BP_AIPS_PACRK_WP0 (29U) /*!< Bit position for AIPS_PACRK_WP0. */ 08589 #define BM_AIPS_PACRK_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRK_WP0. */ 08590 #define BS_AIPS_PACRK_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRK_WP0. */ 08591 08592 /*! @brief Read current value of the AIPS_PACRK_WP0 field. */ 08593 #define BR_AIPS_PACRK_WP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP0))) 08594 08595 /*! @brief Format value for bitfield AIPS_PACRK_WP0. */ 08596 #define BF_AIPS_PACRK_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_WP0) & BM_AIPS_PACRK_WP0) 08597 08598 /*! @brief Set the WP0 field to a new value. */ 08599 #define BW_AIPS_PACRK_WP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_WP0), v)) 08600 /*@}*/ 08601 08602 /*! 08603 * @name Register AIPS_PACRK, field SP0[30] (RW) 08604 * 08605 * Determines whether the peripheral requires supervisor privilege level for 08606 * accesses. When this field is set, the master privilege level must indicate the 08607 * supervisor access attribute, and the MPRx[MPLn] control field for the master 08608 * must be set. If not, access terminates with an error response and no peripheral 08609 * access initiates. 08610 * 08611 * Values: 08612 * - 0 - This peripheral does not require supervisor privilege level for 08613 * accesses. 08614 * - 1 - This peripheral requires supervisor privilege level for accesses. 08615 */ 08616 /*@{*/ 08617 #define BP_AIPS_PACRK_SP0 (30U) /*!< Bit position for AIPS_PACRK_SP0. */ 08618 #define BM_AIPS_PACRK_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRK_SP0. */ 08619 #define BS_AIPS_PACRK_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRK_SP0. */ 08620 08621 /*! @brief Read current value of the AIPS_PACRK_SP0 field. */ 08622 #define BR_AIPS_PACRK_SP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP0))) 08623 08624 /*! @brief Format value for bitfield AIPS_PACRK_SP0. */ 08625 #define BF_AIPS_PACRK_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRK_SP0) & BM_AIPS_PACRK_SP0) 08626 08627 /*! @brief Set the SP0 field to a new value. */ 08628 #define BW_AIPS_PACRK_SP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRK_ADDR(x), BP_AIPS_PACRK_SP0), v)) 08629 /*@}*/ 08630 08631 /******************************************************************************* 08632 * HW_AIPS_PACRL - Peripheral Access Control Register 08633 ******************************************************************************/ 08634 08635 /*! 08636 * @brief HW_AIPS_PACRL - Peripheral Access Control Register (RW) 08637 * 08638 * Reset value: 0x44444444U 08639 * 08640 * This section describes PACR registers E-P, which control peripheral slots 08641 * 32-127. See PACRPeripheral Access Control Register for the description of these 08642 * registers. 08643 */ 08644 typedef union _hw_aips_pacrl 08645 { 08646 uint32_t U; 08647 struct _hw_aips_pacrl_bitfields 08648 { 08649 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 08650 uint32_t WP7 : 1; /*!< [1] Write Protect */ 08651 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 08652 uint32_t RESERVED0 : 1; /*!< [3] */ 08653 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 08654 uint32_t WP6 : 1; /*!< [5] Write Protect */ 08655 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 08656 uint32_t RESERVED1 : 1; /*!< [7] */ 08657 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 08658 uint32_t WP5 : 1; /*!< [9] Write Protect */ 08659 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 08660 uint32_t RESERVED2 : 1; /*!< [11] */ 08661 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 08662 uint32_t WP4 : 1; /*!< [13] Write Protect */ 08663 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 08664 uint32_t RESERVED3 : 1; /*!< [15] */ 08665 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 08666 uint32_t WP3 : 1; /*!< [17] Write Protect */ 08667 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 08668 uint32_t RESERVED4 : 1; /*!< [19] */ 08669 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 08670 uint32_t WP2 : 1; /*!< [21] Write Protect */ 08671 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 08672 uint32_t RESERVED5 : 1; /*!< [23] */ 08673 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 08674 uint32_t WP1 : 1; /*!< [25] Write Protect */ 08675 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 08676 uint32_t RESERVED6 : 1; /*!< [27] */ 08677 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 08678 uint32_t WP0 : 1; /*!< [29] Write Protect */ 08679 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 08680 uint32_t RESERVED7 : 1; /*!< [31] */ 08681 } B; 08682 } hw_aips_pacrl_t; 08683 08684 /*! 08685 * @name Constants and macros for entire AIPS_PACRL register 08686 */ 08687 /*@{*/ 08688 #define HW_AIPS_PACRL_ADDR(x) ((x) + 0x5CU) 08689 08690 #define HW_AIPS_PACRL(x) (*(__IO hw_aips_pacrl_t *) HW_AIPS_PACRL_ADDR(x)) 08691 #define HW_AIPS_PACRL_RD(x) (ADDRESS_READ(hw_aips_pacrl_t, HW_AIPS_PACRL_ADDR(x))) 08692 #define HW_AIPS_PACRL_WR(x, v) (ADDRESS_WRITE(hw_aips_pacrl_t, HW_AIPS_PACRL_ADDR(x), v)) 08693 #define HW_AIPS_PACRL_SET(x, v) (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) | (v))) 08694 #define HW_AIPS_PACRL_CLR(x, v) (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) & ~(v))) 08695 #define HW_AIPS_PACRL_TOG(x, v) (HW_AIPS_PACRL_WR(x, HW_AIPS_PACRL_RD(x) ^ (v))) 08696 /*@}*/ 08697 08698 /* 08699 * Constants & macros for individual AIPS_PACRL bitfields 08700 */ 08701 08702 /*! 08703 * @name Register AIPS_PACRL, field TP7[0] (RW) 08704 * 08705 * Determines whether the peripheral allows accesses from an untrusted master. 08706 * When this field is set and an access is attempted by an untrusted master, the 08707 * access terminates with an error response and no peripheral access initiates. 08708 * 08709 * Values: 08710 * - 0 - Accesses from an untrusted master are allowed. 08711 * - 1 - Accesses from an untrusted master are not allowed. 08712 */ 08713 /*@{*/ 08714 #define BP_AIPS_PACRL_TP7 (0U) /*!< Bit position for AIPS_PACRL_TP7. */ 08715 #define BM_AIPS_PACRL_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRL_TP7. */ 08716 #define BS_AIPS_PACRL_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP7. */ 08717 08718 /*! @brief Read current value of the AIPS_PACRL_TP7 field. */ 08719 #define BR_AIPS_PACRL_TP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP7))) 08720 08721 /*! @brief Format value for bitfield AIPS_PACRL_TP7. */ 08722 #define BF_AIPS_PACRL_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP7) & BM_AIPS_PACRL_TP7) 08723 08724 /*! @brief Set the TP7 field to a new value. */ 08725 #define BW_AIPS_PACRL_TP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP7), v)) 08726 /*@}*/ 08727 08728 /*! 08729 * @name Register AIPS_PACRL, field WP7[1] (RW) 08730 * 08731 * Determines whether the peripheral allows write accesses. When this field is 08732 * set and a write access is attempted, access terminates with an error response 08733 * and no peripheral access initiates. 08734 * 08735 * Values: 08736 * - 0 - This peripheral allows write accesses. 08737 * - 1 - This peripheral is write protected. 08738 */ 08739 /*@{*/ 08740 #define BP_AIPS_PACRL_WP7 (1U) /*!< Bit position for AIPS_PACRL_WP7. */ 08741 #define BM_AIPS_PACRL_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRL_WP7. */ 08742 #define BS_AIPS_PACRL_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP7. */ 08743 08744 /*! @brief Read current value of the AIPS_PACRL_WP7 field. */ 08745 #define BR_AIPS_PACRL_WP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP7))) 08746 08747 /*! @brief Format value for bitfield AIPS_PACRL_WP7. */ 08748 #define BF_AIPS_PACRL_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP7) & BM_AIPS_PACRL_WP7) 08749 08750 /*! @brief Set the WP7 field to a new value. */ 08751 #define BW_AIPS_PACRL_WP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP7), v)) 08752 /*@}*/ 08753 08754 /*! 08755 * @name Register AIPS_PACRL, field SP7[2] (RW) 08756 * 08757 * Determines whether the peripheral requires supervisor privilege level for 08758 * accesses. When this field is set, the master privilege level must indicate the 08759 * supervisor access attribute, and the MPRx[MPLn] control field for the master 08760 * must be set. If not, access terminates with an error response and no peripheral 08761 * access initiates. 08762 * 08763 * Values: 08764 * - 0 - This peripheral does not require supervisor privilege level for 08765 * accesses. 08766 * - 1 - This peripheral requires supervisor privilege level for accesses. 08767 */ 08768 /*@{*/ 08769 #define BP_AIPS_PACRL_SP7 (2U) /*!< Bit position for AIPS_PACRL_SP7. */ 08770 #define BM_AIPS_PACRL_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRL_SP7. */ 08771 #define BS_AIPS_PACRL_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP7. */ 08772 08773 /*! @brief Read current value of the AIPS_PACRL_SP7 field. */ 08774 #define BR_AIPS_PACRL_SP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP7))) 08775 08776 /*! @brief Format value for bitfield AIPS_PACRL_SP7. */ 08777 #define BF_AIPS_PACRL_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP7) & BM_AIPS_PACRL_SP7) 08778 08779 /*! @brief Set the SP7 field to a new value. */ 08780 #define BW_AIPS_PACRL_SP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP7), v)) 08781 /*@}*/ 08782 08783 /*! 08784 * @name Register AIPS_PACRL, field TP6[4] (RW) 08785 * 08786 * Determines whether the peripheral allows accesses from an untrusted master. 08787 * When this field is set and an access is attempted by an untrusted master, the 08788 * access terminates with an error response and no peripheral access initiates. 08789 * 08790 * Values: 08791 * - 0 - Accesses from an untrusted master are allowed. 08792 * - 1 - Accesses from an untrusted master are not allowed. 08793 */ 08794 /*@{*/ 08795 #define BP_AIPS_PACRL_TP6 (4U) /*!< Bit position for AIPS_PACRL_TP6. */ 08796 #define BM_AIPS_PACRL_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRL_TP6. */ 08797 #define BS_AIPS_PACRL_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP6. */ 08798 08799 /*! @brief Read current value of the AIPS_PACRL_TP6 field. */ 08800 #define BR_AIPS_PACRL_TP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP6))) 08801 08802 /*! @brief Format value for bitfield AIPS_PACRL_TP6. */ 08803 #define BF_AIPS_PACRL_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP6) & BM_AIPS_PACRL_TP6) 08804 08805 /*! @brief Set the TP6 field to a new value. */ 08806 #define BW_AIPS_PACRL_TP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP6), v)) 08807 /*@}*/ 08808 08809 /*! 08810 * @name Register AIPS_PACRL, field WP6[5] (RW) 08811 * 08812 * Determines whether the peripheral allows write accesses. When this field is 08813 * set and a write access is attempted, access terminates with an error response 08814 * and no peripheral access initiates. 08815 * 08816 * Values: 08817 * - 0 - This peripheral allows write accesses. 08818 * - 1 - This peripheral is write protected. 08819 */ 08820 /*@{*/ 08821 #define BP_AIPS_PACRL_WP6 (5U) /*!< Bit position for AIPS_PACRL_WP6. */ 08822 #define BM_AIPS_PACRL_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRL_WP6. */ 08823 #define BS_AIPS_PACRL_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP6. */ 08824 08825 /*! @brief Read current value of the AIPS_PACRL_WP6 field. */ 08826 #define BR_AIPS_PACRL_WP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP6))) 08827 08828 /*! @brief Format value for bitfield AIPS_PACRL_WP6. */ 08829 #define BF_AIPS_PACRL_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP6) & BM_AIPS_PACRL_WP6) 08830 08831 /*! @brief Set the WP6 field to a new value. */ 08832 #define BW_AIPS_PACRL_WP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP6), v)) 08833 /*@}*/ 08834 08835 /*! 08836 * @name Register AIPS_PACRL, field SP6[6] (RW) 08837 * 08838 * Determines whether the peripheral requires supervisor privilege level for 08839 * accesses. When this field is set, the master privilege level must indicate the 08840 * supervisor access attribute, and the MPRx[MPLn] control field for the master 08841 * must be set. If not, access terminates with an error response and no peripheral 08842 * access initiates. 08843 * 08844 * Values: 08845 * - 0 - This peripheral does not require supervisor privilege level for 08846 * accesses. 08847 * - 1 - This peripheral requires supervisor privilege level for accesses. 08848 */ 08849 /*@{*/ 08850 #define BP_AIPS_PACRL_SP6 (6U) /*!< Bit position for AIPS_PACRL_SP6. */ 08851 #define BM_AIPS_PACRL_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRL_SP6. */ 08852 #define BS_AIPS_PACRL_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP6. */ 08853 08854 /*! @brief Read current value of the AIPS_PACRL_SP6 field. */ 08855 #define BR_AIPS_PACRL_SP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP6))) 08856 08857 /*! @brief Format value for bitfield AIPS_PACRL_SP6. */ 08858 #define BF_AIPS_PACRL_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP6) & BM_AIPS_PACRL_SP6) 08859 08860 /*! @brief Set the SP6 field to a new value. */ 08861 #define BW_AIPS_PACRL_SP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP6), v)) 08862 /*@}*/ 08863 08864 /*! 08865 * @name Register AIPS_PACRL, field TP5[8] (RW) 08866 * 08867 * Determines whether the peripheral allows accesses from an untrusted master. 08868 * When this field is set and an access is attempted by an untrusted master, the 08869 * access terminates with an error response and no peripheral access initiates. 08870 * 08871 * Values: 08872 * - 0 - Accesses from an untrusted master are allowed. 08873 * - 1 - Accesses from an untrusted master are not allowed. 08874 */ 08875 /*@{*/ 08876 #define BP_AIPS_PACRL_TP5 (8U) /*!< Bit position for AIPS_PACRL_TP5. */ 08877 #define BM_AIPS_PACRL_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRL_TP5. */ 08878 #define BS_AIPS_PACRL_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP5. */ 08879 08880 /*! @brief Read current value of the AIPS_PACRL_TP5 field. */ 08881 #define BR_AIPS_PACRL_TP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP5))) 08882 08883 /*! @brief Format value for bitfield AIPS_PACRL_TP5. */ 08884 #define BF_AIPS_PACRL_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP5) & BM_AIPS_PACRL_TP5) 08885 08886 /*! @brief Set the TP5 field to a new value. */ 08887 #define BW_AIPS_PACRL_TP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP5), v)) 08888 /*@}*/ 08889 08890 /*! 08891 * @name Register AIPS_PACRL, field WP5[9] (RW) 08892 * 08893 * Determines whether the peripheral allows write accesses. When this field is 08894 * set and a write access is attempted, access terminates with an error response 08895 * and no peripheral access initiates. 08896 * 08897 * Values: 08898 * - 0 - This peripheral allows write accesses. 08899 * - 1 - This peripheral is write protected. 08900 */ 08901 /*@{*/ 08902 #define BP_AIPS_PACRL_WP5 (9U) /*!< Bit position for AIPS_PACRL_WP5. */ 08903 #define BM_AIPS_PACRL_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRL_WP5. */ 08904 #define BS_AIPS_PACRL_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP5. */ 08905 08906 /*! @brief Read current value of the AIPS_PACRL_WP5 field. */ 08907 #define BR_AIPS_PACRL_WP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP5))) 08908 08909 /*! @brief Format value for bitfield AIPS_PACRL_WP5. */ 08910 #define BF_AIPS_PACRL_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP5) & BM_AIPS_PACRL_WP5) 08911 08912 /*! @brief Set the WP5 field to a new value. */ 08913 #define BW_AIPS_PACRL_WP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP5), v)) 08914 /*@}*/ 08915 08916 /*! 08917 * @name Register AIPS_PACRL, field SP5[10] (RW) 08918 * 08919 * Determines whether the peripheral requires supervisor privilege level for 08920 * accesses. When this field is set, the master privilege level must indicate the 08921 * supervisor access attribute, and the MPRx[MPLn] control field for the master 08922 * must be set. If not, access terminates with an error response and no peripheral 08923 * access initiates. 08924 * 08925 * Values: 08926 * - 0 - This peripheral does not require supervisor privilege level for 08927 * accesses. 08928 * - 1 - This peripheral requires supervisor privilege level for accesses. 08929 */ 08930 /*@{*/ 08931 #define BP_AIPS_PACRL_SP5 (10U) /*!< Bit position for AIPS_PACRL_SP5. */ 08932 #define BM_AIPS_PACRL_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRL_SP5. */ 08933 #define BS_AIPS_PACRL_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP5. */ 08934 08935 /*! @brief Read current value of the AIPS_PACRL_SP5 field. */ 08936 #define BR_AIPS_PACRL_SP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP5))) 08937 08938 /*! @brief Format value for bitfield AIPS_PACRL_SP5. */ 08939 #define BF_AIPS_PACRL_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP5) & BM_AIPS_PACRL_SP5) 08940 08941 /*! @brief Set the SP5 field to a new value. */ 08942 #define BW_AIPS_PACRL_SP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP5), v)) 08943 /*@}*/ 08944 08945 /*! 08946 * @name Register AIPS_PACRL, field TP4[12] (RW) 08947 * 08948 * Determines whether the peripheral allows accesses from an untrusted master. 08949 * When this bit is set and an access is attempted by an untrusted master, the 08950 * access terminates with an error response and no peripheral access initiates. 08951 * 08952 * Values: 08953 * - 0 - Accesses from an untrusted master are allowed. 08954 * - 1 - Accesses from an untrusted master are not allowed. 08955 */ 08956 /*@{*/ 08957 #define BP_AIPS_PACRL_TP4 (12U) /*!< Bit position for AIPS_PACRL_TP4. */ 08958 #define BM_AIPS_PACRL_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRL_TP4. */ 08959 #define BS_AIPS_PACRL_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP4. */ 08960 08961 /*! @brief Read current value of the AIPS_PACRL_TP4 field. */ 08962 #define BR_AIPS_PACRL_TP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP4))) 08963 08964 /*! @brief Format value for bitfield AIPS_PACRL_TP4. */ 08965 #define BF_AIPS_PACRL_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP4) & BM_AIPS_PACRL_TP4) 08966 08967 /*! @brief Set the TP4 field to a new value. */ 08968 #define BW_AIPS_PACRL_TP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP4), v)) 08969 /*@}*/ 08970 08971 /*! 08972 * @name Register AIPS_PACRL, field WP4[13] (RW) 08973 * 08974 * Determines whether the peripheral allows write accesses. When this field is 08975 * set and a write access is attempted, access terminates with an error response 08976 * and no peripheral access initiates. 08977 * 08978 * Values: 08979 * - 0 - This peripheral allows write accesses. 08980 * - 1 - This peripheral is write protected. 08981 */ 08982 /*@{*/ 08983 #define BP_AIPS_PACRL_WP4 (13U) /*!< Bit position for AIPS_PACRL_WP4. */ 08984 #define BM_AIPS_PACRL_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRL_WP4. */ 08985 #define BS_AIPS_PACRL_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP4. */ 08986 08987 /*! @brief Read current value of the AIPS_PACRL_WP4 field. */ 08988 #define BR_AIPS_PACRL_WP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP4))) 08989 08990 /*! @brief Format value for bitfield AIPS_PACRL_WP4. */ 08991 #define BF_AIPS_PACRL_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP4) & BM_AIPS_PACRL_WP4) 08992 08993 /*! @brief Set the WP4 field to a new value. */ 08994 #define BW_AIPS_PACRL_WP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP4), v)) 08995 /*@}*/ 08996 08997 /*! 08998 * @name Register AIPS_PACRL, field SP4[14] (RW) 08999 * 09000 * Determines whether the peripheral requires supervisor privilege level for 09001 * access. When this bit is set, the master privilege level must indicate the 09002 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 09003 * set. If not, access terminates with an error response and no peripheral access 09004 * initiates. 09005 * 09006 * Values: 09007 * - 0 - This peripheral does not require supervisor privilege level for 09008 * accesses. 09009 * - 1 - This peripheral requires supervisor privilege level for accesses. 09010 */ 09011 /*@{*/ 09012 #define BP_AIPS_PACRL_SP4 (14U) /*!< Bit position for AIPS_PACRL_SP4. */ 09013 #define BM_AIPS_PACRL_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRL_SP4. */ 09014 #define BS_AIPS_PACRL_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP4. */ 09015 09016 /*! @brief Read current value of the AIPS_PACRL_SP4 field. */ 09017 #define BR_AIPS_PACRL_SP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP4))) 09018 09019 /*! @brief Format value for bitfield AIPS_PACRL_SP4. */ 09020 #define BF_AIPS_PACRL_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP4) & BM_AIPS_PACRL_SP4) 09021 09022 /*! @brief Set the SP4 field to a new value. */ 09023 #define BW_AIPS_PACRL_SP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP4), v)) 09024 /*@}*/ 09025 09026 /*! 09027 * @name Register AIPS_PACRL, field TP3[16] (RW) 09028 * 09029 * Determines whether the peripheral allows accesses from an untrusted master. 09030 * When this field is set and an access is attempted by an untrusted master, the 09031 * access terminates with an error response and no peripheral access initiates. 09032 * 09033 * Values: 09034 * - 0 - Accesses from an untrusted master are allowed. 09035 * - 1 - Accesses from an untrusted master are not allowed. 09036 */ 09037 /*@{*/ 09038 #define BP_AIPS_PACRL_TP3 (16U) /*!< Bit position for AIPS_PACRL_TP3. */ 09039 #define BM_AIPS_PACRL_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRL_TP3. */ 09040 #define BS_AIPS_PACRL_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP3. */ 09041 09042 /*! @brief Read current value of the AIPS_PACRL_TP3 field. */ 09043 #define BR_AIPS_PACRL_TP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP3))) 09044 09045 /*! @brief Format value for bitfield AIPS_PACRL_TP3. */ 09046 #define BF_AIPS_PACRL_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP3) & BM_AIPS_PACRL_TP3) 09047 09048 /*! @brief Set the TP3 field to a new value. */ 09049 #define BW_AIPS_PACRL_TP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP3), v)) 09050 /*@}*/ 09051 09052 /*! 09053 * @name Register AIPS_PACRL, field WP3[17] (RW) 09054 * 09055 * Determines whether the peripheral allows write accesss. When this bit is set 09056 * and a write access is attempted, access terminates with an error response and 09057 * no peripheral access initiates. 09058 * 09059 * Values: 09060 * - 0 - This peripheral allows write accesses. 09061 * - 1 - This peripheral is write protected. 09062 */ 09063 /*@{*/ 09064 #define BP_AIPS_PACRL_WP3 (17U) /*!< Bit position for AIPS_PACRL_WP3. */ 09065 #define BM_AIPS_PACRL_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRL_WP3. */ 09066 #define BS_AIPS_PACRL_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP3. */ 09067 09068 /*! @brief Read current value of the AIPS_PACRL_WP3 field. */ 09069 #define BR_AIPS_PACRL_WP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP3))) 09070 09071 /*! @brief Format value for bitfield AIPS_PACRL_WP3. */ 09072 #define BF_AIPS_PACRL_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP3) & BM_AIPS_PACRL_WP3) 09073 09074 /*! @brief Set the WP3 field to a new value. */ 09075 #define BW_AIPS_PACRL_WP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP3), v)) 09076 /*@}*/ 09077 09078 /*! 09079 * @name Register AIPS_PACRL, field SP3[18] (RW) 09080 * 09081 * Determines whether the peripheral requires supervisor privilege level for 09082 * accesses. When this field is set, the master privilege level must indicate the 09083 * supervisor access attribute, and the MPRx[MPLn] control field for the master 09084 * must be set. If not, access terminates with an error response and no peripheral 09085 * access initiates. 09086 * 09087 * Values: 09088 * - 0 - This peripheral does not require supervisor privilege level for 09089 * accesses. 09090 * - 1 - This peripheral requires supervisor privilege level for accesses. 09091 */ 09092 /*@{*/ 09093 #define BP_AIPS_PACRL_SP3 (18U) /*!< Bit position for AIPS_PACRL_SP3. */ 09094 #define BM_AIPS_PACRL_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRL_SP3. */ 09095 #define BS_AIPS_PACRL_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP3. */ 09096 09097 /*! @brief Read current value of the AIPS_PACRL_SP3 field. */ 09098 #define BR_AIPS_PACRL_SP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP3))) 09099 09100 /*! @brief Format value for bitfield AIPS_PACRL_SP3. */ 09101 #define BF_AIPS_PACRL_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP3) & BM_AIPS_PACRL_SP3) 09102 09103 /*! @brief Set the SP3 field to a new value. */ 09104 #define BW_AIPS_PACRL_SP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP3), v)) 09105 /*@}*/ 09106 09107 /*! 09108 * @name Register AIPS_PACRL, field TP2[20] (RW) 09109 * 09110 * Determines whether the peripheral allows accesses from an untrusted master. 09111 * When this bit is set and an access is attempted by an untrusted master, the 09112 * access terminates with an error response and no peripheral access initiates. 09113 * 09114 * Values: 09115 * - 0 - Accesses from an untrusted master are allowed. 09116 * - 1 - Accesses from an untrusted master are not allowed. 09117 */ 09118 /*@{*/ 09119 #define BP_AIPS_PACRL_TP2 (20U) /*!< Bit position for AIPS_PACRL_TP2. */ 09120 #define BM_AIPS_PACRL_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRL_TP2. */ 09121 #define BS_AIPS_PACRL_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP2. */ 09122 09123 /*! @brief Read current value of the AIPS_PACRL_TP2 field. */ 09124 #define BR_AIPS_PACRL_TP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP2))) 09125 09126 /*! @brief Format value for bitfield AIPS_PACRL_TP2. */ 09127 #define BF_AIPS_PACRL_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP2) & BM_AIPS_PACRL_TP2) 09128 09129 /*! @brief Set the TP2 field to a new value. */ 09130 #define BW_AIPS_PACRL_TP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP2), v)) 09131 /*@}*/ 09132 09133 /*! 09134 * @name Register AIPS_PACRL, field WP2[21] (RW) 09135 * 09136 * Determines whether the peripheral allows write accesses. When this field is 09137 * set and a write access is attempted, access terminates with an error response 09138 * and no peripheral access initiates. 09139 * 09140 * Values: 09141 * - 0 - This peripheral allows write accesses. 09142 * - 1 - This peripheral is write protected. 09143 */ 09144 /*@{*/ 09145 #define BP_AIPS_PACRL_WP2 (21U) /*!< Bit position for AIPS_PACRL_WP2. */ 09146 #define BM_AIPS_PACRL_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRL_WP2. */ 09147 #define BS_AIPS_PACRL_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP2. */ 09148 09149 /*! @brief Read current value of the AIPS_PACRL_WP2 field. */ 09150 #define BR_AIPS_PACRL_WP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP2))) 09151 09152 /*! @brief Format value for bitfield AIPS_PACRL_WP2. */ 09153 #define BF_AIPS_PACRL_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP2) & BM_AIPS_PACRL_WP2) 09154 09155 /*! @brief Set the WP2 field to a new value. */ 09156 #define BW_AIPS_PACRL_WP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP2), v)) 09157 /*@}*/ 09158 09159 /*! 09160 * @name Register AIPS_PACRL, field SP2[22] (RW) 09161 * 09162 * Determines whether the peripheral requires supervisor privilege level for 09163 * access. When this bit is set, the master privilege level must indicate the 09164 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 09165 * set. If not, access terminates with an error response and no peripheral access 09166 * initiates. 09167 * 09168 * Values: 09169 * - 0 - This peripheral does not require supervisor privilege level for 09170 * accesses. 09171 * - 1 - This peripheral requires supervisor privilege level for accesses. 09172 */ 09173 /*@{*/ 09174 #define BP_AIPS_PACRL_SP2 (22U) /*!< Bit position for AIPS_PACRL_SP2. */ 09175 #define BM_AIPS_PACRL_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRL_SP2. */ 09176 #define BS_AIPS_PACRL_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP2. */ 09177 09178 /*! @brief Read current value of the AIPS_PACRL_SP2 field. */ 09179 #define BR_AIPS_PACRL_SP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP2))) 09180 09181 /*! @brief Format value for bitfield AIPS_PACRL_SP2. */ 09182 #define BF_AIPS_PACRL_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP2) & BM_AIPS_PACRL_SP2) 09183 09184 /*! @brief Set the SP2 field to a new value. */ 09185 #define BW_AIPS_PACRL_SP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP2), v)) 09186 /*@}*/ 09187 09188 /*! 09189 * @name Register AIPS_PACRL, field TP1[24] (RW) 09190 * 09191 * Determines whether the peripheral allows accesses from an untrusted master. 09192 * When this field is set and an access is attempted by an untrusted master, the 09193 * access terminates with an error response and no peripheral access initiates. 09194 * 09195 * Values: 09196 * - 0 - Accesses from an untrusted master are allowed. 09197 * - 1 - Accesses from an untrusted master are not allowed. 09198 */ 09199 /*@{*/ 09200 #define BP_AIPS_PACRL_TP1 (24U) /*!< Bit position for AIPS_PACRL_TP1. */ 09201 #define BM_AIPS_PACRL_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRL_TP1. */ 09202 #define BS_AIPS_PACRL_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP1. */ 09203 09204 /*! @brief Read current value of the AIPS_PACRL_TP1 field. */ 09205 #define BR_AIPS_PACRL_TP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP1))) 09206 09207 /*! @brief Format value for bitfield AIPS_PACRL_TP1. */ 09208 #define BF_AIPS_PACRL_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP1) & BM_AIPS_PACRL_TP1) 09209 09210 /*! @brief Set the TP1 field to a new value. */ 09211 #define BW_AIPS_PACRL_TP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP1), v)) 09212 /*@}*/ 09213 09214 /*! 09215 * @name Register AIPS_PACRL, field WP1[25] (RW) 09216 * 09217 * Determines whether the peripheral allows write accesses. When this field is 09218 * set and a write access is attempted, access terminates with an error response 09219 * and no peripheral access initiates. 09220 * 09221 * Values: 09222 * - 0 - This peripheral allows write accesses. 09223 * - 1 - This peripheral is write protected. 09224 */ 09225 /*@{*/ 09226 #define BP_AIPS_PACRL_WP1 (25U) /*!< Bit position for AIPS_PACRL_WP1. */ 09227 #define BM_AIPS_PACRL_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRL_WP1. */ 09228 #define BS_AIPS_PACRL_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP1. */ 09229 09230 /*! @brief Read current value of the AIPS_PACRL_WP1 field. */ 09231 #define BR_AIPS_PACRL_WP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP1))) 09232 09233 /*! @brief Format value for bitfield AIPS_PACRL_WP1. */ 09234 #define BF_AIPS_PACRL_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP1) & BM_AIPS_PACRL_WP1) 09235 09236 /*! @brief Set the WP1 field to a new value. */ 09237 #define BW_AIPS_PACRL_WP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP1), v)) 09238 /*@}*/ 09239 09240 /*! 09241 * @name Register AIPS_PACRL, field SP1[26] (RW) 09242 * 09243 * Determines whether the peripheral requires supervisor privilege level for 09244 * access. When this field is set, the master privilege level must indicate the 09245 * supervisor access attribute, and the MPRx[MPLn] control field for the master must 09246 * be set. If not, access terminates with an error response and no peripheral 09247 * access initiates. 09248 * 09249 * Values: 09250 * - 0 - This peripheral does not require supervisor privilege level for 09251 * accesses. 09252 * - 1 - This peripheral requires supervisor privilege level for accesses. 09253 */ 09254 /*@{*/ 09255 #define BP_AIPS_PACRL_SP1 (26U) /*!< Bit position for AIPS_PACRL_SP1. */ 09256 #define BM_AIPS_PACRL_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRL_SP1. */ 09257 #define BS_AIPS_PACRL_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP1. */ 09258 09259 /*! @brief Read current value of the AIPS_PACRL_SP1 field. */ 09260 #define BR_AIPS_PACRL_SP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP1))) 09261 09262 /*! @brief Format value for bitfield AIPS_PACRL_SP1. */ 09263 #define BF_AIPS_PACRL_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP1) & BM_AIPS_PACRL_SP1) 09264 09265 /*! @brief Set the SP1 field to a new value. */ 09266 #define BW_AIPS_PACRL_SP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP1), v)) 09267 /*@}*/ 09268 09269 /*! 09270 * @name Register AIPS_PACRL, field TP0[28] (RW) 09271 * 09272 * Determines whether the peripheral allows accesses from an untrusted master. 09273 * When this bit is set and an access is attempted by an untrusted master, the 09274 * access terminates with an error response and no peripheral access initiates. 09275 * 09276 * Values: 09277 * - 0 - Accesses from an untrusted master are allowed. 09278 * - 1 - Accesses from an untrusted master are not allowed. 09279 */ 09280 /*@{*/ 09281 #define BP_AIPS_PACRL_TP0 (28U) /*!< Bit position for AIPS_PACRL_TP0. */ 09282 #define BM_AIPS_PACRL_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRL_TP0. */ 09283 #define BS_AIPS_PACRL_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRL_TP0. */ 09284 09285 /*! @brief Read current value of the AIPS_PACRL_TP0 field. */ 09286 #define BR_AIPS_PACRL_TP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP0))) 09287 09288 /*! @brief Format value for bitfield AIPS_PACRL_TP0. */ 09289 #define BF_AIPS_PACRL_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_TP0) & BM_AIPS_PACRL_TP0) 09290 09291 /*! @brief Set the TP0 field to a new value. */ 09292 #define BW_AIPS_PACRL_TP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_TP0), v)) 09293 /*@}*/ 09294 09295 /*! 09296 * @name Register AIPS_PACRL, field WP0[29] (RW) 09297 * 09298 * Determines whether the peripheral allows write accesses. When this field is 09299 * set and a write access is attempted, access terminates with an error response 09300 * and no peripheral access initiates. 09301 * 09302 * Values: 09303 * - 0 - This peripheral allows write accesses. 09304 * - 1 - This peripheral is write protected. 09305 */ 09306 /*@{*/ 09307 #define BP_AIPS_PACRL_WP0 (29U) /*!< Bit position for AIPS_PACRL_WP0. */ 09308 #define BM_AIPS_PACRL_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRL_WP0. */ 09309 #define BS_AIPS_PACRL_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRL_WP0. */ 09310 09311 /*! @brief Read current value of the AIPS_PACRL_WP0 field. */ 09312 #define BR_AIPS_PACRL_WP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP0))) 09313 09314 /*! @brief Format value for bitfield AIPS_PACRL_WP0. */ 09315 #define BF_AIPS_PACRL_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_WP0) & BM_AIPS_PACRL_WP0) 09316 09317 /*! @brief Set the WP0 field to a new value. */ 09318 #define BW_AIPS_PACRL_WP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_WP0), v)) 09319 /*@}*/ 09320 09321 /*! 09322 * @name Register AIPS_PACRL, field SP0[30] (RW) 09323 * 09324 * Determines whether the peripheral requires supervisor privilege level for 09325 * accesses. When this field is set, the master privilege level must indicate the 09326 * supervisor access attribute, and the MPRx[MPLn] control field for the master 09327 * must be set. If not, access terminates with an error response and no peripheral 09328 * access initiates. 09329 * 09330 * Values: 09331 * - 0 - This peripheral does not require supervisor privilege level for 09332 * accesses. 09333 * - 1 - This peripheral requires supervisor privilege level for accesses. 09334 */ 09335 /*@{*/ 09336 #define BP_AIPS_PACRL_SP0 (30U) /*!< Bit position for AIPS_PACRL_SP0. */ 09337 #define BM_AIPS_PACRL_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRL_SP0. */ 09338 #define BS_AIPS_PACRL_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRL_SP0. */ 09339 09340 /*! @brief Read current value of the AIPS_PACRL_SP0 field. */ 09341 #define BR_AIPS_PACRL_SP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP0))) 09342 09343 /*! @brief Format value for bitfield AIPS_PACRL_SP0. */ 09344 #define BF_AIPS_PACRL_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRL_SP0) & BM_AIPS_PACRL_SP0) 09345 09346 /*! @brief Set the SP0 field to a new value. */ 09347 #define BW_AIPS_PACRL_SP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRL_ADDR(x), BP_AIPS_PACRL_SP0), v)) 09348 /*@}*/ 09349 09350 /******************************************************************************* 09351 * HW_AIPS_PACRM - Peripheral Access Control Register 09352 ******************************************************************************/ 09353 09354 /*! 09355 * @brief HW_AIPS_PACRM - Peripheral Access Control Register (RW) 09356 * 09357 * Reset value: 0x44444444U 09358 * 09359 * This section describes PACR registers E-P, which control peripheral slots 09360 * 32-127. See PACRPeripheral Access Control Register for the description of these 09361 * registers. 09362 */ 09363 typedef union _hw_aips_pacrm 09364 { 09365 uint32_t U; 09366 struct _hw_aips_pacrm_bitfields 09367 { 09368 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 09369 uint32_t WP7 : 1; /*!< [1] Write Protect */ 09370 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 09371 uint32_t RESERVED0 : 1; /*!< [3] */ 09372 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 09373 uint32_t WP6 : 1; /*!< [5] Write Protect */ 09374 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 09375 uint32_t RESERVED1 : 1; /*!< [7] */ 09376 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 09377 uint32_t WP5 : 1; /*!< [9] Write Protect */ 09378 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 09379 uint32_t RESERVED2 : 1; /*!< [11] */ 09380 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 09381 uint32_t WP4 : 1; /*!< [13] Write Protect */ 09382 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 09383 uint32_t RESERVED3 : 1; /*!< [15] */ 09384 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 09385 uint32_t WP3 : 1; /*!< [17] Write Protect */ 09386 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 09387 uint32_t RESERVED4 : 1; /*!< [19] */ 09388 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 09389 uint32_t WP2 : 1; /*!< [21] Write Protect */ 09390 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 09391 uint32_t RESERVED5 : 1; /*!< [23] */ 09392 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 09393 uint32_t WP1 : 1; /*!< [25] Write Protect */ 09394 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 09395 uint32_t RESERVED6 : 1; /*!< [27] */ 09396 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 09397 uint32_t WP0 : 1; /*!< [29] Write Protect */ 09398 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 09399 uint32_t RESERVED7 : 1; /*!< [31] */ 09400 } B; 09401 } hw_aips_pacrm_t; 09402 09403 /*! 09404 * @name Constants and macros for entire AIPS_PACRM register 09405 */ 09406 /*@{*/ 09407 #define HW_AIPS_PACRM_ADDR(x) ((x) + 0x60U) 09408 09409 #define HW_AIPS_PACRM(x) (*(__IO hw_aips_pacrm_t *) HW_AIPS_PACRM_ADDR(x)) 09410 #define HW_AIPS_PACRM_RD(x) (ADDRESS_READ(hw_aips_pacrm_t, HW_AIPS_PACRM_ADDR(x))) 09411 #define HW_AIPS_PACRM_WR(x, v) (ADDRESS_WRITE(hw_aips_pacrm_t, HW_AIPS_PACRM_ADDR(x), v)) 09412 #define HW_AIPS_PACRM_SET(x, v) (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) | (v))) 09413 #define HW_AIPS_PACRM_CLR(x, v) (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) & ~(v))) 09414 #define HW_AIPS_PACRM_TOG(x, v) (HW_AIPS_PACRM_WR(x, HW_AIPS_PACRM_RD(x) ^ (v))) 09415 /*@}*/ 09416 09417 /* 09418 * Constants & macros for individual AIPS_PACRM bitfields 09419 */ 09420 09421 /*! 09422 * @name Register AIPS_PACRM, field TP7[0] (RW) 09423 * 09424 * Determines whether the peripheral allows accesses from an untrusted master. 09425 * When this field is set and an access is attempted by an untrusted master, the 09426 * access terminates with an error response and no peripheral access initiates. 09427 * 09428 * Values: 09429 * - 0 - Accesses from an untrusted master are allowed. 09430 * - 1 - Accesses from an untrusted master are not allowed. 09431 */ 09432 /*@{*/ 09433 #define BP_AIPS_PACRM_TP7 (0U) /*!< Bit position for AIPS_PACRM_TP7. */ 09434 #define BM_AIPS_PACRM_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRM_TP7. */ 09435 #define BS_AIPS_PACRM_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP7. */ 09436 09437 /*! @brief Read current value of the AIPS_PACRM_TP7 field. */ 09438 #define BR_AIPS_PACRM_TP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP7))) 09439 09440 /*! @brief Format value for bitfield AIPS_PACRM_TP7. */ 09441 #define BF_AIPS_PACRM_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP7) & BM_AIPS_PACRM_TP7) 09442 09443 /*! @brief Set the TP7 field to a new value. */ 09444 #define BW_AIPS_PACRM_TP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP7), v)) 09445 /*@}*/ 09446 09447 /*! 09448 * @name Register AIPS_PACRM, field WP7[1] (RW) 09449 * 09450 * Determines whether the peripheral allows write accesses. When this field is 09451 * set and a write access is attempted, access terminates with an error response 09452 * and no peripheral access initiates. 09453 * 09454 * Values: 09455 * - 0 - This peripheral allows write accesses. 09456 * - 1 - This peripheral is write protected. 09457 */ 09458 /*@{*/ 09459 #define BP_AIPS_PACRM_WP7 (1U) /*!< Bit position for AIPS_PACRM_WP7. */ 09460 #define BM_AIPS_PACRM_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRM_WP7. */ 09461 #define BS_AIPS_PACRM_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP7. */ 09462 09463 /*! @brief Read current value of the AIPS_PACRM_WP7 field. */ 09464 #define BR_AIPS_PACRM_WP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP7))) 09465 09466 /*! @brief Format value for bitfield AIPS_PACRM_WP7. */ 09467 #define BF_AIPS_PACRM_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP7) & BM_AIPS_PACRM_WP7) 09468 09469 /*! @brief Set the WP7 field to a new value. */ 09470 #define BW_AIPS_PACRM_WP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP7), v)) 09471 /*@}*/ 09472 09473 /*! 09474 * @name Register AIPS_PACRM, field SP7[2] (RW) 09475 * 09476 * Determines whether the peripheral requires supervisor privilege level for 09477 * accesses. When this field is set, the master privilege level must indicate the 09478 * supervisor access attribute, and the MPRx[MPLn] control field for the master 09479 * must be set. If not, access terminates with an error response and no peripheral 09480 * access initiates. 09481 * 09482 * Values: 09483 * - 0 - This peripheral does not require supervisor privilege level for 09484 * accesses. 09485 * - 1 - This peripheral requires supervisor privilege level for accesses. 09486 */ 09487 /*@{*/ 09488 #define BP_AIPS_PACRM_SP7 (2U) /*!< Bit position for AIPS_PACRM_SP7. */ 09489 #define BM_AIPS_PACRM_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRM_SP7. */ 09490 #define BS_AIPS_PACRM_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP7. */ 09491 09492 /*! @brief Read current value of the AIPS_PACRM_SP7 field. */ 09493 #define BR_AIPS_PACRM_SP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP7))) 09494 09495 /*! @brief Format value for bitfield AIPS_PACRM_SP7. */ 09496 #define BF_AIPS_PACRM_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP7) & BM_AIPS_PACRM_SP7) 09497 09498 /*! @brief Set the SP7 field to a new value. */ 09499 #define BW_AIPS_PACRM_SP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP7), v)) 09500 /*@}*/ 09501 09502 /*! 09503 * @name Register AIPS_PACRM, field TP6[4] (RW) 09504 * 09505 * Determines whether the peripheral allows accesses from an untrusted master. 09506 * When this field is set and an access is attempted by an untrusted master, the 09507 * access terminates with an error response and no peripheral access initiates. 09508 * 09509 * Values: 09510 * - 0 - Accesses from an untrusted master are allowed. 09511 * - 1 - Accesses from an untrusted master are not allowed. 09512 */ 09513 /*@{*/ 09514 #define BP_AIPS_PACRM_TP6 (4U) /*!< Bit position for AIPS_PACRM_TP6. */ 09515 #define BM_AIPS_PACRM_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRM_TP6. */ 09516 #define BS_AIPS_PACRM_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP6. */ 09517 09518 /*! @brief Read current value of the AIPS_PACRM_TP6 field. */ 09519 #define BR_AIPS_PACRM_TP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP6))) 09520 09521 /*! @brief Format value for bitfield AIPS_PACRM_TP6. */ 09522 #define BF_AIPS_PACRM_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP6) & BM_AIPS_PACRM_TP6) 09523 09524 /*! @brief Set the TP6 field to a new value. */ 09525 #define BW_AIPS_PACRM_TP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP6), v)) 09526 /*@}*/ 09527 09528 /*! 09529 * @name Register AIPS_PACRM, field WP6[5] (RW) 09530 * 09531 * Determines whether the peripheral allows write accesses. When this field is 09532 * set and a write access is attempted, access terminates with an error response 09533 * and no peripheral access initiates. 09534 * 09535 * Values: 09536 * - 0 - This peripheral allows write accesses. 09537 * - 1 - This peripheral is write protected. 09538 */ 09539 /*@{*/ 09540 #define BP_AIPS_PACRM_WP6 (5U) /*!< Bit position for AIPS_PACRM_WP6. */ 09541 #define BM_AIPS_PACRM_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRM_WP6. */ 09542 #define BS_AIPS_PACRM_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP6. */ 09543 09544 /*! @brief Read current value of the AIPS_PACRM_WP6 field. */ 09545 #define BR_AIPS_PACRM_WP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP6))) 09546 09547 /*! @brief Format value for bitfield AIPS_PACRM_WP6. */ 09548 #define BF_AIPS_PACRM_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP6) & BM_AIPS_PACRM_WP6) 09549 09550 /*! @brief Set the WP6 field to a new value. */ 09551 #define BW_AIPS_PACRM_WP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP6), v)) 09552 /*@}*/ 09553 09554 /*! 09555 * @name Register AIPS_PACRM, field SP6[6] (RW) 09556 * 09557 * Determines whether the peripheral requires supervisor privilege level for 09558 * accesses. When this field is set, the master privilege level must indicate the 09559 * supervisor access attribute, and the MPRx[MPLn] control field for the master 09560 * must be set. If not, access terminates with an error response and no peripheral 09561 * access initiates. 09562 * 09563 * Values: 09564 * - 0 - This peripheral does not require supervisor privilege level for 09565 * accesses. 09566 * - 1 - This peripheral requires supervisor privilege level for accesses. 09567 */ 09568 /*@{*/ 09569 #define BP_AIPS_PACRM_SP6 (6U) /*!< Bit position for AIPS_PACRM_SP6. */ 09570 #define BM_AIPS_PACRM_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRM_SP6. */ 09571 #define BS_AIPS_PACRM_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP6. */ 09572 09573 /*! @brief Read current value of the AIPS_PACRM_SP6 field. */ 09574 #define BR_AIPS_PACRM_SP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP6))) 09575 09576 /*! @brief Format value for bitfield AIPS_PACRM_SP6. */ 09577 #define BF_AIPS_PACRM_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP6) & BM_AIPS_PACRM_SP6) 09578 09579 /*! @brief Set the SP6 field to a new value. */ 09580 #define BW_AIPS_PACRM_SP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP6), v)) 09581 /*@}*/ 09582 09583 /*! 09584 * @name Register AIPS_PACRM, field TP5[8] (RW) 09585 * 09586 * Determines whether the peripheral allows accesses from an untrusted master. 09587 * When this field is set and an access is attempted by an untrusted master, the 09588 * access terminates with an error response and no peripheral access initiates. 09589 * 09590 * Values: 09591 * - 0 - Accesses from an untrusted master are allowed. 09592 * - 1 - Accesses from an untrusted master are not allowed. 09593 */ 09594 /*@{*/ 09595 #define BP_AIPS_PACRM_TP5 (8U) /*!< Bit position for AIPS_PACRM_TP5. */ 09596 #define BM_AIPS_PACRM_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRM_TP5. */ 09597 #define BS_AIPS_PACRM_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP5. */ 09598 09599 /*! @brief Read current value of the AIPS_PACRM_TP5 field. */ 09600 #define BR_AIPS_PACRM_TP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP5))) 09601 09602 /*! @brief Format value for bitfield AIPS_PACRM_TP5. */ 09603 #define BF_AIPS_PACRM_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP5) & BM_AIPS_PACRM_TP5) 09604 09605 /*! @brief Set the TP5 field to a new value. */ 09606 #define BW_AIPS_PACRM_TP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP5), v)) 09607 /*@}*/ 09608 09609 /*! 09610 * @name Register AIPS_PACRM, field WP5[9] (RW) 09611 * 09612 * Determines whether the peripheral allows write accesses. When this field is 09613 * set and a write access is attempted, access terminates with an error response 09614 * and no peripheral access initiates. 09615 * 09616 * Values: 09617 * - 0 - This peripheral allows write accesses. 09618 * - 1 - This peripheral is write protected. 09619 */ 09620 /*@{*/ 09621 #define BP_AIPS_PACRM_WP5 (9U) /*!< Bit position for AIPS_PACRM_WP5. */ 09622 #define BM_AIPS_PACRM_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRM_WP5. */ 09623 #define BS_AIPS_PACRM_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP5. */ 09624 09625 /*! @brief Read current value of the AIPS_PACRM_WP5 field. */ 09626 #define BR_AIPS_PACRM_WP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP5))) 09627 09628 /*! @brief Format value for bitfield AIPS_PACRM_WP5. */ 09629 #define BF_AIPS_PACRM_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP5) & BM_AIPS_PACRM_WP5) 09630 09631 /*! @brief Set the WP5 field to a new value. */ 09632 #define BW_AIPS_PACRM_WP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP5), v)) 09633 /*@}*/ 09634 09635 /*! 09636 * @name Register AIPS_PACRM, field SP5[10] (RW) 09637 * 09638 * Determines whether the peripheral requires supervisor privilege level for 09639 * accesses. When this field is set, the master privilege level must indicate the 09640 * supervisor access attribute, and the MPRx[MPLn] control field for the master 09641 * must be set. If not, access terminates with an error response and no peripheral 09642 * access initiates. 09643 * 09644 * Values: 09645 * - 0 - This peripheral does not require supervisor privilege level for 09646 * accesses. 09647 * - 1 - This peripheral requires supervisor privilege level for accesses. 09648 */ 09649 /*@{*/ 09650 #define BP_AIPS_PACRM_SP5 (10U) /*!< Bit position for AIPS_PACRM_SP5. */ 09651 #define BM_AIPS_PACRM_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRM_SP5. */ 09652 #define BS_AIPS_PACRM_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP5. */ 09653 09654 /*! @brief Read current value of the AIPS_PACRM_SP5 field. */ 09655 #define BR_AIPS_PACRM_SP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP5))) 09656 09657 /*! @brief Format value for bitfield AIPS_PACRM_SP5. */ 09658 #define BF_AIPS_PACRM_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP5) & BM_AIPS_PACRM_SP5) 09659 09660 /*! @brief Set the SP5 field to a new value. */ 09661 #define BW_AIPS_PACRM_SP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP5), v)) 09662 /*@}*/ 09663 09664 /*! 09665 * @name Register AIPS_PACRM, field TP4[12] (RW) 09666 * 09667 * Determines whether the peripheral allows accesses from an untrusted master. 09668 * When this bit is set and an access is attempted by an untrusted master, the 09669 * access terminates with an error response and no peripheral access initiates. 09670 * 09671 * Values: 09672 * - 0 - Accesses from an untrusted master are allowed. 09673 * - 1 - Accesses from an untrusted master are not allowed. 09674 */ 09675 /*@{*/ 09676 #define BP_AIPS_PACRM_TP4 (12U) /*!< Bit position for AIPS_PACRM_TP4. */ 09677 #define BM_AIPS_PACRM_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRM_TP4. */ 09678 #define BS_AIPS_PACRM_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP4. */ 09679 09680 /*! @brief Read current value of the AIPS_PACRM_TP4 field. */ 09681 #define BR_AIPS_PACRM_TP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP4))) 09682 09683 /*! @brief Format value for bitfield AIPS_PACRM_TP4. */ 09684 #define BF_AIPS_PACRM_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP4) & BM_AIPS_PACRM_TP4) 09685 09686 /*! @brief Set the TP4 field to a new value. */ 09687 #define BW_AIPS_PACRM_TP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP4), v)) 09688 /*@}*/ 09689 09690 /*! 09691 * @name Register AIPS_PACRM, field WP4[13] (RW) 09692 * 09693 * Determines whether the peripheral allows write accesses. When this field is 09694 * set and a write access is attempted, access terminates with an error response 09695 * and no peripheral access initiates. 09696 * 09697 * Values: 09698 * - 0 - This peripheral allows write accesses. 09699 * - 1 - This peripheral is write protected. 09700 */ 09701 /*@{*/ 09702 #define BP_AIPS_PACRM_WP4 (13U) /*!< Bit position for AIPS_PACRM_WP4. */ 09703 #define BM_AIPS_PACRM_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRM_WP4. */ 09704 #define BS_AIPS_PACRM_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP4. */ 09705 09706 /*! @brief Read current value of the AIPS_PACRM_WP4 field. */ 09707 #define BR_AIPS_PACRM_WP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP4))) 09708 09709 /*! @brief Format value for bitfield AIPS_PACRM_WP4. */ 09710 #define BF_AIPS_PACRM_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP4) & BM_AIPS_PACRM_WP4) 09711 09712 /*! @brief Set the WP4 field to a new value. */ 09713 #define BW_AIPS_PACRM_WP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP4), v)) 09714 /*@}*/ 09715 09716 /*! 09717 * @name Register AIPS_PACRM, field SP4[14] (RW) 09718 * 09719 * Determines whether the peripheral requires supervisor privilege level for 09720 * access. When this bit is set, the master privilege level must indicate the 09721 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 09722 * set. If not, access terminates with an error response and no peripheral access 09723 * initiates. 09724 * 09725 * Values: 09726 * - 0 - This peripheral does not require supervisor privilege level for 09727 * accesses. 09728 * - 1 - This peripheral requires supervisor privilege level for accesses. 09729 */ 09730 /*@{*/ 09731 #define BP_AIPS_PACRM_SP4 (14U) /*!< Bit position for AIPS_PACRM_SP4. */ 09732 #define BM_AIPS_PACRM_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRM_SP4. */ 09733 #define BS_AIPS_PACRM_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP4. */ 09734 09735 /*! @brief Read current value of the AIPS_PACRM_SP4 field. */ 09736 #define BR_AIPS_PACRM_SP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP4))) 09737 09738 /*! @brief Format value for bitfield AIPS_PACRM_SP4. */ 09739 #define BF_AIPS_PACRM_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP4) & BM_AIPS_PACRM_SP4) 09740 09741 /*! @brief Set the SP4 field to a new value. */ 09742 #define BW_AIPS_PACRM_SP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP4), v)) 09743 /*@}*/ 09744 09745 /*! 09746 * @name Register AIPS_PACRM, field TP3[16] (RW) 09747 * 09748 * Determines whether the peripheral allows accesses from an untrusted master. 09749 * When this field is set and an access is attempted by an untrusted master, the 09750 * access terminates with an error response and no peripheral access initiates. 09751 * 09752 * Values: 09753 * - 0 - Accesses from an untrusted master are allowed. 09754 * - 1 - Accesses from an untrusted master are not allowed. 09755 */ 09756 /*@{*/ 09757 #define BP_AIPS_PACRM_TP3 (16U) /*!< Bit position for AIPS_PACRM_TP3. */ 09758 #define BM_AIPS_PACRM_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRM_TP3. */ 09759 #define BS_AIPS_PACRM_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP3. */ 09760 09761 /*! @brief Read current value of the AIPS_PACRM_TP3 field. */ 09762 #define BR_AIPS_PACRM_TP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP3))) 09763 09764 /*! @brief Format value for bitfield AIPS_PACRM_TP3. */ 09765 #define BF_AIPS_PACRM_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP3) & BM_AIPS_PACRM_TP3) 09766 09767 /*! @brief Set the TP3 field to a new value. */ 09768 #define BW_AIPS_PACRM_TP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP3), v)) 09769 /*@}*/ 09770 09771 /*! 09772 * @name Register AIPS_PACRM, field WP3[17] (RW) 09773 * 09774 * Determines whether the peripheral allows write accesss. When this bit is set 09775 * and a write access is attempted, access terminates with an error response and 09776 * no peripheral access initiates. 09777 * 09778 * Values: 09779 * - 0 - This peripheral allows write accesses. 09780 * - 1 - This peripheral is write protected. 09781 */ 09782 /*@{*/ 09783 #define BP_AIPS_PACRM_WP3 (17U) /*!< Bit position for AIPS_PACRM_WP3. */ 09784 #define BM_AIPS_PACRM_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRM_WP3. */ 09785 #define BS_AIPS_PACRM_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP3. */ 09786 09787 /*! @brief Read current value of the AIPS_PACRM_WP3 field. */ 09788 #define BR_AIPS_PACRM_WP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP3))) 09789 09790 /*! @brief Format value for bitfield AIPS_PACRM_WP3. */ 09791 #define BF_AIPS_PACRM_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP3) & BM_AIPS_PACRM_WP3) 09792 09793 /*! @brief Set the WP3 field to a new value. */ 09794 #define BW_AIPS_PACRM_WP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP3), v)) 09795 /*@}*/ 09796 09797 /*! 09798 * @name Register AIPS_PACRM, field SP3[18] (RW) 09799 * 09800 * Determines whether the peripheral requires supervisor privilege level for 09801 * accesses. When this field is set, the master privilege level must indicate the 09802 * supervisor access attribute, and the MPRx[MPLn] control field for the master 09803 * must be set. If not, access terminates with an error response and no peripheral 09804 * access initiates. 09805 * 09806 * Values: 09807 * - 0 - This peripheral does not require supervisor privilege level for 09808 * accesses. 09809 * - 1 - This peripheral requires supervisor privilege level for accesses. 09810 */ 09811 /*@{*/ 09812 #define BP_AIPS_PACRM_SP3 (18U) /*!< Bit position for AIPS_PACRM_SP3. */ 09813 #define BM_AIPS_PACRM_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRM_SP3. */ 09814 #define BS_AIPS_PACRM_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP3. */ 09815 09816 /*! @brief Read current value of the AIPS_PACRM_SP3 field. */ 09817 #define BR_AIPS_PACRM_SP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP3))) 09818 09819 /*! @brief Format value for bitfield AIPS_PACRM_SP3. */ 09820 #define BF_AIPS_PACRM_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP3) & BM_AIPS_PACRM_SP3) 09821 09822 /*! @brief Set the SP3 field to a new value. */ 09823 #define BW_AIPS_PACRM_SP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP3), v)) 09824 /*@}*/ 09825 09826 /*! 09827 * @name Register AIPS_PACRM, field TP2[20] (RW) 09828 * 09829 * Determines whether the peripheral allows accesses from an untrusted master. 09830 * When this bit is set and an access is attempted by an untrusted master, the 09831 * access terminates with an error response and no peripheral access initiates. 09832 * 09833 * Values: 09834 * - 0 - Accesses from an untrusted master are allowed. 09835 * - 1 - Accesses from an untrusted master are not allowed. 09836 */ 09837 /*@{*/ 09838 #define BP_AIPS_PACRM_TP2 (20U) /*!< Bit position for AIPS_PACRM_TP2. */ 09839 #define BM_AIPS_PACRM_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRM_TP2. */ 09840 #define BS_AIPS_PACRM_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP2. */ 09841 09842 /*! @brief Read current value of the AIPS_PACRM_TP2 field. */ 09843 #define BR_AIPS_PACRM_TP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP2))) 09844 09845 /*! @brief Format value for bitfield AIPS_PACRM_TP2. */ 09846 #define BF_AIPS_PACRM_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP2) & BM_AIPS_PACRM_TP2) 09847 09848 /*! @brief Set the TP2 field to a new value. */ 09849 #define BW_AIPS_PACRM_TP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP2), v)) 09850 /*@}*/ 09851 09852 /*! 09853 * @name Register AIPS_PACRM, field WP2[21] (RW) 09854 * 09855 * Determines whether the peripheral allows write accesses. When this field is 09856 * set and a write access is attempted, access terminates with an error response 09857 * and no peripheral access initiates. 09858 * 09859 * Values: 09860 * - 0 - This peripheral allows write accesses. 09861 * - 1 - This peripheral is write protected. 09862 */ 09863 /*@{*/ 09864 #define BP_AIPS_PACRM_WP2 (21U) /*!< Bit position for AIPS_PACRM_WP2. */ 09865 #define BM_AIPS_PACRM_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRM_WP2. */ 09866 #define BS_AIPS_PACRM_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP2. */ 09867 09868 /*! @brief Read current value of the AIPS_PACRM_WP2 field. */ 09869 #define BR_AIPS_PACRM_WP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP2))) 09870 09871 /*! @brief Format value for bitfield AIPS_PACRM_WP2. */ 09872 #define BF_AIPS_PACRM_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP2) & BM_AIPS_PACRM_WP2) 09873 09874 /*! @brief Set the WP2 field to a new value. */ 09875 #define BW_AIPS_PACRM_WP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP2), v)) 09876 /*@}*/ 09877 09878 /*! 09879 * @name Register AIPS_PACRM, field SP2[22] (RW) 09880 * 09881 * Determines whether the peripheral requires supervisor privilege level for 09882 * access. When this bit is set, the master privilege level must indicate the 09883 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 09884 * set. If not, access terminates with an error response and no peripheral access 09885 * initiates. 09886 * 09887 * Values: 09888 * - 0 - This peripheral does not require supervisor privilege level for 09889 * accesses. 09890 * - 1 - This peripheral requires supervisor privilege level for accesses. 09891 */ 09892 /*@{*/ 09893 #define BP_AIPS_PACRM_SP2 (22U) /*!< Bit position for AIPS_PACRM_SP2. */ 09894 #define BM_AIPS_PACRM_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRM_SP2. */ 09895 #define BS_AIPS_PACRM_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP2. */ 09896 09897 /*! @brief Read current value of the AIPS_PACRM_SP2 field. */ 09898 #define BR_AIPS_PACRM_SP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP2))) 09899 09900 /*! @brief Format value for bitfield AIPS_PACRM_SP2. */ 09901 #define BF_AIPS_PACRM_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP2) & BM_AIPS_PACRM_SP2) 09902 09903 /*! @brief Set the SP2 field to a new value. */ 09904 #define BW_AIPS_PACRM_SP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP2), v)) 09905 /*@}*/ 09906 09907 /*! 09908 * @name Register AIPS_PACRM, field TP1[24] (RW) 09909 * 09910 * Determines whether the peripheral allows accesses from an untrusted master. 09911 * When this field is set and an access is attempted by an untrusted master, the 09912 * access terminates with an error response and no peripheral access initiates. 09913 * 09914 * Values: 09915 * - 0 - Accesses from an untrusted master are allowed. 09916 * - 1 - Accesses from an untrusted master are not allowed. 09917 */ 09918 /*@{*/ 09919 #define BP_AIPS_PACRM_TP1 (24U) /*!< Bit position for AIPS_PACRM_TP1. */ 09920 #define BM_AIPS_PACRM_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRM_TP1. */ 09921 #define BS_AIPS_PACRM_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP1. */ 09922 09923 /*! @brief Read current value of the AIPS_PACRM_TP1 field. */ 09924 #define BR_AIPS_PACRM_TP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP1))) 09925 09926 /*! @brief Format value for bitfield AIPS_PACRM_TP1. */ 09927 #define BF_AIPS_PACRM_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP1) & BM_AIPS_PACRM_TP1) 09928 09929 /*! @brief Set the TP1 field to a new value. */ 09930 #define BW_AIPS_PACRM_TP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP1), v)) 09931 /*@}*/ 09932 09933 /*! 09934 * @name Register AIPS_PACRM, field WP1[25] (RW) 09935 * 09936 * Determines whether the peripheral allows write accesses. When this field is 09937 * set and a write access is attempted, access terminates with an error response 09938 * and no peripheral access initiates. 09939 * 09940 * Values: 09941 * - 0 - This peripheral allows write accesses. 09942 * - 1 - This peripheral is write protected. 09943 */ 09944 /*@{*/ 09945 #define BP_AIPS_PACRM_WP1 (25U) /*!< Bit position for AIPS_PACRM_WP1. */ 09946 #define BM_AIPS_PACRM_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRM_WP1. */ 09947 #define BS_AIPS_PACRM_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP1. */ 09948 09949 /*! @brief Read current value of the AIPS_PACRM_WP1 field. */ 09950 #define BR_AIPS_PACRM_WP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP1))) 09951 09952 /*! @brief Format value for bitfield AIPS_PACRM_WP1. */ 09953 #define BF_AIPS_PACRM_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP1) & BM_AIPS_PACRM_WP1) 09954 09955 /*! @brief Set the WP1 field to a new value. */ 09956 #define BW_AIPS_PACRM_WP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP1), v)) 09957 /*@}*/ 09958 09959 /*! 09960 * @name Register AIPS_PACRM, field SP1[26] (RW) 09961 * 09962 * Determines whether the peripheral requires supervisor privilege level for 09963 * access. When this field is set, the master privilege level must indicate the 09964 * supervisor access attribute, and the MPRx[MPLn] control field for the master must 09965 * be set. If not, access terminates with an error response and no peripheral 09966 * access initiates. 09967 * 09968 * Values: 09969 * - 0 - This peripheral does not require supervisor privilege level for 09970 * accesses. 09971 * - 1 - This peripheral requires supervisor privilege level for accesses. 09972 */ 09973 /*@{*/ 09974 #define BP_AIPS_PACRM_SP1 (26U) /*!< Bit position for AIPS_PACRM_SP1. */ 09975 #define BM_AIPS_PACRM_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRM_SP1. */ 09976 #define BS_AIPS_PACRM_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP1. */ 09977 09978 /*! @brief Read current value of the AIPS_PACRM_SP1 field. */ 09979 #define BR_AIPS_PACRM_SP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP1))) 09980 09981 /*! @brief Format value for bitfield AIPS_PACRM_SP1. */ 09982 #define BF_AIPS_PACRM_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP1) & BM_AIPS_PACRM_SP1) 09983 09984 /*! @brief Set the SP1 field to a new value. */ 09985 #define BW_AIPS_PACRM_SP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP1), v)) 09986 /*@}*/ 09987 09988 /*! 09989 * @name Register AIPS_PACRM, field TP0[28] (RW) 09990 * 09991 * Determines whether the peripheral allows accesses from an untrusted master. 09992 * When this bit is set and an access is attempted by an untrusted master, the 09993 * access terminates with an error response and no peripheral access initiates. 09994 * 09995 * Values: 09996 * - 0 - Accesses from an untrusted master are allowed. 09997 * - 1 - Accesses from an untrusted master are not allowed. 09998 */ 09999 /*@{*/ 10000 #define BP_AIPS_PACRM_TP0 (28U) /*!< Bit position for AIPS_PACRM_TP0. */ 10001 #define BM_AIPS_PACRM_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRM_TP0. */ 10002 #define BS_AIPS_PACRM_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRM_TP0. */ 10003 10004 /*! @brief Read current value of the AIPS_PACRM_TP0 field. */ 10005 #define BR_AIPS_PACRM_TP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP0))) 10006 10007 /*! @brief Format value for bitfield AIPS_PACRM_TP0. */ 10008 #define BF_AIPS_PACRM_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_TP0) & BM_AIPS_PACRM_TP0) 10009 10010 /*! @brief Set the TP0 field to a new value. */ 10011 #define BW_AIPS_PACRM_TP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_TP0), v)) 10012 /*@}*/ 10013 10014 /*! 10015 * @name Register AIPS_PACRM, field WP0[29] (RW) 10016 * 10017 * Determines whether the peripheral allows write accesses. When this field is 10018 * set and a write access is attempted, access terminates with an error response 10019 * and no peripheral access initiates. 10020 * 10021 * Values: 10022 * - 0 - This peripheral allows write accesses. 10023 * - 1 - This peripheral is write protected. 10024 */ 10025 /*@{*/ 10026 #define BP_AIPS_PACRM_WP0 (29U) /*!< Bit position for AIPS_PACRM_WP0. */ 10027 #define BM_AIPS_PACRM_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRM_WP0. */ 10028 #define BS_AIPS_PACRM_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRM_WP0. */ 10029 10030 /*! @brief Read current value of the AIPS_PACRM_WP0 field. */ 10031 #define BR_AIPS_PACRM_WP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP0))) 10032 10033 /*! @brief Format value for bitfield AIPS_PACRM_WP0. */ 10034 #define BF_AIPS_PACRM_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_WP0) & BM_AIPS_PACRM_WP0) 10035 10036 /*! @brief Set the WP0 field to a new value. */ 10037 #define BW_AIPS_PACRM_WP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_WP0), v)) 10038 /*@}*/ 10039 10040 /*! 10041 * @name Register AIPS_PACRM, field SP0[30] (RW) 10042 * 10043 * Determines whether the peripheral requires supervisor privilege level for 10044 * accesses. When this field is set, the master privilege level must indicate the 10045 * supervisor access attribute, and the MPRx[MPLn] control field for the master 10046 * must be set. If not, access terminates with an error response and no peripheral 10047 * access initiates. 10048 * 10049 * Values: 10050 * - 0 - This peripheral does not require supervisor privilege level for 10051 * accesses. 10052 * - 1 - This peripheral requires supervisor privilege level for accesses. 10053 */ 10054 /*@{*/ 10055 #define BP_AIPS_PACRM_SP0 (30U) /*!< Bit position for AIPS_PACRM_SP0. */ 10056 #define BM_AIPS_PACRM_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRM_SP0. */ 10057 #define BS_AIPS_PACRM_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRM_SP0. */ 10058 10059 /*! @brief Read current value of the AIPS_PACRM_SP0 field. */ 10060 #define BR_AIPS_PACRM_SP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP0))) 10061 10062 /*! @brief Format value for bitfield AIPS_PACRM_SP0. */ 10063 #define BF_AIPS_PACRM_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRM_SP0) & BM_AIPS_PACRM_SP0) 10064 10065 /*! @brief Set the SP0 field to a new value. */ 10066 #define BW_AIPS_PACRM_SP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRM_ADDR(x), BP_AIPS_PACRM_SP0), v)) 10067 /*@}*/ 10068 10069 /******************************************************************************* 10070 * HW_AIPS_PACRN - Peripheral Access Control Register 10071 ******************************************************************************/ 10072 10073 /*! 10074 * @brief HW_AIPS_PACRN - Peripheral Access Control Register (RW) 10075 * 10076 * Reset value: 0x44444444U 10077 * 10078 * This section describes PACR registers E-P, which control peripheral slots 10079 * 32-127. See PACRPeripheral Access Control Register for the description of these 10080 * registers. 10081 */ 10082 typedef union _hw_aips_pacrn 10083 { 10084 uint32_t U; 10085 struct _hw_aips_pacrn_bitfields 10086 { 10087 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 10088 uint32_t WP7 : 1; /*!< [1] Write Protect */ 10089 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 10090 uint32_t RESERVED0 : 1; /*!< [3] */ 10091 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 10092 uint32_t WP6 : 1; /*!< [5] Write Protect */ 10093 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 10094 uint32_t RESERVED1 : 1; /*!< [7] */ 10095 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 10096 uint32_t WP5 : 1; /*!< [9] Write Protect */ 10097 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 10098 uint32_t RESERVED2 : 1; /*!< [11] */ 10099 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 10100 uint32_t WP4 : 1; /*!< [13] Write Protect */ 10101 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 10102 uint32_t RESERVED3 : 1; /*!< [15] */ 10103 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 10104 uint32_t WP3 : 1; /*!< [17] Write Protect */ 10105 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 10106 uint32_t RESERVED4 : 1; /*!< [19] */ 10107 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 10108 uint32_t WP2 : 1; /*!< [21] Write Protect */ 10109 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 10110 uint32_t RESERVED5 : 1; /*!< [23] */ 10111 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 10112 uint32_t WP1 : 1; /*!< [25] Write Protect */ 10113 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 10114 uint32_t RESERVED6 : 1; /*!< [27] */ 10115 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 10116 uint32_t WP0 : 1; /*!< [29] Write Protect */ 10117 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 10118 uint32_t RESERVED7 : 1; /*!< [31] */ 10119 } B; 10120 } hw_aips_pacrn_t; 10121 10122 /*! 10123 * @name Constants and macros for entire AIPS_PACRN register 10124 */ 10125 /*@{*/ 10126 #define HW_AIPS_PACRN_ADDR(x) ((x) + 0x64U) 10127 10128 #define HW_AIPS_PACRN(x) (*(__IO hw_aips_pacrn_t *) HW_AIPS_PACRN_ADDR(x)) 10129 #define HW_AIPS_PACRN_RD(x) (ADDRESS_READ(hw_aips_pacrn_t, HW_AIPS_PACRN_ADDR(x))) 10130 #define HW_AIPS_PACRN_WR(x, v) (ADDRESS_WRITE(hw_aips_pacrn_t, HW_AIPS_PACRN_ADDR(x), v)) 10131 #define HW_AIPS_PACRN_SET(x, v) (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) | (v))) 10132 #define HW_AIPS_PACRN_CLR(x, v) (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) & ~(v))) 10133 #define HW_AIPS_PACRN_TOG(x, v) (HW_AIPS_PACRN_WR(x, HW_AIPS_PACRN_RD(x) ^ (v))) 10134 /*@}*/ 10135 10136 /* 10137 * Constants & macros for individual AIPS_PACRN bitfields 10138 */ 10139 10140 /*! 10141 * @name Register AIPS_PACRN, field TP7[0] (RW) 10142 * 10143 * Determines whether the peripheral allows accesses from an untrusted master. 10144 * When this field is set and an access is attempted by an untrusted master, the 10145 * access terminates with an error response and no peripheral access initiates. 10146 * 10147 * Values: 10148 * - 0 - Accesses from an untrusted master are allowed. 10149 * - 1 - Accesses from an untrusted master are not allowed. 10150 */ 10151 /*@{*/ 10152 #define BP_AIPS_PACRN_TP7 (0U) /*!< Bit position for AIPS_PACRN_TP7. */ 10153 #define BM_AIPS_PACRN_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRN_TP7. */ 10154 #define BS_AIPS_PACRN_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP7. */ 10155 10156 /*! @brief Read current value of the AIPS_PACRN_TP7 field. */ 10157 #define BR_AIPS_PACRN_TP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP7))) 10158 10159 /*! @brief Format value for bitfield AIPS_PACRN_TP7. */ 10160 #define BF_AIPS_PACRN_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP7) & BM_AIPS_PACRN_TP7) 10161 10162 /*! @brief Set the TP7 field to a new value. */ 10163 #define BW_AIPS_PACRN_TP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP7), v)) 10164 /*@}*/ 10165 10166 /*! 10167 * @name Register AIPS_PACRN, field WP7[1] (RW) 10168 * 10169 * Determines whether the peripheral allows write accesses. When this field is 10170 * set and a write access is attempted, access terminates with an error response 10171 * and no peripheral access initiates. 10172 * 10173 * Values: 10174 * - 0 - This peripheral allows write accesses. 10175 * - 1 - This peripheral is write protected. 10176 */ 10177 /*@{*/ 10178 #define BP_AIPS_PACRN_WP7 (1U) /*!< Bit position for AIPS_PACRN_WP7. */ 10179 #define BM_AIPS_PACRN_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRN_WP7. */ 10180 #define BS_AIPS_PACRN_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP7. */ 10181 10182 /*! @brief Read current value of the AIPS_PACRN_WP7 field. */ 10183 #define BR_AIPS_PACRN_WP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP7))) 10184 10185 /*! @brief Format value for bitfield AIPS_PACRN_WP7. */ 10186 #define BF_AIPS_PACRN_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP7) & BM_AIPS_PACRN_WP7) 10187 10188 /*! @brief Set the WP7 field to a new value. */ 10189 #define BW_AIPS_PACRN_WP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP7), v)) 10190 /*@}*/ 10191 10192 /*! 10193 * @name Register AIPS_PACRN, field SP7[2] (RW) 10194 * 10195 * Determines whether the peripheral requires supervisor privilege level for 10196 * accesses. When this field is set, the master privilege level must indicate the 10197 * supervisor access attribute, and the MPRx[MPLn] control field for the master 10198 * must be set. If not, access terminates with an error response and no peripheral 10199 * access initiates. 10200 * 10201 * Values: 10202 * - 0 - This peripheral does not require supervisor privilege level for 10203 * accesses. 10204 * - 1 - This peripheral requires supervisor privilege level for accesses. 10205 */ 10206 /*@{*/ 10207 #define BP_AIPS_PACRN_SP7 (2U) /*!< Bit position for AIPS_PACRN_SP7. */ 10208 #define BM_AIPS_PACRN_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRN_SP7. */ 10209 #define BS_AIPS_PACRN_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP7. */ 10210 10211 /*! @brief Read current value of the AIPS_PACRN_SP7 field. */ 10212 #define BR_AIPS_PACRN_SP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP7))) 10213 10214 /*! @brief Format value for bitfield AIPS_PACRN_SP7. */ 10215 #define BF_AIPS_PACRN_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP7) & BM_AIPS_PACRN_SP7) 10216 10217 /*! @brief Set the SP7 field to a new value. */ 10218 #define BW_AIPS_PACRN_SP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP7), v)) 10219 /*@}*/ 10220 10221 /*! 10222 * @name Register AIPS_PACRN, field TP6[4] (RW) 10223 * 10224 * Determines whether the peripheral allows accesses from an untrusted master. 10225 * When this field is set and an access is attempted by an untrusted master, the 10226 * access terminates with an error response and no peripheral access initiates. 10227 * 10228 * Values: 10229 * - 0 - Accesses from an untrusted master are allowed. 10230 * - 1 - Accesses from an untrusted master are not allowed. 10231 */ 10232 /*@{*/ 10233 #define BP_AIPS_PACRN_TP6 (4U) /*!< Bit position for AIPS_PACRN_TP6. */ 10234 #define BM_AIPS_PACRN_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRN_TP6. */ 10235 #define BS_AIPS_PACRN_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP6. */ 10236 10237 /*! @brief Read current value of the AIPS_PACRN_TP6 field. */ 10238 #define BR_AIPS_PACRN_TP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP6))) 10239 10240 /*! @brief Format value for bitfield AIPS_PACRN_TP6. */ 10241 #define BF_AIPS_PACRN_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP6) & BM_AIPS_PACRN_TP6) 10242 10243 /*! @brief Set the TP6 field to a new value. */ 10244 #define BW_AIPS_PACRN_TP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP6), v)) 10245 /*@}*/ 10246 10247 /*! 10248 * @name Register AIPS_PACRN, field WP6[5] (RW) 10249 * 10250 * Determines whether the peripheral allows write accesses. When this field is 10251 * set and a write access is attempted, access terminates with an error response 10252 * and no peripheral access initiates. 10253 * 10254 * Values: 10255 * - 0 - This peripheral allows write accesses. 10256 * - 1 - This peripheral is write protected. 10257 */ 10258 /*@{*/ 10259 #define BP_AIPS_PACRN_WP6 (5U) /*!< Bit position for AIPS_PACRN_WP6. */ 10260 #define BM_AIPS_PACRN_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRN_WP6. */ 10261 #define BS_AIPS_PACRN_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP6. */ 10262 10263 /*! @brief Read current value of the AIPS_PACRN_WP6 field. */ 10264 #define BR_AIPS_PACRN_WP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP6))) 10265 10266 /*! @brief Format value for bitfield AIPS_PACRN_WP6. */ 10267 #define BF_AIPS_PACRN_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP6) & BM_AIPS_PACRN_WP6) 10268 10269 /*! @brief Set the WP6 field to a new value. */ 10270 #define BW_AIPS_PACRN_WP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP6), v)) 10271 /*@}*/ 10272 10273 /*! 10274 * @name Register AIPS_PACRN, field SP6[6] (RW) 10275 * 10276 * Determines whether the peripheral requires supervisor privilege level for 10277 * accesses. When this field is set, the master privilege level must indicate the 10278 * supervisor access attribute, and the MPRx[MPLn] control field for the master 10279 * must be set. If not, access terminates with an error response and no peripheral 10280 * access initiates. 10281 * 10282 * Values: 10283 * - 0 - This peripheral does not require supervisor privilege level for 10284 * accesses. 10285 * - 1 - This peripheral requires supervisor privilege level for accesses. 10286 */ 10287 /*@{*/ 10288 #define BP_AIPS_PACRN_SP6 (6U) /*!< Bit position for AIPS_PACRN_SP6. */ 10289 #define BM_AIPS_PACRN_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRN_SP6. */ 10290 #define BS_AIPS_PACRN_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP6. */ 10291 10292 /*! @brief Read current value of the AIPS_PACRN_SP6 field. */ 10293 #define BR_AIPS_PACRN_SP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP6))) 10294 10295 /*! @brief Format value for bitfield AIPS_PACRN_SP6. */ 10296 #define BF_AIPS_PACRN_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP6) & BM_AIPS_PACRN_SP6) 10297 10298 /*! @brief Set the SP6 field to a new value. */ 10299 #define BW_AIPS_PACRN_SP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP6), v)) 10300 /*@}*/ 10301 10302 /*! 10303 * @name Register AIPS_PACRN, field TP5[8] (RW) 10304 * 10305 * Determines whether the peripheral allows accesses from an untrusted master. 10306 * When this field is set and an access is attempted by an untrusted master, the 10307 * access terminates with an error response and no peripheral access initiates. 10308 * 10309 * Values: 10310 * - 0 - Accesses from an untrusted master are allowed. 10311 * - 1 - Accesses from an untrusted master are not allowed. 10312 */ 10313 /*@{*/ 10314 #define BP_AIPS_PACRN_TP5 (8U) /*!< Bit position for AIPS_PACRN_TP5. */ 10315 #define BM_AIPS_PACRN_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRN_TP5. */ 10316 #define BS_AIPS_PACRN_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP5. */ 10317 10318 /*! @brief Read current value of the AIPS_PACRN_TP5 field. */ 10319 #define BR_AIPS_PACRN_TP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP5))) 10320 10321 /*! @brief Format value for bitfield AIPS_PACRN_TP5. */ 10322 #define BF_AIPS_PACRN_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP5) & BM_AIPS_PACRN_TP5) 10323 10324 /*! @brief Set the TP5 field to a new value. */ 10325 #define BW_AIPS_PACRN_TP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP5), v)) 10326 /*@}*/ 10327 10328 /*! 10329 * @name Register AIPS_PACRN, field WP5[9] (RW) 10330 * 10331 * Determines whether the peripheral allows write accesses. When this field is 10332 * set and a write access is attempted, access terminates with an error response 10333 * and no peripheral access initiates. 10334 * 10335 * Values: 10336 * - 0 - This peripheral allows write accesses. 10337 * - 1 - This peripheral is write protected. 10338 */ 10339 /*@{*/ 10340 #define BP_AIPS_PACRN_WP5 (9U) /*!< Bit position for AIPS_PACRN_WP5. */ 10341 #define BM_AIPS_PACRN_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRN_WP5. */ 10342 #define BS_AIPS_PACRN_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP5. */ 10343 10344 /*! @brief Read current value of the AIPS_PACRN_WP5 field. */ 10345 #define BR_AIPS_PACRN_WP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP5))) 10346 10347 /*! @brief Format value for bitfield AIPS_PACRN_WP5. */ 10348 #define BF_AIPS_PACRN_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP5) & BM_AIPS_PACRN_WP5) 10349 10350 /*! @brief Set the WP5 field to a new value. */ 10351 #define BW_AIPS_PACRN_WP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP5), v)) 10352 /*@}*/ 10353 10354 /*! 10355 * @name Register AIPS_PACRN, field SP5[10] (RW) 10356 * 10357 * Determines whether the peripheral requires supervisor privilege level for 10358 * accesses. When this field is set, the master privilege level must indicate the 10359 * supervisor access attribute, and the MPRx[MPLn] control field for the master 10360 * must be set. If not, access terminates with an error response and no peripheral 10361 * access initiates. 10362 * 10363 * Values: 10364 * - 0 - This peripheral does not require supervisor privilege level for 10365 * accesses. 10366 * - 1 - This peripheral requires supervisor privilege level for accesses. 10367 */ 10368 /*@{*/ 10369 #define BP_AIPS_PACRN_SP5 (10U) /*!< Bit position for AIPS_PACRN_SP5. */ 10370 #define BM_AIPS_PACRN_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRN_SP5. */ 10371 #define BS_AIPS_PACRN_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP5. */ 10372 10373 /*! @brief Read current value of the AIPS_PACRN_SP5 field. */ 10374 #define BR_AIPS_PACRN_SP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP5))) 10375 10376 /*! @brief Format value for bitfield AIPS_PACRN_SP5. */ 10377 #define BF_AIPS_PACRN_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP5) & BM_AIPS_PACRN_SP5) 10378 10379 /*! @brief Set the SP5 field to a new value. */ 10380 #define BW_AIPS_PACRN_SP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP5), v)) 10381 /*@}*/ 10382 10383 /*! 10384 * @name Register AIPS_PACRN, field TP4[12] (RW) 10385 * 10386 * Determines whether the peripheral allows accesses from an untrusted master. 10387 * When this bit is set and an access is attempted by an untrusted master, the 10388 * access terminates with an error response and no peripheral access initiates. 10389 * 10390 * Values: 10391 * - 0 - Accesses from an untrusted master are allowed. 10392 * - 1 - Accesses from an untrusted master are not allowed. 10393 */ 10394 /*@{*/ 10395 #define BP_AIPS_PACRN_TP4 (12U) /*!< Bit position for AIPS_PACRN_TP4. */ 10396 #define BM_AIPS_PACRN_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRN_TP4. */ 10397 #define BS_AIPS_PACRN_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP4. */ 10398 10399 /*! @brief Read current value of the AIPS_PACRN_TP4 field. */ 10400 #define BR_AIPS_PACRN_TP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP4))) 10401 10402 /*! @brief Format value for bitfield AIPS_PACRN_TP4. */ 10403 #define BF_AIPS_PACRN_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP4) & BM_AIPS_PACRN_TP4) 10404 10405 /*! @brief Set the TP4 field to a new value. */ 10406 #define BW_AIPS_PACRN_TP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP4), v)) 10407 /*@}*/ 10408 10409 /*! 10410 * @name Register AIPS_PACRN, field WP4[13] (RW) 10411 * 10412 * Determines whether the peripheral allows write accesses. When this field is 10413 * set and a write access is attempted, access terminates with an error response 10414 * and no peripheral access initiates. 10415 * 10416 * Values: 10417 * - 0 - This peripheral allows write accesses. 10418 * - 1 - This peripheral is write protected. 10419 */ 10420 /*@{*/ 10421 #define BP_AIPS_PACRN_WP4 (13U) /*!< Bit position for AIPS_PACRN_WP4. */ 10422 #define BM_AIPS_PACRN_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRN_WP4. */ 10423 #define BS_AIPS_PACRN_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP4. */ 10424 10425 /*! @brief Read current value of the AIPS_PACRN_WP4 field. */ 10426 #define BR_AIPS_PACRN_WP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP4))) 10427 10428 /*! @brief Format value for bitfield AIPS_PACRN_WP4. */ 10429 #define BF_AIPS_PACRN_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP4) & BM_AIPS_PACRN_WP4) 10430 10431 /*! @brief Set the WP4 field to a new value. */ 10432 #define BW_AIPS_PACRN_WP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP4), v)) 10433 /*@}*/ 10434 10435 /*! 10436 * @name Register AIPS_PACRN, field SP4[14] (RW) 10437 * 10438 * Determines whether the peripheral requires supervisor privilege level for 10439 * access. When this bit is set, the master privilege level must indicate the 10440 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 10441 * set. If not, access terminates with an error response and no peripheral access 10442 * initiates. 10443 * 10444 * Values: 10445 * - 0 - This peripheral does not require supervisor privilege level for 10446 * accesses. 10447 * - 1 - This peripheral requires supervisor privilege level for accesses. 10448 */ 10449 /*@{*/ 10450 #define BP_AIPS_PACRN_SP4 (14U) /*!< Bit position for AIPS_PACRN_SP4. */ 10451 #define BM_AIPS_PACRN_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRN_SP4. */ 10452 #define BS_AIPS_PACRN_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP4. */ 10453 10454 /*! @brief Read current value of the AIPS_PACRN_SP4 field. */ 10455 #define BR_AIPS_PACRN_SP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP4))) 10456 10457 /*! @brief Format value for bitfield AIPS_PACRN_SP4. */ 10458 #define BF_AIPS_PACRN_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP4) & BM_AIPS_PACRN_SP4) 10459 10460 /*! @brief Set the SP4 field to a new value. */ 10461 #define BW_AIPS_PACRN_SP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP4), v)) 10462 /*@}*/ 10463 10464 /*! 10465 * @name Register AIPS_PACRN, field TP3[16] (RW) 10466 * 10467 * Determines whether the peripheral allows accesses from an untrusted master. 10468 * When this field is set and an access is attempted by an untrusted master, the 10469 * access terminates with an error response and no peripheral access initiates. 10470 * 10471 * Values: 10472 * - 0 - Accesses from an untrusted master are allowed. 10473 * - 1 - Accesses from an untrusted master are not allowed. 10474 */ 10475 /*@{*/ 10476 #define BP_AIPS_PACRN_TP3 (16U) /*!< Bit position for AIPS_PACRN_TP3. */ 10477 #define BM_AIPS_PACRN_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRN_TP3. */ 10478 #define BS_AIPS_PACRN_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP3. */ 10479 10480 /*! @brief Read current value of the AIPS_PACRN_TP3 field. */ 10481 #define BR_AIPS_PACRN_TP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP3))) 10482 10483 /*! @brief Format value for bitfield AIPS_PACRN_TP3. */ 10484 #define BF_AIPS_PACRN_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP3) & BM_AIPS_PACRN_TP3) 10485 10486 /*! @brief Set the TP3 field to a new value. */ 10487 #define BW_AIPS_PACRN_TP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP3), v)) 10488 /*@}*/ 10489 10490 /*! 10491 * @name Register AIPS_PACRN, field WP3[17] (RW) 10492 * 10493 * Determines whether the peripheral allows write accesss. When this bit is set 10494 * and a write access is attempted, access terminates with an error response and 10495 * no peripheral access initiates. 10496 * 10497 * Values: 10498 * - 0 - This peripheral allows write accesses. 10499 * - 1 - This peripheral is write protected. 10500 */ 10501 /*@{*/ 10502 #define BP_AIPS_PACRN_WP3 (17U) /*!< Bit position for AIPS_PACRN_WP3. */ 10503 #define BM_AIPS_PACRN_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRN_WP3. */ 10504 #define BS_AIPS_PACRN_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP3. */ 10505 10506 /*! @brief Read current value of the AIPS_PACRN_WP3 field. */ 10507 #define BR_AIPS_PACRN_WP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP3))) 10508 10509 /*! @brief Format value for bitfield AIPS_PACRN_WP3. */ 10510 #define BF_AIPS_PACRN_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP3) & BM_AIPS_PACRN_WP3) 10511 10512 /*! @brief Set the WP3 field to a new value. */ 10513 #define BW_AIPS_PACRN_WP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP3), v)) 10514 /*@}*/ 10515 10516 /*! 10517 * @name Register AIPS_PACRN, field SP3[18] (RW) 10518 * 10519 * Determines whether the peripheral requires supervisor privilege level for 10520 * accesses. When this field is set, the master privilege level must indicate the 10521 * supervisor access attribute, and the MPRx[MPLn] control field for the master 10522 * must be set. If not, access terminates with an error response and no peripheral 10523 * access initiates. 10524 * 10525 * Values: 10526 * - 0 - This peripheral does not require supervisor privilege level for 10527 * accesses. 10528 * - 1 - This peripheral requires supervisor privilege level for accesses. 10529 */ 10530 /*@{*/ 10531 #define BP_AIPS_PACRN_SP3 (18U) /*!< Bit position for AIPS_PACRN_SP3. */ 10532 #define BM_AIPS_PACRN_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRN_SP3. */ 10533 #define BS_AIPS_PACRN_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP3. */ 10534 10535 /*! @brief Read current value of the AIPS_PACRN_SP3 field. */ 10536 #define BR_AIPS_PACRN_SP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP3))) 10537 10538 /*! @brief Format value for bitfield AIPS_PACRN_SP3. */ 10539 #define BF_AIPS_PACRN_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP3) & BM_AIPS_PACRN_SP3) 10540 10541 /*! @brief Set the SP3 field to a new value. */ 10542 #define BW_AIPS_PACRN_SP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP3), v)) 10543 /*@}*/ 10544 10545 /*! 10546 * @name Register AIPS_PACRN, field TP2[20] (RW) 10547 * 10548 * Determines whether the peripheral allows accesses from an untrusted master. 10549 * When this bit is set and an access is attempted by an untrusted master, the 10550 * access terminates with an error response and no peripheral access initiates. 10551 * 10552 * Values: 10553 * - 0 - Accesses from an untrusted master are allowed. 10554 * - 1 - Accesses from an untrusted master are not allowed. 10555 */ 10556 /*@{*/ 10557 #define BP_AIPS_PACRN_TP2 (20U) /*!< Bit position for AIPS_PACRN_TP2. */ 10558 #define BM_AIPS_PACRN_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRN_TP2. */ 10559 #define BS_AIPS_PACRN_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP2. */ 10560 10561 /*! @brief Read current value of the AIPS_PACRN_TP2 field. */ 10562 #define BR_AIPS_PACRN_TP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP2))) 10563 10564 /*! @brief Format value for bitfield AIPS_PACRN_TP2. */ 10565 #define BF_AIPS_PACRN_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP2) & BM_AIPS_PACRN_TP2) 10566 10567 /*! @brief Set the TP2 field to a new value. */ 10568 #define BW_AIPS_PACRN_TP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP2), v)) 10569 /*@}*/ 10570 10571 /*! 10572 * @name Register AIPS_PACRN, field WP2[21] (RW) 10573 * 10574 * Determines whether the peripheral allows write accesses. When this field is 10575 * set and a write access is attempted, access terminates with an error response 10576 * and no peripheral access initiates. 10577 * 10578 * Values: 10579 * - 0 - This peripheral allows write accesses. 10580 * - 1 - This peripheral is write protected. 10581 */ 10582 /*@{*/ 10583 #define BP_AIPS_PACRN_WP2 (21U) /*!< Bit position for AIPS_PACRN_WP2. */ 10584 #define BM_AIPS_PACRN_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRN_WP2. */ 10585 #define BS_AIPS_PACRN_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP2. */ 10586 10587 /*! @brief Read current value of the AIPS_PACRN_WP2 field. */ 10588 #define BR_AIPS_PACRN_WP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP2))) 10589 10590 /*! @brief Format value for bitfield AIPS_PACRN_WP2. */ 10591 #define BF_AIPS_PACRN_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP2) & BM_AIPS_PACRN_WP2) 10592 10593 /*! @brief Set the WP2 field to a new value. */ 10594 #define BW_AIPS_PACRN_WP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP2), v)) 10595 /*@}*/ 10596 10597 /*! 10598 * @name Register AIPS_PACRN, field SP2[22] (RW) 10599 * 10600 * Determines whether the peripheral requires supervisor privilege level for 10601 * access. When this bit is set, the master privilege level must indicate the 10602 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 10603 * set. If not, access terminates with an error response and no peripheral access 10604 * initiates. 10605 * 10606 * Values: 10607 * - 0 - This peripheral does not require supervisor privilege level for 10608 * accesses. 10609 * - 1 - This peripheral requires supervisor privilege level for accesses. 10610 */ 10611 /*@{*/ 10612 #define BP_AIPS_PACRN_SP2 (22U) /*!< Bit position for AIPS_PACRN_SP2. */ 10613 #define BM_AIPS_PACRN_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRN_SP2. */ 10614 #define BS_AIPS_PACRN_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP2. */ 10615 10616 /*! @brief Read current value of the AIPS_PACRN_SP2 field. */ 10617 #define BR_AIPS_PACRN_SP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP2))) 10618 10619 /*! @brief Format value for bitfield AIPS_PACRN_SP2. */ 10620 #define BF_AIPS_PACRN_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP2) & BM_AIPS_PACRN_SP2) 10621 10622 /*! @brief Set the SP2 field to a new value. */ 10623 #define BW_AIPS_PACRN_SP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP2), v)) 10624 /*@}*/ 10625 10626 /*! 10627 * @name Register AIPS_PACRN, field TP1[24] (RW) 10628 * 10629 * Determines whether the peripheral allows accesses from an untrusted master. 10630 * When this field is set and an access is attempted by an untrusted master, the 10631 * access terminates with an error response and no peripheral access initiates. 10632 * 10633 * Values: 10634 * - 0 - Accesses from an untrusted master are allowed. 10635 * - 1 - Accesses from an untrusted master are not allowed. 10636 */ 10637 /*@{*/ 10638 #define BP_AIPS_PACRN_TP1 (24U) /*!< Bit position for AIPS_PACRN_TP1. */ 10639 #define BM_AIPS_PACRN_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRN_TP1. */ 10640 #define BS_AIPS_PACRN_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP1. */ 10641 10642 /*! @brief Read current value of the AIPS_PACRN_TP1 field. */ 10643 #define BR_AIPS_PACRN_TP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP1))) 10644 10645 /*! @brief Format value for bitfield AIPS_PACRN_TP1. */ 10646 #define BF_AIPS_PACRN_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP1) & BM_AIPS_PACRN_TP1) 10647 10648 /*! @brief Set the TP1 field to a new value. */ 10649 #define BW_AIPS_PACRN_TP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP1), v)) 10650 /*@}*/ 10651 10652 /*! 10653 * @name Register AIPS_PACRN, field WP1[25] (RW) 10654 * 10655 * Determines whether the peripheral allows write accesses. When this field is 10656 * set and a write access is attempted, access terminates with an error response 10657 * and no peripheral access initiates. 10658 * 10659 * Values: 10660 * - 0 - This peripheral allows write accesses. 10661 * - 1 - This peripheral is write protected. 10662 */ 10663 /*@{*/ 10664 #define BP_AIPS_PACRN_WP1 (25U) /*!< Bit position for AIPS_PACRN_WP1. */ 10665 #define BM_AIPS_PACRN_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRN_WP1. */ 10666 #define BS_AIPS_PACRN_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP1. */ 10667 10668 /*! @brief Read current value of the AIPS_PACRN_WP1 field. */ 10669 #define BR_AIPS_PACRN_WP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP1))) 10670 10671 /*! @brief Format value for bitfield AIPS_PACRN_WP1. */ 10672 #define BF_AIPS_PACRN_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP1) & BM_AIPS_PACRN_WP1) 10673 10674 /*! @brief Set the WP1 field to a new value. */ 10675 #define BW_AIPS_PACRN_WP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP1), v)) 10676 /*@}*/ 10677 10678 /*! 10679 * @name Register AIPS_PACRN, field SP1[26] (RW) 10680 * 10681 * Determines whether the peripheral requires supervisor privilege level for 10682 * access. When this field is set, the master privilege level must indicate the 10683 * supervisor access attribute, and the MPRx[MPLn] control field for the master must 10684 * be set. If not, access terminates with an error response and no peripheral 10685 * access initiates. 10686 * 10687 * Values: 10688 * - 0 - This peripheral does not require supervisor privilege level for 10689 * accesses. 10690 * - 1 - This peripheral requires supervisor privilege level for accesses. 10691 */ 10692 /*@{*/ 10693 #define BP_AIPS_PACRN_SP1 (26U) /*!< Bit position for AIPS_PACRN_SP1. */ 10694 #define BM_AIPS_PACRN_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRN_SP1. */ 10695 #define BS_AIPS_PACRN_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP1. */ 10696 10697 /*! @brief Read current value of the AIPS_PACRN_SP1 field. */ 10698 #define BR_AIPS_PACRN_SP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP1))) 10699 10700 /*! @brief Format value for bitfield AIPS_PACRN_SP1. */ 10701 #define BF_AIPS_PACRN_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP1) & BM_AIPS_PACRN_SP1) 10702 10703 /*! @brief Set the SP1 field to a new value. */ 10704 #define BW_AIPS_PACRN_SP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP1), v)) 10705 /*@}*/ 10706 10707 /*! 10708 * @name Register AIPS_PACRN, field TP0[28] (RW) 10709 * 10710 * Determines whether the peripheral allows accesses from an untrusted master. 10711 * When this bit is set and an access is attempted by an untrusted master, the 10712 * access terminates with an error response and no peripheral access initiates. 10713 * 10714 * Values: 10715 * - 0 - Accesses from an untrusted master are allowed. 10716 * - 1 - Accesses from an untrusted master are not allowed. 10717 */ 10718 /*@{*/ 10719 #define BP_AIPS_PACRN_TP0 (28U) /*!< Bit position for AIPS_PACRN_TP0. */ 10720 #define BM_AIPS_PACRN_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRN_TP0. */ 10721 #define BS_AIPS_PACRN_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRN_TP0. */ 10722 10723 /*! @brief Read current value of the AIPS_PACRN_TP0 field. */ 10724 #define BR_AIPS_PACRN_TP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP0))) 10725 10726 /*! @brief Format value for bitfield AIPS_PACRN_TP0. */ 10727 #define BF_AIPS_PACRN_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_TP0) & BM_AIPS_PACRN_TP0) 10728 10729 /*! @brief Set the TP0 field to a new value. */ 10730 #define BW_AIPS_PACRN_TP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_TP0), v)) 10731 /*@}*/ 10732 10733 /*! 10734 * @name Register AIPS_PACRN, field WP0[29] (RW) 10735 * 10736 * Determines whether the peripheral allows write accesses. When this field is 10737 * set and a write access is attempted, access terminates with an error response 10738 * and no peripheral access initiates. 10739 * 10740 * Values: 10741 * - 0 - This peripheral allows write accesses. 10742 * - 1 - This peripheral is write protected. 10743 */ 10744 /*@{*/ 10745 #define BP_AIPS_PACRN_WP0 (29U) /*!< Bit position for AIPS_PACRN_WP0. */ 10746 #define BM_AIPS_PACRN_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRN_WP0. */ 10747 #define BS_AIPS_PACRN_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRN_WP0. */ 10748 10749 /*! @brief Read current value of the AIPS_PACRN_WP0 field. */ 10750 #define BR_AIPS_PACRN_WP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP0))) 10751 10752 /*! @brief Format value for bitfield AIPS_PACRN_WP0. */ 10753 #define BF_AIPS_PACRN_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_WP0) & BM_AIPS_PACRN_WP0) 10754 10755 /*! @brief Set the WP0 field to a new value. */ 10756 #define BW_AIPS_PACRN_WP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_WP0), v)) 10757 /*@}*/ 10758 10759 /*! 10760 * @name Register AIPS_PACRN, field SP0[30] (RW) 10761 * 10762 * Determines whether the peripheral requires supervisor privilege level for 10763 * accesses. When this field is set, the master privilege level must indicate the 10764 * supervisor access attribute, and the MPRx[MPLn] control field for the master 10765 * must be set. If not, access terminates with an error response and no peripheral 10766 * access initiates. 10767 * 10768 * Values: 10769 * - 0 - This peripheral does not require supervisor privilege level for 10770 * accesses. 10771 * - 1 - This peripheral requires supervisor privilege level for accesses. 10772 */ 10773 /*@{*/ 10774 #define BP_AIPS_PACRN_SP0 (30U) /*!< Bit position for AIPS_PACRN_SP0. */ 10775 #define BM_AIPS_PACRN_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRN_SP0. */ 10776 #define BS_AIPS_PACRN_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRN_SP0. */ 10777 10778 /*! @brief Read current value of the AIPS_PACRN_SP0 field. */ 10779 #define BR_AIPS_PACRN_SP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP0))) 10780 10781 /*! @brief Format value for bitfield AIPS_PACRN_SP0. */ 10782 #define BF_AIPS_PACRN_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRN_SP0) & BM_AIPS_PACRN_SP0) 10783 10784 /*! @brief Set the SP0 field to a new value. */ 10785 #define BW_AIPS_PACRN_SP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRN_ADDR(x), BP_AIPS_PACRN_SP0), v)) 10786 /*@}*/ 10787 10788 /******************************************************************************* 10789 * HW_AIPS_PACRO - Peripheral Access Control Register 10790 ******************************************************************************/ 10791 10792 /*! 10793 * @brief HW_AIPS_PACRO - Peripheral Access Control Register (RW) 10794 * 10795 * Reset value: 0x44444444U 10796 * 10797 * This section describes PACR registers E-P, which control peripheral slots 10798 * 32-127. See PACRPeripheral Access Control Register for the description of these 10799 * registers. 10800 */ 10801 typedef union _hw_aips_pacro 10802 { 10803 uint32_t U; 10804 struct _hw_aips_pacro_bitfields 10805 { 10806 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 10807 uint32_t WP7 : 1; /*!< [1] Write Protect */ 10808 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 10809 uint32_t RESERVED0 : 1; /*!< [3] */ 10810 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 10811 uint32_t WP6 : 1; /*!< [5] Write Protect */ 10812 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 10813 uint32_t RESERVED1 : 1; /*!< [7] */ 10814 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 10815 uint32_t WP5 : 1; /*!< [9] Write Protect */ 10816 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 10817 uint32_t RESERVED2 : 1; /*!< [11] */ 10818 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 10819 uint32_t WP4 : 1; /*!< [13] Write Protect */ 10820 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 10821 uint32_t RESERVED3 : 1; /*!< [15] */ 10822 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 10823 uint32_t WP3 : 1; /*!< [17] Write Protect */ 10824 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 10825 uint32_t RESERVED4 : 1; /*!< [19] */ 10826 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 10827 uint32_t WP2 : 1; /*!< [21] Write Protect */ 10828 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 10829 uint32_t RESERVED5 : 1; /*!< [23] */ 10830 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 10831 uint32_t WP1 : 1; /*!< [25] Write Protect */ 10832 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 10833 uint32_t RESERVED6 : 1; /*!< [27] */ 10834 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 10835 uint32_t WP0 : 1; /*!< [29] Write Protect */ 10836 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 10837 uint32_t RESERVED7 : 1; /*!< [31] */ 10838 } B; 10839 } hw_aips_pacro_t; 10840 10841 /*! 10842 * @name Constants and macros for entire AIPS_PACRO register 10843 */ 10844 /*@{*/ 10845 #define HW_AIPS_PACRO_ADDR(x) ((x) + 0x68U) 10846 10847 #define HW_AIPS_PACRO(x) (*(__IO hw_aips_pacro_t *) HW_AIPS_PACRO_ADDR(x)) 10848 #define HW_AIPS_PACRO_RD(x) (ADDRESS_READ(hw_aips_pacro_t, HW_AIPS_PACRO_ADDR(x))) 10849 #define HW_AIPS_PACRO_WR(x, v) (ADDRESS_WRITE(hw_aips_pacro_t, HW_AIPS_PACRO_ADDR(x), v)) 10850 #define HW_AIPS_PACRO_SET(x, v) (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) | (v))) 10851 #define HW_AIPS_PACRO_CLR(x, v) (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) & ~(v))) 10852 #define HW_AIPS_PACRO_TOG(x, v) (HW_AIPS_PACRO_WR(x, HW_AIPS_PACRO_RD(x) ^ (v))) 10853 /*@}*/ 10854 10855 /* 10856 * Constants & macros for individual AIPS_PACRO bitfields 10857 */ 10858 10859 /*! 10860 * @name Register AIPS_PACRO, field TP7[0] (RW) 10861 * 10862 * Determines whether the peripheral allows accesses from an untrusted master. 10863 * When this field is set and an access is attempted by an untrusted master, the 10864 * access terminates with an error response and no peripheral access initiates. 10865 * 10866 * Values: 10867 * - 0 - Accesses from an untrusted master are allowed. 10868 * - 1 - Accesses from an untrusted master are not allowed. 10869 */ 10870 /*@{*/ 10871 #define BP_AIPS_PACRO_TP7 (0U) /*!< Bit position for AIPS_PACRO_TP7. */ 10872 #define BM_AIPS_PACRO_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRO_TP7. */ 10873 #define BS_AIPS_PACRO_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP7. */ 10874 10875 /*! @brief Read current value of the AIPS_PACRO_TP7 field. */ 10876 #define BR_AIPS_PACRO_TP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP7))) 10877 10878 /*! @brief Format value for bitfield AIPS_PACRO_TP7. */ 10879 #define BF_AIPS_PACRO_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP7) & BM_AIPS_PACRO_TP7) 10880 10881 /*! @brief Set the TP7 field to a new value. */ 10882 #define BW_AIPS_PACRO_TP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP7), v)) 10883 /*@}*/ 10884 10885 /*! 10886 * @name Register AIPS_PACRO, field WP7[1] (RW) 10887 * 10888 * Determines whether the peripheral allows write accesses. When this field is 10889 * set and a write access is attempted, access terminates with an error response 10890 * and no peripheral access initiates. 10891 * 10892 * Values: 10893 * - 0 - This peripheral allows write accesses. 10894 * - 1 - This peripheral is write protected. 10895 */ 10896 /*@{*/ 10897 #define BP_AIPS_PACRO_WP7 (1U) /*!< Bit position for AIPS_PACRO_WP7. */ 10898 #define BM_AIPS_PACRO_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRO_WP7. */ 10899 #define BS_AIPS_PACRO_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP7. */ 10900 10901 /*! @brief Read current value of the AIPS_PACRO_WP7 field. */ 10902 #define BR_AIPS_PACRO_WP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP7))) 10903 10904 /*! @brief Format value for bitfield AIPS_PACRO_WP7. */ 10905 #define BF_AIPS_PACRO_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP7) & BM_AIPS_PACRO_WP7) 10906 10907 /*! @brief Set the WP7 field to a new value. */ 10908 #define BW_AIPS_PACRO_WP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP7), v)) 10909 /*@}*/ 10910 10911 /*! 10912 * @name Register AIPS_PACRO, field SP7[2] (RW) 10913 * 10914 * Determines whether the peripheral requires supervisor privilege level for 10915 * accesses. When this field is set, the master privilege level must indicate the 10916 * supervisor access attribute, and the MPRx[MPLn] control field for the master 10917 * must be set. If not, access terminates with an error response and no peripheral 10918 * access initiates. 10919 * 10920 * Values: 10921 * - 0 - This peripheral does not require supervisor privilege level for 10922 * accesses. 10923 * - 1 - This peripheral requires supervisor privilege level for accesses. 10924 */ 10925 /*@{*/ 10926 #define BP_AIPS_PACRO_SP7 (2U) /*!< Bit position for AIPS_PACRO_SP7. */ 10927 #define BM_AIPS_PACRO_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRO_SP7. */ 10928 #define BS_AIPS_PACRO_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP7. */ 10929 10930 /*! @brief Read current value of the AIPS_PACRO_SP7 field. */ 10931 #define BR_AIPS_PACRO_SP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP7))) 10932 10933 /*! @brief Format value for bitfield AIPS_PACRO_SP7. */ 10934 #define BF_AIPS_PACRO_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP7) & BM_AIPS_PACRO_SP7) 10935 10936 /*! @brief Set the SP7 field to a new value. */ 10937 #define BW_AIPS_PACRO_SP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP7), v)) 10938 /*@}*/ 10939 10940 /*! 10941 * @name Register AIPS_PACRO, field TP6[4] (RW) 10942 * 10943 * Determines whether the peripheral allows accesses from an untrusted master. 10944 * When this field is set and an access is attempted by an untrusted master, the 10945 * access terminates with an error response and no peripheral access initiates. 10946 * 10947 * Values: 10948 * - 0 - Accesses from an untrusted master are allowed. 10949 * - 1 - Accesses from an untrusted master are not allowed. 10950 */ 10951 /*@{*/ 10952 #define BP_AIPS_PACRO_TP6 (4U) /*!< Bit position for AIPS_PACRO_TP6. */ 10953 #define BM_AIPS_PACRO_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRO_TP6. */ 10954 #define BS_AIPS_PACRO_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP6. */ 10955 10956 /*! @brief Read current value of the AIPS_PACRO_TP6 field. */ 10957 #define BR_AIPS_PACRO_TP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP6))) 10958 10959 /*! @brief Format value for bitfield AIPS_PACRO_TP6. */ 10960 #define BF_AIPS_PACRO_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP6) & BM_AIPS_PACRO_TP6) 10961 10962 /*! @brief Set the TP6 field to a new value. */ 10963 #define BW_AIPS_PACRO_TP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP6), v)) 10964 /*@}*/ 10965 10966 /*! 10967 * @name Register AIPS_PACRO, field WP6[5] (RW) 10968 * 10969 * Determines whether the peripheral allows write accesses. When this field is 10970 * set and a write access is attempted, access terminates with an error response 10971 * and no peripheral access initiates. 10972 * 10973 * Values: 10974 * - 0 - This peripheral allows write accesses. 10975 * - 1 - This peripheral is write protected. 10976 */ 10977 /*@{*/ 10978 #define BP_AIPS_PACRO_WP6 (5U) /*!< Bit position for AIPS_PACRO_WP6. */ 10979 #define BM_AIPS_PACRO_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRO_WP6. */ 10980 #define BS_AIPS_PACRO_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP6. */ 10981 10982 /*! @brief Read current value of the AIPS_PACRO_WP6 field. */ 10983 #define BR_AIPS_PACRO_WP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP6))) 10984 10985 /*! @brief Format value for bitfield AIPS_PACRO_WP6. */ 10986 #define BF_AIPS_PACRO_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP6) & BM_AIPS_PACRO_WP6) 10987 10988 /*! @brief Set the WP6 field to a new value. */ 10989 #define BW_AIPS_PACRO_WP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP6), v)) 10990 /*@}*/ 10991 10992 /*! 10993 * @name Register AIPS_PACRO, field SP6[6] (RW) 10994 * 10995 * Determines whether the peripheral requires supervisor privilege level for 10996 * accesses. When this field is set, the master privilege level must indicate the 10997 * supervisor access attribute, and the MPRx[MPLn] control field for the master 10998 * must be set. If not, access terminates with an error response and no peripheral 10999 * access initiates. 11000 * 11001 * Values: 11002 * - 0 - This peripheral does not require supervisor privilege level for 11003 * accesses. 11004 * - 1 - This peripheral requires supervisor privilege level for accesses. 11005 */ 11006 /*@{*/ 11007 #define BP_AIPS_PACRO_SP6 (6U) /*!< Bit position for AIPS_PACRO_SP6. */ 11008 #define BM_AIPS_PACRO_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRO_SP6. */ 11009 #define BS_AIPS_PACRO_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP6. */ 11010 11011 /*! @brief Read current value of the AIPS_PACRO_SP6 field. */ 11012 #define BR_AIPS_PACRO_SP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP6))) 11013 11014 /*! @brief Format value for bitfield AIPS_PACRO_SP6. */ 11015 #define BF_AIPS_PACRO_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP6) & BM_AIPS_PACRO_SP6) 11016 11017 /*! @brief Set the SP6 field to a new value. */ 11018 #define BW_AIPS_PACRO_SP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP6), v)) 11019 /*@}*/ 11020 11021 /*! 11022 * @name Register AIPS_PACRO, field TP5[8] (RW) 11023 * 11024 * Determines whether the peripheral allows accesses from an untrusted master. 11025 * When this field is set and an access is attempted by an untrusted master, the 11026 * access terminates with an error response and no peripheral access initiates. 11027 * 11028 * Values: 11029 * - 0 - Accesses from an untrusted master are allowed. 11030 * - 1 - Accesses from an untrusted master are not allowed. 11031 */ 11032 /*@{*/ 11033 #define BP_AIPS_PACRO_TP5 (8U) /*!< Bit position for AIPS_PACRO_TP5. */ 11034 #define BM_AIPS_PACRO_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRO_TP5. */ 11035 #define BS_AIPS_PACRO_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP5. */ 11036 11037 /*! @brief Read current value of the AIPS_PACRO_TP5 field. */ 11038 #define BR_AIPS_PACRO_TP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP5))) 11039 11040 /*! @brief Format value for bitfield AIPS_PACRO_TP5. */ 11041 #define BF_AIPS_PACRO_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP5) & BM_AIPS_PACRO_TP5) 11042 11043 /*! @brief Set the TP5 field to a new value. */ 11044 #define BW_AIPS_PACRO_TP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP5), v)) 11045 /*@}*/ 11046 11047 /*! 11048 * @name Register AIPS_PACRO, field WP5[9] (RW) 11049 * 11050 * Determines whether the peripheral allows write accesses. When this field is 11051 * set and a write access is attempted, access terminates with an error response 11052 * and no peripheral access initiates. 11053 * 11054 * Values: 11055 * - 0 - This peripheral allows write accesses. 11056 * - 1 - This peripheral is write protected. 11057 */ 11058 /*@{*/ 11059 #define BP_AIPS_PACRO_WP5 (9U) /*!< Bit position for AIPS_PACRO_WP5. */ 11060 #define BM_AIPS_PACRO_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRO_WP5. */ 11061 #define BS_AIPS_PACRO_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP5. */ 11062 11063 /*! @brief Read current value of the AIPS_PACRO_WP5 field. */ 11064 #define BR_AIPS_PACRO_WP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP5))) 11065 11066 /*! @brief Format value for bitfield AIPS_PACRO_WP5. */ 11067 #define BF_AIPS_PACRO_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP5) & BM_AIPS_PACRO_WP5) 11068 11069 /*! @brief Set the WP5 field to a new value. */ 11070 #define BW_AIPS_PACRO_WP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP5), v)) 11071 /*@}*/ 11072 11073 /*! 11074 * @name Register AIPS_PACRO, field SP5[10] (RW) 11075 * 11076 * Determines whether the peripheral requires supervisor privilege level for 11077 * accesses. When this field is set, the master privilege level must indicate the 11078 * supervisor access attribute, and the MPRx[MPLn] control field for the master 11079 * must be set. If not, access terminates with an error response and no peripheral 11080 * access initiates. 11081 * 11082 * Values: 11083 * - 0 - This peripheral does not require supervisor privilege level for 11084 * accesses. 11085 * - 1 - This peripheral requires supervisor privilege level for accesses. 11086 */ 11087 /*@{*/ 11088 #define BP_AIPS_PACRO_SP5 (10U) /*!< Bit position for AIPS_PACRO_SP5. */ 11089 #define BM_AIPS_PACRO_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRO_SP5. */ 11090 #define BS_AIPS_PACRO_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP5. */ 11091 11092 /*! @brief Read current value of the AIPS_PACRO_SP5 field. */ 11093 #define BR_AIPS_PACRO_SP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP5))) 11094 11095 /*! @brief Format value for bitfield AIPS_PACRO_SP5. */ 11096 #define BF_AIPS_PACRO_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP5) & BM_AIPS_PACRO_SP5) 11097 11098 /*! @brief Set the SP5 field to a new value. */ 11099 #define BW_AIPS_PACRO_SP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP5), v)) 11100 /*@}*/ 11101 11102 /*! 11103 * @name Register AIPS_PACRO, field TP4[12] (RW) 11104 * 11105 * Determines whether the peripheral allows accesses from an untrusted master. 11106 * When this bit is set and an access is attempted by an untrusted master, the 11107 * access terminates with an error response and no peripheral access initiates. 11108 * 11109 * Values: 11110 * - 0 - Accesses from an untrusted master are allowed. 11111 * - 1 - Accesses from an untrusted master are not allowed. 11112 */ 11113 /*@{*/ 11114 #define BP_AIPS_PACRO_TP4 (12U) /*!< Bit position for AIPS_PACRO_TP4. */ 11115 #define BM_AIPS_PACRO_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRO_TP4. */ 11116 #define BS_AIPS_PACRO_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP4. */ 11117 11118 /*! @brief Read current value of the AIPS_PACRO_TP4 field. */ 11119 #define BR_AIPS_PACRO_TP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP4))) 11120 11121 /*! @brief Format value for bitfield AIPS_PACRO_TP4. */ 11122 #define BF_AIPS_PACRO_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP4) & BM_AIPS_PACRO_TP4) 11123 11124 /*! @brief Set the TP4 field to a new value. */ 11125 #define BW_AIPS_PACRO_TP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP4), v)) 11126 /*@}*/ 11127 11128 /*! 11129 * @name Register AIPS_PACRO, field WP4[13] (RW) 11130 * 11131 * Determines whether the peripheral allows write accesses. When this field is 11132 * set and a write access is attempted, access terminates with an error response 11133 * and no peripheral access initiates. 11134 * 11135 * Values: 11136 * - 0 - This peripheral allows write accesses. 11137 * - 1 - This peripheral is write protected. 11138 */ 11139 /*@{*/ 11140 #define BP_AIPS_PACRO_WP4 (13U) /*!< Bit position for AIPS_PACRO_WP4. */ 11141 #define BM_AIPS_PACRO_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRO_WP4. */ 11142 #define BS_AIPS_PACRO_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP4. */ 11143 11144 /*! @brief Read current value of the AIPS_PACRO_WP4 field. */ 11145 #define BR_AIPS_PACRO_WP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP4))) 11146 11147 /*! @brief Format value for bitfield AIPS_PACRO_WP4. */ 11148 #define BF_AIPS_PACRO_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP4) & BM_AIPS_PACRO_WP4) 11149 11150 /*! @brief Set the WP4 field to a new value. */ 11151 #define BW_AIPS_PACRO_WP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP4), v)) 11152 /*@}*/ 11153 11154 /*! 11155 * @name Register AIPS_PACRO, field SP4[14] (RW) 11156 * 11157 * Determines whether the peripheral requires supervisor privilege level for 11158 * access. When this bit is set, the master privilege level must indicate the 11159 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 11160 * set. If not, access terminates with an error response and no peripheral access 11161 * initiates. 11162 * 11163 * Values: 11164 * - 0 - This peripheral does not require supervisor privilege level for 11165 * accesses. 11166 * - 1 - This peripheral requires supervisor privilege level for accesses. 11167 */ 11168 /*@{*/ 11169 #define BP_AIPS_PACRO_SP4 (14U) /*!< Bit position for AIPS_PACRO_SP4. */ 11170 #define BM_AIPS_PACRO_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRO_SP4. */ 11171 #define BS_AIPS_PACRO_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP4. */ 11172 11173 /*! @brief Read current value of the AIPS_PACRO_SP4 field. */ 11174 #define BR_AIPS_PACRO_SP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP4))) 11175 11176 /*! @brief Format value for bitfield AIPS_PACRO_SP4. */ 11177 #define BF_AIPS_PACRO_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP4) & BM_AIPS_PACRO_SP4) 11178 11179 /*! @brief Set the SP4 field to a new value. */ 11180 #define BW_AIPS_PACRO_SP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP4), v)) 11181 /*@}*/ 11182 11183 /*! 11184 * @name Register AIPS_PACRO, field TP3[16] (RW) 11185 * 11186 * Determines whether the peripheral allows accesses from an untrusted master. 11187 * When this field is set and an access is attempted by an untrusted master, the 11188 * access terminates with an error response and no peripheral access initiates. 11189 * 11190 * Values: 11191 * - 0 - Accesses from an untrusted master are allowed. 11192 * - 1 - Accesses from an untrusted master are not allowed. 11193 */ 11194 /*@{*/ 11195 #define BP_AIPS_PACRO_TP3 (16U) /*!< Bit position for AIPS_PACRO_TP3. */ 11196 #define BM_AIPS_PACRO_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRO_TP3. */ 11197 #define BS_AIPS_PACRO_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP3. */ 11198 11199 /*! @brief Read current value of the AIPS_PACRO_TP3 field. */ 11200 #define BR_AIPS_PACRO_TP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP3))) 11201 11202 /*! @brief Format value for bitfield AIPS_PACRO_TP3. */ 11203 #define BF_AIPS_PACRO_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP3) & BM_AIPS_PACRO_TP3) 11204 11205 /*! @brief Set the TP3 field to a new value. */ 11206 #define BW_AIPS_PACRO_TP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP3), v)) 11207 /*@}*/ 11208 11209 /*! 11210 * @name Register AIPS_PACRO, field WP3[17] (RW) 11211 * 11212 * Determines whether the peripheral allows write accesss. When this bit is set 11213 * and a write access is attempted, access terminates with an error response and 11214 * no peripheral access initiates. 11215 * 11216 * Values: 11217 * - 0 - This peripheral allows write accesses. 11218 * - 1 - This peripheral is write protected. 11219 */ 11220 /*@{*/ 11221 #define BP_AIPS_PACRO_WP3 (17U) /*!< Bit position for AIPS_PACRO_WP3. */ 11222 #define BM_AIPS_PACRO_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRO_WP3. */ 11223 #define BS_AIPS_PACRO_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP3. */ 11224 11225 /*! @brief Read current value of the AIPS_PACRO_WP3 field. */ 11226 #define BR_AIPS_PACRO_WP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP3))) 11227 11228 /*! @brief Format value for bitfield AIPS_PACRO_WP3. */ 11229 #define BF_AIPS_PACRO_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP3) & BM_AIPS_PACRO_WP3) 11230 11231 /*! @brief Set the WP3 field to a new value. */ 11232 #define BW_AIPS_PACRO_WP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP3), v)) 11233 /*@}*/ 11234 11235 /*! 11236 * @name Register AIPS_PACRO, field SP3[18] (RW) 11237 * 11238 * Determines whether the peripheral requires supervisor privilege level for 11239 * accesses. When this field is set, the master privilege level must indicate the 11240 * supervisor access attribute, and the MPRx[MPLn] control field for the master 11241 * must be set. If not, access terminates with an error response and no peripheral 11242 * access initiates. 11243 * 11244 * Values: 11245 * - 0 - This peripheral does not require supervisor privilege level for 11246 * accesses. 11247 * - 1 - This peripheral requires supervisor privilege level for accesses. 11248 */ 11249 /*@{*/ 11250 #define BP_AIPS_PACRO_SP3 (18U) /*!< Bit position for AIPS_PACRO_SP3. */ 11251 #define BM_AIPS_PACRO_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRO_SP3. */ 11252 #define BS_AIPS_PACRO_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP3. */ 11253 11254 /*! @brief Read current value of the AIPS_PACRO_SP3 field. */ 11255 #define BR_AIPS_PACRO_SP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP3))) 11256 11257 /*! @brief Format value for bitfield AIPS_PACRO_SP3. */ 11258 #define BF_AIPS_PACRO_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP3) & BM_AIPS_PACRO_SP3) 11259 11260 /*! @brief Set the SP3 field to a new value. */ 11261 #define BW_AIPS_PACRO_SP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP3), v)) 11262 /*@}*/ 11263 11264 /*! 11265 * @name Register AIPS_PACRO, field TP2[20] (RW) 11266 * 11267 * Determines whether the peripheral allows accesses from an untrusted master. 11268 * When this bit is set and an access is attempted by an untrusted master, the 11269 * access terminates with an error response and no peripheral access initiates. 11270 * 11271 * Values: 11272 * - 0 - Accesses from an untrusted master are allowed. 11273 * - 1 - Accesses from an untrusted master are not allowed. 11274 */ 11275 /*@{*/ 11276 #define BP_AIPS_PACRO_TP2 (20U) /*!< Bit position for AIPS_PACRO_TP2. */ 11277 #define BM_AIPS_PACRO_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRO_TP2. */ 11278 #define BS_AIPS_PACRO_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP2. */ 11279 11280 /*! @brief Read current value of the AIPS_PACRO_TP2 field. */ 11281 #define BR_AIPS_PACRO_TP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP2))) 11282 11283 /*! @brief Format value for bitfield AIPS_PACRO_TP2. */ 11284 #define BF_AIPS_PACRO_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP2) & BM_AIPS_PACRO_TP2) 11285 11286 /*! @brief Set the TP2 field to a new value. */ 11287 #define BW_AIPS_PACRO_TP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP2), v)) 11288 /*@}*/ 11289 11290 /*! 11291 * @name Register AIPS_PACRO, field WP2[21] (RW) 11292 * 11293 * Determines whether the peripheral allows write accesses. When this field is 11294 * set and a write access is attempted, access terminates with an error response 11295 * and no peripheral access initiates. 11296 * 11297 * Values: 11298 * - 0 - This peripheral allows write accesses. 11299 * - 1 - This peripheral is write protected. 11300 */ 11301 /*@{*/ 11302 #define BP_AIPS_PACRO_WP2 (21U) /*!< Bit position for AIPS_PACRO_WP2. */ 11303 #define BM_AIPS_PACRO_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRO_WP2. */ 11304 #define BS_AIPS_PACRO_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP2. */ 11305 11306 /*! @brief Read current value of the AIPS_PACRO_WP2 field. */ 11307 #define BR_AIPS_PACRO_WP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP2))) 11308 11309 /*! @brief Format value for bitfield AIPS_PACRO_WP2. */ 11310 #define BF_AIPS_PACRO_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP2) & BM_AIPS_PACRO_WP2) 11311 11312 /*! @brief Set the WP2 field to a new value. */ 11313 #define BW_AIPS_PACRO_WP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP2), v)) 11314 /*@}*/ 11315 11316 /*! 11317 * @name Register AIPS_PACRO, field SP2[22] (RW) 11318 * 11319 * Determines whether the peripheral requires supervisor privilege level for 11320 * access. When this bit is set, the master privilege level must indicate the 11321 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 11322 * set. If not, access terminates with an error response and no peripheral access 11323 * initiates. 11324 * 11325 * Values: 11326 * - 0 - This peripheral does not require supervisor privilege level for 11327 * accesses. 11328 * - 1 - This peripheral requires supervisor privilege level for accesses. 11329 */ 11330 /*@{*/ 11331 #define BP_AIPS_PACRO_SP2 (22U) /*!< Bit position for AIPS_PACRO_SP2. */ 11332 #define BM_AIPS_PACRO_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRO_SP2. */ 11333 #define BS_AIPS_PACRO_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP2. */ 11334 11335 /*! @brief Read current value of the AIPS_PACRO_SP2 field. */ 11336 #define BR_AIPS_PACRO_SP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP2))) 11337 11338 /*! @brief Format value for bitfield AIPS_PACRO_SP2. */ 11339 #define BF_AIPS_PACRO_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP2) & BM_AIPS_PACRO_SP2) 11340 11341 /*! @brief Set the SP2 field to a new value. */ 11342 #define BW_AIPS_PACRO_SP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP2), v)) 11343 /*@}*/ 11344 11345 /*! 11346 * @name Register AIPS_PACRO, field TP1[24] (RW) 11347 * 11348 * Determines whether the peripheral allows accesses from an untrusted master. 11349 * When this field is set and an access is attempted by an untrusted master, the 11350 * access terminates with an error response and no peripheral access initiates. 11351 * 11352 * Values: 11353 * - 0 - Accesses from an untrusted master are allowed. 11354 * - 1 - Accesses from an untrusted master are not allowed. 11355 */ 11356 /*@{*/ 11357 #define BP_AIPS_PACRO_TP1 (24U) /*!< Bit position for AIPS_PACRO_TP1. */ 11358 #define BM_AIPS_PACRO_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRO_TP1. */ 11359 #define BS_AIPS_PACRO_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP1. */ 11360 11361 /*! @brief Read current value of the AIPS_PACRO_TP1 field. */ 11362 #define BR_AIPS_PACRO_TP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP1))) 11363 11364 /*! @brief Format value for bitfield AIPS_PACRO_TP1. */ 11365 #define BF_AIPS_PACRO_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP1) & BM_AIPS_PACRO_TP1) 11366 11367 /*! @brief Set the TP1 field to a new value. */ 11368 #define BW_AIPS_PACRO_TP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP1), v)) 11369 /*@}*/ 11370 11371 /*! 11372 * @name Register AIPS_PACRO, field WP1[25] (RW) 11373 * 11374 * Determines whether the peripheral allows write accesses. When this field is 11375 * set and a write access is attempted, access terminates with an error response 11376 * and no peripheral access initiates. 11377 * 11378 * Values: 11379 * - 0 - This peripheral allows write accesses. 11380 * - 1 - This peripheral is write protected. 11381 */ 11382 /*@{*/ 11383 #define BP_AIPS_PACRO_WP1 (25U) /*!< Bit position for AIPS_PACRO_WP1. */ 11384 #define BM_AIPS_PACRO_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRO_WP1. */ 11385 #define BS_AIPS_PACRO_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP1. */ 11386 11387 /*! @brief Read current value of the AIPS_PACRO_WP1 field. */ 11388 #define BR_AIPS_PACRO_WP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP1))) 11389 11390 /*! @brief Format value for bitfield AIPS_PACRO_WP1. */ 11391 #define BF_AIPS_PACRO_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP1) & BM_AIPS_PACRO_WP1) 11392 11393 /*! @brief Set the WP1 field to a new value. */ 11394 #define BW_AIPS_PACRO_WP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP1), v)) 11395 /*@}*/ 11396 11397 /*! 11398 * @name Register AIPS_PACRO, field SP1[26] (RW) 11399 * 11400 * Determines whether the peripheral requires supervisor privilege level for 11401 * access. When this field is set, the master privilege level must indicate the 11402 * supervisor access attribute, and the MPRx[MPLn] control field for the master must 11403 * be set. If not, access terminates with an error response and no peripheral 11404 * access initiates. 11405 * 11406 * Values: 11407 * - 0 - This peripheral does not require supervisor privilege level for 11408 * accesses. 11409 * - 1 - This peripheral requires supervisor privilege level for accesses. 11410 */ 11411 /*@{*/ 11412 #define BP_AIPS_PACRO_SP1 (26U) /*!< Bit position for AIPS_PACRO_SP1. */ 11413 #define BM_AIPS_PACRO_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRO_SP1. */ 11414 #define BS_AIPS_PACRO_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP1. */ 11415 11416 /*! @brief Read current value of the AIPS_PACRO_SP1 field. */ 11417 #define BR_AIPS_PACRO_SP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP1))) 11418 11419 /*! @brief Format value for bitfield AIPS_PACRO_SP1. */ 11420 #define BF_AIPS_PACRO_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP1) & BM_AIPS_PACRO_SP1) 11421 11422 /*! @brief Set the SP1 field to a new value. */ 11423 #define BW_AIPS_PACRO_SP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP1), v)) 11424 /*@}*/ 11425 11426 /*! 11427 * @name Register AIPS_PACRO, field TP0[28] (RW) 11428 * 11429 * Determines whether the peripheral allows accesses from an untrusted master. 11430 * When this bit is set and an access is attempted by an untrusted master, the 11431 * access terminates with an error response and no peripheral access initiates. 11432 * 11433 * Values: 11434 * - 0 - Accesses from an untrusted master are allowed. 11435 * - 1 - Accesses from an untrusted master are not allowed. 11436 */ 11437 /*@{*/ 11438 #define BP_AIPS_PACRO_TP0 (28U) /*!< Bit position for AIPS_PACRO_TP0. */ 11439 #define BM_AIPS_PACRO_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRO_TP0. */ 11440 #define BS_AIPS_PACRO_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRO_TP0. */ 11441 11442 /*! @brief Read current value of the AIPS_PACRO_TP0 field. */ 11443 #define BR_AIPS_PACRO_TP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP0))) 11444 11445 /*! @brief Format value for bitfield AIPS_PACRO_TP0. */ 11446 #define BF_AIPS_PACRO_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_TP0) & BM_AIPS_PACRO_TP0) 11447 11448 /*! @brief Set the TP0 field to a new value. */ 11449 #define BW_AIPS_PACRO_TP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_TP0), v)) 11450 /*@}*/ 11451 11452 /*! 11453 * @name Register AIPS_PACRO, field WP0[29] (RW) 11454 * 11455 * Determines whether the peripheral allows write accesses. When this field is 11456 * set and a write access is attempted, access terminates with an error response 11457 * and no peripheral access initiates. 11458 * 11459 * Values: 11460 * - 0 - This peripheral allows write accesses. 11461 * - 1 - This peripheral is write protected. 11462 */ 11463 /*@{*/ 11464 #define BP_AIPS_PACRO_WP0 (29U) /*!< Bit position for AIPS_PACRO_WP0. */ 11465 #define BM_AIPS_PACRO_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRO_WP0. */ 11466 #define BS_AIPS_PACRO_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRO_WP0. */ 11467 11468 /*! @brief Read current value of the AIPS_PACRO_WP0 field. */ 11469 #define BR_AIPS_PACRO_WP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP0))) 11470 11471 /*! @brief Format value for bitfield AIPS_PACRO_WP0. */ 11472 #define BF_AIPS_PACRO_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_WP0) & BM_AIPS_PACRO_WP0) 11473 11474 /*! @brief Set the WP0 field to a new value. */ 11475 #define BW_AIPS_PACRO_WP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_WP0), v)) 11476 /*@}*/ 11477 11478 /*! 11479 * @name Register AIPS_PACRO, field SP0[30] (RW) 11480 * 11481 * Determines whether the peripheral requires supervisor privilege level for 11482 * accesses. When this field is set, the master privilege level must indicate the 11483 * supervisor access attribute, and the MPRx[MPLn] control field for the master 11484 * must be set. If not, access terminates with an error response and no peripheral 11485 * access initiates. 11486 * 11487 * Values: 11488 * - 0 - This peripheral does not require supervisor privilege level for 11489 * accesses. 11490 * - 1 - This peripheral requires supervisor privilege level for accesses. 11491 */ 11492 /*@{*/ 11493 #define BP_AIPS_PACRO_SP0 (30U) /*!< Bit position for AIPS_PACRO_SP0. */ 11494 #define BM_AIPS_PACRO_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRO_SP0. */ 11495 #define BS_AIPS_PACRO_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRO_SP0. */ 11496 11497 /*! @brief Read current value of the AIPS_PACRO_SP0 field. */ 11498 #define BR_AIPS_PACRO_SP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP0))) 11499 11500 /*! @brief Format value for bitfield AIPS_PACRO_SP0. */ 11501 #define BF_AIPS_PACRO_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRO_SP0) & BM_AIPS_PACRO_SP0) 11502 11503 /*! @brief Set the SP0 field to a new value. */ 11504 #define BW_AIPS_PACRO_SP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRO_ADDR(x), BP_AIPS_PACRO_SP0), v)) 11505 /*@}*/ 11506 11507 /******************************************************************************* 11508 * HW_AIPS_PACRP - Peripheral Access Control Register 11509 ******************************************************************************/ 11510 11511 /*! 11512 * @brief HW_AIPS_PACRP - Peripheral Access Control Register (RW) 11513 * 11514 * Reset value: 0x44444444U 11515 * 11516 * This section describes PACR registers E-P, which control peripheral slots 11517 * 32-127. See PACRPeripheral Access Control Register for the description of these 11518 * registers. 11519 */ 11520 typedef union _hw_aips_pacrp 11521 { 11522 uint32_t U; 11523 struct _hw_aips_pacrp_bitfields 11524 { 11525 uint32_t TP7 : 1; /*!< [0] Trusted Protect */ 11526 uint32_t WP7 : 1; /*!< [1] Write Protect */ 11527 uint32_t SP7 : 1; /*!< [2] Supervisor Protect */ 11528 uint32_t RESERVED0 : 1; /*!< [3] */ 11529 uint32_t TP6 : 1; /*!< [4] Trusted Protect */ 11530 uint32_t WP6 : 1; /*!< [5] Write Protect */ 11531 uint32_t SP6 : 1; /*!< [6] Supervisor Protect */ 11532 uint32_t RESERVED1 : 1; /*!< [7] */ 11533 uint32_t TP5 : 1; /*!< [8] Trusted Protect */ 11534 uint32_t WP5 : 1; /*!< [9] Write Protect */ 11535 uint32_t SP5 : 1; /*!< [10] Supervisor Protect */ 11536 uint32_t RESERVED2 : 1; /*!< [11] */ 11537 uint32_t TP4 : 1; /*!< [12] Trusted Protect */ 11538 uint32_t WP4 : 1; /*!< [13] Write Protect */ 11539 uint32_t SP4 : 1; /*!< [14] Supervisor Protect */ 11540 uint32_t RESERVED3 : 1; /*!< [15] */ 11541 uint32_t TP3 : 1; /*!< [16] Trusted Protect */ 11542 uint32_t WP3 : 1; /*!< [17] Write Protect */ 11543 uint32_t SP3 : 1; /*!< [18] Supervisor Protect */ 11544 uint32_t RESERVED4 : 1; /*!< [19] */ 11545 uint32_t TP2 : 1; /*!< [20] Trusted Protect */ 11546 uint32_t WP2 : 1; /*!< [21] Write Protect */ 11547 uint32_t SP2 : 1; /*!< [22] Supervisor Protect */ 11548 uint32_t RESERVED5 : 1; /*!< [23] */ 11549 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 11550 uint32_t WP1 : 1; /*!< [25] Write Protect */ 11551 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 11552 uint32_t RESERVED6 : 1; /*!< [27] */ 11553 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 11554 uint32_t WP0 : 1; /*!< [29] Write Protect */ 11555 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 11556 uint32_t RESERVED7 : 1; /*!< [31] */ 11557 } B; 11558 } hw_aips_pacrp_t; 11559 11560 /*! 11561 * @name Constants and macros for entire AIPS_PACRP register 11562 */ 11563 /*@{*/ 11564 #define HW_AIPS_PACRP_ADDR(x) ((x) + 0x6CU) 11565 11566 #define HW_AIPS_PACRP(x) (*(__IO hw_aips_pacrp_t *) HW_AIPS_PACRP_ADDR(x)) 11567 #define HW_AIPS_PACRP_RD(x) (ADDRESS_READ(hw_aips_pacrp_t, HW_AIPS_PACRP_ADDR(x))) 11568 #define HW_AIPS_PACRP_WR(x, v) (ADDRESS_WRITE(hw_aips_pacrp_t, HW_AIPS_PACRP_ADDR(x), v)) 11569 #define HW_AIPS_PACRP_SET(x, v) (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) | (v))) 11570 #define HW_AIPS_PACRP_CLR(x, v) (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) & ~(v))) 11571 #define HW_AIPS_PACRP_TOG(x, v) (HW_AIPS_PACRP_WR(x, HW_AIPS_PACRP_RD(x) ^ (v))) 11572 /*@}*/ 11573 11574 /* 11575 * Constants & macros for individual AIPS_PACRP bitfields 11576 */ 11577 11578 /*! 11579 * @name Register AIPS_PACRP, field TP7[0] (RW) 11580 * 11581 * Determines whether the peripheral allows accesses from an untrusted master. 11582 * When this field is set and an access is attempted by an untrusted master, the 11583 * access terminates with an error response and no peripheral access initiates. 11584 * 11585 * Values: 11586 * - 0 - Accesses from an untrusted master are allowed. 11587 * - 1 - Accesses from an untrusted master are not allowed. 11588 */ 11589 /*@{*/ 11590 #define BP_AIPS_PACRP_TP7 (0U) /*!< Bit position for AIPS_PACRP_TP7. */ 11591 #define BM_AIPS_PACRP_TP7 (0x00000001U) /*!< Bit mask for AIPS_PACRP_TP7. */ 11592 #define BS_AIPS_PACRP_TP7 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP7. */ 11593 11594 /*! @brief Read current value of the AIPS_PACRP_TP7 field. */ 11595 #define BR_AIPS_PACRP_TP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP7))) 11596 11597 /*! @brief Format value for bitfield AIPS_PACRP_TP7. */ 11598 #define BF_AIPS_PACRP_TP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP7) & BM_AIPS_PACRP_TP7) 11599 11600 /*! @brief Set the TP7 field to a new value. */ 11601 #define BW_AIPS_PACRP_TP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP7), v)) 11602 /*@}*/ 11603 11604 /*! 11605 * @name Register AIPS_PACRP, field WP7[1] (RW) 11606 * 11607 * Determines whether the peripheral allows write accesses. When this field is 11608 * set and a write access is attempted, access terminates with an error response 11609 * and no peripheral access initiates. 11610 * 11611 * Values: 11612 * - 0 - This peripheral allows write accesses. 11613 * - 1 - This peripheral is write protected. 11614 */ 11615 /*@{*/ 11616 #define BP_AIPS_PACRP_WP7 (1U) /*!< Bit position for AIPS_PACRP_WP7. */ 11617 #define BM_AIPS_PACRP_WP7 (0x00000002U) /*!< Bit mask for AIPS_PACRP_WP7. */ 11618 #define BS_AIPS_PACRP_WP7 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP7. */ 11619 11620 /*! @brief Read current value of the AIPS_PACRP_WP7 field. */ 11621 #define BR_AIPS_PACRP_WP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP7))) 11622 11623 /*! @brief Format value for bitfield AIPS_PACRP_WP7. */ 11624 #define BF_AIPS_PACRP_WP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP7) & BM_AIPS_PACRP_WP7) 11625 11626 /*! @brief Set the WP7 field to a new value. */ 11627 #define BW_AIPS_PACRP_WP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP7), v)) 11628 /*@}*/ 11629 11630 /*! 11631 * @name Register AIPS_PACRP, field SP7[2] (RW) 11632 * 11633 * Determines whether the peripheral requires supervisor privilege level for 11634 * accesses. When this field is set, the master privilege level must indicate the 11635 * supervisor access attribute, and the MPRx[MPLn] control field for the master 11636 * must be set. If not, access terminates with an error response and no peripheral 11637 * access initiates. 11638 * 11639 * Values: 11640 * - 0 - This peripheral does not require supervisor privilege level for 11641 * accesses. 11642 * - 1 - This peripheral requires supervisor privilege level for accesses. 11643 */ 11644 /*@{*/ 11645 #define BP_AIPS_PACRP_SP7 (2U) /*!< Bit position for AIPS_PACRP_SP7. */ 11646 #define BM_AIPS_PACRP_SP7 (0x00000004U) /*!< Bit mask for AIPS_PACRP_SP7. */ 11647 #define BS_AIPS_PACRP_SP7 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP7. */ 11648 11649 /*! @brief Read current value of the AIPS_PACRP_SP7 field. */ 11650 #define BR_AIPS_PACRP_SP7(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP7))) 11651 11652 /*! @brief Format value for bitfield AIPS_PACRP_SP7. */ 11653 #define BF_AIPS_PACRP_SP7(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP7) & BM_AIPS_PACRP_SP7) 11654 11655 /*! @brief Set the SP7 field to a new value. */ 11656 #define BW_AIPS_PACRP_SP7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP7), v)) 11657 /*@}*/ 11658 11659 /*! 11660 * @name Register AIPS_PACRP, field TP6[4] (RW) 11661 * 11662 * Determines whether the peripheral allows accesses from an untrusted master. 11663 * When this field is set and an access is attempted by an untrusted master, the 11664 * access terminates with an error response and no peripheral access initiates. 11665 * 11666 * Values: 11667 * - 0 - Accesses from an untrusted master are allowed. 11668 * - 1 - Accesses from an untrusted master are not allowed. 11669 */ 11670 /*@{*/ 11671 #define BP_AIPS_PACRP_TP6 (4U) /*!< Bit position for AIPS_PACRP_TP6. */ 11672 #define BM_AIPS_PACRP_TP6 (0x00000010U) /*!< Bit mask for AIPS_PACRP_TP6. */ 11673 #define BS_AIPS_PACRP_TP6 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP6. */ 11674 11675 /*! @brief Read current value of the AIPS_PACRP_TP6 field. */ 11676 #define BR_AIPS_PACRP_TP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP6))) 11677 11678 /*! @brief Format value for bitfield AIPS_PACRP_TP6. */ 11679 #define BF_AIPS_PACRP_TP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP6) & BM_AIPS_PACRP_TP6) 11680 11681 /*! @brief Set the TP6 field to a new value. */ 11682 #define BW_AIPS_PACRP_TP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP6), v)) 11683 /*@}*/ 11684 11685 /*! 11686 * @name Register AIPS_PACRP, field WP6[5] (RW) 11687 * 11688 * Determines whether the peripheral allows write accesses. When this field is 11689 * set and a write access is attempted, access terminates with an error response 11690 * and no peripheral access initiates. 11691 * 11692 * Values: 11693 * - 0 - This peripheral allows write accesses. 11694 * - 1 - This peripheral is write protected. 11695 */ 11696 /*@{*/ 11697 #define BP_AIPS_PACRP_WP6 (5U) /*!< Bit position for AIPS_PACRP_WP6. */ 11698 #define BM_AIPS_PACRP_WP6 (0x00000020U) /*!< Bit mask for AIPS_PACRP_WP6. */ 11699 #define BS_AIPS_PACRP_WP6 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP6. */ 11700 11701 /*! @brief Read current value of the AIPS_PACRP_WP6 field. */ 11702 #define BR_AIPS_PACRP_WP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP6))) 11703 11704 /*! @brief Format value for bitfield AIPS_PACRP_WP6. */ 11705 #define BF_AIPS_PACRP_WP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP6) & BM_AIPS_PACRP_WP6) 11706 11707 /*! @brief Set the WP6 field to a new value. */ 11708 #define BW_AIPS_PACRP_WP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP6), v)) 11709 /*@}*/ 11710 11711 /*! 11712 * @name Register AIPS_PACRP, field SP6[6] (RW) 11713 * 11714 * Determines whether the peripheral requires supervisor privilege level for 11715 * accesses. When this field is set, the master privilege level must indicate the 11716 * supervisor access attribute, and the MPRx[MPLn] control field for the master 11717 * must be set. If not, access terminates with an error response and no peripheral 11718 * access initiates. 11719 * 11720 * Values: 11721 * - 0 - This peripheral does not require supervisor privilege level for 11722 * accesses. 11723 * - 1 - This peripheral requires supervisor privilege level for accesses. 11724 */ 11725 /*@{*/ 11726 #define BP_AIPS_PACRP_SP6 (6U) /*!< Bit position for AIPS_PACRP_SP6. */ 11727 #define BM_AIPS_PACRP_SP6 (0x00000040U) /*!< Bit mask for AIPS_PACRP_SP6. */ 11728 #define BS_AIPS_PACRP_SP6 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP6. */ 11729 11730 /*! @brief Read current value of the AIPS_PACRP_SP6 field. */ 11731 #define BR_AIPS_PACRP_SP6(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP6))) 11732 11733 /*! @brief Format value for bitfield AIPS_PACRP_SP6. */ 11734 #define BF_AIPS_PACRP_SP6(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP6) & BM_AIPS_PACRP_SP6) 11735 11736 /*! @brief Set the SP6 field to a new value. */ 11737 #define BW_AIPS_PACRP_SP6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP6), v)) 11738 /*@}*/ 11739 11740 /*! 11741 * @name Register AIPS_PACRP, field TP5[8] (RW) 11742 * 11743 * Determines whether the peripheral allows accesses from an untrusted master. 11744 * When this field is set and an access is attempted by an untrusted master, the 11745 * access terminates with an error response and no peripheral access initiates. 11746 * 11747 * Values: 11748 * - 0 - Accesses from an untrusted master are allowed. 11749 * - 1 - Accesses from an untrusted master are not allowed. 11750 */ 11751 /*@{*/ 11752 #define BP_AIPS_PACRP_TP5 (8U) /*!< Bit position for AIPS_PACRP_TP5. */ 11753 #define BM_AIPS_PACRP_TP5 (0x00000100U) /*!< Bit mask for AIPS_PACRP_TP5. */ 11754 #define BS_AIPS_PACRP_TP5 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP5. */ 11755 11756 /*! @brief Read current value of the AIPS_PACRP_TP5 field. */ 11757 #define BR_AIPS_PACRP_TP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP5))) 11758 11759 /*! @brief Format value for bitfield AIPS_PACRP_TP5. */ 11760 #define BF_AIPS_PACRP_TP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP5) & BM_AIPS_PACRP_TP5) 11761 11762 /*! @brief Set the TP5 field to a new value. */ 11763 #define BW_AIPS_PACRP_TP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP5), v)) 11764 /*@}*/ 11765 11766 /*! 11767 * @name Register AIPS_PACRP, field WP5[9] (RW) 11768 * 11769 * Determines whether the peripheral allows write accesses. When this field is 11770 * set and a write access is attempted, access terminates with an error response 11771 * and no peripheral access initiates. 11772 * 11773 * Values: 11774 * - 0 - This peripheral allows write accesses. 11775 * - 1 - This peripheral is write protected. 11776 */ 11777 /*@{*/ 11778 #define BP_AIPS_PACRP_WP5 (9U) /*!< Bit position for AIPS_PACRP_WP5. */ 11779 #define BM_AIPS_PACRP_WP5 (0x00000200U) /*!< Bit mask for AIPS_PACRP_WP5. */ 11780 #define BS_AIPS_PACRP_WP5 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP5. */ 11781 11782 /*! @brief Read current value of the AIPS_PACRP_WP5 field. */ 11783 #define BR_AIPS_PACRP_WP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP5))) 11784 11785 /*! @brief Format value for bitfield AIPS_PACRP_WP5. */ 11786 #define BF_AIPS_PACRP_WP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP5) & BM_AIPS_PACRP_WP5) 11787 11788 /*! @brief Set the WP5 field to a new value. */ 11789 #define BW_AIPS_PACRP_WP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP5), v)) 11790 /*@}*/ 11791 11792 /*! 11793 * @name Register AIPS_PACRP, field SP5[10] (RW) 11794 * 11795 * Determines whether the peripheral requires supervisor privilege level for 11796 * accesses. When this field is set, the master privilege level must indicate the 11797 * supervisor access attribute, and the MPRx[MPLn] control field for the master 11798 * must be set. If not, access terminates with an error response and no peripheral 11799 * access initiates. 11800 * 11801 * Values: 11802 * - 0 - This peripheral does not require supervisor privilege level for 11803 * accesses. 11804 * - 1 - This peripheral requires supervisor privilege level for accesses. 11805 */ 11806 /*@{*/ 11807 #define BP_AIPS_PACRP_SP5 (10U) /*!< Bit position for AIPS_PACRP_SP5. */ 11808 #define BM_AIPS_PACRP_SP5 (0x00000400U) /*!< Bit mask for AIPS_PACRP_SP5. */ 11809 #define BS_AIPS_PACRP_SP5 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP5. */ 11810 11811 /*! @brief Read current value of the AIPS_PACRP_SP5 field. */ 11812 #define BR_AIPS_PACRP_SP5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP5))) 11813 11814 /*! @brief Format value for bitfield AIPS_PACRP_SP5. */ 11815 #define BF_AIPS_PACRP_SP5(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP5) & BM_AIPS_PACRP_SP5) 11816 11817 /*! @brief Set the SP5 field to a new value. */ 11818 #define BW_AIPS_PACRP_SP5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP5), v)) 11819 /*@}*/ 11820 11821 /*! 11822 * @name Register AIPS_PACRP, field TP4[12] (RW) 11823 * 11824 * Determines whether the peripheral allows accesses from an untrusted master. 11825 * When this bit is set and an access is attempted by an untrusted master, the 11826 * access terminates with an error response and no peripheral access initiates. 11827 * 11828 * Values: 11829 * - 0 - Accesses from an untrusted master are allowed. 11830 * - 1 - Accesses from an untrusted master are not allowed. 11831 */ 11832 /*@{*/ 11833 #define BP_AIPS_PACRP_TP4 (12U) /*!< Bit position for AIPS_PACRP_TP4. */ 11834 #define BM_AIPS_PACRP_TP4 (0x00001000U) /*!< Bit mask for AIPS_PACRP_TP4. */ 11835 #define BS_AIPS_PACRP_TP4 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP4. */ 11836 11837 /*! @brief Read current value of the AIPS_PACRP_TP4 field. */ 11838 #define BR_AIPS_PACRP_TP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP4))) 11839 11840 /*! @brief Format value for bitfield AIPS_PACRP_TP4. */ 11841 #define BF_AIPS_PACRP_TP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP4) & BM_AIPS_PACRP_TP4) 11842 11843 /*! @brief Set the TP4 field to a new value. */ 11844 #define BW_AIPS_PACRP_TP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP4), v)) 11845 /*@}*/ 11846 11847 /*! 11848 * @name Register AIPS_PACRP, field WP4[13] (RW) 11849 * 11850 * Determines whether the peripheral allows write accesses. When this field is 11851 * set and a write access is attempted, access terminates with an error response 11852 * and no peripheral access initiates. 11853 * 11854 * Values: 11855 * - 0 - This peripheral allows write accesses. 11856 * - 1 - This peripheral is write protected. 11857 */ 11858 /*@{*/ 11859 #define BP_AIPS_PACRP_WP4 (13U) /*!< Bit position for AIPS_PACRP_WP4. */ 11860 #define BM_AIPS_PACRP_WP4 (0x00002000U) /*!< Bit mask for AIPS_PACRP_WP4. */ 11861 #define BS_AIPS_PACRP_WP4 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP4. */ 11862 11863 /*! @brief Read current value of the AIPS_PACRP_WP4 field. */ 11864 #define BR_AIPS_PACRP_WP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP4))) 11865 11866 /*! @brief Format value for bitfield AIPS_PACRP_WP4. */ 11867 #define BF_AIPS_PACRP_WP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP4) & BM_AIPS_PACRP_WP4) 11868 11869 /*! @brief Set the WP4 field to a new value. */ 11870 #define BW_AIPS_PACRP_WP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP4), v)) 11871 /*@}*/ 11872 11873 /*! 11874 * @name Register AIPS_PACRP, field SP4[14] (RW) 11875 * 11876 * Determines whether the peripheral requires supervisor privilege level for 11877 * access. When this bit is set, the master privilege level must indicate the 11878 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 11879 * set. If not, access terminates with an error response and no peripheral access 11880 * initiates. 11881 * 11882 * Values: 11883 * - 0 - This peripheral does not require supervisor privilege level for 11884 * accesses. 11885 * - 1 - This peripheral requires supervisor privilege level for accesses. 11886 */ 11887 /*@{*/ 11888 #define BP_AIPS_PACRP_SP4 (14U) /*!< Bit position for AIPS_PACRP_SP4. */ 11889 #define BM_AIPS_PACRP_SP4 (0x00004000U) /*!< Bit mask for AIPS_PACRP_SP4. */ 11890 #define BS_AIPS_PACRP_SP4 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP4. */ 11891 11892 /*! @brief Read current value of the AIPS_PACRP_SP4 field. */ 11893 #define BR_AIPS_PACRP_SP4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP4))) 11894 11895 /*! @brief Format value for bitfield AIPS_PACRP_SP4. */ 11896 #define BF_AIPS_PACRP_SP4(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP4) & BM_AIPS_PACRP_SP4) 11897 11898 /*! @brief Set the SP4 field to a new value. */ 11899 #define BW_AIPS_PACRP_SP4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP4), v)) 11900 /*@}*/ 11901 11902 /*! 11903 * @name Register AIPS_PACRP, field TP3[16] (RW) 11904 * 11905 * Determines whether the peripheral allows accesses from an untrusted master. 11906 * When this field is set and an access is attempted by an untrusted master, the 11907 * access terminates with an error response and no peripheral access initiates. 11908 * 11909 * Values: 11910 * - 0 - Accesses from an untrusted master are allowed. 11911 * - 1 - Accesses from an untrusted master are not allowed. 11912 */ 11913 /*@{*/ 11914 #define BP_AIPS_PACRP_TP3 (16U) /*!< Bit position for AIPS_PACRP_TP3. */ 11915 #define BM_AIPS_PACRP_TP3 (0x00010000U) /*!< Bit mask for AIPS_PACRP_TP3. */ 11916 #define BS_AIPS_PACRP_TP3 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP3. */ 11917 11918 /*! @brief Read current value of the AIPS_PACRP_TP3 field. */ 11919 #define BR_AIPS_PACRP_TP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP3))) 11920 11921 /*! @brief Format value for bitfield AIPS_PACRP_TP3. */ 11922 #define BF_AIPS_PACRP_TP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP3) & BM_AIPS_PACRP_TP3) 11923 11924 /*! @brief Set the TP3 field to a new value. */ 11925 #define BW_AIPS_PACRP_TP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP3), v)) 11926 /*@}*/ 11927 11928 /*! 11929 * @name Register AIPS_PACRP, field WP3[17] (RW) 11930 * 11931 * Determines whether the peripheral allows write accesss. When this bit is set 11932 * and a write access is attempted, access terminates with an error response and 11933 * no peripheral access initiates. 11934 * 11935 * Values: 11936 * - 0 - This peripheral allows write accesses. 11937 * - 1 - This peripheral is write protected. 11938 */ 11939 /*@{*/ 11940 #define BP_AIPS_PACRP_WP3 (17U) /*!< Bit position for AIPS_PACRP_WP3. */ 11941 #define BM_AIPS_PACRP_WP3 (0x00020000U) /*!< Bit mask for AIPS_PACRP_WP3. */ 11942 #define BS_AIPS_PACRP_WP3 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP3. */ 11943 11944 /*! @brief Read current value of the AIPS_PACRP_WP3 field. */ 11945 #define BR_AIPS_PACRP_WP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP3))) 11946 11947 /*! @brief Format value for bitfield AIPS_PACRP_WP3. */ 11948 #define BF_AIPS_PACRP_WP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP3) & BM_AIPS_PACRP_WP3) 11949 11950 /*! @brief Set the WP3 field to a new value. */ 11951 #define BW_AIPS_PACRP_WP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP3), v)) 11952 /*@}*/ 11953 11954 /*! 11955 * @name Register AIPS_PACRP, field SP3[18] (RW) 11956 * 11957 * Determines whether the peripheral requires supervisor privilege level for 11958 * accesses. When this field is set, the master privilege level must indicate the 11959 * supervisor access attribute, and the MPRx[MPLn] control field for the master 11960 * must be set. If not, access terminates with an error response and no peripheral 11961 * access initiates. 11962 * 11963 * Values: 11964 * - 0 - This peripheral does not require supervisor privilege level for 11965 * accesses. 11966 * - 1 - This peripheral requires supervisor privilege level for accesses. 11967 */ 11968 /*@{*/ 11969 #define BP_AIPS_PACRP_SP3 (18U) /*!< Bit position for AIPS_PACRP_SP3. */ 11970 #define BM_AIPS_PACRP_SP3 (0x00040000U) /*!< Bit mask for AIPS_PACRP_SP3. */ 11971 #define BS_AIPS_PACRP_SP3 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP3. */ 11972 11973 /*! @brief Read current value of the AIPS_PACRP_SP3 field. */ 11974 #define BR_AIPS_PACRP_SP3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP3))) 11975 11976 /*! @brief Format value for bitfield AIPS_PACRP_SP3. */ 11977 #define BF_AIPS_PACRP_SP3(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP3) & BM_AIPS_PACRP_SP3) 11978 11979 /*! @brief Set the SP3 field to a new value. */ 11980 #define BW_AIPS_PACRP_SP3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP3), v)) 11981 /*@}*/ 11982 11983 /*! 11984 * @name Register AIPS_PACRP, field TP2[20] (RW) 11985 * 11986 * Determines whether the peripheral allows accesses from an untrusted master. 11987 * When this bit is set and an access is attempted by an untrusted master, the 11988 * access terminates with an error response and no peripheral access initiates. 11989 * 11990 * Values: 11991 * - 0 - Accesses from an untrusted master are allowed. 11992 * - 1 - Accesses from an untrusted master are not allowed. 11993 */ 11994 /*@{*/ 11995 #define BP_AIPS_PACRP_TP2 (20U) /*!< Bit position for AIPS_PACRP_TP2. */ 11996 #define BM_AIPS_PACRP_TP2 (0x00100000U) /*!< Bit mask for AIPS_PACRP_TP2. */ 11997 #define BS_AIPS_PACRP_TP2 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP2. */ 11998 11999 /*! @brief Read current value of the AIPS_PACRP_TP2 field. */ 12000 #define BR_AIPS_PACRP_TP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP2))) 12001 12002 /*! @brief Format value for bitfield AIPS_PACRP_TP2. */ 12003 #define BF_AIPS_PACRP_TP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP2) & BM_AIPS_PACRP_TP2) 12004 12005 /*! @brief Set the TP2 field to a new value. */ 12006 #define BW_AIPS_PACRP_TP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP2), v)) 12007 /*@}*/ 12008 12009 /*! 12010 * @name Register AIPS_PACRP, field WP2[21] (RW) 12011 * 12012 * Determines whether the peripheral allows write accesses. When this field is 12013 * set and a write access is attempted, access terminates with an error response 12014 * and no peripheral access initiates. 12015 * 12016 * Values: 12017 * - 0 - This peripheral allows write accesses. 12018 * - 1 - This peripheral is write protected. 12019 */ 12020 /*@{*/ 12021 #define BP_AIPS_PACRP_WP2 (21U) /*!< Bit position for AIPS_PACRP_WP2. */ 12022 #define BM_AIPS_PACRP_WP2 (0x00200000U) /*!< Bit mask for AIPS_PACRP_WP2. */ 12023 #define BS_AIPS_PACRP_WP2 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP2. */ 12024 12025 /*! @brief Read current value of the AIPS_PACRP_WP2 field. */ 12026 #define BR_AIPS_PACRP_WP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP2))) 12027 12028 /*! @brief Format value for bitfield AIPS_PACRP_WP2. */ 12029 #define BF_AIPS_PACRP_WP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP2) & BM_AIPS_PACRP_WP2) 12030 12031 /*! @brief Set the WP2 field to a new value. */ 12032 #define BW_AIPS_PACRP_WP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP2), v)) 12033 /*@}*/ 12034 12035 /*! 12036 * @name Register AIPS_PACRP, field SP2[22] (RW) 12037 * 12038 * Determines whether the peripheral requires supervisor privilege level for 12039 * access. When this bit is set, the master privilege level must indicate the 12040 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 12041 * set. If not, access terminates with an error response and no peripheral access 12042 * initiates. 12043 * 12044 * Values: 12045 * - 0 - This peripheral does not require supervisor privilege level for 12046 * accesses. 12047 * - 1 - This peripheral requires supervisor privilege level for accesses. 12048 */ 12049 /*@{*/ 12050 #define BP_AIPS_PACRP_SP2 (22U) /*!< Bit position for AIPS_PACRP_SP2. */ 12051 #define BM_AIPS_PACRP_SP2 (0x00400000U) /*!< Bit mask for AIPS_PACRP_SP2. */ 12052 #define BS_AIPS_PACRP_SP2 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP2. */ 12053 12054 /*! @brief Read current value of the AIPS_PACRP_SP2 field. */ 12055 #define BR_AIPS_PACRP_SP2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP2))) 12056 12057 /*! @brief Format value for bitfield AIPS_PACRP_SP2. */ 12058 #define BF_AIPS_PACRP_SP2(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP2) & BM_AIPS_PACRP_SP2) 12059 12060 /*! @brief Set the SP2 field to a new value. */ 12061 #define BW_AIPS_PACRP_SP2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP2), v)) 12062 /*@}*/ 12063 12064 /*! 12065 * @name Register AIPS_PACRP, field TP1[24] (RW) 12066 * 12067 * Determines whether the peripheral allows accesses from an untrusted master. 12068 * When this field is set and an access is attempted by an untrusted master, the 12069 * access terminates with an error response and no peripheral access initiates. 12070 * 12071 * Values: 12072 * - 0 - Accesses from an untrusted master are allowed. 12073 * - 1 - Accesses from an untrusted master are not allowed. 12074 */ 12075 /*@{*/ 12076 #define BP_AIPS_PACRP_TP1 (24U) /*!< Bit position for AIPS_PACRP_TP1. */ 12077 #define BM_AIPS_PACRP_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRP_TP1. */ 12078 #define BS_AIPS_PACRP_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP1. */ 12079 12080 /*! @brief Read current value of the AIPS_PACRP_TP1 field. */ 12081 #define BR_AIPS_PACRP_TP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP1))) 12082 12083 /*! @brief Format value for bitfield AIPS_PACRP_TP1. */ 12084 #define BF_AIPS_PACRP_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP1) & BM_AIPS_PACRP_TP1) 12085 12086 /*! @brief Set the TP1 field to a new value. */ 12087 #define BW_AIPS_PACRP_TP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP1), v)) 12088 /*@}*/ 12089 12090 /*! 12091 * @name Register AIPS_PACRP, field WP1[25] (RW) 12092 * 12093 * Determines whether the peripheral allows write accesses. When this field is 12094 * set and a write access is attempted, access terminates with an error response 12095 * and no peripheral access initiates. 12096 * 12097 * Values: 12098 * - 0 - This peripheral allows write accesses. 12099 * - 1 - This peripheral is write protected. 12100 */ 12101 /*@{*/ 12102 #define BP_AIPS_PACRP_WP1 (25U) /*!< Bit position for AIPS_PACRP_WP1. */ 12103 #define BM_AIPS_PACRP_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRP_WP1. */ 12104 #define BS_AIPS_PACRP_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP1. */ 12105 12106 /*! @brief Read current value of the AIPS_PACRP_WP1 field. */ 12107 #define BR_AIPS_PACRP_WP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP1))) 12108 12109 /*! @brief Format value for bitfield AIPS_PACRP_WP1. */ 12110 #define BF_AIPS_PACRP_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP1) & BM_AIPS_PACRP_WP1) 12111 12112 /*! @brief Set the WP1 field to a new value. */ 12113 #define BW_AIPS_PACRP_WP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP1), v)) 12114 /*@}*/ 12115 12116 /*! 12117 * @name Register AIPS_PACRP, field SP1[26] (RW) 12118 * 12119 * Determines whether the peripheral requires supervisor privilege level for 12120 * access. When this field is set, the master privilege level must indicate the 12121 * supervisor access attribute, and the MPRx[MPLn] control field for the master must 12122 * be set. If not, access terminates with an error response and no peripheral 12123 * access initiates. 12124 * 12125 * Values: 12126 * - 0 - This peripheral does not require supervisor privilege level for 12127 * accesses. 12128 * - 1 - This peripheral requires supervisor privilege level for accesses. 12129 */ 12130 /*@{*/ 12131 #define BP_AIPS_PACRP_SP1 (26U) /*!< Bit position for AIPS_PACRP_SP1. */ 12132 #define BM_AIPS_PACRP_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRP_SP1. */ 12133 #define BS_AIPS_PACRP_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP1. */ 12134 12135 /*! @brief Read current value of the AIPS_PACRP_SP1 field. */ 12136 #define BR_AIPS_PACRP_SP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP1))) 12137 12138 /*! @brief Format value for bitfield AIPS_PACRP_SP1. */ 12139 #define BF_AIPS_PACRP_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP1) & BM_AIPS_PACRP_SP1) 12140 12141 /*! @brief Set the SP1 field to a new value. */ 12142 #define BW_AIPS_PACRP_SP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP1), v)) 12143 /*@}*/ 12144 12145 /*! 12146 * @name Register AIPS_PACRP, field TP0[28] (RW) 12147 * 12148 * Determines whether the peripheral allows accesses from an untrusted master. 12149 * When this bit is set and an access is attempted by an untrusted master, the 12150 * access terminates with an error response and no peripheral access initiates. 12151 * 12152 * Values: 12153 * - 0 - Accesses from an untrusted master are allowed. 12154 * - 1 - Accesses from an untrusted master are not allowed. 12155 */ 12156 /*@{*/ 12157 #define BP_AIPS_PACRP_TP0 (28U) /*!< Bit position for AIPS_PACRP_TP0. */ 12158 #define BM_AIPS_PACRP_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRP_TP0. */ 12159 #define BS_AIPS_PACRP_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRP_TP0. */ 12160 12161 /*! @brief Read current value of the AIPS_PACRP_TP0 field. */ 12162 #define BR_AIPS_PACRP_TP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP0))) 12163 12164 /*! @brief Format value for bitfield AIPS_PACRP_TP0. */ 12165 #define BF_AIPS_PACRP_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_TP0) & BM_AIPS_PACRP_TP0) 12166 12167 /*! @brief Set the TP0 field to a new value. */ 12168 #define BW_AIPS_PACRP_TP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_TP0), v)) 12169 /*@}*/ 12170 12171 /*! 12172 * @name Register AIPS_PACRP, field WP0[29] (RW) 12173 * 12174 * Determines whether the peripheral allows write accesses. When this field is 12175 * set and a write access is attempted, access terminates with an error response 12176 * and no peripheral access initiates. 12177 * 12178 * Values: 12179 * - 0 - This peripheral allows write accesses. 12180 * - 1 - This peripheral is write protected. 12181 */ 12182 /*@{*/ 12183 #define BP_AIPS_PACRP_WP0 (29U) /*!< Bit position for AIPS_PACRP_WP0. */ 12184 #define BM_AIPS_PACRP_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRP_WP0. */ 12185 #define BS_AIPS_PACRP_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRP_WP0. */ 12186 12187 /*! @brief Read current value of the AIPS_PACRP_WP0 field. */ 12188 #define BR_AIPS_PACRP_WP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP0))) 12189 12190 /*! @brief Format value for bitfield AIPS_PACRP_WP0. */ 12191 #define BF_AIPS_PACRP_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_WP0) & BM_AIPS_PACRP_WP0) 12192 12193 /*! @brief Set the WP0 field to a new value. */ 12194 #define BW_AIPS_PACRP_WP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_WP0), v)) 12195 /*@}*/ 12196 12197 /*! 12198 * @name Register AIPS_PACRP, field SP0[30] (RW) 12199 * 12200 * Determines whether the peripheral requires supervisor privilege level for 12201 * accesses. When this field is set, the master privilege level must indicate the 12202 * supervisor access attribute, and the MPRx[MPLn] control field for the master 12203 * must be set. If not, access terminates with an error response and no peripheral 12204 * access initiates. 12205 * 12206 * Values: 12207 * - 0 - This peripheral does not require supervisor privilege level for 12208 * accesses. 12209 * - 1 - This peripheral requires supervisor privilege level for accesses. 12210 */ 12211 /*@{*/ 12212 #define BP_AIPS_PACRP_SP0 (30U) /*!< Bit position for AIPS_PACRP_SP0. */ 12213 #define BM_AIPS_PACRP_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRP_SP0. */ 12214 #define BS_AIPS_PACRP_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRP_SP0. */ 12215 12216 /*! @brief Read current value of the AIPS_PACRP_SP0 field. */ 12217 #define BR_AIPS_PACRP_SP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP0))) 12218 12219 /*! @brief Format value for bitfield AIPS_PACRP_SP0. */ 12220 #define BF_AIPS_PACRP_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRP_SP0) & BM_AIPS_PACRP_SP0) 12221 12222 /*! @brief Set the SP0 field to a new value. */ 12223 #define BW_AIPS_PACRP_SP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRP_ADDR(x), BP_AIPS_PACRP_SP0), v)) 12224 /*@}*/ 12225 12226 /******************************************************************************* 12227 * HW_AIPS_PACRU - Peripheral Access Control Register 12228 ******************************************************************************/ 12229 12230 /*! 12231 * @brief HW_AIPS_PACRU - Peripheral Access Control Register (RW) 12232 * 12233 * Reset value: 0x44000000U 12234 * 12235 * PACRU defines the access levels for the two global spaces. 12236 */ 12237 typedef union _hw_aips_pacru 12238 { 12239 uint32_t U; 12240 struct _hw_aips_pacru_bitfields 12241 { 12242 uint32_t RESERVED0 : 24; /*!< [23:0] */ 12243 uint32_t TP1 : 1; /*!< [24] Trusted Protect */ 12244 uint32_t WP1 : 1; /*!< [25] Write Protect */ 12245 uint32_t SP1 : 1; /*!< [26] Supervisor Protect */ 12246 uint32_t RESERVED1 : 1; /*!< [27] */ 12247 uint32_t TP0 : 1; /*!< [28] Trusted Protect */ 12248 uint32_t WP0 : 1; /*!< [29] Write Protect */ 12249 uint32_t SP0 : 1; /*!< [30] Supervisor Protect */ 12250 uint32_t RESERVED2 : 1; /*!< [31] */ 12251 } B; 12252 } hw_aips_pacru_t; 12253 12254 /*! 12255 * @name Constants and macros for entire AIPS_PACRU register 12256 */ 12257 /*@{*/ 12258 #define HW_AIPS_PACRU_ADDR(x) ((x) + 0x80U) 12259 12260 #define HW_AIPS_PACRU(x) (*(__IO hw_aips_pacru_t *) HW_AIPS_PACRU_ADDR(x)) 12261 #define HW_AIPS_PACRU_RD(x) (ADDRESS_READ(hw_aips_pacru_t, HW_AIPS_PACRU_ADDR(x))) 12262 #define HW_AIPS_PACRU_WR(x, v) (ADDRESS_WRITE(hw_aips_pacru_t, HW_AIPS_PACRU_ADDR(x), v)) 12263 #define HW_AIPS_PACRU_SET(x, v) (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) | (v))) 12264 #define HW_AIPS_PACRU_CLR(x, v) (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) & ~(v))) 12265 #define HW_AIPS_PACRU_TOG(x, v) (HW_AIPS_PACRU_WR(x, HW_AIPS_PACRU_RD(x) ^ (v))) 12266 /*@}*/ 12267 12268 /* 12269 * Constants & macros for individual AIPS_PACRU bitfields 12270 */ 12271 12272 /*! 12273 * @name Register AIPS_PACRU, field TP1[24] (RW) 12274 * 12275 * Determines whether the peripheral allows accesses from an untrusted master. 12276 * When this field is set and an access is attempted by an untrusted master, the 12277 * access terminates with an error response and no peripheral access initiates. 12278 * 12279 * Values: 12280 * - 0 - Accesses from an untrusted master are allowed. 12281 * - 1 - Accesses from an untrusted master are not allowed. 12282 */ 12283 /*@{*/ 12284 #define BP_AIPS_PACRU_TP1 (24U) /*!< Bit position for AIPS_PACRU_TP1. */ 12285 #define BM_AIPS_PACRU_TP1 (0x01000000U) /*!< Bit mask for AIPS_PACRU_TP1. */ 12286 #define BS_AIPS_PACRU_TP1 (1U) /*!< Bit field size in bits for AIPS_PACRU_TP1. */ 12287 12288 /*! @brief Read current value of the AIPS_PACRU_TP1 field. */ 12289 #define BR_AIPS_PACRU_TP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP1))) 12290 12291 /*! @brief Format value for bitfield AIPS_PACRU_TP1. */ 12292 #define BF_AIPS_PACRU_TP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRU_TP1) & BM_AIPS_PACRU_TP1) 12293 12294 /*! @brief Set the TP1 field to a new value. */ 12295 #define BW_AIPS_PACRU_TP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP1), v)) 12296 /*@}*/ 12297 12298 /*! 12299 * @name Register AIPS_PACRU, field WP1[25] (RW) 12300 * 12301 * Determines whether the peripheral allows write accesss. When this bit is set 12302 * and a write access is attempted, access terminates with an error response and 12303 * no peripheral access initiates. 12304 * 12305 * Values: 12306 * - 0 - This peripheral allows write accesses. 12307 * - 1 - This peripheral is write protected. 12308 */ 12309 /*@{*/ 12310 #define BP_AIPS_PACRU_WP1 (25U) /*!< Bit position for AIPS_PACRU_WP1. */ 12311 #define BM_AIPS_PACRU_WP1 (0x02000000U) /*!< Bit mask for AIPS_PACRU_WP1. */ 12312 #define BS_AIPS_PACRU_WP1 (1U) /*!< Bit field size in bits for AIPS_PACRU_WP1. */ 12313 12314 /*! @brief Read current value of the AIPS_PACRU_WP1 field. */ 12315 #define BR_AIPS_PACRU_WP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP1))) 12316 12317 /*! @brief Format value for bitfield AIPS_PACRU_WP1. */ 12318 #define BF_AIPS_PACRU_WP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRU_WP1) & BM_AIPS_PACRU_WP1) 12319 12320 /*! @brief Set the WP1 field to a new value. */ 12321 #define BW_AIPS_PACRU_WP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP1), v)) 12322 /*@}*/ 12323 12324 /*! 12325 * @name Register AIPS_PACRU, field SP1[26] (RW) 12326 * 12327 * Determines whether the peripheral requires supervisor privilege level for 12328 * accesses. When this field is set, the master privilege level must indicate the 12329 * supervisor access attribute, and the MPRx[MPLn] control field for the master 12330 * must be set. If not, access terminates with an error response and no peripheral 12331 * access initiates. 12332 * 12333 * Values: 12334 * - 0 - This peripheral does not require supervisor privilege level for 12335 * accesses. 12336 * - 1 - This peripheral requires supervisor privilege level for accesses. 12337 */ 12338 /*@{*/ 12339 #define BP_AIPS_PACRU_SP1 (26U) /*!< Bit position for AIPS_PACRU_SP1. */ 12340 #define BM_AIPS_PACRU_SP1 (0x04000000U) /*!< Bit mask for AIPS_PACRU_SP1. */ 12341 #define BS_AIPS_PACRU_SP1 (1U) /*!< Bit field size in bits for AIPS_PACRU_SP1. */ 12342 12343 /*! @brief Read current value of the AIPS_PACRU_SP1 field. */ 12344 #define BR_AIPS_PACRU_SP1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP1))) 12345 12346 /*! @brief Format value for bitfield AIPS_PACRU_SP1. */ 12347 #define BF_AIPS_PACRU_SP1(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRU_SP1) & BM_AIPS_PACRU_SP1) 12348 12349 /*! @brief Set the SP1 field to a new value. */ 12350 #define BW_AIPS_PACRU_SP1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP1), v)) 12351 /*@}*/ 12352 12353 /*! 12354 * @name Register AIPS_PACRU, field TP0[28] (RW) 12355 * 12356 * Determines whether the peripheral allows accesses from an untrusted master. 12357 * When this field is set and an access is attempted by an untrusted master, the 12358 * access terminates with an error response and no peripheral access initiates. 12359 * 12360 * Values: 12361 * - 0 - Accesses from an untrusted master are allowed. 12362 * - 1 - Accesses from an untrusted master are not allowed. 12363 */ 12364 /*@{*/ 12365 #define BP_AIPS_PACRU_TP0 (28U) /*!< Bit position for AIPS_PACRU_TP0. */ 12366 #define BM_AIPS_PACRU_TP0 (0x10000000U) /*!< Bit mask for AIPS_PACRU_TP0. */ 12367 #define BS_AIPS_PACRU_TP0 (1U) /*!< Bit field size in bits for AIPS_PACRU_TP0. */ 12368 12369 /*! @brief Read current value of the AIPS_PACRU_TP0 field. */ 12370 #define BR_AIPS_PACRU_TP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP0))) 12371 12372 /*! @brief Format value for bitfield AIPS_PACRU_TP0. */ 12373 #define BF_AIPS_PACRU_TP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRU_TP0) & BM_AIPS_PACRU_TP0) 12374 12375 /*! @brief Set the TP0 field to a new value. */ 12376 #define BW_AIPS_PACRU_TP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_TP0), v)) 12377 /*@}*/ 12378 12379 /*! 12380 * @name Register AIPS_PACRU, field WP0[29] (RW) 12381 * 12382 * Determines whether the peripheral allows write accesses. When this field is 12383 * set and a write access is attempted, access terminates with an error response 12384 * and no peripheral access initiates. 12385 * 12386 * Values: 12387 * - 0 - This peripheral allows write accesses. 12388 * - 1 - This peripheral is write protected. 12389 */ 12390 /*@{*/ 12391 #define BP_AIPS_PACRU_WP0 (29U) /*!< Bit position for AIPS_PACRU_WP0. */ 12392 #define BM_AIPS_PACRU_WP0 (0x20000000U) /*!< Bit mask for AIPS_PACRU_WP0. */ 12393 #define BS_AIPS_PACRU_WP0 (1U) /*!< Bit field size in bits for AIPS_PACRU_WP0. */ 12394 12395 /*! @brief Read current value of the AIPS_PACRU_WP0 field. */ 12396 #define BR_AIPS_PACRU_WP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP0))) 12397 12398 /*! @brief Format value for bitfield AIPS_PACRU_WP0. */ 12399 #define BF_AIPS_PACRU_WP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRU_WP0) & BM_AIPS_PACRU_WP0) 12400 12401 /*! @brief Set the WP0 field to a new value. */ 12402 #define BW_AIPS_PACRU_WP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_WP0), v)) 12403 /*@}*/ 12404 12405 /*! 12406 * @name Register AIPS_PACRU, field SP0[30] (RW) 12407 * 12408 * Determines whether the peripheral requires supervisor privilege level for 12409 * access. When this bit is set, the master privilege level must indicate the 12410 * supervisor access attribute, and the MPRx[MPLn] control bit for the master must be 12411 * set. If not, access terminates with an error response and no peripheral access 12412 * initiates. 12413 * 12414 * Values: 12415 * - 0 - This peripheral does not require supervisor privilege level for 12416 * accesses. 12417 * - 1 - This peripheral requires supervisor privilege level for accesses. 12418 */ 12419 /*@{*/ 12420 #define BP_AIPS_PACRU_SP0 (30U) /*!< Bit position for AIPS_PACRU_SP0. */ 12421 #define BM_AIPS_PACRU_SP0 (0x40000000U) /*!< Bit mask for AIPS_PACRU_SP0. */ 12422 #define BS_AIPS_PACRU_SP0 (1U) /*!< Bit field size in bits for AIPS_PACRU_SP0. */ 12423 12424 /*! @brief Read current value of the AIPS_PACRU_SP0 field. */ 12425 #define BR_AIPS_PACRU_SP0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP0))) 12426 12427 /*! @brief Format value for bitfield AIPS_PACRU_SP0. */ 12428 #define BF_AIPS_PACRU_SP0(v) ((uint32_t)((uint32_t)(v) << BP_AIPS_PACRU_SP0) & BM_AIPS_PACRU_SP0) 12429 12430 /*! @brief Set the SP0 field to a new value. */ 12431 #define BW_AIPS_PACRU_SP0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_AIPS_PACRU_ADDR(x), BP_AIPS_PACRU_SP0), v)) 12432 /*@}*/ 12433 12434 /******************************************************************************* 12435 * hw_aips_t - module struct 12436 ******************************************************************************/ 12437 /*! 12438 * @brief All AIPS module registers. 12439 */ 12440 #pragma pack(1) 12441 typedef struct _hw_aips 12442 { 12443 __IO hw_aips_mpra_t MPRA ; /*!< [0x0] Master Privilege Register A */ 12444 uint8_t _reserved0[28]; 12445 __IO hw_aips_pacra_t PACRA ; /*!< [0x20] Peripheral Access Control Register */ 12446 __IO hw_aips_pacrb_t PACRB ; /*!< [0x24] Peripheral Access Control Register */ 12447 __IO hw_aips_pacrc_t PACRC ; /*!< [0x28] Peripheral Access Control Register */ 12448 __IO hw_aips_pacrd_t PACRD ; /*!< [0x2C] Peripheral Access Control Register */ 12449 uint8_t _reserved1[16]; 12450 __IO hw_aips_pacre_t PACRE ; /*!< [0x40] Peripheral Access Control Register */ 12451 __IO hw_aips_pacrf_t PACRF ; /*!< [0x44] Peripheral Access Control Register */ 12452 __IO hw_aips_pacrg_t PACRG ; /*!< [0x48] Peripheral Access Control Register */ 12453 __IO hw_aips_pacrh_t PACRH ; /*!< [0x4C] Peripheral Access Control Register */ 12454 __IO hw_aips_pacri_t PACRI ; /*!< [0x50] Peripheral Access Control Register */ 12455 __IO hw_aips_pacrj_t PACRJ ; /*!< [0x54] Peripheral Access Control Register */ 12456 __IO hw_aips_pacrk_t PACRK ; /*!< [0x58] Peripheral Access Control Register */ 12457 __IO hw_aips_pacrl_t PACRL ; /*!< [0x5C] Peripheral Access Control Register */ 12458 __IO hw_aips_pacrm_t PACRM ; /*!< [0x60] Peripheral Access Control Register */ 12459 __IO hw_aips_pacrn_t PACRN ; /*!< [0x64] Peripheral Access Control Register */ 12460 __IO hw_aips_pacro_t PACRO ; /*!< [0x68] Peripheral Access Control Register */ 12461 __IO hw_aips_pacrp_t PACRP ; /*!< [0x6C] Peripheral Access Control Register */ 12462 uint8_t _reserved2[16]; 12463 __IO hw_aips_pacru_t PACRU ; /*!< [0x80] Peripheral Access Control Register */ 12464 } hw_aips_t; 12465 #pragma pack() 12466 12467 /*! @brief Macro to access all AIPS registers. */ 12468 /*! @param x AIPS module instance base address. */ 12469 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, 12470 * use the '&' operator, like <code>&HW_AIPS(AIPS0_BASE)</code>. */ 12471 #define HW_AIPS(x) (*(hw_aips_t *)(x)) 12472 12473 #endif /* __HW_AIPS_REGISTERS_H__ */ 12474 /* EOF */
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