Alessandro Angelino / target-freescale-ksdk

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Fork of target-freescale-ksdk by Morpheus

TARGET_KPSDK_CODE/hal/flextimer/fsl_ftm_hal.c@0:e4d670b91a9a, 2016-03-23 (annotated)

Committer:
screamer
Date:
Wed Mar 23 21:26:50 2016 +0000
Revision:
0:e4d670b91a9a
Initial revision

Who changed what in which revision?

UserRevisionLine numberNew contents of line
screamer 0:e4d670b91a9a 1 /*
screamer 0:e4d670b91a9a 2 * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
screamer 0:e4d670b91a9a 3 * All rights reserved.
screamer 0:e4d670b91a9a 4 *
screamer 0:e4d670b91a9a 5 * Redistribution and use in source and binary forms, with or without modification,
screamer 0:e4d670b91a9a 6 * are permitted provided that the following conditions are met:
screamer 0:e4d670b91a9a 7 *
screamer 0:e4d670b91a9a 8 * o Redistributions of source code must retain the above copyright notice, this list
screamer 0:e4d670b91a9a 9 * of conditions and the following disclaimer.
screamer 0:e4d670b91a9a 10 *
screamer 0:e4d670b91a9a 11 * o Redistributions in binary form must reproduce the above copyright notice, this
screamer 0:e4d670b91a9a 12 * list of conditions and the following disclaimer in the documentation and/or
screamer 0:e4d670b91a9a 13 * other materials provided with the distribution.
screamer 0:e4d670b91a9a 14 *
screamer 0:e4d670b91a9a 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
screamer 0:e4d670b91a9a 16 * contributors may be used to endorse or promote products derived from this
screamer 0:e4d670b91a9a 17 * software without specific prior written permission.
screamer 0:e4d670b91a9a 18 *
screamer 0:e4d670b91a9a 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
screamer 0:e4d670b91a9a 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
screamer 0:e4d670b91a9a 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
screamer 0:e4d670b91a9a 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
screamer 0:e4d670b91a9a 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
screamer 0:e4d670b91a9a 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
screamer 0:e4d670b91a9a 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
screamer 0:e4d670b91a9a 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
screamer 0:e4d670b91a9a 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
screamer 0:e4d670b91a9a 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
screamer 0:e4d670b91a9a 29 */
screamer 0:e4d670b91a9a 30 #include "fsl_ftm_hal.h"
screamer 0:e4d670b91a9a 31
screamer 0:e4d670b91a9a 32 /*******************************************************************************
screamer 0:e4d670b91a9a 33 * Definitions
screamer 0:e4d670b91a9a 34 ******************************************************************************/
screamer 0:e4d670b91a9a 35 void FTM_HAL_Init(uint32_t ftmBaseAddr)
screamer 0:e4d670b91a9a 36 {
screamer 0:e4d670b91a9a 37
screamer 0:e4d670b91a9a 38 }
screamer 0:e4d670b91a9a 39
screamer 0:e4d670b91a9a 40 void FTM_HAL_EnablePwmMode(uint32_t ftmBaseAddr, ftm_pwm_param_t *config, uint8_t channel)
screamer 0:e4d670b91a9a 41 {
screamer 0:e4d670b91a9a 42 FTM_HAL_SetDualEdgeCaptureCmd(ftmBaseAddr, channel, false);
screamer 0:e4d670b91a9a 43 FTM_HAL_SetChnEdgeLevel(ftmBaseAddr, channel, config->edgeMode ? 1 : 2);
screamer 0:e4d670b91a9a 44 switch(config->mode)
screamer 0:e4d670b91a9a 45 {
screamer 0:e4d670b91a9a 46 case kFtmEdgeAlignedPWM:
screamer 0:e4d670b91a9a 47 FTM_HAL_SetDualChnCombineCmd(ftmBaseAddr, channel, false);
screamer 0:e4d670b91a9a 48 FTM_HAL_SetCpwms(ftmBaseAddr, 0);
screamer 0:e4d670b91a9a 49 FTM_HAL_SetChnMSnBAMode(ftmBaseAddr, channel, 2);
screamer 0:e4d670b91a9a 50 break;
screamer 0:e4d670b91a9a 51 case kFtmCenterAlignedPWM:
screamer 0:e4d670b91a9a 52 FTM_HAL_SetDualChnCombineCmd(ftmBaseAddr, channel, false);
screamer 0:e4d670b91a9a 53 FTM_HAL_SetCpwms(ftmBaseAddr, 1);
screamer 0:e4d670b91a9a 54 break;
screamer 0:e4d670b91a9a 55 case kFtmCombinedPWM:
screamer 0:e4d670b91a9a 56 FTM_HAL_SetCpwms(ftmBaseAddr, 0);
screamer 0:e4d670b91a9a 57 FTM_HAL_SetDualChnCombineCmd(ftmBaseAddr, channel, true);
screamer 0:e4d670b91a9a 58 break;
screamer 0:e4d670b91a9a 59 default:
screamer 0:e4d670b91a9a 60 assert(0);
screamer 0:e4d670b91a9a 61 break;
screamer 0:e4d670b91a9a 62 }
screamer 0:e4d670b91a9a 63 }
screamer 0:e4d670b91a9a 64
screamer 0:e4d670b91a9a 65 void FTM_HAL_DisablePwmMode(uint32_t ftmBaseAddr, ftm_pwm_param_t *config, uint8_t channel)
screamer 0:e4d670b91a9a 66 {
screamer 0:e4d670b91a9a 67
screamer 0:e4d670b91a9a 68 FTM_HAL_SetChnCountVal(ftmBaseAddr, channel, 0);
screamer 0:e4d670b91a9a 69 FTM_HAL_SetChnEdgeLevel(ftmBaseAddr, channel, 0);
screamer 0:e4d670b91a9a 70 FTM_HAL_SetChnMSnBAMode(ftmBaseAddr, channel, 0);
screamer 0:e4d670b91a9a 71 FTM_HAL_SetCpwms(ftmBaseAddr, 0);
screamer 0:e4d670b91a9a 72 FTM_HAL_SetDualChnCombineCmd(ftmBaseAddr, channel, false);
screamer 0:e4d670b91a9a 73 }
screamer 0:e4d670b91a9a 74
screamer 0:e4d670b91a9a 75 void FTM_HAL_Reset(uint32_t ftmBaseAddr, uint32_t instance)
screamer 0:e4d670b91a9a 76 {
screamer 0:e4d670b91a9a 77 uint8_t chan = FSL_FEATURE_FTM_CHANNEL_COUNTn(instance);
screamer 0:e4d670b91a9a 78
screamer 0:e4d670b91a9a 79 HW_FTM_SC_WR(ftmBaseAddr, 0);
screamer 0:e4d670b91a9a 80 HW_FTM_CNT_WR(ftmBaseAddr, 0);
screamer 0:e4d670b91a9a 81 HW_FTM_MOD_WR(ftmBaseAddr, 0);
screamer 0:e4d670b91a9a 82
screamer 0:e4d670b91a9a 83 for(int i = 0; i < chan; i++)
screamer 0:e4d670b91a9a 84 {
screamer 0:e4d670b91a9a 85 HW_FTM_CnSC_WR(ftmBaseAddr, i, 0);
screamer 0:e4d670b91a9a 86 HW_FTM_CnV_WR(ftmBaseAddr, i, 0);
screamer 0:e4d670b91a9a 87 }
screamer 0:e4d670b91a9a 88 HW_FTM_CNTIN_WR(ftmBaseAddr, 0);
screamer 0:e4d670b91a9a 89 HW_FTM_STATUS_WR(ftmBaseAddr, 0);
screamer 0:e4d670b91a9a 90 HW_FTM_MODE_WR(ftmBaseAddr, 0x00000004);
screamer 0:e4d670b91a9a 91 HW_FTM_SYNC_WR(ftmBaseAddr, 0);
screamer 0:e4d670b91a9a 92 HW_FTM_OUTINIT_WR(ftmBaseAddr, 0);
screamer 0:e4d670b91a9a 93 HW_FTM_OUTMASK_WR(ftmBaseAddr, 0);
screamer 0:e4d670b91a9a 94 HW_FTM_COMBINE_WR(ftmBaseAddr, 0);
screamer 0:e4d670b91a9a 95 HW_FTM_DEADTIME_WR(ftmBaseAddr, 0);
screamer 0:e4d670b91a9a 96 HW_FTM_EXTTRIG_WR(ftmBaseAddr, 0);
screamer 0:e4d670b91a9a 97 HW_FTM_POL_WR(ftmBaseAddr, 0);
screamer 0:e4d670b91a9a 98 HW_FTM_FMS_WR(ftmBaseAddr, 0);
screamer 0:e4d670b91a9a 99 HW_FTM_FILTER_WR(ftmBaseAddr, 0);
screamer 0:e4d670b91a9a 100 HW_FTM_FLTCTRL_WR(ftmBaseAddr, 0);
screamer 0:e4d670b91a9a 101 /*HW_FTM_QDCTRL_WR(instance, 0);*/
screamer 0:e4d670b91a9a 102 HW_FTM_CONF_WR(ftmBaseAddr, 0);
screamer 0:e4d670b91a9a 103 HW_FTM_FLTPOL_WR(ftmBaseAddr, 0);
screamer 0:e4d670b91a9a 104 HW_FTM_SYNCONF_WR(ftmBaseAddr, 0);
screamer 0:e4d670b91a9a 105 HW_FTM_INVCTRL_WR(ftmBaseAddr, 0);
screamer 0:e4d670b91a9a 106 HW_FTM_SWOCTRL_WR(ftmBaseAddr, 0);
screamer 0:e4d670b91a9a 107 HW_FTM_PWMLOAD_WR(ftmBaseAddr, 0);
screamer 0:e4d670b91a9a 108 }
screamer 0:e4d670b91a9a 109
screamer 0:e4d670b91a9a 110 void FTM_HAL_SetHardwareTriggerCmd(uint32_t ftmBaseAddr, uint8_t trigger_num, bool enable)
screamer 0:e4d670b91a9a 111 {
screamer 0:e4d670b91a9a 112 switch(trigger_num)
screamer 0:e4d670b91a9a 113 {
screamer 0:e4d670b91a9a 114 case 0:
screamer 0:e4d670b91a9a 115 BW_FTM_SYNC_TRIG0(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 116 break;
screamer 0:e4d670b91a9a 117 case 1:
screamer 0:e4d670b91a9a 118 BW_FTM_SYNC_TRIG1(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 119 break;
screamer 0:e4d670b91a9a 120 case 2:
screamer 0:e4d670b91a9a 121 BW_FTM_SYNC_TRIG2(ftmBaseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 122 break;
screamer 0:e4d670b91a9a 123 default:
screamer 0:e4d670b91a9a 124 assert(0);
screamer 0:e4d670b91a9a 125 break;
screamer 0:e4d670b91a9a 126 }
screamer 0:e4d670b91a9a 127 }
screamer 0:e4d670b91a9a 128
screamer 0:e4d670b91a9a 129 void FTM_HAL_SetChnTriggerCmd(uint32_t ftmBaseAddr, uint8_t channel, bool val)
screamer 0:e4d670b91a9a 130 {
screamer 0:e4d670b91a9a 131 assert(channel < HW_CHAN6);
screamer 0:e4d670b91a9a 132
screamer 0:e4d670b91a9a 133 uint8_t bit = val ? 1 : 0;
screamer 0:e4d670b91a9a 134 uint32_t value = (channel > 1U) ? (uint8_t)(bit << (channel - 2U)) : (uint8_t)(bit << (channel + 4U));
screamer 0:e4d670b91a9a 135
screamer 0:e4d670b91a9a 136 val ? HW_FTM_EXTTRIG_SET(ftmBaseAddr, value) : HW_FTM_EXTTRIG_CLR(ftmBaseAddr, value);
screamer 0:e4d670b91a9a 137 }
screamer 0:e4d670b91a9a 138
screamer 0:e4d670b91a9a 139 void FTM_HAL_SetChnInputCaptureFilter(uint32_t ftmBaseAddr, uint8_t channel, uint8_t val)
screamer 0:e4d670b91a9a 140 {
screamer 0:e4d670b91a9a 141 assert(channel < HW_CHAN4);
screamer 0:e4d670b91a9a 142
screamer 0:e4d670b91a9a 143 switch(channel)
screamer 0:e4d670b91a9a 144 {
screamer 0:e4d670b91a9a 145 case HW_CHAN0:
screamer 0:e4d670b91a9a 146 BW_FTM_FILTER_CH0FVAL(ftmBaseAddr, val);
screamer 0:e4d670b91a9a 147 break;
screamer 0:e4d670b91a9a 148 case HW_CHAN1:
screamer 0:e4d670b91a9a 149 BW_FTM_FILTER_CH1FVAL(ftmBaseAddr, val);
screamer 0:e4d670b91a9a 150 break;
screamer 0:e4d670b91a9a 151 case HW_CHAN2:
screamer 0:e4d670b91a9a 152 BW_FTM_FILTER_CH2FVAL(ftmBaseAddr, val);
screamer 0:e4d670b91a9a 153 break;
screamer 0:e4d670b91a9a 154 case HW_CHAN3:
screamer 0:e4d670b91a9a 155 BW_FTM_FILTER_CH3FVAL(ftmBaseAddr, val);
screamer 0:e4d670b91a9a 156 break;
screamer 0:e4d670b91a9a 157 default:
screamer 0:e4d670b91a9a 158 assert(0);
screamer 0:e4d670b91a9a 159 break;
screamer 0:e4d670b91a9a 160 }
screamer 0:e4d670b91a9a 161 }
screamer 0:e4d670b91a9a 162
screamer 0:e4d670b91a9a 163 uint32_t FTM_HAL_GetChnPairIndex(uint8_t channel)
screamer 0:e4d670b91a9a 164 {
screamer 0:e4d670b91a9a 165 if((channel == HW_CHAN0) || (channel == HW_CHAN1))
screamer 0:e4d670b91a9a 166 {
screamer 0:e4d670b91a9a 167 return 0;
screamer 0:e4d670b91a9a 168 }
screamer 0:e4d670b91a9a 169 else if((channel == HW_CHAN2) || (channel == HW_CHAN3))
screamer 0:e4d670b91a9a 170 {
screamer 0:e4d670b91a9a 171 return 1;
screamer 0:e4d670b91a9a 172 }
screamer 0:e4d670b91a9a 173 else if((channel == HW_CHAN4) || (channel == HW_CHAN5))
screamer 0:e4d670b91a9a 174 {
screamer 0:e4d670b91a9a 175 return 2;
screamer 0:e4d670b91a9a 176 }
screamer 0:e4d670b91a9a 177 else
screamer 0:e4d670b91a9a 178 {
screamer 0:e4d670b91a9a 179 return 3;
screamer 0:e4d670b91a9a 180 }
screamer 0:e4d670b91a9a 181 }
screamer 0:e4d670b91a9a 182
screamer 0:e4d670b91a9a 183 /*******************************************************************************
screamer 0:e4d670b91a9a 184 * EOF
screamer 0:e4d670b91a9a 185 ******************************************************************************/
screamer 0:e4d670b91a9a 186