Alessandro Angelino / target-freescale-ksdk

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Fork of target-freescale-ksdk by Morpheus

TARGET_KPSDK_CODE/hal/mcg/fsl_mcg_hal.h@1:d01108809007, 2016-04-04 (annotated)

Committer:
Alessandro Angelino
Date:
Mon Apr 04 14:18:16 2016 +0100
Revision:
1:d01108809007
Parent:
0:e4d670b91a9a 
Replace NVIC APIs with vIRQ ones

Who changed what in which revision?

UserRevisionLine numberNew contents of line
screamer 0:e4d670b91a9a 1 /*
screamer 0:e4d670b91a9a 2 * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
screamer 0:e4d670b91a9a 3 * All rights reserved.
screamer 0:e4d670b91a9a 4 *
screamer 0:e4d670b91a9a 5 * Redistribution and use in source and binary forms, with or without modification,
screamer 0:e4d670b91a9a 6 * are permitted provided that the following conditions are met:
screamer 0:e4d670b91a9a 7 *
screamer 0:e4d670b91a9a 8 * o Redistributions of source code must retain the above copyright notice, this list
screamer 0:e4d670b91a9a 9 * of conditions and the following disclaimer.
screamer 0:e4d670b91a9a 10 *
screamer 0:e4d670b91a9a 11 * o Redistributions in binary form must reproduce the above copyright notice, this
screamer 0:e4d670b91a9a 12 * list of conditions and the following disclaimer in the documentation and/or
screamer 0:e4d670b91a9a 13 * other materials provided with the distribution.
screamer 0:e4d670b91a9a 14 *
screamer 0:e4d670b91a9a 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
screamer 0:e4d670b91a9a 16 * contributors may be used to endorse or promote products derived from this
screamer 0:e4d670b91a9a 17 * software without specific prior written permission.
screamer 0:e4d670b91a9a 18 *
screamer 0:e4d670b91a9a 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
screamer 0:e4d670b91a9a 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
screamer 0:e4d670b91a9a 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
screamer 0:e4d670b91a9a 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
screamer 0:e4d670b91a9a 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
screamer 0:e4d670b91a9a 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
screamer 0:e4d670b91a9a 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
screamer 0:e4d670b91a9a 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
screamer 0:e4d670b91a9a 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
screamer 0:e4d670b91a9a 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
screamer 0:e4d670b91a9a 29 */
screamer 0:e4d670b91a9a 30
screamer 0:e4d670b91a9a 31 #if !defined(__FSL_MCG_HAL_H__)
screamer 0:e4d670b91a9a 32 #define __FSL_MCG_HAL_H__
screamer 0:e4d670b91a9a 33
screamer 0:e4d670b91a9a 34 #include <stdint.h>
screamer 0:e4d670b91a9a 35 #include <stdbool.h>
screamer 0:e4d670b91a9a 36 #include <assert.h>
screamer 0:e4d670b91a9a 37 #include "fsl_device_registers.h"
screamer 0:e4d670b91a9a 38 #include "fsl_mcg_features.h"
screamer 0:e4d670b91a9a 39
screamer 0:e4d670b91a9a 40 /*! @addtogroup mcg_hal*/
screamer 0:e4d670b91a9a 41 /*! @{*/
screamer 0:e4d670b91a9a 42
screamer 0:e4d670b91a9a 43 /*! @file fsl_mcg_hal.h */
screamer 0:e4d670b91a9a 44
screamer 0:e4d670b91a9a 45 /*******************************************************************************
screamer 0:e4d670b91a9a 46 * Definitions
screamer 0:e4d670b91a9a 47 ******************************************************************************/
screamer 0:e4d670b91a9a 48 /*! @brief MCG constant definitions*/
screamer 0:e4d670b91a9a 49 enum _mcg_constant
screamer 0:e4d670b91a9a 50 {
screamer 0:e4d670b91a9a 51 kMcgConstant0 = (0u),
screamer 0:e4d670b91a9a 52 kMcgConstant1 = (1u),
screamer 0:e4d670b91a9a 53 kMcgConstant2 = (2u),
screamer 0:e4d670b91a9a 54 kMcgConstant3 = (3u),
screamer 0:e4d670b91a9a 55 kMcgConstant4 = (4u),
screamer 0:e4d670b91a9a 56 kMcgConstant5 = (5u),
screamer 0:e4d670b91a9a 57 kMcgConstant32 = (32u),
screamer 0:e4d670b91a9a 58
screamer 0:e4d670b91a9a 59 kMcgConstant640 = (640u),
screamer 0:e4d670b91a9a 60 kMcgConstant1280 = (1280u),
screamer 0:e4d670b91a9a 61 kMcgConstant1920 = (1920u),
screamer 0:e4d670b91a9a 62 kMcgConstant2560 = (2560u),
screamer 0:e4d670b91a9a 63 kMcgConstant732 = (732u),
screamer 0:e4d670b91a9a 64 kMcgConstant1464 = (1464u),
screamer 0:e4d670b91a9a 65 kMcgConstant2197 = (2197u),
screamer 0:e4d670b91a9a 66 kMcgConstant2929 = (2929u),
screamer 0:e4d670b91a9a 67
screamer 0:e4d670b91a9a 68 kMcgConstantHex20 = (0x20u),
screamer 0:e4d670b91a9a 69 kMcgConstantHex40 = (0x40u),
screamer 0:e4d670b91a9a 70 kMcgConstantHex60 = (0x60u),
screamer 0:e4d670b91a9a 71 kMcgConstantHex80 = (0x80u),
screamer 0:e4d670b91a9a 72 kMcgConstantHexA0 = (0xA0u),
screamer 0:e4d670b91a9a 73 kMcgConstantHexC0 = (0xC0u),
screamer 0:e4d670b91a9a 74 kMcgConstantHexE0 = (0xE0u),
screamer 0:e4d670b91a9a 75
screamer 0:e4d670b91a9a 76 kMcgConstant2000 = (2000u),
screamer 0:e4d670b91a9a 77 kMcgConstant3000 = (3000u),
screamer 0:e4d670b91a9a 78 kMcgConstant4000 = (4000u),
screamer 0:e4d670b91a9a 79
screamer 0:e4d670b91a9a 80 kMcgConstant10000 = (10000u),
screamer 0:e4d670b91a9a 81 kMcgConstant30000 = (30000u),
screamer 0:e4d670b91a9a 82 kMcgConstant31250 = (31250u),
screamer 0:e4d670b91a9a 83 kMcgConstant39063 = (39063u),
screamer 0:e4d670b91a9a 84 kMcgConstant40000 = (40000u),
screamer 0:e4d670b91a9a 85
screamer 0:e4d670b91a9a 86 kMcgConstant1250000 = (1250000u),
screamer 0:e4d670b91a9a 87 kMcgConstant2500000 = (2500000u),
screamer 0:e4d670b91a9a 88 kMcgConstant3000000 = (3000000u),
screamer 0:e4d670b91a9a 89 kMcgConstant5000000 = (5000000u),
screamer 0:e4d670b91a9a 90 kMcgConstant8000000 = (8000000u),
screamer 0:e4d670b91a9a 91
screamer 0:e4d670b91a9a 92 kMcgConstant10000000 = (10000000u),
screamer 0:e4d670b91a9a 93 kMcgConstant20000000 = (20000000u),
screamer 0:e4d670b91a9a 94 kMcgConstant25000000 = (25000000u),
screamer 0:e4d670b91a9a 95 kMcgConstant32000000 = (32000000u),
screamer 0:e4d670b91a9a 96 kMcgConstant40000000 = (40000000u),
screamer 0:e4d670b91a9a 97 kMcgConstant50000000 = (50000000u),
screamer 0:e4d670b91a9a 98 kMcgConstant60000000 = (60000000u),
screamer 0:e4d670b91a9a 99 kMcgConstant75000000 = (75000000u),
screamer 0:e4d670b91a9a 100 kMcgConstant80000000 = (80000000u),
screamer 0:e4d670b91a9a 101
screamer 0:e4d670b91a9a 102 kMcgConstant100000000 = (100000000u),
screamer 0:e4d670b91a9a 103 kMcgConstant180000000 = (180000000u),
screamer 0:e4d670b91a9a 104 kMcgConstant360000000 = (360000000u)
screamer 0:e4d670b91a9a 105 };
screamer 0:e4d670b91a9a 106
screamer 0:e4d670b91a9a 107 /*! @brief MCG clock source select */
screamer 0:e4d670b91a9a 108 typedef enum _mcg_clock_select
screamer 0:e4d670b91a9a 109 {
screamer 0:e4d670b91a9a 110 kMcgClkSelOut, /* Output of FLL or PLLCS is selected(depends on PLLS bit) */
screamer 0:e4d670b91a9a 111 kMcgClkSelInternal, /* Internal reference clock is selected */
screamer 0:e4d670b91a9a 112 kMcgClkSelExternal, /* External reference clock is selected */
screamer 0:e4d670b91a9a 113 kMcgClkSelReserved
screamer 0:e4d670b91a9a 114 } mcg_clock_select_t;
screamer 0:e4d670b91a9a 115
screamer 0:e4d670b91a9a 116 /*! @brief MCG internal reference clock source select */
screamer 0:e4d670b91a9a 117 typedef enum _mcg_internal_ref_clock_source
screamer 0:e4d670b91a9a 118 {
screamer 0:e4d670b91a9a 119 kMcgInternalRefClkSrcExternal, /* External reference clock is selected */
screamer 0:e4d670b91a9a 120 kMcgInternalRefClkSrcSlow /* The slow internal reference clock is selected */
screamer 0:e4d670b91a9a 121 } mcg_internal_ref_clock_source_t;
screamer 0:e4d670b91a9a 122
screamer 0:e4d670b91a9a 123 /*! @brief MCG frequency range select */
screamer 0:e4d670b91a9a 124 typedef enum _mcg_freq_range_select
screamer 0:e4d670b91a9a 125 {
screamer 0:e4d670b91a9a 126 kMcgFreqRangeSelLow, /* Low frequency range selected for the crystal OSC */
screamer 0:e4d670b91a9a 127 kMcgFreqRangeSelHigh, /* High frequency range selected for the crystal OSC */
screamer 0:e4d670b91a9a 128 kMcgFreqRangeSelVeryHigh, /* Very High frequency range selected for the crystal OSC */
screamer 0:e4d670b91a9a 129 kMcgFreqRangeSelVeryHigh1 /* Very High frequency range selected for the crystal OSC */
screamer 0:e4d670b91a9a 130 } mcg_freq_range_select_t;
screamer 0:e4d670b91a9a 131
screamer 0:e4d670b91a9a 132 /*! @brief MCG high gain oscillator select */
screamer 0:e4d670b91a9a 133 typedef enum _mcg_high_gain_osc_select
screamer 0:e4d670b91a9a 134 {
screamer 0:e4d670b91a9a 135 kMcgHighGainOscSelLow, /* Configure crystal oscillator for low-power operation */
screamer 0:e4d670b91a9a 136 kMcgHighGainOscSelHigh /* Configure crystal oscillator for high-gain operation */
screamer 0:e4d670b91a9a 137 } mcg_high_gain_osc_select_t;
screamer 0:e4d670b91a9a 138
screamer 0:e4d670b91a9a 139 /*! @brief MCG high gain oscillator select */
screamer 0:e4d670b91a9a 140 typedef enum _mcg_external_ref_clock_select
screamer 0:e4d670b91a9a 141 {
screamer 0:e4d670b91a9a 142 kMcgExternalRefClkSelExternal, /* External reference clock requested */
screamer 0:e4d670b91a9a 143 kMcgExternalRefClkSelOsc /* Oscillator requested */
screamer 0:e4d670b91a9a 144 } mcg_external_ref_clock_select_t;
screamer 0:e4d670b91a9a 145
screamer 0:e4d670b91a9a 146 /*! @brief MCG low power select */
screamer 0:e4d670b91a9a 147 typedef enum _mcg_low_power_select
screamer 0:e4d670b91a9a 148 {
screamer 0:e4d670b91a9a 149 kMcgLowPowerSelNormal, /* FLL (or PLL) is not disabled in bypass modes */
screamer 0:e4d670b91a9a 150 kMcgLowPowerSelLowPower /* FLL (or PLL) is disabled in bypass modes (lower power) */
screamer 0:e4d670b91a9a 151 } mcg_low_power_select_t;
screamer 0:e4d670b91a9a 152
screamer 0:e4d670b91a9a 153 /*! @brief MCG internal reference clock select */
screamer 0:e4d670b91a9a 154 typedef enum _mcg_internal_ref_clock_select
screamer 0:e4d670b91a9a 155 {
screamer 0:e4d670b91a9a 156 kMcgInternalRefClkSelSlow, /* Slow internal reference clock selected */
screamer 0:e4d670b91a9a 157 kMcgInternalRefClkSelFast /* Fast internal reference clock selected */
screamer 0:e4d670b91a9a 158 } mcg_internal_ref_clock_select_t;
screamer 0:e4d670b91a9a 159
screamer 0:e4d670b91a9a 160 /*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */
screamer 0:e4d670b91a9a 161 typedef enum _mcg_dmx32_select
screamer 0:e4d670b91a9a 162 {
screamer 0:e4d670b91a9a 163 kMcgDmx32Default, /* DCO has a default range of 25% */
screamer 0:e4d670b91a9a 164 kMcgDmx32Fine /* DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
screamer 0:e4d670b91a9a 165 } mcg_dmx32_select_t;
screamer 0:e4d670b91a9a 166
screamer 0:e4d670b91a9a 167 /*! @brief MCG DCO range select */
screamer 0:e4d670b91a9a 168 typedef enum _mcg_digital_controlled_osc_range_select
screamer 0:e4d670b91a9a 169 {
screamer 0:e4d670b91a9a 170 kMcgDigitalControlledOscRangeSelLow, /* Low frequency range */
screamer 0:e4d670b91a9a 171 kMcgDigitalControlledOscRangeSelMid, /* Mid frequency range*/
screamer 0:e4d670b91a9a 172 kMcgDigitalControlledOscRangeSelMidHigh, /* Mid-High frequency range */
screamer 0:e4d670b91a9a 173 kMcgDigitalControlledOscRangeSelHigh /* High frequency range */
screamer 0:e4d670b91a9a 174 } mcg_digital_controlled_osc_range_select_t;
screamer 0:e4d670b91a9a 175
screamer 0:e4d670b91a9a 176 /*! @brief MCG PLL external reference clock select */
screamer 0:e4d670b91a9a 177 typedef enum _mcg_pll_external_ref_clk_select
screamer 0:e4d670b91a9a 178 {
screamer 0:e4d670b91a9a 179 kMcgPllExternalRefClkSelOsc0, /* Selects OSC0 clock source as its external reference clock */
screamer 0:e4d670b91a9a 180 kMcgPllExternalRefClkSelOsc1 /* Selects OSC1 clock source as its external reference clock */
screamer 0:e4d670b91a9a 181 } mcg_pll_external_ref_clk_select_t;
screamer 0:e4d670b91a9a 182
screamer 0:e4d670b91a9a 183 /*! @brief MCG PLL select */
screamer 0:e4d670b91a9a 184 typedef enum _mcg_pll_select
screamer 0:e4d670b91a9a 185 {
screamer 0:e4d670b91a9a 186 kMcgPllSelFll, /* FLL is selected */
screamer 0:e4d670b91a9a 187 kMcgPllSelPllClkSel /* PLLCS output clock is selected */
screamer 0:e4d670b91a9a 188 } mcg_pll_select_t;
screamer 0:e4d670b91a9a 189
screamer 0:e4d670b91a9a 190 /*! @brief MCG loss of lock status */
screamer 0:e4d670b91a9a 191 typedef enum _mcg_loss_of_lock_status
screamer 0:e4d670b91a9a 192 {
screamer 0:e4d670b91a9a 193 kMcgLossOfLockNotLost, /* PLL has not lost lock since LOLS 0 was last cleared */
screamer 0:e4d670b91a9a 194 kMcgLossOfLockLost /* PLL has lost lock since LOLS 0 was last cleared */
screamer 0:e4d670b91a9a 195 } mcg_loss_of_lock_status_t;
screamer 0:e4d670b91a9a 196
screamer 0:e4d670b91a9a 197 /*! @brief MCG lock status */
screamer 0:e4d670b91a9a 198 typedef enum _mcg_lock_status
screamer 0:e4d670b91a9a 199 {
screamer 0:e4d670b91a9a 200 kMcgLockUnlocked, /* PLL is currently unlocked */
screamer 0:e4d670b91a9a 201 kMcgLockLocked /* PLL is currently locked */
screamer 0:e4d670b91a9a 202 } mcg_lock_status_t;
screamer 0:e4d670b91a9a 203
screamer 0:e4d670b91a9a 204 /*! @brief MCG clock status */
screamer 0:e4d670b91a9a 205 typedef enum _mcg_pll_stat_status
screamer 0:e4d670b91a9a 206 {
screamer 0:e4d670b91a9a 207 kMcgPllStatFll, /* Source of PLLS clock is FLL clock */
screamer 0:e4d670b91a9a 208 kMcgPllStatPllClkSel /* Source of PLLS clock is PLLCS output clock */
screamer 0:e4d670b91a9a 209 } mcg_pll_stat_status_t;
screamer 0:e4d670b91a9a 210
screamer 0:e4d670b91a9a 211 /*! @brief MCG iref status */
screamer 0:e4d670b91a9a 212 typedef enum _mcg_internal_ref_status
screamer 0:e4d670b91a9a 213 {
screamer 0:e4d670b91a9a 214 kMcgInternalRefStatExternal, /* FLL reference clock is the external reference clock */
screamer 0:e4d670b91a9a 215 kMcgInternalRefStatInternal /* FLL reference clock is the internal reference clock */
screamer 0:e4d670b91a9a 216 } mcg_internal_ref_status_t;
screamer 0:e4d670b91a9a 217
screamer 0:e4d670b91a9a 218 /*! @brief MCG clock mode status */
screamer 0:e4d670b91a9a 219 typedef enum _mcg_clk_stat_status
screamer 0:e4d670b91a9a 220 {
screamer 0:e4d670b91a9a 221 kMcgClkStatFll, /* Output of the FLL is selected (reset default) */
screamer 0:e4d670b91a9a 222 kMcgClkStatInternalRef, /* Internal reference clock is selected */
screamer 0:e4d670b91a9a 223 kMcgClkStatExternalRef, /* External reference clock is selected */
screamer 0:e4d670b91a9a 224 kMcgClkStatPll /* Output of the PLL is selected */
screamer 0:e4d670b91a9a 225 } mcg_clk_stat_status_t;
screamer 0:e4d670b91a9a 226
screamer 0:e4d670b91a9a 227 /*! @brief MCG ircst status */
screamer 0:e4d670b91a9a 228 typedef enum _mcg_internal_ref_clk_status
screamer 0:e4d670b91a9a 229 {
screamer 0:e4d670b91a9a 230 kMcgInternalRefClkStatSlow, /* internal reference clock is the slow clock (32 kHz IRC) */
screamer 0:e4d670b91a9a 231 kMcgInternalRefClkStatFast /* internal reference clock is the fast clock (2 MHz IRC) */
screamer 0:e4d670b91a9a 232 } mcg_internal_ref_clk_status_t;
screamer 0:e4d670b91a9a 233
screamer 0:e4d670b91a9a 234 /*! @brief MCG auto trim fail status */
screamer 0:e4d670b91a9a 235 typedef enum _mcg_auto_trim_machine_fail_status
screamer 0:e4d670b91a9a 236 {
screamer 0:e4d670b91a9a 237 kMcgAutoTrimMachineNormal, /* Automatic Trim Machine completed normally */
screamer 0:e4d670b91a9a 238 kMcgAutoTrimMachineFail /* Automatic Trim Machine failed */
screamer 0:e4d670b91a9a 239 } mcg_auto_trim_machine_fail_status_t;
screamer 0:e4d670b91a9a 240
screamer 0:e4d670b91a9a 241 /*! @brief MCG loss of clock status */
screamer 0:e4d670b91a9a 242 typedef enum _mcg_locs0_status
screamer 0:e4d670b91a9a 243 {
screamer 0:e4d670b91a9a 244 kMcgLocs0NotOccured, /* Loss of OSC0 has not occurred */
screamer 0:e4d670b91a9a 245 kMcgLocs0Occured /* Loss of OSC0 has occurred */
screamer 0:e4d670b91a9a 246 } mcg_locs0_status_t;
screamer 0:e4d670b91a9a 247
screamer 0:e4d670b91a9a 248 /*! @brief MCG Automatic Trim Machine Select */
screamer 0:e4d670b91a9a 249 typedef enum _mcg_auto_trim_machine_select
screamer 0:e4d670b91a9a 250 {
screamer 0:e4d670b91a9a 251 kMcgAutoTrimMachineSel32k, /* 32 kHz Internal Reference Clock selected */
screamer 0:e4d670b91a9a 252 kMcgAutoTrimMachineSel4m /* 4 MHz Internal Reference Clock selected */
screamer 0:e4d670b91a9a 253 } mcg_auto_trim_machine_select_t;
screamer 0:e4d670b91a9a 254
screamer 0:e4d670b91a9a 255 /*! @brief MCG OSC Clock Select */
screamer 0:e4d670b91a9a 256 typedef enum _mcg_oscsel_select
screamer 0:e4d670b91a9a 257 {
screamer 0:e4d670b91a9a 258 kMcgOscselOsc, /* Selects System Oscillator (OSCCLK) */
screamer 0:e4d670b91a9a 259 kMcgOscselRtc, /* Selects 32 kHz RTC Oscillator */
screamer 0:e4d670b91a9a 260 #if FSL_FEATURE_MCG_HAS_IRC_48M
screamer 0:e4d670b91a9a 261 kMcgOscselIrc /* Selects 48 MHz IRC Oscillator */
screamer 0:e4d670b91a9a 262 #endif
screamer 0:e4d670b91a9a 263 } mcg_oscsel_select_t;
screamer 0:e4d670b91a9a 264
screamer 0:e4d670b91a9a 265 /*! @brief MCG loss of clock status */
screamer 0:e4d670b91a9a 266 typedef enum _mcg_loss_of_clk1_status
screamer 0:e4d670b91a9a 267 {
screamer 0:e4d670b91a9a 268 kMcgLossOfClk1NotOccured, /* Loss of RTC has not occurred */
screamer 0:e4d670b91a9a 269 kMcgLossOfClk1Occured /* Loss of RTC has occurred */
screamer 0:e4d670b91a9a 270 } mcg_loss_of_clk1_status_t;
screamer 0:e4d670b91a9a 271
screamer 0:e4d670b91a9a 272 /*! @brief MCG PLLCS select */
screamer 0:e4d670b91a9a 273 typedef enum _mcg_pll_clk_select
screamer 0:e4d670b91a9a 274 {
screamer 0:e4d670b91a9a 275 kMcgPllClkSelPll0, /* PLL0 output clock is selected */
screamer 0:e4d670b91a9a 276 kMcgPllClkSelPll1, /* PLL1 output clock is selected */
screamer 0:e4d670b91a9a 277 } mcg_pll_clk_select_t;
screamer 0:e4d670b91a9a 278
screamer 0:e4d670b91a9a 279 /*! @brief MCG loss of clock status */
screamer 0:e4d670b91a9a 280 typedef enum _mcg_locs2_status
screamer 0:e4d670b91a9a 281 {
screamer 0:e4d670b91a9a 282 kMcgLocs2NotOccured, /* Loss of OSC1 has not occurred */
screamer 0:e4d670b91a9a 283 kMcgLocs2Occured /* Loss of OSC1 has occurred */
screamer 0:e4d670b91a9a 284 } mcg_locs2_status_t;
screamer 0:e4d670b91a9a 285
screamer 0:e4d670b91a9a 286 /*******************************************************************************
screamer 0:e4d670b91a9a 287 * API
screamer 0:e4d670b91a9a 288 ******************************************************************************/
screamer 0:e4d670b91a9a 289
screamer 0:e4d670b91a9a 290 #if defined(__cplusplus)
screamer 0:e4d670b91a9a 291 extern "C" {
screamer 0:e4d670b91a9a 292 #endif /* __cplusplus*/
screamer 0:e4d670b91a9a 293
screamer 0:e4d670b91a9a 294 /*! @name MCG out clock access API*/
screamer 0:e4d670b91a9a 295 /*@{*/
screamer 0:e4d670b91a9a 296
screamer 0:e4d670b91a9a 297 /*!
screamer 0:e4d670b91a9a 298 * @brief Gets the current MCG FLL clock.
screamer 0:e4d670b91a9a 299 *
screamer 0:e4d670b91a9a 300 * This function returns the mcgfllclk value in frequency(Hertz) based on the
screamer 0:e4d670b91a9a 301 * current MCG configurations and settings. FLL should be properly configured
screamer 0:e4d670b91a9a 302 * in order to get the valid value.
screamer 0:e4d670b91a9a 303 *
screamer 0:e4d670b91a9a 304 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 305 * @return value Frequency value in Hertz of the mcgpllclk.
screamer 0:e4d670b91a9a 306 */
screamer 0:e4d670b91a9a 307 uint32_t CLOCK_HAL_GetFllRefClk(uint32_t baseAddr);
screamer 0:e4d670b91a9a 308
screamer 0:e4d670b91a9a 309 /*!
screamer 0:e4d670b91a9a 310 * @brief Gets the current MCG FLL clock.
screamer 0:e4d670b91a9a 311 *
screamer 0:e4d670b91a9a 312 * This function returns the mcgfllclk value in frequency(Hertz) based on the
screamer 0:e4d670b91a9a 313 * current MCG configurations and settings. FLL should be properly configured
screamer 0:e4d670b91a9a 314 * in order to get the valid value.
screamer 0:e4d670b91a9a 315 *
screamer 0:e4d670b91a9a 316 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 317 * @return value Frequency value in Hertz of the mcgpllclk.
screamer 0:e4d670b91a9a 318 */
screamer 0:e4d670b91a9a 319 uint32_t CLOCK_HAL_GetFllClk(uint32_t baseAddr);
screamer 0:e4d670b91a9a 320
screamer 0:e4d670b91a9a 321 /*!
screamer 0:e4d670b91a9a 322 * @brief Gets the current MCG PLL/PLL0 clock.
screamer 0:e4d670b91a9a 323 *
screamer 0:e4d670b91a9a 324 * This function returns the mcgpllclk/mcgpll0 value in frequency(Hertz) based
screamer 0:e4d670b91a9a 325 * on the current MCG configurations and settings. PLL/PLL0 should be properly
screamer 0:e4d670b91a9a 326 * configured in order to get the valid value.
screamer 0:e4d670b91a9a 327 *
screamer 0:e4d670b91a9a 328 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 329 * @return value Frequency value in Hertz of the mcgpllclk or the mcgpll0clk.
screamer 0:e4d670b91a9a 330 */
screamer 0:e4d670b91a9a 331 uint32_t CLOCK_HAL_GetPll0Clk(uint32_t baseAddr);
screamer 0:e4d670b91a9a 332
screamer 0:e4d670b91a9a 333 #if FSL_FEATURE_MCG_HAS_PLL1
screamer 0:e4d670b91a9a 334 /*!
screamer 0:e4d670b91a9a 335 * @brief Gets the current MCG PLL1 clock.
screamer 0:e4d670b91a9a 336 *
screamer 0:e4d670b91a9a 337 * This function returns the mcgpll1clk value in frequency (Hertz) based
screamer 0:e4d670b91a9a 338 * on the current MCG configurations and settings. PLL1 should be properly configured
screamer 0:e4d670b91a9a 339 * in order to get the valid value.
screamer 0:e4d670b91a9a 340 *
screamer 0:e4d670b91a9a 341 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 342 * @return value Frequency value in Hertz of mcgpll1clk.
screamer 0:e4d670b91a9a 343 */
screamer 0:e4d670b91a9a 344 uint32_t CLOCK_HAL_GetPll1Clk(uint32_t baseAddr);
screamer 0:e4d670b91a9a 345 #endif
screamer 0:e4d670b91a9a 346
screamer 0:e4d670b91a9a 347 /*!
screamer 0:e4d670b91a9a 348 * @brief Gets the current MCG IR clock.
screamer 0:e4d670b91a9a 349 *
screamer 0:e4d670b91a9a 350 * This function returns the mcgirclk value in frequency (Hertz) based
screamer 0:e4d670b91a9a 351 * on the current MCG configurations and settings. It does not check if the
screamer 0:e4d670b91a9a 352 * mcgirclk is enabled or not, just calculate and return the value.
screamer 0:e4d670b91a9a 353 *
screamer 0:e4d670b91a9a 354 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 355 * @return value Frequency value in Hertz of the mcgirclk.
screamer 0:e4d670b91a9a 356 */
screamer 0:e4d670b91a9a 357 uint32_t CLOCK_HAL_GetInternalRefClk(uint32_t baseAddr);
screamer 0:e4d670b91a9a 358
screamer 0:e4d670b91a9a 359 /*!
screamer 0:e4d670b91a9a 360 * @brief Gets the current MCG out clock.
screamer 0:e4d670b91a9a 361 *
screamer 0:e4d670b91a9a 362 * This function returns the mcgoutclk value in frequency (Hertz) based on the
screamer 0:e4d670b91a9a 363 * current MCG configurations and settings. The configuration should be
screamer 0:e4d670b91a9a 364 * properly done in order to get the valid value.
screamer 0:e4d670b91a9a 365 *
screamer 0:e4d670b91a9a 366 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 367 * @return value Frequency value in Hertz of mcgoutclk.
screamer 0:e4d670b91a9a 368 */
screamer 0:e4d670b91a9a 369 uint32_t CLOCK_HAL_GetOutClk(uint32_t baseAddr);
screamer 0:e4d670b91a9a 370
screamer 0:e4d670b91a9a 371 /*@}*/
screamer 0:e4d670b91a9a 372
screamer 0:e4d670b91a9a 373 /*! @name MCG control register access API*/
screamer 0:e4d670b91a9a 374 /*@{*/
screamer 0:e4d670b91a9a 375
screamer 0:e4d670b91a9a 376 /*!
screamer 0:e4d670b91a9a 377 * @brief Sets the Clock Source Select
screamer 0:e4d670b91a9a 378 *
screamer 0:e4d670b91a9a 379 * This function selects the clock source for the MCGOUTCLK.
screamer 0:e4d670b91a9a 380 *
screamer 0:e4d670b91a9a 381 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 382 * @param select Clock source selection
screamer 0:e4d670b91a9a 383 * - 00: Output of FLL or PLLCS is selected(depends on PLLS control bit)
screamer 0:e4d670b91a9a 384 * - 01: Internal reference clock is selected.
screamer 0:e4d670b91a9a 385 * - 10: External reference clock is selected.
screamer 0:e4d670b91a9a 386 * - 11: Reserved.
screamer 0:e4d670b91a9a 387 */
screamer 0:e4d670b91a9a 388 static inline void CLOCK_HAL_SetClkSrcMode(uint32_t baseAddr, mcg_clock_select_t select)
screamer 0:e4d670b91a9a 389 {
screamer 0:e4d670b91a9a 390 BW_MCG_C1_CLKS(baseAddr, select);
screamer 0:e4d670b91a9a 391 }
screamer 0:e4d670b91a9a 392
screamer 0:e4d670b91a9a 393 /*!
screamer 0:e4d670b91a9a 394 * @brief Gets the Clock Source Select.
screamer 0:e4d670b91a9a 395 *
screamer 0:e4d670b91a9a 396 * This function gets the select of the clock source for the MCGOUTCLK.
screamer 0:e4d670b91a9a 397 *
screamer 0:e4d670b91a9a 398 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 399 * @return select Clock source selection
screamer 0:e4d670b91a9a 400 */
screamer 0:e4d670b91a9a 401 static inline mcg_clock_select_t CLOCK_HAL_GetClkSrcMode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 402 {
screamer 0:e4d670b91a9a 403 return (mcg_clock_select_t)BR_MCG_C1_CLKS(baseAddr);
screamer 0:e4d670b91a9a 404 }
screamer 0:e4d670b91a9a 405
screamer 0:e4d670b91a9a 406 /*!
screamer 0:e4d670b91a9a 407 * @brief Sets the FLL External Reference Divider.
screamer 0:e4d670b91a9a 408 *
screamer 0:e4d670b91a9a 409 * This function sets the FLL External Reference Divider.
screamer 0:e4d670b91a9a 410 *
screamer 0:e4d670b91a9a 411 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 412 * @param setting Divider setting
screamer 0:e4d670b91a9a 413 */
screamer 0:e4d670b91a9a 414 static inline void CLOCK_HAL_SetFllExternalRefDivider(uint32_t baseAddr,
screamer 0:e4d670b91a9a 415 uint8_t setting)
screamer 0:e4d670b91a9a 416 {
screamer 0:e4d670b91a9a 417 BW_MCG_C1_FRDIV(baseAddr, setting);
screamer 0:e4d670b91a9a 418 }
screamer 0:e4d670b91a9a 419
screamer 0:e4d670b91a9a 420 /*!
screamer 0:e4d670b91a9a 421 * @brief Gets the FLL External Reference Divider.
screamer 0:e4d670b91a9a 422 *
screamer 0:e4d670b91a9a 423 * This function gets the FLL External Reference Divider.
screamer 0:e4d670b91a9a 424 *
screamer 0:e4d670b91a9a 425 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 426 * @return setting Divider setting
screamer 0:e4d670b91a9a 427 */
screamer 0:e4d670b91a9a 428 static inline uint8_t CLOCK_HAL_GetFllExternalRefDivider(uint32_t baseAddr)
screamer 0:e4d670b91a9a 429 {
screamer 0:e4d670b91a9a 430 return BR_MCG_C1_FRDIV(baseAddr);
screamer 0:e4d670b91a9a 431 }
screamer 0:e4d670b91a9a 432
screamer 0:e4d670b91a9a 433 /*!
screamer 0:e4d670b91a9a 434 * @brief Sets the Internal Reference Select.
screamer 0:e4d670b91a9a 435 *
screamer 0:e4d670b91a9a 436 * This function selects the reference clock source for the FLL.
screamer 0:e4d670b91a9a 437 *
screamer 0:e4d670b91a9a 438 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 439 * @param select Clock source select
screamer 0:e4d670b91a9a 440 * - 0: External reference clock is selected
screamer 0:e4d670b91a9a 441 * - 1: The slow internal reference clock is selected
screamer 0:e4d670b91a9a 442 */
screamer 0:e4d670b91a9a 443 static inline void CLOCK_HAL_SetInternalRefSelMode(uint32_t baseAddr,
screamer 0:e4d670b91a9a 444 mcg_internal_ref_clock_source_t select)
screamer 0:e4d670b91a9a 445 {
screamer 0:e4d670b91a9a 446 BW_MCG_C1_IREFS(baseAddr, select);
screamer 0:e4d670b91a9a 447 }
screamer 0:e4d670b91a9a 448
screamer 0:e4d670b91a9a 449 /*!
screamer 0:e4d670b91a9a 450 * @brief Gets the Internal Reference Select
screamer 0:e4d670b91a9a 451 *
screamer 0:e4d670b91a9a 452 * This function gets the reference clock source for the FLL.
screamer 0:e4d670b91a9a 453 *
screamer 0:e4d670b91a9a 454 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 455 * @return select Clock source select
screamer 0:e4d670b91a9a 456 */
screamer 0:e4d670b91a9a 457 static inline mcg_internal_ref_clock_source_t CLOCK_HAL_GetInternalRefSelMode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 458 {
screamer 0:e4d670b91a9a 459 return (mcg_internal_ref_clock_source_t)BR_MCG_C1_IREFS(baseAddr);
screamer 0:e4d670b91a9a 460 }
screamer 0:e4d670b91a9a 461
screamer 0:e4d670b91a9a 462 /*!
screamer 0:e4d670b91a9a 463 * @brief Sets the CLKS, FRDIV and IREFS at the same time.
screamer 0:e4d670b91a9a 464 *
screamer 0:e4d670b91a9a 465 * This function sets the CLKS, FRDIV, and IREFS settings at the same time
screamer 0:e4d670b91a9a 466 * in order keep the integrity of the clock switching.
screamer 0:e4d670b91a9a 467 *
screamer 0:e4d670b91a9a 468 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 469 * @param clks Clock source select
screamer 0:e4d670b91a9a 470 * @param frdiv FLL external reference divider select
screamer 0:e4d670b91a9a 471 * @param irefs Internal reference select
screamer 0:e4d670b91a9a 472 */
screamer 0:e4d670b91a9a 473 static inline void CLOCK_HAL_SetClksFrdivInternalRefSelect(uint32_t baseAddr,
screamer 0:e4d670b91a9a 474 mcg_clock_select_t clks,
screamer 0:e4d670b91a9a 475 uint8_t frdiv,
screamer 0:e4d670b91a9a 476 mcg_internal_ref_clock_source_t irefs)
screamer 0:e4d670b91a9a 477 {
screamer 0:e4d670b91a9a 478 /* Set the required CLKS , FRDIV and IREFS values */
screamer 0:e4d670b91a9a 479 HW_MCG_C1_WR(baseAddr, (HW_MCG_C1_RD(baseAddr) & ~(BM_MCG_C1_CLKS | BM_MCG_C1_FRDIV | BM_MCG_C1_IREFS))
screamer 0:e4d670b91a9a 480 | (BF_MCG_C1_CLKS(clks) | BF_MCG_C1_FRDIV(frdiv) | BF_MCG_C1_IREFS(irefs)));
screamer 0:e4d670b91a9a 481 }
screamer 0:e4d670b91a9a 482
screamer 0:e4d670b91a9a 483 /*!
screamer 0:e4d670b91a9a 484 * @brief Sets the Enable Internal Reference Clock setting.
screamer 0:e4d670b91a9a 485 *
screamer 0:e4d670b91a9a 486 * This function enables/disables the internal reference clock to use as the MCGIRCLK.
screamer 0:e4d670b91a9a 487 *
screamer 0:e4d670b91a9a 488 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 489 * @params enable Enable or disable internal reference clock.
screamer 0:e4d670b91a9a 490 * - true: MCGIRCLK active
screamer 0:e4d670b91a9a 491 * - false: MCGIRCLK inactive
screamer 0:e4d670b91a9a 492 */
screamer 0:e4d670b91a9a 493 static inline void CLOCK_HAL_SetInternalClkCmd(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 494 {
screamer 0:e4d670b91a9a 495 BW_MCG_C1_IRCLKEN(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 496 }
screamer 0:e4d670b91a9a 497
screamer 0:e4d670b91a9a 498 /*!
screamer 0:e4d670b91a9a 499 * @brief Gets the enable Internal Reference Clock setting.
screamer 0:e4d670b91a9a 500 *
screamer 0:e4d670b91a9a 501 * This function gets the reference clock enable setting.
screamer 0:e4d670b91a9a 502 *
screamer 0:e4d670b91a9a 503 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 504 * @return enabled True if the internal reference clock is enabled.
screamer 0:e4d670b91a9a 505 */
screamer 0:e4d670b91a9a 506 static inline bool CLOCK_HAL_GetInternalClkCmd(uint32_t baseAddr)
screamer 0:e4d670b91a9a 507 {
screamer 0:e4d670b91a9a 508 return BR_MCG_C1_IRCLKEN(baseAddr);
screamer 0:e4d670b91a9a 509 }
screamer 0:e4d670b91a9a 510
screamer 0:e4d670b91a9a 511 /*!
screamer 0:e4d670b91a9a 512 * @brief Sets the Internal Reference Clock Stop Enable setting.
screamer 0:e4d670b91a9a 513 *
screamer 0:e4d670b91a9a 514 * This function controls whether or not the internal reference clock remains
screamer 0:e4d670b91a9a 515 * enabled when the MCG enters Stop mode.
screamer 0:e4d670b91a9a 516 *
screamer 0:e4d670b91a9a 517 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 518 * @params enable Enable or disable the internal reference clock stop setting.
screamer 0:e4d670b91a9a 519 * - true: Internal reference clock is enabled in Stop mode if IRCLKEN is set
screamer 0:e4d670b91a9a 520 * or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
screamer 0:e4d670b91a9a 521 * - false: Internal reference clock is disabled in Stop mode
screamer 0:e4d670b91a9a 522 */
screamer 0:e4d670b91a9a 523 static inline void CLOCK_HAL_SetInternalRefStopCmd(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 524 {
screamer 0:e4d670b91a9a 525 BW_MCG_C1_IREFSTEN(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 526 }
screamer 0:e4d670b91a9a 527
screamer 0:e4d670b91a9a 528 /*!
screamer 0:e4d670b91a9a 529 * @brief Gets the Enable Internal Reference Clock setting.
screamer 0:e4d670b91a9a 530 *
screamer 0:e4d670b91a9a 531 * This function gets the Internal Reference Clock Stop Enable setting.
screamer 0:e4d670b91a9a 532 *
screamer 0:e4d670b91a9a 533 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 534 * @return enabled True if internal reference clock stop is enabled.
screamer 0:e4d670b91a9a 535 */
screamer 0:e4d670b91a9a 536 static inline bool CLOCK_HAL_GetInternalRefStopCmd(uint32_t baseAddr)
screamer 0:e4d670b91a9a 537 {
screamer 0:e4d670b91a9a 538 return BR_MCG_C1_IREFSTEN(baseAddr);
screamer 0:e4d670b91a9a 539 }
screamer 0:e4d670b91a9a 540
screamer 0:e4d670b91a9a 541 /*!
screamer 0:e4d670b91a9a 542 * @brief Sets the Loss of Clock Reset Enable setting.
screamer 0:e4d670b91a9a 543 *
screamer 0:e4d670b91a9a 544 * This function determines whether an interrupt or a reset request is made following a loss
screamer 0:e4d670b91a9a 545 * of the OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is set.
screamer 0:e4d670b91a9a 546 *
screamer 0:e4d670b91a9a 547 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 548 * @params enable Loss of Clock Reset Enable setting
screamer 0:e4d670b91a9a 549 * - true: Generate a reset request on a loss of OSC0 external reference clock
screamer 0:e4d670b91a9a 550 * - false: Interrupt request is generated on a loss of OSC0 external reference clock
screamer 0:e4d670b91a9a 551 */
screamer 0:e4d670b91a9a 552 static inline void CLOCK_HAL_SetLossOfClkReset0Cmd(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 553 {
screamer 0:e4d670b91a9a 554 BW_MCG_C2_LOCRE0(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 555 }
screamer 0:e4d670b91a9a 556
screamer 0:e4d670b91a9a 557 /*!
screamer 0:e4d670b91a9a 558 * @brief Gets the Loss of Clock Reset Enable setting.
screamer 0:e4d670b91a9a 559 *
screamer 0:e4d670b91a9a 560 * This function gets the Loss of Clock Reset Enable setting.
screamer 0:e4d670b91a9a 561 *
screamer 0:e4d670b91a9a 562 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 563 * @return enabled True if Loss of Clock Reset is enabled.
screamer 0:e4d670b91a9a 564 */
screamer 0:e4d670b91a9a 565 static inline bool CLOCK_HAL_GetLossOfClkReset0Cmd(uint32_t baseAddr)
screamer 0:e4d670b91a9a 566 {
screamer 0:e4d670b91a9a 567 return BR_MCG_C2_LOCRE0(baseAddr);
screamer 0:e4d670b91a9a 568 }
screamer 0:e4d670b91a9a 569
screamer 0:e4d670b91a9a 570 #if FSL_FEATURE_MCG_HAS_FCFTRIM
screamer 0:e4d670b91a9a 571 /*!
screamer 0:e4d670b91a9a 572 * @brief Sets the Fast Internal Reference Clock Fine Trim setting.
screamer 0:e4d670b91a9a 573 *
screamer 0:e4d670b91a9a 574 * This function sets the Fast Internal Reference Clock Fine Trim setting. FCFTRIM
screamer 0:e4d670b91a9a 575 * controls the smallest adjustment of the fast internal reference clock frequency.
screamer 0:e4d670b91a9a 576 * Setting the FCFTRIM increases the period and clearing FCFTRIM decreases the period
screamer 0:e4d670b91a9a 577 * by the smallest amount possible. If an FCFTRIM value is stored and non-volatile
screamer 0:e4d670b91a9a 578 * memory is to be used, it is the user's responsibility to copy that value from the
screamer 0:e4d670b91a9a 579 * non-volatile memory location to this bit.
screamer 0:e4d670b91a9a 580 *
screamer 0:e4d670b91a9a 581 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 582 * @params setting Fast Internal Reference Clock Fine Trim setting
screamer 0:e4d670b91a9a 583 */
screamer 0:e4d670b91a9a 584 static inline void CLOCK_HAL_SetFastInternalRefClkFineTrim(uint32_t baseAddr, uint8_t setting)
screamer 0:e4d670b91a9a 585 {
screamer 0:e4d670b91a9a 586 BW_MCG_C2_FCFTRIM(baseAddr, setting);
screamer 0:e4d670b91a9a 587 }
screamer 0:e4d670b91a9a 588
screamer 0:e4d670b91a9a 589 /*!
screamer 0:e4d670b91a9a 590 * @brief Gets the Fast Internal Reference Clock Fine Trim setting.
screamer 0:e4d670b91a9a 591 *
screamer 0:e4d670b91a9a 592 * This function gets the Fast Internal Reference Clock Fine Trim setting.
screamer 0:e4d670b91a9a 593 *
screamer 0:e4d670b91a9a 594 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 595 * @return setting Fast Internal Reference Clock Fine Trim setting
screamer 0:e4d670b91a9a 596 */
screamer 0:e4d670b91a9a 597 static inline uint8_t CLOCK_HAL_GetFastInternalRefClkFineTrim(uint32_t baseAddr)
screamer 0:e4d670b91a9a 598 {
screamer 0:e4d670b91a9a 599 return BR_MCG_C2_FCFTRIM(baseAddr);
screamer 0:e4d670b91a9a 600 }
screamer 0:e4d670b91a9a 601 #endif /* FSL_FEATURE_MCG_HAS_FCFTRIM */
screamer 0:e4d670b91a9a 602
screamer 0:e4d670b91a9a 603 /*!
screamer 0:e4d670b91a9a 604 * @brief Sets the Frequency Range Select.
screamer 0:e4d670b91a9a 605 *
screamer 0:e4d670b91a9a 606 * This function selects the frequency range for the crystal oscillator or an external
screamer 0:e4d670b91a9a 607 * clock source. See the Oscillator (OSC) chapter for more details and the device
screamer 0:e4d670b91a9a 608 * data sheet for the frequency ranges used.
screamer 0:e4d670b91a9a 609 *
screamer 0:e4d670b91a9a 610 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 611 * @params select Frequency Range Select
screamer 0:e4d670b91a9a 612 * - 00: Low frequency range selected for the crystal oscillator
screamer 0:e4d670b91a9a 613 * - 01: High frequency range selected for the crystal oscillator
screamer 0:e4d670b91a9a 614 * - 1X: Very high frequency range selected for the crystal oscillator
screamer 0:e4d670b91a9a 615 */
screamer 0:e4d670b91a9a 616 static inline void CLOCK_HAL_SetRange0Mode(uint32_t baseAddr, mcg_freq_range_select_t select)
screamer 0:e4d670b91a9a 617 {
screamer 0:e4d670b91a9a 618 BW_MCG_C2_RANGE(baseAddr, select);
screamer 0:e4d670b91a9a 619 }
screamer 0:e4d670b91a9a 620
screamer 0:e4d670b91a9a 621 /*!
screamer 0:e4d670b91a9a 622 * @brief Gets the Frequency Range Select.
screamer 0:e4d670b91a9a 623 *
screamer 0:e4d670b91a9a 624 * This function gets the Frequency Range Select.
screamer 0:e4d670b91a9a 625 *
screamer 0:e4d670b91a9a 626 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 627 * @return select Frequency Range Select
screamer 0:e4d670b91a9a 628 */
screamer 0:e4d670b91a9a 629 static inline mcg_freq_range_select_t CLOCK_HAL_GetRange0Mode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 630 {
screamer 0:e4d670b91a9a 631 return (mcg_freq_range_select_t)BR_MCG_C2_RANGE(baseAddr);
screamer 0:e4d670b91a9a 632 }
screamer 0:e4d670b91a9a 633
screamer 0:e4d670b91a9a 634 /*!
screamer 0:e4d670b91a9a 635 * @brief Sets the High Gain Oscillator Select.
screamer 0:e4d670b91a9a 636 *
screamer 0:e4d670b91a9a 637 * This function controls the crystal oscillator mode of operation. See the
screamer 0:e4d670b91a9a 638 * Oscillator (OSC) chapter for more details.
screamer 0:e4d670b91a9a 639 *
screamer 0:e4d670b91a9a 640 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 641 * @params select High Gain Oscillator Select.
screamer 0:e4d670b91a9a 642 * - 0: Configure crystal oscillator for low-power operation
screamer 0:e4d670b91a9a 643 * - 1: Configure crystal oscillator for high-gain operation
screamer 0:e4d670b91a9a 644 */
screamer 0:e4d670b91a9a 645 static inline void CLOCK_HAL_SetHighGainOsc0Mode(uint32_t baseAddr, mcg_high_gain_osc_select_t select)
screamer 0:e4d670b91a9a 646 {
screamer 0:e4d670b91a9a 647 BW_MCG_C2_HGO(baseAddr, select);
screamer 0:e4d670b91a9a 648 }
screamer 0:e4d670b91a9a 649
screamer 0:e4d670b91a9a 650 /*!
screamer 0:e4d670b91a9a 651 * @brief Gets the High Gain Oscillator Select.
screamer 0:e4d670b91a9a 652 *
screamer 0:e4d670b91a9a 653 * This function gets the High Gain Oscillator Select.
screamer 0:e4d670b91a9a 654 *
screamer 0:e4d670b91a9a 655 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 656 * @return select High Gain Oscillator Select
screamer 0:e4d670b91a9a 657 */
screamer 0:e4d670b91a9a 658 static inline mcg_high_gain_osc_select_t CLOCK_HAL_GetHighGainOsc0Mode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 659 {
screamer 0:e4d670b91a9a 660 return (mcg_high_gain_osc_select_t)BR_MCG_C2_HGO(baseAddr);
screamer 0:e4d670b91a9a 661 }
screamer 0:e4d670b91a9a 662
screamer 0:e4d670b91a9a 663 /*!
screamer 0:e4d670b91a9a 664 * @brief Sets the External Reference Select.
screamer 0:e4d670b91a9a 665 *
screamer 0:e4d670b91a9a 666 * This function selects the source for the external reference clock.
screamer 0:e4d670b91a9a 667 * See the Oscillator (OSC) chapter for more details.
screamer 0:e4d670b91a9a 668 *
screamer 0:e4d670b91a9a 669 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 670 * @params select External Reference Select
screamer 0:e4d670b91a9a 671 * - 0: External reference clock requested
screamer 0:e4d670b91a9a 672 * - 1: Oscillator requested
screamer 0:e4d670b91a9a 673 */
screamer 0:e4d670b91a9a 674 static inline void CLOCK_HAL_SetExternalRefSel0Mode(uint32_t baseAddr, mcg_external_ref_clock_select_t select)
screamer 0:e4d670b91a9a 675 {
screamer 0:e4d670b91a9a 676 BW_MCG_C2_EREFS(baseAddr, select);
screamer 0:e4d670b91a9a 677 }
screamer 0:e4d670b91a9a 678
screamer 0:e4d670b91a9a 679 /*!
screamer 0:e4d670b91a9a 680 * @brief Gets the External Reference Select.
screamer 0:e4d670b91a9a 681 *
screamer 0:e4d670b91a9a 682 * This function gets the External Reference Select.
screamer 0:e4d670b91a9a 683 *
screamer 0:e4d670b91a9a 684 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 685 * @return select External Reference Select
screamer 0:e4d670b91a9a 686 */
screamer 0:e4d670b91a9a 687 static inline mcg_external_ref_clock_select_t CLOCK_HAL_GetExternalRefSel0Mode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 688 {
screamer 0:e4d670b91a9a 689 return (mcg_external_ref_clock_select_t)BR_MCG_C2_EREFS(baseAddr);
screamer 0:e4d670b91a9a 690 }
screamer 0:e4d670b91a9a 691
screamer 0:e4d670b91a9a 692 /*!
screamer 0:e4d670b91a9a 693 * @brief Sets the Low Power Select.
screamer 0:e4d670b91a9a 694 *
screamer 0:e4d670b91a9a 695 * This function controls whether the FLL (or PLL) is disabled in the BLPI and the
screamer 0:e4d670b91a9a 696 * BLPE modes. In the FBE or the PBE modes, setting this bit to 1 transitions the MCG
screamer 0:e4d670b91a9a 697 * into the BLPE mode; in the FBI mode, setting this bit to 1 transitions the MCG into
screamer 0:e4d670b91a9a 698 * the BLPI mode. In any other MCG mode, the LP bit has no affect..
screamer 0:e4d670b91a9a 699 *
screamer 0:e4d670b91a9a 700 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 701 * @params select Low Power Select
screamer 0:e4d670b91a9a 702 * - 0: FLL (or PLL) is not disabled in bypass modes
screamer 0:e4d670b91a9a 703 * - 1: FLL (or PLL) is disabled in bypass modes (lower power)
screamer 0:e4d670b91a9a 704 */
screamer 0:e4d670b91a9a 705 static inline void CLOCK_HAL_SetLowPowerMode(uint32_t baseAddr, mcg_low_power_select_t select)
screamer 0:e4d670b91a9a 706 {
screamer 0:e4d670b91a9a 707 BW_MCG_C2_LP(baseAddr, select);
screamer 0:e4d670b91a9a 708 }
screamer 0:e4d670b91a9a 709
screamer 0:e4d670b91a9a 710 /*!
screamer 0:e4d670b91a9a 711 * @brief Gets the Low Power Select.
screamer 0:e4d670b91a9a 712 *
screamer 0:e4d670b91a9a 713 * This function gets the Low Power Select.
screamer 0:e4d670b91a9a 714 *
screamer 0:e4d670b91a9a 715 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 716 * @return select Low Power Select
screamer 0:e4d670b91a9a 717 */
screamer 0:e4d670b91a9a 718 static inline mcg_low_power_select_t CLOCK_HAL_GetLowPowerMode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 719 {
screamer 0:e4d670b91a9a 720 return (mcg_low_power_select_t)BR_MCG_C2_LP(baseAddr);
screamer 0:e4d670b91a9a 721 }
screamer 0:e4d670b91a9a 722
screamer 0:e4d670b91a9a 723 /*!
screamer 0:e4d670b91a9a 724 * @brief Sets the Internal Reference Clock Select.
screamer 0:e4d670b91a9a 725 *
screamer 0:e4d670b91a9a 726 * This function selects between the fast or slow internal reference clock source.
screamer 0:e4d670b91a9a 727 *
screamer 0:e4d670b91a9a 728 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 729 * @params select Low Power Select
screamer 0:e4d670b91a9a 730 * - 0: Slow internal reference clock selected.
screamer 0:e4d670b91a9a 731 * - 1: Fast internal reference clock selected.
screamer 0:e4d670b91a9a 732 */
screamer 0:e4d670b91a9a 733 static inline void CLOCK_HAL_SetInternalRefClkSelMode(uint32_t baseAddr,
screamer 0:e4d670b91a9a 734 mcg_internal_ref_clock_select_t select)
screamer 0:e4d670b91a9a 735 {
screamer 0:e4d670b91a9a 736 BW_MCG_C2_IRCS(baseAddr, select);
screamer 0:e4d670b91a9a 737 }
screamer 0:e4d670b91a9a 738
screamer 0:e4d670b91a9a 739 /*!
screamer 0:e4d670b91a9a 740 * @brief Gets the Internal Reference Clock Select.
screamer 0:e4d670b91a9a 741 *
screamer 0:e4d670b91a9a 742 * This function gets the Internal Reference Clock Select.
screamer 0:e4d670b91a9a 743 *
screamer 0:e4d670b91a9a 744 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 745 * @return select Internal Reference Clock Select
screamer 0:e4d670b91a9a 746 */
screamer 0:e4d670b91a9a 747 static inline mcg_internal_ref_clock_select_t CLOCK_HAL_GetInternalRefClkSelMode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 748 {
screamer 0:e4d670b91a9a 749 return (mcg_internal_ref_clock_select_t)BR_MCG_C2_IRCS(baseAddr);
screamer 0:e4d670b91a9a 750 }
screamer 0:e4d670b91a9a 751
screamer 0:e4d670b91a9a 752 /*!
screamer 0:e4d670b91a9a 753 * @brief Sets the Slow Internal Reference Clock Trim Setting.
screamer 0:e4d670b91a9a 754 *
screamer 0:e4d670b91a9a 755 * This function controls the slow internal reference clock frequency by
screamer 0:e4d670b91a9a 756 * controlling the slow internal reference clock period. The SCTRIM bits are
screamer 0:e4d670b91a9a 757 * binary weighted (that is, bit 1 adjusts twice as much as bit 0).
screamer 0:e4d670b91a9a 758 * Increasing the binary value increases the period, and decreasing the value
screamer 0:e4d670b91a9a 759 * decreases the period.
screamer 0:e4d670b91a9a 760 * An additional fine trim bit is available in the C4 register as the SCFTRIM bit.
screamer 0:e4d670b91a9a 761 * Upon reset, this value is loaded with a factory trim value.
screamer 0:e4d670b91a9a 762 * If an SCTRIM value stored in non-volatile memory is to be used, it is the user's
screamer 0:e4d670b91a9a 763 * responsibility to copy that value from the non-volatile memory location to
screamer 0:e4d670b91a9a 764 * this register.
screamer 0:e4d670b91a9a 765 *
screamer 0:e4d670b91a9a 766 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 767 * @params setting Slow Internal Reference Clock Trim Setting
screamer 0:e4d670b91a9a 768 */
screamer 0:e4d670b91a9a 769 static inline void CLOCK_HAL_SetSlowInternalRefClkTrim(uint32_t baseAddr, uint8_t setting)
screamer 0:e4d670b91a9a 770 {
screamer 0:e4d670b91a9a 771 BW_MCG_C3_SCTRIM(baseAddr, setting);
screamer 0:e4d670b91a9a 772 }
screamer 0:e4d670b91a9a 773
screamer 0:e4d670b91a9a 774 /*!
screamer 0:e4d670b91a9a 775 * @brief Gets the Slow Internal Reference Clock Trim Setting.
screamer 0:e4d670b91a9a 776 *
screamer 0:e4d670b91a9a 777 * This function gets the Slow Internal Reference Clock Trim Setting.
screamer 0:e4d670b91a9a 778 *
screamer 0:e4d670b91a9a 779 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 780 * @return setting Slow Internal Reference Clock Trim Setting
screamer 0:e4d670b91a9a 781 */
screamer 0:e4d670b91a9a 782 static inline uint8_t CLOCK_HAL_GetSlowInternalRefClkTrim(uint32_t baseAddr)
screamer 0:e4d670b91a9a 783 {
screamer 0:e4d670b91a9a 784 return BR_MCG_C3_SCTRIM(baseAddr);
screamer 0:e4d670b91a9a 785 }
screamer 0:e4d670b91a9a 786
screamer 0:e4d670b91a9a 787 /*!
screamer 0:e4d670b91a9a 788 * @brief Sets the DCO Maximum Frequency with 32.768 kHz Reference.
screamer 0:e4d670b91a9a 789 *
screamer 0:e4d670b91a9a 790 * This function controls whether or not the DCO frequency range
screamer 0:e4d670b91a9a 791 * is narrowed to its maximum frequency with a 32.768 kHz reference.
screamer 0:e4d670b91a9a 792 *
screamer 0:e4d670b91a9a 793 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 794 * @params setting DCO Maximum Frequency with 32.768 kHz Reference Setting
screamer 0:e4d670b91a9a 795 * - 0: DCO has a default range of 25%.
screamer 0:e4d670b91a9a 796 * - 1: DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
screamer 0:e4d670b91a9a 797 */
screamer 0:e4d670b91a9a 798 static inline void CLOCK_HAL_SetDmx32(uint32_t baseAddr, mcg_dmx32_select_t setting)
screamer 0:e4d670b91a9a 799 {
screamer 0:e4d670b91a9a 800 BW_MCG_C4_DMX32(baseAddr, setting);
screamer 0:e4d670b91a9a 801 }
screamer 0:e4d670b91a9a 802
screamer 0:e4d670b91a9a 803 /*!
screamer 0:e4d670b91a9a 804 * @brief Gets the DCO Maximum Frequency with the 32.768 kHz Reference Setting.
screamer 0:e4d670b91a9a 805 *
screamer 0:e4d670b91a9a 806 * This function gets the DCO Maximum Frequency with 32.768 kHz Reference Setting.
screamer 0:e4d670b91a9a 807 *
screamer 0:e4d670b91a9a 808 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 809 * @return setting DCO Maximum Frequency with 32.768 kHz Reference Setting
screamer 0:e4d670b91a9a 810 */
screamer 0:e4d670b91a9a 811 static inline mcg_dmx32_select_t CLOCK_HAL_GetDmx32(uint32_t baseAddr)
screamer 0:e4d670b91a9a 812 {
screamer 0:e4d670b91a9a 813 return (mcg_dmx32_select_t)BR_MCG_C4_DMX32(baseAddr);
screamer 0:e4d670b91a9a 814 }
screamer 0:e4d670b91a9a 815
screamer 0:e4d670b91a9a 816 /*!
screamer 0:e4d670b91a9a 817 * @brief Sets the DCO Range Select.
screamer 0:e4d670b91a9a 818 *
screamer 0:e4d670b91a9a 819 * This function selects the frequency range for the FLL output, DCOOUT.
screamer 0:e4d670b91a9a 820 * When the LP bit is set, the writes to the DRS bits are ignored. The DRST read
screamer 0:e4d670b91a9a 821 * field indicates the current frequency range for the DCOOUT. The DRST field does
screamer 0:e4d670b91a9a 822 * not update immediately after a write to the DRS field due to internal
screamer 0:e4d670b91a9a 823 * synchronization between the clock domains. See the DCO Frequency Range table
screamer 0:e4d670b91a9a 824 * for more details.
screamer 0:e4d670b91a9a 825 *
screamer 0:e4d670b91a9a 826 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 827 * @params setting DCO Range Select Setting
screamer 0:e4d670b91a9a 828 * - 00: Low range (reset default).
screamer 0:e4d670b91a9a 829 * - 01: Mid range.
screamer 0:e4d670b91a9a 830 * - 10: Mid-high range.
screamer 0:e4d670b91a9a 831 * - 11: High range.
screamer 0:e4d670b91a9a 832 */
screamer 0:e4d670b91a9a 833 static inline void CLOCK_HAL_SetDigitalControlledOscRangeMode(uint32_t baseAddr,
screamer 0:e4d670b91a9a 834 mcg_digital_controlled_osc_range_select_t setting)
screamer 0:e4d670b91a9a 835 {
screamer 0:e4d670b91a9a 836 BW_MCG_C4_DRST_DRS(baseAddr, setting);
screamer 0:e4d670b91a9a 837 }
screamer 0:e4d670b91a9a 838
screamer 0:e4d670b91a9a 839 /*!
screamer 0:e4d670b91a9a 840 * @brief Gets the DCO Range Select Setting.
screamer 0:e4d670b91a9a 841 *
screamer 0:e4d670b91a9a 842 * This function gets the DCO Range Select Setting.
screamer 0:e4d670b91a9a 843 *
screamer 0:e4d670b91a9a 844 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 845 * @return setting DCO Range Select Setting
screamer 0:e4d670b91a9a 846 */
screamer 0:e4d670b91a9a 847 static inline mcg_digital_controlled_osc_range_select_t CLOCK_HAL_GetDigitalControlledOscRangeMode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 848 {
screamer 0:e4d670b91a9a 849 return (mcg_digital_controlled_osc_range_select_t)BR_MCG_C4_DRST_DRS(baseAddr);
screamer 0:e4d670b91a9a 850 }
screamer 0:e4d670b91a9a 851
screamer 0:e4d670b91a9a 852 /*!
screamer 0:e4d670b91a9a 853 * @brief Sets the Fast Internal Reference Clock Trim Setting.
screamer 0:e4d670b91a9a 854 *
screamer 0:e4d670b91a9a 855 * This function controls the fast internal reference clock frequency
screamer 0:e4d670b91a9a 856 * by controlling the fast internal reference clock period. The FCTRIM
screamer 0:e4d670b91a9a 857 * bits are binary weighted (that is, bit 1 adjusts twice as much as bit 0).
screamer 0:e4d670b91a9a 858 * Increasing the binary value increases the period, and decreasing the
screamer 0:e4d670b91a9a 859 * value decreases the period.
screamer 0:e4d670b91a9a 860 * If an FCTRIM[3:0] value stored in non-volatile memory is to be used, it is
screamer 0:e4d670b91a9a 861 * the user's responsibility to copy that value from the non-volatile memory location
screamer 0:e4d670b91a9a 862 * to this register.
screamer 0:e4d670b91a9a 863 *
screamer 0:e4d670b91a9a 864 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 865 * @params setting Fast Internal Reference Clock Trim Setting.
screamer 0:e4d670b91a9a 866 */
screamer 0:e4d670b91a9a 867 static inline void CLOCK_HAL_SetFastInternalRefClkTrim(uint32_t baseAddr, uint8_t setting)
screamer 0:e4d670b91a9a 868 {
screamer 0:e4d670b91a9a 869 BW_MCG_C4_FCTRIM(baseAddr, setting);
screamer 0:e4d670b91a9a 870 }
screamer 0:e4d670b91a9a 871
screamer 0:e4d670b91a9a 872 /*!
screamer 0:e4d670b91a9a 873 * @brief Gets the Fast Internal Reference Clock Trim Setting.
screamer 0:e4d670b91a9a 874 *
screamer 0:e4d670b91a9a 875 * This function gets the Fast Internal Reference Clock Trim Setting.
screamer 0:e4d670b91a9a 876 *
screamer 0:e4d670b91a9a 877 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 878 * @return setting Fast Internal Reference Clock Trim Setting
screamer 0:e4d670b91a9a 879 */
screamer 0:e4d670b91a9a 880 static inline uint8_t CLOCK_HAL_GetFastInternalRefClkTrim(uint32_t baseAddr)
screamer 0:e4d670b91a9a 881 {
screamer 0:e4d670b91a9a 882 return BR_MCG_C4_FCTRIM(baseAddr);
screamer 0:e4d670b91a9a 883 }
screamer 0:e4d670b91a9a 884
screamer 0:e4d670b91a9a 885 /*!
screamer 0:e4d670b91a9a 886 * @brief Sets the Slow Internal Reference Clock Fine Trim Setting.
screamer 0:e4d670b91a9a 887 *
screamer 0:e4d670b91a9a 888 * This function controls the smallest adjustment of the slow internal
screamer 0:e4d670b91a9a 889 * reference clock frequency. Setting the SCFTRIM increases the period and
screamer 0:e4d670b91a9a 890 * clearing the SCFTRIM decreases the period by the smallest amount possible.
screamer 0:e4d670b91a9a 891 * If an SCFTRIM value, stored in non-volatile memory, is to be used, it is
screamer 0:e4d670b91a9a 892 * the user's responsibility to copy that value from the non-volatile memory
screamer 0:e4d670b91a9a 893 * location to this bit.
screamer 0:e4d670b91a9a 894 *
screamer 0:e4d670b91a9a 895 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 896 * @params setting Slow Internal Reference Clock Fine Trim Setting
screamer 0:e4d670b91a9a 897 */
screamer 0:e4d670b91a9a 898 static inline void CLOCK_HAL_SetSlowInternalRefClkFineTrim(uint32_t baseAddr, uint8_t setting)
screamer 0:e4d670b91a9a 899 {
screamer 0:e4d670b91a9a 900 BW_MCG_C4_SCFTRIM(baseAddr, setting);
screamer 0:e4d670b91a9a 901 }
screamer 0:e4d670b91a9a 902
screamer 0:e4d670b91a9a 903 /*!
screamer 0:e4d670b91a9a 904 * @brief Gets the Slow Internal Reference Clock Fine Trim Setting.
screamer 0:e4d670b91a9a 905 *
screamer 0:e4d670b91a9a 906 * This function gets the Slow Internal Reference Clock Fine Trim Setting.
screamer 0:e4d670b91a9a 907 *
screamer 0:e4d670b91a9a 908 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 909 * @return setting Slow Internal Reference Clock Fine Trim Setting
screamer 0:e4d670b91a9a 910 */
screamer 0:e4d670b91a9a 911 static inline uint8_t CLOCK_HAL_GetSlowInternalRefClkFineTrim(uint32_t baseAddr)
screamer 0:e4d670b91a9a 912 {
screamer 0:e4d670b91a9a 913 return BR_MCG_C4_SCFTRIM(baseAddr);
screamer 0:e4d670b91a9a 914 }
screamer 0:e4d670b91a9a 915
screamer 0:e4d670b91a9a 916 #if FSL_FEATURE_MCG_USE_PLLREFSEL
screamer 0:e4d670b91a9a 917 /*!
screamer 0:e4d670b91a9a 918 * @brief Sets the PLL0 External Reference Select Setting.
screamer 0:e4d670b91a9a 919 *
screamer 0:e4d670b91a9a 920 * This function selects the PLL0 external reference clock source.
screamer 0:e4d670b91a9a 921 *
screamer 0:e4d670b91a9a 922 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 923 * @params setting PLL0 External Reference Select Setting
screamer 0:e4d670b91a9a 924 * - 0: Selects OSC0 clock source as its external reference clock
screamer 0:e4d670b91a9a 925 * - 1: Selects OSC1 clock source as its external reference clock
screamer 0:e4d670b91a9a 926 */
screamer 0:e4d670b91a9a 927 static inline void CLOCK_HAL_SetPllRefSel0Mode(uint32_t baseAddr,
screamer 0:e4d670b91a9a 928 mcg_pll_external_ref_clk_select_t setting)
screamer 0:e4d670b91a9a 929 {
screamer 0:e4d670b91a9a 930 BW_MCG_C5_PLLREFSEL0(baseAddr, setting);
screamer 0:e4d670b91a9a 931 }
screamer 0:e4d670b91a9a 932
screamer 0:e4d670b91a9a 933 /*!
screamer 0:e4d670b91a9a 934 * @brief Gets the PLL0 External Reference Select Setting.
screamer 0:e4d670b91a9a 935 *
screamer 0:e4d670b91a9a 936 * This function gets the PLL0 External Reference Select Setting.
screamer 0:e4d670b91a9a 937 *
screamer 0:e4d670b91a9a 938 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 939 * @return setting PLL0 External Reference Select Setting
screamer 0:e4d670b91a9a 940 */
screamer 0:e4d670b91a9a 941 static inline mcg_pll_external_ref_clk_select_t CLOCK_HAL_GetPllRefSel0Mode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 942 {
screamer 0:e4d670b91a9a 943 return (mcg_pll_external_ref_clk_select_t)BR_MCG_C5_PLLREFSEL0(baseAddr);
screamer 0:e4d670b91a9a 944 }
screamer 0:e4d670b91a9a 945 #endif /* FSL_FEATURE_MCG_USE_PLLREFSEL */
screamer 0:e4d670b91a9a 946
screamer 0:e4d670b91a9a 947 #if FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR
screamer 0:e4d670b91a9a 948
screamer 0:e4d670b91a9a 949 /*!
screamer 0:e4d670b91a9a 950 * @brief Sets the Clock Monitor Enable Setting.
screamer 0:e4d670b91a9a 951 *
screamer 0:e4d670b91a9a 952 * This function enables/disables the loss of clock monitoring circuit for
screamer 0:e4d670b91a9a 953 * the OSC0 external reference mux select. The LOCRE0 bit determines whether an
screamer 0:e4d670b91a9a 954 * interrupt or a reset request is generated following a loss of the OSC0 indication.
screamer 0:e4d670b91a9a 955 * The CME0 bit should only be set to a logic 1 when the MCG is in an operational
screamer 0:e4d670b91a9a 956 * mode that uses the external clock (FEE, FBE, PEE, PBE, or BLPE). Whenever the
screamer 0:e4d670b91a9a 957 * CME0 bit is set to a logic 1, the value of the RANGE0 bits in the C2 register
screamer 0:e4d670b91a9a 958 * should not be changed. CME0 bit should be set to a logic 0 before the MCG
screamer 0:e4d670b91a9a 959 * enters any Stop mode. Otherwise, a reset request may occur while in Stop mode.
screamer 0:e4d670b91a9a 960 * CME0 should also be set to a logic 0 before entering VLPR or VLPW power modes
screamer 0:e4d670b91a9a 961 * if the MCG is in BLPE mode.
screamer 0:e4d670b91a9a 962 *
screamer 0:e4d670b91a9a 963 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 964 * @params enable Clock Monitor Enable Setting
screamer 0:e4d670b91a9a 965 * - true: External clock monitor is enabled for OSC0.
screamer 0:e4d670b91a9a 966 * - false: External clock monitor is disabled for OSC0.
screamer 0:e4d670b91a9a 967 */
screamer 0:e4d670b91a9a 968 static inline void CLOCK_HAL_SetClkMonitor0Cmd(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 969 {
screamer 0:e4d670b91a9a 970 #if FSL_FEATURE_MCG_HAS_PLL
screamer 0:e4d670b91a9a 971 BW_MCG_C6_CME0(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 972 #else
screamer 0:e4d670b91a9a 973 BW_MCG_C6_CME(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 974 #endif
screamer 0:e4d670b91a9a 975 }
screamer 0:e4d670b91a9a 976
screamer 0:e4d670b91a9a 977 /*!
screamer 0:e4d670b91a9a 978 * @brief Gets the Clock Monitor Enable Setting.
screamer 0:e4d670b91a9a 979 *
screamer 0:e4d670b91a9a 980 * This function gets the Clock Monitor Enable Setting.
screamer 0:e4d670b91a9a 981 *
screamer 0:e4d670b91a9a 982 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 983 * @return enabled True if Clock Monitor is enabled
screamer 0:e4d670b91a9a 984 */
screamer 0:e4d670b91a9a 985 static inline bool CLOCK_HAL_GetClkMonitor0Cmd(uint32_t baseAddr)
screamer 0:e4d670b91a9a 986 {
screamer 0:e4d670b91a9a 987 #if FSL_FEATURE_MCG_HAS_PLL
screamer 0:e4d670b91a9a 988 return BR_MCG_C6_CME0(baseAddr);
screamer 0:e4d670b91a9a 989 #else
screamer 0:e4d670b91a9a 990 return BR_MCG_C6_CME(baseAddr);
screamer 0:e4d670b91a9a 991 #endif
screamer 0:e4d670b91a9a 992 }
screamer 0:e4d670b91a9a 993
screamer 0:e4d670b91a9a 994 #endif
screamer 0:e4d670b91a9a 995
screamer 0:e4d670b91a9a 996 #if FSL_FEATURE_MCG_HAS_PLL
screamer 0:e4d670b91a9a 997 /*!
screamer 0:e4d670b91a9a 998 * @brief Sets the PLL Clock Enable Setting.
screamer 0:e4d670b91a9a 999 *
screamer 0:e4d670b91a9a 1000 * This function enables/disables the PLL0 independent of the PLLS and enables the PLL0
screamer 0:e4d670b91a9a 1001 * clock to use as the MCGPLL0CLK and the MCGPLL0CLK2X. (PRDIV0 needs to be programmed to
screamer 0:e4d670b91a9a 1002 * the correct divider to generate a PLL1 reference clock in a valid reference range
screamer 0:e4d670b91a9a 1003 * prior to setting the PLLCLKEN0 bit). Setting PLLCLKEN0 enables the external
screamer 0:e4d670b91a9a 1004 * oscillator selected by REFSEL if not already enabled. Whenever the PLL0 is being
screamer 0:e4d670b91a9a 1005 * enabled with the PLLCLKEN0 bit, and the external oscillator is being used
screamer 0:e4d670b91a9a 1006 * as the reference clock, the OSCINIT 0 bit should be checked to make sure it is set.
screamer 0:e4d670b91a9a 1007 *
screamer 0:e4d670b91a9a 1008 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1009 * @params enable PLL Clock Enable Setting
screamer 0:e4d670b91a9a 1010 * - true: MCGPLL0CLK and MCGPLL0CLK2X are active
screamer 0:e4d670b91a9a 1011 * - false: MCGPLL0CLK and MCGPLL0CLK2X are inactive
screamer 0:e4d670b91a9a 1012 */
screamer 0:e4d670b91a9a 1013 static inline void CLOCK_HAL_SetPllClk0Cmd(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 1014 {
screamer 0:e4d670b91a9a 1015 BW_MCG_C5_PLLCLKEN0(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1016 }
screamer 0:e4d670b91a9a 1017
screamer 0:e4d670b91a9a 1018 /*!
screamer 0:e4d670b91a9a 1019 * @brief Gets the PLL Clock Enable Setting.
screamer 0:e4d670b91a9a 1020 *
screamer 0:e4d670b91a9a 1021 * This function gets the PLL Clock Enable Setting.
screamer 0:e4d670b91a9a 1022 *
screamer 0:e4d670b91a9a 1023 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1024 * @return enabled True if PLL0 PLL Clock is enabled.
screamer 0:e4d670b91a9a 1025 */
screamer 0:e4d670b91a9a 1026 static inline bool CLOCK_HAL_GetPllClk0Cmd(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1027 {
screamer 0:e4d670b91a9a 1028 return BR_MCG_C5_PLLCLKEN0(baseAddr);
screamer 0:e4d670b91a9a 1029 }
screamer 0:e4d670b91a9a 1030
screamer 0:e4d670b91a9a 1031 /*!
screamer 0:e4d670b91a9a 1032 * @brief Sets the PLL0 Stop Enable Setting.
screamer 0:e4d670b91a9a 1033 *
screamer 0:e4d670b91a9a 1034 * This function enables/disables the PLL0 Clock during a Normal Stop (In Low
screamer 0:e4d670b91a9a 1035 * Power Stop mode, the PLL0 clock gets disabled even if PLLSTEN0=1). In all other
screamer 0:e4d670b91a9a 1036 * power modes, the PLLSTEN0 bit has no affect and does not enable the PLL0 Clock
screamer 0:e4d670b91a9a 1037 * to run if it is written to 1.
screamer 0:e4d670b91a9a 1038 *
screamer 0:e4d670b91a9a 1039 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1040 * @params enable PLL0 Stop Enable Setting
screamer 0:e4d670b91a9a 1041 * - true: MCGPLL0CLK and MCGPLL0CLK2X are enabled if system is in
screamer 0:e4d670b91a9a 1042 * Normal Stop mode.
screamer 0:e4d670b91a9a 1043 * - false: MCGPLL0CLK and MCGPLL0CLK2X are disabled in any of the
screamer 0:e4d670b91a9a 1044 * Stop modes.
screamer 0:e4d670b91a9a 1045 */
screamer 0:e4d670b91a9a 1046 static inline void CLOCK_HAL_SetPllStat0Cmd(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 1047 {
screamer 0:e4d670b91a9a 1048 BW_MCG_C5_PLLSTEN0(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1049 }
screamer 0:e4d670b91a9a 1050
screamer 0:e4d670b91a9a 1051 /*!
screamer 0:e4d670b91a9a 1052 * @brief Gets the PLL0 Stop Enable Setting.
screamer 0:e4d670b91a9a 1053 *
screamer 0:e4d670b91a9a 1054 * This function gets the PLL0 Stop Enable Setting.
screamer 0:e4d670b91a9a 1055 *
screamer 0:e4d670b91a9a 1056 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1057 * @return enabled True if the PLL0 Stop is enabled.
screamer 0:e4d670b91a9a 1058 */
screamer 0:e4d670b91a9a 1059 static inline bool CLOCK_HAL_GetPllStat0Cmd(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1060 {
screamer 0:e4d670b91a9a 1061 return BR_MCG_C5_PLLSTEN0(baseAddr);
screamer 0:e4d670b91a9a 1062 }
screamer 0:e4d670b91a9a 1063
screamer 0:e4d670b91a9a 1064 /*!
screamer 0:e4d670b91a9a 1065 * @brief Sets the PLL0 External Reference Divider Setting.
screamer 0:e4d670b91a9a 1066 *
screamer 0:e4d670b91a9a 1067 * This function selects the amount to divide down the external reference
screamer 0:e4d670b91a9a 1068 * clock for the PLL0. The resulting frequency must be in a valid reference
screamer 0:e4d670b91a9a 1069 * range. After the PLL0 is enabled, (by setting either PLLCLKEN0 or PLLS), the
screamer 0:e4d670b91a9a 1070 * PRDIV0 value must not be changed when LOCK0 is zero.
screamer 0:e4d670b91a9a 1071 *
screamer 0:e4d670b91a9a 1072 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1073 * @params setting PLL0 External Reference Divider Setting
screamer 0:e4d670b91a9a 1074 */
screamer 0:e4d670b91a9a 1075 static inline void CLOCK_HAL_SetPllExternalRefDivider0(uint32_t baseAddr, uint8_t setting)
screamer 0:e4d670b91a9a 1076 {
screamer 0:e4d670b91a9a 1077 BW_MCG_C5_PRDIV0(baseAddr, setting);
screamer 0:e4d670b91a9a 1078 }
screamer 0:e4d670b91a9a 1079
screamer 0:e4d670b91a9a 1080 /*!
screamer 0:e4d670b91a9a 1081 * @brief Gets the PLL0 External Reference Divider Setting.
screamer 0:e4d670b91a9a 1082 *
screamer 0:e4d670b91a9a 1083 * This function gets the PLL0 External Reference Divider Setting.
screamer 0:e4d670b91a9a 1084 *
screamer 0:e4d670b91a9a 1085 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1086 * @return setting PLL0 External Reference Divider Setting
screamer 0:e4d670b91a9a 1087 */
screamer 0:e4d670b91a9a 1088 static inline uint8_t CLOCK_HAL_GetPllExternalRefDivider0(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1089 {
screamer 0:e4d670b91a9a 1090 return BR_MCG_C5_PRDIV0(baseAddr);
screamer 0:e4d670b91a9a 1091 }
screamer 0:e4d670b91a9a 1092
screamer 0:e4d670b91a9a 1093 /*!
screamer 0:e4d670b91a9a 1094 * @brief Sets the Loss of Lock Interrupt Enable Setting.
screamer 0:e4d670b91a9a 1095 *
screamer 0:e4d670b91a9a 1096 * This function determine whether an interrupt request is made following a loss
screamer 0:e4d670b91a9a 1097 * of lock indication. This bit only has an effect when LOLS 0 is set.
screamer 0:e4d670b91a9a 1098 *
screamer 0:e4d670b91a9a 1099 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1100 * @params enable Loss of Lock Interrupt Enable Setting
screamer 0:e4d670b91a9a 1101 * - true: Generate an interrupt request on loss of lock.
screamer 0:e4d670b91a9a 1102 * - false: No interrupt request is generated on loss of lock.
screamer 0:e4d670b91a9a 1103 */
screamer 0:e4d670b91a9a 1104 static inline void CLOCK_HAL_SetLossOfClkInt0Cmd(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 1105 {
screamer 0:e4d670b91a9a 1106 BW_MCG_C6_LOLIE0(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1107 }
screamer 0:e4d670b91a9a 1108
screamer 0:e4d670b91a9a 1109 /*!
screamer 0:e4d670b91a9a 1110 * @brief Gets the Loss of the Lock Interrupt Enable Setting.
screamer 0:e4d670b91a9a 1111 *
screamer 0:e4d670b91a9a 1112 * This function gets the Loss of the Lock Interrupt Enable Setting.
screamer 0:e4d670b91a9a 1113 *
screamer 0:e4d670b91a9a 1114 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1115 * @return enabled True if the Loss of Lock Interrupt is enabled.
screamer 0:e4d670b91a9a 1116 */
screamer 0:e4d670b91a9a 1117 static inline bool CLOCK_HAL_GetLossOfClkInt0Cmd(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1118 {
screamer 0:e4d670b91a9a 1119 return BR_MCG_C6_LOLIE0(baseAddr);
screamer 0:e4d670b91a9a 1120 }
screamer 0:e4d670b91a9a 1121
screamer 0:e4d670b91a9a 1122 /*!
screamer 0:e4d670b91a9a 1123 * @brief Sets the PLL Select Setting.
screamer 0:e4d670b91a9a 1124 *
screamer 0:e4d670b91a9a 1125 * This function controls whether the PLLCS or FLL output is selected as the
screamer 0:e4d670b91a9a 1126 * MCG source when CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN0 and
screamer 0:e4d670b91a9a 1127 * PLLCLKEN1 is not set, the PLLCS output clock is disabled in all modes. If the
screamer 0:e4d670b91a9a 1128 * PLLS is set, the FLL is disabled in all modes.
screamer 0:e4d670b91a9a 1129 *
screamer 0:e4d670b91a9a 1130 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1131 * @params setting PLL Select Setting
screamer 0:e4d670b91a9a 1132 * - 0: FLL is selected.
screamer 0:e4d670b91a9a 1133 * - 1: PLLCS output clock is selected (PRDIV0 bits of PLL in
screamer 0:e4d670b91a9a 1134 * control need to be programmed to the correct divider to
screamer 0:e4d670b91a9a 1135 * generate a PLL reference clock in the range of 1 - 32 MHz
screamer 0:e4d670b91a9a 1136 * prior to setting the PLLS bit).
screamer 0:e4d670b91a9a 1137 */
screamer 0:e4d670b91a9a 1138 static inline void CLOCK_HAL_SetPllSelMode(uint32_t baseAddr, mcg_pll_select_t setting)
screamer 0:e4d670b91a9a 1139 {
screamer 0:e4d670b91a9a 1140 BW_MCG_C6_PLLS(baseAddr, setting);
screamer 0:e4d670b91a9a 1141 }
screamer 0:e4d670b91a9a 1142
screamer 0:e4d670b91a9a 1143 /*!
screamer 0:e4d670b91a9a 1144 * @brief Gets the PLL Select Setting.
screamer 0:e4d670b91a9a 1145 *
screamer 0:e4d670b91a9a 1146 * This function gets the PLL Select Setting.
screamer 0:e4d670b91a9a 1147 *
screamer 0:e4d670b91a9a 1148 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1149 * @return setting PLL Select Setting
screamer 0:e4d670b91a9a 1150 */
screamer 0:e4d670b91a9a 1151 static inline mcg_pll_select_t CLOCK_HAL_GetPllSelMode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1152 {
screamer 0:e4d670b91a9a 1153 return (mcg_pll_select_t)BR_MCG_C6_PLLS(baseAddr);
screamer 0:e4d670b91a9a 1154 }
screamer 0:e4d670b91a9a 1155
screamer 0:e4d670b91a9a 1156 /*!
screamer 0:e4d670b91a9a 1157 * @brief Sets the VCO0 Divider Setting.
screamer 0:e4d670b91a9a 1158 *
screamer 0:e4d670b91a9a 1159 * This function selects the amount to divide the VCO output of the PLL0.
screamer 0:e4d670b91a9a 1160 * The VDIV0 bits establish the multiplication factor (M) applied to the
screamer 0:e4d670b91a9a 1161 * reference clock frequency. After the PLL0 is enabled (by setting either
screamer 0:e4d670b91a9a 1162 * PLLCLKEN0 or PLLS), the VDIV0 value must not be changed when LOCK0 is zero.
screamer 0:e4d670b91a9a 1163 *
screamer 0:e4d670b91a9a 1164 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1165 * @params setting VCO0 Divider Setting
screamer 0:e4d670b91a9a 1166 */
screamer 0:e4d670b91a9a 1167 static inline void CLOCK_HAL_SetVoltCtrlOscDivider0(uint32_t baseAddr, uint8_t setting)
screamer 0:e4d670b91a9a 1168 {
screamer 0:e4d670b91a9a 1169 BW_MCG_C6_VDIV0(baseAddr, setting);
screamer 0:e4d670b91a9a 1170 }
screamer 0:e4d670b91a9a 1171
screamer 0:e4d670b91a9a 1172 /*!
screamer 0:e4d670b91a9a 1173 * @brief Gets the VCO0 Divider Setting.
screamer 0:e4d670b91a9a 1174 *
screamer 0:e4d670b91a9a 1175 * This function gets the VCO0 Divider Setting.
screamer 0:e4d670b91a9a 1176 *
screamer 0:e4d670b91a9a 1177 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1178 * @return setting VCO0 Divider Setting
screamer 0:e4d670b91a9a 1179 */
screamer 0:e4d670b91a9a 1180 static inline uint8_t CLOCK_HAL_GetVoltCtrlOscDivider0(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1181 {
screamer 0:e4d670b91a9a 1182 return BR_MCG_C6_VDIV0(baseAddr);
screamer 0:e4d670b91a9a 1183 }
screamer 0:e4d670b91a9a 1184
screamer 0:e4d670b91a9a 1185 /*!
screamer 0:e4d670b91a9a 1186 * @brief Gets the Loss of the Lock Status.
screamer 0:e4d670b91a9a 1187 *
screamer 0:e4d670b91a9a 1188 * This function gets the Loss of Lock Status. This bit is a sticky bit indicating
screamer 0:e4d670b91a9a 1189 * the lock status for the PLL. LOLS 0 is set if after acquiring lock, the PLL
screamer 0:e4d670b91a9a 1190 * output frequency has fallen outside the lock exit frequency tolerance, D unl .
screamer 0:e4d670b91a9a 1191 * LOLIE 0 determines whether an interrupt request is made when LOLS 0 is set.
screamer 0:e4d670b91a9a 1192 * This bit is cleared by reset or by writing a logic 1 to it when set. Writing a
screamer 0:e4d670b91a9a 1193 * logic 0 to this bit has no effect.
screamer 0:e4d670b91a9a 1194 *
screamer 0:e4d670b91a9a 1195 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1196 * @return status Loss of Lock Status
screamer 0:e4d670b91a9a 1197 * - 0: PLL has not lost lock since LOLS 0 was last cleared
screamer 0:e4d670b91a9a 1198 * - 1: PLL has lost lock since LOLS 0 was last cleared
screamer 0:e4d670b91a9a 1199 */
screamer 0:e4d670b91a9a 1200 static inline mcg_loss_of_lock_status_t CLOCK_HAL_GetLossOfLock0Mode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1201 {
screamer 0:e4d670b91a9a 1202 return (mcg_loss_of_lock_status_t)BR_MCG_S_LOLS0(baseAddr);
screamer 0:e4d670b91a9a 1203 }
screamer 0:e4d670b91a9a 1204
screamer 0:e4d670b91a9a 1205 /*!
screamer 0:e4d670b91a9a 1206 * @brief Gets the Lock Status.
screamer 0:e4d670b91a9a 1207 *
screamer 0:e4d670b91a9a 1208 * This function gets the Lock Status. This bit indicates whether the PLL0 has
screamer 0:e4d670b91a9a 1209 * acquired the lock. Lock detection is disabled when not operating in either the PBE or the
screamer 0:e4d670b91a9a 1210 * PEE mode unless PLLCLKEN0=1 and the MCG is not configured in the BLPI or the BLPE mode.
screamer 0:e4d670b91a9a 1211 * While the PLL0 clock is locking to the desired frequency, MCGPLL0CLK and
screamer 0:e4d670b91a9a 1212 * MCGPLL0CLK2X are gated off until the LOCK0 bit gets asserted. If the lock
screamer 0:e4d670b91a9a 1213 * status bit is set, changing the value of the PRDIV0[2:0] bits in the C5 register
screamer 0:e4d670b91a9a 1214 * or the VDIV0[4:0] bits in the C6 register causes the lock status bit to clear
screamer 0:e4d670b91a9a 1215 * and stay cleared until the PLL0 has reacquired the lock. The loss of the PLL0 reference
screamer 0:e4d670b91a9a 1216 * clock also causes the LOCK0 bit to clear until the PLL0 has an entry into the LLS,
screamer 0:e4d670b91a9a 1217 * VLPS, or a regular Stop with PLLSTEN0=0 also causes the lock status bit to clear
screamer 0:e4d670b91a9a 1218 * and stay cleared until the stop mode is exited and the PLL0 has reacquired the lock.
screamer 0:e4d670b91a9a 1219 * Any time the PLL0 is enabled and the LOCK0 bit is cleared, the MCGPLL0CLK and
screamer 0:e4d670b91a9a 1220 * MCGPLL0CLK2X are gated off until the LOCK0 bit is reasserted.
screamer 0:e4d670b91a9a 1221 *
screamer 0:e4d670b91a9a 1222 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1223 * @return status Lock Status
screamer 0:e4d670b91a9a 1224 * - 0: PLL is currently unlocked
screamer 0:e4d670b91a9a 1225 * - 1: PLL is currently locked
screamer 0:e4d670b91a9a 1226 */
screamer 0:e4d670b91a9a 1227 static inline mcg_lock_status_t CLOCK_HAL_GetLock0Mode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1228 {
screamer 0:e4d670b91a9a 1229 return (mcg_lock_status_t)BR_MCG_S_LOCK0(baseAddr);
screamer 0:e4d670b91a9a 1230 }
screamer 0:e4d670b91a9a 1231
screamer 0:e4d670b91a9a 1232 /*!
screamer 0:e4d670b91a9a 1233 * @brief Gets the PLL Select Status.
screamer 0:e4d670b91a9a 1234 *
screamer 0:e4d670b91a9a 1235 * This function gets the PLL Select Status. This bit indicates the clock source
screamer 0:e4d670b91a9a 1236 * selected by PLLS . The PLLST bit does not update immediately after a write to
screamer 0:e4d670b91a9a 1237 * the PLLS bit due to the internal synchronization between the clock domains.
screamer 0:e4d670b91a9a 1238 *
screamer 0:e4d670b91a9a 1239 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1240 * @return status PLL Select Status
screamer 0:e4d670b91a9a 1241 * - 0: Source of PLLS clock is FLL clock.
screamer 0:e4d670b91a9a 1242 * - 1: Source of PLLS clock is PLLCS output clock.
screamer 0:e4d670b91a9a 1243 */
screamer 0:e4d670b91a9a 1244 static inline mcg_pll_stat_status_t CLOCK_HAL_GetPllStatMode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1245 {
screamer 0:e4d670b91a9a 1246 return (mcg_pll_stat_status_t)BR_MCG_S_PLLST(baseAddr);
screamer 0:e4d670b91a9a 1247 }
screamer 0:e4d670b91a9a 1248 #endif
screamer 0:e4d670b91a9a 1249
screamer 0:e4d670b91a9a 1250 /*!
screamer 0:e4d670b91a9a 1251 * @brief Gets the Internal Reference Status.
screamer 0:e4d670b91a9a 1252 *
screamer 0:e4d670b91a9a 1253 * This function gets the Internal Reference Status. This bit indicates the current
screamer 0:e4d670b91a9a 1254 * source for the FLL reference clock. The IREFST bit does not update immediately
screamer 0:e4d670b91a9a 1255 * after a write to the IREFS bit due to internal synchronization between the clock
screamer 0:e4d670b91a9a 1256 * domains.
screamer 0:e4d670b91a9a 1257 *
screamer 0:e4d670b91a9a 1258 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1259 * @return status Internal Reference Status
screamer 0:e4d670b91a9a 1260 * - 0: Source of FLL reference clock is the external reference clock.
screamer 0:e4d670b91a9a 1261 * - 1: Source of FLL reference clock is the internal reference clock.
screamer 0:e4d670b91a9a 1262 */
screamer 0:e4d670b91a9a 1263 static inline mcg_internal_ref_status_t CLOCK_HAL_GetInternalRefStatMode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1264 {
screamer 0:e4d670b91a9a 1265 return (mcg_internal_ref_status_t)BR_MCG_S_IREFST(baseAddr);
screamer 0:e4d670b91a9a 1266 }
screamer 0:e4d670b91a9a 1267
screamer 0:e4d670b91a9a 1268 /*!
screamer 0:e4d670b91a9a 1269 * @brief Gets the Clock Mode Status.
screamer 0:e4d670b91a9a 1270 *
screamer 0:e4d670b91a9a 1271 * This function gets the Clock Mode Status. These bits indicate the current clock mode.
screamer 0:e4d670b91a9a 1272 * The CLKST bits do not update immediately after a write to the CLKS bits due to
screamer 0:e4d670b91a9a 1273 * internal synchronization between clock domains.
screamer 0:e4d670b91a9a 1274 *
screamer 0:e4d670b91a9a 1275 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1276 * @return status Clock Mode Status
screamer 0:e4d670b91a9a 1277 * - 00: Output of the FLL is selected (reset default).
screamer 0:e4d670b91a9a 1278 * - 01: Internal reference clock is selected.
screamer 0:e4d670b91a9a 1279 * - 10: External reference clock is selected.
screamer 0:e4d670b91a9a 1280 * - 11: Output of the PLL is selected.
screamer 0:e4d670b91a9a 1281 */
screamer 0:e4d670b91a9a 1282 static inline mcg_clk_stat_status_t CLOCK_HAL_GetClkStatMode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1283 {
screamer 0:e4d670b91a9a 1284 return (mcg_clk_stat_status_t)BR_MCG_S_CLKST(baseAddr);
screamer 0:e4d670b91a9a 1285 }
screamer 0:e4d670b91a9a 1286
screamer 0:e4d670b91a9a 1287 /*!
screamer 0:e4d670b91a9a 1288 * @brief Gets the OSC Initialization Status.
screamer 0:e4d670b91a9a 1289 *
screamer 0:e4d670b91a9a 1290 * This function gets the OSC Initialization Status. This bit, which resets to 0, is set
screamer 0:e4d670b91a9a 1291 * to 1 after the initialization cycles of the crystal oscillator clock have completed.
screamer 0:e4d670b91a9a 1292 * After being set, the bit is cleared to 0 if the OSC is subsequently disabled. See the
screamer 0:e4d670b91a9a 1293 * OSC module's detailed description for more information.
screamer 0:e4d670b91a9a 1294 *
screamer 0:e4d670b91a9a 1295 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1296 * @return status OSC Initialization Status
screamer 0:e4d670b91a9a 1297 */
screamer 0:e4d670b91a9a 1298 static inline uint8_t CLOCK_HAL_GetOscInit0(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1299 {
screamer 0:e4d670b91a9a 1300 return BR_MCG_S_OSCINIT0(baseAddr);
screamer 0:e4d670b91a9a 1301 }
screamer 0:e4d670b91a9a 1302
screamer 0:e4d670b91a9a 1303 /*!
screamer 0:e4d670b91a9a 1304 * @brief Gets the Internal Reference Clock Status.
screamer 0:e4d670b91a9a 1305 *
screamer 0:e4d670b91a9a 1306 * This function gets the Internal Reference Clock Status. The IRCST bit indicates the
screamer 0:e4d670b91a9a 1307 * current source for the internal reference clock select clock (IRCSCLK). The IRCST bit
screamer 0:e4d670b91a9a 1308 * does not update immediately after a write to the IRCS bit due to the internal
screamer 0:e4d670b91a9a 1309 * synchronization between clock domains. The IRCST bit is only updated if the
screamer 0:e4d670b91a9a 1310 * internal reference clock is enabled, either by the MCG being in a mode that uses the
screamer 0:e4d670b91a9a 1311 * IRC or by setting the C1[IRCLKEN] bit.
screamer 0:e4d670b91a9a 1312 *
screamer 0:e4d670b91a9a 1313 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1314 * @return status Internal Reference Clock Status
screamer 0:e4d670b91a9a 1315 * - 0: Source of internal reference clock is the slow clock (32 kHz IRC).
screamer 0:e4d670b91a9a 1316 * - 1: Source of internal reference clock is the fast clock (2 MHz IRC).
screamer 0:e4d670b91a9a 1317 */
screamer 0:e4d670b91a9a 1318 static inline mcg_internal_ref_clk_status_t CLOCK_HAL_GetInternalRefClkStatMode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1319 {
screamer 0:e4d670b91a9a 1320 return (mcg_internal_ref_clk_status_t)BR_MCG_S_IRCST(baseAddr);
screamer 0:e4d670b91a9a 1321 }
screamer 0:e4d670b91a9a 1322
screamer 0:e4d670b91a9a 1323 /*!
screamer 0:e4d670b91a9a 1324 * @brief Gets the Automatic Trim machine Fail Flag.
screamer 0:e4d670b91a9a 1325 *
screamer 0:e4d670b91a9a 1326 * This function gets the Automatic Trim machine Fail Flag. This Fail flag for the
screamer 0:e4d670b91a9a 1327 * Automatic Trim Machine (ATM). This bit asserts when the Automatic Trim Machine is
screamer 0:e4d670b91a9a 1328 * enabled (ATME=1) and a write to the C1, C3, C4, and SC registers is detected or the MCG
screamer 0:e4d670b91a9a 1329 * enters into any Stop mode. A write to ATMF clears the flag.
screamer 0:e4d670b91a9a 1330 *
screamer 0:e4d670b91a9a 1331 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1332 * @return flag Automatic Trim machine Fail Flag
screamer 0:e4d670b91a9a 1333 * - 0: Automatic Trim Machine completed normally.
screamer 0:e4d670b91a9a 1334 * - 1: Automatic Trim Machine failed.
screamer 0:e4d670b91a9a 1335 */
screamer 0:e4d670b91a9a 1336 static inline mcg_auto_trim_machine_fail_status_t CLOCK_HAL_GetAutoTrimMachineFailMode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1337 {
screamer 0:e4d670b91a9a 1338 return (mcg_auto_trim_machine_fail_status_t)BR_MCG_SC_ATMF(baseAddr);
screamer 0:e4d670b91a9a 1339 }
screamer 0:e4d670b91a9a 1340
screamer 0:e4d670b91a9a 1341 /*!
screamer 0:e4d670b91a9a 1342 * @brief Sets the Automatic Trim machine Fail Flag.
screamer 0:e4d670b91a9a 1343 *
screamer 0:e4d670b91a9a 1344 * This function clears the ATMF flag.
screamer 0:e4d670b91a9a 1345 *
screamer 0:e4d670b91a9a 1346 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1347 */
screamer 0:e4d670b91a9a 1348 static inline void CLOCK_HAL_SetAutoTrimMachineFail(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1349 {
screamer 0:e4d670b91a9a 1350 BW_MCG_SC_ATMF(baseAddr, 1);
screamer 0:e4d670b91a9a 1351 }
screamer 0:e4d670b91a9a 1352
screamer 0:e4d670b91a9a 1353 /*!
screamer 0:e4d670b91a9a 1354 * @brief Gets the OSC0 Loss of Clock Status.
screamer 0:e4d670b91a9a 1355 *
screamer 0:e4d670b91a9a 1356 * This function gets the OSC0 Loss of Clock Status. The LOCS0 indicates when a loss of
screamer 0:e4d670b91a9a 1357 * OSC0 reference clock has occurred. The LOCS0 bit only has an effect when CME0 is set.
screamer 0:e4d670b91a9a 1358 * This bit is cleared by writing a logic 1 to it when set.
screamer 0:e4d670b91a9a 1359 *
screamer 0:e4d670b91a9a 1360 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1361 * @return status OSC0 Loss of Clock Status
screamer 0:e4d670b91a9a 1362 * - 0: Loss of OSC0 has not occurred.
screamer 0:e4d670b91a9a 1363 * - 1: Loss of OSC0 has occurred.
screamer 0:e4d670b91a9a 1364 */
screamer 0:e4d670b91a9a 1365 static inline mcg_locs0_status_t CLOCK_HAL_GetLocs0Mode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1366 {
screamer 0:e4d670b91a9a 1367 return (mcg_locs0_status_t)BR_MCG_SC_LOCS0(baseAddr);
screamer 0:e4d670b91a9a 1368 }
screamer 0:e4d670b91a9a 1369
screamer 0:e4d670b91a9a 1370 /*!
screamer 0:e4d670b91a9a 1371 * @brief Sets the Automatic Trim Machine Enable Setting.
screamer 0:e4d670b91a9a 1372 *
screamer 0:e4d670b91a9a 1373 * This function enables/disables the Auto Trim Machine to start automatically
screamer 0:e4d670b91a9a 1374 * trimming the selected Internal Reference Clock.
screamer 0:e4d670b91a9a 1375 * ATME de-asserts after the Auto Trim Machine has completed trimming all trim bits
screamer 0:e4d670b91a9a 1376 * of the IRCS clock selected by the ATMS bit.
screamer 0:e4d670b91a9a 1377 * Writing to C1, C3, C4, and SC registers or entering Stop mode aborts the auto
screamer 0:e4d670b91a9a 1378 * trim operation and clears this bit.
screamer 0:e4d670b91a9a 1379 *
screamer 0:e4d670b91a9a 1380 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1381 * @params enable Automatic Trim Machine Enable Setting
screamer 0:e4d670b91a9a 1382 * - true: Auto Trim Machine enabled
screamer 0:e4d670b91a9a 1383 * - false: Auto Trim Machine disabled
screamer 0:e4d670b91a9a 1384 */
screamer 0:e4d670b91a9a 1385 static inline void CLOCK_HAL_SetAutoTrimMachineCmd(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 1386 {
screamer 0:e4d670b91a9a 1387 BW_MCG_SC_ATME(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1388 }
screamer 0:e4d670b91a9a 1389
screamer 0:e4d670b91a9a 1390 /*!
screamer 0:e4d670b91a9a 1391 * @brief Gets the Automatic Trim Machine Enable Setting.
screamer 0:e4d670b91a9a 1392 *
screamer 0:e4d670b91a9a 1393 * This function gets the Automatic Trim Machine Enable Setting.
screamer 0:e4d670b91a9a 1394 *
screamer 0:e4d670b91a9a 1395 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1396 * @return enabled True if Automatic Trim Machine is enabled
screamer 0:e4d670b91a9a 1397 */
screamer 0:e4d670b91a9a 1398 static inline bool CLOCK_HAL_GetAutoTrimMachineCmd(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1399 {
screamer 0:e4d670b91a9a 1400 return BR_MCG_SC_ATME(baseAddr);
screamer 0:e4d670b91a9a 1401 }
screamer 0:e4d670b91a9a 1402
screamer 0:e4d670b91a9a 1403 /*!
screamer 0:e4d670b91a9a 1404 * @brief Sets the Automatic Trim Machine Select Setting.
screamer 0:e4d670b91a9a 1405 *
screamer 0:e4d670b91a9a 1406 * This function selects the IRCS clock for Auto Trim Test.
screamer 0:e4d670b91a9a 1407 *
screamer 0:e4d670b91a9a 1408 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1409 * @params setting Automatic Trim Machine Select Setting
screamer 0:e4d670b91a9a 1410 * - 0: 32 kHz Internal Reference Clock selected
screamer 0:e4d670b91a9a 1411 * - 1: 4 MHz Internal Reference Clock selected
screamer 0:e4d670b91a9a 1412 */
screamer 0:e4d670b91a9a 1413 static inline void CLOCK_HAL_SetAutoTrimMachineSelMode(uint32_t baseAddr,
screamer 0:e4d670b91a9a 1414 mcg_auto_trim_machine_select_t setting)
screamer 0:e4d670b91a9a 1415 {
screamer 0:e4d670b91a9a 1416 BW_MCG_SC_ATMS(baseAddr, setting);
screamer 0:e4d670b91a9a 1417 }
screamer 0:e4d670b91a9a 1418
screamer 0:e4d670b91a9a 1419 /*!
screamer 0:e4d670b91a9a 1420 * @brief Gets the Automatic Trim Machine Select Setting.
screamer 0:e4d670b91a9a 1421 *
screamer 0:e4d670b91a9a 1422 * This function gets the Automatic Trim Machine Select Setting.
screamer 0:e4d670b91a9a 1423 *
screamer 0:e4d670b91a9a 1424 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1425 * @return setting Automatic Trim Machine Select Setting
screamer 0:e4d670b91a9a 1426 */
screamer 0:e4d670b91a9a 1427 static inline mcg_auto_trim_machine_select_t CLOCK_HAL_GetAutoTrimMachineSelMode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1428 {
screamer 0:e4d670b91a9a 1429 return (mcg_auto_trim_machine_select_t)BR_MCG_SC_ATMS(baseAddr);
screamer 0:e4d670b91a9a 1430 }
screamer 0:e4d670b91a9a 1431
screamer 0:e4d670b91a9a 1432 /*!
screamer 0:e4d670b91a9a 1433 * @brief Sets the FLL Filter Preserve Enable Setting.
screamer 0:e4d670b91a9a 1434 *
screamer 0:e4d670b91a9a 1435 * This function sets the FLL Filter Preserve Enable. This bit prevents the
screamer 0:e4d670b91a9a 1436 * FLL filter values from resetting allowing the FLL output frequency to remain the
screamer 0:e4d670b91a9a 1437 * same during the clock mode changes where the FLL/DCO output is still valid.
screamer 0:e4d670b91a9a 1438 * (Note: This requires that the FLL reference frequency remain the same as
screamer 0:e4d670b91a9a 1439 * the value prior to the new clock mode switch. Otherwise, the FLL filter and the frequency
screamer 0:e4d670b91a9a 1440 * values change.)
screamer 0:e4d670b91a9a 1441 *
screamer 0:e4d670b91a9a 1442 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1443 * @params enable FLL Filter Preserve Enable Setting
screamer 0:e4d670b91a9a 1444 * - true: FLL filter and FLL frequency retain their previous values
screamer 0:e4d670b91a9a 1445 * during new clock mode change
screamer 0:e4d670b91a9a 1446 * - false: FLL filter and FLL frequency will reset on changes to correct
screamer 0:e4d670b91a9a 1447 * clock mode
screamer 0:e4d670b91a9a 1448 */
screamer 0:e4d670b91a9a 1449 static inline void CLOCK_HAL_SetFllFilterPreserveCmd(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 1450 {
screamer 0:e4d670b91a9a 1451 BW_MCG_SC_FLTPRSRV(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1452 }
screamer 0:e4d670b91a9a 1453
screamer 0:e4d670b91a9a 1454 /*!
screamer 0:e4d670b91a9a 1455 * @brief Gets the FLL Filter Preserve Enable Setting.
screamer 0:e4d670b91a9a 1456 *
screamer 0:e4d670b91a9a 1457 * This function gets the FLL Filter Preserve Enable Setting.
screamer 0:e4d670b91a9a 1458 *
screamer 0:e4d670b91a9a 1459 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1460 * @return enabled True if FLL Filter Preserve is enabled.
screamer 0:e4d670b91a9a 1461 */
screamer 0:e4d670b91a9a 1462 static inline bool CLOCK_HAL_GetFllFilterPreserveCmd(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1463 {
screamer 0:e4d670b91a9a 1464 return BR_MCG_SC_FLTPRSRV(baseAddr);
screamer 0:e4d670b91a9a 1465 }
screamer 0:e4d670b91a9a 1466
screamer 0:e4d670b91a9a 1467 /*!
screamer 0:e4d670b91a9a 1468 * @brief Sets the Fast Clock Internal Reference Divider Setting.
screamer 0:e4d670b91a9a 1469 *
screamer 0:e4d670b91a9a 1470 * This function selects the amount to divide down the fast internal reference
screamer 0:e4d670b91a9a 1471 * clock. The resulting frequency is in the range 31.25 kHz to 4 MHz.
screamer 0:e4d670b91a9a 1472 * (Note: Changing the divider when the Fast IRC is enabled is not supported).
screamer 0:e4d670b91a9a 1473 *
screamer 0:e4d670b91a9a 1474 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1475 * @params setting Fast Clock Internal Reference Divider Setting
screamer 0:e4d670b91a9a 1476 */
screamer 0:e4d670b91a9a 1477 static inline void CLOCK_HAL_SetFastClkInternalRefDivider(uint32_t baseAddr, uint8_t setting)
screamer 0:e4d670b91a9a 1478 {
screamer 0:e4d670b91a9a 1479 BW_MCG_SC_FCRDIV(baseAddr, setting);
screamer 0:e4d670b91a9a 1480 }
screamer 0:e4d670b91a9a 1481
screamer 0:e4d670b91a9a 1482 /*!
screamer 0:e4d670b91a9a 1483 * @brief Gets the Fast Clock Internal Reference Divider Setting.
screamer 0:e4d670b91a9a 1484 *
screamer 0:e4d670b91a9a 1485 * This function gets the Fast Clock Internal Reference Divider Setting.
screamer 0:e4d670b91a9a 1486 *
screamer 0:e4d670b91a9a 1487 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1488 * @return setting Fast Clock Internal Reference Divider Setting
screamer 0:e4d670b91a9a 1489 */
screamer 0:e4d670b91a9a 1490 static inline uint8_t CLOCK_HAL_GetFastClkInternalRefDivider(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1491 {
screamer 0:e4d670b91a9a 1492 return BR_MCG_SC_FCRDIV(baseAddr);
screamer 0:e4d670b91a9a 1493 }
screamer 0:e4d670b91a9a 1494
screamer 0:e4d670b91a9a 1495 /*!
screamer 0:e4d670b91a9a 1496 * @brief Sets the ATM Compare Value High Setting.
screamer 0:e4d670b91a9a 1497 *
screamer 0:e4d670b91a9a 1498 * This function sets the ATM compare value high setting. The values are used by the
screamer 0:e4d670b91a9a 1499 * Auto Trim Machine to compare and adjust the Internal Reference trim values during the ATM
screamer 0:e4d670b91a9a 1500 * SAR conversion.
screamer 0:e4d670b91a9a 1501 *
screamer 0:e4d670b91a9a 1502 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1503 * @params setting ATM Compare Value High Setting
screamer 0:e4d670b91a9a 1504 */
screamer 0:e4d670b91a9a 1505 static inline void CLOCK_HAL_SetAutoTrimMachineCompValHigh(uint32_t baseAddr, uint8_t setting)
screamer 0:e4d670b91a9a 1506 {
screamer 0:e4d670b91a9a 1507 BW_MCG_ATCVH_ATCVH(baseAddr, setting);
screamer 0:e4d670b91a9a 1508 }
screamer 0:e4d670b91a9a 1509
screamer 0:e4d670b91a9a 1510 /*!
screamer 0:e4d670b91a9a 1511 * @brief Gets the ATM Compare Value High Setting.
screamer 0:e4d670b91a9a 1512 *
screamer 0:e4d670b91a9a 1513 * This function gets the ATM Compare Value High Setting.
screamer 0:e4d670b91a9a 1514 *
screamer 0:e4d670b91a9a 1515 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1516 * @return setting ATM Compare Value High Setting
screamer 0:e4d670b91a9a 1517 */
screamer 0:e4d670b91a9a 1518 static inline uint8_t CLOCK_HAL_GetAutoTrimMachineCompValHigh(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1519 {
screamer 0:e4d670b91a9a 1520 return BR_MCG_ATCVH_ATCVH(baseAddr);
screamer 0:e4d670b91a9a 1521 }
screamer 0:e4d670b91a9a 1522
screamer 0:e4d670b91a9a 1523 /*!
screamer 0:e4d670b91a9a 1524 * @brief Sets the ATM Compare Value Low Setting.
screamer 0:e4d670b91a9a 1525 *
screamer 0:e4d670b91a9a 1526 * This function sets the ATM compare value low setting. The values are used by the
screamer 0:e4d670b91a9a 1527 * Auto Trim Machine to compare and adjust Internal Reference trim values during the ATM
screamer 0:e4d670b91a9a 1528 * SAR conversion.
screamer 0:e4d670b91a9a 1529 *
screamer 0:e4d670b91a9a 1530 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1531 * @params setting ATM Compare Value Low Setting
screamer 0:e4d670b91a9a 1532 */
screamer 0:e4d670b91a9a 1533 static inline void CLOCK_HAL_SetAutoTrimMachineCompValLow(uint32_t baseAddr, uint8_t setting)
screamer 0:e4d670b91a9a 1534 {
screamer 0:e4d670b91a9a 1535 BW_MCG_ATCVL_ATCVL(baseAddr, setting);
screamer 0:e4d670b91a9a 1536 }
screamer 0:e4d670b91a9a 1537
screamer 0:e4d670b91a9a 1538 /*!
screamer 0:e4d670b91a9a 1539 * @brief Gets the ATM Compare Value Low Setting.
screamer 0:e4d670b91a9a 1540 *
screamer 0:e4d670b91a9a 1541 * This function gets the ATM Compare Value Low Setting.
screamer 0:e4d670b91a9a 1542 *
screamer 0:e4d670b91a9a 1543 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1544 * @return setting ATM Compare Value Low Setting
screamer 0:e4d670b91a9a 1545 */
screamer 0:e4d670b91a9a 1546 static inline uint8_t CLOCK_HAL_GetAutoTrimMachineCompValLow(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1547 {
screamer 0:e4d670b91a9a 1548 return BR_MCG_ATCVL_ATCVL(baseAddr);
screamer 0:e4d670b91a9a 1549 }
screamer 0:e4d670b91a9a 1550
screamer 0:e4d670b91a9a 1551 #if FSL_FEATURE_MCG_USE_OSCSEL
screamer 0:e4d670b91a9a 1552 /*!
screamer 0:e4d670b91a9a 1553 * @brief Sets the MCG OSC Clock Select Setting.
screamer 0:e4d670b91a9a 1554 *
screamer 0:e4d670b91a9a 1555 * This function selects the MCG FLL external reference clock.
screamer 0:e4d670b91a9a 1556 *
screamer 0:e4d670b91a9a 1557 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1558 * @params setting MCG OSC Clock Select Setting
screamer 0:e4d670b91a9a 1559 * - 0: Selects System Oscillator (OSCCLK).
screamer 0:e4d670b91a9a 1560 * - 1: Selects 32 kHz RTC Oscillator.
screamer 0:e4d670b91a9a 1561 */
screamer 0:e4d670b91a9a 1562 static inline void CLOCK_HAL_SetOscselMode(uint32_t baseAddr, mcg_oscsel_select_t setting)
screamer 0:e4d670b91a9a 1563 {
screamer 0:e4d670b91a9a 1564 BW_MCG_C7_OSCSEL(baseAddr, setting);
screamer 0:e4d670b91a9a 1565 }
screamer 0:e4d670b91a9a 1566
screamer 0:e4d670b91a9a 1567 /*!
screamer 0:e4d670b91a9a 1568 * @brief Gets the MCG OSC Clock Select Setting.
screamer 0:e4d670b91a9a 1569 *
screamer 0:e4d670b91a9a 1570 * This function gets the MCG OSC Clock Select Setting.
screamer 0:e4d670b91a9a 1571 *
screamer 0:e4d670b91a9a 1572 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1573 * @return setting MCG OSC Clock Select Setting
screamer 0:e4d670b91a9a 1574 */
screamer 0:e4d670b91a9a 1575 static inline mcg_oscsel_select_t CLOCK_HAL_GetOscselMode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1576 {
screamer 0:e4d670b91a9a 1577 return (mcg_oscsel_select_t)BR_MCG_C7_OSCSEL(baseAddr);
screamer 0:e4d670b91a9a 1578 }
screamer 0:e4d670b91a9a 1579 #endif /* FSL_FEATURE_MCG_USE_OSCSEL */
screamer 0:e4d670b91a9a 1580
screamer 0:e4d670b91a9a 1581 #if FSL_FEATURE_MCG_HAS_LOLRE
screamer 0:e4d670b91a9a 1582 /*!
screamer 0:e4d670b91a9a 1583 * @brief Sets the PLL Loss of Lock Reset Enable Setting.
screamer 0:e4d670b91a9a 1584 *
screamer 0:e4d670b91a9a 1585 * This function determines whether an interrupt or a reset request is made
screamer 0:e4d670b91a9a 1586 * following a PLL loss of lock.
screamer 0:e4d670b91a9a 1587 *
screamer 0:e4d670b91a9a 1588 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1589 * @params enable PLL Loss of Lock Reset Enable Setting
screamer 0:e4d670b91a9a 1590 * - true: Generate a reset request on a PLL loss of lock indication.
screamer 0:e4d670b91a9a 1591 * - false: Interrupt request is generated on a PLL loss of lock
screamer 0:e4d670b91a9a 1592 * indication. The PLL loss of lock interrupt enable bit
screamer 0:e4d670b91a9a 1593 * must also be set to generate the interrupt request.
screamer 0:e4d670b91a9a 1594 */
screamer 0:e4d670b91a9a 1595 static inline void CLOCK_HAL_SetLossOfClkResetCmd(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 1596 {
screamer 0:e4d670b91a9a 1597 BW_MCG_C8_LOLRE(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1598 }
screamer 0:e4d670b91a9a 1599
screamer 0:e4d670b91a9a 1600 /*!
screamer 0:e4d670b91a9a 1601 * @brief Gets the PLL Loss of Lock Reset Enable Setting.
screamer 0:e4d670b91a9a 1602 *
screamer 0:e4d670b91a9a 1603 * This function gets the PLL Loss of Lock Reset Enable Setting.
screamer 0:e4d670b91a9a 1604 *
screamer 0:e4d670b91a9a 1605 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1606 * @return enabled True if the PLL Loss of Lock Reset is enabled.
screamer 0:e4d670b91a9a 1607 */
screamer 0:e4d670b91a9a 1608 static inline bool CLOCK_HAL_GetLossOfClkResetCmd(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1609 {
screamer 0:e4d670b91a9a 1610 return BR_MCG_C8_LOLRE(baseAddr);
screamer 0:e4d670b91a9a 1611 }
screamer 0:e4d670b91a9a 1612 #endif /* FSL_FEATURE_MCG_HAS_LOLRE */
screamer 0:e4d670b91a9a 1613
screamer 0:e4d670b91a9a 1614
screamer 0:e4d670b91a9a 1615 #if FSL_FEATURE_MCG_HAS_RTC_32K
screamer 0:e4d670b91a9a 1616 /*!
screamer 0:e4d670b91a9a 1617 * @brief Sets the Loss of Clock Reset Enable Setting.
screamer 0:e4d670b91a9a 1618 *
screamer 0:e4d670b91a9a 1619 * This function determines whether an interrupt or a reset request is made following
screamer 0:e4d670b91a9a 1620 * a loss of the RTC external reference clock. The LOCRE1 only has an affect when CME1
screamer 0:e4d670b91a9a 1621 * is set.
screamer 0:e4d670b91a9a 1622 *
screamer 0:e4d670b91a9a 1623 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1624 * @params enable Loss of Clock Reset Enable Setting
screamer 0:e4d670b91a9a 1625 * - true: Generate a reset request on a loss of RTC external reference clock.
screamer 0:e4d670b91a9a 1626 * - false: Interrupt request is generated on a loss of RTC external
screamer 0:e4d670b91a9a 1627 * reference clock.
screamer 0:e4d670b91a9a 1628 */
screamer 0:e4d670b91a9a 1629 static inline void CLOCK_HAL_SetLossClkReset1Cmd(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 1630 {
screamer 0:e4d670b91a9a 1631 BW_MCG_C8_LOCRE1(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1632 }
screamer 0:e4d670b91a9a 1633
screamer 0:e4d670b91a9a 1634 /*!
screamer 0:e4d670b91a9a 1635 * @brief Gets the Loss of Clock Reset Enable Setting.
screamer 0:e4d670b91a9a 1636 *
screamer 0:e4d670b91a9a 1637 * This function gets the Loss of Clock Reset Enable Setting.
screamer 0:e4d670b91a9a 1638 *
screamer 0:e4d670b91a9a 1639 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1640 * @return enabled True if Loss of Clock Reset is enabled.
screamer 0:e4d670b91a9a 1641 */
screamer 0:e4d670b91a9a 1642 static inline bool CLOCK_HAL_GetLossClkReset1Cmd(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1643 {
screamer 0:e4d670b91a9a 1644 return BR_MCG_C8_LOCRE1(baseAddr);
screamer 0:e4d670b91a9a 1645 }
screamer 0:e4d670b91a9a 1646
screamer 0:e4d670b91a9a 1647 /*!
screamer 0:e4d670b91a9a 1648 * @brief Sets the Clock Monitor Enable1 Setting.
screamer 0:e4d670b91a9a 1649 *
screamer 0:e4d670b91a9a 1650 * This function enables/disables the loss of the clock monitoring circuit for the
screamer 0:e4d670b91a9a 1651 * output of the RTC external reference clock. The LOCRE1 bit determines whether an
screamer 0:e4d670b91a9a 1652 * interrupt or a reset request is generated following a loss of the RTC clock indication.
screamer 0:e4d670b91a9a 1653 * The CME1 bit should only be set to a logic 1 when the MCG is in an operational mode
screamer 0:e4d670b91a9a 1654 * that uses the external clock (FEE, FBE, PEE, PBE, or BLPE). CME1 bit must be set to
screamer 0:e4d670b91a9a 1655 * a logic 0 before the MCG enters any Stop mode. Otherwise, a reset request may occur
screamer 0:e4d670b91a9a 1656 * while in Stop mode. CME1 should also be set to a logic 0 before entering VLPR or
screamer 0:e4d670b91a9a 1657 * VLPW power modes if the MCG is in BLPE mode.
screamer 0:e4d670b91a9a 1658 *
screamer 0:e4d670b91a9a 1659 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1660 * @params enable Clock Monitor Enable1 Setting
screamer 0:e4d670b91a9a 1661 * - true: External clock monitor is enabled for RTC clock.
screamer 0:e4d670b91a9a 1662 * - false: External clock monitor is disabled for RTC clock.
screamer 0:e4d670b91a9a 1663 */
screamer 0:e4d670b91a9a 1664 static inline void CLOCK_HAL_SetClkMonitor1Cmd(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 1665 {
screamer 0:e4d670b91a9a 1666 BW_MCG_C8_CME1(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1667 }
screamer 0:e4d670b91a9a 1668
screamer 0:e4d670b91a9a 1669 /*!
screamer 0:e4d670b91a9a 1670 * @brief Gets the Clock Monitor Enable1 Setting.
screamer 0:e4d670b91a9a 1671 *
screamer 0:e4d670b91a9a 1672 * This function gets the Clock Monitor Enable1 Setting.
screamer 0:e4d670b91a9a 1673 *
screamer 0:e4d670b91a9a 1674 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1675 * @return enabled True if Clock Monitor Enable1 is enabled
screamer 0:e4d670b91a9a 1676 */
screamer 0:e4d670b91a9a 1677 static inline bool CLOCK_HAL_GetClkMonitor1Cmd(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1678 {
screamer 0:e4d670b91a9a 1679 return BR_MCG_C8_CME1(baseAddr);
screamer 0:e4d670b91a9a 1680 }
screamer 0:e4d670b91a9a 1681
screamer 0:e4d670b91a9a 1682 /*!
screamer 0:e4d670b91a9a 1683 * @brief Gets the RTC Loss of Clock Status.
screamer 0:e4d670b91a9a 1684 *
screamer 0:e4d670b91a9a 1685 * This function gets the RTC Loss of Clock Status. This bit indicates when a loss
screamer 0:e4d670b91a9a 1686 * of clock has occurred. This bit is cleared by writing a logic 1 to it when set.
screamer 0:e4d670b91a9a 1687 *
screamer 0:e4d670b91a9a 1688 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1689 * @return status RTC Loss of Clock Status
screamer 0:e4d670b91a9a 1690 * - 0: Loss of RTC has not occurred
screamer 0:e4d670b91a9a 1691 * - 1: Loss of RTC has occurred
screamer 0:e4d670b91a9a 1692 */
screamer 0:e4d670b91a9a 1693 static inline mcg_loss_of_clk1_status_t CLOCK_HAL_GetLossOfClk1Mode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1694 {
screamer 0:e4d670b91a9a 1695 return (mcg_loss_of_clk1_status_t)BR_MCG_C8_LOCS1(baseAddr);
screamer 0:e4d670b91a9a 1696 }
screamer 0:e4d670b91a9a 1697 #endif /* FSL_FEATURE_MCG_HAS_RTC_32K */
screamer 0:e4d670b91a9a 1698
screamer 0:e4d670b91a9a 1699 #if FSL_FEATURE_MCG_USE_PLLREFSEL
screamer 0:e4d670b91a9a 1700 /*!
screamer 0:e4d670b91a9a 1701 * @brief Sets the OSC1 Loss of Clock Reset Enable Setting.
screamer 0:e4d670b91a9a 1702 *
screamer 0:e4d670b91a9a 1703 * This function determines whether an interrupt or reset request is made following
screamer 0:e4d670b91a9a 1704 * a loss of OSC1 external reference clock. The LOCRE2 only has an affect when
screamer 0:e4d670b91a9a 1705 * LOCS2 is set.
screamer 0:e4d670b91a9a 1706 *
screamer 0:e4d670b91a9a 1707 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1708 * @params enable OSC1 Loss of Clock Reset Enable Setting
screamer 0:e4d670b91a9a 1709 * - true: Reset request is generated on a loss of OSC1 external
screamer 0:e4d670b91a9a 1710 * reference clock..
screamer 0:e4d670b91a9a 1711 * - false: Interrupt request is generated on a loss of OSC1 external
screamer 0:e4d670b91a9a 1712 * reference clock.
screamer 0:e4d670b91a9a 1713 */
screamer 0:e4d670b91a9a 1714 static inline void CLOCK_HAL_SetLossClkReset2Cmd(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 1715 {
screamer 0:e4d670b91a9a 1716 BW_MCG_C10_LOCRE2(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1717 }
screamer 0:e4d670b91a9a 1718
screamer 0:e4d670b91a9a 1719 /*!
screamer 0:e4d670b91a9a 1720 * @brief Gets the OSC1 Loss of the Clock Reset Enable Setting.
screamer 0:e4d670b91a9a 1721 *
screamer 0:e4d670b91a9a 1722 * This function gets the OSC1 Loss of Clock Reset Enable Setting.
screamer 0:e4d670b91a9a 1723 *
screamer 0:e4d670b91a9a 1724 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1725 * @return enabled True if OSC1 Loss of Clock Reset is enabled.
screamer 0:e4d670b91a9a 1726 */
screamer 0:e4d670b91a9a 1727 static inline bool CLOCK_HAL_GetLossClkReset2Cmd(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1728 {
screamer 0:e4d670b91a9a 1729 return BR_MCG_C10_LOCRE2(baseAddr);
screamer 0:e4d670b91a9a 1730 }
screamer 0:e4d670b91a9a 1731
screamer 0:e4d670b91a9a 1732 /*!
screamer 0:e4d670b91a9a 1733 * @brief Sets the Frequency Range1 Select Setting.
screamer 0:e4d670b91a9a 1734 *
screamer 0:e4d670b91a9a 1735 * This function selects the frequency range for the OSC1 crystal oscillator
screamer 0:e4d670b91a9a 1736 * or an external clock source. See the Oscillator chapter for more details and
screamer 0:e4d670b91a9a 1737 * the device data sheet for the frequency ranges used.
screamer 0:e4d670b91a9a 1738 *
screamer 0:e4d670b91a9a 1739 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1740 * @params setting Frequency Range1 Select Setting
screamer 0:e4d670b91a9a 1741 * - 00: Low frequency range selected for the crystal oscillator.
screamer 0:e4d670b91a9a 1742 * - 01: High frequency range selected for the crystal oscillator.
screamer 0:e4d670b91a9a 1743 * - 1X: Very high frequency range selected for the crystal oscillator.
screamer 0:e4d670b91a9a 1744 */
screamer 0:e4d670b91a9a 1745 static inline void CLOCK_HAL_SetRange1Mode(uint32_t baseAddr, mcg_freq_range_select_t setting)
screamer 0:e4d670b91a9a 1746 {
screamer 0:e4d670b91a9a 1747 BW_MCG_C10_RANGE1(baseAddr, setting);
screamer 0:e4d670b91a9a 1748 }
screamer 0:e4d670b91a9a 1749
screamer 0:e4d670b91a9a 1750 /*!
screamer 0:e4d670b91a9a 1751 * @brief Gets the Frequency Range1 Select Setting.
screamer 0:e4d670b91a9a 1752 *
screamer 0:e4d670b91a9a 1753 * This function gets the Frequency Range1 Select Setting.
screamer 0:e4d670b91a9a 1754 *
screamer 0:e4d670b91a9a 1755 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1756 * @return setting Frequency Range1 Select Setting
screamer 0:e4d670b91a9a 1757 */
screamer 0:e4d670b91a9a 1758 static inline mcg_freq_range_select_t CLOCK_HAL_GetRange1Mode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1759 {
screamer 0:e4d670b91a9a 1760 return (mcg_freq_range_select_t)BR_MCG_C10_RANGE1(baseAddr);
screamer 0:e4d670b91a9a 1761 }
screamer 0:e4d670b91a9a 1762
screamer 0:e4d670b91a9a 1763 /*!
screamer 0:e4d670b91a9a 1764 * @brief Sets the High Gain Oscillator1 Select Setting.
screamer 0:e4d670b91a9a 1765 *
screamer 0:e4d670b91a9a 1766 * This function controls the OSC1 crystal oscillator mode of operation.
screamer 0:e4d670b91a9a 1767 * See the Oscillator chapter for more details.
screamer 0:e4d670b91a9a 1768 *
screamer 0:e4d670b91a9a 1769 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1770 * @params setting High Gain Oscillator1 Select Setting
screamer 0:e4d670b91a9a 1771 * - 0: Configure crystal oscillator for low-power operation.
screamer 0:e4d670b91a9a 1772 * - 1: Configure crystal oscillator for high-gain operation.
screamer 0:e4d670b91a9a 1773 */
screamer 0:e4d670b91a9a 1774 static inline void CLOCK_HAL_SetHighGainOsc1Mode(uint32_t baseAddr,
screamer 0:e4d670b91a9a 1775 mcg_high_gain_osc_select_t setting)
screamer 0:e4d670b91a9a 1776 {
screamer 0:e4d670b91a9a 1777 BW_MCG_C10_HGO1(baseAddr, setting);
screamer 0:e4d670b91a9a 1778 }
screamer 0:e4d670b91a9a 1779
screamer 0:e4d670b91a9a 1780 /*!
screamer 0:e4d670b91a9a 1781 * @brief Gets the High Gain Oscillator1 Select Setting.
screamer 0:e4d670b91a9a 1782 *
screamer 0:e4d670b91a9a 1783 * This function gets the High Gain Oscillator1 Select Setting.
screamer 0:e4d670b91a9a 1784 *
screamer 0:e4d670b91a9a 1785 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1786 * @return setting High Gain Oscillator1 Select Setting
screamer 0:e4d670b91a9a 1787 */
screamer 0:e4d670b91a9a 1788 static inline mcg_high_gain_osc_select_t CLOCK_HAL_GetHighGainOsc1Mode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1789 {
screamer 0:e4d670b91a9a 1790 return (mcg_high_gain_osc_select_t)BR_MCG_C10_HGO1(baseAddr);
screamer 0:e4d670b91a9a 1791 }
screamer 0:e4d670b91a9a 1792
screamer 0:e4d670b91a9a 1793 /*!
screamer 0:e4d670b91a9a 1794 * @brief Sets the External Reference Select Setting.
screamer 0:e4d670b91a9a 1795 *
screamer 0:e4d670b91a9a 1796 * This function selects the source for the OSC1 external reference clock.
screamer 0:e4d670b91a9a 1797 * See the Oscillator chapter for more details.
screamer 0:e4d670b91a9a 1798 *
screamer 0:e4d670b91a9a 1799 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1800 * @params setting External Reference Select Setting
screamer 0:e4d670b91a9a 1801 * - 0: External reference clock requested.
screamer 0:e4d670b91a9a 1802 * - 1: Oscillator requested.
screamer 0:e4d670b91a9a 1803 */
screamer 0:e4d670b91a9a 1804 static inline void CLOCK_HAL_SetExternalRefSel1Mode(uint32_t baseAddr,
screamer 0:e4d670b91a9a 1805 mcg_external_ref_clock_select_t setting)
screamer 0:e4d670b91a9a 1806 {
screamer 0:e4d670b91a9a 1807 BW_MCG_C10_EREFS1(baseAddr, setting);
screamer 0:e4d670b91a9a 1808 }
screamer 0:e4d670b91a9a 1809
screamer 0:e4d670b91a9a 1810 /*!
screamer 0:e4d670b91a9a 1811 * @brief Gets the External Reference Select Setting.
screamer 0:e4d670b91a9a 1812 *
screamer 0:e4d670b91a9a 1813 * This function gets the External Reference Select Setting.
screamer 0:e4d670b91a9a 1814 *
screamer 0:e4d670b91a9a 1815 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1816 * @return setting External Reference Select Setting
screamer 0:e4d670b91a9a 1817 */
screamer 0:e4d670b91a9a 1818 static inline mcg_external_ref_clock_select_t CLOCK_HAL_GetExternalRefSel1Mode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1819 {
screamer 0:e4d670b91a9a 1820 return (mcg_external_ref_clock_select_t)BR_MCG_C10_EREFS1(baseAddr);
screamer 0:e4d670b91a9a 1821 }
screamer 0:e4d670b91a9a 1822
screamer 0:e4d670b91a9a 1823 /*!
screamer 0:e4d670b91a9a 1824 * @brief Sets the PLL1 External Reference Select Setting.
screamer 0:e4d670b91a9a 1825 *
screamer 0:e4d670b91a9a 1826 * This function selects the PLL1 external reference clock source.
screamer 0:e4d670b91a9a 1827 *
screamer 0:e4d670b91a9a 1828 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1829 * @params setting PLL1 External Reference Select Setting
screamer 0:e4d670b91a9a 1830 * - 0: Selects OSC0 clock source as its external reference clock.
screamer 0:e4d670b91a9a 1831 * - 1: Selects OSC1 clock source as its external reference clock.
screamer 0:e4d670b91a9a 1832 */
screamer 0:e4d670b91a9a 1833 static inline void CLOCK_HAL_SetPllRefSel1Mode(uint32_t baseAddr,
screamer 0:e4d670b91a9a 1834 mcg_pll_external_ref_clk_select_t setting)
screamer 0:e4d670b91a9a 1835 {
screamer 0:e4d670b91a9a 1836 BW_MCG_C11_PLLREFSEL1(baseAddr, setting);
screamer 0:e4d670b91a9a 1837 }
screamer 0:e4d670b91a9a 1838
screamer 0:e4d670b91a9a 1839 /*!
screamer 0:e4d670b91a9a 1840 * @brief Gets the PLL1 External Reference Select Setting.
screamer 0:e4d670b91a9a 1841 *
screamer 0:e4d670b91a9a 1842 * This function gets the PLL1 External Reference Select Setting.
screamer 0:e4d670b91a9a 1843 *
screamer 0:e4d670b91a9a 1844 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1845 * @return setting PLL1 External Reference Select Setting
screamer 0:e4d670b91a9a 1846 */
screamer 0:e4d670b91a9a 1847 static inline mcg_pll_external_ref_clk_select_t CLOCK_HAL_GetPllRefSel1Mode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1848 {
screamer 0:e4d670b91a9a 1849 return (mcg_pll_external_ref_clk_select_t)BR_MCG_C11_PLLREFSEL1(baseAddr);
screamer 0:e4d670b91a9a 1850 }
screamer 0:e4d670b91a9a 1851
screamer 0:e4d670b91a9a 1852 /*!
screamer 0:e4d670b91a9a 1853 * @brief Sets the PLL1 Clock Enable Setting.
screamer 0:e4d670b91a9a 1854 *
screamer 0:e4d670b91a9a 1855 * This function enables/disables the PLL1 independent of PLLS and enables the
screamer 0:e4d670b91a9a 1856 * PLL clocks for use as MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X. (PRDIV1 needs
screamer 0:e4d670b91a9a 1857 * to be programmed to the correct divider to generate a PLL1 reference clock in a
screamer 0:e4d670b91a9a 1858 * valid reference range prior to setting the PLLCLKEN1 bit.) Setting PLLCLKEN1
screamer 0:e4d670b91a9a 1859 * enables the PLL1 selected external oscillator if not already enabled.
screamer 0:e4d670b91a9a 1860 * Whenever the PLL1 is enabled with the PLLCLKEN1 bit, and the
screamer 0:e4d670b91a9a 1861 * external oscillator is used as the reference clock, the OSCINIT1 bit should
screamer 0:e4d670b91a9a 1862 * be checked to make sure it is set.
screamer 0:e4d670b91a9a 1863 *
screamer 0:e4d670b91a9a 1864 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1865 * @params enable PLL1 Clock Enable Setting
screamer 0:e4d670b91a9a 1866 * - true: MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X are active unless
screamer 0:e4d670b91a9a 1867 * MCG is in a bypass mode with LP=1 (BLPI or BLPE).
screamer 0:e4d670b91a9a 1868 * - false: MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X are inactive.
screamer 0:e4d670b91a9a 1869 */
screamer 0:e4d670b91a9a 1870 static inline void CLOCK_HAL_SetPllClk1Cmd(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 1871 {
screamer 0:e4d670b91a9a 1872 BW_MCG_C11_PLLCLKEN1(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1873 }
screamer 0:e4d670b91a9a 1874
screamer 0:e4d670b91a9a 1875 /*!
screamer 0:e4d670b91a9a 1876 * @brief Gets the PLL1 Clock Enable Setting.
screamer 0:e4d670b91a9a 1877 *
screamer 0:e4d670b91a9a 1878 * This function gets the PLL1 Clock Enable Setting.
screamer 0:e4d670b91a9a 1879 *
screamer 0:e4d670b91a9a 1880 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1881 * @return enabled True if the PLL1 Clock is enabled.
screamer 0:e4d670b91a9a 1882 */
screamer 0:e4d670b91a9a 1883 static inline bool CLOCK_HAL_GetPllClk1Cmd(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1884 {
screamer 0:e4d670b91a9a 1885 return BR_MCG_C11_PLLCLKEN1(baseAddr);
screamer 0:e4d670b91a9a 1886 }
screamer 0:e4d670b91a9a 1887
screamer 0:e4d670b91a9a 1888 /*!
screamer 0:e4d670b91a9a 1889 * @brief Sets the PLL1 Stop Enable Setting.
screamer 0:e4d670b91a9a 1890 *
screamer 0:e4d670b91a9a 1891 * This function enables/disables the PLL1 Clock during the Normal Stop (In Low
screamer 0:e4d670b91a9a 1892 * Power Stop modes, the PLL1 clock gets disabled even if PLLSTEN1=1. In all other
screamer 0:e4d670b91a9a 1893 * power modes, PLLSTEN1 bit has no affect and does not enable the PLL1 Clock to
screamer 0:e4d670b91a9a 1894 * run if it is written to 1.
screamer 0:e4d670b91a9a 1895 *
screamer 0:e4d670b91a9a 1896 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1897 * @params enable PLL1 Stop Enable Setting
screamer 0:e4d670b91a9a 1898 * - true: PLL1 and its clocks (MCGPLL1CLK, MCGPLL1CLK2X, and
screamer 0:e4d670b91a9a 1899 * MCGDDRCLK2X) are enabled if system is in Normal Stop mode.
screamer 0:e4d670b91a9a 1900 * - false: PLL1 clocks (MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X)
screamer 0:e4d670b91a9a 1901 * are disabled in any of the Stop modes.
screamer 0:e4d670b91a9a 1902 */
screamer 0:e4d670b91a9a 1903 static inline void CLOCK_HAL_SetPllStop1Cmd(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 1904 {
screamer 0:e4d670b91a9a 1905 BW_MCG_C11_PLLSTEN1(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1906 }
screamer 0:e4d670b91a9a 1907
screamer 0:e4d670b91a9a 1908 /*!
screamer 0:e4d670b91a9a 1909 * @brief Gets the PLL1 Stop Enable Setting.
screamer 0:e4d670b91a9a 1910 *
screamer 0:e4d670b91a9a 1911 * This function gets the PLL1 Stop Enable Setting.
screamer 0:e4d670b91a9a 1912 *
screamer 0:e4d670b91a9a 1913 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1914 * @return enabled True if PLL1 Stop is enabled.
screamer 0:e4d670b91a9a 1915 */
screamer 0:e4d670b91a9a 1916 static inline bool CLOCK_HAL_GetPllStop1Cmd(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1917 {
screamer 0:e4d670b91a9a 1918 return BR_MCG_C11_PLLSTEN1(baseAddr);
screamer 0:e4d670b91a9a 1919 }
screamer 0:e4d670b91a9a 1920
screamer 0:e4d670b91a9a 1921 /*!
screamer 0:e4d670b91a9a 1922 * @brief Sets the PLL Clock Select Setting.
screamer 0:e4d670b91a9a 1923 *
screamer 0:e4d670b91a9a 1924 * This function controls whether the PLL0 or PLL1 output is selected as the
screamer 0:e4d670b91a9a 1925 * MCG source when CLKS are programmed in PLL Engaged External (PEE) mode
screamer 0:e4d670b91a9a 1926 * (CLKS[1:0]=00 and IREFS=0 and PLLS=1).
screamer 0:e4d670b91a9a 1927 *
screamer 0:e4d670b91a9a 1928 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1929 * @params setting PLL Clock Select Setting
screamer 0:e4d670b91a9a 1930 * - 0: PLL0 output clock is selected.
screamer 0:e4d670b91a9a 1931 * - 1: PLL1 output clock is selected.
screamer 0:e4d670b91a9a 1932 */
screamer 0:e4d670b91a9a 1933 static inline void CLOCK_HAL_SetPllClkSelMode(uint32_t baseAddr, mcg_pll_clk_select_t setting)
screamer 0:e4d670b91a9a 1934 {
screamer 0:e4d670b91a9a 1935 BW_MCG_C11_PLLCS(baseAddr, setting);
screamer 0:e4d670b91a9a 1936 }
screamer 0:e4d670b91a9a 1937
screamer 0:e4d670b91a9a 1938 /*!
screamer 0:e4d670b91a9a 1939 * @brief Gets the PLL Clock Select Setting.
screamer 0:e4d670b91a9a 1940 *
screamer 0:e4d670b91a9a 1941 * This function gets the PLL Clock Select Setting.
screamer 0:e4d670b91a9a 1942 *
screamer 0:e4d670b91a9a 1943 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1944 * @return setting PLL Clock Select Setting
screamer 0:e4d670b91a9a 1945 */
screamer 0:e4d670b91a9a 1946 static inline mcg_pll_clk_select_t CLOCK_HAL_GetPllClkSelMode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1947 {
screamer 0:e4d670b91a9a 1948 return (mcg_pll_clk_select_t)BR_MCG_C11_PLLCS(baseAddr);
screamer 0:e4d670b91a9a 1949 }
screamer 0:e4d670b91a9a 1950
screamer 0:e4d670b91a9a 1951 /*!
screamer 0:e4d670b91a9a 1952 * @brief Sets the PLL1 External Reference Divider Setting.
screamer 0:e4d670b91a9a 1953 *
screamer 0:e4d670b91a9a 1954 * This function selects the amount to divide down the external reference
screamer 0:e4d670b91a9a 1955 * clock selected by REFSEL2 for PLL1. The resulting frequency must be in a valid
screamer 0:e4d670b91a9a 1956 * reference range. After the PLL1 is enabled (by setting either PLLCLKEN1 or PLLS),
screamer 0:e4d670b91a9a 1957 * the PRDIV1 value must not be changed when LOCK1 is zero.
screamer 0:e4d670b91a9a 1958 *
screamer 0:e4d670b91a9a 1959 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1960 * @params setting PLL1 External Reference Divider Setting
screamer 0:e4d670b91a9a 1961 */
screamer 0:e4d670b91a9a 1962 static inline void CLOCK_HAL_SetPllExternalRefDivider1(uint32_t baseAddr, uint8_t setting)
screamer 0:e4d670b91a9a 1963 {
screamer 0:e4d670b91a9a 1964 BW_MCG_C11_PRDIV1(baseAddr, setting);
screamer 0:e4d670b91a9a 1965 }
screamer 0:e4d670b91a9a 1966
screamer 0:e4d670b91a9a 1967 /*!
screamer 0:e4d670b91a9a 1968 * @brief Gets the PLL1 External Reference Divider Setting.
screamer 0:e4d670b91a9a 1969 *
screamer 0:e4d670b91a9a 1970 * This function gets the PLL1 External Reference Divider Setting.
screamer 0:e4d670b91a9a 1971 *
screamer 0:e4d670b91a9a 1972 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1973 * @return setting PLL1 External Reference Divider Setting
screamer 0:e4d670b91a9a 1974 */
screamer 0:e4d670b91a9a 1975 static inline uint8_t CLOCK_HAL_GetPllExternalRefDivider1(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1976 {
screamer 0:e4d670b91a9a 1977 return BR_MCG_C11_PRDIV1(baseAddr);
screamer 0:e4d670b91a9a 1978 }
screamer 0:e4d670b91a9a 1979
screamer 0:e4d670b91a9a 1980 /*!
screamer 0:e4d670b91a9a 1981 * @brief Sets the PLL1 Loss of Lock Interrupt Enable Setting.
screamer 0:e4d670b91a9a 1982 *
screamer 0:e4d670b91a9a 1983 * This function determines whether an interrupt request is made following a
screamer 0:e4d670b91a9a 1984 * loss of lock indication for PLL1. This bit only has an affect when LOLS1 is set.
screamer 0:e4d670b91a9a 1985 *
screamer 0:e4d670b91a9a 1986 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 1987 * @params enable PLL1 Loss of Lock Interrupt Enable Setting
screamer 0:e4d670b91a9a 1988 * - true: Generate an interrupt request on loss of lock on PLL1.
screamer 0:e4d670b91a9a 1989 * - false: No interrupt request is generated on loss of lock on PLL1.
screamer 0:e4d670b91a9a 1990 */
screamer 0:e4d670b91a9a 1991 static inline void CLOCK_HAL_SetLossOfLock1Cmd(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 1992 {
screamer 0:e4d670b91a9a 1993 BW_MCG_C12_LOLIE1(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1994 }
screamer 0:e4d670b91a9a 1995
screamer 0:e4d670b91a9a 1996 /*!
screamer 0:e4d670b91a9a 1997 * @brief Gets the PLL1 Loss of Lock Interrupt Enable Setting.
screamer 0:e4d670b91a9a 1998 *
screamer 0:e4d670b91a9a 1999 * This function gets the PLL1 Loss of Lock Interrupt Enable Setting.
screamer 0:e4d670b91a9a 2000 *
screamer 0:e4d670b91a9a 2001 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 2002 * @return enabled true if PLL1 Loss of Lock Interrupt is enabled.
screamer 0:e4d670b91a9a 2003 */
screamer 0:e4d670b91a9a 2004 static inline bool CLOCK_HAL_GetLossOfLock1Cmd(uint32_t baseAddr)
screamer 0:e4d670b91a9a 2005 {
screamer 0:e4d670b91a9a 2006 return BR_MCG_C12_LOLIE1(baseAddr);
screamer 0:e4d670b91a9a 2007 }
screamer 0:e4d670b91a9a 2008
screamer 0:e4d670b91a9a 2009 /*!
screamer 0:e4d670b91a9a 2010 * @brief Sets the Clock Monitor Enable2 Setting
screamer 0:e4d670b91a9a 2011 *
screamer 0:e4d670b91a9a 2012 * This function enables/disables the loss of the clock monitor for the OSC1 external
screamer 0:e4d670b91a9a 2013 * reference clock. LOCRE2 determines whether a reset or interrupt request is generated
screamer 0:e4d670b91a9a 2014 * following a loss of OSC1 external reference clock. The CME2 bit should only be set
screamer 0:e4d670b91a9a 2015 * to a logic 1 when the MCG is in an operational mode that uses the external clock
screamer 0:e4d670b91a9a 2016 * (PEE or PBE) . Whenever the CME2 bit is set to a logic 1, the value of the RANGE1
screamer 0:e4d670b91a9a 2017 * bits in the C10 register should not be changed. CME2 bit should be set to a logic 0
screamer 0:e4d670b91a9a 2018 * before the MCG enters any Stop mode. Otherwise, a reset request may occur while in
screamer 0:e4d670b91a9a 2019 * Stop mode.
screamer 0:e4d670b91a9a 2020 *
screamer 0:e4d670b91a9a 2021 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 2022 * @params enable Clock Monitor Enable2 Setting
screamer 0:e4d670b91a9a 2023 * - true: Generate a reset request on loss of external clock on OSC1.
screamer 0:e4d670b91a9a 2024 * - false: External clock monitor for OSC1 is disabled.
screamer 0:e4d670b91a9a 2025 */
screamer 0:e4d670b91a9a 2026 static inline void CLOCK_HAL_SetClkMonitor2Cmd(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 2027 {
screamer 0:e4d670b91a9a 2028 BW_MCG_C12_CME2(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 2029 }
screamer 0:e4d670b91a9a 2030
screamer 0:e4d670b91a9a 2031 /*!
screamer 0:e4d670b91a9a 2032 * @brief Gets the Clock Monitor Enable2 Setting.
screamer 0:e4d670b91a9a 2033 *
screamer 0:e4d670b91a9a 2034 * This function gets the Clock Monitor Enable2 Setting.
screamer 0:e4d670b91a9a 2035 *
screamer 0:e4d670b91a9a 2036 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 2037 * @return enabled True if Clock Monitor Enable2 is enabled.
screamer 0:e4d670b91a9a 2038 */
screamer 0:e4d670b91a9a 2039 static inline bool CLOCK_HAL_GetClkMonitor2Cmd(uint32_t baseAddr)
screamer 0:e4d670b91a9a 2040 {
screamer 0:e4d670b91a9a 2041 return BR_MCG_C12_CME2(baseAddr);
screamer 0:e4d670b91a9a 2042 }
screamer 0:e4d670b91a9a 2043
screamer 0:e4d670b91a9a 2044 /*!
screamer 0:e4d670b91a9a 2045 * @brief Sets the VCO1 Divider Setting.
screamer 0:e4d670b91a9a 2046 *
screamer 0:e4d670b91a9a 2047 * This function selects the amount to divide the VCO output of the PLL1.
screamer 0:e4d670b91a9a 2048 * The VDIV1 bits establishes the multiplication factor (M) applied to the reference
screamer 0:e4d670b91a9a 2049 * clock frequency. After the PLL1 is enabled (by setting either PLLCLKEN1 or
screamer 0:e4d670b91a9a 2050 * PLLS), the VDIV1 value must not be changed when LOCK1 is zero.
screamer 0:e4d670b91a9a 2051 *
screamer 0:e4d670b91a9a 2052 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 2053 * @params setting VCO1 Divider Setting
screamer 0:e4d670b91a9a 2054 */
screamer 0:e4d670b91a9a 2055 static inline void CLOCK_HAL_SetVoltCtrlOscDivider1(uint32_t baseAddr, uint8_t setting)
screamer 0:e4d670b91a9a 2056 {
screamer 0:e4d670b91a9a 2057 BW_MCG_C12_VDIV1(baseAddr, setting);
screamer 0:e4d670b91a9a 2058 }
screamer 0:e4d670b91a9a 2059
screamer 0:e4d670b91a9a 2060 /*!
screamer 0:e4d670b91a9a 2061 * @brief Gets the VCO1 Divider Setting.
screamer 0:e4d670b91a9a 2062 *
screamer 0:e4d670b91a9a 2063 * This function gets the VCO1 Divider Setting.
screamer 0:e4d670b91a9a 2064 *
screamer 0:e4d670b91a9a 2065 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 2066 * @return setting VCO1 Divider Setting
screamer 0:e4d670b91a9a 2067 */
screamer 0:e4d670b91a9a 2068 static inline uint8_t CLOCK_HAL_GetVoltCtrlOscDivider1(uint32_t baseAddr)
screamer 0:e4d670b91a9a 2069 {
screamer 0:e4d670b91a9a 2070 return BR_MCG_C12_VDIV1(baseAddr);
screamer 0:e4d670b91a9a 2071 }
screamer 0:e4d670b91a9a 2072
screamer 0:e4d670b91a9a 2073 /*!
screamer 0:e4d670b91a9a 2074 * @brief Gets the Loss of the Lock2 Status.
screamer 0:e4d670b91a9a 2075 *
screamer 0:e4d670b91a9a 2076 * This function gets the Loss of the Lock2 Status. This bit is a sticky bit indicating
screamer 0:e4d670b91a9a 2077 * the lock status for the PLL1. LOLS1 is set if after acquiring lock, the PLL1
screamer 0:e4d670b91a9a 2078 * output frequency has fallen outside the lock exit frequency tolerance, D unl.
screamer 0:e4d670b91a9a 2079 * LOLIE1 determines whether an interrupt request is made when LOLS1 is set. This
screamer 0:e4d670b91a9a 2080 * bit is cleared by reset or by writing a logic 1 to it when set. Writing a logic 0
screamer 0:e4d670b91a9a 2081 * to this bit has no effect.
screamer 0:e4d670b91a9a 2082 *
screamer 0:e4d670b91a9a 2083 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 2084 * @return status Loss of Lock2 Status
screamer 0:e4d670b91a9a 2085 * - 0: PLL1 has not lost lock since LOLS1 was last cleared.
screamer 0:e4d670b91a9a 2086 * - 1: PLL1 has lost lock since LOLS1 was last cleared.
screamer 0:e4d670b91a9a 2087 */
screamer 0:e4d670b91a9a 2088 static inline mcg_loss_of_lock_status_t CLOCK_HAL_GetLossOfLock1Mode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 2089 {
screamer 0:e4d670b91a9a 2090 return (mcg_loss_of_lock_status_t)BR_MCG_S2_LOLS1(baseAddr);
screamer 0:e4d670b91a9a 2091 }
screamer 0:e4d670b91a9a 2092
screamer 0:e4d670b91a9a 2093 /*!
screamer 0:e4d670b91a9a 2094 * @brief Gets the Lock1 Status.
screamer 0:e4d670b91a9a 2095 *
screamer 0:e4d670b91a9a 2096 * This function gets the Lock1 Status. This bit indicates whether PLL1 has
screamer 0:e4d670b91a9a 2097 * acquired the lock. PLL1 Lock detection is disabled when not operating in either
screamer 0:e4d670b91a9a 2098 * PBE or PEE mode unless the PLLCLKEN1=1 and the the MCG is not configured in the BLPI or the
screamer 0:e4d670b91a9a 2099 * BLPE mode. While the PLL1 clock is locking to the desired frequency, MCGPLL1CLK,
screamer 0:e4d670b91a9a 2100 * MCGPLL1CLK2X, and MCGDDRCLK2X are gated off until the LOCK1 bit gets
screamer 0:e4d670b91a9a 2101 * asserted. If the lock status bit is set, changing the value of the PRDIV1[2:0]
screamer 0:e4d670b91a9a 2102 * bits in the C8 register or the VDIV2[4:0] bits in the C9 register causes the
screamer 0:e4d670b91a9a 2103 * lock status bit to clear and stay cleared until the PLL1 has reacquired lock.
screamer 0:e4d670b91a9a 2104 * Loss of PLL1 reference clock will also causes the LOCK1 bit to clear until the PLL1
screamer 0:e4d670b91a9a 2105 * has reacquired lock. Entry into the LLS, VLPS, or a regular Stop with the PLLSTEN1=0 also
screamer 0:e4d670b91a9a 2106 * causes the lock status bit to clear and stay cleared until the Stop mode is exited
screamer 0:e4d670b91a9a 2107 * and the PLL1 has reacquired the lock. Any time the PLL1 is enabled and the LOCK1 bit
screamer 0:e4d670b91a9a 2108 * is cleared, the MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X are gated off
screamer 0:e4d670b91a9a 2109 * until the LOCK1 bit is asserted again.
screamer 0:e4d670b91a9a 2110 *
screamer 0:e4d670b91a9a 2111 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 2112 * @return status Lock1 Status
screamer 0:e4d670b91a9a 2113 * - 0: PLL1 is currently unlocked.
screamer 0:e4d670b91a9a 2114 * - 1: PLL1 is currently locked.
screamer 0:e4d670b91a9a 2115 */
screamer 0:e4d670b91a9a 2116 static inline mcg_lock_status_t CLOCK_HAL_GetLock1Mode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 2117 {
screamer 0:e4d670b91a9a 2118 return (mcg_lock_status_t)BR_MCG_S2_LOCK1(baseAddr);
screamer 0:e4d670b91a9a 2119 }
screamer 0:e4d670b91a9a 2120
screamer 0:e4d670b91a9a 2121 /*!
screamer 0:e4d670b91a9a 2122 * @brief Gets the PLL Clock Select Status.
screamer 0:e4d670b91a9a 2123 *
screamer 0:e4d670b91a9a 2124 * This function gets the PLL Clock Select Status. The PLLCST indicates the PLL
screamer 0:e4d670b91a9a 2125 * clock selected by PLLCS. The PLLCST bit is not updated immediately after a
screamer 0:e4d670b91a9a 2126 * write to the PLLCS bit due internal synchronization between clock domains.
screamer 0:e4d670b91a9a 2127 *
screamer 0:e4d670b91a9a 2128 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 2129 * @return status PLL Clock Select Status
screamer 0:e4d670b91a9a 2130 * - 0: Source of PLLCS is PLL0 clock.
screamer 0:e4d670b91a9a 2131 * - 1: Source of PLLCS is PLL1 clock.
screamer 0:e4d670b91a9a 2132 */
screamer 0:e4d670b91a9a 2133 static inline mcg_pll_clk_select_t CLOCK_HAL_GetPllClkSelStatMode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 2134 {
screamer 0:e4d670b91a9a 2135 return (mcg_pll_clk_select_t)BR_MCG_S2_PLLCST(baseAddr);
screamer 0:e4d670b91a9a 2136 }
screamer 0:e4d670b91a9a 2137
screamer 0:e4d670b91a9a 2138 /*!
screamer 0:e4d670b91a9a 2139 * @brief Gets the OSC1 Initialization Status.
screamer 0:e4d670b91a9a 2140 *
screamer 0:e4d670b91a9a 2141 * This function gets the OSC1 Initialization Status. This bit is set after the
screamer 0:e4d670b91a9a 2142 * initialization cycles of the 2nd crystal oscillator clock have completed. See
screamer 0:e4d670b91a9a 2143 * the Oscillator block guide for more details.
screamer 0:e4d670b91a9a 2144 *
screamer 0:e4d670b91a9a 2145 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 2146 * @return status OSC1 Initialization Status
screamer 0:e4d670b91a9a 2147 */
screamer 0:e4d670b91a9a 2148 static inline uint8_t CLOCK_HAL_GetOscInit1(uint32_t baseAddr)
screamer 0:e4d670b91a9a 2149 {
screamer 0:e4d670b91a9a 2150 return BR_MCG_S2_OSCINIT1(baseAddr);
screamer 0:e4d670b91a9a 2151 }
screamer 0:e4d670b91a9a 2152
screamer 0:e4d670b91a9a 2153 /*!
screamer 0:e4d670b91a9a 2154 * @brief Gets the OSC1 Loss of Clock Status.
screamer 0:e4d670b91a9a 2155 *
screamer 0:e4d670b91a9a 2156 * This function gets the OSC1 Loss of Clock Status. This bit indicates when a loss
screamer 0:e4d670b91a9a 2157 * of the OSC1 external reference clock has occurred. LOCRE2 determines if a reset or
screamer 0:e4d670b91a9a 2158 * interrupt is generated when LOCS2 is set. This bit is cleared by writing a
screamer 0:e4d670b91a9a 2159 * logic 1 to it when set.
screamer 0:e4d670b91a9a 2160 *
screamer 0:e4d670b91a9a 2161 * @param baseAddr Base address for current MCG instance.
screamer 0:e4d670b91a9a 2162 * @return status OSC1 Loss of Clock Status
screamer 0:e4d670b91a9a 2163 * - 0: No loss of OSC1 external reference clock has occurred.
screamer 0:e4d670b91a9a 2164 * - 1: Loss of OSC1 external reference clock has occurred.
screamer 0:e4d670b91a9a 2165 */
screamer 0:e4d670b91a9a 2166 static inline mcg_locs2_status_t CLOCK_HAL_GetLocs2Mode(uint32_t baseAddr)
screamer 0:e4d670b91a9a 2167 {
screamer 0:e4d670b91a9a 2168 return (mcg_locs2_status_t)BR_MCG_S2_LOCS2(baseAddr);
screamer 0:e4d670b91a9a 2169 }
screamer 0:e4d670b91a9a 2170 #endif /* FSL_FEATURE_MCG_USE_PLLREFSEL */
screamer 0:e4d670b91a9a 2171
screamer 0:e4d670b91a9a 2172 /*@}*/
screamer 0:e4d670b91a9a 2173
screamer 0:e4d670b91a9a 2174 #if defined(__cplusplus)
screamer 0:e4d670b91a9a 2175 }
screamer 0:e4d670b91a9a 2176 #endif /* __cplusplus*/
screamer 0:e4d670b91a9a 2177
screamer 0:e4d670b91a9a 2178 /*! @}*/
screamer 0:e4d670b91a9a 2179
screamer 0:e4d670b91a9a 2180 #endif /* __FSL_MCG_HAL_H__*/
screamer 0:e4d670b91a9a 2181 /*******************************************************************************
screamer 0:e4d670b91a9a 2182 * EOF
screamer 0:e4d670b91a9a 2183 ******************************************************************************/
screamer 0:e4d670b91a9a 2184