Alessandro Angelino / target-freescale-ksdk

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Fork of target-freescale-ksdk by Morpheus

TARGET_KPSDK_CODE/hal/sdhc/fsl_sdhc_hal.h@0:e4d670b91a9a, 2016-03-23 (annotated)

Committer:
screamer
Date:
Wed Mar 23 21:26:50 2016 +0000
Revision:
0:e4d670b91a9a
Initial revision

Who changed what in which revision?

UserRevisionLine numberNew contents of line
screamer 0:e4d670b91a9a 1 /*
screamer 0:e4d670b91a9a 2 * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
screamer 0:e4d670b91a9a 3 * All rights reserved.
screamer 0:e4d670b91a9a 4 *
screamer 0:e4d670b91a9a 5 * Redistribution and use in source and binary forms, with or without modification,
screamer 0:e4d670b91a9a 6 * are permitted provided that the following conditions are met:
screamer 0:e4d670b91a9a 7 *
screamer 0:e4d670b91a9a 8 * o Redistributions of source code must retain the above copyright notice, this list
screamer 0:e4d670b91a9a 9 * of conditions and the following disclaimer.
screamer 0:e4d670b91a9a 10 *
screamer 0:e4d670b91a9a 11 * o Redistributions in binary form must reproduce the above copyright notice, this
screamer 0:e4d670b91a9a 12 * list of conditions and the following disclaimer in the documentation and/or
screamer 0:e4d670b91a9a 13 * other materials provided with the distribution.
screamer 0:e4d670b91a9a 14 *
screamer 0:e4d670b91a9a 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
screamer 0:e4d670b91a9a 16 * contributors may be used to endorse or promote products derived from this
screamer 0:e4d670b91a9a 17 * software without specific prior written permission.
screamer 0:e4d670b91a9a 18 *
screamer 0:e4d670b91a9a 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
screamer 0:e4d670b91a9a 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
screamer 0:e4d670b91a9a 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
screamer 0:e4d670b91a9a 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
screamer 0:e4d670b91a9a 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
screamer 0:e4d670b91a9a 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
screamer 0:e4d670b91a9a 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
screamer 0:e4d670b91a9a 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
screamer 0:e4d670b91a9a 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
screamer 0:e4d670b91a9a 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
screamer 0:e4d670b91a9a 29 */
screamer 0:e4d670b91a9a 30 #ifndef __FSL_SDHC_HAL_H__
screamer 0:e4d670b91a9a 31 #define __FSL_SDHC_HAL_H__
screamer 0:e4d670b91a9a 32
screamer 0:e4d670b91a9a 33 #include <assert.h>
screamer 0:e4d670b91a9a 34 #include <stdbool.h>
screamer 0:e4d670b91a9a 35 #include "fsl_device_registers.h"
screamer 0:e4d670b91a9a 36 #include "fsl_sdhc_features.h"
screamer 0:e4d670b91a9a 37
screamer 0:e4d670b91a9a 38 #ifndef MBED_NO_SDHC
screamer 0:e4d670b91a9a 39
screamer 0:e4d670b91a9a 40 /*! @addtogroup sdhc_hal */
screamer 0:e4d670b91a9a 41 /*! @{ */
screamer 0:e4d670b91a9a 42
screamer 0:e4d670b91a9a 43 /* PRSSTA */
screamer 0:e4d670b91a9a 44 #define SDHC_HAL_DAT0_LEVEL (BM_SDHC_PRSSTAT_DLSL & (1 << 24))
screamer 0:e4d670b91a9a 45
screamer 0:e4d670b91a9a 46 /* XFERTYP */
screamer 0:e4d670b91a9a 47 #define SDHC_HAL_MAX_BLOCK_COUNT ((1 << BS_SDHC_BLKATTR_BLKCNT) - 1)
screamer 0:e4d670b91a9a 48 #define SDHC_HAL_ENABLE_DMA BM_SDHC_XFERTYP_DMAEN
screamer 0:e4d670b91a9a 49
screamer 0:e4d670b91a9a 50 #define SDHC_HAL_CMD_TYPE_SUSPEND (BF_SDHC_XFERTYP_CMDTYP(1))
screamer 0:e4d670b91a9a 51 #define SDHC_HAL_CMD_TYPE_RESUME (BF_SDHC_XFERTYP_CMDTYP(2))
screamer 0:e4d670b91a9a 52 #define SDHC_HAL_CMD_TYPE_ABORT (BF_SDHC_XFERTYP_CMDTYP(3))
screamer 0:e4d670b91a9a 53
screamer 0:e4d670b91a9a 54 #define SDHC_HAL_ENABLE_BLOCK_COUNT BM_SDHC_XFERTYP_BCEN
screamer 0:e4d670b91a9a 55 #define SDHC_HAL_ENABLE_AUTO_CMD12 BM_SDHC_XFERTYP_AC12EN
screamer 0:e4d670b91a9a 56 #define SDHC_HAL_ENABLE_DATA_READ BM_SDHC_XFERTYP_DTDSEL
screamer 0:e4d670b91a9a 57 #define SDHC_HAL_MULTIPLE_BLOCK BM_SDHC_XFERTYP_MSBSEL
screamer 0:e4d670b91a9a 58
screamer 0:e4d670b91a9a 59 #define SDHC_HAL_RESP_LEN_136 ((0x1 << BP_SDHC_XFERTYP_RSPTYP) & BM_SDHC_XFERTYP_RSPTYP)
screamer 0:e4d670b91a9a 60 #define SDHC_HAL_RESP_LEN_48 ((0x2 << BP_SDHC_XFERTYP_RSPTYP) & BM_SDHC_XFERTYP_RSPTYP)
screamer 0:e4d670b91a9a 61 #define SDHC_HAL_RESP_LEN_48_BC ((0x3 << BP_SDHC_XFERTYP_RSPTYP) & BM_SDHC_XFERTYP_RSPTYP)
screamer 0:e4d670b91a9a 62
screamer 0:e4d670b91a9a 63 #define SDHC_HAL_ENABLE_CRC_CHECK BM_SDHC_XFERTYP_CCCEN
screamer 0:e4d670b91a9a 64 #define SDHC_HAL_ENABLE_INDEX_CHECK BM_SDHC_XFERTYP_CICEN
screamer 0:e4d670b91a9a 65 #define SDHC_HAL_DATA_PRESENT BM_SDHC_XFERTYP_DPSEL
screamer 0:e4d670b91a9a 66
screamer 0:e4d670b91a9a 67 /* SYSCTL */
screamer 0:e4d670b91a9a 68 #define SDHC_HAL_MAX_DVS (16U)
screamer 0:e4d670b91a9a 69 #define SDHC_HAL_INITIAL_DVS (1U) /* initial value of divisor to calculate clock rate */
screamer 0:e4d670b91a9a 70 #define SDHC_HAL_INITIAL_CLKFS (2U) /* initial value of clock selector to calculate clock rate */
screamer 0:e4d670b91a9a 71 #define SDHC_HAL_NEXT_DVS(x) do { ((x) += 1); } while(0)
screamer 0:e4d670b91a9a 72 #define SDHC_HAL_PREV_DVS(x) do { ((x) -= 1); } while(0)
screamer 0:e4d670b91a9a 73 #define SDHC_HAL_MAX_CLKFS (256U)
screamer 0:e4d670b91a9a 74 #define SDHC_HAL_NEXT_CLKFS(x) do { ((x) <<= 1); } while(0)
screamer 0:e4d670b91a9a 75 #define SDHC_HAL_PREV_CLKFS(x) do { ((x) >>= 1); } while(0)
screamer 0:e4d670b91a9a 76
screamer 0:e4d670b91a9a 77 /* IRQSTAT */
screamer 0:e4d670b91a9a 78 #define SDHC_HAL_CMD_COMPLETE_INT BM_SDHC_IRQSTAT_CC
screamer 0:e4d670b91a9a 79 #define SDHC_HAL_DATA_COMPLETE_INT BM_SDHC_IRQSTAT_TC
screamer 0:e4d670b91a9a 80 #define SDHC_HAL_BLOCK_GAP_EVENT_INT BM_SDHC_IRQSTAT_BGE
screamer 0:e4d670b91a9a 81 #define SDHC_HAL_DMA_INT BM_SDHC_IRQSTAT_DINT
screamer 0:e4d670b91a9a 82 #define SDHC_HAL_DMA_ERR_INT BM_SDHC_IRQSTAT_DMAE
screamer 0:e4d670b91a9a 83 #define SDHC_HAL_BUF_WRITE_READY_INT BM_SDHC_IRQSTAT_BWR
screamer 0:e4d670b91a9a 84 #define SDHC_HAL_BUF_READ_READY_INT BM_SDHC_IRQSTAT_BRR
screamer 0:e4d670b91a9a 85 #define SDHC_HAL_CARD_INSERTION_INT BM_SDHC_IRQSTAT_CINS
screamer 0:e4d670b91a9a 86 #define SDHC_HAL_CARD_REMOVAL_INT BM_SDHC_IRQSTAT_CRM
screamer 0:e4d670b91a9a 87 #define SDHC_HAL_CARD_INT BM_SDHC_IRQSTAT_CINT
screamer 0:e4d670b91a9a 88 #define SDHC_HAL_CMD_TIMEOUT_ERR_INT BM_SDHC_IRQSTAT_CTOE
screamer 0:e4d670b91a9a 89 #define SDHC_HAL_CMD_CRC_ERR_INT BM_SDHC_IRQSTAT_CCE
screamer 0:e4d670b91a9a 90 #define SDHC_HAL_CMD_END_BIT_ERR_INT BM_SDHC_IRQSTAT_CEBE
screamer 0:e4d670b91a9a 91 #define SDHC_HAL_CMD_INDEX_ERR_INT BM_SDHC_IRQSTAT_CIE
screamer 0:e4d670b91a9a 92 #define SDHC_HAL_DATA_TIMEOUT_ERR_INT BM_SDHC_IRQSTAT_DTOE
screamer 0:e4d670b91a9a 93 #define SDHC_HAL_DATA_CRC_ERR_INT BM_SDHC_IRQSTAT_DCE
screamer 0:e4d670b91a9a 94 #define SDHC_HAL_DATA_END_BIT_ERR_INT BM_SDHC_IRQSTAT_DEBE
screamer 0:e4d670b91a9a 95 #define SDHC_HAL_AUTO_CMD12_ERR_INT BM_SDHC_IRQSTAT_AC12E
screamer 0:e4d670b91a9a 96
screamer 0:e4d670b91a9a 97 #define SDHC_HAL_CMD_ERR_INT ((uint32_t)(SDHC_HAL_CMD_TIMEOUT_ERR_INT | \
screamer 0:e4d670b91a9a 98 SDHC_HAL_CMD_CRC_ERR_INT | \
screamer 0:e4d670b91a9a 99 SDHC_HAL_CMD_END_BIT_ERR_INT | \
screamer 0:e4d670b91a9a 100 SDHC_HAL_CMD_INDEX_ERR_INT))
screamer 0:e4d670b91a9a 101 #define SDHC_HAL_DATA_ERR_INT ((uint32_t)(SDHC_HAL_DATA_TIMEOUT_ERR_INT | \
screamer 0:e4d670b91a9a 102 SDHC_HAL_DATA_CRC_ERR_INT | \
screamer 0:e4d670b91a9a 103 SDHC_HAL_DATA_END_BIT_ERR_INT))
screamer 0:e4d670b91a9a 104 #define SDHC_HAL_DATA_ALL_INT ((uint32_t)(SDHC_HAL_DATA_ERR_INT | \
screamer 0:e4d670b91a9a 105 SDHC_HAL_DATA_COMPLETE_INT | \
screamer 0:e4d670b91a9a 106 SDHC_HAL_BUF_READ_READY_INT | \
screamer 0:e4d670b91a9a 107 SDHC_HAL_BUF_WRITE_READY_INT | \
screamer 0:e4d670b91a9a 108 SDHC_HAL_DMA_ERR_INT | SDHC_HAL_DMA_INT))
screamer 0:e4d670b91a9a 109 #define SDHC_HAL_CMD_ALL_INT ((uint32_t)(SDHC_HAL_CMD_ERR_INT | \
screamer 0:e4d670b91a9a 110 SDHC_HAL_CMD_COMPLETE_INT | \
screamer 0:e4d670b91a9a 111 SDHC_HAL_AUTO_CMD12_ERR_INT))
screamer 0:e4d670b91a9a 112 #define SDHC_HAL_CD_ALL_INT ((uint32_t)(SDHC_HAL_CARD_INSERTION_INT | \
screamer 0:e4d670b91a9a 113 SDHC_HAL_CARD_REMOVAL_INT))
screamer 0:e4d670b91a9a 114 #define SDHC_HAL_ALL_ERR_INT ((uint32_t)(SDHC_HAL_CMD_ERR_INT | \
screamer 0:e4d670b91a9a 115 SDHC_HAL_DATA_ERR_INT | \
screamer 0:e4d670b91a9a 116 SDHC_HAL_AUTO_CMD12_ERR_INT | \
screamer 0:e4d670b91a9a 117 SDHC_HAL_DMA_ERR_INT))
screamer 0:e4d670b91a9a 118
screamer 0:e4d670b91a9a 119 /* AC12ERR */
screamer 0:e4d670b91a9a 120 #define SDHC_HAL_ACMD12_NOT_EXEC_ERR BM_SDHC_AC12ERR_AC12NE
screamer 0:e4d670b91a9a 121 #define SDHC_HAL_ACMD12_TIMEOUT_ERR BM_SDHC_AC12ERR_AC12TOE
screamer 0:e4d670b91a9a 122 #define SDHC_HAL_ACMD12_END_BIT_ERR BM_SDHC_AC12ERR_AC12EBE
screamer 0:e4d670b91a9a 123 #define SDHC_HAL_ACMD12_CRC_ERR BM_SDHC_AC12ERR_AC12CE
screamer 0:e4d670b91a9a 124 #define SDHC_HAL_ACMD12_INDEX_ERR BM_SDHC_AC12ERR_AC12IE
screamer 0:e4d670b91a9a 125 #define SDHC_HAL_ACMD12_NOT_ISSUE_ERR BM_SDHC_AC12ERR_CNIBAC12E
screamer 0:e4d670b91a9a 126
screamer 0:e4d670b91a9a 127 /* HTCAPBLT */
screamer 0:e4d670b91a9a 128 #define SDHC_HAL_SUPPORT_ADMA BM_SDHC_HTCAPBLT_ADMAS
screamer 0:e4d670b91a9a 129 #define SDHC_HAL_SUPPORT_HIGHSPEED BM_SDHC_HTCAPBLT_HSS
screamer 0:e4d670b91a9a 130 #define SDHC_HAL_SUPPORT_DMA BM_SDHC_HTCAPBLT_DMAS
screamer 0:e4d670b91a9a 131 #define SDHC_HAL_SUPPORT_SUSPEND_RESUME BM_SDHC_HTCAPBLT_SRS
screamer 0:e4d670b91a9a 132 #define SDHC_HAL_SUPPORT_3_3_V BM_SDHC_HTCAPBLT_VS33
screamer 0:e4d670b91a9a 133 #define SDHC_HAL_SUPPORT_3_0_V BM_SDHC_HTCAPBLT_VS30
screamer 0:e4d670b91a9a 134 #define SDHC_HAL_SUPPORT_1_8_V BM_SDHC_HTCAPBLT_VS18
screamer 0:e4d670b91a9a 135
screamer 0:e4d670b91a9a 136 /* FEVT */
screamer 0:e4d670b91a9a 137 #define SDHC_HAL_ACMD12_NOT_EXEC_ERR_EVENT BM_SDHC_FEVT_AC12NE
screamer 0:e4d670b91a9a 138 #define SDHC_HAL_ACMD12_TIMEOUT_ERR_EVENT BM_SDHC_FEVT_AC12TOE
screamer 0:e4d670b91a9a 139 #define SDHC_HAL_ACMD12_CRC_ERR_EVENT BM_SDHC_FEVT_AC12CE
screamer 0:e4d670b91a9a 140 #define SDHC_HAL_ACMD12_END_BIT_ERR_EVENT BM_SDHC_FEVT_AC12EBE
screamer 0:e4d670b91a9a 141 #define SDHC_HAL_ACMD12_INDEX_ERR_EVENT BM_SDHC_FEVT_AC12IE
screamer 0:e4d670b91a9a 142 #define SDHC_HAL_ACMD12_NOT_ISSUE_ERR_EVENT BM_SDHC_FEVT_CNIBAC12E
screamer 0:e4d670b91a9a 143 #define SDHC_HAL_CMD_TIMEOUT_ERR_EVENT BM_SDHC_FEVT_CTOE
screamer 0:e4d670b91a9a 144 #define SDHC_HAL_CMD_CRC_ERR_EVENT BM_SDHC_FEVT_CCE
screamer 0:e4d670b91a9a 145 #define SDHC_HAL_CMD_END_BIT_ERR_EVENT BM_SDHC_FEVT_CEBE
screamer 0:e4d670b91a9a 146 #define SDHC_HAL_CMD_INDEX_ERR_EVENT BM_SDHC_FEVT_CIE
screamer 0:e4d670b91a9a 147 #define SDHC_HAL_DATA_TIMEOUT_ERR_EVENT BM_SDHC_FEVT_DTOE
screamer 0:e4d670b91a9a 148 #define SDHC_HAL_DATA_CRC_ERR_EVENT BM_SDHC_FEVT_DCE
screamer 0:e4d670b91a9a 149 #define SDHC_HAL_DATA_END_BIT_ERR_EVENT BM_SDHC_FEVT_DEBE
screamer 0:e4d670b91a9a 150 #define SDHC_HAL_ACMD12_ERR_EVENT BM_SDHC_FEVT_AC12E
screamer 0:e4d670b91a9a 151 #define SDHC_HAL_CARD_INT_EVENT BM_SDHC_FEVT_CINT
screamer 0:e4d670b91a9a 152 #define SDHC_HAL_DMA_ERROR_EVENT BM_SDHC_FEVT_DMAE
screamer 0:e4d670b91a9a 153
screamer 0:e4d670b91a9a 154 /* MMCBOOT */
screamer 0:e4d670b91a9a 155 typedef enum _sdhc_hal_mmcboot {
screamer 0:e4d670b91a9a 156 kSdhcHalMmcbootNormal = 0,
screamer 0:e4d670b91a9a 157 kSdhcHalMmcbootAlter = 1,
screamer 0:e4d670b91a9a 158 } sdhc_hal_mmcboot_t;
screamer 0:e4d670b91a9a 159
screamer 0:e4d670b91a9a 160 /* PROCTL */
screamer 0:e4d670b91a9a 161 typedef enum _sdhc_hal_led {
screamer 0:e4d670b91a9a 162 kSdhcHalLedOff = 0,
screamer 0:e4d670b91a9a 163 kSdhcHalLedOn = 1,
screamer 0:e4d670b91a9a 164 } sdhc_hal_led_t;
screamer 0:e4d670b91a9a 165
screamer 0:e4d670b91a9a 166 typedef enum _sdhc_hal_dtw {
screamer 0:e4d670b91a9a 167 kSdhcHalDtw1Bit = 0,
screamer 0:e4d670b91a9a 168 kSdhcHalDtw4Bit = 1,
screamer 0:e4d670b91a9a 169 kSdhcHalDtw8Bit = 2,
screamer 0:e4d670b91a9a 170 } sdhc_hal_dtw_t;
screamer 0:e4d670b91a9a 171
screamer 0:e4d670b91a9a 172 typedef enum _sdhc_hal_endian {
screamer 0:e4d670b91a9a 173 kSdhcHalEndianBig = 0,
screamer 0:e4d670b91a9a 174 kSdhcHalEndianHalfWordBig = 1,
screamer 0:e4d670b91a9a 175 kSdhcHalEndianLittle = 2,
screamer 0:e4d670b91a9a 176 } sdhc_hal_endian_t;
screamer 0:e4d670b91a9a 177
screamer 0:e4d670b91a9a 178 typedef enum _sdhc_hal_dma_mode {
screamer 0:e4d670b91a9a 179 kSdhcHalDmaSimple = 0,
screamer 0:e4d670b91a9a 180 kSdhcHalDmaAdma1 = 1,
screamer 0:e4d670b91a9a 181 kSdhcHalDmaAdma2 = 2,
screamer 0:e4d670b91a9a 182 } sdhc_hal_dma_mode_t;
screamer 0:e4d670b91a9a 183
screamer 0:e4d670b91a9a 184 #define SDHC_HAL_ADMA1_ADDR_ALIGN (4096)
screamer 0:e4d670b91a9a 185 #define SDHC_HAL_ADMA1_LEN_ALIGN (4096)
screamer 0:e4d670b91a9a 186 #define SDHC_HAL_ADMA2_ADDR_ALIGN (4)
screamer 0:e4d670b91a9a 187 #define SDHC_HAL_ADMA2_LEN_ALIGN (4)
screamer 0:e4d670b91a9a 188
screamer 0:e4d670b91a9a 189 /*
screamer 0:e4d670b91a9a 190 * ADMA1 descriptor table
screamer 0:e4d670b91a9a 191 * |------------------------|---------|--------------------------|
screamer 0:e4d670b91a9a 192 * | Address/page Field |reserved | Attribute |
screamer 0:e4d670b91a9a 193 * |------------------------|---------|--------------------------|
screamer 0:e4d670b91a9a 194 * |31 12|11 6|05 |04 |03|02 |01 |00 |
screamer 0:e4d670b91a9a 195 * |------------------------|---------|----|----|--|---|---|-----|
screamer 0:e4d670b91a9a 196 * | address or data length | 000000 |Act2|Act1| 0|Int|End|Valid|
screamer 0:e4d670b91a9a 197 * |------------------------|---------|----|----|--|---|---|-----|
screamer 0:e4d670b91a9a 198 *
screamer 0:e4d670b91a9a 199 *
screamer 0:e4d670b91a9a 200 * |------|------|-----------------|-------|-------------|
screamer 0:e4d670b91a9a 201 * | Act2 | Act1 | Comment | 31-28 | 27 - 12 |
screamer 0:e4d670b91a9a 202 * |------|------|-----------------|---------------------|
screamer 0:e4d670b91a9a 203 * | 0 | 0 | No op | Don't care |
screamer 0:e4d670b91a9a 204 * |------|------|-----------------|-------|-------------|
screamer 0:e4d670b91a9a 205 * | 0 | 1 | Set data length | 0000 | Data Length |
screamer 0:e4d670b91a9a 206 * |------|------|-----------------|-------|-------------|
screamer 0:e4d670b91a9a 207 * | 1 | 0 | Transfer data | Data address |
screamer 0:e4d670b91a9a 208 * |------|------|-----------------|---------------------|
screamer 0:e4d670b91a9a 209 * | 1 | 1 | Link descriptor | Descriptor address |
screamer 0:e4d670b91a9a 210 * |------|------|-----------------|---------------------|
screamer 0:e4d670b91a9a 211 *
screamer 0:e4d670b91a9a 212 */
screamer 0:e4d670b91a9a 213 typedef uint32_t sdhc_hal_adma1_descriptor_t;
screamer 0:e4d670b91a9a 214 #define SDHC_HAL_ADMA1_DESC_VALID_MASK (1 << 0)
screamer 0:e4d670b91a9a 215 #define SDHC_HAL_ADMA1_DESC_END_MASK (1 << 1)
screamer 0:e4d670b91a9a 216 #define SDHC_HAL_ADMA1_DESC_INT_MASK (1 << 2)
screamer 0:e4d670b91a9a 217 #define SDHC_HAL_ADMA1_DESC_ACT1_MASK (1 << 4)
screamer 0:e4d670b91a9a 218 #define SDHC_HAL_ADMA1_DESC_ACT2_MASK (1 << 5)
screamer 0:e4d670b91a9a 219 #define SDHC_HAL_ADMA1_DESC_TYPE_NOP (SDHC_HAL_ADMA1_DESC_VALID_MASK)
screamer 0:e4d670b91a9a 220 #define SDHC_HAL_ADMA1_DESC_TYPE_TRAN (SDHC_HAL_ADMA1_DESC_ACT2_MASK | SDHC_HAL_ADMA1_DESC_VALID_MASK)
screamer 0:e4d670b91a9a 221 #define SDHC_HAL_ADMA1_DESC_TYPE_LINK (SDHC_HAL_ADMA1_DESC_ACT1_MASK | SDHC_HAL_ADMA1_DESC_ACT2_MASK | SDHC_HAL_ADMA1_DESC_VALID_MASK)
screamer 0:e4d670b91a9a 222 #define SDHC_HAL_ADMA1_DESC_TYPE_SET (SDHC_HAL_ADMA1_DESC_ACT1_MASK | SDHC_HAL_ADMA1_DESC_VALID_MASK)
screamer 0:e4d670b91a9a 223 #define SDHC_HAL_ADMA1_DESC_ADDRESS_SHIFT (12)
screamer 0:e4d670b91a9a 224 #define SDHC_HAL_ADMA1_DESC_ADDRESS_MASK (0xFFFFFU)
screamer 0:e4d670b91a9a 225 #define SDHC_HAL_ADMA1_DESC_LEN_SHIFT (12)
screamer 0:e4d670b91a9a 226 #define SDHC_HAL_ADMA1_DESC_LEN_MASK (0xFFFFU)
screamer 0:e4d670b91a9a 227 #define SDHC_HAL_ADMA1_DESC_MAX_LEN_PER_ENTRY (SDHC_HAL_ADMA1_DESC_LEN_MASK + 1)
screamer 0:e4d670b91a9a 228
screamer 0:e4d670b91a9a 229 /*
screamer 0:e4d670b91a9a 230 * ADMA2 descriptor table
screamer 0:e4d670b91a9a 231 * |----------------|---------------|-------------|--------------------------|
screamer 0:e4d670b91a9a 232 * | Address Field | length | reserved | Attribute |
screamer 0:e4d670b91a9a 233 * |----------------|---------------|-------------|--------------------------|
screamer 0:e4d670b91a9a 234 * |63 32|31 16|15 06|05 |04 |03|02 |01 |00 |
screamer 0:e4d670b91a9a 235 * |----------------|---------------|-------------|----|----|--|---|---|-----|
screamer 0:e4d670b91a9a 236 * | 32-bit address | 16-bit length | 0000000000 |Act2|Act1| 0|Int|End|Valid|
screamer 0:e4d670b91a9a 237 * |----------------|---------------|-------------|----|----|--|---|---|-----|
screamer 0:e4d670b91a9a 238 *
screamer 0:e4d670b91a9a 239 *
screamer 0:e4d670b91a9a 240 * | Act2 | Act1 | Comment | Operation |
screamer 0:e4d670b91a9a 241 * |------|------|-----------------|-------------------------------------------------------------------|
screamer 0:e4d670b91a9a 242 * | 0 | 0 | No op | Don't care |
screamer 0:e4d670b91a9a 243 * |------|------|-----------------|-------------------------------------------------------------------|
screamer 0:e4d670b91a9a 244 * | 0 | 1 | Reserved | Read this line and go to next one |
screamer 0:e4d670b91a9a 245 * |------|------|-----------------|-------------------------------------------------------------------|
screamer 0:e4d670b91a9a 246 * | 1 | 0 | Transfer data | Transfer data with address and length set in this descriptor line |
screamer 0:e4d670b91a9a 247 * |------|------|-----------------|-------------------------------------------------------------------|
screamer 0:e4d670b91a9a 248 * | 1 | 1 | Link descriptor | Link to another descriptor |
screamer 0:e4d670b91a9a 249 * |------|------|-----------------|-------------------------------------------------------------------|
screamer 0:e4d670b91a9a 250 *
screamer 0:e4d670b91a9a 251 */
screamer 0:e4d670b91a9a 252 typedef struct SdhcHalAdma2Descriptor {
screamer 0:e4d670b91a9a 253 uint32_t attribute;
screamer 0:e4d670b91a9a 254 uint32_t *address;
screamer 0:e4d670b91a9a 255 } sdhc_hal_adma2_descriptor_t;
screamer 0:e4d670b91a9a 256
screamer 0:e4d670b91a9a 257 #define SDHC_HAL_ADMA2_DESC_VALID_MASK (1 << 0)
screamer 0:e4d670b91a9a 258 #define SDHC_HAL_ADMA2_DESC_END_MASK (1 << 1)
screamer 0:e4d670b91a9a 259 #define SDHC_HAL_ADMA2_DESC_INT_MASK (1 << 2)
screamer 0:e4d670b91a9a 260 #define SDHC_HAL_ADMA2_DESC_ACT1_MASK (1 << 4)
screamer 0:e4d670b91a9a 261 #define SDHC_HAL_ADMA2_DESC_ACT2_MASK (1 << 5)
screamer 0:e4d670b91a9a 262 #define SDHC_HAL_ADMA2_DESC_TYPE_NOP (SDHC_HAL_ADMA2_DESC_VALID_MASK)
screamer 0:e4d670b91a9a 263 #define SDHC_HAL_ADMA2_DESC_TYPE_RCV (SDHC_HAL_ADMA2_DESC_ACT1_MASK | SDHC_HAL_ADMA2_DESC_VALID_MASK)
screamer 0:e4d670b91a9a 264 #define SDHC_HAL_ADMA2_DESC_TYPE_TRAN (SDHC_HAL_ADMA2_DESC_ACT2_MASK | SDHC_HAL_ADMA2_DESC_VALID_MASK)
screamer 0:e4d670b91a9a 265 #define SDHC_HAL_ADMA2_DESC_TYPE_LINK (SDHC_HAL_ADMA2_DESC_ACT1_MASK | SDHC_HAL_ADMA2_DESC_ACT2_MASK | SDHC_HAL_ADMA2_DESC_VALID_MASK)
screamer 0:e4d670b91a9a 266 #define SDHC_HAL_ADMA2_DESC_LEN_SHIFT (16)
screamer 0:e4d670b91a9a 267 #define SDHC_HAL_ADMA2_DESC_LEN_MASK (0xFFFFU)
screamer 0:e4d670b91a9a 268 #define SDHC_HAL_ADMA2_DESC_MAX_LEN_PER_ENTRY (SDHC_HAL_ADMA2_DESC_LEN_MASK + 1)
screamer 0:e4d670b91a9a 269
screamer 0:e4d670b91a9a 270 #define SDHC_HAL_RST_TYPE_ALL BM_SDHC_SYSCTL_RSTA
screamer 0:e4d670b91a9a 271 #define SDHC_HAL_RST_TYPE_CMD BM_SDHC_SYSCTL_RSTC
screamer 0:e4d670b91a9a 272 #define SDHC_HAL_RST_TYPE_DATA BM_SDHC_SYSCTL_RSTD
screamer 0:e4d670b91a9a 273
screamer 0:e4d670b91a9a 274 #define SDHC_HAL_MAX_BLKLEN_512B (0U)
screamer 0:e4d670b91a9a 275 #define SDHC_HAL_MAX_BLKLEN_1024B (1U)
screamer 0:e4d670b91a9a 276 #define SDHC_HAL_MAX_BLKLEN_2048B (2U)
screamer 0:e4d670b91a9a 277 #define SDHC_HAL_MAX_BLKLEN_4096B (3U)
screamer 0:e4d670b91a9a 278
screamer 0:e4d670b91a9a 279 /*************************************************************************************************
screamer 0:e4d670b91a9a 280 * API
screamer 0:e4d670b91a9a 281 ************************************************************************************************/
screamer 0:e4d670b91a9a 282
screamer 0:e4d670b91a9a 283 #if defined(__cplusplus)
screamer 0:e4d670b91a9a 284 extern "C" {
screamer 0:e4d670b91a9a 285 #endif
screamer 0:e4d670b91a9a 286
screamer 0:e4d670b91a9a 287 /*! @name SDHC HAL FUNCTION */
screamer 0:e4d670b91a9a 288 /*@{ */
screamer 0:e4d670b91a9a 289
screamer 0:e4d670b91a9a 290 /*!
screamer 0:e4d670b91a9a 291 * @brief Configures the DMA address.
screamer 0:e4d670b91a9a 292 *
screamer 0:e4d670b91a9a 293 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 294 * @param address the DMA address
screamer 0:e4d670b91a9a 295 */
screamer 0:e4d670b91a9a 296 static inline void SDHC_HAL_SetDmaAddress(uint32_t baseAddr, uint32_t address)
screamer 0:e4d670b91a9a 297 {
screamer 0:e4d670b91a9a 298 HW_SDHC_DSADDR_WR(baseAddr, BF_SDHC_DSADDR_DSADDR(address));
screamer 0:e4d670b91a9a 299 }
screamer 0:e4d670b91a9a 300
screamer 0:e4d670b91a9a 301 /*!
screamer 0:e4d670b91a9a 302 * @brief Gets the DMA address.
screamer 0:e4d670b91a9a 303 *
screamer 0:e4d670b91a9a 304 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 305 * @return the DMA address
screamer 0:e4d670b91a9a 306 */
screamer 0:e4d670b91a9a 307 static inline uint32_t SDHC_HAL_GetDmaAddress(uint32_t baseAddr)
screamer 0:e4d670b91a9a 308 {
screamer 0:e4d670b91a9a 309 return HW_SDHC_DSADDR_RD(baseAddr);
screamer 0:e4d670b91a9a 310 }
screamer 0:e4d670b91a9a 311
screamer 0:e4d670b91a9a 312 /*!
screamer 0:e4d670b91a9a 313 * @brief Gets the block size configured.
screamer 0:e4d670b91a9a 314 *
screamer 0:e4d670b91a9a 315 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 316 * @return the block size already configured
screamer 0:e4d670b91a9a 317 */
screamer 0:e4d670b91a9a 318 static inline uint32_t SDHC_HAL_GetBlockSize(uint32_t baseAddr)
screamer 0:e4d670b91a9a 319 {
screamer 0:e4d670b91a9a 320 return BR_SDHC_BLKATTR_BLKSIZE(baseAddr);
screamer 0:e4d670b91a9a 321 }
screamer 0:e4d670b91a9a 322
screamer 0:e4d670b91a9a 323 /*!
screamer 0:e4d670b91a9a 324 * @brief Sets the block size.
screamer 0:e4d670b91a9a 325 *
screamer 0:e4d670b91a9a 326 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 327 * @param blockSize the block size
screamer 0:e4d670b91a9a 328 */
screamer 0:e4d670b91a9a 329 static inline void SDHC_HAL_SetBlockSize(uint32_t baseAddr, uint32_t blockSize)
screamer 0:e4d670b91a9a 330 {
screamer 0:e4d670b91a9a 331 BW_SDHC_BLKATTR_BLKSIZE(baseAddr, blockSize);
screamer 0:e4d670b91a9a 332 }
screamer 0:e4d670b91a9a 333
screamer 0:e4d670b91a9a 334 /*!
screamer 0:e4d670b91a9a 335 * @brief Sets the block count.
screamer 0:e4d670b91a9a 336 *
screamer 0:e4d670b91a9a 337 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 338 * @param blockCount the block count
screamer 0:e4d670b91a9a 339 */
screamer 0:e4d670b91a9a 340 static inline void SDHC_HAL_SetBlockCount(uint32_t baseAddr, uint32_t blockCount)
screamer 0:e4d670b91a9a 341 {
screamer 0:e4d670b91a9a 342 BW_SDHC_BLKATTR_BLKCNT(baseAddr, blockCount);
screamer 0:e4d670b91a9a 343 }
screamer 0:e4d670b91a9a 344
screamer 0:e4d670b91a9a 345 /*!
screamer 0:e4d670b91a9a 346 * @brief Gets the block count configured.
screamer 0:e4d670b91a9a 347 *
screamer 0:e4d670b91a9a 348 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 349 * @return the block count already configured
screamer 0:e4d670b91a9a 350 */
screamer 0:e4d670b91a9a 351 static inline uint32_t SDHC_HAL_GetBlockCount(uint32_t baseAddr)
screamer 0:e4d670b91a9a 352 {
screamer 0:e4d670b91a9a 353 return BR_SDHC_BLKATTR_BLKCNT(baseAddr);
screamer 0:e4d670b91a9a 354 }
screamer 0:e4d670b91a9a 355
screamer 0:e4d670b91a9a 356 /*!
screamer 0:e4d670b91a9a 357 * @brief Configures the command argument.
screamer 0:e4d670b91a9a 358 *
screamer 0:e4d670b91a9a 359 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 360 * @param arg the command argument
screamer 0:e4d670b91a9a 361 */
screamer 0:e4d670b91a9a 362 static inline void SDHC_HAL_SetCmdArgument(uint32_t baseAddr, uint32_t arg)
screamer 0:e4d670b91a9a 363 {
screamer 0:e4d670b91a9a 364 BW_SDHC_CMDARG_CMDARG(baseAddr, arg);
screamer 0:e4d670b91a9a 365 }
screamer 0:e4d670b91a9a 366
screamer 0:e4d670b91a9a 367 /*!
screamer 0:e4d670b91a9a 368 * @brief Sends a command.
screamer 0:e4d670b91a9a 369 *
screamer 0:e4d670b91a9a 370 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 371 * @param index command index
screamer 0:e4d670b91a9a 372 * @param flags transfer type flags
screamer 0:e4d670b91a9a 373 */
screamer 0:e4d670b91a9a 374 static inline void SDHC_HAL_SendCmd(uint32_t baseAddr, uint32_t index, uint32_t flags)
screamer 0:e4d670b91a9a 375 {
screamer 0:e4d670b91a9a 376 HW_SDHC_XFERTYP_WR(baseAddr, ((index << BP_SDHC_XFERTYP_CMDINX) & BM_SDHC_XFERTYP_CMDINX)
screamer 0:e4d670b91a9a 377 | (flags & ( BM_SDHC_XFERTYP_DMAEN | BM_SDHC_XFERTYP_MSBSEL | BM_SDHC_XFERTYP_DPSEL
screamer 0:e4d670b91a9a 378 | BM_SDHC_XFERTYP_CMDTYP | BM_SDHC_XFERTYP_BCEN | BM_SDHC_XFERTYP_CICEN
screamer 0:e4d670b91a9a 379 | BM_SDHC_XFERTYP_CCCEN | BM_SDHC_XFERTYP_RSPTYP | BM_SDHC_XFERTYP_DTDSEL
screamer 0:e4d670b91a9a 380 | BM_SDHC_XFERTYP_AC12EN)));
screamer 0:e4d670b91a9a 381 }
screamer 0:e4d670b91a9a 382
screamer 0:e4d670b91a9a 383 /*!
screamer 0:e4d670b91a9a 384 * @brief Fills the the data port.
screamer 0:e4d670b91a9a 385 *
screamer 0:e4d670b91a9a 386 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 387 * @param data the data about to be sent
screamer 0:e4d670b91a9a 388 */
screamer 0:e4d670b91a9a 389 static inline void SDHC_HAL_SetData(uint32_t baseAddr, uint32_t data)
screamer 0:e4d670b91a9a 390 {
screamer 0:e4d670b91a9a 391 HW_SDHC_DATPORT_WR(baseAddr, data);
screamer 0:e4d670b91a9a 392 }
screamer 0:e4d670b91a9a 393
screamer 0:e4d670b91a9a 394 /*!
screamer 0:e4d670b91a9a 395 * @brief Retrieves the data from the data port.
screamer 0:e4d670b91a9a 396 *
screamer 0:e4d670b91a9a 397 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 398 * @return data the data read
screamer 0:e4d670b91a9a 399 */
screamer 0:e4d670b91a9a 400 static inline uint32_t SDHC_HAL_GetData(uint32_t baseAddr)
screamer 0:e4d670b91a9a 401 {
screamer 0:e4d670b91a9a 402 return BR_SDHC_DATPORT_DATCONT(baseAddr);
screamer 0:e4d670b91a9a 403 }
screamer 0:e4d670b91a9a 404
screamer 0:e4d670b91a9a 405 /*!
screamer 0:e4d670b91a9a 406 * @brief Checks whether the command inhibit bit is set or not.
screamer 0:e4d670b91a9a 407 *
screamer 0:e4d670b91a9a 408 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 409 * @return 1 if command inhibit, 0 if not.
screamer 0:e4d670b91a9a 410 */
screamer 0:e4d670b91a9a 411 static inline uint32_t SDHC_HAL_IsCmdInhibit(uint32_t baseAddr)
screamer 0:e4d670b91a9a 412 {
screamer 0:e4d670b91a9a 413 return BR_SDHC_PRSSTAT_CIHB(baseAddr);
screamer 0:e4d670b91a9a 414 }
screamer 0:e4d670b91a9a 415
screamer 0:e4d670b91a9a 416 /*!
screamer 0:e4d670b91a9a 417 * @brief Checks whether data inhibit bit is set or not.
screamer 0:e4d670b91a9a 418 *
screamer 0:e4d670b91a9a 419 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 420 * @return 1 if data inhibit, 0 if not.
screamer 0:e4d670b91a9a 421 */
screamer 0:e4d670b91a9a 422 static inline uint32_t SDHC_HAL_IsDataInhibit(uint32_t baseAddr)
screamer 0:e4d670b91a9a 423 {
screamer 0:e4d670b91a9a 424 return BR_SDHC_PRSSTAT_CDIHB(baseAddr);
screamer 0:e4d670b91a9a 425 }
screamer 0:e4d670b91a9a 426
screamer 0:e4d670b91a9a 427 /*!
screamer 0:e4d670b91a9a 428 * @brief Checks whether data line is active.
screamer 0:e4d670b91a9a 429 *
screamer 0:e4d670b91a9a 430 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 431 * @return 1 if it's active, 0 if not.
screamer 0:e4d670b91a9a 432 */
screamer 0:e4d670b91a9a 433 static inline uint32_t SDHC_HAL_IsDataLineActive(uint32_t baseAddr)
screamer 0:e4d670b91a9a 434 {
screamer 0:e4d670b91a9a 435 return BR_SDHC_PRSSTAT_DLA(baseAddr);
screamer 0:e4d670b91a9a 436 }
screamer 0:e4d670b91a9a 437
screamer 0:e4d670b91a9a 438 /*!
screamer 0:e4d670b91a9a 439 * @brief Checks whether the SD clock is stable or not.
screamer 0:e4d670b91a9a 440 *
screamer 0:e4d670b91a9a 441 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 442 * @return 1 if it's stable, 0 if not.
screamer 0:e4d670b91a9a 443 */
screamer 0:e4d670b91a9a 444 static inline uint32_t SDHC_HAL_IsSdClockStable(uint32_t baseAddr)
screamer 0:e4d670b91a9a 445 {
screamer 0:e4d670b91a9a 446 return BR_SDHC_PRSSTAT_SDSTB(baseAddr);
screamer 0:e4d670b91a9a 447 }
screamer 0:e4d670b91a9a 448
screamer 0:e4d670b91a9a 449 /*!
screamer 0:e4d670b91a9a 450 * @brief Checks whether the IPG clock is off or not.
screamer 0:e4d670b91a9a 451 *
screamer 0:e4d670b91a9a 452 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 453 * @return 1 if it's off, 0 if not.
screamer 0:e4d670b91a9a 454 */
screamer 0:e4d670b91a9a 455 static inline uint32_t SDHC_HAL_IsIpgClockOff(uint32_t baseAddr)
screamer 0:e4d670b91a9a 456 {
screamer 0:e4d670b91a9a 457 return BR_SDHC_PRSSTAT_IPGOFF(baseAddr);
screamer 0:e4d670b91a9a 458 }
screamer 0:e4d670b91a9a 459
screamer 0:e4d670b91a9a 460 /*!
screamer 0:e4d670b91a9a 461 * @brief Checks whether the system clock is off or not.
screamer 0:e4d670b91a9a 462 *
screamer 0:e4d670b91a9a 463 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 464 * @return 1 if it's off, 0 if not.
screamer 0:e4d670b91a9a 465 */
screamer 0:e4d670b91a9a 466 static inline uint32_t SDHC_HAL_IsSysClockOff(uint32_t baseAddr)
screamer 0:e4d670b91a9a 467 {
screamer 0:e4d670b91a9a 468 return BR_SDHC_PRSSTAT_HCKOFF(baseAddr);
screamer 0:e4d670b91a9a 469 }
screamer 0:e4d670b91a9a 470
screamer 0:e4d670b91a9a 471 /*!
screamer 0:e4d670b91a9a 472 * @brief Checks whether the peripheral clock is off or not.
screamer 0:e4d670b91a9a 473 *
screamer 0:e4d670b91a9a 474 * @param baseAddr SDHC base address.
screamer 0:e4d670b91a9a 475 * @return 1 if it's off, 0 if not.
screamer 0:e4d670b91a9a 476 */
screamer 0:e4d670b91a9a 477 static inline uint32_t SDHC_HAL_IsPeripheralClockOff(uint32_t baseAddr)
screamer 0:e4d670b91a9a 478 {
screamer 0:e4d670b91a9a 479 return BR_SDHC_PRSSTAT_PEROFF(baseAddr);
screamer 0:e4d670b91a9a 480 }
screamer 0:e4d670b91a9a 481
screamer 0:e4d670b91a9a 482 /*!
screamer 0:e4d670b91a9a 483 * @brief Checks whether the SD clock is off or not.
screamer 0:e4d670b91a9a 484 *
screamer 0:e4d670b91a9a 485 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 486 * @return 1 if it's off, 0 if not.
screamer 0:e4d670b91a9a 487 */
screamer 0:e4d670b91a9a 488 static inline uint32_t SDHC_HAL_IsSdClkOff(uint32_t baseAddr)
screamer 0:e4d670b91a9a 489 {
screamer 0:e4d670b91a9a 490 return BR_SDHC_PRSSTAT_SDOFF(baseAddr);
screamer 0:e4d670b91a9a 491 }
screamer 0:e4d670b91a9a 492
screamer 0:e4d670b91a9a 493 /*!
screamer 0:e4d670b91a9a 494 * @brief Checks whether the write transfer is active or not.
screamer 0:e4d670b91a9a 495 *
screamer 0:e4d670b91a9a 496 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 497 * @return 1 if it's active, 0 if not.
screamer 0:e4d670b91a9a 498 */
screamer 0:e4d670b91a9a 499 static inline uint32_t SDHC_HAL_IsWriteTransferActive(uint32_t baseAddr)
screamer 0:e4d670b91a9a 500 {
screamer 0:e4d670b91a9a 501 return BR_SDHC_PRSSTAT_WTA(baseAddr);
screamer 0:e4d670b91a9a 502 }
screamer 0:e4d670b91a9a 503
screamer 0:e4d670b91a9a 504 /*!
screamer 0:e4d670b91a9a 505 * @brief Checks whether the read transfer is active or not.
screamer 0:e4d670b91a9a 506 *
screamer 0:e4d670b91a9a 507 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 508 * @return 1 if it's off, 0 if not.
screamer 0:e4d670b91a9a 509 */
screamer 0:e4d670b91a9a 510 static inline uint32_t SDHC_HAL_IsReadTransferActive(uint32_t baseAddr)
screamer 0:e4d670b91a9a 511 {
screamer 0:e4d670b91a9a 512 return BR_SDHC_PRSSTAT_RTA(baseAddr);
screamer 0:e4d670b91a9a 513 }
screamer 0:e4d670b91a9a 514
screamer 0:e4d670b91a9a 515 /*!
screamer 0:e4d670b91a9a 516 * @brief Check whether the buffer write is enabled or not.
screamer 0:e4d670b91a9a 517 *
screamer 0:e4d670b91a9a 518 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 519 * @return 1 if it's isEnabledd, 0 if not.
screamer 0:e4d670b91a9a 520 */
screamer 0:e4d670b91a9a 521 static inline uint32_t SDHC_HAL_IsBuffWriteEnabled(uint32_t baseAddr)
screamer 0:e4d670b91a9a 522 {
screamer 0:e4d670b91a9a 523 return BR_SDHC_PRSSTAT_BWEN(baseAddr);
screamer 0:e4d670b91a9a 524 }
screamer 0:e4d670b91a9a 525
screamer 0:e4d670b91a9a 526 /*!
screamer 0:e4d670b91a9a 527 * @brief Checks whether the buffer read is enabled or not.
screamer 0:e4d670b91a9a 528 *
screamer 0:e4d670b91a9a 529 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 530 * @return 1 if it's isEnabledd, 0 if not.
screamer 0:e4d670b91a9a 531 */
screamer 0:e4d670b91a9a 532 static inline uint32_t SDHC_HAL_IsBuffReadEnabled(uint32_t baseAddr)
screamer 0:e4d670b91a9a 533 {
screamer 0:e4d670b91a9a 534 return BR_SDHC_PRSSTAT_BREN(baseAddr);
screamer 0:e4d670b91a9a 535 }
screamer 0:e4d670b91a9a 536
screamer 0:e4d670b91a9a 537 /*!
screamer 0:e4d670b91a9a 538 * @brief Checks whether the card is inserted or not.
screamer 0:e4d670b91a9a 539 *
screamer 0:e4d670b91a9a 540 * @param baseAddr SDHC base address.
screamer 0:e4d670b91a9a 541 * @return 1 if it's inserted, 0 if not.
screamer 0:e4d670b91a9a 542 */
screamer 0:e4d670b91a9a 543 static inline uint32_t SDHC_HAL_IsCardInserted(uint32_t baseAddr)
screamer 0:e4d670b91a9a 544 {
screamer 0:e4d670b91a9a 545 return BR_SDHC_PRSSTAT_CINS(baseAddr);
screamer 0:e4d670b91a9a 546 }
screamer 0:e4d670b91a9a 547
screamer 0:e4d670b91a9a 548 /*!
screamer 0:e4d670b91a9a 549 * @brief Checks whether the command line signal is high or not.
screamer 0:e4d670b91a9a 550 *
screamer 0:e4d670b91a9a 551 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 552 * @return 1 if it's high, 0 if not.
screamer 0:e4d670b91a9a 553 */
screamer 0:e4d670b91a9a 554 static inline uint32_t SDHC_HAL_IsCmdLineLevelHigh(uint32_t baseAddr)
screamer 0:e4d670b91a9a 555 {
screamer 0:e4d670b91a9a 556 return BR_SDHC_PRSSTAT_CLSL(baseAddr);
screamer 0:e4d670b91a9a 557 }
screamer 0:e4d670b91a9a 558
screamer 0:e4d670b91a9a 559 /*!
screamer 0:e4d670b91a9a 560 * @brief Gets the data line signal level or not.
screamer 0:e4d670b91a9a 561 *
screamer 0:e4d670b91a9a 562 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 563 * @return [7:0] data line signal level
screamer 0:e4d670b91a9a 564 */
screamer 0:e4d670b91a9a 565 static inline uint32_t SDHC_HAL_GetDataLineLevel(uint32_t baseAddr)
screamer 0:e4d670b91a9a 566 {
screamer 0:e4d670b91a9a 567 return BR_SDHC_PRSSTAT_DLSL(baseAddr);
screamer 0:e4d670b91a9a 568 }
screamer 0:e4d670b91a9a 569
screamer 0:e4d670b91a9a 570 /*!
screamer 0:e4d670b91a9a 571 * @brief Sets the LED state.
screamer 0:e4d670b91a9a 572 *
screamer 0:e4d670b91a9a 573 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 574 * @param state the LED state
screamer 0:e4d670b91a9a 575 */
screamer 0:e4d670b91a9a 576 static inline void SDHC_HAL_SetLedState(uint32_t baseAddr, sdhc_hal_led_t state)
screamer 0:e4d670b91a9a 577 {
screamer 0:e4d670b91a9a 578 BW_SDHC_PROCTL_LCTL(baseAddr, state);
screamer 0:e4d670b91a9a 579 }
screamer 0:e4d670b91a9a 580
screamer 0:e4d670b91a9a 581 /*!
screamer 0:e4d670b91a9a 582 * @brief Sets the data transfer width.
screamer 0:e4d670b91a9a 583 *
screamer 0:e4d670b91a9a 584 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 585 * @param dtw data transfer width
screamer 0:e4d670b91a9a 586 */
screamer 0:e4d670b91a9a 587 static inline void SDHC_HAL_SetDataTransferWidth(uint32_t baseAddr, sdhc_hal_dtw_t dtw)
screamer 0:e4d670b91a9a 588 {
screamer 0:e4d670b91a9a 589 BW_SDHC_PROCTL_DTW(baseAddr, dtw);
screamer 0:e4d670b91a9a 590 }
screamer 0:e4d670b91a9a 591
screamer 0:e4d670b91a9a 592 /*!
screamer 0:e4d670b91a9a 593 * @brief Checks whether the DAT3 is taken as card detect pin.
screamer 0:e4d670b91a9a 594 *
screamer 0:e4d670b91a9a 595 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 596 * @return if DAT3 as card detect pin is enabled
screamer 0:e4d670b91a9a 597 */
screamer 0:e4d670b91a9a 598 static inline bool SDHC_HAL_IsD3cdEnabled(uint32_t baseAddr)
screamer 0:e4d670b91a9a 599 {
screamer 0:e4d670b91a9a 600 return BR_SDHC_PROCTL_D3CD(baseAddr);
screamer 0:e4d670b91a9a 601 }
screamer 0:e4d670b91a9a 602
screamer 0:e4d670b91a9a 603 /*!
screamer 0:e4d670b91a9a 604 * @brief Enables the DAT3 as a card detect pin.
screamer 0:e4d670b91a9a 605 *
screamer 0:e4d670b91a9a 606 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 607 * @param enable to enable DAT3 as card detect pin
screamer 0:e4d670b91a9a 608 */
screamer 0:e4d670b91a9a 609 static inline void SDHC_HAL_SetD3cd(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 610 {
screamer 0:e4d670b91a9a 611 BW_SDHC_PROCTL_D3CD(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 612 }
screamer 0:e4d670b91a9a 613
screamer 0:e4d670b91a9a 614 /*!
screamer 0:e4d670b91a9a 615 * @brief Configures the endian mode.
screamer 0:e4d670b91a9a 616 *
screamer 0:e4d670b91a9a 617 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 618 * @param endianMode endian mode
screamer 0:e4d670b91a9a 619 */
screamer 0:e4d670b91a9a 620 static inline void SDHC_HAL_SetEndian(uint32_t baseAddr, sdhc_hal_endian_t endianMode)
screamer 0:e4d670b91a9a 621 {
screamer 0:e4d670b91a9a 622 BW_SDHC_PROCTL_EMODE(baseAddr, endianMode);
screamer 0:e4d670b91a9a 623 }
screamer 0:e4d670b91a9a 624
screamer 0:e4d670b91a9a 625 /*!
screamer 0:e4d670b91a9a 626 * @brief Gets the card detect test level.
screamer 0:e4d670b91a9a 627 *
screamer 0:e4d670b91a9a 628 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 629 * @return card detect test level
screamer 0:e4d670b91a9a 630 */
screamer 0:e4d670b91a9a 631 static inline uint32_t SDHC_HAL_GetCdTestLevel(uint32_t baseAddr)
screamer 0:e4d670b91a9a 632 {
screamer 0:e4d670b91a9a 633 return BR_SDHC_PROCTL_CDTL(baseAddr);
screamer 0:e4d670b91a9a 634 }
screamer 0:e4d670b91a9a 635
screamer 0:e4d670b91a9a 636 /*!
screamer 0:e4d670b91a9a 637 * @brief Enables the card detect test.
screamer 0:e4d670b91a9a 638 *
screamer 0:e4d670b91a9a 639 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 640 * @param enable to enable card detect signal for test purpose
screamer 0:e4d670b91a9a 641 */
screamer 0:e4d670b91a9a 642 static inline void SDHC_HAL_SetCdTest(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 643 {
screamer 0:e4d670b91a9a 644 BW_SDHC_PROCTL_CDSS(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 645 }
screamer 0:e4d670b91a9a 646
screamer 0:e4d670b91a9a 647 /*!
screamer 0:e4d670b91a9a 648 * @brief Sets the DMA mode.
screamer 0:e4d670b91a9a 649 *
screamer 0:e4d670b91a9a 650 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 651 * @param dmaMode the DMA mode
screamer 0:e4d670b91a9a 652 */
screamer 0:e4d670b91a9a 653 static inline void SDHC_HAL_SetDmaMode(uint32_t baseAddr, sdhc_hal_dma_mode_t dmaMode)
screamer 0:e4d670b91a9a 654 {
screamer 0:e4d670b91a9a 655 BW_SDHC_PROCTL_DMAS(baseAddr, dmaMode);
screamer 0:e4d670b91a9a 656 }
screamer 0:e4d670b91a9a 657
screamer 0:e4d670b91a9a 658 /*!
screamer 0:e4d670b91a9a 659 * @brief Enables stop at the block gap.
screamer 0:e4d670b91a9a 660 *
screamer 0:e4d670b91a9a 661 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 662 * @param enable to stop at block gap request
screamer 0:e4d670b91a9a 663 */
screamer 0:e4d670b91a9a 664 static inline void SDHC_HAL_SetStopAtBlockGap(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 665 {
screamer 0:e4d670b91a9a 666 BW_SDHC_PROCTL_SABGREQ(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 667 }
screamer 0:e4d670b91a9a 668
screamer 0:e4d670b91a9a 669 /*!
screamer 0:e4d670b91a9a 670 * @brief Restarts a transaction which has stopped at the block gap.
screamer 0:e4d670b91a9a 671 *
screamer 0:e4d670b91a9a 672 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 673 */
screamer 0:e4d670b91a9a 674 static inline void SDHC_HAL_SetContinueRequest(uint32_t baseAddr)
screamer 0:e4d670b91a9a 675 {
screamer 0:e4d670b91a9a 676 BW_SDHC_PROCTL_CREQ(baseAddr, 1);
screamer 0:e4d670b91a9a 677 }
screamer 0:e4d670b91a9a 678
screamer 0:e4d670b91a9a 679 /*!
screamer 0:e4d670b91a9a 680 * @brief Enables the read wait control for the SDIO cards.
screamer 0:e4d670b91a9a 681 *
screamer 0:e4d670b91a9a 682 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 683 * @param enable to enable read wait control
screamer 0:e4d670b91a9a 684 */
screamer 0:e4d670b91a9a 685 static inline void SDHC_HAL_SetReadWaitCtrl(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 686 {
screamer 0:e4d670b91a9a 687 BW_SDHC_PROCTL_RWCTL(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 688 }
screamer 0:e4d670b91a9a 689
screamer 0:e4d670b91a9a 690 /*!
screamer 0:e4d670b91a9a 691 * @brief Enables stop at the block gap requests.
screamer 0:e4d670b91a9a 692 *
screamer 0:e4d670b91a9a 693 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 694 * @param enable to enable interrupt at block gap
screamer 0:e4d670b91a9a 695 */
screamer 0:e4d670b91a9a 696 static inline void SDHC_HAL_SetIntStopAtBlockGap(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 697 {
screamer 0:e4d670b91a9a 698 BW_SDHC_PROCTL_IABG(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 699 }
screamer 0:e4d670b91a9a 700
screamer 0:e4d670b91a9a 701 /*!
screamer 0:e4d670b91a9a 702 * @brief Enables wakeup event on the card interrupt.
screamer 0:e4d670b91a9a 703 *
screamer 0:e4d670b91a9a 704 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 705 * @param enable to enable wakeup event on card interrupt
screamer 0:e4d670b91a9a 706 */
screamer 0:e4d670b91a9a 707 static inline void SDHC_HAL_SetWakeupOnCardInt(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 708 {
screamer 0:e4d670b91a9a 709 BW_SDHC_PROCTL_WECINT(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 710 }
screamer 0:e4d670b91a9a 711
screamer 0:e4d670b91a9a 712 /*!
screamer 0:e4d670b91a9a 713 * @brief Enables wakeup event on the card insertion.
screamer 0:e4d670b91a9a 714 *
screamer 0:e4d670b91a9a 715 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 716 * @param enable to enable wakeup event on card insertion
screamer 0:e4d670b91a9a 717 */
screamer 0:e4d670b91a9a 718 static inline void SDHC_HAL_SetWakeupOnCardInsertion(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 719 {
screamer 0:e4d670b91a9a 720 BW_SDHC_PROCTL_WECINS(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 721 }
screamer 0:e4d670b91a9a 722
screamer 0:e4d670b91a9a 723 /*!
screamer 0:e4d670b91a9a 724 * @brief Enables wakeup event on card removal.
screamer 0:e4d670b91a9a 725 *
screamer 0:e4d670b91a9a 726 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 727 * @param enable to enable wakeup event on card removal
screamer 0:e4d670b91a9a 728 */
screamer 0:e4d670b91a9a 729 static inline void SDHC_HAL_SetWakeupOnCardRemoval(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 730 {
screamer 0:e4d670b91a9a 731 BW_SDHC_PROCTL_WECRM(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 732 }
screamer 0:e4d670b91a9a 733
screamer 0:e4d670b91a9a 734 /*!
screamer 0:e4d670b91a9a 735 * @brief Enables the IPG clock and no automatic clock gating off.
screamer 0:e4d670b91a9a 736 *
screamer 0:e4d670b91a9a 737 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 738 * @param enable to enable IPG clock
screamer 0:e4d670b91a9a 739 */
screamer 0:e4d670b91a9a 740 static inline void SDHC_HAL_SetIpgClock(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 741 {
screamer 0:e4d670b91a9a 742 BW_SDHC_SYSCTL_IPGEN(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 743 }
screamer 0:e4d670b91a9a 744
screamer 0:e4d670b91a9a 745 /*!
screamer 0:e4d670b91a9a 746 * @brief Enables the system clock and no automatic clock gating off.
screamer 0:e4d670b91a9a 747 *
screamer 0:e4d670b91a9a 748 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 749 * @param enable to enable SYS clock
screamer 0:e4d670b91a9a 750 */
screamer 0:e4d670b91a9a 751 static inline void SDHC_HAL_SetSysClock(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 752 {
screamer 0:e4d670b91a9a 753 BW_SDHC_SYSCTL_HCKEN(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 754 }
screamer 0:e4d670b91a9a 755
screamer 0:e4d670b91a9a 756 /*!
screamer 0:e4d670b91a9a 757 * @brief Enables the peripheral clock and no automatic clock gating off.
screamer 0:e4d670b91a9a 758 *
screamer 0:e4d670b91a9a 759 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 760 * @param enable to enable Peripheral clock
screamer 0:e4d670b91a9a 761 */
screamer 0:e4d670b91a9a 762 static inline void SDHC_HAL_SetPeripheralClock(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 763 {
screamer 0:e4d670b91a9a 764 BW_SDHC_SYSCTL_PEREN(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 765 }
screamer 0:e4d670b91a9a 766
screamer 0:e4d670b91a9a 767 /*!
screamer 0:e4d670b91a9a 768 * @brief Enables the SD clock. It should be disabled before changing the SD clock
screamer 0:e4d670b91a9a 769 * frequency.
screamer 0:e4d670b91a9a 770 *
screamer 0:e4d670b91a9a 771 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 772 * @param enable to enable SD clock or not
screamer 0:e4d670b91a9a 773 */
screamer 0:e4d670b91a9a 774 static inline void SDHC_HAL_SetSdClock(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 775 {
screamer 0:e4d670b91a9a 776 BW_SDHC_SYSCTL_SDCLKEN(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 777 }
screamer 0:e4d670b91a9a 778
screamer 0:e4d670b91a9a 779 /*!
screamer 0:e4d670b91a9a 780 * @brief Sets the SD clock frequency divisor.
screamer 0:e4d670b91a9a 781 *
screamer 0:e4d670b91a9a 782 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 783 * @param divisor the divisor
screamer 0:e4d670b91a9a 784 */
screamer 0:e4d670b91a9a 785 static inline void SDHC_HAL_SetClockDivisor(uint32_t baseAddr, uint32_t divisor)
screamer 0:e4d670b91a9a 786 {
screamer 0:e4d670b91a9a 787 BW_SDHC_SYSCTL_DVS(baseAddr, divisor);
screamer 0:e4d670b91a9a 788 }
screamer 0:e4d670b91a9a 789
screamer 0:e4d670b91a9a 790 /*!
screamer 0:e4d670b91a9a 791 * @brief Sets the SD clock frequency select.
screamer 0:e4d670b91a9a 792 *
screamer 0:e4d670b91a9a 793 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 794 * @param frequency the frequency selector
screamer 0:e4d670b91a9a 795 */
screamer 0:e4d670b91a9a 796 static inline void SDHC_HAL_SetClockFrequency(uint32_t baseAddr, uint32_t frequency)
screamer 0:e4d670b91a9a 797 {
screamer 0:e4d670b91a9a 798 BW_SDHC_SYSCTL_SDCLKFS(baseAddr, frequency);
screamer 0:e4d670b91a9a 799 }
screamer 0:e4d670b91a9a 800
screamer 0:e4d670b91a9a 801 /*!
screamer 0:e4d670b91a9a 802 * @brief Sets the data timeout counter value.
screamer 0:e4d670b91a9a 803 *
screamer 0:e4d670b91a9a 804 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 805 * @param timeout Data timeout counter value
screamer 0:e4d670b91a9a 806 */
screamer 0:e4d670b91a9a 807 static inline void SDHC_HAL_SetDataTimeout(uint32_t baseAddr, uint32_t timeout)
screamer 0:e4d670b91a9a 808 {
screamer 0:e4d670b91a9a 809 BW_SDHC_SYSCTL_DTOCV(baseAddr, timeout);
screamer 0:e4d670b91a9a 810 }
screamer 0:e4d670b91a9a 811
screamer 0:e4d670b91a9a 812 /*!
screamer 0:e4d670b91a9a 813 * @brief Gets the current interrupt status.
screamer 0:e4d670b91a9a 814 *
screamer 0:e4d670b91a9a 815 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 816 * @return current interrupt flags
screamer 0:e4d670b91a9a 817 */
screamer 0:e4d670b91a9a 818 static inline uint32_t SDHC_HAL_GetIntFlags(uint32_t baseAddr)
screamer 0:e4d670b91a9a 819 {
screamer 0:e4d670b91a9a 820 return HW_SDHC_IRQSTAT_RD(baseAddr);
screamer 0:e4d670b91a9a 821 }
screamer 0:e4d670b91a9a 822
screamer 0:e4d670b91a9a 823 /*!
screamer 0:e4d670b91a9a 824 * @brief Clears a specified interrupt status.
screamer 0:e4d670b91a9a 825 *
screamer 0:e4d670b91a9a 826 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 827 * @param mask to specify interrupts' flags to be cleared
screamer 0:e4d670b91a9a 828 */
screamer 0:e4d670b91a9a 829 static inline void SDHC_HAL_ClearIntFlags(uint32_t baseAddr, uint32_t mask)
screamer 0:e4d670b91a9a 830 {
screamer 0:e4d670b91a9a 831 HW_SDHC_IRQSTAT_WR(baseAddr, mask);
screamer 0:e4d670b91a9a 832 }
screamer 0:e4d670b91a9a 833
screamer 0:e4d670b91a9a 834 /*!
screamer 0:e4d670b91a9a 835 * @brief Gets the currently enabled interrupt signal.
screamer 0:e4d670b91a9a 836 *
screamer 0:e4d670b91a9a 837 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 838 * @return currently enabled interrupt signal
screamer 0:e4d670b91a9a 839 */
screamer 0:e4d670b91a9a 840 static inline uint32_t SDHC_HAL_GetIntSignal(uint32_t baseAddr)
screamer 0:e4d670b91a9a 841 {
screamer 0:e4d670b91a9a 842 return HW_SDHC_IRQSIGEN_RD(baseAddr);
screamer 0:e4d670b91a9a 843 }
screamer 0:e4d670b91a9a 844
screamer 0:e4d670b91a9a 845 /*!
screamer 0:e4d670b91a9a 846 * @brief Gets the currently enabled interrupt state.
screamer 0:e4d670b91a9a 847 *
screamer 0:e4d670b91a9a 848 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 849 * @return currently enabled interrupts' state
screamer 0:e4d670b91a9a 850 */
screamer 0:e4d670b91a9a 851 static inline uint32_t SDHC_HAL_GetIntState(uint32_t baseAddr)
screamer 0:e4d670b91a9a 852 {
screamer 0:e4d670b91a9a 853 return HW_SDHC_IRQSTATEN_RD(baseAddr);
screamer 0:e4d670b91a9a 854 }
screamer 0:e4d670b91a9a 855
screamer 0:e4d670b91a9a 856 /*!
screamer 0:e4d670b91a9a 857 * @brief Gets the auto cmd12 error.
screamer 0:e4d670b91a9a 858 *
screamer 0:e4d670b91a9a 859 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 860 * @return auto cmd12 error status
screamer 0:e4d670b91a9a 861 */
screamer 0:e4d670b91a9a 862 static inline uint32_t SDHC_HAL_GetAc12Error(uint32_t baseAddr)
screamer 0:e4d670b91a9a 863 {
screamer 0:e4d670b91a9a 864 return HW_SDHC_AC12ERR_RD(baseAddr);
screamer 0:e4d670b91a9a 865 }
screamer 0:e4d670b91a9a 866
screamer 0:e4d670b91a9a 867 /*!
screamer 0:e4d670b91a9a 868 * @brief Gets the maximum block length supported.
screamer 0:e4d670b91a9a 869 *
screamer 0:e4d670b91a9a 870 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 871 * @return the maximum block length support
screamer 0:e4d670b91a9a 872 */
screamer 0:e4d670b91a9a 873 static inline uint32_t SDHC_HAL_GetMaxBlockLength(uint32_t baseAddr)
screamer 0:e4d670b91a9a 874 {
screamer 0:e4d670b91a9a 875 return BR_SDHC_HTCAPBLT_MBL(baseAddr);
screamer 0:e4d670b91a9a 876 }
screamer 0:e4d670b91a9a 877
screamer 0:e4d670b91a9a 878 /*!
screamer 0:e4d670b91a9a 879 * @brief Checks whether the ADMA is supported.
screamer 0:e4d670b91a9a 880 *
screamer 0:e4d670b91a9a 881 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 882 * @return if ADMA is supported
screamer 0:e4d670b91a9a 883 */
screamer 0:e4d670b91a9a 884 static inline uint32_t SDHC_HAL_DoesHostSupportAdma(uint32_t baseAddr)
screamer 0:e4d670b91a9a 885 {
screamer 0:e4d670b91a9a 886 return BR_SDHC_HTCAPBLT_ADMAS(baseAddr);
screamer 0:e4d670b91a9a 887 }
screamer 0:e4d670b91a9a 888
screamer 0:e4d670b91a9a 889 /*!
screamer 0:e4d670b91a9a 890 * @brief Checks whether the high speed is supported.
screamer 0:e4d670b91a9a 891 *
screamer 0:e4d670b91a9a 892 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 893 * @return if high speed is supported
screamer 0:e4d670b91a9a 894 */
screamer 0:e4d670b91a9a 895 static inline uint32_t SDHC_HAL_DoesHostSupportHighspeed(uint32_t baseAddr)
screamer 0:e4d670b91a9a 896 {
screamer 0:e4d670b91a9a 897 return BR_SDHC_HTCAPBLT_HSS(baseAddr);
screamer 0:e4d670b91a9a 898 }
screamer 0:e4d670b91a9a 899
screamer 0:e4d670b91a9a 900 /*!
screamer 0:e4d670b91a9a 901 * @brief Checks whether the DMA is supported.
screamer 0:e4d670b91a9a 902 *
screamer 0:e4d670b91a9a 903 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 904 * @return if high speed is supported
screamer 0:e4d670b91a9a 905 */
screamer 0:e4d670b91a9a 906 static inline uint32_t SDHC_HAL_DoesHostSupportDma(uint32_t baseAddr)
screamer 0:e4d670b91a9a 907 {
screamer 0:e4d670b91a9a 908 return BR_SDHC_HTCAPBLT_DMAS(baseAddr);
screamer 0:e4d670b91a9a 909 }
screamer 0:e4d670b91a9a 910
screamer 0:e4d670b91a9a 911 /*!
screamer 0:e4d670b91a9a 912 * @brief Checks whether the suspend/resume is supported.
screamer 0:e4d670b91a9a 913 *
screamer 0:e4d670b91a9a 914 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 915 * @return if suspend and resume is supported
screamer 0:e4d670b91a9a 916 */
screamer 0:e4d670b91a9a 917 static inline uint32_t SDHC_HAL_DoesHostSupportSuspendResume(uint32_t baseAddr)
screamer 0:e4d670b91a9a 918 {
screamer 0:e4d670b91a9a 919 return BR_SDHC_HTCAPBLT_SRS(baseAddr);
screamer 0:e4d670b91a9a 920 }
screamer 0:e4d670b91a9a 921
screamer 0:e4d670b91a9a 922 /*!
screamer 0:e4d670b91a9a 923 * @brief Checks whether the voltage 3.3 is supported.
screamer 0:e4d670b91a9a 924 *
screamer 0:e4d670b91a9a 925 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 926 * @return if voltage 3.3 is supported
screamer 0:e4d670b91a9a 927 */
screamer 0:e4d670b91a9a 928 static inline uint32_t SDHC_HAL_DoesHostSupportV330(uint32_t baseAddr)
screamer 0:e4d670b91a9a 929 {
screamer 0:e4d670b91a9a 930 return BR_SDHC_HTCAPBLT_VS33(baseAddr);
screamer 0:e4d670b91a9a 931 }
screamer 0:e4d670b91a9a 932
screamer 0:e4d670b91a9a 933 /*!
screamer 0:e4d670b91a9a 934 * @brief Checks whether the voltage 3.0 is supported.
screamer 0:e4d670b91a9a 935 *
screamer 0:e4d670b91a9a 936 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 937 * @return if voltage 3.0 is supported
screamer 0:e4d670b91a9a 938 */
screamer 0:e4d670b91a9a 939 static inline uint32_t SDHC_HAL_DoesHostSupportV300(uint32_t baseAddr)
screamer 0:e4d670b91a9a 940 {
screamer 0:e4d670b91a9a 941 #if defined(FSL_FEATURE_SDHC_HAS_V300_SUPPORT) && FSL_FEATURE_SDHC_HAS_V300_SUPPORT
screamer 0:e4d670b91a9a 942 return BR_SDHC_HTCAPBLT_VS30(baseAddr);
screamer 0:e4d670b91a9a 943 #else
screamer 0:e4d670b91a9a 944 return 0;
screamer 0:e4d670b91a9a 945 #endif
screamer 0:e4d670b91a9a 946 }
screamer 0:e4d670b91a9a 947
screamer 0:e4d670b91a9a 948 /*!
screamer 0:e4d670b91a9a 949 * @brief Checks whether the voltage 1.8 is supported.
screamer 0:e4d670b91a9a 950 *
screamer 0:e4d670b91a9a 951 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 952 * @return if voltage 1.8 is supported
screamer 0:e4d670b91a9a 953 */
screamer 0:e4d670b91a9a 954 static inline uint32_t SDHC_HAL_DoesHostSupportV180(uint32_t baseAddr)
screamer 0:e4d670b91a9a 955 {
screamer 0:e4d670b91a9a 956 #if defined(FSL_FEATURE_SDHC_HAS_V180_SUPPORT) && FSL_FEATURE_SDHC_HAS_V180_SUPPORT
screamer 0:e4d670b91a9a 957 return BR_SDHC_HTCAPBLT_VS18(baseAddr);
screamer 0:e4d670b91a9a 958 #else
screamer 0:e4d670b91a9a 959 return 0;
screamer 0:e4d670b91a9a 960 #endif
screamer 0:e4d670b91a9a 961 }
screamer 0:e4d670b91a9a 962
screamer 0:e4d670b91a9a 963 /*!
screamer 0:e4d670b91a9a 964 * @brief Sets the watermark for writing.
screamer 0:e4d670b91a9a 965 *
screamer 0:e4d670b91a9a 966 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 967 * @param watermark for writing
screamer 0:e4d670b91a9a 968 */
screamer 0:e4d670b91a9a 969 static inline void SDHC_HAL_SetWriteWatermarkLevel(uint32_t baseAddr, uint32_t watermark)
screamer 0:e4d670b91a9a 970 {
screamer 0:e4d670b91a9a 971 BW_SDHC_WML_WRWML(baseAddr, watermark);
screamer 0:e4d670b91a9a 972 }
screamer 0:e4d670b91a9a 973
screamer 0:e4d670b91a9a 974 /*!
screamer 0:e4d670b91a9a 975 * @brief Sets the watermark for reading.
screamer 0:e4d670b91a9a 976 *
screamer 0:e4d670b91a9a 977 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 978 * @param watermark for reading
screamer 0:e4d670b91a9a 979 */
screamer 0:e4d670b91a9a 980 static inline void SDHC_HAL_SetReadWatermarkLevel(uint32_t baseAddr, uint32_t watermark)
screamer 0:e4d670b91a9a 981 {
screamer 0:e4d670b91a9a 982 BW_SDHC_WML_RDWML(baseAddr, watermark);
screamer 0:e4d670b91a9a 983 }
screamer 0:e4d670b91a9a 984
screamer 0:e4d670b91a9a 985 /*!
screamer 0:e4d670b91a9a 986 * @brief Sets the force events according to the given mask.
screamer 0:e4d670b91a9a 987 *
screamer 0:e4d670b91a9a 988 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 989 * @param mask to specify the force events' flags to be set
screamer 0:e4d670b91a9a 990 */
screamer 0:e4d670b91a9a 991 static inline void SDHC_HAL_SetForceEventFlags(uint32_t baseAddr, uint32_t mask)
screamer 0:e4d670b91a9a 992 {
screamer 0:e4d670b91a9a 993 HW_SDHC_FEVT_WR(baseAddr, mask);
screamer 0:e4d670b91a9a 994 }
screamer 0:e4d670b91a9a 995
screamer 0:e4d670b91a9a 996 /*!
screamer 0:e4d670b91a9a 997 * @brief Checks whether the ADMA error is length mismatch.
screamer 0:e4d670b91a9a 998 *
screamer 0:e4d670b91a9a 999 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 1000 * @return if ADMA error is length mismatch
screamer 0:e4d670b91a9a 1001 */
screamer 0:e4d670b91a9a 1002 static inline uint32_t SDHC_HAL_IsAdmaLengthMismatchError(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1003 {
screamer 0:e4d670b91a9a 1004 return BR_SDHC_ADMAES_ADMALME(baseAddr);
screamer 0:e4d670b91a9a 1005 }
screamer 0:e4d670b91a9a 1006
screamer 0:e4d670b91a9a 1007 /*!
screamer 0:e4d670b91a9a 1008 * @brief Checks the SD clock.
screamer 0:e4d670b91a9a 1009 *
screamer 0:e4d670b91a9a 1010 * Checks whether the clock to the SD is enabled.
screamer 0:e4d670b91a9a 1011 *
screamer 0:e4d670b91a9a 1012 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 1013 * @return true if enabled
screamer 0:e4d670b91a9a 1014 */
screamer 0:e4d670b91a9a 1015 static inline bool SDHC_HAL_IsSdClockOff(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1016 {
screamer 0:e4d670b91a9a 1017 return BR_SDHC_SYSCTL_SDCLKEN(baseAddr);
screamer 0:e4d670b91a9a 1018 }
screamer 0:e4d670b91a9a 1019
screamer 0:e4d670b91a9a 1020 /*!
screamer 0:e4d670b91a9a 1021 * @brief Returns the state of the ADMA error.
screamer 0:e4d670b91a9a 1022 *
screamer 0:e4d670b91a9a 1023 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 1024 * @return error state
screamer 0:e4d670b91a9a 1025 */
screamer 0:e4d670b91a9a 1026 static inline uint32_t SDHC_HAL_GetAdmaErrorState(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1027 {
screamer 0:e4d670b91a9a 1028 return BR_SDHC_ADMAES_ADMAES(baseAddr);
screamer 0:e4d670b91a9a 1029 }
screamer 0:e4d670b91a9a 1030
screamer 0:e4d670b91a9a 1031 /*!
screamer 0:e4d670b91a9a 1032 * @brief Checks whether the ADMA error is a descriptor error.
screamer 0:e4d670b91a9a 1033 *
screamer 0:e4d670b91a9a 1034 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 1035 * @return if ADMA error is descriptor error
screamer 0:e4d670b91a9a 1036 */
screamer 0:e4d670b91a9a 1037 static inline uint32_t SDHC_HAL_IsAdmaDescriptionError(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1038 {
screamer 0:e4d670b91a9a 1039 return BR_SDHC_ADMAES_ADMADCE(baseAddr);
screamer 0:e4d670b91a9a 1040 }
screamer 0:e4d670b91a9a 1041
screamer 0:e4d670b91a9a 1042 /*!
screamer 0:e4d670b91a9a 1043 * @brief Sets the ADMA address.
screamer 0:e4d670b91a9a 1044 *
screamer 0:e4d670b91a9a 1045 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 1046 * @param address for ADMA transfer
screamer 0:e4d670b91a9a 1047 */
screamer 0:e4d670b91a9a 1048 static inline void SDHC_HAL_SetAdmaAddress(uint32_t baseAddr, uint32_t address)
screamer 0:e4d670b91a9a 1049 {
screamer 0:e4d670b91a9a 1050 HW_SDHC_ADSADDR_WR(baseAddr, address);
screamer 0:e4d670b91a9a 1051 }
screamer 0:e4d670b91a9a 1052
screamer 0:e4d670b91a9a 1053 /*!
screamer 0:e4d670b91a9a 1054 * @brief Enables the external DMA request.
screamer 0:e4d670b91a9a 1055 *
screamer 0:e4d670b91a9a 1056 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 1057 * @param enable to external DMA
screamer 0:e4d670b91a9a 1058 */
screamer 0:e4d670b91a9a 1059 static inline void SDHC_HAL_SetExternalDmaRequest(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 1060 {
screamer 0:e4d670b91a9a 1061 BW_SDHC_VENDOR_EXTDMAEN(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1062 }
screamer 0:e4d670b91a9a 1063
screamer 0:e4d670b91a9a 1064 /*!
screamer 0:e4d670b91a9a 1065 * @brief Enables the exact block number for the SDIO CMD53.
screamer 0:e4d670b91a9a 1066 *
screamer 0:e4d670b91a9a 1067 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 1068 * @param enable to enable exact block number block read for SDIO CMD53
screamer 0:e4d670b91a9a 1069 */
screamer 0:e4d670b91a9a 1070 static inline void SDHC_HAL_SetExactBlockNumber(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 1071 {
screamer 0:e4d670b91a9a 1072 BW_SDHC_VENDOR_EXBLKNU(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1073 }
screamer 0:e4d670b91a9a 1074
screamer 0:e4d670b91a9a 1075 /*!
screamer 0:e4d670b91a9a 1076 * @brief Sets the timeout value for the boot ACK.
screamer 0:e4d670b91a9a 1077 *
screamer 0:e4d670b91a9a 1078 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 1079 * @param timeout boot ack time out counter value
screamer 0:e4d670b91a9a 1080 */
screamer 0:e4d670b91a9a 1081 static inline void SDHC_HAL_SetBootAckTimeout(uint32_t baseAddr, uint32_t timeout)
screamer 0:e4d670b91a9a 1082 {
screamer 0:e4d670b91a9a 1083 BW_SDHC_MMCBOOT_DTOCVACK(baseAddr, timeout);
screamer 0:e4d670b91a9a 1084 }
screamer 0:e4d670b91a9a 1085
screamer 0:e4d670b91a9a 1086 /*!
screamer 0:e4d670b91a9a 1087 * @brief Enables the boot ACK.
screamer 0:e4d670b91a9a 1088 *
screamer 0:e4d670b91a9a 1089 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 1090 * @param enable to enable boot ack mode
screamer 0:e4d670b91a9a 1091 */
screamer 0:e4d670b91a9a 1092 static inline void SDHC_HAL_SetBootAck(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 1093 {
screamer 0:e4d670b91a9a 1094 BW_SDHC_MMCBOOT_BOOTACK(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1095 }
screamer 0:e4d670b91a9a 1096
screamer 0:e4d670b91a9a 1097 /*!
screamer 0:e4d670b91a9a 1098 * @brief Configures the boot mode.
screamer 0:e4d670b91a9a 1099 *
screamer 0:e4d670b91a9a 1100 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 1101 * @param mode the boot mode
screamer 0:e4d670b91a9a 1102 */
screamer 0:e4d670b91a9a 1103 static inline void SDHC_HAL_SetBootMode(uint32_t baseAddr, sdhc_hal_mmcboot_t mode)
screamer 0:e4d670b91a9a 1104 {
screamer 0:e4d670b91a9a 1105 BW_SDHC_MMCBOOT_BOOTMODE(baseAddr, mode);
screamer 0:e4d670b91a9a 1106 }
screamer 0:e4d670b91a9a 1107
screamer 0:e4d670b91a9a 1108 /*!
screamer 0:e4d670b91a9a 1109 * @brief Enables the fast boot.
screamer 0:e4d670b91a9a 1110 *
screamer 0:e4d670b91a9a 1111 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 1112 * @param enable to enable fast boot
screamer 0:e4d670b91a9a 1113 */
screamer 0:e4d670b91a9a 1114 static inline void SDHC_HAL_SetFastboot(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 1115 {
screamer 0:e4d670b91a9a 1116 BW_SDHC_MMCBOOT_BOOTEN(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1117 }
screamer 0:e4d670b91a9a 1118
screamer 0:e4d670b91a9a 1119 /*!
screamer 0:e4d670b91a9a 1120 * @brief Enables the automatic stop at the block gap.
screamer 0:e4d670b91a9a 1121 *
screamer 0:e4d670b91a9a 1122 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 1123 * @param enable to enable auto stop at block gap function, when boot.
screamer 0:e4d670b91a9a 1124 */
screamer 0:e4d670b91a9a 1125 static inline void SDHC_HAL_SetAutoStopAtBlockGap(uint32_t baseAddr, bool enable)
screamer 0:e4d670b91a9a 1126 {
screamer 0:e4d670b91a9a 1127 BW_SDHC_MMCBOOT_AUTOSABGEN(baseAddr, enable ? 1 : 0);
screamer 0:e4d670b91a9a 1128 }
screamer 0:e4d670b91a9a 1129
screamer 0:e4d670b91a9a 1130 /*!
screamer 0:e4d670b91a9a 1131 * @brief Configures the the block count for the boot.
screamer 0:e4d670b91a9a 1132 *
screamer 0:e4d670b91a9a 1133 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 1134 * @param blockCount the block count for boot
screamer 0:e4d670b91a9a 1135 */
screamer 0:e4d670b91a9a 1136 static inline void SDHC_HAL_SetBootBlockCount(uint32_t baseAddr, uint32_t blockCount)
screamer 0:e4d670b91a9a 1137 {
screamer 0:e4d670b91a9a 1138 BW_SDHC_MMCBOOT_BOOTBLKCNT(baseAddr, blockCount);
screamer 0:e4d670b91a9a 1139 }
screamer 0:e4d670b91a9a 1140
screamer 0:e4d670b91a9a 1141 /*!
screamer 0:e4d670b91a9a 1142 * @brief Gets a specification version.
screamer 0:e4d670b91a9a 1143 *
screamer 0:e4d670b91a9a 1144 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 1145 * @return specification version
screamer 0:e4d670b91a9a 1146 */
screamer 0:e4d670b91a9a 1147 static inline uint32_t SDHC_HAL_GetSpecificationVersion(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1148 {
screamer 0:e4d670b91a9a 1149 return BR_SDHC_HOSTVER_SVN(baseAddr);
screamer 0:e4d670b91a9a 1150 }
screamer 0:e4d670b91a9a 1151
screamer 0:e4d670b91a9a 1152 /*!
screamer 0:e4d670b91a9a 1153 * @brief Gets the vendor version.
screamer 0:e4d670b91a9a 1154 *
screamer 0:e4d670b91a9a 1155 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 1156 * @return vendor version
screamer 0:e4d670b91a9a 1157 */
screamer 0:e4d670b91a9a 1158 static inline uint32_t SDHC_HAL_GetVendorVersion(uint32_t baseAddr)
screamer 0:e4d670b91a9a 1159 {
screamer 0:e4d670b91a9a 1160 return BR_SDHC_HOSTVER_VVN(baseAddr);
screamer 0:e4d670b91a9a 1161 }
screamer 0:e4d670b91a9a 1162
screamer 0:e4d670b91a9a 1163 /*!
screamer 0:e4d670b91a9a 1164 * @brief Gets the command response.
screamer 0:e4d670b91a9a 1165 *
screamer 0:e4d670b91a9a 1166 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 1167 * @param index of response register, range from 0 to 3
screamer 0:e4d670b91a9a 1168 */
screamer 0:e4d670b91a9a 1169 uint32_t SDHC_HAL_GetResponse(uint32_t baseAddr, uint32_t index);
screamer 0:e4d670b91a9a 1170
screamer 0:e4d670b91a9a 1171 /*!
screamer 0:e4d670b91a9a 1172 * @brief Enables the specified interrupts.
screamer 0:e4d670b91a9a 1173 *
screamer 0:e4d670b91a9a 1174 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 1175 * @param enable enable or disable
screamer 0:e4d670b91a9a 1176 * @param mask to specify interrupts to be isEnabledd
screamer 0:e4d670b91a9a 1177 */
screamer 0:e4d670b91a9a 1178 void SDHC_HAL_SetIntSignal(uint32_t baseAddr, bool enable, uint32_t mask);
screamer 0:e4d670b91a9a 1179
screamer 0:e4d670b91a9a 1180 /*!
screamer 0:e4d670b91a9a 1181 * @brief Enables the specified interrupt state.
screamer 0:e4d670b91a9a 1182 *
screamer 0:e4d670b91a9a 1183 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 1184 * @param enable enable or disable
screamer 0:e4d670b91a9a 1185 * @param mask to specify interrupts' state to be enabled
screamer 0:e4d670b91a9a 1186 */
screamer 0:e4d670b91a9a 1187 void SDHC_HAL_SetIntState(uint32_t baseAddr, bool enable, uint32_t mask);
screamer 0:e4d670b91a9a 1188
screamer 0:e4d670b91a9a 1189 /*!
screamer 0:e4d670b91a9a 1190 * @brief Performs an SDHC reset.
screamer 0:e4d670b91a9a 1191 *
screamer 0:e4d670b91a9a 1192 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 1193 * @param type the type of reset
screamer 0:e4d670b91a9a 1194 * @param timeout timeout for reset
screamer 0:e4d670b91a9a 1195 * @return 0 on success, else on error
screamer 0:e4d670b91a9a 1196 */
screamer 0:e4d670b91a9a 1197 uint32_t SDHC_HAL_Reset(uint32_t baseAddr, uint32_t type, uint32_t timeout);
screamer 0:e4d670b91a9a 1198
screamer 0:e4d670b91a9a 1199 /*!
screamer 0:e4d670b91a9a 1200 * @brief Sends 80 clocks to the card to initialize the card.
screamer 0:e4d670b91a9a 1201 *
screamer 0:e4d670b91a9a 1202 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 1203 * @param timeout timeout for initialize card
screamer 0:e4d670b91a9a 1204 * @return 0 on success, else on error
screamer 0:e4d670b91a9a 1205 */
screamer 0:e4d670b91a9a 1206 uint32_t SDHC_HAL_InitCard(uint32_t baseAddr, uint32_t timeout);
screamer 0:e4d670b91a9a 1207
screamer 0:e4d670b91a9a 1208 /*!
screamer 0:e4d670b91a9a 1209 * @brief Gets the IRQ ID for a given host controller.
screamer 0:e4d670b91a9a 1210 *
screamer 0:e4d670b91a9a 1211 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 1212 * @return IRQ number for specific SDHC instance
screamer 0:e4d670b91a9a 1213 */
screamer 0:e4d670b91a9a 1214 IRQn_Type SDHC_HAL_GetIrqId(uint32_t baseAddr);
screamer 0:e4d670b91a9a 1215
screamer 0:e4d670b91a9a 1216 /*!
screamer 0:e4d670b91a9a 1217 * @brief Initializes the SDHC HAL.
screamer 0:e4d670b91a9a 1218 *
screamer 0:e4d670b91a9a 1219 * @param baseAddr SDHC base address
screamer 0:e4d670b91a9a 1220 */
screamer 0:e4d670b91a9a 1221 void SDHC_HAL_Init(uint32_t baseAddr);
screamer 0:e4d670b91a9a 1222
screamer 0:e4d670b91a9a 1223 /*@} */
screamer 0:e4d670b91a9a 1224 #if defined(__cplusplus)
screamer 0:e4d670b91a9a 1225 }
screamer 0:e4d670b91a9a 1226 #endif
screamer 0:e4d670b91a9a 1227 /*! @} */
screamer 0:e4d670b91a9a 1228
screamer 0:e4d670b91a9a 1229 #endif /* MBED_NO_SDHC */
screamer 0:e4d670b91a9a 1230
screamer 0:e4d670b91a9a 1231 #endif
screamer 0:e4d670b91a9a 1232
screamer 0:e4d670b91a9a 1233 /*************************************************************************************************
screamer 0:e4d670b91a9a 1234 * EOF
screamer 0:e4d670b91a9a 1235 ************************************************************************************************/
screamer 0:e4d670b91a9a 1236