Alessandro Angelino / target-freescale-ksdk

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Fork of target-freescale-ksdk by Morpheus

TARGET_KPSDK_CODE/hal/enet/fsl_enet_hal.h@1:d01108809007, 2016-04-04 (annotated)

Committer:
Alessandro Angelino
Date:
Mon Apr 04 14:18:16 2016 +0100
Revision:
1:d01108809007
Parent:
0:e4d670b91a9a 
Replace NVIC APIs with vIRQ ones

Who changed what in which revision?

UserRevisionLine numberNew contents of line
screamer 0:e4d670b91a9a 1 /*
screamer 0:e4d670b91a9a 2 * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
screamer 0:e4d670b91a9a 3 * All rights reserved.
screamer 0:e4d670b91a9a 4 *
screamer 0:e4d670b91a9a 5 * Redistribution and use in source and binary forms, with or without modification,
screamer 0:e4d670b91a9a 6 * are permitted provided that the following conditions are met:
screamer 0:e4d670b91a9a 7 *
screamer 0:e4d670b91a9a 8 * o Redistributions of source code must retain the above copyright notice, this list
screamer 0:e4d670b91a9a 9 * of conditions and the following disclaimer.
screamer 0:e4d670b91a9a 10 *
screamer 0:e4d670b91a9a 11 * o Redistributions in binary form must reproduce the above copyright notice, this
screamer 0:e4d670b91a9a 12 * list of conditions and the following disclaimer in the documentation and/or
screamer 0:e4d670b91a9a 13 * other materials provided with the distribution.
screamer 0:e4d670b91a9a 14 *
screamer 0:e4d670b91a9a 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
screamer 0:e4d670b91a9a 16 * contributors may be used to endorse or promote products derived from this
screamer 0:e4d670b91a9a 17 * software without specific prior written permission.
screamer 0:e4d670b91a9a 18 *
screamer 0:e4d670b91a9a 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
screamer 0:e4d670b91a9a 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
screamer 0:e4d670b91a9a 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
screamer 0:e4d670b91a9a 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
screamer 0:e4d670b91a9a 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
screamer 0:e4d670b91a9a 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
screamer 0:e4d670b91a9a 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
screamer 0:e4d670b91a9a 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
screamer 0:e4d670b91a9a 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
screamer 0:e4d670b91a9a 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
screamer 0:e4d670b91a9a 29 */
screamer 0:e4d670b91a9a 30
screamer 0:e4d670b91a9a 31 #ifndef __FSL_ENET_HAL_H__
screamer 0:e4d670b91a9a 32 #define __FSL_ENET_HAL_H__
screamer 0:e4d670b91a9a 33
screamer 0:e4d670b91a9a 34 #include <stdint.h>
screamer 0:e4d670b91a9a 35 #include <stdbool.h>
screamer 0:e4d670b91a9a 36 #include "fsl_device_registers.h"
screamer 0:e4d670b91a9a 37 #include "fsl_enet_features.h"
screamer 0:e4d670b91a9a 38 #include <assert.h>
screamer 0:e4d670b91a9a 39
screamer 0:e4d670b91a9a 40 #ifndef MBED_NO_ENET
screamer 0:e4d670b91a9a 41
screamer 0:e4d670b91a9a 42 /*!
screamer 0:e4d670b91a9a 43 * @addtogroup enet_hal
screamer 0:e4d670b91a9a 44 * @{
screamer 0:e4d670b91a9a 45 */
screamer 0:e4d670b91a9a 46
screamer 0:e4d670b91a9a 47 /*******************************************************************************
screamer 0:e4d670b91a9a 48 * Definitions
screamer 0:e4d670b91a9a 49 ******************************************************************************/
screamer 0:e4d670b91a9a 50 /*! @brief Defines the system endian type.*/
screamer 0:e4d670b91a9a 51 #define SYSTEM_LITTLE_ENDIAN (1)
screamer 0:e4d670b91a9a 52
screamer 0:e4d670b91a9a 53 /*! @brief Define macro to do the endianness swap*/
screamer 0:e4d670b91a9a 54 #define BSWAP_16(x) (uint16_t)((uint16_t)(((uint16_t)(x) & (uint16_t)0xFF00) >> 0x8) | (uint16_t)(((uint16_t)(x) & (uint16_t)0xFF) << 0x8))
screamer 0:e4d670b91a9a 55 #define BSWAP_32(x) (uint32_t)((((uint32_t)(x) & 0x00FFU) << 24) | (((uint32_t)(x) & 0x00FF00U) << 8) | (((uint32_t)(x) & 0xFF0000U) >> 8) | (((uint32_t)(x) & 0xFF000000U) >> 24))
screamer 0:e4d670b91a9a 56 #if SYSTEM_LITTLE_ENDIAN && FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY
screamer 0:e4d670b91a9a 57 #define HTONS(n) BSWAP_16(n)
screamer 0:e4d670b91a9a 58 #define HTONL(n) BSWAP_32(n)
screamer 0:e4d670b91a9a 59 #define NTOHS(n) BSWAP_16(n)
screamer 0:e4d670b91a9a 60 #define NTOHL(n) BSWAP_32(n)
screamer 0:e4d670b91a9a 61 #else
screamer 0:e4d670b91a9a 62 #define HTONS(n) (n)
screamer 0:e4d670b91a9a 63 #define HTONL(n) (n)
screamer 0:e4d670b91a9a 64 #define NTOHS(n) (n)
screamer 0:e4d670b91a9a 65 #define NTOHL(n) (n)
screamer 0:e4d670b91a9a 66 #endif
screamer 0:e4d670b91a9a 67
screamer 0:e4d670b91a9a 68 /*! @brief Defines the Status return codes.*/
screamer 0:e4d670b91a9a 69 typedef enum _enet_status
screamer 0:e4d670b91a9a 70 {
screamer 0:e4d670b91a9a 71 kStatus_ENET_Success = 0,
screamer 0:e4d670b91a9a 72 kStatus_ENET_InvalidInput, /*!< Invalid ENET input parameter */
screamer 0:e4d670b91a9a 73 kStatus_ENET_MemoryAllocateFail, /*!< Memory allocate failure*/
screamer 0:e4d670b91a9a 74 kStatus_ENET_GetClockFreqFail, /*!< Get clock frequency failure*/
screamer 0:e4d670b91a9a 75 kStatus_ENET_Initialized, /*!< ENET device already initialized*/
screamer 0:e4d670b91a9a 76 kStatus_ENET_Layer2QueueNull, /*!< NULL L2 PTP buffer queue pointer*/
screamer 0:e4d670b91a9a 77 kStatus_ENET_Layer2OverLarge, /*!< Layer2 packet length over large*/
screamer 0:e4d670b91a9a 78 kStatus_ENET_Layer2BufferFull, /*!< Layer2 packet buffer full*/
screamer 0:e4d670b91a9a 79 kStatus_ENET_PtpringBufferFull, /*!< PTP ring buffer full*/
screamer 0:e4d670b91a9a 80 kStatus_ENET_PtpringBufferEmpty, /*!< PTP ring buffer empty*/
screamer 0:e4d670b91a9a 81 kStatus_ENET_Miiuninitialized, /*!< MII uninitialized*/
screamer 0:e4d670b91a9a 82 kStatus_ENET_RxbdInvalid, /*!< Receive buffer descriptor invalid*/
screamer 0:e4d670b91a9a 83 kStatus_ENET_RxbdEmpty, /*!< Receive buffer descriptor empty*/
screamer 0:e4d670b91a9a 84 kStatus_ENET_RxbdTrunc, /*!< Receive buffer descriptor truncate*/
screamer 0:e4d670b91a9a 85 kStatus_ENET_RxbdError, /*!< Receive buffer descriptor error*/
screamer 0:e4d670b91a9a 86 kStatus_ENET_RxBdFull, /*!< Receive buffer descriptor full*/
screamer 0:e4d670b91a9a 87 kStatus_ENET_SmallBdSize, /*!< Small receive buffer size*/
screamer 0:e4d670b91a9a 88 kStatus_ENET_LargeBufferFull, /*!< Receive large buffer full*/
screamer 0:e4d670b91a9a 89 kStatus_ENET_TxbdFull, /*!< Transmit buffer descriptor full*/
screamer 0:e4d670b91a9a 90 kStatus_ENET_TxbdNull, /*!< Transmit buffer descriptor Null*/
screamer 0:e4d670b91a9a 91 kStatus_ENET_TxBufferNull, /*!< Transmit data buffer Null*/
screamer 0:e4d670b91a9a 92 kStatus_ENET_NoRxBufferLeft, /*!< No more receive buffer left*/
screamer 0:e4d670b91a9a 93 kStatus_ENET_UnknownCommand, /*!< Invalid ENET PTP IOCTL command*/
screamer 0:e4d670b91a9a 94 kStatus_ENET_TimeOut, /*!< ENET Timeout*/
screamer 0:e4d670b91a9a 95 kStatus_ENET_MulticastPointerNull, /*!< Null multicast group pointer*/
screamer 0:e4d670b91a9a 96 kStatus_ENET_AlreadyAddedMulticast /*!< Have Already added to multicast group*/
screamer 0:e4d670b91a9a 97 } enet_status_t;
screamer 0:e4d670b91a9a 98
screamer 0:e4d670b91a9a 99
screamer 0:e4d670b91a9a 100 #if FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY && SYSTEM_LITTLE_ENDIAN
screamer 0:e4d670b91a9a 101 /*! @brief Defines the control and status regions of the receive buffer descriptor.*/
screamer 0:e4d670b91a9a 102 typedef enum _enet_rx_bd_control_status
screamer 0:e4d670b91a9a 103 {
screamer 0:e4d670b91a9a 104 kEnetRxBdBroadCast = 0x8000, /*!< Broadcast */
screamer 0:e4d670b91a9a 105 kEnetRxBdMultiCast = 0x4000, /*!< Multicast*/
screamer 0:e4d670b91a9a 106 kEnetRxBdLengthViolation = 0x2000, /*!< Receive length violation*/
screamer 0:e4d670b91a9a 107 kEnetRxBdNoOctet = 0x1000, /*!< Receive non-octet aligned frame*/
screamer 0:e4d670b91a9a 108 kEnetRxBdCrc = 0x0400, /*!< Receive CRC error*/
screamer 0:e4d670b91a9a 109 kEnetRxBdOverRun = 0x0200, /*!< Receive FIFO overrun*/
screamer 0:e4d670b91a9a 110 kEnetRxBdTrunc = 0x0100, /*!< Frame is truncated */
screamer 0:e4d670b91a9a 111 kEnetRxBdEmpty = 0x0080, /*!< Empty bit*/
screamer 0:e4d670b91a9a 112 kEnetRxBdRxSoftOwner1 = 0x0040, /*!< Receive software owner*/
screamer 0:e4d670b91a9a 113 kEnetRxBdWrap = 0x0020, /*!< Update buffer descriptor*/
screamer 0:e4d670b91a9a 114 kEnetRxBdRxSoftOwner2 = 0x0010, /*!< Receive software owner*/
screamer 0:e4d670b91a9a 115 kEnetRxBdLast = 0x0008, /*!< Last BD in the frame*/
screamer 0:e4d670b91a9a 116 kEnetRxBdMiss = 0x0001 /*!< Receive for promiscuous mode*/
screamer 0:e4d670b91a9a 117 } enet_rx_bd_control_status_t;
screamer 0:e4d670b91a9a 118
screamer 0:e4d670b91a9a 119 /*! @brief Defines the control extended regions of the receive buffer descriptor.*/
screamer 0:e4d670b91a9a 120 typedef enum _enet_rx_bd_control_extend
screamer 0:e4d670b91a9a 121 {
screamer 0:e4d670b91a9a 122 kEnetRxBdUnicast = 0x0001, /*!< Unicast frame*/
screamer 0:e4d670b91a9a 123 kEnetRxBdCollision = 0x0002, /*!< BD collision*/
screamer 0:e4d670b91a9a 124 kEnetRxBdPhyErr = 0x0004, /*!< PHY error*/
screamer 0:e4d670b91a9a 125 kEnetRxBdMacErr = 0x0080, /*!< Mac error*/
screamer 0:e4d670b91a9a 126 kEnetRxBdIpv4 = 0x0100, /*!< Ipv4 frame*/
screamer 0:e4d670b91a9a 127 kEnetRxBdIpv6 = 0x0200, /*!< Ipv6 frame*/
screamer 0:e4d670b91a9a 128 kEnetRxBdVlan = 0x0400, /*!< VLAN*/
screamer 0:e4d670b91a9a 129 kEnetRxBdProtocolChecksumErr = 0x1000, /*!< Protocol checksum error*/
screamer 0:e4d670b91a9a 130 kEnetRxBdIpHeaderChecksumErr = 0x2000, /*!< IP header checksum error*/
screamer 0:e4d670b91a9a 131 kEnetRxBdIntrrupt = 0x8000 /*!< BD interrupt*/
screamer 0:e4d670b91a9a 132 } enet_rx_bd_control_extend_t;
screamer 0:e4d670b91a9a 133
screamer 0:e4d670b91a9a 134 /*! @brief Defines the control status region of the transmit buffer descriptor.*/
screamer 0:e4d670b91a9a 135 typedef enum _enet_tx_bd_control_status
screamer 0:e4d670b91a9a 136 {
screamer 0:e4d670b91a9a 137 kEnetTxBdReady = 0x0080, /*!< Ready bit*/
screamer 0:e4d670b91a9a 138 kEnetTxBdTxSoftOwner1 = 0x0040, /*!< Transmit software owner*/
screamer 0:e4d670b91a9a 139 kEnetTxBdWrap = 0x0020, /*!< Wrap buffer descriptor*/
screamer 0:e4d670b91a9a 140 kEnetTxBdTxSoftOwner2 = 0x0010, /*!< Transmit software owner*/
screamer 0:e4d670b91a9a 141 kEnetTxBdLast = 0x0008, /*!< Last BD in the frame*/
screamer 0:e4d670b91a9a 142 kEnetTxBdTransmitCrc = 0x0004 /*!< Receive for transmit CRC*/
screamer 0:e4d670b91a9a 143 } enet_tx_bd_control_status_t;
screamer 0:e4d670b91a9a 144
screamer 0:e4d670b91a9a 145 /*! @brief Defines the control extended region of the transmit buffer descriptor.*/
screamer 0:e4d670b91a9a 146 typedef enum _enet_tx_bd_control_extend
screamer 0:e4d670b91a9a 147 {
screamer 0:e4d670b91a9a 148 kEnetTxBdTxErr = 0x0080, /*!< Transmit error*/
screamer 0:e4d670b91a9a 149 kEnetTxBdTxUnderFlowErr = 0x0020, /*!< Underflow error*/
screamer 0:e4d670b91a9a 150 kEnetTxBdExcessCollisionErr = 0x0010, /*!< Excess collision error*/
screamer 0:e4d670b91a9a 151 kEnetTxBdTxFrameErr = 0x0008, /*!< Frame error*/
screamer 0:e4d670b91a9a 152 kEnetTxBdLatecollisionErr = 0x0004, /*!< Late collision error*/
screamer 0:e4d670b91a9a 153 kEnetTxBdOverFlowErr = 0x0002, /*!< Overflow error*/
screamer 0:e4d670b91a9a 154 kEnetTxTimestampErr = 0x0001 /*!< Timestamp error*/
screamer 0:e4d670b91a9a 155 } enet_tx_bd_control_extend_t;
screamer 0:e4d670b91a9a 156
screamer 0:e4d670b91a9a 157 /*! @brief Defines the control extended2 region of the transmit buffer descriptor.*/
screamer 0:e4d670b91a9a 158 typedef enum _enet_tx_bd_control_extend2
screamer 0:e4d670b91a9a 159 {
screamer 0:e4d670b91a9a 160 kEnetTxBdTxInterrupt = 0x0040, /*!< Transmit interrupt*/
screamer 0:e4d670b91a9a 161 kEnetTxBdTimeStamp = 0x0020 /*!< Transmit timestamp flag */
screamer 0:e4d670b91a9a 162 } enet_tx_bd_control_extend2_t;
screamer 0:e4d670b91a9a 163 #else
screamer 0:e4d670b91a9a 164 /*! @brief Defines the control and status region of the receive buffer descriptor.*/
screamer 0:e4d670b91a9a 165 typedef enum _enet_rx_bd_control_status
screamer 0:e4d670b91a9a 166 {
screamer 0:e4d670b91a9a 167 kEnetRxBdEmpty = 0x8000, /*!< Empty bit*/
screamer 0:e4d670b91a9a 168 kEnetRxBdRxSoftOwner1 = 0x4000, /*!< Receive software owner*/
screamer 0:e4d670b91a9a 169 kEnetRxBdWrap = 0x2000, /*!< Update buffer descriptor*/
screamer 0:e4d670b91a9a 170 kEnetRxBdRxSoftOwner2 = 0x1000, /*!< Receive software owner*/
screamer 0:e4d670b91a9a 171 kEnetRxBdLast = 0x0800, /*!< Last BD in the frame*/
screamer 0:e4d670b91a9a 172 kEnetRxBdMiss = 0x0100, /*!< Receive for promiscuous mode*/
screamer 0:e4d670b91a9a 173 kEnetRxBdBroadCast = 0x0080, /*!< Broadcast */
screamer 0:e4d670b91a9a 174 kEnetRxBdMultiCast = 0x0040, /*!< Multicast*/
screamer 0:e4d670b91a9a 175 kEnetRxBdLengthViolation = 0x0020, /*!< Receive length violation*/
screamer 0:e4d670b91a9a 176 kEnetRxBdNoOctet = 0x0010, /*!< Receive non-octet aligned frame*/
screamer 0:e4d670b91a9a 177 kEnetRxBdCrc = 0x0004, /*!< Receive CRC error*/
screamer 0:e4d670b91a9a 178 kEnetRxBdOverRun = 0x0002, /*!< Receive FIFO overrun*/
screamer 0:e4d670b91a9a 179 kEnetRxBdTrunc = 0x0001 /*!< Frame is truncated */
screamer 0:e4d670b91a9a 180 } enet_rx_bd_control_status_t;
screamer 0:e4d670b91a9a 181
screamer 0:e4d670b91a9a 182 /*! @brief Defines the control extended region of the receive buffer descriptor.*/
screamer 0:e4d670b91a9a 183 typedef enum _enet_rx_bd_control_extend
screamer 0:e4d670b91a9a 184 {
screamer 0:e4d670b91a9a 185 kEnetRxBdIpv4 = 0x0001, /*!< Ipv4 frame*/
screamer 0:e4d670b91a9a 186 kEnetRxBdIpv6 = 0x0002, /*!< Ipv6 frame*/
screamer 0:e4d670b91a9a 187 kEnetRxBdVlan = 0x0004, /*!< VLAN*/
screamer 0:e4d670b91a9a 188 kEnetRxBdProtocolChecksumErr = 0x0010, /*!< Protocol checksum error*/
screamer 0:e4d670b91a9a 189 kEnetRxBdIpHeaderChecksumErr = 0x0020, /*!< IP header checksum error*/
screamer 0:e4d670b91a9a 190 kEnetRxBdIntrrupt = 0x0080, /*!< BD interrupt*/
screamer 0:e4d670b91a9a 191 kEnetRxBdUnicast = 0x0100, /*!< Unicast frame*/
screamer 0:e4d670b91a9a 192 kEnetRxBdCollision = 0x0200, /*!< BD collision*/
screamer 0:e4d670b91a9a 193 kEnetRxBdPhyErr = 0x0400, /*!< PHY error*/
screamer 0:e4d670b91a9a 194 kEnetRxBdMacErr = 0x8000 /*!< Mac error */
screamer 0:e4d670b91a9a 195 } enet_rx_bd_control_extend_t;
screamer 0:e4d670b91a9a 196
screamer 0:e4d670b91a9a 197 /*! @brief Defines the control status of the transmit buffer descriptor.*/
screamer 0:e4d670b91a9a 198 typedef enum _enet_tx_bd_control_status
screamer 0:e4d670b91a9a 199 {
screamer 0:e4d670b91a9a 200 kEnetTxBdReady = 0x8000, /*!< Ready bit*/
screamer 0:e4d670b91a9a 201 kEnetTxBdTxSoftOwner1 = 0x4000, /*!< Transmit software owner*/
screamer 0:e4d670b91a9a 202 kEnetTxBdWrap = 0x2000, /*!< Wrap buffer descriptor*/
screamer 0:e4d670b91a9a 203 kEnetTxBdTxSoftOwner2 = 0x1000, /*!< Transmit software owner*/
screamer 0:e4d670b91a9a 204 kEnetTxBdLast = 0x0800, /*!< Last BD in the frame*/
screamer 0:e4d670b91a9a 205 kEnetTxBdTransmitCrc = 0x0400 /*!< Receive for transmit CRC */
screamer 0:e4d670b91a9a 206 } enet_tx_bd_control_status_t;
screamer 0:e4d670b91a9a 207
screamer 0:e4d670b91a9a 208 /*! @brief Defines the control extended of the transmit buffer descriptor.*/
screamer 0:e4d670b91a9a 209 typedef enum _enet_tx_bd_control_extend
screamer 0:e4d670b91a9a 210 {
screamer 0:e4d670b91a9a 211 kEnetTxBdTxErr = 0x8000, /*!< Transmit error*/
screamer 0:e4d670b91a9a 212 kEnetTxBdTxUnderFlowErr = 0x2000, /*!< Underflow error*/
screamer 0:e4d670b91a9a 213 kEnetTxBdExcessCollisionErr = 0x1000, /*!< Excess collision error*/
screamer 0:e4d670b91a9a 214 kEnetTxBdTxFrameErr = 0x0800, /*!< Frame error*/
screamer 0:e4d670b91a9a 215 kEnetTxBdLatecollisionErr = 0x0400, /*!< Late collision error*/
screamer 0:e4d670b91a9a 216 kEnetTxBdOverFlowErr = 0x0200, /*!< Overflow error*/
screamer 0:e4d670b91a9a 217 kEnetTxTimestampErr = 0x0100 /*!< Timestamp error*/
screamer 0:e4d670b91a9a 218 } enet_tx_bd_control_extend_t;
screamer 0:e4d670b91a9a 219
screamer 0:e4d670b91a9a 220 /*! @brief Defines the control extended2 of the transmit buffer descriptor.*/
screamer 0:e4d670b91a9a 221 typedef enum _enet_tx_bd_control_extend2
screamer 0:e4d670b91a9a 222 {
screamer 0:e4d670b91a9a 223 kEnetTxBdTxInterrupt = 0x4000, /*!< Transmit interrupt*/
screamer 0:e4d670b91a9a 224 kEnetTxBdTimeStamp = 0x2000 /*!< Transmit timestamp flag */
screamer 0:e4d670b91a9a 225 } enet_tx_bd_control_extend2_t;
screamer 0:e4d670b91a9a 226 #endif
screamer 0:e4d670b91a9a 227
screamer 0:e4d670b91a9a 228 /*! @brief Defines the macro to the different ENET constant value.*/
screamer 0:e4d670b91a9a 229 typedef enum _enet_constant_parameter
screamer 0:e4d670b91a9a 230 {
screamer 0:e4d670b91a9a 231 kEnetMacAddrLen = 6, /*!< ENET mac address length*/
screamer 0:e4d670b91a9a 232 kEnetHashValMask = 0x1f, /*!< ENET hash value mask*/
screamer 0:e4d670b91a9a 233 kEnetRxBdCtlJudge1 = 0x0080,/*!< ENET receive buffer descriptor control judge value1*/
screamer 0:e4d670b91a9a 234 kEnetRxBdCtlJudge2 = 0x8000 /*!< ENET receive buffer descriptor control judge value2*/
screamer 0:e4d670b91a9a 235 } enet_constant_parameter_t;
screamer 0:e4d670b91a9a 236
screamer 0:e4d670b91a9a 237 /*! @brief Defines the RMII or MII mode for data interface between the MAC and the PHY.*/
screamer 0:e4d670b91a9a 238 typedef enum _enet_config_rmii
screamer 0:e4d670b91a9a 239 {
screamer 0:e4d670b91a9a 240 kEnetCfgMii = 0, /*!< MII mode for data interface*/
screamer 0:e4d670b91a9a 241 kEnetCfgRmii = 1 /*!< RMII mode for data interface*/
screamer 0:e4d670b91a9a 242 } enet_config_rmii_t;
screamer 0:e4d670b91a9a 243
screamer 0:e4d670b91a9a 244 /*! @brief Defines the 10 Mbps or 100 Mbps speed mode for the data transfer.*/
screamer 0:e4d670b91a9a 245 typedef enum _enet_config_speed
screamer 0:e4d670b91a9a 246 {
screamer 0:e4d670b91a9a 247 kEnetCfgSpeed100M = 0, /*!< Speed 100 M mode*/
screamer 0:e4d670b91a9a 248 kEnetCfgSpeed10M = 1 /*!< Speed 10 M mode*/
screamer 0:e4d670b91a9a 249 } enet_config_speed_t;
screamer 0:e4d670b91a9a 250
screamer 0:e4d670b91a9a 251 /*! @brief Defines the half or full duplex mode for the data transfer.*/
screamer 0:e4d670b91a9a 252 typedef enum _enet_config_duplex
screamer 0:e4d670b91a9a 253 {
screamer 0:e4d670b91a9a 254 kEnetCfgHalfDuplex = 0, /*!< Half duplex mode*/
screamer 0:e4d670b91a9a 255 kEnetCfgFullDuplex = 1 /*!< Full duplex mode*/
screamer 0:e4d670b91a9a 256 } enet_config_duplex_t;
screamer 0:e4d670b91a9a 257
screamer 0:e4d670b91a9a 258 /*! @brief Defines the write/read operation for the MII.*/
screamer 0:e4d670b91a9a 259 typedef enum _enet_mii_operation
screamer 0:e4d670b91a9a 260 {
screamer 0:e4d670b91a9a 261 kEnetWriteNoCompliant = 0, /*!< Write frame operation, but not MII compliant.*/
screamer 0:e4d670b91a9a 262 kEnetWriteValidFrame = 1, /*!< Write frame operation for a valid MII management frame*/
screamer 0:e4d670b91a9a 263 kEnetReadValidFrame = 2, /*!< Read frame operation for a valid MII management frame.*/
screamer 0:e4d670b91a9a 264 kEnetReadNoCompliant = 3 /*!< Read frame operation, but not MII compliant*/
screamer 0:e4d670b91a9a 265 }enet_mii_operation_t;
screamer 0:e4d670b91a9a 266
screamer 0:e4d670b91a9a 267 /*! @brief Define holdon time on MDIO output*/
screamer 0:e4d670b91a9a 268 typedef enum _enet_mdio_holdon_clkcycle
screamer 0:e4d670b91a9a 269 {
screamer 0:e4d670b91a9a 270 kEnetMdioHoldOneClkCycle = 0, /*!< MDIO output hold on one clock cycle*/
screamer 0:e4d670b91a9a 271 kEnetMdioHoldTwoClkCycle = 1, /*!< MDIO output hold on two clock cycles*/
screamer 0:e4d670b91a9a 272 kEnetMdioHoldThreeClkCycle = 2, /*!< MDIO output hold on three clock cycles*/
screamer 0:e4d670b91a9a 273 kEnetMdioHoldFourClkCycle = 3, /*!< MDIO output hold on four clock cycles*/
screamer 0:e4d670b91a9a 274 kEnetMdioHoldFiveClkCycle = 4, /*!< MDIO output hold on five clock cycles*/
screamer 0:e4d670b91a9a 275 kEnetMdioHoldSixClkCycle = 5, /*!< MDIO output hold on six clock cycles*/
screamer 0:e4d670b91a9a 276 kEnetMdioHoldSevenClkCycle = 6, /*!< MDIO output hold seven two clock cycles*/
screamer 0:e4d670b91a9a 277 kEnetMdioHoldEightClkCycle = 7, /*!< MDIO output hold on eight clock cycles*/
screamer 0:e4d670b91a9a 278 }enet_mdio_holdon_clkcycle_t;
screamer 0:e4d670b91a9a 279
screamer 0:e4d670b91a9a 280 /*! @brief Defines the initialization, enables or disables the operation for a special address filter */
screamer 0:e4d670b91a9a 281 typedef enum _enet_special_address_filter
screamer 0:e4d670b91a9a 282 {
screamer 0:e4d670b91a9a 283 kEnetSpecialAddressInit= 0, /*!< Initializes the special address filter.*/
screamer 0:e4d670b91a9a 284 kEnetSpecialAddressEnable = 1, /*!< Enables the special address filter.*/
screamer 0:e4d670b91a9a 285 kEnetSpecialAddressDisable = 2 /*!< Disables the special address filter.*/
screamer 0:e4d670b91a9a 286 } enet_special_address_filter_t;
screamer 0:e4d670b91a9a 287
screamer 0:e4d670b91a9a 288 /*! @brief Defines the capture or compare mode for 1588 timer channels.*/
screamer 0:e4d670b91a9a 289 typedef enum _enet_timer_channel_mode
screamer 0:e4d670b91a9a 290 {
screamer 0:e4d670b91a9a 291 kEnetChannelDisable = 0, /*!< Disable timer channel*/
screamer 0:e4d670b91a9a 292 kEnetChannelRisingCapture = 1, /*!< Input capture on rising edge*/
screamer 0:e4d670b91a9a 293 kEnetChannelFallingCapture = 2, /*!< Input capture on falling edge*/
screamer 0:e4d670b91a9a 294 kEnetChannelBothCapture = 3, /*!< Input capture on both edges*/
screamer 0:e4d670b91a9a 295 kEnetChannelSoftCompare = 4, /*!< Output compare software only*/
screamer 0:e4d670b91a9a 296 kEnetChannelToggleCompare = 5, /*!< Toggle output on compare*/
screamer 0:e4d670b91a9a 297 kEnetChannelClearCompare = 6, /*!< Clear output on compare*/
screamer 0:e4d670b91a9a 298 kEnetChannelSetCompare = 7, /*!< Set output on compare*/
screamer 0:e4d670b91a9a 299 kEnetChannelClearCompareSetOverflow = 10, /*!< Clear output on compare, set output on overflow*/
screamer 0:e4d670b91a9a 300 kEnetChannelSetCompareClearOverflow = 11, /*!< Set output on compare, clear output on overflow*/
screamer 0:e4d670b91a9a 301 kEnetChannelPulseLowonCompare = 14, /*!< Pulse output low on compare for one 1588 clock cycle*/
screamer 0:e4d670b91a9a 302 kEnetChannelPulseHighonCompare = 15 /*!< Pulse output high on compare for one 1588 clock cycle*/
screamer 0:e4d670b91a9a 303 } enet_timer_channel_mode_t;
screamer 0:e4d670b91a9a 304
screamer 0:e4d670b91a9a 305 /*! @brief Defines the RXFRAME/RXBYTE/TXFRAME/TXBYTE/MII/TSTIMER/TSAVAIL interrupt source for ENET.*/
screamer 0:e4d670b91a9a 306 typedef enum _enet_interrupt_request
screamer 0:e4d670b91a9a 307 {
screamer 0:e4d670b91a9a 308 kEnetBabrInterrupt = 0x40000000, /*!< BABR interrupt source*/
screamer 0:e4d670b91a9a 309 kEnetBabtInterrupt = 0x20000000, /*!< BABT interrupt source*/
screamer 0:e4d670b91a9a 310 kEnetGraInterrupt = 0x10000000, /*!< GRA interrupt source*/
screamer 0:e4d670b91a9a 311 kEnetTxFrameInterrupt = 0x8000000, /*!< TXFRAME interrupt source */
screamer 0:e4d670b91a9a 312 kEnetTxByteInterrupt = 0x4000000, /*!< TXBYTE interrupt source*/
screamer 0:e4d670b91a9a 313 kEnetRxFrameInterrupt = 0x2000000, /*!< RXFRAME interrupt source */
screamer 0:e4d670b91a9a 314 kEnetRxByteInterrupt = 0x1000000, /*!< RXBYTE interrupt source */
screamer 0:e4d670b91a9a 315 kEnetMiiInterrupt = 0x0800000, /*!< MII interrupt source*/
screamer 0:e4d670b91a9a 316 kEnetEBERInterrupt = 0x0400000, /*!< EBERR interrupt source*/
screamer 0:e4d670b91a9a 317 kEnetLcInterrupt = 0x0200000, /*!< LC interrupt source*/
screamer 0:e4d670b91a9a 318 kEnetRlInterrupt = 0x0100000, /*!< RL interrupt source*/
screamer 0:e4d670b91a9a 319 kEnetUnInterrupt = 0x0080000, /*!< UN interrupt source*/
screamer 0:e4d670b91a9a 320 kEnetPlrInterrupt = 0x0040000, /*!< PLR interrupt source*/
screamer 0:e4d670b91a9a 321 kEnetWakeupInterrupt = 0x0020000, /*!< WAKEUP interrupt source*/
screamer 0:e4d670b91a9a 322 kEnetTsAvailInterrupt = 0x0010000, /*!< TS AVAIL interrupt source*/
screamer 0:e4d670b91a9a 323 kEnetTsTimerInterrupt = 0x0008000, /*!< TS WRAP interrupt source*/
screamer 0:e4d670b91a9a 324 kEnetAllInterrupt = 0x7FFFFFFF /*!< All interrupt*/
screamer 0:e4d670b91a9a 325 } enet_interrupt_request_t;
screamer 0:e4d670b91a9a 326
screamer 0:e4d670b91a9a 327 /*! @brief Defines the six-byte Mac address type.*/
screamer 0:e4d670b91a9a 328 typedef uint8_t enetMacAddr[kEnetMacAddrLen];
screamer 0:e4d670b91a9a 329
screamer 0:e4d670b91a9a 330 #if (!FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY) && SYSTEM_LITTLE_ENDIAN
screamer 0:e4d670b91a9a 331 /*! @brief Defines the buffer descriptor structure for the little-Endian system and endianness configurable IP.*/
screamer 0:e4d670b91a9a 332 typedef struct ENETBdStruct
screamer 0:e4d670b91a9a 333 {
screamer 0:e4d670b91a9a 334 uint16_t length; /*!< Buffer descriptor data length*/
screamer 0:e4d670b91a9a 335 uint16_t control; /*!< Buffer descriptor control*/
screamer 0:e4d670b91a9a 336 uint8_t *buffer; /*!< Data buffer pointer*/
screamer 0:e4d670b91a9a 337 uint16_t controlExtend0; /*!< Extend buffer descriptor control0*/
screamer 0:e4d670b91a9a 338 uint16_t controlExtend1; /*!< Extend buffer descriptor control1*/
screamer 0:e4d670b91a9a 339 uint16_t payloadCheckSum; /*!< Internal payload checksum*/
screamer 0:e4d670b91a9a 340 uint8_t headerLength; /*!< Header length*/
screamer 0:e4d670b91a9a 341 uint8_t protocalTyte; /*!< Protocol type*/
screamer 0:e4d670b91a9a 342 uint16_t reserved0;
screamer 0:e4d670b91a9a 343 uint16_t controlExtend2; /*!< Extend buffer descriptor control2*/
screamer 0:e4d670b91a9a 344 uint32_t timestamp; /*!< Timestamp */
screamer 0:e4d670b91a9a 345 uint16_t reserved1;
screamer 0:e4d670b91a9a 346 uint16_t reserved2;
screamer 0:e4d670b91a9a 347 uint16_t reserved3;
screamer 0:e4d670b91a9a 348 uint16_t reserved4;
screamer 0:e4d670b91a9a 349 } enet_bd_struct_t;
screamer 0:e4d670b91a9a 350 #define TX_DESC_UPDATED_MASK (0x8000)
screamer 0:e4d670b91a9a 351 #else
screamer 0:e4d670b91a9a 352 /*! @brief Defines the buffer descriptors structure for the Big-Endian system.*/
screamer 0:e4d670b91a9a 353 typedef struct ENETBdStruct
screamer 0:e4d670b91a9a 354 {
screamer 0:e4d670b91a9a 355 uint16_t control; /*!< Buffer descriptor control */
screamer 0:e4d670b91a9a 356 uint16_t length; /*!< Buffer descriptor data length*/
screamer 0:e4d670b91a9a 357 uint8_t *buffer; /*!< Data buffer pointer*/
screamer 0:e4d670b91a9a 358 uint16_t controlExtend1; /*!< Extend buffer descriptor control1*/
screamer 0:e4d670b91a9a 359 uint16_t controlExtend0; /*!< Extend buffer descriptor control0*/
screamer 0:e4d670b91a9a 360 uint8_t headerLength; /*!< Header length*/
screamer 0:e4d670b91a9a 361 uint8_t protocalTyte; /*!< Protocol type*/
screamer 0:e4d670b91a9a 362 uint16_t payloadCheckSum; /*!< Internal payload checksum*/
screamer 0:e4d670b91a9a 363 uint16_t controlExtend2; /*!< Extend buffer descriptor control2*/
screamer 0:e4d670b91a9a 364 uint16_t reserved0;
screamer 0:e4d670b91a9a 365 uint32_t timestamp; /*!< Timestamp pointer*/
screamer 0:e4d670b91a9a 366 uint16_t reserved1;
screamer 0:e4d670b91a9a 367 uint16_t reserved2;
screamer 0:e4d670b91a9a 368 uint16_t reserved3;
screamer 0:e4d670b91a9a 369 uint16_t reserved4;
screamer 0:e4d670b91a9a 370 } enet_bd_struct_t;
screamer 0:e4d670b91a9a 371 #define TX_DESC_UPDATED_MASK (0x0080)
screamer 0:e4d670b91a9a 372 #endif
screamer 0:e4d670b91a9a 373
screamer 0:e4d670b91a9a 374 /*! @brief Defines the configuration structure for the 1588 PTP timer.*/
screamer 0:e4d670b91a9a 375 typedef struct ENETConfigPtpTimer
screamer 0:e4d670b91a9a 376 {
screamer 0:e4d670b91a9a 377 bool isSlaveEnabled; /*!< Master or slave PTP timer*/
screamer 0:e4d670b91a9a 378 uint32_t clockIncease; /*!< Timer increase value each clock period*/
screamer 0:e4d670b91a9a 379 uint32_t period; /*!< Timer period for generate interrupt event */
screamer 0:e4d670b91a9a 380 } enet_config_ptp_timer_t;
screamer 0:e4d670b91a9a 381
screamer 0:e4d670b91a9a 382 /*! @brief Defines the transmit accelerator configuration.*/
screamer 0:e4d670b91a9a 383 typedef struct ENETConfigTxAccelerator
screamer 0:e4d670b91a9a 384 {
screamer 0:e4d670b91a9a 385 bool isIpCheckEnabled; /*!< Insert IP header checksum */
screamer 0:e4d670b91a9a 386 bool isProtocolCheckEnabled; /*!< Insert protocol checksum*/
screamer 0:e4d670b91a9a 387 bool isShift16Enabled; /*!< Tx FIFO shift-16*/
screamer 0:e4d670b91a9a 388 } enet_config_tx_accelerator_t;
screamer 0:e4d670b91a9a 389
screamer 0:e4d670b91a9a 390 /*! @brief Defines the receive accelerator configuration.*/
screamer 0:e4d670b91a9a 391 typedef struct ENETConfigRxAccelerator
screamer 0:e4d670b91a9a 392 {
screamer 0:e4d670b91a9a 393 bool isIpcheckEnabled; /*!< Discard with wrong IP header checksum */
screamer 0:e4d670b91a9a 394 bool isProtocolCheckEnabled; /*!< Discard with wrong protocol checksum*/
screamer 0:e4d670b91a9a 395 bool isMacCheckEnabled; /*!< Discard with Mac layer errors*/
screamer 0:e4d670b91a9a 396 bool isPadRemoveEnabled; /*!< Padding removal for short IP frames*/
screamer 0:e4d670b91a9a 397 bool isShift16Enabled; /*!< Rx FIFO shift-16*/
screamer 0:e4d670b91a9a 398 } enet_config_rx_accelerator_t;
screamer 0:e4d670b91a9a 399
screamer 0:e4d670b91a9a 400 /*! @brief Defines the transmit FIFO configuration.*/
screamer 0:e4d670b91a9a 401 typedef struct ENETConfigTxFifo
screamer 0:e4d670b91a9a 402 {
screamer 0:e4d670b91a9a 403 bool isStoreForwardEnabled; /*!< Transmit FIFO store and forward */
screamer 0:e4d670b91a9a 404 uint8_t txFifoWrite; /*!< Transmit FIFO write */
screamer 0:e4d670b91a9a 405 uint8_t txEmpty; /*!< Transmit FIFO section empty threshold*/
screamer 0:e4d670b91a9a 406 uint8_t txAlmostEmpty; /*!< Transmit FIFO section almost empty threshold*/
screamer 0:e4d670b91a9a 407 uint8_t txAlmostFull; /*!< Transmit FIFO section almost full threshold*/
screamer 0:e4d670b91a9a 408 } enet_config_tx_fifo_t;
screamer 0:e4d670b91a9a 409
screamer 0:e4d670b91a9a 410 /*! @brief Defines the receive FIFO configuration.*/
screamer 0:e4d670b91a9a 411 typedef struct ENETConfigRxFifo
screamer 0:e4d670b91a9a 412 {
screamer 0:e4d670b91a9a 413 uint8_t rxFull; /*!< Receive FIFO section full threshold*/
screamer 0:e4d670b91a9a 414 uint8_t rxAlmostFull; /*!< Receive FIFO section almost full threshold*/
screamer 0:e4d670b91a9a 415 uint8_t rxEmpty; /*!< Receive FIFO section empty threshold*/
screamer 0:e4d670b91a9a 416 uint8_t rxAlmostEmpty; /*!< Receive FIFO section almost empty threshold*/
screamer 0:e4d670b91a9a 417 } enet_config_rx_fifo_t;
screamer 0:e4d670b91a9a 418
screamer 0:e4d670b91a9a 419 /*******************************************************************************
screamer 0:e4d670b91a9a 420 * API
screamer 0:e4d670b91a9a 421 ******************************************************************************/
screamer 0:e4d670b91a9a 422
screamer 0:e4d670b91a9a 423 #if defined(__cplusplus)
screamer 0:e4d670b91a9a 424 extern "C" {
screamer 0:e4d670b91a9a 425 #endif
screamer 0:e4d670b91a9a 426
screamer 0:e4d670b91a9a 427 /*!
screamer 0:e4d670b91a9a 428 * @brief Resets the ENET module.
screamer 0:e4d670b91a9a 429 *
screamer 0:e4d670b91a9a 430 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 431 */
screamer 0:e4d670b91a9a 432 static inline void enet_hal_reset_ethernet(uint32_t instance)
screamer 0:e4d670b91a9a 433 {
screamer 0:e4d670b91a9a 434 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 435
screamer 0:e4d670b91a9a 436 HW_ENET_ECR_SET(instance, BM_ENET_ECR_RESET);
screamer 0:e4d670b91a9a 437 }
screamer 0:e4d670b91a9a 438
screamer 0:e4d670b91a9a 439 /*!
screamer 0:e4d670b91a9a 440 * @brief Gets the ENET status to check whether the reset has completed.
screamer 0:e4d670b91a9a 441 *
screamer 0:e4d670b91a9a 442 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 443 * @return Current status of the reset operation
screamer 0:e4d670b91a9a 444 * - true if ENET reset completed.
screamer 0:e4d670b91a9a 445 * - false if ENET reset has not completed.
screamer 0:e4d670b91a9a 446 */
screamer 0:e4d670b91a9a 447 static inline bool enet_hal_is_reset_completed(uint32_t instance)
screamer 0:e4d670b91a9a 448 {
screamer 0:e4d670b91a9a 449 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 450
screamer 0:e4d670b91a9a 451 return (BR_ENET_ECR_RESET(instance) == 0);
screamer 0:e4d670b91a9a 452 }
screamer 0:e4d670b91a9a 453
screamer 0:e4d670b91a9a 454 /*!
screamer 0:e4d670b91a9a 455 * @brief Enable or disable stop mode.
screamer 0:e4d670b91a9a 456 *
screamer 0:e4d670b91a9a 457 * Enable stop mode will control device behavior in doze mode.
screamer 0:e4d670b91a9a 458 * In doze mode, if this filed is set then all clock of the enet assemably are
screamer 0:e4d670b91a9a 459 * disabled, except the RMII/MII clock.
screamer 0:e4d670b91a9a 460 *
screamer 0:e4d670b91a9a 461 * @param instance The ENET instance number.
screamer 0:e4d670b91a9a 462 * @param isEnabled The switch to enable/disable stop mode.
screamer 0:e4d670b91a9a 463 * - true to enabale the stop mode.
screamer 0:e4d670b91a9a 464 * - false to disable the stop mode.
screamer 0:e4d670b91a9a 465 */
screamer 0:e4d670b91a9a 466 static inline void enet_hal_enable_stop(uint32_t instance, bool isEnabled)
screamer 0:e4d670b91a9a 467 {
screamer 0:e4d670b91a9a 468 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 469 BW_ENET_ECR_STOPEN(instance, isEnabled);
screamer 0:e4d670b91a9a 470 }
screamer 0:e4d670b91a9a 471 /*!
screamer 0:e4d670b91a9a 472 * @brief Enable or disable sleep mode.
screamer 0:e4d670b91a9a 473 *
screamer 0:e4d670b91a9a 474 * Enable sleep mode will disable normal operating mode. When enable the sleep
screamer 0:e4d670b91a9a 475 * mode, the magic packet detection is also enabled so that a remote agent can
screamer 0:e4d670b91a9a 476 * wakeup the node.
screamer 0:e4d670b91a9a 477 *
screamer 0:e4d670b91a9a 478 * @param instance The ENET instance number.
screamer 0:e4d670b91a9a 479 * @param isEnabled The switch to enable/disable the sleep mode.
screamer 0:e4d670b91a9a 480 * - true to enabale the sleep mode.
screamer 0:e4d670b91a9a 481 * - false to disable the sleep mode.
screamer 0:e4d670b91a9a 482 */
screamer 0:e4d670b91a9a 483 static inline void enet_hal_enable_sleep(uint32_t instance, bool isEnabled)
screamer 0:e4d670b91a9a 484 {
screamer 0:e4d670b91a9a 485 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 486 BW_ENET_ECR_SLEEP(instance, isEnabled);
screamer 0:e4d670b91a9a 487 BW_ENET_ECR_MAGICEN(instance, isEnabled);
screamer 0:e4d670b91a9a 488 }
screamer 0:e4d670b91a9a 489
screamer 0:e4d670b91a9a 490 /*!
screamer 0:e4d670b91a9a 491 * @brief Sets the Mac address.
screamer 0:e4d670b91a9a 492 *
screamer 0:e4d670b91a9a 493 * This interface sets the six-byte Mac address of the ENET interface.
screamer 0:e4d670b91a9a 494 *
screamer 0:e4d670b91a9a 495 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 496 * @param hwAddr The mac address pointer store for six bytes Mac address
screamer 0:e4d670b91a9a 497 */
screamer 0:e4d670b91a9a 498 void enet_hal_set_mac_address(uint32_t instance, enetMacAddr hwAddr);
screamer 0:e4d670b91a9a 499
screamer 0:e4d670b91a9a 500 /*!
screamer 0:e4d670b91a9a 501 * @brief Sets the hardware addressing filtering to a multicast group address.
screamer 0:e4d670b91a9a 502 *
screamer 0:e4d670b91a9a 503 * This interface is used to add the ENET device to a multicast group address.
screamer 0:e4d670b91a9a 504 * After joining the group, Mac receives all frames with the group Mac address.
screamer 0:e4d670b91a9a 505 *
screamer 0:e4d670b91a9a 506 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 507 * @param crcValue The CRC value of the special address
screamer 0:e4d670b91a9a 508 * @param mode The operation for init/enable/disable the specified hardware address
screamer 0:e4d670b91a9a 509 */
screamer 0:e4d670b91a9a 510 void enet_hal_set_group_hashtable(uint32_t instance, uint32_t crcValue, enet_special_address_filter_t mode);
screamer 0:e4d670b91a9a 511
screamer 0:e4d670b91a9a 512 /*!
screamer 0:e4d670b91a9a 513 * @brief Sets the hardware addressing filtering to an individual address.
screamer 0:e4d670b91a9a 514 *
screamer 0:e4d670b91a9a 515 * This interface is used to add an individual address to the hardware address
screamer 0:e4d670b91a9a 516 * filter. Mac receives all frames with the individual address as a destination address.
screamer 0:e4d670b91a9a 517 *
screamer 0:e4d670b91a9a 518 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 519 * @param crcValue The CRC value of the special address
screamer 0:e4d670b91a9a 520 * @param mode The operation for init/enable/disable the specified hardware address
screamer 0:e4d670b91a9a 521 */
screamer 0:e4d670b91a9a 522 void enet_hal_set_individual_hashtable(uint32_t instance, uint32_t crcValue, enet_special_address_filter_t mode);
screamer 0:e4d670b91a9a 523
screamer 0:e4d670b91a9a 524 /*!
screamer 0:e4d670b91a9a 525 * @brief Enable/disable payload length check.
screamer 0:e4d670b91a9a 526 *
screamer 0:e4d670b91a9a 527 * If the length/type is less than 0x600,When enable payload length check
screamer 0:e4d670b91a9a 528 * the core checks the fame's payload length. If the length/type is greater
screamer 0:e4d670b91a9a 529 * than or equal to 0x600. The MAC interprets the field as a type and no
screamer 0:e4d670b91a9a 530 * payload length check is performanced.
screamer 0:e4d670b91a9a 531 *
screamer 0:e4d670b91a9a 532 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 533 * @param isEnabled The switch to enable/disable payload length check
screamer 0:e4d670b91a9a 534 * - True to enabale payload length check.
screamer 0:e4d670b91a9a 535 * - False to disable payload legnth check.
screamer 0:e4d670b91a9a 536 */
screamer 0:e4d670b91a9a 537 static inline void enet_hal_enable_payloadcheck(uint32_t instance, bool isEnabled)
screamer 0:e4d670b91a9a 538 {
screamer 0:e4d670b91a9a 539 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 540 BW_ENET_RCR_NLC(instance, isEnabled);
screamer 0:e4d670b91a9a 541 }
screamer 0:e4d670b91a9a 542
screamer 0:e4d670b91a9a 543 /*!
screamer 0:e4d670b91a9a 544 * @brief Enable/disable append CRC to transmitted frames.
screamer 0:e4d670b91a9a 545 *
screamer 0:e4d670b91a9a 546 * If transmit CRC forward is enabled, the transmit buffer descriptor controls
screamer 0:e4d670b91a9a 547 * whether the frame has a CRC from the application. If transmit CRC forward is disabled,
screamer 0:e4d670b91a9a 548 * transmitter does not append any CRC to transmitted frames.
screamer 0:e4d670b91a9a 549 *
screamer 0:e4d670b91a9a 550 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 551 * @param isEnabled The switch to enable/disable transmit the receive CRC
screamer 0:e4d670b91a9a 552 * - True the transmitter control CRC through transmit buffer descriptor.
screamer 0:e4d670b91a9a 553 * - False the transmitter does not append any CRC to transmitted frames.
screamer 0:e4d670b91a9a 554 */
screamer 0:e4d670b91a9a 555 static inline void enet_hal_enable_txcrcforward(uint32_t instance, bool isEnabled)
screamer 0:e4d670b91a9a 556 {
screamer 0:e4d670b91a9a 557 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 558 BW_ENET_TCR_CRCFWD(instance, !isEnabled);
screamer 0:e4d670b91a9a 559 }
screamer 0:e4d670b91a9a 560
screamer 0:e4d670b91a9a 561 /*!
screamer 0:e4d670b91a9a 562 * @brief Enable/disable forward the CRC filed of the received frame.
screamer 0:e4d670b91a9a 563 *
screamer 0:e4d670b91a9a 564 * This is used to deceide whether the CRC field of received frame is transmitted
screamer 0:e4d670b91a9a 565 * or stripped. Enable this feature to strip CRC field from the frame.
screamer 0:e4d670b91a9a 566 * If padding remove is enabled, this feature will be ignored and
screamer 0:e4d670b91a9a 567 * the CRC field is checked and always terminated and removed.
screamer 0:e4d670b91a9a 568 *
screamer 0:e4d670b91a9a 569 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 570 * @param isEnabled The switch to enable/disable transmit the receive CRC
screamer 0:e4d670b91a9a 571 * - True to transmit the received CRC.
screamer 0:e4d670b91a9a 572 * - False to strip the received CRC.
screamer 0:e4d670b91a9a 573 */
screamer 0:e4d670b91a9a 574 static inline void enet_hal_enable_rxcrcforward(uint32_t instance, bool isEnabled)
screamer 0:e4d670b91a9a 575 {
screamer 0:e4d670b91a9a 576 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 577 BW_ENET_RCR_CRCFWD(instance, !isEnabled);
screamer 0:e4d670b91a9a 578 }
screamer 0:e4d670b91a9a 579 /*!
screamer 0:e4d670b91a9a 580 * @brief Enable/disable forward PAUSE frames.
screamer 0:e4d670b91a9a 581 *
screamer 0:e4d670b91a9a 582 * This is used to deceide whether PAUSE frames is forwarded or discarded.
screamer 0:e4d670b91a9a 583 *
screamer 0:e4d670b91a9a 584 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 585 * @param isEnabled The switch to enable/disable forward PAUSE frames
screamer 0:e4d670b91a9a 586 * - True to forward PAUSE frames.
screamer 0:e4d670b91a9a 587 * - False to terminate and discard PAUSE frames.
screamer 0:e4d670b91a9a 588 */
screamer 0:e4d670b91a9a 589 static inline void enet_hal_enable_pauseforward(uint32_t instance, bool isEnabled)
screamer 0:e4d670b91a9a 590 {
screamer 0:e4d670b91a9a 591 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 592 BW_ENET_RCR_PAUFWD(instance, isEnabled);
screamer 0:e4d670b91a9a 593 }
screamer 0:e4d670b91a9a 594
screamer 0:e4d670b91a9a 595 /*!
screamer 0:e4d670b91a9a 596 * @brief Enable/disable frame padding remove on receive.
screamer 0:e4d670b91a9a 597 *
screamer 0:e4d670b91a9a 598 * Enable frame padding remove will remove the padding from the received frames.
screamer 0:e4d670b91a9a 599 *
screamer 0:e4d670b91a9a 600 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 601 * @param isEnabled The switch to enable/disable remove padding
screamer 0:e4d670b91a9a 602 * - True to remove padding from frames.
screamer 0:e4d670b91a9a 603 * - False to disable padding remove.
screamer 0:e4d670b91a9a 604 */
screamer 0:e4d670b91a9a 605 static inline void enet_hal_enable_padremove(uint32_t instance, bool isEnabled)
screamer 0:e4d670b91a9a 606 {
screamer 0:e4d670b91a9a 607 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 608 BW_ENET_RCR_PADEN(instance, isEnabled);
screamer 0:e4d670b91a9a 609 }
screamer 0:e4d670b91a9a 610
screamer 0:e4d670b91a9a 611 /*!
screamer 0:e4d670b91a9a 612 * @brief Enable/disable flow control.
screamer 0:e4d670b91a9a 613 *
screamer 0:e4d670b91a9a 614 * If flow control is enabled, the receive detects PAUSE frames.
screamer 0:e4d670b91a9a 615 * Upon PAUSE frame detection, the transmitter stops transmitting
screamer 0:e4d670b91a9a 616 * data frames for a given duration.
screamer 0:e4d670b91a9a 617 *
screamer 0:e4d670b91a9a 618 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 619 * @param isEnabled The switch to enable/disable flow control
screamer 0:e4d670b91a9a 620 * - True to enable the flow control.
screamer 0:e4d670b91a9a 621 * - False to disable the flow control.
screamer 0:e4d670b91a9a 622 */
screamer 0:e4d670b91a9a 623 static inline void enet_hal_enable_flowcontrol(uint32_t instance, bool isEnabled)
screamer 0:e4d670b91a9a 624 {
screamer 0:e4d670b91a9a 625 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 626 BW_ENET_RCR_CFEN(instance, isEnabled);
screamer 0:e4d670b91a9a 627 BW_ENET_RCR_FCE(instance, isEnabled);
screamer 0:e4d670b91a9a 628 }
screamer 0:e4d670b91a9a 629
screamer 0:e4d670b91a9a 630 /*!
screamer 0:e4d670b91a9a 631 * @brief Enable/disable broadcast frame reject.
screamer 0:e4d670b91a9a 632 *
screamer 0:e4d670b91a9a 633 * If broadcast frame reject is enabled, frames with destination address
screamer 0:e4d670b91a9a 634 * equal to 0xffff_ffff_ffff are rejected unless the promiscuous mode is open.
screamer 0:e4d670b91a9a 635 *
screamer 0:e4d670b91a9a 636 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 637 * @param isEnabled The switch to enable/disable reject broadcast frames
screamer 0:e4d670b91a9a 638 * - True to reject broadcast frames.
screamer 0:e4d670b91a9a 639 * - False to accept broadcast frames.
screamer 0:e4d670b91a9a 640 */
screamer 0:e4d670b91a9a 641 static inline void enet_hal_enable_broadcastreject(uint32_t instance, bool isEnabled)
screamer 0:e4d670b91a9a 642 {
screamer 0:e4d670b91a9a 643 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 644 BW_ENET_RCR_BC_REJ(instance, isEnabled);
screamer 0:e4d670b91a9a 645 }
screamer 0:e4d670b91a9a 646
screamer 0:e4d670b91a9a 647 /*!
screamer 0:e4d670b91a9a 648 * @brief Sets PAUSE duration for a PAUSE frame.
screamer 0:e4d670b91a9a 649 *
screamer 0:e4d670b91a9a 650 * This function is used to set the pause duraion used in transmission
screamer 0:e4d670b91a9a 651 * of a PAUSE frame. When another node detects a PAUSE frame, that node
screamer 0:e4d670b91a9a 652 * pauses transmission for the pause duration.
screamer 0:e4d670b91a9a 653 *
screamer 0:e4d670b91a9a 654 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 655 * @param pauseDuration The PAUSE duration for the transmitted PAUSE frame
screamer 0:e4d670b91a9a 656 * the maximum pause duration is 0xFFFF.
screamer 0:e4d670b91a9a 657 */
screamer 0:e4d670b91a9a 658 static inline void enet_hal_set_pauseduration(uint32_t instance, uint32_t pauseDuration)
screamer 0:e4d670b91a9a 659 {
screamer 0:e4d670b91a9a 660 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 661 assert(pauseDuration <= BM_ENET_OPD_PAUSE_DUR);
screamer 0:e4d670b91a9a 662 BW_ENET_OPD_PAUSE_DUR(instance, pauseDuration);
screamer 0:e4d670b91a9a 663 }
screamer 0:e4d670b91a9a 664
screamer 0:e4d670b91a9a 665 /*!
screamer 0:e4d670b91a9a 666 * @brief Gets receive PAUSE frame status.
screamer 0:e4d670b91a9a 667 *
screamer 0:e4d670b91a9a 668 * This function is used to get the received PAUSE frame status.
screamer 0:e4d670b91a9a 669 *
screamer 0:e4d670b91a9a 670 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 671 * @return The status of the received flow control frames
screamer 0:e4d670b91a9a 672 * true if the flow control pause frame is received.
screamer 0:e4d670b91a9a 673 * false if there is no flow control frame received or the pause duration is complete.
screamer 0:e4d670b91a9a 674 */
screamer 0:e4d670b91a9a 675 static inline bool enet_hal_get_rxpause_status(uint32_t instance)
screamer 0:e4d670b91a9a 676 {
screamer 0:e4d670b91a9a 677 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 678 return BR_ENET_TCR_RFC_PAUSE(instance);
screamer 0:e4d670b91a9a 679 }
screamer 0:e4d670b91a9a 680 /*!
screamer 0:e4d670b91a9a 681 * @brief Enables transmit frame control PAUSE.
screamer 0:e4d670b91a9a 682 *
screamer 0:e4d670b91a9a 683 * This function enables pauses frame transmission.
screamer 0:e4d670b91a9a 684 * When this is set, with transmission of data frames stopped, the MAC
screamer 0:e4d670b91a9a 685 * transmits a MAC control PAUSE frame. NEXT, the MAC clear the
screamer 0:e4d670b91a9a 686 * and resumes transmitting data frames.
screamer 0:e4d670b91a9a 687 *
screamer 0:e4d670b91a9a 688 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 689 * @param isEnabled The switch to enable/disable PAUSE control frame transmission
screamer 0:e4d670b91a9a 690 * - True enable PAUSE control frame transmission.
screamer 0:e4d670b91a9a 691 * - Flase disable PAUSE control frame transmission.
screamer 0:e4d670b91a9a 692 */
screamer 0:e4d670b91a9a 693 static inline void enet_hal_enable_txpause(uint32_t instance, bool isEnabled)
screamer 0:e4d670b91a9a 694 {
screamer 0:e4d670b91a9a 695 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 696 BW_ENET_TCR_TFC_PAUSE(instance, isEnabled);
screamer 0:e4d670b91a9a 697 }
screamer 0:e4d670b91a9a 698
screamer 0:e4d670b91a9a 699 /*!
screamer 0:e4d670b91a9a 700 * @brief Sets transmit PAUSE frame.
screamer 0:e4d670b91a9a 701 *
screamer 0:e4d670b91a9a 702 * This function Sets ENET transmit controller with pause duration.
screamer 0:e4d670b91a9a 703 * And set the transmit control to do PAUSE frame transmission
screamer 0:e4d670b91a9a 704 * This should be called when a PAUSE frame is dynamically wanted.
screamer 0:e4d670b91a9a 705 *
screamer 0:e4d670b91a9a 706 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 707 */
screamer 0:e4d670b91a9a 708 void enet_hal_set_txpause(uint32_t instance, uint32_t pauseDuration);
screamer 0:e4d670b91a9a 709
screamer 0:e4d670b91a9a 710 /*!
screamer 0:e4d670b91a9a 711 * @brief Sets the transmit inter-packet gap.
screamer 0:e4d670b91a9a 712 *
screamer 0:e4d670b91a9a 713 * This function indicates the IPG, in bytes, between transmitted frames.
screamer 0:e4d670b91a9a 714 * Valid values range from 8 to 27. If value is less than 8, the IPG is 8.
screamer 0:e4d670b91a9a 715 * If value is greater than 27, the IPG is 27.
screamer 0:e4d670b91a9a 716 *
screamer 0:e4d670b91a9a 717 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 718 * @param ipgValue The IPG for transmitted frames
screamer 0:e4d670b91a9a 719 * The default value is 12, the maximum value set to ipg is 0x1F.
screamer 0:e4d670b91a9a 720 *
screamer 0:e4d670b91a9a 721 */
screamer 0:e4d670b91a9a 722 static inline void enet_hal_set_txipg(uint32_t instance, uint32_t ipgValue)
screamer 0:e4d670b91a9a 723 {
screamer 0:e4d670b91a9a 724 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 725 assert(ipgValue <= BM_ENET_TIPG_IPG);
screamer 0:e4d670b91a9a 726 BW_ENET_TIPG_IPG(instance, ipgValue);
screamer 0:e4d670b91a9a 727 }
screamer 0:e4d670b91a9a 728
screamer 0:e4d670b91a9a 729 /*!
screamer 0:e4d670b91a9a 730 * @brief Sets the receive frame truncation length.
screamer 0:e4d670b91a9a 731 *
screamer 0:e4d670b91a9a 732 * This function indicates the value a receive frame is truncated,
screamer 0:e4d670b91a9a 733 * if it is greater than this value. The frame truncation length must be greater
screamer 0:e4d670b91a9a 734 * than or equal to the receive maximum frame length.
screamer 0:e4d670b91a9a 735 *
screamer 0:e4d670b91a9a 736 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 737 * @param length The truncation length. The maximum value is 0x3FFF
screamer 0:e4d670b91a9a 738 * The default truncation length is 2047(0x7FF).
screamer 0:e4d670b91a9a 739 *
screamer 0:e4d670b91a9a 740 */
screamer 0:e4d670b91a9a 741 static inline void enet_hal_set_truncationlen(uint32_t instance, uint32_t length)
screamer 0:e4d670b91a9a 742 {
screamer 0:e4d670b91a9a 743 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 744 assert(length <= BM_ENET_FTRL_TRUNC_FL);
screamer 0:e4d670b91a9a 745 BW_ENET_FTRL_TRUNC_FL(instance, length);
screamer 0:e4d670b91a9a 746 }
screamer 0:e4d670b91a9a 747
screamer 0:e4d670b91a9a 748 /*!
screamer 0:e4d670b91a9a 749 * @brief Sets the maximum receive buffer size and the maximum frame size.
screamer 0:e4d670b91a9a 750 *
screamer 0:e4d670b91a9a 751 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 752 * @param maxBufferSize The maximum receive buffer size, which should not be smaller than 256
screamer 0:e4d670b91a9a 753 * It should be evenly divisible by 16 and the maximum receive size should not be larger than 0x3ff0.
screamer 0:e4d670b91a9a 754 * @param maxFrameSize The maximum receive frame size, the reset value is 1518 or 1522 if the VLAN tags are
screamer 0:e4d670b91a9a 755 * supported. The length is measured starting at DA and including the CRC.
screamer 0:e4d670b91a9a 756 */
screamer 0:e4d670b91a9a 757 static inline void enet_hal_set_rx_max_size(uint32_t instance, uint32_t maxBufferSize, uint32_t maxFrameSize)
screamer 0:e4d670b91a9a 758 {
screamer 0:e4d670b91a9a 759 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 760 /* max buffer size must larger than 256 to minimize bus usage*/
screamer 0:e4d670b91a9a 761 assert(maxBufferSize >= 256);
screamer 0:e4d670b91a9a 762 assert(maxFrameSize <= (BM_ENET_RCR_MAX_FL >> BP_ENET_RCR_MAX_FL));
screamer 0:e4d670b91a9a 763
screamer 0:e4d670b91a9a 764 BW_ENET_RCR_MAX_FL(instance, maxFrameSize);
screamer 0:e4d670b91a9a 765 HW_ENET_MRBR_WR(instance, (maxBufferSize & BM_ENET_MRBR_R_BUF_SIZE));
screamer 0:e4d670b91a9a 766 }
screamer 0:e4d670b91a9a 767
screamer 0:e4d670b91a9a 768 /*!
screamer 0:e4d670b91a9a 769 * @brief Configures the ENET transmit FIFO.
screamer 0:e4d670b91a9a 770 *
screamer 0:e4d670b91a9a 771 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 772 * @param thresholdCfg The FIFO threshold configuration
screamer 0:e4d670b91a9a 773 */
screamer 0:e4d670b91a9a 774 void enet_hal_config_tx_fifo(uint32_t instance, enet_config_tx_fifo_t *thresholdCfg);
screamer 0:e4d670b91a9a 775
screamer 0:e4d670b91a9a 776 /*!
screamer 0:e4d670b91a9a 777 * @brief Configures the ENET receive FIFO.
screamer 0:e4d670b91a9a 778 *
screamer 0:e4d670b91a9a 779 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 780 * @param thresholdCfg The FIFO threshold configuration
screamer 0:e4d670b91a9a 781 */
screamer 0:e4d670b91a9a 782 void enet_hal_config_rx_fifo(uint32_t instance, enet_config_rx_fifo_t *thresholdCfg);
screamer 0:e4d670b91a9a 783
screamer 0:e4d670b91a9a 784 /*!
screamer 0:e4d670b91a9a 785 * @brief Sets the start address for ENET receive buffer descriptors.
screamer 0:e4d670b91a9a 786 *
screamer 0:e4d670b91a9a 787 * This interface provides the beginning of the receive
screamer 0:e4d670b91a9a 788 * and receive buffer descriptor queue in the external memory. The
screamer 0:e4d670b91a9a 789 * txbdAddr is recommended to be 128-bit aligned, must be evenly divisible by 16.
screamer 0:e4d670b91a9a 790 *
screamer 0:e4d670b91a9a 791 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 792 * @param rxBdAddr The start address of receive buffer descriptors
screamer 0:e4d670b91a9a 793 */
screamer 0:e4d670b91a9a 794 static inline void enet_hal_set_rxbd_address(uint32_t instance, uint32_t rxBdAddr)
screamer 0:e4d670b91a9a 795 {
screamer 0:e4d670b91a9a 796 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 797
screamer 0:e4d670b91a9a 798 HW_ENET_RDSR_WR(instance,rxBdAddr); /* Initialize receive buffer descriptor start address*/
screamer 0:e4d670b91a9a 799 }
screamer 0:e4d670b91a9a 800 /*!
screamer 0:e4d670b91a9a 801 * @brief Sets the start address for ENET transmit buffer descriptors.
screamer 0:e4d670b91a9a 802 *
screamer 0:e4d670b91a9a 803 * This interface provides the beginning of the receive
screamer 0:e4d670b91a9a 804 * and transmit buffer descriptor queue in the external memory. The
screamer 0:e4d670b91a9a 805 * txbdAddr is recommended to be 128-bit aligned, must be evenly divisible by 16.
screamer 0:e4d670b91a9a 806 *
screamer 0:e4d670b91a9a 807 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 808 * @param txBdAddr The start address of transmit buffer descriptors
screamer 0:e4d670b91a9a 809 */
screamer 0:e4d670b91a9a 810 static inline void enet_hal_set_txbd_address(uint32_t instance, uint32_t txBdAddr)
screamer 0:e4d670b91a9a 811 {
screamer 0:e4d670b91a9a 812 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 813
screamer 0:e4d670b91a9a 814 HW_ENET_TDSR_WR(instance,txBdAddr); /* Initialize transmit buffer descriptor start address*/
screamer 0:e4d670b91a9a 815 }
screamer 0:e4d670b91a9a 816
screamer 0:e4d670b91a9a 817 /*!
screamer 0:e4d670b91a9a 818 * @brief Initializes the receive buffer descriptors.
screamer 0:e4d670b91a9a 819 *
screamer 0:e4d670b91a9a 820 * To make sure the uDMA will do the right data transfer after you activate
screamer 0:e4d670b91a9a 821 * with wrap flag and all the buffer descriptors should be initialized with an empty bit.
screamer 0:e4d670b91a9a 822 *
screamer 0:e4d670b91a9a 823 * @param rxBds The current receive buffer descriptor
screamer 0:e4d670b91a9a 824 * @param buffer The data buffer on buffer descriptor
screamer 0:e4d670b91a9a 825 * @param isLastBd The flag to indicate the last receive buffer descriptor
screamer 0:e4d670b91a9a 826 */
screamer 0:e4d670b91a9a 827 void enet_hal_init_rxbds(void *rxBds, uint8_t *buffer, bool isLastBd);
screamer 0:e4d670b91a9a 828
screamer 0:e4d670b91a9a 829 /*!
screamer 0:e4d670b91a9a 830 * @brief Initializes the transmit buffer descriptors.
screamer 0:e4d670b91a9a 831 *
screamer 0:e4d670b91a9a 832 * To make sure the uDMA will do the right data transfer after you active
screamer 0:e4d670b91a9a 833 * with wrap flag.
screamer 0:e4d670b91a9a 834 *
screamer 0:e4d670b91a9a 835 * @param txBds The current transmit buffer descriptor.
screamer 0:e4d670b91a9a 836 * @param isLastBd The last transmit buffer descriptor flag.
screamer 0:e4d670b91a9a 837 */
screamer 0:e4d670b91a9a 838 void enet_hal_init_txbds(void *txBds, bool isLastBd);
screamer 0:e4d670b91a9a 839
screamer 0:e4d670b91a9a 840 /*!
screamer 0:e4d670b91a9a 841 * @brief Updates the receive buffer descriptors.
screamer 0:e4d670b91a9a 842 *
screamer 0:e4d670b91a9a 843 * This interface mainly clears the status region and updates the received
screamer 0:e4d670b91a9a 844 * buffer descriptor to ensure that the BD is correctly used.
screamer 0:e4d670b91a9a 845 *
screamer 0:e4d670b91a9a 846 * @param rxBds The current receive buffer descriptor
screamer 0:e4d670b91a9a 847 * @param data The data buffer address
screamer 0:e4d670b91a9a 848 * @param isbufferUpdate The data buffer update flag. When you want to update
screamer 0:e4d670b91a9a 849 * the data buffer of the buffer descriptor ensure that this flag
screamer 0:e4d670b91a9a 850 * is set.
screamer 0:e4d670b91a9a 851 */
screamer 0:e4d670b91a9a 852 void enet_hal_update_rxbds(void *rxBds, uint8_t *data, bool isbufferUpdate);
screamer 0:e4d670b91a9a 853
screamer 0:e4d670b91a9a 854 /*!
screamer 0:e4d670b91a9a 855 * @brief Initializes the transmit buffer descriptors.
screamer 0:e4d670b91a9a 856 *
screamer 0:e4d670b91a9a 857 * Ensures that the uDMA transfer data correctly after the user activates
screamer 0:e4d670b91a9a 858 * with the wrap flag.
screamer 0:e4d670b91a9a 859 *
screamer 0:e4d670b91a9a 860 * @param txBds The current transmit buffer descriptor
screamer 0:e4d670b91a9a 861 * @param isLastBd The last transmit buffer descriptor flag
screamer 0:e4d670b91a9a 862 */
screamer 0:e4d670b91a9a 863 void enet_hal_init_txbds(void *txBds, bool isLastBd);
screamer 0:e4d670b91a9a 864
screamer 0:e4d670b91a9a 865 /*!
screamer 0:e4d670b91a9a 866 * @brief Updates the transmit buffer descriptors.
screamer 0:e4d670b91a9a 867 *
screamer 0:e4d670b91a9a 868 * This interface mainly clears the status region and updates the transmit
screamer 0:e4d670b91a9a 869 * buffer descriptor to ensure tat this BD is correctly used again.
screamer 0:e4d670b91a9a 870 * You should set the isTxtsCfged when the transmit timestamp feature is required.
screamer 0:e4d670b91a9a 871 *
screamer 0:e4d670b91a9a 872 * @param txBds The current transmit buffer descriptor
screamer 0:e4d670b91a9a 873 * @param buffer The data buffer on buffer descriptor
screamer 0:e4d670b91a9a 874 * @param length The data length on buffer descriptor
screamer 0:e4d670b91a9a 875 * @param isTxtsCfged The timestamp configure flag. The timestamp is
screamer 0:e4d670b91a9a 876 * added to the transmit buffer descriptor when this flag is set.
screamer 0:e4d670b91a9a 877 */
screamer 0:e4d670b91a9a 878 void enet_hal_update_txbds(void *txBds,uint8_t *buffer, uint16_t length, bool isTxtsCfged);
screamer 0:e4d670b91a9a 879
screamer 0:e4d670b91a9a 880 /*!
screamer 0:e4d670b91a9a 881 * @brief Clears the context in the transmit buffer descriptors.
screamer 0:e4d670b91a9a 882 *
screamer 0:e4d670b91a9a 883 * Clears the data, length, control, and status region of the transmit buffer descriptor.
screamer 0:e4d670b91a9a 884 *
screamer 0:e4d670b91a9a 885 * @param curBd The current buffer descriptor
screamer 0:e4d670b91a9a 886 */
screamer 0:e4d670b91a9a 887 static inline void enet_hal_clear_txbds(void *curBd)
screamer 0:e4d670b91a9a 888 {
screamer 0:e4d670b91a9a 889 assert(curBd);
screamer 0:e4d670b91a9a 890
screamer 0:e4d670b91a9a 891 volatile enet_bd_struct_t *bdPtr = (enet_bd_struct_t *)curBd;
screamer 0:e4d670b91a9a 892 bdPtr->length = 0; /* Set data length*/
screamer 0:e4d670b91a9a 893 bdPtr->buffer = (uint8_t *)(NULL);/* Set data buffer*/
screamer 0:e4d670b91a9a 894 bdPtr->control &= (kEnetTxBdWrap);/* Set control */
screamer 0:e4d670b91a9a 895 }
screamer 0:e4d670b91a9a 896
screamer 0:e4d670b91a9a 897 /*!
screamer 0:e4d670b91a9a 898 * @brief Gets the control and the status region of the receive buffer descriptors.
screamer 0:e4d670b91a9a 899 *
screamer 0:e4d670b91a9a 900 * This interface can get the whole control and status region of the
screamer 0:e4d670b91a9a 901 * receive buffer descriptor. The enet_rx_bd_control_status_t enum type
screamer 0:e4d670b91a9a 902 * definition should be used if you want to get each status bit of
screamer 0:e4d670b91a9a 903 * the control and status region.
screamer 0:e4d670b91a9a 904 *
screamer 0:e4d670b91a9a 905 * @param curBd The current receive buffer descriptor
screamer 0:e4d670b91a9a 906 * @return The control and status data on buffer descriptors
screamer 0:e4d670b91a9a 907 */
screamer 0:e4d670b91a9a 908 uint16_t enet_hal_get_rxbd_control(void *curBd);
screamer 0:e4d670b91a9a 909
screamer 0:e4d670b91a9a 910 /*!
screamer 0:e4d670b91a9a 911 * @brief Gets the control and the status region of the transmit buffer descriptors.
screamer 0:e4d670b91a9a 912 *
screamer 0:e4d670b91a9a 913 * This interface can get the whole control and status region of the
screamer 0:e4d670b91a9a 914 * transmit buffer descriptor. The enet_tx_bd_control_status_t enum type
screamer 0:e4d670b91a9a 915 * definition should be used if you want to get each status bit of
screamer 0:e4d670b91a9a 916 * the control and status region.
screamer 0:e4d670b91a9a 917 *
screamer 0:e4d670b91a9a 918 * @param curBd The current transmit buffer descriptor
screamer 0:e4d670b91a9a 919 * @return The extended control region of transmit buffer descriptor
screamer 0:e4d670b91a9a 920 */
screamer 0:e4d670b91a9a 921 uint16_t enet_hal_get_txbd_control(void *curBd);
screamer 0:e4d670b91a9a 922
screamer 0:e4d670b91a9a 923 /*!
screamer 0:e4d670b91a9a 924 * @brief Gets the extended control region of the receive buffer descriptors.
screamer 0:e4d670b91a9a 925 *
screamer 0:e4d670b91a9a 926 * This interface can get the whole control and status region of the
screamer 0:e4d670b91a9a 927 * receive buffer descriptor. The enet_rx_bd_control_extend_t enum type
screamer 0:e4d670b91a9a 928 * definition should be used if you want to get each status bit of
screamer 0:e4d670b91a9a 929 * the control and status region.
screamer 0:e4d670b91a9a 930 *
screamer 0:e4d670b91a9a 931 * @param curBd The current receive buffer descriptor
screamer 0:e4d670b91a9a 932 * @param controlRegion The different control region
screamer 0:e4d670b91a9a 933 * @return The extended control region data of receive buffer descriptor
screamer 0:e4d670b91a9a 934 * - true when the control region is set
screamer 0:e4d670b91a9a 935 * - false when the control region is not set
screamer 0:e4d670b91a9a 936 */
screamer 0:e4d670b91a9a 937 bool enet_hal_get_rxbd_control_extend(void *curBd,enet_rx_bd_control_extend_t controlRegion);
screamer 0:e4d670b91a9a 938 /*!
screamer 0:e4d670b91a9a 939 * @brief Gets the extended control region of the transmit buffer descriptors.
screamer 0:e4d670b91a9a 940 *
screamer 0:e4d670b91a9a 941 * This interface can get the whole control and status region of the
screamer 0:e4d670b91a9a 942 * transmit buffer descriptor. The enet_tx_bd_control_extend_t enum type
screamer 0:e4d670b91a9a 943 * definition should be used if you want to get each status bit of
screamer 0:e4d670b91a9a 944 * the control and status region.
screamer 0:e4d670b91a9a 945 *
screamer 0:e4d670b91a9a 946 * @param curBd The current transmit buffer descriptor
screamer 0:e4d670b91a9a 947 * @return The extended control data
screamer 0:e4d670b91a9a 948 */
screamer 0:e4d670b91a9a 949 uint16_t enet_hal_get_txbd_control_extend(void *curBd);
screamer 0:e4d670b91a9a 950
screamer 0:e4d670b91a9a 951 /*!
screamer 0:e4d670b91a9a 952 * @brief Gets the data length of the buffer descriptors.
screamer 0:e4d670b91a9a 953 *
screamer 0:e4d670b91a9a 954 * @param curBd The current buffer descriptor
screamer 0:e4d670b91a9a 955 * @return The data length of the buffer descriptor
screamer 0:e4d670b91a9a 956 */
screamer 0:e4d670b91a9a 957 uint16_t enet_hal_get_bd_length(void *curBd);
screamer 0:e4d670b91a9a 958
screamer 0:e4d670b91a9a 959 /*!
screamer 0:e4d670b91a9a 960 * @brief Gets the buffer address of the buffer descriptors.
screamer 0:e4d670b91a9a 961 *
screamer 0:e4d670b91a9a 962 * @param curBd The current buffer descriptor
screamer 0:e4d670b91a9a 963 * @return The buffer address of the buffer descriptor
screamer 0:e4d670b91a9a 964 */
screamer 0:e4d670b91a9a 965 uint8_t* enet_hal_get_bd_buffer(void *curBd);
screamer 0:e4d670b91a9a 966
screamer 0:e4d670b91a9a 967 /*!
screamer 0:e4d670b91a9a 968 * @brief Gets the timestamp of the buffer descriptors.
screamer 0:e4d670b91a9a 969 *
screamer 0:e4d670b91a9a 970 * @param curBd The current buffer descriptor
screamer 0:e4d670b91a9a 971 * @return The time stamp of the frame in the buffer descriptor.
screamer 0:e4d670b91a9a 972 * Notice that the frame timestamp is only set in the last
screamer 0:e4d670b91a9a 973 * buffer descriptor of the frame.
screamer 0:e4d670b91a9a 974 */
screamer 0:e4d670b91a9a 975 uint32_t enet_hal_get_bd_timestamp(void *curBd);
screamer 0:e4d670b91a9a 976
screamer 0:e4d670b91a9a 977 /*!
screamer 0:e4d670b91a9a 978 * @brief Activates the receive buffer descriptor.
screamer 0:e4d670b91a9a 979 *
screamer 0:e4d670b91a9a 980 * The buffer descriptor activation
screamer 0:e4d670b91a9a 981 * should be done after the ENET module is enabled. Otherwise, the activation fails.
screamer 0:e4d670b91a9a 982 *
screamer 0:e4d670b91a9a 983 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 984 */
screamer 0:e4d670b91a9a 985 static inline void enet_hal_active_rxbd(uint32_t instance)
screamer 0:e4d670b91a9a 986 {
screamer 0:e4d670b91a9a 987 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 988
screamer 0:e4d670b91a9a 989 HW_ENET_RDAR_SET(instance, BM_ENET_RDAR_RDAR);
screamer 0:e4d670b91a9a 990 }
screamer 0:e4d670b91a9a 991
screamer 0:e4d670b91a9a 992 /*!
screamer 0:e4d670b91a9a 993 * @brief Activates the transmit buffer descriptor.
screamer 0:e4d670b91a9a 994 *
screamer 0:e4d670b91a9a 995 * The buffer descriptor activation should be done after the ENET module is
screamer 0:e4d670b91a9a 996 * enabled. Otherwise, the activation fails.
screamer 0:e4d670b91a9a 997 *
screamer 0:e4d670b91a9a 998 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 999 */
screamer 0:e4d670b91a9a 1000 static inline void enet_hal_active_txbd(uint32_t instance)
screamer 0:e4d670b91a9a 1001 {
screamer 0:e4d670b91a9a 1002 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 1003
screamer 0:e4d670b91a9a 1004 HW_ENET_TDAR_SET(instance, BM_ENET_TDAR_TDAR);
screamer 0:e4d670b91a9a 1005 }
screamer 0:e4d670b91a9a 1006
screamer 0:e4d670b91a9a 1007 /*!
screamer 0:e4d670b91a9a 1008 * @brief Configures the (R)MII of ENET.
screamer 0:e4d670b91a9a 1009 *
screamer 0:e4d670b91a9a 1010 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 1011 * @param mode The RMII or MII mode
screamer 0:e4d670b91a9a 1012 * @param speed The speed of RMII
screamer 0:e4d670b91a9a 1013 * @param duplex The full or half duplex mode
screamer 0:e4d670b91a9a 1014 * @param isRxOnTxDisabled The Receive on transmit disable flag
screamer 0:e4d670b91a9a 1015 * @param isLoopEnabled The loop enable flag
screamer 0:e4d670b91a9a 1016 */
screamer 0:e4d670b91a9a 1017 void enet_hal_config_rmii(uint32_t instance, enet_config_rmii_t mode, enet_config_speed_t speed, enet_config_duplex_t duplex, bool isRxOnTxDisabled, bool isLoopEnabled);
screamer 0:e4d670b91a9a 1018
screamer 0:e4d670b91a9a 1019 /*!
screamer 0:e4d670b91a9a 1020 * @brief Configures the MII of ENET.
screamer 0:e4d670b91a9a 1021 *
screamer 0:e4d670b91a9a 1022 * Sets the MII interface between Mac and PHY. The miiSpeed is
screamer 0:e4d670b91a9a 1023 * a value that controls the frequency of the MDC, relative to the internal module clock(InterClockSrc).
screamer 0:e4d670b91a9a 1024 * A value of zero in this parameter turns the MDC off and leaves it in the low voltage state.
screamer 0:e4d670b91a9a 1025 * Any non-zero value results in the MDC frequency MDC = InterClockSrc/((miiSpeed + 1)*2).
screamer 0:e4d670b91a9a 1026 * So miiSpeed = InterClockSrc/(2*MDC) - 1.
screamer 0:e4d670b91a9a 1027 * The Maximum MDC clock is 2.5MHZ(maximum). We should round up and plus one to simlplify:
screamer 0:e4d670b91a9a 1028 * miiSpeed = InterClockSrc/(2*2.5MHZ).
screamer 0:e4d670b91a9a 1029 *
screamer 0:e4d670b91a9a 1030 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 1031 * @param miiSpeed The MII speed and it is ranged from 0~0x3F
screamer 0:e4d670b91a9a 1032 * @param time The holdon clock cycles for MDIO output
screamer 0:e4d670b91a9a 1033 * @param isPreambleDisabled The preamble disabled flag
screamer 0:e4d670b91a9a 1034 */
screamer 0:e4d670b91a9a 1035 static inline void enet_hal_config_mii(uint32_t instance, uint32_t miiSpeed,
screamer 0:e4d670b91a9a 1036 enet_mdio_holdon_clkcycle_t clkCycle, bool isPreambleDisabled)
screamer 0:e4d670b91a9a 1037 {
screamer 0:e4d670b91a9a 1038 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 1039
screamer 0:e4d670b91a9a 1040 BW_ENET_MSCR_MII_SPEED(instance, miiSpeed); /* MII speed set*/
screamer 0:e4d670b91a9a 1041 BW_ENET_MSCR_DIS_PRE(instance, isPreambleDisabled); /* Preamble is disabled*/
screamer 0:e4d670b91a9a 1042 BW_ENET_MSCR_HOLDTIME(instance, clkCycle); /* hold on clock cycles for MDIO output*/
screamer 0:e4d670b91a9a 1043
screamer 0:e4d670b91a9a 1044 }
screamer 0:e4d670b91a9a 1045
screamer 0:e4d670b91a9a 1046 /*!
screamer 0:e4d670b91a9a 1047 * @brief Gets the MII configuration status.
screamer 0:e4d670b91a9a 1048 *
screamer 0:e4d670b91a9a 1049 * This interface is usually called to check the MII interface before
screamer 0:e4d670b91a9a 1050 * the Mac writes or reads the PHY registers.
screamer 0:e4d670b91a9a 1051 *
screamer 0:e4d670b91a9a 1052 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 1053 * @return The MII configuration status
screamer 0:e4d670b91a9a 1054 * - true if the MII has been configured.
screamer 0:e4d670b91a9a 1055 * - false if the MII has not been configured.
screamer 0:e4d670b91a9a 1056 */
screamer 0:e4d670b91a9a 1057 static inline bool enet_hal_is_mii_enabled(uint32_t instance)
screamer 0:e4d670b91a9a 1058 {
screamer 0:e4d670b91a9a 1059 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 1060
screamer 0:e4d670b91a9a 1061 return (HW_ENET_MSCR_RD(instance) & 0x7E)!= 0;
screamer 0:e4d670b91a9a 1062 }
screamer 0:e4d670b91a9a 1063
screamer 0:e4d670b91a9a 1064 /*!
screamer 0:e4d670b91a9a 1065 * @brief Reads data from PHY.
screamer 0:e4d670b91a9a 1066 *
screamer 0:e4d670b91a9a 1067 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 1068 * @return The data read from PHY
screamer 0:e4d670b91a9a 1069 */
screamer 0:e4d670b91a9a 1070 static inline uint32_t enet_hal_get_mii_data(uint32_t instance)
screamer 0:e4d670b91a9a 1071 {
screamer 0:e4d670b91a9a 1072 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 1073
screamer 0:e4d670b91a9a 1074 return (uint32_t)BR_ENET_MMFR_DATA(instance);
screamer 0:e4d670b91a9a 1075 }
screamer 0:e4d670b91a9a 1076
screamer 0:e4d670b91a9a 1077 /*!
screamer 0:e4d670b91a9a 1078 * @brief Sets the MII command.
screamer 0:e4d670b91a9a 1079 *
screamer 0:e4d670b91a9a 1080 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 1081 * @param phyAddr The PHY address
screamer 0:e4d670b91a9a 1082 * @param phyReg The PHY register
screamer 0:e4d670b91a9a 1083 * @param operation The read or write operation
screamer 0:e4d670b91a9a 1084 * @param data The data written to PHY
screamer 0:e4d670b91a9a 1085 */
screamer 0:e4d670b91a9a 1086 void enet_hal_set_mii_command(uint32_t instance, uint32_t phyAddr, uint32_t phyReg, enet_mii_operation_t operation, uint32_t data);
screamer 0:e4d670b91a9a 1087
screamer 0:e4d670b91a9a 1088 /*!
screamer 0:e4d670b91a9a 1089 * @brief Enables/Disables the ENET module.
screamer 0:e4d670b91a9a 1090 *
screamer 0:e4d670b91a9a 1091 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 1092 * @param isEnhanced The enhanced 1588 feature switch
screamer 0:e4d670b91a9a 1093 * @param isEnabled The ENET module enable switch
screamer 0:e4d670b91a9a 1094 */
screamer 0:e4d670b91a9a 1095 void enet_hal_config_ethernet(uint32_t instance, bool isEnhanced, bool isEnabled);
screamer 0:e4d670b91a9a 1096
screamer 0:e4d670b91a9a 1097 /*!
screamer 0:e4d670b91a9a 1098 * @brief Enables/Disables the ENET interrupt.
screamer 0:e4d670b91a9a 1099 *
screamer 0:e4d670b91a9a 1100 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 1101 * @param source The interrupt sources. enet_interrupt_request_t enum types
screamer 0:e4d670b91a9a 1102 * is recommended as the interrupt source.
screamer 0:e4d670b91a9a 1103 * @param isEnabled The interrupt enable switch
screamer 0:e4d670b91a9a 1104 */
screamer 0:e4d670b91a9a 1105 void enet_hal_config_interrupt(uint32_t instance, uint32_t source, bool isEnabled);
screamer 0:e4d670b91a9a 1106
screamer 0:e4d670b91a9a 1107 /*!
screamer 0:e4d670b91a9a 1108 * @brief Clears ENET interrupt events.
screamer 0:e4d670b91a9a 1109 *
screamer 0:e4d670b91a9a 1110 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 1111 * @param source The interrupt source to be cleared. enet_interrupt_request_t
screamer 0:e4d670b91a9a 1112 * enum types is recommended as the interrupt source.
screamer 0:e4d670b91a9a 1113 */
screamer 0:e4d670b91a9a 1114 static inline void enet_hal_clear_interrupt(uint32_t instance, uint32_t source)
screamer 0:e4d670b91a9a 1115 {
screamer 0:e4d670b91a9a 1116 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 1117
screamer 0:e4d670b91a9a 1118 HW_ENET_EIR_WR(instance,source);
screamer 0:e4d670b91a9a 1119 }
screamer 0:e4d670b91a9a 1120
screamer 0:e4d670b91a9a 1121 /*!
screamer 0:e4d670b91a9a 1122 * @brief Gets the ENET interrupt status.
screamer 0:e4d670b91a9a 1123 *
screamer 0:e4d670b91a9a 1124 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 1125 * @param source The interrupt sources. enet_interrupt_request_t
screamer 0:e4d670b91a9a 1126 * enum types is recommended as the interrupt source.
screamer 0:e4d670b91a9a 1127 * @return The event status of the interrupt source
screamer 0:e4d670b91a9a 1128 * - true if the interrupt event happened.
screamer 0:e4d670b91a9a 1129 * - false if the interrupt event has not happened.
screamer 0:e4d670b91a9a 1130 */
screamer 0:e4d670b91a9a 1131 static inline bool enet_hal_get_interrupt_status(uint32_t instance, uint32_t source)
screamer 0:e4d670b91a9a 1132 {
screamer 0:e4d670b91a9a 1133 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 1134
screamer 0:e4d670b91a9a 1135 return ((HW_ENET_EIR_RD(instance) & source) != 0);
screamer 0:e4d670b91a9a 1136 }
screamer 0:e4d670b91a9a 1137
screamer 0:e4d670b91a9a 1138 /*
screamer 0:e4d670b91a9a 1139 * @brief Enables/disables the ENET promiscuous mode.
screamer 0:e4d670b91a9a 1140 *
screamer 0:e4d670b91a9a 1141 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 1142 * @param isEnabled The enable switch
screamer 0:e4d670b91a9a 1143 */
screamer 0:e4d670b91a9a 1144 static inline void enet_hal_config_promiscuous(uint32_t instance, bool isEnabled)
screamer 0:e4d670b91a9a 1145 {
screamer 0:e4d670b91a9a 1146 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 1147
screamer 0:e4d670b91a9a 1148 BW_ENET_RCR_PROM(instance,isEnabled);
screamer 0:e4d670b91a9a 1149 }
screamer 0:e4d670b91a9a 1150
screamer 0:e4d670b91a9a 1151 /*!
screamer 0:e4d670b91a9a 1152 * @brief Enables/disables the clear MIB counter.
screamer 0:e4d670b91a9a 1153 *
screamer 0:e4d670b91a9a 1154 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 1155 * @param isEnabled The enable switch
screamer 0:e4d670b91a9a 1156 */
screamer 0:e4d670b91a9a 1157 static inline void enet_hal_clear_mib(uint32_t instance, bool isEnabled)
screamer 0:e4d670b91a9a 1158 {
screamer 0:e4d670b91a9a 1159 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 1160
screamer 0:e4d670b91a9a 1161 BW_ENET_MIBC_MIB_CLEAR(instance, isEnabled);
screamer 0:e4d670b91a9a 1162
screamer 0:e4d670b91a9a 1163 }
screamer 0:e4d670b91a9a 1164
screamer 0:e4d670b91a9a 1165 /*!
screamer 0:e4d670b91a9a 1166 * @brief Sets the enable/disable of the MIB block.
screamer 0:e4d670b91a9a 1167 *
screamer 0:e4d670b91a9a 1168 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 1169 * @param isEnabled The enable flag
screamer 0:e4d670b91a9a 1170 * - True to enabale MIB block.
screamer 0:e4d670b91a9a 1171 * - False to disable MIB block.
screamer 0:e4d670b91a9a 1172 */
screamer 0:e4d670b91a9a 1173 static inline void enet_hal_enable_mib(uint32_t instance, bool isEnabled)
screamer 0:e4d670b91a9a 1174 {
screamer 0:e4d670b91a9a 1175 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 1176
screamer 0:e4d670b91a9a 1177 BW_ENET_MIBC_MIB_DIS(instance,!isEnabled);
screamer 0:e4d670b91a9a 1178
screamer 0:e4d670b91a9a 1179 }
screamer 0:e4d670b91a9a 1180
screamer 0:e4d670b91a9a 1181 /*!
screamer 0:e4d670b91a9a 1182 * @brief Gets the MIB idle status.
screamer 0:e4d670b91a9a 1183 *
screamer 0:e4d670b91a9a 1184 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 1185 * @return true if in MIB idle and MIB is not updating else false.
screamer 0:e4d670b91a9a 1186 */
screamer 0:e4d670b91a9a 1187 static inline bool enet_hal_get_mib_status(uint32_t instance)
screamer 0:e4d670b91a9a 1188 {
screamer 0:e4d670b91a9a 1189 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 1190
screamer 0:e4d670b91a9a 1191 return BR_ENET_MIBC_MIB_IDLE(instance);
screamer 0:e4d670b91a9a 1192 }
screamer 0:e4d670b91a9a 1193
screamer 0:e4d670b91a9a 1194 /*!
screamer 0:e4d670b91a9a 1195 * @brief Sets the transmit accelerator.
screamer 0:e4d670b91a9a 1196 *
screamer 0:e4d670b91a9a 1197 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 1198 * @param txCfgPtr The transmit accelerator configuration
screamer 0:e4d670b91a9a 1199 */
screamer 0:e4d670b91a9a 1200 void enet_hal_config_tx_accelerator(uint32_t instance, enet_config_tx_accelerator_t *txCfgPtr);
screamer 0:e4d670b91a9a 1201
screamer 0:e4d670b91a9a 1202 /*!
screamer 0:e4d670b91a9a 1203 * @brief Sets the receive accelerator.
screamer 0:e4d670b91a9a 1204 *
screamer 0:e4d670b91a9a 1205 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 1206 * @param rxCfgPtr The receive accelerator configuration
screamer 0:e4d670b91a9a 1207 */
screamer 0:e4d670b91a9a 1208 void enet_hal_config_rx_accelerator(uint32_t instance, enet_config_rx_accelerator_t *rxCfgPtr);
screamer 0:e4d670b91a9a 1209
screamer 0:e4d670b91a9a 1210 /*!
screamer 0:e4d670b91a9a 1211 * @brief Initializes the 1588 timer.
screamer 0:e4d670b91a9a 1212 *
screamer 0:e4d670b91a9a 1213 * This interface initializes the 1588 context structure.
screamer 0:e4d670b91a9a 1214 * Initialize 1588 parameters according to the user configuration structure.
screamer 0:e4d670b91a9a 1215 *
screamer 0:e4d670b91a9a 1216 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 1217 * @param ptpCfg The 1588 timer configuration
screamer 0:e4d670b91a9a 1218 */
screamer 0:e4d670b91a9a 1219 void enet_hal_init_ptp_timer(uint32_t instance, enet_config_ptp_timer_t *ptpCfgPtr);
screamer 0:e4d670b91a9a 1220
screamer 0:e4d670b91a9a 1221 /*!
screamer 0:e4d670b91a9a 1222 * @brief Enables or disables the 1588 timer.
screamer 0:e4d670b91a9a 1223 *
screamer 0:e4d670b91a9a 1224 * Enable the PTP timer will starts the timer. Disable the timer will stop timer
screamer 0:e4d670b91a9a 1225 * at the current value.
screamer 0:e4d670b91a9a 1226 *
screamer 0:e4d670b91a9a 1227 * @param instance The ENET instance number.
screamer 0:e4d670b91a9a 1228 * @param isEnabled The 1588 timer Enable switch
screamer 0:e4d670b91a9a 1229 * - True enbaled the 1588 PTP timer.
screamer 0:e4d670b91a9a 1230 * - False disable or stop the 1588 PTP timer.
screamer 0:e4d670b91a9a 1231 */
screamer 0:e4d670b91a9a 1232 static inline void enet_hal_enable_ptp_timer(uint32_t instance, uint32_t isEnabled)
screamer 0:e4d670b91a9a 1233 {
screamer 0:e4d670b91a9a 1234 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 1235
screamer 0:e4d670b91a9a 1236 BW_ENET_ATCR_EN(instance,isEnabled);
screamer 0:e4d670b91a9a 1237 }
screamer 0:e4d670b91a9a 1238
screamer 0:e4d670b91a9a 1239 /*!
screamer 0:e4d670b91a9a 1240 * @brief Restarts the 1588 timer.
screamer 0:e4d670b91a9a 1241 *
screamer 0:e4d670b91a9a 1242 * Restarting the PTP timer clears all PTP-timer counters to zero.
screamer 0:e4d670b91a9a 1243 *
screamer 0:e4d670b91a9a 1244 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 1245 */
screamer 0:e4d670b91a9a 1246 static inline void enet_hal_restart_ptp_timer(uint32_t instance)
screamer 0:e4d670b91a9a 1247 {
screamer 0:e4d670b91a9a 1248 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 1249
screamer 0:e4d670b91a9a 1250 BW_ENET_ATCR_RESTART(instance,1);
screamer 0:e4d670b91a9a 1251 }
screamer 0:e4d670b91a9a 1252
screamer 0:e4d670b91a9a 1253 /*!
screamer 0:e4d670b91a9a 1254 * @brief Adjusts the 1588 timer.
screamer 0:e4d670b91a9a 1255 *
screamer 0:e4d670b91a9a 1256 * Adjust the 1588 timer according to the increase and correction period of the configured correction.
screamer 0:e4d670b91a9a 1257 *
screamer 0:e4d670b91a9a 1258 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 1259 * @param inceaseCorrection The increase correction for 1588 timer
screamer 0:e4d670b91a9a 1260 * @param periodCorrection The period correction for 1588 timer
screamer 0:e4d670b91a9a 1261 */
screamer 0:e4d670b91a9a 1262 static inline void enet_hal_adjust_ptp_timer(uint32_t instance, uint32_t increaseCorrection, uint32_t periodCorrection)
screamer 0:e4d670b91a9a 1263 {
screamer 0:e4d670b91a9a 1264 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 1265
screamer 0:e4d670b91a9a 1266 HW_ENET_ATINC_SET(instance,((increaseCorrection << ENET_ATINC_INC_CORR_SHIFT) & ENET_ATINC_INC_CORR_MASK)); /* set correction for ptp timer increase*/
screamer 0:e4d670b91a9a 1267 /* set correction for ptp timer period*/
screamer 0:e4d670b91a9a 1268 HW_ENET_ATCOR_SET(instance, (BM_ENET_ATCOR_COR & periodCorrection));
screamer 0:e4d670b91a9a 1269 }
screamer 0:e4d670b91a9a 1270
screamer 0:e4d670b91a9a 1271 /*!
screamer 0:e4d670b91a9a 1272 * @brief Initializes the 1588 timer channel.
screamer 0:e4d670b91a9a 1273 *
screamer 0:e4d670b91a9a 1274 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 1275 * @Param channel The 1588 timer channel number
screamer 0:e4d670b91a9a 1276 * @param mode Compare or capture mode for the 1588 timer channel
screamer 0:e4d670b91a9a 1277 */
screamer 0:e4d670b91a9a 1278 static inline void enet_hal_init_timer_channel(uint32_t instance, uint32_t channel, enet_timer_channel_mode_t mode)
screamer 0:e4d670b91a9a 1279 {
screamer 0:e4d670b91a9a 1280 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 1281 assert(channel < HW_ENET_TCSRn_COUNT);
screamer 0:e4d670b91a9a 1282 HW_ENET_TCSRn_SET(instance, channel,
screamer 0:e4d670b91a9a 1283 (BM_ENET_TCSRn_TMODE &(mode << BP_ENET_TCSRn_TMODE)));
screamer 0:e4d670b91a9a 1284 HW_ENET_TCSRn_SET(instance, channel, BM_ENET_TCSRn_TIE);
screamer 0:e4d670b91a9a 1285 }
screamer 0:e4d670b91a9a 1286
screamer 0:e4d670b91a9a 1287 /*!
screamer 0:e4d670b91a9a 1288 * @brief Sets the compare value for the 1588 timer channel.
screamer 0:e4d670b91a9a 1289 *
screamer 0:e4d670b91a9a 1290 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 1291 * @Param channel The 1588 timer channel number
screamer 0:e4d670b91a9a 1292 * @param compareValue Compare value for 1588 timer channel
screamer 0:e4d670b91a9a 1293 */
screamer 0:e4d670b91a9a 1294 static inline void enet_hal_set_timer_channel_compare(uint32_t instance, uint32_t channel, uint32_t compareValue)
screamer 0:e4d670b91a9a 1295 {
screamer 0:e4d670b91a9a 1296 assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 1297 assert(channel < HW_ENET_TCSRn_COUNT);
screamer 0:e4d670b91a9a 1298 HW_ENET_TCCRn_WR(instance,channel, compareValue);
screamer 0:e4d670b91a9a 1299 }
screamer 0:e4d670b91a9a 1300
screamer 0:e4d670b91a9a 1301 /*!
screamer 0:e4d670b91a9a 1302 * @brief Gets the 1588 timer channel status.
screamer 0:e4d670b91a9a 1303 *
screamer 0:e4d670b91a9a 1304 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 1305 * @param channel The 1588 timer channel number
screamer 0:e4d670b91a9a 1306 * @return Compare or capture operation status
screamer 0:e4d670b91a9a 1307 * - True if the compare or capture has occurred.
screamer 0:e4d670b91a9a 1308 * - False if the compare or capture has not occurred.
screamer 0:e4d670b91a9a 1309 */
screamer 0:e4d670b91a9a 1310 static inline bool enet_hal_get_timer_channel_status(uint32_t instance, uint32_t channel)
screamer 0:e4d670b91a9a 1311 {
screamer 0:e4d670b91a9a 1312 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 1313 assert(channel < HW_ENET_TCSRn_COUNT);
screamer 0:e4d670b91a9a 1314
screamer 0:e4d670b91a9a 1315 return BR_ENET_TCSRn_TF(instance,channel);
screamer 0:e4d670b91a9a 1316 }
screamer 0:e4d670b91a9a 1317
screamer 0:e4d670b91a9a 1318 /*!
screamer 0:e4d670b91a9a 1319 * @brief Clears the 1588 timer channel flag.
screamer 0:e4d670b91a9a 1320 *
screamer 0:e4d670b91a9a 1321 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 1322 * @param channel The 1588 timer channel number
screamer 0:e4d670b91a9a 1323 */
screamer 0:e4d670b91a9a 1324 static inline void enet_hal_clear_timer_channel_flag(uint32_t instance, uint32_t channel)
screamer 0:e4d670b91a9a 1325 {
screamer 0:e4d670b91a9a 1326 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 1327 assert(channel < HW_ENET_TCSRn_COUNT);
screamer 0:e4d670b91a9a 1328 HW_ENET_TCSRn_SET(instance, channel, BM_ENET_TCSRn_TF);/* clear interrupt flag*/
screamer 0:e4d670b91a9a 1329 HW_ENET_TGSR_WR(instance,(1U << channel)); /* clear channel flag*/
screamer 0:e4d670b91a9a 1330 }
screamer 0:e4d670b91a9a 1331
screamer 0:e4d670b91a9a 1332 /*!
screamer 0:e4d670b91a9a 1333 * @brief Sets the capture command to the 1588 timer.
screamer 0:e4d670b91a9a 1334 *
screamer 0:e4d670b91a9a 1335 * This is used before reading the current time register.
screamer 0:e4d670b91a9a 1336 * After set timer capture, please wait for about 1us before read
screamer 0:e4d670b91a9a 1337 * the captured timer.
screamer 0:e4d670b91a9a 1338 *
screamer 0:e4d670b91a9a 1339 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 1340 */
screamer 0:e4d670b91a9a 1341 static inline void enet_hal_set_timer_capture(uint32_t instance)
screamer 0:e4d670b91a9a 1342 {
screamer 0:e4d670b91a9a 1343 assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 1344
screamer 0:e4d670b91a9a 1345 HW_ENET_ATCR_SET(instance, BM_ENET_ATCR_CAPTURE);
screamer 0:e4d670b91a9a 1346 }
screamer 0:e4d670b91a9a 1347
screamer 0:e4d670b91a9a 1348 /*!
screamer 0:e4d670b91a9a 1349 * @brief Sets the 1588 timer.
screamer 0:e4d670b91a9a 1350 *
screamer 0:e4d670b91a9a 1351 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 1352 * @param nanSecond The nanosecond set to 1588 timer
screamer 0:e4d670b91a9a 1353 */
screamer 0:e4d670b91a9a 1354 static inline void enet_hal_set_current_time(uint32_t instance, uint32_t nanSecond)
screamer 0:e4d670b91a9a 1355 {
screamer 0:e4d670b91a9a 1356 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 1357
screamer 0:e4d670b91a9a 1358 HW_ENET_ATVR_WR(instance,nanSecond);
screamer 0:e4d670b91a9a 1359 }
screamer 0:e4d670b91a9a 1360
screamer 0:e4d670b91a9a 1361 /*!
screamer 0:e4d670b91a9a 1362 * @brief Gets the time from the 1588 timer.
screamer 0:e4d670b91a9a 1363 *
screamer 0:e4d670b91a9a 1364 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 1365 * @return the current time from 1588 timer
screamer 0:e4d670b91a9a 1366 */
screamer 0:e4d670b91a9a 1367 static inline uint32_t enet_hal_get_current_time(uint32_t instance)
screamer 0:e4d670b91a9a 1368 {
screamer 0:e4d670b91a9a 1369 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 1370
screamer 0:e4d670b91a9a 1371 return HW_ENET_ATVR_RD(instance);
screamer 0:e4d670b91a9a 1372 }
screamer 0:e4d670b91a9a 1373
screamer 0:e4d670b91a9a 1374 /*!
screamer 0:e4d670b91a9a 1375 * @brief Gets the transmit timestamp.
screamer 0:e4d670b91a9a 1376 *
screamer 0:e4d670b91a9a 1377 * @param instance The ENET instance number
screamer 0:e4d670b91a9a 1378 * @return The timestamp of the last transmitted frame
screamer 0:e4d670b91a9a 1379 */
screamer 0:e4d670b91a9a 1380 static inline uint32_t enet_hal_get_tx_timestamp(uint32_t instance)
screamer 0:e4d670b91a9a 1381 {
screamer 0:e4d670b91a9a 1382 // assert(instance < HW_ENET_INSTANCE_COUNT);
screamer 0:e4d670b91a9a 1383
screamer 0:e4d670b91a9a 1384 return HW_ENET_ATSTMP_RD(instance);
screamer 0:e4d670b91a9a 1385 }
screamer 0:e4d670b91a9a 1386
screamer 0:e4d670b91a9a 1387 /*!
screamer 0:e4d670b91a9a 1388 * @brief Gets the transmit buffer descriptor timestamp flag.
screamer 0:e4d670b91a9a 1389 *
screamer 0:e4d670b91a9a 1390 * @param curBd The ENET transmit buffer descriptor
screamer 0:e4d670b91a9a 1391 * @return true if timestamp region is set else false.
screamer 0:e4d670b91a9a 1392 */
screamer 0:e4d670b91a9a 1393 bool enet_hal_get_txbd_timestamp_flag(void *curBd);
screamer 0:e4d670b91a9a 1394
screamer 0:e4d670b91a9a 1395 /*!
screamer 0:e4d670b91a9a 1396 * @brief Gets the buffer descriptor timestamp.
screamer 0:e4d670b91a9a 1397 *
screamer 0:e4d670b91a9a 1398 * @param null
screamer 0:e4d670b91a9a 1399 * @return The the size of the buffer descriptor
screamer 0:e4d670b91a9a 1400 */
screamer 0:e4d670b91a9a 1401 static inline uint32_t enet_hal_get_bd_size(void)
screamer 0:e4d670b91a9a 1402 {
screamer 0:e4d670b91a9a 1403 return sizeof(enet_bd_struct_t);
screamer 0:e4d670b91a9a 1404 }
screamer 0:e4d670b91a9a 1405
screamer 0:e4d670b91a9a 1406 /* @} */
screamer 0:e4d670b91a9a 1407
screamer 0:e4d670b91a9a 1408 #if defined(__cplusplus)
screamer 0:e4d670b91a9a 1409 }
screamer 0:e4d670b91a9a 1410 #endif
screamer 0:e4d670b91a9a 1411
screamer 0:e4d670b91a9a 1412 #endif
screamer 0:e4d670b91a9a 1413
screamer 0:e4d670b91a9a 1414 /*! @}*/
screamer 0:e4d670b91a9a 1415 #endif /*!< __FSL_ENET_HAL_H__*/
screamer 0:e4d670b91a9a 1416
screamer 0:e4d670b91a9a 1417 /*******************************************************************************
screamer 0:e4d670b91a9a 1418 * EOF
screamer 0:e4d670b91a9a 1419 ******************************************************************************/
screamer 0:e4d670b91a9a 1420