Alessandro Angelino / mbed-hal

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Dependencies:   target-freescale

Fork of mbed-hal by Morpheus

targets/common/cmsis/core_cm0.h@4:473d4af53300, 2016-04-04 (annotated)

Committer:
Alessandro Angelino
Date:
Mon Apr 04 14:24:07 2016 +0100
Revision:
4:473d4af53300
Parent:
0:9c59db1fbc9e 
Fix function to get sp when in unprivileged mode

Who changed what in which revision?

UserRevisionLine numberNew contents of line
screamer 0:9c59db1fbc9e 1 /**************************************************************************//**
screamer 0:9c59db1fbc9e 2 * @file core_cm0.h
screamer 0:9c59db1fbc9e 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
screamer 0:9c59db1fbc9e 4 * @version V4.10
screamer 0:9c59db1fbc9e 5 * @date 18. March 2015
screamer 0:9c59db1fbc9e 6 *
screamer 0:9c59db1fbc9e 7 * @note
screamer 0:9c59db1fbc9e 8 *
screamer 0:9c59db1fbc9e 9 ******************************************************************************/
screamer 0:9c59db1fbc9e 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
screamer 0:9c59db1fbc9e 11
screamer 0:9c59db1fbc9e 12 All rights reserved.
screamer 0:9c59db1fbc9e 13 Redistribution and use in source and binary forms, with or without
screamer 0:9c59db1fbc9e 14 modification, are permitted provided that the following conditions are met:
screamer 0:9c59db1fbc9e 15 - Redistributions of source code must retain the above copyright
screamer 0:9c59db1fbc9e 16 notice, this list of conditions and the following disclaimer.
screamer 0:9c59db1fbc9e 17 - Redistributions in binary form must reproduce the above copyright
screamer 0:9c59db1fbc9e 18 notice, this list of conditions and the following disclaimer in the
screamer 0:9c59db1fbc9e 19 documentation and/or other materials provided with the distribution.
screamer 0:9c59db1fbc9e 20 - Neither the name of ARM nor the names of its contributors may be used
screamer 0:9c59db1fbc9e 21 to endorse or promote products derived from this software without
screamer 0:9c59db1fbc9e 22 specific prior written permission.
screamer 0:9c59db1fbc9e 23 *
screamer 0:9c59db1fbc9e 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
screamer 0:9c59db1fbc9e 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
screamer 0:9c59db1fbc9e 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
screamer 0:9c59db1fbc9e 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
screamer 0:9c59db1fbc9e 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
screamer 0:9c59db1fbc9e 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
screamer 0:9c59db1fbc9e 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
screamer 0:9c59db1fbc9e 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
screamer 0:9c59db1fbc9e 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
screamer 0:9c59db1fbc9e 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
screamer 0:9c59db1fbc9e 34 POSSIBILITY OF SUCH DAMAGE.
screamer 0:9c59db1fbc9e 35 ---------------------------------------------------------------------------*/
screamer 0:9c59db1fbc9e 36
screamer 0:9c59db1fbc9e 37
screamer 0:9c59db1fbc9e 38 #if defined ( __ICCARM__ )
screamer 0:9c59db1fbc9e 39 #pragma system_include /* treat file as system include file for MISRA check */
screamer 0:9c59db1fbc9e 40 #endif
screamer 0:9c59db1fbc9e 41
screamer 0:9c59db1fbc9e 42 #ifndef __CORE_CM0_H_GENERIC
screamer 0:9c59db1fbc9e 43 #define __CORE_CM0_H_GENERIC
screamer 0:9c59db1fbc9e 44
screamer 0:9c59db1fbc9e 45 #ifdef __cplusplus
screamer 0:9c59db1fbc9e 46 extern "C" {
screamer 0:9c59db1fbc9e 47 #endif
screamer 0:9c59db1fbc9e 48
screamer 0:9c59db1fbc9e 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
screamer 0:9c59db1fbc9e 50 CMSIS violates the following MISRA-C:2004 rules:
screamer 0:9c59db1fbc9e 51
screamer 0:9c59db1fbc9e 52 \li Required Rule 8.5, object/function definition in header file.<br>
screamer 0:9c59db1fbc9e 53 Function definitions in header files are used to allow 'inlining'.
screamer 0:9c59db1fbc9e 54
screamer 0:9c59db1fbc9e 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
screamer 0:9c59db1fbc9e 56 Unions are used for effective representation of core registers.
screamer 0:9c59db1fbc9e 57
screamer 0:9c59db1fbc9e 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
screamer 0:9c59db1fbc9e 59 Function-like macros are used to allow more efficient code.
screamer 0:9c59db1fbc9e 60 */
screamer 0:9c59db1fbc9e 61
screamer 0:9c59db1fbc9e 62
screamer 0:9c59db1fbc9e 63 /*******************************************************************************
screamer 0:9c59db1fbc9e 64 * CMSIS definitions
screamer 0:9c59db1fbc9e 65 ******************************************************************************/
screamer 0:9c59db1fbc9e 66 /** \ingroup Cortex_M0
screamer 0:9c59db1fbc9e 67 @{
screamer 0:9c59db1fbc9e 68 */
screamer 0:9c59db1fbc9e 69
screamer 0:9c59db1fbc9e 70 /* CMSIS CM0 definitions */
screamer 0:9c59db1fbc9e 71 #define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
screamer 0:9c59db1fbc9e 72 #define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
screamer 0:9c59db1fbc9e 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
screamer 0:9c59db1fbc9e 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
screamer 0:9c59db1fbc9e 75
screamer 0:9c59db1fbc9e 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
screamer 0:9c59db1fbc9e 77
screamer 0:9c59db1fbc9e 78
screamer 0:9c59db1fbc9e 79 #if defined ( __CC_ARM )
screamer 0:9c59db1fbc9e 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
screamer 0:9c59db1fbc9e 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
screamer 0:9c59db1fbc9e 82 #define __STATIC_INLINE static __inline
screamer 0:9c59db1fbc9e 83
screamer 0:9c59db1fbc9e 84 #elif defined ( __GNUC__ )
screamer 0:9c59db1fbc9e 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
screamer 0:9c59db1fbc9e 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
screamer 0:9c59db1fbc9e 87 #define __STATIC_INLINE static inline
screamer 0:9c59db1fbc9e 88
screamer 0:9c59db1fbc9e 89 #elif defined ( __ICCARM__ )
screamer 0:9c59db1fbc9e 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
screamer 0:9c59db1fbc9e 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
screamer 0:9c59db1fbc9e 92 #define __STATIC_INLINE static inline
screamer 0:9c59db1fbc9e 93
screamer 0:9c59db1fbc9e 94 #elif defined ( __TMS470__ )
screamer 0:9c59db1fbc9e 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
screamer 0:9c59db1fbc9e 96 #define __STATIC_INLINE static inline
screamer 0:9c59db1fbc9e 97
screamer 0:9c59db1fbc9e 98 #elif defined ( __TASKING__ )
screamer 0:9c59db1fbc9e 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
screamer 0:9c59db1fbc9e 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
screamer 0:9c59db1fbc9e 101 #define __STATIC_INLINE static inline
screamer 0:9c59db1fbc9e 102
screamer 0:9c59db1fbc9e 103 #elif defined ( __CSMC__ )
screamer 0:9c59db1fbc9e 104 #define __packed
screamer 0:9c59db1fbc9e 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
screamer 0:9c59db1fbc9e 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
screamer 0:9c59db1fbc9e 107 #define __STATIC_INLINE static inline
screamer 0:9c59db1fbc9e 108
screamer 0:9c59db1fbc9e 109 #endif
screamer 0:9c59db1fbc9e 110
screamer 0:9c59db1fbc9e 111 /** __FPU_USED indicates whether an FPU is used or not.
screamer 0:9c59db1fbc9e 112 This core does not support an FPU at all
screamer 0:9c59db1fbc9e 113 */
screamer 0:9c59db1fbc9e 114 #define __FPU_USED 0
screamer 0:9c59db1fbc9e 115
screamer 0:9c59db1fbc9e 116 #if defined ( __CC_ARM )
screamer 0:9c59db1fbc9e 117 #if defined __TARGET_FPU_VFP
screamer 0:9c59db1fbc9e 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
screamer 0:9c59db1fbc9e 119 #endif
screamer 0:9c59db1fbc9e 120
screamer 0:9c59db1fbc9e 121 #elif defined ( __GNUC__ )
screamer 0:9c59db1fbc9e 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
screamer 0:9c59db1fbc9e 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
screamer 0:9c59db1fbc9e 124 #endif
screamer 0:9c59db1fbc9e 125
screamer 0:9c59db1fbc9e 126 #elif defined ( __ICCARM__ )
screamer 0:9c59db1fbc9e 127 #if defined __ARMVFP__
screamer 0:9c59db1fbc9e 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
screamer 0:9c59db1fbc9e 129 #endif
screamer 0:9c59db1fbc9e 130
screamer 0:9c59db1fbc9e 131 #elif defined ( __TMS470__ )
screamer 0:9c59db1fbc9e 132 #if defined __TI__VFP_SUPPORT____
screamer 0:9c59db1fbc9e 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
screamer 0:9c59db1fbc9e 134 #endif
screamer 0:9c59db1fbc9e 135
screamer 0:9c59db1fbc9e 136 #elif defined ( __TASKING__ )
screamer 0:9c59db1fbc9e 137 #if defined __FPU_VFP__
screamer 0:9c59db1fbc9e 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
screamer 0:9c59db1fbc9e 139 #endif
screamer 0:9c59db1fbc9e 140
screamer 0:9c59db1fbc9e 141 #elif defined ( __CSMC__ ) /* Cosmic */
screamer 0:9c59db1fbc9e 142 #if ( __CSMC__ & 0x400) // FPU present for parser
screamer 0:9c59db1fbc9e 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
screamer 0:9c59db1fbc9e 144 #endif
screamer 0:9c59db1fbc9e 145 #endif
screamer 0:9c59db1fbc9e 146
screamer 0:9c59db1fbc9e 147 #include <stdint.h> /* standard types definitions */
screamer 0:9c59db1fbc9e 148 #include <core_cmInstr.h> /* Core Instruction Access */
screamer 0:9c59db1fbc9e 149 #include <core_cmFunc.h> /* Core Function Access */
screamer 0:9c59db1fbc9e 150
screamer 0:9c59db1fbc9e 151 #ifdef __cplusplus
screamer 0:9c59db1fbc9e 152 }
screamer 0:9c59db1fbc9e 153 #endif
screamer 0:9c59db1fbc9e 154
screamer 0:9c59db1fbc9e 155 #endif /* __CORE_CM0_H_GENERIC */
screamer 0:9c59db1fbc9e 156
screamer 0:9c59db1fbc9e 157 #ifndef __CMSIS_GENERIC
screamer 0:9c59db1fbc9e 158
screamer 0:9c59db1fbc9e 159 #ifndef __CORE_CM0_H_DEPENDANT
screamer 0:9c59db1fbc9e 160 #define __CORE_CM0_H_DEPENDANT
screamer 0:9c59db1fbc9e 161
screamer 0:9c59db1fbc9e 162 #ifdef __cplusplus
screamer 0:9c59db1fbc9e 163 extern "C" {
screamer 0:9c59db1fbc9e 164 #endif
screamer 0:9c59db1fbc9e 165
screamer 0:9c59db1fbc9e 166 /* check device defines and use defaults */
screamer 0:9c59db1fbc9e 167 #if defined __CHECK_DEVICE_DEFINES
screamer 0:9c59db1fbc9e 168 #ifndef __CM0_REV
screamer 0:9c59db1fbc9e 169 #define __CM0_REV 0x0000
screamer 0:9c59db1fbc9e 170 #warning "__CM0_REV not defined in device header file; using default!"
screamer 0:9c59db1fbc9e 171 #endif
screamer 0:9c59db1fbc9e 172
screamer 0:9c59db1fbc9e 173 #ifndef __NVIC_PRIO_BITS
screamer 0:9c59db1fbc9e 174 #define __NVIC_PRIO_BITS 2
screamer 0:9c59db1fbc9e 175 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
screamer 0:9c59db1fbc9e 176 #endif
screamer 0:9c59db1fbc9e 177
screamer 0:9c59db1fbc9e 178 #ifndef __Vendor_SysTickConfig
screamer 0:9c59db1fbc9e 179 #define __Vendor_SysTickConfig 0
screamer 0:9c59db1fbc9e 180 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
screamer 0:9c59db1fbc9e 181 #endif
screamer 0:9c59db1fbc9e 182 #endif
screamer 0:9c59db1fbc9e 183
screamer 0:9c59db1fbc9e 184 /* IO definitions (access restrictions to peripheral registers) */
screamer 0:9c59db1fbc9e 185 /**
screamer 0:9c59db1fbc9e 186 \defgroup CMSIS_glob_defs CMSIS Global Defines
screamer 0:9c59db1fbc9e 187
screamer 0:9c59db1fbc9e 188 <strong>IO Type Qualifiers</strong> are used
screamer 0:9c59db1fbc9e 189 \li to specify the access to peripheral variables.
screamer 0:9c59db1fbc9e 190 \li for automatic generation of peripheral register debug information.
screamer 0:9c59db1fbc9e 191 */
screamer 0:9c59db1fbc9e 192 #ifdef __cplusplus
screamer 0:9c59db1fbc9e 193 #define __I volatile /*!< Defines 'read only' permissions */
screamer 0:9c59db1fbc9e 194 #else
screamer 0:9c59db1fbc9e 195 #define __I volatile const /*!< Defines 'read only' permissions */
screamer 0:9c59db1fbc9e 196 #endif
screamer 0:9c59db1fbc9e 197 #define __O volatile /*!< Defines 'write only' permissions */
screamer 0:9c59db1fbc9e 198 #define __IO volatile /*!< Defines 'read / write' permissions */
screamer 0:9c59db1fbc9e 199
screamer 0:9c59db1fbc9e 200 /*@} end of group Cortex_M0 */
screamer 0:9c59db1fbc9e 201
screamer 0:9c59db1fbc9e 202
screamer 0:9c59db1fbc9e 203
screamer 0:9c59db1fbc9e 204 /*******************************************************************************
screamer 0:9c59db1fbc9e 205 * Register Abstraction
screamer 0:9c59db1fbc9e 206 Core Register contain:
screamer 0:9c59db1fbc9e 207 - Core Register
screamer 0:9c59db1fbc9e 208 - Core NVIC Register
screamer 0:9c59db1fbc9e 209 - Core SCB Register
screamer 0:9c59db1fbc9e 210 - Core SysTick Register
screamer 0:9c59db1fbc9e 211 ******************************************************************************/
screamer 0:9c59db1fbc9e 212 /** \defgroup CMSIS_core_register Defines and Type Definitions
screamer 0:9c59db1fbc9e 213 \brief Type definitions and defines for Cortex-M processor based devices.
screamer 0:9c59db1fbc9e 214 */
screamer 0:9c59db1fbc9e 215
screamer 0:9c59db1fbc9e 216 /** \ingroup CMSIS_core_register
screamer 0:9c59db1fbc9e 217 \defgroup CMSIS_CORE Status and Control Registers
screamer 0:9c59db1fbc9e 218 \brief Core Register type definitions.
screamer 0:9c59db1fbc9e 219 @{
screamer 0:9c59db1fbc9e 220 */
screamer 0:9c59db1fbc9e 221
screamer 0:9c59db1fbc9e 222 /** \brief Union type to access the Application Program Status Register (APSR).
screamer 0:9c59db1fbc9e 223 */
screamer 0:9c59db1fbc9e 224 typedef union
screamer 0:9c59db1fbc9e 225 {
screamer 0:9c59db1fbc9e 226 struct
screamer 0:9c59db1fbc9e 227 {
screamer 0:9c59db1fbc9e 228 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
screamer 0:9c59db1fbc9e 229 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
screamer 0:9c59db1fbc9e 230 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
screamer 0:9c59db1fbc9e 231 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
screamer 0:9c59db1fbc9e 232 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
screamer 0:9c59db1fbc9e 233 } b; /*!< Structure used for bit access */
screamer 0:9c59db1fbc9e 234 uint32_t w; /*!< Type used for word access */
screamer 0:9c59db1fbc9e 235 } APSR_Type;
screamer 0:9c59db1fbc9e 236
screamer 0:9c59db1fbc9e 237 /* APSR Register Definitions */
screamer 0:9c59db1fbc9e 238 #define APSR_N_Pos 31 /*!< APSR: N Position */
screamer 0:9c59db1fbc9e 239 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
screamer 0:9c59db1fbc9e 240
screamer 0:9c59db1fbc9e 241 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
screamer 0:9c59db1fbc9e 242 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
screamer 0:9c59db1fbc9e 243
screamer 0:9c59db1fbc9e 244 #define APSR_C_Pos 29 /*!< APSR: C Position */
screamer 0:9c59db1fbc9e 245 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
screamer 0:9c59db1fbc9e 246
screamer 0:9c59db1fbc9e 247 #define APSR_V_Pos 28 /*!< APSR: V Position */
screamer 0:9c59db1fbc9e 248 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
screamer 0:9c59db1fbc9e 249
screamer 0:9c59db1fbc9e 250
screamer 0:9c59db1fbc9e 251 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
screamer 0:9c59db1fbc9e 252 */
screamer 0:9c59db1fbc9e 253 typedef union
screamer 0:9c59db1fbc9e 254 {
screamer 0:9c59db1fbc9e 255 struct
screamer 0:9c59db1fbc9e 256 {
screamer 0:9c59db1fbc9e 257 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
screamer 0:9c59db1fbc9e 258 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
screamer 0:9c59db1fbc9e 259 } b; /*!< Structure used for bit access */
screamer 0:9c59db1fbc9e 260 uint32_t w; /*!< Type used for word access */
screamer 0:9c59db1fbc9e 261 } IPSR_Type;
screamer 0:9c59db1fbc9e 262
screamer 0:9c59db1fbc9e 263 /* IPSR Register Definitions */
screamer 0:9c59db1fbc9e 264 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
screamer 0:9c59db1fbc9e 265 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
screamer 0:9c59db1fbc9e 266
screamer 0:9c59db1fbc9e 267
screamer 0:9c59db1fbc9e 268 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
screamer 0:9c59db1fbc9e 269 */
screamer 0:9c59db1fbc9e 270 typedef union
screamer 0:9c59db1fbc9e 271 {
screamer 0:9c59db1fbc9e 272 struct
screamer 0:9c59db1fbc9e 273 {
screamer 0:9c59db1fbc9e 274 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
screamer 0:9c59db1fbc9e 275 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
screamer 0:9c59db1fbc9e 276 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
screamer 0:9c59db1fbc9e 277 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
screamer 0:9c59db1fbc9e 278 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
screamer 0:9c59db1fbc9e 279 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
screamer 0:9c59db1fbc9e 280 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
screamer 0:9c59db1fbc9e 281 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
screamer 0:9c59db1fbc9e 282 } b; /*!< Structure used for bit access */
screamer 0:9c59db1fbc9e 283 uint32_t w; /*!< Type used for word access */
screamer 0:9c59db1fbc9e 284 } xPSR_Type;
screamer 0:9c59db1fbc9e 285
screamer 0:9c59db1fbc9e 286 /* xPSR Register Definitions */
screamer 0:9c59db1fbc9e 287 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
screamer 0:9c59db1fbc9e 288 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
screamer 0:9c59db1fbc9e 289
screamer 0:9c59db1fbc9e 290 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
screamer 0:9c59db1fbc9e 291 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
screamer 0:9c59db1fbc9e 292
screamer 0:9c59db1fbc9e 293 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
screamer 0:9c59db1fbc9e 294 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
screamer 0:9c59db1fbc9e 295
screamer 0:9c59db1fbc9e 296 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
screamer 0:9c59db1fbc9e 297 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
screamer 0:9c59db1fbc9e 298
screamer 0:9c59db1fbc9e 299 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
screamer 0:9c59db1fbc9e 300 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
screamer 0:9c59db1fbc9e 301
screamer 0:9c59db1fbc9e 302 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
screamer 0:9c59db1fbc9e 303 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
screamer 0:9c59db1fbc9e 304
screamer 0:9c59db1fbc9e 305
screamer 0:9c59db1fbc9e 306 /** \brief Union type to access the Control Registers (CONTROL).
screamer 0:9c59db1fbc9e 307 */
screamer 0:9c59db1fbc9e 308 typedef union
screamer 0:9c59db1fbc9e 309 {
screamer 0:9c59db1fbc9e 310 struct
screamer 0:9c59db1fbc9e 311 {
screamer 0:9c59db1fbc9e 312 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
screamer 0:9c59db1fbc9e 313 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
screamer 0:9c59db1fbc9e 314 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
screamer 0:9c59db1fbc9e 315 } b; /*!< Structure used for bit access */
screamer 0:9c59db1fbc9e 316 uint32_t w; /*!< Type used for word access */
screamer 0:9c59db1fbc9e 317 } CONTROL_Type;
screamer 0:9c59db1fbc9e 318
screamer 0:9c59db1fbc9e 319 /* CONTROL Register Definitions */
screamer 0:9c59db1fbc9e 320 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
screamer 0:9c59db1fbc9e 321 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
screamer 0:9c59db1fbc9e 322
screamer 0:9c59db1fbc9e 323 /*@} end of group CMSIS_CORE */
screamer 0:9c59db1fbc9e 324
screamer 0:9c59db1fbc9e 325
screamer 0:9c59db1fbc9e 326 /** \ingroup CMSIS_core_register
screamer 0:9c59db1fbc9e 327 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
screamer 0:9c59db1fbc9e 328 \brief Type definitions for the NVIC Registers
screamer 0:9c59db1fbc9e 329 @{
screamer 0:9c59db1fbc9e 330 */
screamer 0:9c59db1fbc9e 331
screamer 0:9c59db1fbc9e 332 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
screamer 0:9c59db1fbc9e 333 */
screamer 0:9c59db1fbc9e 334 typedef struct
screamer 0:9c59db1fbc9e 335 {
screamer 0:9c59db1fbc9e 336 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
screamer 0:9c59db1fbc9e 337 uint32_t RESERVED0[31];
screamer 0:9c59db1fbc9e 338 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
screamer 0:9c59db1fbc9e 339 uint32_t RSERVED1[31];
screamer 0:9c59db1fbc9e 340 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
screamer 0:9c59db1fbc9e 341 uint32_t RESERVED2[31];
screamer 0:9c59db1fbc9e 342 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
screamer 0:9c59db1fbc9e 343 uint32_t RESERVED3[31];
screamer 0:9c59db1fbc9e 344 uint32_t RESERVED4[64];
screamer 0:9c59db1fbc9e 345 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
screamer 0:9c59db1fbc9e 346 } NVIC_Type;
screamer 0:9c59db1fbc9e 347
screamer 0:9c59db1fbc9e 348 /*@} end of group CMSIS_NVIC */
screamer 0:9c59db1fbc9e 349
screamer 0:9c59db1fbc9e 350
screamer 0:9c59db1fbc9e 351 /** \ingroup CMSIS_core_register
screamer 0:9c59db1fbc9e 352 \defgroup CMSIS_SCB System Control Block (SCB)
screamer 0:9c59db1fbc9e 353 \brief Type definitions for the System Control Block Registers
screamer 0:9c59db1fbc9e 354 @{
screamer 0:9c59db1fbc9e 355 */
screamer 0:9c59db1fbc9e 356
screamer 0:9c59db1fbc9e 357 /** \brief Structure type to access the System Control Block (SCB).
screamer 0:9c59db1fbc9e 358 */
screamer 0:9c59db1fbc9e 359 typedef struct
screamer 0:9c59db1fbc9e 360 {
screamer 0:9c59db1fbc9e 361 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
screamer 0:9c59db1fbc9e 362 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
screamer 0:9c59db1fbc9e 363 uint32_t RESERVED0;
screamer 0:9c59db1fbc9e 364 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
screamer 0:9c59db1fbc9e 365 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
screamer 0:9c59db1fbc9e 366 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
screamer 0:9c59db1fbc9e 367 uint32_t RESERVED1;
screamer 0:9c59db1fbc9e 368 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
screamer 0:9c59db1fbc9e 369 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
screamer 0:9c59db1fbc9e 370 } SCB_Type;
screamer 0:9c59db1fbc9e 371
screamer 0:9c59db1fbc9e 372 /* SCB CPUID Register Definitions */
screamer 0:9c59db1fbc9e 373 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
screamer 0:9c59db1fbc9e 374 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
screamer 0:9c59db1fbc9e 375
screamer 0:9c59db1fbc9e 376 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
screamer 0:9c59db1fbc9e 377 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
screamer 0:9c59db1fbc9e 378
screamer 0:9c59db1fbc9e 379 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
screamer 0:9c59db1fbc9e 380 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
screamer 0:9c59db1fbc9e 381
screamer 0:9c59db1fbc9e 382 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
screamer 0:9c59db1fbc9e 383 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
screamer 0:9c59db1fbc9e 384
screamer 0:9c59db1fbc9e 385 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
screamer 0:9c59db1fbc9e 386 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
screamer 0:9c59db1fbc9e 387
screamer 0:9c59db1fbc9e 388 /* SCB Interrupt Control State Register Definitions */
screamer 0:9c59db1fbc9e 389 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
screamer 0:9c59db1fbc9e 390 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
screamer 0:9c59db1fbc9e 391
screamer 0:9c59db1fbc9e 392 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
screamer 0:9c59db1fbc9e 393 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
screamer 0:9c59db1fbc9e 394
screamer 0:9c59db1fbc9e 395 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
screamer 0:9c59db1fbc9e 396 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
screamer 0:9c59db1fbc9e 397
screamer 0:9c59db1fbc9e 398 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
screamer 0:9c59db1fbc9e 399 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
screamer 0:9c59db1fbc9e 400
screamer 0:9c59db1fbc9e 401 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
screamer 0:9c59db1fbc9e 402 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
screamer 0:9c59db1fbc9e 403
screamer 0:9c59db1fbc9e 404 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
screamer 0:9c59db1fbc9e 405 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
screamer 0:9c59db1fbc9e 406
screamer 0:9c59db1fbc9e 407 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
screamer 0:9c59db1fbc9e 408 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
screamer 0:9c59db1fbc9e 409
screamer 0:9c59db1fbc9e 410 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
screamer 0:9c59db1fbc9e 411 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
screamer 0:9c59db1fbc9e 412
screamer 0:9c59db1fbc9e 413 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
screamer 0:9c59db1fbc9e 414 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
screamer 0:9c59db1fbc9e 415
screamer 0:9c59db1fbc9e 416 /* SCB Application Interrupt and Reset Control Register Definitions */
screamer 0:9c59db1fbc9e 417 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
screamer 0:9c59db1fbc9e 418 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
screamer 0:9c59db1fbc9e 419
screamer 0:9c59db1fbc9e 420 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
screamer 0:9c59db1fbc9e 421 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
screamer 0:9c59db1fbc9e 422
screamer 0:9c59db1fbc9e 423 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
screamer 0:9c59db1fbc9e 424 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
screamer 0:9c59db1fbc9e 425
screamer 0:9c59db1fbc9e 426 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
screamer 0:9c59db1fbc9e 427 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
screamer 0:9c59db1fbc9e 428
screamer 0:9c59db1fbc9e 429 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
screamer 0:9c59db1fbc9e 430 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
screamer 0:9c59db1fbc9e 431
screamer 0:9c59db1fbc9e 432 /* SCB System Control Register Definitions */
screamer 0:9c59db1fbc9e 433 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
screamer 0:9c59db1fbc9e 434 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
screamer 0:9c59db1fbc9e 435
screamer 0:9c59db1fbc9e 436 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
screamer 0:9c59db1fbc9e 437 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
screamer 0:9c59db1fbc9e 438
screamer 0:9c59db1fbc9e 439 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
screamer 0:9c59db1fbc9e 440 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
screamer 0:9c59db1fbc9e 441
screamer 0:9c59db1fbc9e 442 /* SCB Configuration Control Register Definitions */
screamer 0:9c59db1fbc9e 443 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
screamer 0:9c59db1fbc9e 444 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
screamer 0:9c59db1fbc9e 445
screamer 0:9c59db1fbc9e 446 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
screamer 0:9c59db1fbc9e 447 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
screamer 0:9c59db1fbc9e 448
screamer 0:9c59db1fbc9e 449 /* SCB System Handler Control and State Register Definitions */
screamer 0:9c59db1fbc9e 450 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
screamer 0:9c59db1fbc9e 451 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
screamer 0:9c59db1fbc9e 452
screamer 0:9c59db1fbc9e 453 /*@} end of group CMSIS_SCB */
screamer 0:9c59db1fbc9e 454
screamer 0:9c59db1fbc9e 455
screamer 0:9c59db1fbc9e 456 /** \ingroup CMSIS_core_register
screamer 0:9c59db1fbc9e 457 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
screamer 0:9c59db1fbc9e 458 \brief Type definitions for the System Timer Registers.
screamer 0:9c59db1fbc9e 459 @{
screamer 0:9c59db1fbc9e 460 */
screamer 0:9c59db1fbc9e 461
screamer 0:9c59db1fbc9e 462 /** \brief Structure type to access the System Timer (SysTick).
screamer 0:9c59db1fbc9e 463 */
screamer 0:9c59db1fbc9e 464 typedef struct
screamer 0:9c59db1fbc9e 465 {
screamer 0:9c59db1fbc9e 466 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
screamer 0:9c59db1fbc9e 467 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
screamer 0:9c59db1fbc9e 468 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
screamer 0:9c59db1fbc9e 469 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
screamer 0:9c59db1fbc9e 470 } SysTick_Type;
screamer 0:9c59db1fbc9e 471
screamer 0:9c59db1fbc9e 472 /* SysTick Control / Status Register Definitions */
screamer 0:9c59db1fbc9e 473 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
screamer 0:9c59db1fbc9e 474 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
screamer 0:9c59db1fbc9e 475
screamer 0:9c59db1fbc9e 476 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
screamer 0:9c59db1fbc9e 477 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
screamer 0:9c59db1fbc9e 478
screamer 0:9c59db1fbc9e 479 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
screamer 0:9c59db1fbc9e 480 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
screamer 0:9c59db1fbc9e 481
screamer 0:9c59db1fbc9e 482 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
screamer 0:9c59db1fbc9e 483 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
screamer 0:9c59db1fbc9e 484
screamer 0:9c59db1fbc9e 485 /* SysTick Reload Register Definitions */
screamer 0:9c59db1fbc9e 486 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
screamer 0:9c59db1fbc9e 487 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
screamer 0:9c59db1fbc9e 488
screamer 0:9c59db1fbc9e 489 /* SysTick Current Register Definitions */
screamer 0:9c59db1fbc9e 490 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
screamer 0:9c59db1fbc9e 491 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
screamer 0:9c59db1fbc9e 492
screamer 0:9c59db1fbc9e 493 /* SysTick Calibration Register Definitions */
screamer 0:9c59db1fbc9e 494 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
screamer 0:9c59db1fbc9e 495 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
screamer 0:9c59db1fbc9e 496
screamer 0:9c59db1fbc9e 497 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
screamer 0:9c59db1fbc9e 498 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
screamer 0:9c59db1fbc9e 499
screamer 0:9c59db1fbc9e 500 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
screamer 0:9c59db1fbc9e 501 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
screamer 0:9c59db1fbc9e 502
screamer 0:9c59db1fbc9e 503 /*@} end of group CMSIS_SysTick */
screamer 0:9c59db1fbc9e 504
screamer 0:9c59db1fbc9e 505
screamer 0:9c59db1fbc9e 506 /** \ingroup CMSIS_core_register
screamer 0:9c59db1fbc9e 507 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
screamer 0:9c59db1fbc9e 508 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
screamer 0:9c59db1fbc9e 509 are only accessible over DAP and not via processor. Therefore
screamer 0:9c59db1fbc9e 510 they are not covered by the Cortex-M0 header file.
screamer 0:9c59db1fbc9e 511 @{
screamer 0:9c59db1fbc9e 512 */
screamer 0:9c59db1fbc9e 513 /*@} end of group CMSIS_CoreDebug */
screamer 0:9c59db1fbc9e 514
screamer 0:9c59db1fbc9e 515
screamer 0:9c59db1fbc9e 516 /** \ingroup CMSIS_core_register
screamer 0:9c59db1fbc9e 517 \defgroup CMSIS_core_base Core Definitions
screamer 0:9c59db1fbc9e 518 \brief Definitions for base addresses, unions, and structures.
screamer 0:9c59db1fbc9e 519 @{
screamer 0:9c59db1fbc9e 520 */
screamer 0:9c59db1fbc9e 521
screamer 0:9c59db1fbc9e 522 /* Memory mapping of Cortex-M0 Hardware */
screamer 0:9c59db1fbc9e 523 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
screamer 0:9c59db1fbc9e 524 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
screamer 0:9c59db1fbc9e 525 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
screamer 0:9c59db1fbc9e 526 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
screamer 0:9c59db1fbc9e 527
screamer 0:9c59db1fbc9e 528 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
screamer 0:9c59db1fbc9e 529 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
screamer 0:9c59db1fbc9e 530 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
screamer 0:9c59db1fbc9e 531
screamer 0:9c59db1fbc9e 532
screamer 0:9c59db1fbc9e 533 /*@} */
screamer 0:9c59db1fbc9e 534
screamer 0:9c59db1fbc9e 535
screamer 0:9c59db1fbc9e 536
screamer 0:9c59db1fbc9e 537 /*******************************************************************************
screamer 0:9c59db1fbc9e 538 * Hardware Abstraction Layer
screamer 0:9c59db1fbc9e 539 Core Function Interface contains:
screamer 0:9c59db1fbc9e 540 - Core NVIC Functions
screamer 0:9c59db1fbc9e 541 - Core SysTick Functions
screamer 0:9c59db1fbc9e 542 - Core Register Access Functions
screamer 0:9c59db1fbc9e 543 ******************************************************************************/
screamer 0:9c59db1fbc9e 544 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
screamer 0:9c59db1fbc9e 545 */
screamer 0:9c59db1fbc9e 546
screamer 0:9c59db1fbc9e 547
screamer 0:9c59db1fbc9e 548
screamer 0:9c59db1fbc9e 549 /* ########################## NVIC functions #################################### */
screamer 0:9c59db1fbc9e 550 /** \ingroup CMSIS_Core_FunctionInterface
screamer 0:9c59db1fbc9e 551 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
screamer 0:9c59db1fbc9e 552 \brief Functions that manage interrupts and exceptions via the NVIC.
screamer 0:9c59db1fbc9e 553 @{
screamer 0:9c59db1fbc9e 554 */
screamer 0:9c59db1fbc9e 555
screamer 0:9c59db1fbc9e 556 /* Interrupt Priorities are WORD accessible only under ARMv6M */
screamer 0:9c59db1fbc9e 557 /* The following MACROS handle generation of the register offset and byte masks */
screamer 0:9c59db1fbc9e 558 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
screamer 0:9c59db1fbc9e 559 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
screamer 0:9c59db1fbc9e 560 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
screamer 0:9c59db1fbc9e 561
screamer 0:9c59db1fbc9e 562
screamer 0:9c59db1fbc9e 563 /** \brief Enable External Interrupt
screamer 0:9c59db1fbc9e 564
screamer 0:9c59db1fbc9e 565 The function enables a device-specific interrupt in the NVIC interrupt controller.
screamer 0:9c59db1fbc9e 566
screamer 0:9c59db1fbc9e 567 \param [in] IRQn External interrupt number. Value cannot be negative.
screamer 0:9c59db1fbc9e 568 */
screamer 0:9c59db1fbc9e 569 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
screamer 0:9c59db1fbc9e 570 {
screamer 0:9c59db1fbc9e 571 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
screamer 0:9c59db1fbc9e 572 }
screamer 0:9c59db1fbc9e 573
screamer 0:9c59db1fbc9e 574
screamer 0:9c59db1fbc9e 575 /** \brief Disable External Interrupt
screamer 0:9c59db1fbc9e 576
screamer 0:9c59db1fbc9e 577 The function disables a device-specific interrupt in the NVIC interrupt controller.
screamer 0:9c59db1fbc9e 578
screamer 0:9c59db1fbc9e 579 \param [in] IRQn External interrupt number. Value cannot be negative.
screamer 0:9c59db1fbc9e 580 */
screamer 0:9c59db1fbc9e 581 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
screamer 0:9c59db1fbc9e 582 {
screamer 0:9c59db1fbc9e 583 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
screamer 0:9c59db1fbc9e 584 }
screamer 0:9c59db1fbc9e 585
screamer 0:9c59db1fbc9e 586
screamer 0:9c59db1fbc9e 587 /** \brief Get Pending Interrupt
screamer 0:9c59db1fbc9e 588
screamer 0:9c59db1fbc9e 589 The function reads the pending register in the NVIC and returns the pending bit
screamer 0:9c59db1fbc9e 590 for the specified interrupt.
screamer 0:9c59db1fbc9e 591
screamer 0:9c59db1fbc9e 592 \param [in] IRQn Interrupt number.
screamer 0:9c59db1fbc9e 593
screamer 0:9c59db1fbc9e 594 \return 0 Interrupt status is not pending.
screamer 0:9c59db1fbc9e 595 \return 1 Interrupt status is pending.
screamer 0:9c59db1fbc9e 596 */
screamer 0:9c59db1fbc9e 597 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
screamer 0:9c59db1fbc9e 598 {
screamer 0:9c59db1fbc9e 599 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
screamer 0:9c59db1fbc9e 600 }
screamer 0:9c59db1fbc9e 601
screamer 0:9c59db1fbc9e 602
screamer 0:9c59db1fbc9e 603 /** \brief Set Pending Interrupt
screamer 0:9c59db1fbc9e 604
screamer 0:9c59db1fbc9e 605 The function sets the pending bit of an external interrupt.
screamer 0:9c59db1fbc9e 606
screamer 0:9c59db1fbc9e 607 \param [in] IRQn Interrupt number. Value cannot be negative.
screamer 0:9c59db1fbc9e 608 */
screamer 0:9c59db1fbc9e 609 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
screamer 0:9c59db1fbc9e 610 {
screamer 0:9c59db1fbc9e 611 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
screamer 0:9c59db1fbc9e 612 }
screamer 0:9c59db1fbc9e 613
screamer 0:9c59db1fbc9e 614
screamer 0:9c59db1fbc9e 615 /** \brief Clear Pending Interrupt
screamer 0:9c59db1fbc9e 616
screamer 0:9c59db1fbc9e 617 The function clears the pending bit of an external interrupt.
screamer 0:9c59db1fbc9e 618
screamer 0:9c59db1fbc9e 619 \param [in] IRQn External interrupt number. Value cannot be negative.
screamer 0:9c59db1fbc9e 620 */
screamer 0:9c59db1fbc9e 621 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
screamer 0:9c59db1fbc9e 622 {
screamer 0:9c59db1fbc9e 623 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
screamer 0:9c59db1fbc9e 624 }
screamer 0:9c59db1fbc9e 625
screamer 0:9c59db1fbc9e 626
screamer 0:9c59db1fbc9e 627 /** \brief Set Interrupt Priority
screamer 0:9c59db1fbc9e 628
screamer 0:9c59db1fbc9e 629 The function sets the priority of an interrupt.
screamer 0:9c59db1fbc9e 630
screamer 0:9c59db1fbc9e 631 \note The priority cannot be set for every core interrupt.
screamer 0:9c59db1fbc9e 632
screamer 0:9c59db1fbc9e 633 \param [in] IRQn Interrupt number.
screamer 0:9c59db1fbc9e 634 \param [in] priority Priority to set.
screamer 0:9c59db1fbc9e 635 */
screamer 0:9c59db1fbc9e 636 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
screamer 0:9c59db1fbc9e 637 {
screamer 0:9c59db1fbc9e 638 if((int32_t)(IRQn) < 0) {
screamer 0:9c59db1fbc9e 639 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
screamer 0:9c59db1fbc9e 640 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
screamer 0:9c59db1fbc9e 641 }
screamer 0:9c59db1fbc9e 642 else {
screamer 0:9c59db1fbc9e 643 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
screamer 0:9c59db1fbc9e 644 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
screamer 0:9c59db1fbc9e 645 }
screamer 0:9c59db1fbc9e 646 }
screamer 0:9c59db1fbc9e 647
screamer 0:9c59db1fbc9e 648
screamer 0:9c59db1fbc9e 649 /** \brief Get Interrupt Priority
screamer 0:9c59db1fbc9e 650
screamer 0:9c59db1fbc9e 651 The function reads the priority of an interrupt. The interrupt
screamer 0:9c59db1fbc9e 652 number can be positive to specify an external (device specific)
screamer 0:9c59db1fbc9e 653 interrupt, or negative to specify an internal (core) interrupt.
screamer 0:9c59db1fbc9e 654
screamer 0:9c59db1fbc9e 655
screamer 0:9c59db1fbc9e 656 \param [in] IRQn Interrupt number.
screamer 0:9c59db1fbc9e 657 \return Interrupt Priority. Value is aligned automatically to the implemented
screamer 0:9c59db1fbc9e 658 priority bits of the microcontroller.
screamer 0:9c59db1fbc9e 659 */
screamer 0:9c59db1fbc9e 660 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
screamer 0:9c59db1fbc9e 661 {
screamer 0:9c59db1fbc9e 662
screamer 0:9c59db1fbc9e 663 if((int32_t)(IRQn) < 0) {
screamer 0:9c59db1fbc9e 664 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
screamer 0:9c59db1fbc9e 665 }
screamer 0:9c59db1fbc9e 666 else {
screamer 0:9c59db1fbc9e 667 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
screamer 0:9c59db1fbc9e 668 }
screamer 0:9c59db1fbc9e 669 }
screamer 0:9c59db1fbc9e 670
screamer 0:9c59db1fbc9e 671
screamer 0:9c59db1fbc9e 672 /** \brief System Reset
screamer 0:9c59db1fbc9e 673
screamer 0:9c59db1fbc9e 674 The function initiates a system reset request to reset the MCU.
screamer 0:9c59db1fbc9e 675 */
screamer 0:9c59db1fbc9e 676 __STATIC_INLINE void NVIC_SystemReset(void)
screamer 0:9c59db1fbc9e 677 {
screamer 0:9c59db1fbc9e 678 __DSB(); /* Ensure all outstanding memory accesses included
screamer 0:9c59db1fbc9e 679 buffered write are completed before reset */
screamer 0:9c59db1fbc9e 680 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
screamer 0:9c59db1fbc9e 681 SCB_AIRCR_SYSRESETREQ_Msk);
screamer 0:9c59db1fbc9e 682 __DSB(); /* Ensure completion of memory access */
screamer 0:9c59db1fbc9e 683 while(1) { __NOP(); } /* wait until reset */
screamer 0:9c59db1fbc9e 684 }
screamer 0:9c59db1fbc9e 685
screamer 0:9c59db1fbc9e 686 /*@} end of CMSIS_Core_NVICFunctions */
screamer 0:9c59db1fbc9e 687
screamer 0:9c59db1fbc9e 688
screamer 0:9c59db1fbc9e 689
screamer 0:9c59db1fbc9e 690 /* ################################## SysTick function ############################################ */
screamer 0:9c59db1fbc9e 691 /** \ingroup CMSIS_Core_FunctionInterface
screamer 0:9c59db1fbc9e 692 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
screamer 0:9c59db1fbc9e 693 \brief Functions that configure the System.
screamer 0:9c59db1fbc9e 694 @{
screamer 0:9c59db1fbc9e 695 */
screamer 0:9c59db1fbc9e 696
screamer 0:9c59db1fbc9e 697 #if (__Vendor_SysTickConfig == 0)
screamer 0:9c59db1fbc9e 698
screamer 0:9c59db1fbc9e 699 /** \brief System Tick Configuration
screamer 0:9c59db1fbc9e 700
screamer 0:9c59db1fbc9e 701 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
screamer 0:9c59db1fbc9e 702 Counter is in free running mode to generate periodic interrupts.
screamer 0:9c59db1fbc9e 703
screamer 0:9c59db1fbc9e 704 \param [in] ticks Number of ticks between two interrupts.
screamer 0:9c59db1fbc9e 705
screamer 0:9c59db1fbc9e 706 \return 0 Function succeeded.
screamer 0:9c59db1fbc9e 707 \return 1 Function failed.
screamer 0:9c59db1fbc9e 708
screamer 0:9c59db1fbc9e 709 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
screamer 0:9c59db1fbc9e 710 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
screamer 0:9c59db1fbc9e 711 must contain a vendor-specific implementation of this function.
screamer 0:9c59db1fbc9e 712
screamer 0:9c59db1fbc9e 713 */
screamer 0:9c59db1fbc9e 714 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
screamer 0:9c59db1fbc9e 715 {
screamer 0:9c59db1fbc9e 716 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
screamer 0:9c59db1fbc9e 717
screamer 0:9c59db1fbc9e 718 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
screamer 0:9c59db1fbc9e 719 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
screamer 0:9c59db1fbc9e 720 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
screamer 0:9c59db1fbc9e 721 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
screamer 0:9c59db1fbc9e 722 SysTick_CTRL_TICKINT_Msk |
screamer 0:9c59db1fbc9e 723 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
screamer 0:9c59db1fbc9e 724 return (0UL); /* Function successful */
screamer 0:9c59db1fbc9e 725 }
screamer 0:9c59db1fbc9e 726
screamer 0:9c59db1fbc9e 727 #endif
screamer 0:9c59db1fbc9e 728
screamer 0:9c59db1fbc9e 729 /*@} end of CMSIS_Core_SysTickFunctions */
screamer 0:9c59db1fbc9e 730
screamer 0:9c59db1fbc9e 731
screamer 0:9c59db1fbc9e 732
screamer 0:9c59db1fbc9e 733
screamer 0:9c59db1fbc9e 734 #ifdef __cplusplus
screamer 0:9c59db1fbc9e 735 }
screamer 0:9c59db1fbc9e 736 #endif
screamer 0:9c59db1fbc9e 737
screamer 0:9c59db1fbc9e 738 #endif /* __CORE_CM0_H_DEPENDANT */
screamer 0:9c59db1fbc9e 739
screamer 0:9c59db1fbc9e 740 #endif /* __CMSIS_GENERIC */
screamer 0:9c59db1fbc9e 741