yotsaphat Lertsukon / RFID

5555

MFRC522.cpp@0:4f5ffc06a65b, 2017-12-11 (annotated)

Committer:
59340500048
Date:
Mon Dec 11 15:27:03 2017 +0000
Revision:
0:4f5ffc06a65b
eiei

Who changed what in which revision?

UserRevisionLine numberNew contents of line
59340500048 0:4f5ffc06a65b 1 /*
59340500048 0:4f5ffc06a65b 2 * MFRC522.cpp - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI W AND R BY COOQROBOT.
59340500048 0:4f5ffc06a65b 3 * _Please_ see the comments in MFRC522.h - they give useful hints and background.
59340500048 0:4f5ffc06a65b 4 * Released into the public domain.
59340500048 0:4f5ffc06a65b 5 */
59340500048 0:4f5ffc06a65b 6
59340500048 0:4f5ffc06a65b 7 #include "MFRC522.h"
59340500048 0:4f5ffc06a65b 8
59340500048 0:4f5ffc06a65b 9 static const char* const _TypeNamePICC[] =
59340500048 0:4f5ffc06a65b 10 {
59340500048 0:4f5ffc06a65b 11 "Unknown type",
59340500048 0:4f5ffc06a65b 12 "PICC compliant with ISO/IEC 14443-4",
59340500048 0:4f5ffc06a65b 13 "PICC compliant with ISO/IEC 18092 (NFC)",
59340500048 0:4f5ffc06a65b 14 "MIFARE Mini, 320 bytes",
59340500048 0:4f5ffc06a65b 15 "MIFARE 1KB",
59340500048 0:4f5ffc06a65b 16 "MIFARE 4KB",
59340500048 0:4f5ffc06a65b 17 "MIFARE Ultralight or Ultralight C",
59340500048 0:4f5ffc06a65b 18 "MIFARE Plus",
59340500048 0:4f5ffc06a65b 19 "MIFARE TNP3XXX",
59340500048 0:4f5ffc06a65b 20
59340500048 0:4f5ffc06a65b 21 /* not complete UID */
59340500048 0:4f5ffc06a65b 22 "SAK indicates UID is not complete"
59340500048 0:4f5ffc06a65b 23 };
59340500048 0:4f5ffc06a65b 24
59340500048 0:4f5ffc06a65b 25 static const char* const _ErrorMessage[] =
59340500048 0:4f5ffc06a65b 26 {
59340500048 0:4f5ffc06a65b 27 "Unknown error",
59340500048 0:4f5ffc06a65b 28 "Success",
59340500048 0:4f5ffc06a65b 29 "Error in communication",
59340500048 0:4f5ffc06a65b 30 "Collision detected",
59340500048 0:4f5ffc06a65b 31 "Timeout in communication",
59340500048 0:4f5ffc06a65b 32 "A buffer is not big enough",
59340500048 0:4f5ffc06a65b 33 "Internal error in the code, should not happen",
59340500048 0:4f5ffc06a65b 34 "Invalid argument",
59340500048 0:4f5ffc06a65b 35 "The CRC_A does not match",
59340500048 0:4f5ffc06a65b 36 "A MIFARE PICC responded with NAK"
59340500048 0:4f5ffc06a65b 37 };
59340500048 0:4f5ffc06a65b 38
59340500048 0:4f5ffc06a65b 39 #define MFRC522_MaxPICCs (sizeof(_TypeNamePICC)/sizeof(_TypeNamePICC[0]))
59340500048 0:4f5ffc06a65b 40 #define MFRC522_MaxError (sizeof(_ErrorMessage)/sizeof(_ErrorMessage[0]))
59340500048 0:4f5ffc06a65b 41
59340500048 0:4f5ffc06a65b 42 /////////////////////////////////////////////////////////////////////////////////////
59340500048 0:4f5ffc06a65b 43 // Functions for setting up the driver
59340500048 0:4f5ffc06a65b 44 /////////////////////////////////////////////////////////////////////////////////////
59340500048 0:4f5ffc06a65b 45
59340500048 0:4f5ffc06a65b 46 /**
59340500048 0:4f5ffc06a65b 47 * Constructor.
59340500048 0:4f5ffc06a65b 48 * Prepares the output pins.
59340500048 0:4f5ffc06a65b 49 */
59340500048 0:4f5ffc06a65b 50 MFRC522::MFRC522(PinName mosi,
59340500048 0:4f5ffc06a65b 51 PinName miso,
59340500048 0:4f5ffc06a65b 52 PinName sclk,
59340500048 0:4f5ffc06a65b 53 PinName cs,
59340500048 0:4f5ffc06a65b 54 PinName reset) : m_SPI(mosi, miso, sclk), m_CS(cs), m_RESET(reset)
59340500048 0:4f5ffc06a65b 55 {
59340500048 0:4f5ffc06a65b 56 /* Configure SPI bus */
59340500048 0:4f5ffc06a65b 57 m_SPI.format(8, 0);
59340500048 0:4f5ffc06a65b 58 m_SPI.frequency(8000000);
59340500048 0:4f5ffc06a65b 59
59340500048 0:4f5ffc06a65b 60 /* Release SPI-CS pin */
59340500048 0:4f5ffc06a65b 61 m_CS = 1;
59340500048 0:4f5ffc06a65b 62
59340500048 0:4f5ffc06a65b 63 /* Release RESET pin */
59340500048 0:4f5ffc06a65b 64 m_RESET = 1;
59340500048 0:4f5ffc06a65b 65 } // End constructor
59340500048 0:4f5ffc06a65b 66
59340500048 0:4f5ffc06a65b 67
59340500048 0:4f5ffc06a65b 68 /**
59340500048 0:4f5ffc06a65b 69 * Destructor.
59340500048 0:4f5ffc06a65b 70 */
59340500048 0:4f5ffc06a65b 71 MFRC522::~MFRC522()
59340500048 0:4f5ffc06a65b 72 {
59340500048 0:4f5ffc06a65b 73
59340500048 0:4f5ffc06a65b 74 }
59340500048 0:4f5ffc06a65b 75
59340500048 0:4f5ffc06a65b 76
59340500048 0:4f5ffc06a65b 77 /////////////////////////////////////////////////////////////////////////////////////
59340500048 0:4f5ffc06a65b 78 // Basic interface functions for communicating with the MFRC522
59340500048 0:4f5ffc06a65b 79 /////////////////////////////////////////////////////////////////////////////////////
59340500048 0:4f5ffc06a65b 80
59340500048 0:4f5ffc06a65b 81 /**
59340500048 0:4f5ffc06a65b 82 * Writes a byte to the specified register in the MFRC522 chip.
59340500048 0:4f5ffc06a65b 83 * The interface is described in the datasheet section 8.1.2.
59340500048 0:4f5ffc06a65b 84 */
59340500048 0:4f5ffc06a65b 85 void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t value)
59340500048 0:4f5ffc06a65b 86 {
59340500048 0:4f5ffc06a65b 87 m_CS = 0; /* Select SPI Chip MFRC522 */
59340500048 0:4f5ffc06a65b 88
59340500048 0:4f5ffc06a65b 89 // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
59340500048 0:4f5ffc06a65b 90 (void) m_SPI.write(reg & 0x7E);
59340500048 0:4f5ffc06a65b 91 (void) m_SPI.write(value);
59340500048 0:4f5ffc06a65b 92
59340500048 0:4f5ffc06a65b 93 m_CS = 1; /* Release SPI Chip MFRC522 */
59340500048 0:4f5ffc06a65b 94 } // End PCD_WriteRegister()
59340500048 0:4f5ffc06a65b 95
59340500048 0:4f5ffc06a65b 96 /**
59340500048 0:4f5ffc06a65b 97 * Writes a number of bytes to the specified register in the MFRC522 chip.
59340500048 0:4f5ffc06a65b 98 * The interface is described in the datasheet section 8.1.2.
59340500048 0:4f5ffc06a65b 99 */
59340500048 0:4f5ffc06a65b 100 void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t count, uint8_t *values)
59340500048 0:4f5ffc06a65b 101 {
59340500048 0:4f5ffc06a65b 102 m_CS = 0; /* Select SPI Chip MFRC522 */
59340500048 0:4f5ffc06a65b 103
59340500048 0:4f5ffc06a65b 104 // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
59340500048 0:4f5ffc06a65b 105 (void) m_SPI.write(reg & 0x7E);
59340500048 0:4f5ffc06a65b 106 for (uint8_t index = 0; index < count; index++)
59340500048 0:4f5ffc06a65b 107 {
59340500048 0:4f5ffc06a65b 108 (void) m_SPI.write(values[index]);
59340500048 0:4f5ffc06a65b 109 }
59340500048 0:4f5ffc06a65b 110
59340500048 0:4f5ffc06a65b 111 m_CS = 1; /* Release SPI Chip MFRC522 */
59340500048 0:4f5ffc06a65b 112 } // End PCD_WriteRegister()
59340500048 0:4f5ffc06a65b 113
59340500048 0:4f5ffc06a65b 114 /**
59340500048 0:4f5ffc06a65b 115 * Reads a byte from the specified register in the MFRC522 chip.
59340500048 0:4f5ffc06a65b 116 * The interface is described in the datasheet section 8.1.2.
59340500048 0:4f5ffc06a65b 117 */
59340500048 0:4f5ffc06a65b 118 uint8_t MFRC522::PCD_ReadRegister(uint8_t reg)
59340500048 0:4f5ffc06a65b 119 {
59340500048 0:4f5ffc06a65b 120 uint8_t value;
59340500048 0:4f5ffc06a65b 121 m_CS = 0; /* Select SPI Chip MFRC522 */
59340500048 0:4f5ffc06a65b 122
59340500048 0:4f5ffc06a65b 123 // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
59340500048 0:4f5ffc06a65b 124 (void) m_SPI.write(0x80 | reg);
59340500048 0:4f5ffc06a65b 125
59340500048 0:4f5ffc06a65b 126 // Read the value back. Send 0 to stop reading.
59340500048 0:4f5ffc06a65b 127 value = m_SPI.write(0);
59340500048 0:4f5ffc06a65b 128
59340500048 0:4f5ffc06a65b 129 m_CS = 1; /* Release SPI Chip MFRC522 */
59340500048 0:4f5ffc06a65b 130
59340500048 0:4f5ffc06a65b 131 return value;
59340500048 0:4f5ffc06a65b 132 } // End PCD_ReadRegister()
59340500048 0:4f5ffc06a65b 133
59340500048 0:4f5ffc06a65b 134 /**
59340500048 0:4f5ffc06a65b 135 * Reads a number of bytes from the specified register in the MFRC522 chip.
59340500048 0:4f5ffc06a65b 136 * The interface is described in the datasheet section 8.1.2.
59340500048 0:4f5ffc06a65b 137 */
59340500048 0:4f5ffc06a65b 138 void MFRC522::PCD_ReadRegister(uint8_t reg, uint8_t count, uint8_t *values, uint8_t rxAlign)
59340500048 0:4f5ffc06a65b 139 {
59340500048 0:4f5ffc06a65b 140 if (count == 0) { return; }
59340500048 0:4f5ffc06a65b 141
59340500048 0:4f5ffc06a65b 142 uint8_t address = 0x80 | reg; // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
59340500048 0:4f5ffc06a65b 143 uint8_t index = 0; // Index in values array.
59340500048 0:4f5ffc06a65b 144
59340500048 0:4f5ffc06a65b 145 m_CS = 0; /* Select SPI Chip MFRC522 */
59340500048 0:4f5ffc06a65b 146 count--; // One read is performed outside of the loop
59340500048 0:4f5ffc06a65b 147 (void) m_SPI.write(address); // Tell MFRC522 which address we want to read
59340500048 0:4f5ffc06a65b 148
59340500048 0:4f5ffc06a65b 149 while (index < count)
59340500048 0:4f5ffc06a65b 150 {
59340500048 0:4f5ffc06a65b 151 if ((index == 0) && rxAlign) // Only update bit positions rxAlign..7 in values[0]
59340500048 0:4f5ffc06a65b 152 {
59340500048 0:4f5ffc06a65b 153 // Create bit mask for bit positions rxAlign..7
59340500048 0:4f5ffc06a65b 154 uint8_t mask = 0;
59340500048 0:4f5ffc06a65b 155 for (uint8_t i = rxAlign; i <= 7; i++)
59340500048 0:4f5ffc06a65b 156 {
59340500048 0:4f5ffc06a65b 157 mask |= (1 << i);
59340500048 0:4f5ffc06a65b 158 }
59340500048 0:4f5ffc06a65b 159
59340500048 0:4f5ffc06a65b 160 // Read value and tell that we want to read the same address again.
59340500048 0:4f5ffc06a65b 161 uint8_t value = m_SPI.write(address);
59340500048 0:4f5ffc06a65b 162
59340500048 0:4f5ffc06a65b 163 // Apply mask to both current value of values[0] and the new data in value.
59340500048 0:4f5ffc06a65b 164 values[0] = (values[index] & ~mask) | (value & mask);
59340500048 0:4f5ffc06a65b 165 }
59340500048 0:4f5ffc06a65b 166 else
59340500048 0:4f5ffc06a65b 167 {
59340500048 0:4f5ffc06a65b 168 // Read value and tell that we want to read the same address again.
59340500048 0:4f5ffc06a65b 169 values[index] = m_SPI.write(address);
59340500048 0:4f5ffc06a65b 170 }
59340500048 0:4f5ffc06a65b 171
59340500048 0:4f5ffc06a65b 172 index++;
59340500048 0:4f5ffc06a65b 173 }
59340500048 0:4f5ffc06a65b 174
59340500048 0:4f5ffc06a65b 175 values[index] = m_SPI.write(0); // Read the final byte. Send 0 to stop reading.
59340500048 0:4f5ffc06a65b 176
59340500048 0:4f5ffc06a65b 177 m_CS = 1; /* Release SPI Chip MFRC522 */
59340500048 0:4f5ffc06a65b 178 } // End PCD_ReadRegister()
59340500048 0:4f5ffc06a65b 179
59340500048 0:4f5ffc06a65b 180 /**
59340500048 0:4f5ffc06a65b 181 * Sets the bits given in mask in register reg.
59340500048 0:4f5ffc06a65b 182 */
59340500048 0:4f5ffc06a65b 183 void MFRC522::PCD_SetRegisterBits(uint8_t reg, uint8_t mask)
59340500048 0:4f5ffc06a65b 184 {
59340500048 0:4f5ffc06a65b 185 uint8_t tmp = PCD_ReadRegister(reg);
59340500048 0:4f5ffc06a65b 186 PCD_WriteRegister(reg, tmp | mask); // set bit mask
59340500048 0:4f5ffc06a65b 187 } // End PCD_SetRegisterBitMask()
59340500048 0:4f5ffc06a65b 188
59340500048 0:4f5ffc06a65b 189 /**
59340500048 0:4f5ffc06a65b 190 * Clears the bits given in mask from register reg.
59340500048 0:4f5ffc06a65b 191 */
59340500048 0:4f5ffc06a65b 192 void MFRC522::PCD_ClrRegisterBits(uint8_t reg, uint8_t mask)
59340500048 0:4f5ffc06a65b 193 {
59340500048 0:4f5ffc06a65b 194 uint8_t tmp = PCD_ReadRegister(reg);
59340500048 0:4f5ffc06a65b 195 PCD_WriteRegister(reg, tmp & (~mask)); // clear bit mask
59340500048 0:4f5ffc06a65b 196 } // End PCD_ClearRegisterBitMask()
59340500048 0:4f5ffc06a65b 197
59340500048 0:4f5ffc06a65b 198
59340500048 0:4f5ffc06a65b 199 /**
59340500048 0:4f5ffc06a65b 200 * Use the CRC coprocessor in the MFRC522 to calculate a CRC_A.
59340500048 0:4f5ffc06a65b 201 */
59340500048 0:4f5ffc06a65b 202 uint8_t MFRC522::PCD_CalculateCRC(uint8_t *data, uint8_t length, uint8_t *result)
59340500048 0:4f5ffc06a65b 203 {
59340500048 0:4f5ffc06a65b 204 PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
59340500048 0:4f5ffc06a65b 205 PCD_WriteRegister(DivIrqReg, 0x04); // Clear the CRCIRq interrupt request bit
59340500048 0:4f5ffc06a65b 206 PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
59340500048 0:4f5ffc06a65b 207 PCD_WriteRegister(FIFODataReg, length, data); // Write data to the FIFO
59340500048 0:4f5ffc06a65b 208 PCD_WriteRegister(CommandReg, PCD_CalcCRC); // Start the calculation
59340500048 0:4f5ffc06a65b 209
59340500048 0:4f5ffc06a65b 210 // Wait for the CRC calculation to complete. Each iteration of the while-loop takes 17.73us.
59340500048 0:4f5ffc06a65b 211 uint16_t i = 5000;
59340500048 0:4f5ffc06a65b 212 uint8_t n;
59340500048 0:4f5ffc06a65b 213 while (1)
59340500048 0:4f5ffc06a65b 214 {
59340500048 0:4f5ffc06a65b 215 n = PCD_ReadRegister(DivIrqReg); // DivIrqReg[7..0] bits are: Set2 reserved reserved MfinActIRq reserved CRCIRq reserved reserved
59340500048 0:4f5ffc06a65b 216 if (n & 0x04)
59340500048 0:4f5ffc06a65b 217 {
59340500048 0:4f5ffc06a65b 218 // CRCIRq bit set - calculation done
59340500048 0:4f5ffc06a65b 219 break;
59340500048 0:4f5ffc06a65b 220 }
59340500048 0:4f5ffc06a65b 221
59340500048 0:4f5ffc06a65b 222 if (--i == 0)
59340500048 0:4f5ffc06a65b 223 {
59340500048 0:4f5ffc06a65b 224 // The emergency break. We will eventually terminate on this one after 89ms.
59340500048 0:4f5ffc06a65b 225 // Communication with the MFRC522 might be down.
59340500048 0:4f5ffc06a65b 226 return STATUS_TIMEOUT;
59340500048 0:4f5ffc06a65b 227 }
59340500048 0:4f5ffc06a65b 228 }
59340500048 0:4f5ffc06a65b 229
59340500048 0:4f5ffc06a65b 230 // Stop calculating CRC for new content in the FIFO.
59340500048 0:4f5ffc06a65b 231 PCD_WriteRegister(CommandReg, PCD_Idle);
59340500048 0:4f5ffc06a65b 232
59340500048 0:4f5ffc06a65b 233 // Transfer the result from the registers to the result buffer
59340500048 0:4f5ffc06a65b 234 result[0] = PCD_ReadRegister(CRCResultRegL);
59340500048 0:4f5ffc06a65b 235 result[1] = PCD_ReadRegister(CRCResultRegH);
59340500048 0:4f5ffc06a65b 236 return STATUS_OK;
59340500048 0:4f5ffc06a65b 237 } // End PCD_CalculateCRC()
59340500048 0:4f5ffc06a65b 238
59340500048 0:4f5ffc06a65b 239
59340500048 0:4f5ffc06a65b 240 /////////////////////////////////////////////////////////////////////////////////////
59340500048 0:4f5ffc06a65b 241 // Functions for manipulating the MFRC522
59340500048 0:4f5ffc06a65b 242 /////////////////////////////////////////////////////////////////////////////////////
59340500048 0:4f5ffc06a65b 243
59340500048 0:4f5ffc06a65b 244 /**
59340500048 0:4f5ffc06a65b 245 * Initializes the MFRC522 chip.
59340500048 0:4f5ffc06a65b 246 */
59340500048 0:4f5ffc06a65b 247 void MFRC522::PCD_Init()
59340500048 0:4f5ffc06a65b 248 {
59340500048 0:4f5ffc06a65b 249 /* Reset MFRC522 */
59340500048 0:4f5ffc06a65b 250 m_RESET = 0;
59340500048 0:4f5ffc06a65b 251 wait_ms(10);
59340500048 0:4f5ffc06a65b 252 m_RESET = 1;
59340500048 0:4f5ffc06a65b 253
59340500048 0:4f5ffc06a65b 254 // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms.
59340500048 0:4f5ffc06a65b 255 wait_ms(50);
59340500048 0:4f5ffc06a65b 256
59340500048 0:4f5ffc06a65b 257 // When communicating with a PICC we need a timeout if something goes wrong.
59340500048 0:4f5ffc06a65b 258 // f_timer = 13.56 MHz / (2*TPreScaler+1) where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo].
59340500048 0:4f5ffc06a65b 259 // TPrescaler_Hi are the four low bits in TModeReg. TPrescaler_Lo is TPrescalerReg.
59340500048 0:4f5ffc06a65b 260 PCD_WriteRegister(TModeReg, 0x80); // TAuto=1; timer starts automatically at the end of the transmission in all communication modes at all speeds
59340500048 0:4f5ffc06a65b 261 PCD_WriteRegister(TPrescalerReg, 0xA9); // TPreScaler = TModeReg[3..0]:TPrescalerReg, ie 0x0A9 = 169 => f_timer=40kHz, ie a timer period of 25us.
59340500048 0:4f5ffc06a65b 262 PCD_WriteRegister(TReloadRegH, 0x03); // Reload timer with 0x3E8 = 1000, ie 25ms before timeout.
59340500048 0:4f5ffc06a65b 263 PCD_WriteRegister(TReloadRegL, 0xE8);
59340500048 0:4f5ffc06a65b 264
59340500048 0:4f5ffc06a65b 265 PCD_WriteRegister(TxASKReg, 0x40); // Default 0x00. Force a 100 % ASK modulation independent of the ModGsPReg register setting
59340500048 0:4f5ffc06a65b 266 PCD_WriteRegister(ModeReg, 0x3D); // Default 0x3F. Set the preset value for the CRC coprocessor for the CalcCRC command to 0x6363 (ISO 14443-3 part 6.2.4)
59340500048 0:4f5ffc06a65b 267
59340500048 0:4f5ffc06a65b 268 PCD_WriteRegister(RFCfgReg, (0x07<<4)); // Set Rx Gain to max
59340500048 0:4f5ffc06a65b 269
59340500048 0:4f5ffc06a65b 270 PCD_AntennaOn(); // Enable the antenna driver pins TX1 and TX2 (they were disabled by the reset)
59340500048 0:4f5ffc06a65b 271 } // End PCD_Init()
59340500048 0:4f5ffc06a65b 272
59340500048 0:4f5ffc06a65b 273 /**
59340500048 0:4f5ffc06a65b 274 * Performs a soft reset on the MFRC522 chip and waits for it to be ready again.
59340500048 0:4f5ffc06a65b 275 */
59340500048 0:4f5ffc06a65b 276 void MFRC522::PCD_Reset()
59340500048 0:4f5ffc06a65b 277 {
59340500048 0:4f5ffc06a65b 278 PCD_WriteRegister(CommandReg, PCD_SoftReset); // Issue the SoftReset command.
59340500048 0:4f5ffc06a65b 279 // The datasheet does not mention how long the SoftRest command takes to complete.
59340500048 0:4f5ffc06a65b 280 // But the MFRC522 might have been in soft power-down mode (triggered by bit 4 of CommandReg)
59340500048 0:4f5ffc06a65b 281 // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms.
59340500048 0:4f5ffc06a65b 282 wait_ms(50);
59340500048 0:4f5ffc06a65b 283
59340500048 0:4f5ffc06a65b 284 // Wait for the PowerDown bit in CommandReg to be cleared
59340500048 0:4f5ffc06a65b 285 while (PCD_ReadRegister(CommandReg) & (1<<4))
59340500048 0:4f5ffc06a65b 286 {
59340500048 0:4f5ffc06a65b 287 // PCD still restarting - unlikely after waiting 50ms, but better safe than sorry.
59340500048 0:4f5ffc06a65b 288 }
59340500048 0:4f5ffc06a65b 289 } // End PCD_Reset()
59340500048 0:4f5ffc06a65b 290
59340500048 0:4f5ffc06a65b 291 /**
59340500048 0:4f5ffc06a65b 292 * Turns the antenna on by enabling pins TX1 and TX2.
59340500048 0:4f5ffc06a65b 293 * After a reset these pins disabled.
59340500048 0:4f5ffc06a65b 294 */
59340500048 0:4f5ffc06a65b 295 void MFRC522::PCD_AntennaOn()
59340500048 0:4f5ffc06a65b 296 {
59340500048 0:4f5ffc06a65b 297 uint8_t value = PCD_ReadRegister(TxControlReg);
59340500048 0:4f5ffc06a65b 298 if ((value & 0x03) != 0x03)
59340500048 0:4f5ffc06a65b 299 {
59340500048 0:4f5ffc06a65b 300 PCD_WriteRegister(TxControlReg, value | 0x03);
59340500048 0:4f5ffc06a65b 301 }
59340500048 0:4f5ffc06a65b 302 } // End PCD_AntennaOn()
59340500048 0:4f5ffc06a65b 303
59340500048 0:4f5ffc06a65b 304 /////////////////////////////////////////////////////////////////////////////////////
59340500048 0:4f5ffc06a65b 305 // Functions for communicating with PICCs
59340500048 0:4f5ffc06a65b 306 /////////////////////////////////////////////////////////////////////////////////////
59340500048 0:4f5ffc06a65b 307
59340500048 0:4f5ffc06a65b 308 /**
59340500048 0:4f5ffc06a65b 309 * Executes the Transceive command.
59340500048 0:4f5ffc06a65b 310 * CRC validation can only be done if backData and backLen are specified.
59340500048 0:4f5ffc06a65b 311 */
59340500048 0:4f5ffc06a65b 312 uint8_t MFRC522::PCD_TransceiveData(uint8_t *sendData,
59340500048 0:4f5ffc06a65b 313 uint8_t sendLen,
59340500048 0:4f5ffc06a65b 314 uint8_t *backData,
59340500048 0:4f5ffc06a65b 315 uint8_t *backLen,
59340500048 0:4f5ffc06a65b 316 uint8_t *validBits,
59340500048 0:4f5ffc06a65b 317 uint8_t rxAlign,
59340500048 0:4f5ffc06a65b 318 bool checkCRC)
59340500048 0:4f5ffc06a65b 319 {
59340500048 0:4f5ffc06a65b 320 uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
59340500048 0:4f5ffc06a65b 321 return PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, sendData, sendLen, backData, backLen, validBits, rxAlign, checkCRC);
59340500048 0:4f5ffc06a65b 322 } // End PCD_TransceiveData()
59340500048 0:4f5ffc06a65b 323
59340500048 0:4f5ffc06a65b 324 /**
59340500048 0:4f5ffc06a65b 325 * Transfers data to the MFRC522 FIFO, executes a commend, waits for completion and transfers data back from the FIFO.
59340500048 0:4f5ffc06a65b 326 * CRC validation can only be done if backData and backLen are specified.
59340500048 0:4f5ffc06a65b 327 */
59340500048 0:4f5ffc06a65b 328 uint8_t MFRC522::PCD_CommunicateWithPICC(uint8_t command,
59340500048 0:4f5ffc06a65b 329 uint8_t waitIRq,
59340500048 0:4f5ffc06a65b 330 uint8_t *sendData,
59340500048 0:4f5ffc06a65b 331 uint8_t sendLen,
59340500048 0:4f5ffc06a65b 332 uint8_t *backData,
59340500048 0:4f5ffc06a65b 333 uint8_t *backLen,
59340500048 0:4f5ffc06a65b 334 uint8_t *validBits,
59340500048 0:4f5ffc06a65b 335 uint8_t rxAlign,
59340500048 0:4f5ffc06a65b 336 bool checkCRC)
59340500048 0:4f5ffc06a65b 337 {
59340500048 0:4f5ffc06a65b 338 uint8_t n, _validBits = 0;
59340500048 0:4f5ffc06a65b 339 uint32_t i;
59340500048 0:4f5ffc06a65b 340
59340500048 0:4f5ffc06a65b 341 // Prepare values for BitFramingReg
59340500048 0:4f5ffc06a65b 342 uint8_t txLastBits = validBits ? *validBits : 0;
59340500048 0:4f5ffc06a65b 343 uint8_t bitFraming = (rxAlign << 4) + txLastBits; // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
59340500048 0:4f5ffc06a65b 344
59340500048 0:4f5ffc06a65b 345 PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
59340500048 0:4f5ffc06a65b 346 PCD_WriteRegister(ComIrqReg, 0x7F); // Clear all seven interrupt request bits
59340500048 0:4f5ffc06a65b 347 PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
59340500048 0:4f5ffc06a65b 348 PCD_WriteRegister(FIFODataReg, sendLen, sendData); // Write sendData to the FIFO
59340500048 0:4f5ffc06a65b 349 PCD_WriteRegister(BitFramingReg, bitFraming); // Bit adjustments
59340500048 0:4f5ffc06a65b 350 PCD_WriteRegister(CommandReg, command); // Execute the command
59340500048 0:4f5ffc06a65b 351 if (command == PCD_Transceive)
59340500048 0:4f5ffc06a65b 352 {
59340500048 0:4f5ffc06a65b 353 PCD_SetRegisterBits(BitFramingReg, 0x80); // StartSend=1, transmission of data starts
59340500048 0:4f5ffc06a65b 354 }
59340500048 0:4f5ffc06a65b 355
59340500048 0:4f5ffc06a65b 356 // Wait for the command to complete.
59340500048 0:4f5ffc06a65b 357 // In PCD_Init() we set the TAuto flag in TModeReg. This means the timer automatically starts when the PCD stops transmitting.
59340500048 0:4f5ffc06a65b 358 // Each iteration of the do-while-loop takes 17.86us.
59340500048 0:4f5ffc06a65b 359 i = 2000;
59340500048 0:4f5ffc06a65b 360 while (1)
59340500048 0:4f5ffc06a65b 361 {
59340500048 0:4f5ffc06a65b 362 n = PCD_ReadRegister(ComIrqReg); // ComIrqReg[7..0] bits are: Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq
59340500048 0:4f5ffc06a65b 363 if (n & waitIRq)
59340500048 0:4f5ffc06a65b 364 { // One of the interrupts that signal success has been set.
59340500048 0:4f5ffc06a65b 365 break;
59340500048 0:4f5ffc06a65b 366 }
59340500048 0:4f5ffc06a65b 367
59340500048 0:4f5ffc06a65b 368 if (n & 0x01)
59340500048 0:4f5ffc06a65b 369 { // Timer interrupt - nothing received in 25ms
59340500048 0:4f5ffc06a65b 370 return STATUS_TIMEOUT;
59340500048 0:4f5ffc06a65b 371 }
59340500048 0:4f5ffc06a65b 372
59340500048 0:4f5ffc06a65b 373 if (--i == 0)
59340500048 0:4f5ffc06a65b 374 { // The emergency break. If all other condions fail we will eventually terminate on this one after 35.7ms. Communication with the MFRC522 might be down.
59340500048 0:4f5ffc06a65b 375 return STATUS_TIMEOUT;
59340500048 0:4f5ffc06a65b 376 }
59340500048 0:4f5ffc06a65b 377 }
59340500048 0:4f5ffc06a65b 378
59340500048 0:4f5ffc06a65b 379 // Stop now if any errors except collisions were detected.
59340500048 0:4f5ffc06a65b 380 uint8_t errorRegValue = PCD_ReadRegister(ErrorReg); // ErrorReg[7..0] bits are: WrErr TempErr reserved BufferOvfl CollErr CRCErr ParityErr ProtocolErr
59340500048 0:4f5ffc06a65b 381 if (errorRegValue & 0x13)
59340500048 0:4f5ffc06a65b 382 { // BufferOvfl ParityErr ProtocolErr
59340500048 0:4f5ffc06a65b 383 return STATUS_ERROR;
59340500048 0:4f5ffc06a65b 384 }
59340500048 0:4f5ffc06a65b 385
59340500048 0:4f5ffc06a65b 386 // If the caller wants data back, get it from the MFRC522.
59340500048 0:4f5ffc06a65b 387 if (backData && backLen)
59340500048 0:4f5ffc06a65b 388 {
59340500048 0:4f5ffc06a65b 389 n = PCD_ReadRegister(FIFOLevelReg); // Number of bytes in the FIFO
59340500048 0:4f5ffc06a65b 390 if (n > *backLen)
59340500048 0:4f5ffc06a65b 391 {
59340500048 0:4f5ffc06a65b 392 return STATUS_NO_ROOM;
59340500048 0:4f5ffc06a65b 393 }
59340500048 0:4f5ffc06a65b 394
59340500048 0:4f5ffc06a65b 395 *backLen = n; // Number of bytes returned
59340500048 0:4f5ffc06a65b 396 PCD_ReadRegister(FIFODataReg, n, backData, rxAlign); // Get received data from FIFO
59340500048 0:4f5ffc06a65b 397 _validBits = PCD_ReadRegister(ControlReg) & 0x07; // RxLastBits[2:0] indicates the number of valid bits in the last received byte. If this value is 000b, the whole byte is valid.
59340500048 0:4f5ffc06a65b 398 if (validBits)
59340500048 0:4f5ffc06a65b 399 {
59340500048 0:4f5ffc06a65b 400 *validBits = _validBits;
59340500048 0:4f5ffc06a65b 401 }
59340500048 0:4f5ffc06a65b 402 }
59340500048 0:4f5ffc06a65b 403
59340500048 0:4f5ffc06a65b 404 // Tell about collisions
59340500048 0:4f5ffc06a65b 405 if (errorRegValue & 0x08)
59340500048 0:4f5ffc06a65b 406 { // CollErr
59340500048 0:4f5ffc06a65b 407 return STATUS_COLLISION;
59340500048 0:4f5ffc06a65b 408 }
59340500048 0:4f5ffc06a65b 409
59340500048 0:4f5ffc06a65b 410 // Perform CRC_A validation if requested.
59340500048 0:4f5ffc06a65b 411 if (backData && backLen && checkCRC)
59340500048 0:4f5ffc06a65b 412 {
59340500048 0:4f5ffc06a65b 413 // In this case a MIFARE Classic NAK is not OK.
59340500048 0:4f5ffc06a65b 414 if ((*backLen == 1) && (_validBits == 4))
59340500048 0:4f5ffc06a65b 415 {
59340500048 0:4f5ffc06a65b 416 return STATUS_MIFARE_NACK;
59340500048 0:4f5ffc06a65b 417 }
59340500048 0:4f5ffc06a65b 418
59340500048 0:4f5ffc06a65b 419 // We need at least the CRC_A value and all 8 bits of the last byte must be received.
59340500048 0:4f5ffc06a65b 420 if ((*backLen < 2) || (_validBits != 0))
59340500048 0:4f5ffc06a65b 421 {
59340500048 0:4f5ffc06a65b 422 return STATUS_CRC_WRONG;
59340500048 0:4f5ffc06a65b 423 }
59340500048 0:4f5ffc06a65b 424
59340500048 0:4f5ffc06a65b 425 // Verify CRC_A - do our own calculation and store the control in controlBuffer.
59340500048 0:4f5ffc06a65b 426 uint8_t controlBuffer[2];
59340500048 0:4f5ffc06a65b 427 n = PCD_CalculateCRC(&backData[0], *backLen - 2, &controlBuffer[0]);
59340500048 0:4f5ffc06a65b 428 if (n != STATUS_OK)
59340500048 0:4f5ffc06a65b 429 {
59340500048 0:4f5ffc06a65b 430 return n;
59340500048 0:4f5ffc06a65b 431 }
59340500048 0:4f5ffc06a65b 432
59340500048 0:4f5ffc06a65b 433 if ((backData[*backLen - 2] != controlBuffer[0]) || (backData[*backLen - 1] != controlBuffer[1]))
59340500048 0:4f5ffc06a65b 434 {
59340500048 0:4f5ffc06a65b 435 return STATUS_CRC_WRONG;
59340500048 0:4f5ffc06a65b 436 }
59340500048 0:4f5ffc06a65b 437 }
59340500048 0:4f5ffc06a65b 438
59340500048 0:4f5ffc06a65b 439 return STATUS_OK;
59340500048 0:4f5ffc06a65b 440 } // End PCD_CommunicateWithPICC()
59340500048 0:4f5ffc06a65b 441
59340500048 0:4f5ffc06a65b 442 /*
59340500048 0:4f5ffc06a65b 443 * Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
59340500048 0:4f5ffc06a65b 444 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
59340500048 0:4f5ffc06a65b 445 */
59340500048 0:4f5ffc06a65b 446 uint8_t MFRC522::PICC_RequestA(uint8_t *bufferATQA, uint8_t *bufferSize)
59340500048 0:4f5ffc06a65b 447 {
59340500048 0:4f5ffc06a65b 448 return PICC_REQA_or_WUPA(PICC_CMD_REQA, bufferATQA, bufferSize);
59340500048 0:4f5ffc06a65b 449 } // End PICC_RequestA()
59340500048 0:4f5ffc06a65b 450
59340500048 0:4f5ffc06a65b 451 /**
59340500048 0:4f5ffc06a65b 452 * Transmits a Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
59340500048 0:4f5ffc06a65b 453 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
59340500048 0:4f5ffc06a65b 454 */
59340500048 0:4f5ffc06a65b 455 uint8_t MFRC522::PICC_WakeupA(uint8_t *bufferATQA, uint8_t *bufferSize)
59340500048 0:4f5ffc06a65b 456 {
59340500048 0:4f5ffc06a65b 457 return PICC_REQA_or_WUPA(PICC_CMD_WUPA, bufferATQA, bufferSize);
59340500048 0:4f5ffc06a65b 458 } // End PICC_WakeupA()
59340500048 0:4f5ffc06a65b 459
59340500048 0:4f5ffc06a65b 460 /*
59340500048 0:4f5ffc06a65b 461 * Transmits REQA or WUPA commands.
59340500048 0:4f5ffc06a65b 462 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
59340500048 0:4f5ffc06a65b 463 */
59340500048 0:4f5ffc06a65b 464 uint8_t MFRC522::PICC_REQA_or_WUPA(uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize)
59340500048 0:4f5ffc06a65b 465 {
59340500048 0:4f5ffc06a65b 466 uint8_t validBits;
59340500048 0:4f5ffc06a65b 467 uint8_t status;
59340500048 0:4f5ffc06a65b 468
59340500048 0:4f5ffc06a65b 469 if (bufferATQA == NULL || *bufferSize < 2)
59340500048 0:4f5ffc06a65b 470 { // The ATQA response is 2 bytes long.
59340500048 0:4f5ffc06a65b 471 return STATUS_NO_ROOM;
59340500048 0:4f5ffc06a65b 472 }
59340500048 0:4f5ffc06a65b 473
59340500048 0:4f5ffc06a65b 474 // ValuesAfterColl=1 => Bits received after collision are cleared.
59340500048 0:4f5ffc06a65b 475 PCD_ClrRegisterBits(CollReg, 0x80);
59340500048 0:4f5ffc06a65b 476
59340500048 0:4f5ffc06a65b 477 // For REQA and WUPA we need the short frame format
59340500048 0:4f5ffc06a65b 478 // - transmit only 7 bits of the last (and only) byte. TxLastBits = BitFramingReg[2..0]
59340500048 0:4f5ffc06a65b 479 validBits = 7;
59340500048 0:4f5ffc06a65b 480
59340500048 0:4f5ffc06a65b 481 status = PCD_TransceiveData(&command, 1, bufferATQA, bufferSize, &validBits);
59340500048 0:4f5ffc06a65b 482 if (status != STATUS_OK)
59340500048 0:4f5ffc06a65b 483 {
59340500048 0:4f5ffc06a65b 484 return status;
59340500048 0:4f5ffc06a65b 485 }
59340500048 0:4f5ffc06a65b 486
59340500048 0:4f5ffc06a65b 487 if ((*bufferSize != 2) || (validBits != 0))
59340500048 0:4f5ffc06a65b 488 { // ATQA must be exactly 16 bits.
59340500048 0:4f5ffc06a65b 489 return STATUS_ERROR;
59340500048 0:4f5ffc06a65b 490 }
59340500048 0:4f5ffc06a65b 491
59340500048 0:4f5ffc06a65b 492 return STATUS_OK;
59340500048 0:4f5ffc06a65b 493 } // End PICC_REQA_or_WUPA()
59340500048 0:4f5ffc06a65b 494
59340500048 0:4f5ffc06a65b 495 /*
59340500048 0:4f5ffc06a65b 496 * Transmits SELECT/ANTICOLLISION commands to select a single PICC.
59340500048 0:4f5ffc06a65b 497 */
59340500048 0:4f5ffc06a65b 498 uint8_t MFRC522::PICC_Select(Uid *uid, uint8_t validBits)
59340500048 0:4f5ffc06a65b 499 {
59340500048 0:4f5ffc06a65b 500 bool uidComplete;
59340500048 0:4f5ffc06a65b 501 bool selectDone;
59340500048 0:4f5ffc06a65b 502 bool useCascadeTag;
59340500048 0:4f5ffc06a65b 503 uint8_t cascadeLevel = 1;
59340500048 0:4f5ffc06a65b 504 uint8_t result;
59340500048 0:4f5ffc06a65b 505 uint8_t count;
59340500048 0:4f5ffc06a65b 506 uint8_t index;
59340500048 0:4f5ffc06a65b 507 uint8_t uidIndex; // The first index in uid->uidByte[] that is used in the current Cascade Level.
59340500048 0:4f5ffc06a65b 508 uint8_t currentLevelKnownBits; // The number of known UID bits in the current Cascade Level.
59340500048 0:4f5ffc06a65b 509 uint8_t buffer[9]; // The SELECT/ANTICOLLISION commands uses a 7 byte standard frame + 2 bytes CRC_A
59340500048 0:4f5ffc06a65b 510 uint8_t bufferUsed; // The number of bytes used in the buffer, ie the number of bytes to transfer to the FIFO.
59340500048 0:4f5ffc06a65b 511 uint8_t rxAlign; // Used in BitFramingReg. Defines the bit position for the first bit received.
59340500048 0:4f5ffc06a65b 512 uint8_t txLastBits; // Used in BitFramingReg. The number of valid bits in the last transmitted byte.
59340500048 0:4f5ffc06a65b 513 uint8_t *responseBuffer;
59340500048 0:4f5ffc06a65b 514 uint8_t responseLength;
59340500048 0:4f5ffc06a65b 515
59340500048 0:4f5ffc06a65b 516 // Description of buffer structure:
59340500048 0:4f5ffc06a65b 517 // Byte 0: SEL Indicates the Cascade Level: PICC_CMD_SEL_CL1, PICC_CMD_SEL_CL2 or PICC_CMD_SEL_CL3
59340500048 0:4f5ffc06a65b 518 // Byte 1: NVB Number of Valid Bits (in complete command, not just the UID): High nibble: complete bytes, Low nibble: Extra bits.
59340500048 0:4f5ffc06a65b 519 // Byte 2: UID-data or CT See explanation below. CT means Cascade Tag.
59340500048 0:4f5ffc06a65b 520 // Byte 3: UID-data
59340500048 0:4f5ffc06a65b 521 // Byte 4: UID-data
59340500048 0:4f5ffc06a65b 522 // Byte 5: UID-data
59340500048 0:4f5ffc06a65b 523 // Byte 6: BCC Block Check Character - XOR of bytes 2-5
59340500048 0:4f5ffc06a65b 524 // Byte 7: CRC_A
59340500048 0:4f5ffc06a65b 525 // Byte 8: CRC_A
59340500048 0:4f5ffc06a65b 526 // The BCC and CRC_A is only transmitted if we know all the UID bits of the current Cascade Level.
59340500048 0:4f5ffc06a65b 527 //
59340500048 0:4f5ffc06a65b 528 // Description of bytes 2-5: (Section 6.5.4 of the ISO/IEC 14443-3 draft: UID contents and cascade levels)
59340500048 0:4f5ffc06a65b 529 // UID size Cascade level Byte2 Byte3 Byte4 Byte5
59340500048 0:4f5ffc06a65b 530 // ======== ============= ===== ===== ===== =====
59340500048 0:4f5ffc06a65b 531 // 4 bytes 1 uid0 uid1 uid2 uid3
59340500048 0:4f5ffc06a65b 532 // 7 bytes 1 CT uid0 uid1 uid2
59340500048 0:4f5ffc06a65b 533 // 2 uid3 uid4 uid5 uid6
59340500048 0:4f5ffc06a65b 534 // 10 bytes 1 CT uid0 uid1 uid2
59340500048 0:4f5ffc06a65b 535 // 2 CT uid3 uid4 uid5
59340500048 0:4f5ffc06a65b 536 // 3 uid6 uid7 uid8 uid9
59340500048 0:4f5ffc06a65b 537
59340500048 0:4f5ffc06a65b 538 // Sanity checks
59340500048 0:4f5ffc06a65b 539 if (validBits > 80)
59340500048 0:4f5ffc06a65b 540 {
59340500048 0:4f5ffc06a65b 541 return STATUS_INVALID;
59340500048 0:4f5ffc06a65b 542 }
59340500048 0:4f5ffc06a65b 543
59340500048 0:4f5ffc06a65b 544 // Prepare MFRC522
59340500048 0:4f5ffc06a65b 545 // ValuesAfterColl=1 => Bits received after collision are cleared.
59340500048 0:4f5ffc06a65b 546 PCD_ClrRegisterBits(CollReg, 0x80);
59340500048 0:4f5ffc06a65b 547
59340500048 0:4f5ffc06a65b 548 // Repeat Cascade Level loop until we have a complete UID.
59340500048 0:4f5ffc06a65b 549 uidComplete = false;
59340500048 0:4f5ffc06a65b 550 while ( ! uidComplete)
59340500048 0:4f5ffc06a65b 551 {
59340500048 0:4f5ffc06a65b 552 // Set the Cascade Level in the SEL byte, find out if we need to use the Cascade Tag in byte 2.
59340500048 0:4f5ffc06a65b 553 switch (cascadeLevel)
59340500048 0:4f5ffc06a65b 554 {
59340500048 0:4f5ffc06a65b 555 case 1:
59340500048 0:4f5ffc06a65b 556 buffer[0] = PICC_CMD_SEL_CL1;
59340500048 0:4f5ffc06a65b 557 uidIndex = 0;
59340500048 0:4f5ffc06a65b 558 useCascadeTag = validBits && (uid->size > 4); // When we know that the UID has more than 4 bytes
59340500048 0:4f5ffc06a65b 559 break;
59340500048 0:4f5ffc06a65b 560
59340500048 0:4f5ffc06a65b 561 case 2:
59340500048 0:4f5ffc06a65b 562 buffer[0] = PICC_CMD_SEL_CL2;
59340500048 0:4f5ffc06a65b 563 uidIndex = 3;
59340500048 0:4f5ffc06a65b 564 useCascadeTag = validBits && (uid->size > 7); // When we know that the UID has more than 7 bytes
59340500048 0:4f5ffc06a65b 565 break;
59340500048 0:4f5ffc06a65b 566
59340500048 0:4f5ffc06a65b 567 case 3:
59340500048 0:4f5ffc06a65b 568 buffer[0] = PICC_CMD_SEL_CL3;
59340500048 0:4f5ffc06a65b 569 uidIndex = 6;
59340500048 0:4f5ffc06a65b 570 useCascadeTag = false; // Never used in CL3.
59340500048 0:4f5ffc06a65b 571 break;
59340500048 0:4f5ffc06a65b 572
59340500048 0:4f5ffc06a65b 573 default:
59340500048 0:4f5ffc06a65b 574 return STATUS_INTERNAL_ERROR;
59340500048 0:4f5ffc06a65b 575 //break;
59340500048 0:4f5ffc06a65b 576 }
59340500048 0:4f5ffc06a65b 577
59340500048 0:4f5ffc06a65b 578 // How many UID bits are known in this Cascade Level?
59340500048 0:4f5ffc06a65b 579 if(validBits > (8 * uidIndex))
59340500048 0:4f5ffc06a65b 580 {
59340500048 0:4f5ffc06a65b 581 currentLevelKnownBits = validBits - (8 * uidIndex);
59340500048 0:4f5ffc06a65b 582 }
59340500048 0:4f5ffc06a65b 583 else
59340500048 0:4f5ffc06a65b 584 {
59340500048 0:4f5ffc06a65b 585 currentLevelKnownBits = 0;
59340500048 0:4f5ffc06a65b 586 }
59340500048 0:4f5ffc06a65b 587
59340500048 0:4f5ffc06a65b 588 // Copy the known bits from uid->uidByte[] to buffer[]
59340500048 0:4f5ffc06a65b 589 index = 2; // destination index in buffer[]
59340500048 0:4f5ffc06a65b 590 if (useCascadeTag)
59340500048 0:4f5ffc06a65b 591 {
59340500048 0:4f5ffc06a65b 592 buffer[index++] = PICC_CMD_CT;
59340500048 0:4f5ffc06a65b 593 }
59340500048 0:4f5ffc06a65b 594
59340500048 0:4f5ffc06a65b 595 uint8_t bytesToCopy = currentLevelKnownBits / 8 + (currentLevelKnownBits % 8 ? 1 : 0); // The number of bytes needed to represent the known bits for this level.
59340500048 0:4f5ffc06a65b 596 if (bytesToCopy)
59340500048 0:4f5ffc06a65b 597 {
59340500048 0:4f5ffc06a65b 598 // Max 4 bytes in each Cascade Level. Only 3 left if we use the Cascade Tag
59340500048 0:4f5ffc06a65b 599 uint8_t maxBytes = useCascadeTag ? 3 : 4;
59340500048 0:4f5ffc06a65b 600 if (bytesToCopy > maxBytes)
59340500048 0:4f5ffc06a65b 601 {
59340500048 0:4f5ffc06a65b 602 bytesToCopy = maxBytes;
59340500048 0:4f5ffc06a65b 603 }
59340500048 0:4f5ffc06a65b 604
59340500048 0:4f5ffc06a65b 605 for (count = 0; count < bytesToCopy; count++)
59340500048 0:4f5ffc06a65b 606 {
59340500048 0:4f5ffc06a65b 607 buffer[index++] = uid->uidByte[uidIndex + count];
59340500048 0:4f5ffc06a65b 608 }
59340500048 0:4f5ffc06a65b 609 }
59340500048 0:4f5ffc06a65b 610
59340500048 0:4f5ffc06a65b 611 // Now that the data has been copied we need to include the 8 bits in CT in currentLevelKnownBits
59340500048 0:4f5ffc06a65b 612 if (useCascadeTag)
59340500048 0:4f5ffc06a65b 613 {
59340500048 0:4f5ffc06a65b 614 currentLevelKnownBits += 8;
59340500048 0:4f5ffc06a65b 615 }
59340500048 0:4f5ffc06a65b 616
59340500048 0:4f5ffc06a65b 617 // Repeat anti collision loop until we can transmit all UID bits + BCC and receive a SAK - max 32 iterations.
59340500048 0:4f5ffc06a65b 618 selectDone = false;
59340500048 0:4f5ffc06a65b 619 while ( ! selectDone)
59340500048 0:4f5ffc06a65b 620 {
59340500048 0:4f5ffc06a65b 621 // Find out how many bits and bytes to send and receive.
59340500048 0:4f5ffc06a65b 622 if (currentLevelKnownBits >= 32)
59340500048 0:4f5ffc06a65b 623 { // All UID bits in this Cascade Level are known. This is a SELECT.
59340500048 0:4f5ffc06a65b 624 //Serial.print("SELECT: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
59340500048 0:4f5ffc06a65b 625 buffer[1] = 0x70; // NVB - Number of Valid Bits: Seven whole bytes
59340500048 0:4f5ffc06a65b 626
59340500048 0:4f5ffc06a65b 627 // Calulate BCC - Block Check Character
59340500048 0:4f5ffc06a65b 628 buffer[6] = buffer[2] ^ buffer[3] ^ buffer[4] ^ buffer[5];
59340500048 0:4f5ffc06a65b 629
59340500048 0:4f5ffc06a65b 630 // Calculate CRC_A
59340500048 0:4f5ffc06a65b 631 result = PCD_CalculateCRC(buffer, 7, &buffer[7]);
59340500048 0:4f5ffc06a65b 632 if (result != STATUS_OK)
59340500048 0:4f5ffc06a65b 633 {
59340500048 0:4f5ffc06a65b 634 return result;
59340500048 0:4f5ffc06a65b 635 }
59340500048 0:4f5ffc06a65b 636
59340500048 0:4f5ffc06a65b 637 txLastBits = 0; // 0 => All 8 bits are valid.
59340500048 0:4f5ffc06a65b 638 bufferUsed = 9;
59340500048 0:4f5ffc06a65b 639
59340500048 0:4f5ffc06a65b 640 // Store response in the last 3 bytes of buffer (BCC and CRC_A - not needed after tx)
59340500048 0:4f5ffc06a65b 641 responseBuffer = &buffer[6];
59340500048 0:4f5ffc06a65b 642 responseLength = 3;
59340500048 0:4f5ffc06a65b 643 }
59340500048 0:4f5ffc06a65b 644 else
59340500048 0:4f5ffc06a65b 645 { // This is an ANTICOLLISION.
59340500048 0:4f5ffc06a65b 646 //Serial.print("ANTICOLLISION: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
59340500048 0:4f5ffc06a65b 647 txLastBits = currentLevelKnownBits % 8;
59340500048 0:4f5ffc06a65b 648 count = currentLevelKnownBits / 8; // Number of whole bytes in the UID part.
59340500048 0:4f5ffc06a65b 649 index = 2 + count; // Number of whole bytes: SEL + NVB + UIDs
59340500048 0:4f5ffc06a65b 650 buffer[1] = (index << 4) + txLastBits; // NVB - Number of Valid Bits
59340500048 0:4f5ffc06a65b 651 bufferUsed = index + (txLastBits ? 1 : 0);
59340500048 0:4f5ffc06a65b 652
59340500048 0:4f5ffc06a65b 653 // Store response in the unused part of buffer
59340500048 0:4f5ffc06a65b 654 responseBuffer = &buffer[index];
59340500048 0:4f5ffc06a65b 655 responseLength = sizeof(buffer) - index;
59340500048 0:4f5ffc06a65b 656 }
59340500048 0:4f5ffc06a65b 657
59340500048 0:4f5ffc06a65b 658 // Set bit adjustments
59340500048 0:4f5ffc06a65b 659 rxAlign = txLastBits; // Having a seperate variable is overkill. But it makes the next line easier to read.
59340500048 0:4f5ffc06a65b 660 PCD_WriteRegister(BitFramingReg, (rxAlign << 4) + txLastBits); // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
59340500048 0:4f5ffc06a65b 661
59340500048 0:4f5ffc06a65b 662 // Transmit the buffer and receive the response.
59340500048 0:4f5ffc06a65b 663 result = PCD_TransceiveData(buffer, bufferUsed, responseBuffer, &responseLength, &txLastBits, rxAlign);
59340500048 0:4f5ffc06a65b 664 if (result == STATUS_COLLISION)
59340500048 0:4f5ffc06a65b 665 { // More than one PICC in the field => collision.
59340500048 0:4f5ffc06a65b 666 result = PCD_ReadRegister(CollReg); // CollReg[7..0] bits are: ValuesAfterColl reserved CollPosNotValid CollPos[4:0]
59340500048 0:4f5ffc06a65b 667 if (result & 0x20)
59340500048 0:4f5ffc06a65b 668 { // CollPosNotValid
59340500048 0:4f5ffc06a65b 669 return STATUS_COLLISION; // Without a valid collision position we cannot continue
59340500048 0:4f5ffc06a65b 670 }
59340500048 0:4f5ffc06a65b 671
59340500048 0:4f5ffc06a65b 672 uint8_t collisionPos = result & 0x1F; // Values 0-31, 0 means bit 32.
59340500048 0:4f5ffc06a65b 673 if (collisionPos == 0)
59340500048 0:4f5ffc06a65b 674 {
59340500048 0:4f5ffc06a65b 675 collisionPos = 32;
59340500048 0:4f5ffc06a65b 676 }
59340500048 0:4f5ffc06a65b 677
59340500048 0:4f5ffc06a65b 678 if (collisionPos <= currentLevelKnownBits)
59340500048 0:4f5ffc06a65b 679 { // No progress - should not happen
59340500048 0:4f5ffc06a65b 680 return STATUS_INTERNAL_ERROR;
59340500048 0:4f5ffc06a65b 681 }
59340500048 0:4f5ffc06a65b 682
59340500048 0:4f5ffc06a65b 683 // Choose the PICC with the bit set.
59340500048 0:4f5ffc06a65b 684 currentLevelKnownBits = collisionPos;
59340500048 0:4f5ffc06a65b 685 count = (currentLevelKnownBits - 1) % 8; // The bit to modify
59340500048 0:4f5ffc06a65b 686 index = 1 + (currentLevelKnownBits / 8) + (count ? 1 : 0); // First byte is index 0.
59340500048 0:4f5ffc06a65b 687 buffer[index] |= (1 << count);
59340500048 0:4f5ffc06a65b 688 }
59340500048 0:4f5ffc06a65b 689 else if (result != STATUS_OK)
59340500048 0:4f5ffc06a65b 690 {
59340500048 0:4f5ffc06a65b 691 return result;
59340500048 0:4f5ffc06a65b 692 }
59340500048 0:4f5ffc06a65b 693 else
59340500048 0:4f5ffc06a65b 694 { // STATUS_OK
59340500048 0:4f5ffc06a65b 695 if (currentLevelKnownBits >= 32)
59340500048 0:4f5ffc06a65b 696 { // This was a SELECT.
59340500048 0:4f5ffc06a65b 697 selectDone = true; // No more anticollision
59340500048 0:4f5ffc06a65b 698 // We continue below outside the while.
59340500048 0:4f5ffc06a65b 699 }
59340500048 0:4f5ffc06a65b 700 else
59340500048 0:4f5ffc06a65b 701 { // This was an ANTICOLLISION.
59340500048 0:4f5ffc06a65b 702 // We now have all 32 bits of the UID in this Cascade Level
59340500048 0:4f5ffc06a65b 703 currentLevelKnownBits = 32;
59340500048 0:4f5ffc06a65b 704 // Run loop again to do the SELECT.
59340500048 0:4f5ffc06a65b 705 }
59340500048 0:4f5ffc06a65b 706 }
59340500048 0:4f5ffc06a65b 707 } // End of while ( ! selectDone)
59340500048 0:4f5ffc06a65b 708
59340500048 0:4f5ffc06a65b 709 // We do not check the CBB - it was constructed by us above.
59340500048 0:4f5ffc06a65b 710
59340500048 0:4f5ffc06a65b 711 // Copy the found UID bytes from buffer[] to uid->uidByte[]
59340500048 0:4f5ffc06a65b 712 index = (buffer[2] == PICC_CMD_CT) ? 3 : 2; // source index in buffer[]
59340500048 0:4f5ffc06a65b 713 bytesToCopy = (buffer[2] == PICC_CMD_CT) ? 3 : 4;
59340500048 0:4f5ffc06a65b 714 for (count = 0; count < bytesToCopy; count++)
59340500048 0:4f5ffc06a65b 715 {
59340500048 0:4f5ffc06a65b 716 uid->uidByte[uidIndex + count] = buffer[index++];
59340500048 0:4f5ffc06a65b 717 }
59340500048 0:4f5ffc06a65b 718
59340500048 0:4f5ffc06a65b 719 // Check response SAK (Select Acknowledge)
59340500048 0:4f5ffc06a65b 720 if (responseLength != 3 || txLastBits != 0)
59340500048 0:4f5ffc06a65b 721 { // SAK must be exactly 24 bits (1 byte + CRC_A).
59340500048 0:4f5ffc06a65b 722 return STATUS_ERROR;
59340500048 0:4f5ffc06a65b 723 }
59340500048 0:4f5ffc06a65b 724
59340500048 0:4f5ffc06a65b 725 // Verify CRC_A - do our own calculation and store the control in buffer[2..3] - those bytes are not needed anymore.
59340500048 0:4f5ffc06a65b 726 result = PCD_CalculateCRC(responseBuffer, 1, &buffer[2]);
59340500048 0:4f5ffc06a65b 727 if (result != STATUS_OK)
59340500048 0:4f5ffc06a65b 728 {
59340500048 0:4f5ffc06a65b 729 return result;
59340500048 0:4f5ffc06a65b 730 }
59340500048 0:4f5ffc06a65b 731
59340500048 0:4f5ffc06a65b 732 if ((buffer[2] != responseBuffer[1]) || (buffer[3] != responseBuffer[2]))
59340500048 0:4f5ffc06a65b 733 {
59340500048 0:4f5ffc06a65b 734 return STATUS_CRC_WRONG;
59340500048 0:4f5ffc06a65b 735 }
59340500048 0:4f5ffc06a65b 736
59340500048 0:4f5ffc06a65b 737 if (responseBuffer[0] & 0x04)
59340500048 0:4f5ffc06a65b 738 { // Cascade bit set - UID not complete yes
59340500048 0:4f5ffc06a65b 739 cascadeLevel++;
59340500048 0:4f5ffc06a65b 740 }
59340500048 0:4f5ffc06a65b 741 else
59340500048 0:4f5ffc06a65b 742 {
59340500048 0:4f5ffc06a65b 743 uidComplete = true;
59340500048 0:4f5ffc06a65b 744 uid->sak = responseBuffer[0];
59340500048 0:4f5ffc06a65b 745 }
59340500048 0:4f5ffc06a65b 746 } // End of while ( ! uidComplete)
59340500048 0:4f5ffc06a65b 747
59340500048 0:4f5ffc06a65b 748 // Set correct uid->size
59340500048 0:4f5ffc06a65b 749 uid->size = 3 * cascadeLevel + 1;
59340500048 0:4f5ffc06a65b 750
59340500048 0:4f5ffc06a65b 751 return STATUS_OK;
59340500048 0:4f5ffc06a65b 752 } // End PICC_Select()
59340500048 0:4f5ffc06a65b 753
59340500048 0:4f5ffc06a65b 754 /*
59340500048 0:4f5ffc06a65b 755 * Instructs a PICC in state ACTIVE(*) to go to state HALT.
59340500048 0:4f5ffc06a65b 756 */
59340500048 0:4f5ffc06a65b 757 uint8_t MFRC522::PICC_HaltA()
59340500048 0:4f5ffc06a65b 758 {
59340500048 0:4f5ffc06a65b 759 uint8_t result;
59340500048 0:4f5ffc06a65b 760 uint8_t buffer[4];
59340500048 0:4f5ffc06a65b 761
59340500048 0:4f5ffc06a65b 762 // Build command buffer
59340500048 0:4f5ffc06a65b 763 buffer[0] = PICC_CMD_HLTA;
59340500048 0:4f5ffc06a65b 764 buffer[1] = 0;
59340500048 0:4f5ffc06a65b 765
59340500048 0:4f5ffc06a65b 766 // Calculate CRC_A
59340500048 0:4f5ffc06a65b 767 result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
59340500048 0:4f5ffc06a65b 768 if (result == STATUS_OK)
59340500048 0:4f5ffc06a65b 769 {
59340500048 0:4f5ffc06a65b 770 // Send the command.
59340500048 0:4f5ffc06a65b 771 // The standard says:
59340500048 0:4f5ffc06a65b 772 // If the PICC responds with any modulation during a period of 1 ms after the end of the frame containing the
59340500048 0:4f5ffc06a65b 773 // HLTA command, this response shall be interpreted as 'not acknowledge'.
59340500048 0:4f5ffc06a65b 774 // We interpret that this way: Only STATUS_TIMEOUT is an success.
59340500048 0:4f5ffc06a65b 775 result = PCD_TransceiveData(buffer, sizeof(buffer), NULL, 0);
59340500048 0:4f5ffc06a65b 776 if (result == STATUS_TIMEOUT)
59340500048 0:4f5ffc06a65b 777 {
59340500048 0:4f5ffc06a65b 778 result = STATUS_OK;
59340500048 0:4f5ffc06a65b 779 }
59340500048 0:4f5ffc06a65b 780 else if (result == STATUS_OK)
59340500048 0:4f5ffc06a65b 781 { // That is ironically NOT ok in this case ;-)
59340500048 0:4f5ffc06a65b 782 result = STATUS_ERROR;
59340500048 0:4f5ffc06a65b 783 }
59340500048 0:4f5ffc06a65b 784 }
59340500048 0:4f5ffc06a65b 785
59340500048 0:4f5ffc06a65b 786 return result;
59340500048 0:4f5ffc06a65b 787 } // End PICC_HaltA()
59340500048 0:4f5ffc06a65b 788
59340500048 0:4f5ffc06a65b 789
59340500048 0:4f5ffc06a65b 790 /////////////////////////////////////////////////////////////////////////////////////
59340500048 0:4f5ffc06a65b 791 // Functions for communicating with MIFARE PICCs
59340500048 0:4f5ffc06a65b 792 /////////////////////////////////////////////////////////////////////////////////////
59340500048 0:4f5ffc06a65b 793
59340500048 0:4f5ffc06a65b 794 /*
59340500048 0:4f5ffc06a65b 795 * Executes the MFRC522 MFAuthent command.
59340500048 0:4f5ffc06a65b 796 */
59340500048 0:4f5ffc06a65b 797 uint8_t MFRC522::PCD_Authenticate(uint8_t command, uint8_t blockAddr, MIFARE_Key *key, Uid *uid)
59340500048 0:4f5ffc06a65b 798 {
59340500048 0:4f5ffc06a65b 799 uint8_t i, waitIRq = 0x10; // IdleIRq
59340500048 0:4f5ffc06a65b 800
59340500048 0:4f5ffc06a65b 801 // Build command buffer
59340500048 0:4f5ffc06a65b 802 uint8_t sendData[12];
59340500048 0:4f5ffc06a65b 803 sendData[0] = command;
59340500048 0:4f5ffc06a65b 804 sendData[1] = blockAddr;
59340500048 0:4f5ffc06a65b 805
59340500048 0:4f5ffc06a65b 806 for (i = 0; i < MF_KEY_SIZE; i++)
59340500048 0:4f5ffc06a65b 807 { // 6 key bytes
59340500048 0:4f5ffc06a65b 808 sendData[2+i] = key->keyByte[i];
59340500048 0:4f5ffc06a65b 809 }
59340500048 0:4f5ffc06a65b 810
59340500048 0:4f5ffc06a65b 811 for (i = 0; i < 4; i++)
59340500048 0:4f5ffc06a65b 812 { // The first 4 bytes of the UID
59340500048 0:4f5ffc06a65b 813 sendData[8+i] = uid->uidByte[i];
59340500048 0:4f5ffc06a65b 814 }
59340500048 0:4f5ffc06a65b 815
59340500048 0:4f5ffc06a65b 816 // Start the authentication.
59340500048 0:4f5ffc06a65b 817 return PCD_CommunicateWithPICC(PCD_MFAuthent, waitIRq, &sendData[0], sizeof(sendData));
59340500048 0:4f5ffc06a65b 818 } // End PCD_Authenticate()
59340500048 0:4f5ffc06a65b 819
59340500048 0:4f5ffc06a65b 820 /*
59340500048 0:4f5ffc06a65b 821 * Used to exit the PCD from its authenticated state.
59340500048 0:4f5ffc06a65b 822 * Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start.
59340500048 0:4f5ffc06a65b 823 */
59340500048 0:4f5ffc06a65b 824 void MFRC522::PCD_StopCrypto1()
59340500048 0:4f5ffc06a65b 825 {
59340500048 0:4f5ffc06a65b 826 // Clear MFCrypto1On bit
59340500048 0:4f5ffc06a65b 827 PCD_ClrRegisterBits(Status2Reg, 0x08); // Status2Reg[7..0] bits are: TempSensClear I2CForceHS reserved reserved MFCrypto1On ModemState[2:0]
59340500048 0:4f5ffc06a65b 828 } // End PCD_StopCrypto1()
59340500048 0:4f5ffc06a65b 829
59340500048 0:4f5ffc06a65b 830 /*
59340500048 0:4f5ffc06a65b 831 * Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC.
59340500048 0:4f5ffc06a65b 832 */
59340500048 0:4f5ffc06a65b 833 uint8_t MFRC522::MIFARE_Read(uint8_t blockAddr, uint8_t *buffer, uint8_t *bufferSize)
59340500048 0:4f5ffc06a65b 834 {
59340500048 0:4f5ffc06a65b 835 uint8_t result = STATUS_NO_ROOM;
59340500048 0:4f5ffc06a65b 836
59340500048 0:4f5ffc06a65b 837 // Sanity check
59340500048 0:4f5ffc06a65b 838 if ((buffer == NULL) || (*bufferSize < 18))
59340500048 0:4f5ffc06a65b 839 {
59340500048 0:4f5ffc06a65b 840 return result;
59340500048 0:4f5ffc06a65b 841 }
59340500048 0:4f5ffc06a65b 842
59340500048 0:4f5ffc06a65b 843 // Build command buffer
59340500048 0:4f5ffc06a65b 844 buffer[0] = PICC_CMD_MF_READ;
59340500048 0:4f5ffc06a65b 845 buffer[1] = blockAddr;
59340500048 0:4f5ffc06a65b 846
59340500048 0:4f5ffc06a65b 847 // Calculate CRC_A
59340500048 0:4f5ffc06a65b 848 result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
59340500048 0:4f5ffc06a65b 849 if (result != STATUS_OK)
59340500048 0:4f5ffc06a65b 850 {
59340500048 0:4f5ffc06a65b 851 return result;
59340500048 0:4f5ffc06a65b 852 }
59340500048 0:4f5ffc06a65b 853
59340500048 0:4f5ffc06a65b 854 // Transmit the buffer and receive the response, validate CRC_A.
59340500048 0:4f5ffc06a65b 855 return PCD_TransceiveData(buffer, 4, buffer, bufferSize, NULL, 0, true);
59340500048 0:4f5ffc06a65b 856 } // End MIFARE_Read()
59340500048 0:4f5ffc06a65b 857
59340500048 0:4f5ffc06a65b 858 /*
59340500048 0:4f5ffc06a65b 859 * Writes 16 bytes to the active PICC.
59340500048 0:4f5ffc06a65b 860 */
59340500048 0:4f5ffc06a65b 861 uint8_t MFRC522::MIFARE_Write(uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize)
59340500048 0:4f5ffc06a65b 862 {
59340500048 0:4f5ffc06a65b 863 uint8_t result;
59340500048 0:4f5ffc06a65b 864
59340500048 0:4f5ffc06a65b 865 // Sanity check
59340500048 0:4f5ffc06a65b 866 if (buffer == NULL || bufferSize < 16)
59340500048 0:4f5ffc06a65b 867 {
59340500048 0:4f5ffc06a65b 868 return STATUS_INVALID;
59340500048 0:4f5ffc06a65b 869 }
59340500048 0:4f5ffc06a65b 870
59340500048 0:4f5ffc06a65b 871 // Mifare Classic protocol requires two communications to perform a write.
59340500048 0:4f5ffc06a65b 872 // Step 1: Tell the PICC we want to write to block blockAddr.
59340500048 0:4f5ffc06a65b 873 uint8_t cmdBuffer[2];
59340500048 0:4f5ffc06a65b 874 cmdBuffer[0] = PICC_CMD_MF_WRITE;
59340500048 0:4f5ffc06a65b 875 cmdBuffer[1] = blockAddr;
59340500048 0:4f5ffc06a65b 876 // Adds CRC_A and checks that the response is MF_ACK.
59340500048 0:4f5ffc06a65b 877 result = PCD_MIFARE_Transceive(cmdBuffer, 2);
59340500048 0:4f5ffc06a65b 878 if (result != STATUS_OK)
59340500048 0:4f5ffc06a65b 879 {
59340500048 0:4f5ffc06a65b 880 return result;
59340500048 0:4f5ffc06a65b 881 }
59340500048 0:4f5ffc06a65b 882
59340500048 0:4f5ffc06a65b 883 // Step 2: Transfer the data
59340500048 0:4f5ffc06a65b 884 // Adds CRC_A and checks that the response is MF_ACK.
59340500048 0:4f5ffc06a65b 885 result = PCD_MIFARE_Transceive(buffer, bufferSize);
59340500048 0:4f5ffc06a65b 886 if (result != STATUS_OK)
59340500048 0:4f5ffc06a65b 887 {
59340500048 0:4f5ffc06a65b 888 return result;
59340500048 0:4f5ffc06a65b 889 }
59340500048 0:4f5ffc06a65b 890
59340500048 0:4f5ffc06a65b 891 return STATUS_OK;
59340500048 0:4f5ffc06a65b 892 } // End MIFARE_Write()
59340500048 0:4f5ffc06a65b 893
59340500048 0:4f5ffc06a65b 894 /*
59340500048 0:4f5ffc06a65b 895 * Writes a 4 byte page to the active MIFARE Ultralight PICC.
59340500048 0:4f5ffc06a65b 896 */
59340500048 0:4f5ffc06a65b 897 uint8_t MFRC522::MIFARE_UltralightWrite(uint8_t page, uint8_t *buffer, uint8_t bufferSize)
59340500048 0:4f5ffc06a65b 898 {
59340500048 0:4f5ffc06a65b 899 uint8_t result;
59340500048 0:4f5ffc06a65b 900
59340500048 0:4f5ffc06a65b 901 // Sanity check
59340500048 0:4f5ffc06a65b 902 if (buffer == NULL || bufferSize < 4)
59340500048 0:4f5ffc06a65b 903 {
59340500048 0:4f5ffc06a65b 904 return STATUS_INVALID;
59340500048 0:4f5ffc06a65b 905 }
59340500048 0:4f5ffc06a65b 906
59340500048 0:4f5ffc06a65b 907 // Build commmand buffer
59340500048 0:4f5ffc06a65b 908 uint8_t cmdBuffer[6];
59340500048 0:4f5ffc06a65b 909 cmdBuffer[0] = PICC_CMD_UL_WRITE;
59340500048 0:4f5ffc06a65b 910 cmdBuffer[1] = page;
59340500048 0:4f5ffc06a65b 911 memcpy(&cmdBuffer[2], buffer, 4);
59340500048 0:4f5ffc06a65b 912
59340500048 0:4f5ffc06a65b 913 // Perform the write
59340500048 0:4f5ffc06a65b 914 result = PCD_MIFARE_Transceive(cmdBuffer, 6); // Adds CRC_A and checks that the response is MF_ACK.
59340500048 0:4f5ffc06a65b 915 if (result != STATUS_OK)
59340500048 0:4f5ffc06a65b 916 {
59340500048 0:4f5ffc06a65b 917 return result;
59340500048 0:4f5ffc06a65b 918 }
59340500048 0:4f5ffc06a65b 919
59340500048 0:4f5ffc06a65b 920 return STATUS_OK;
59340500048 0:4f5ffc06a65b 921 } // End MIFARE_Ultralight_Write()
59340500048 0:4f5ffc06a65b 922
59340500048 0:4f5ffc06a65b 923 /*
59340500048 0:4f5ffc06a65b 924 * MIFARE Decrement subtracts the delta from the value of the addressed block, and stores the result in a volatile memory.
59340500048 0:4f5ffc06a65b 925 */
59340500048 0:4f5ffc06a65b 926 uint8_t MFRC522::MIFARE_Decrement(uint8_t blockAddr, uint32_t delta)
59340500048 0:4f5ffc06a65b 927 {
59340500048 0:4f5ffc06a65b 928 return MIFARE_TwoStepHelper(PICC_CMD_MF_DECREMENT, blockAddr, delta);
59340500048 0:4f5ffc06a65b 929 } // End MIFARE_Decrement()
59340500048 0:4f5ffc06a65b 930
59340500048 0:4f5ffc06a65b 931 /*
59340500048 0:4f5ffc06a65b 932 * MIFARE Increment adds the delta to the value of the addressed block, and stores the result in a volatile memory.
59340500048 0:4f5ffc06a65b 933 */
59340500048 0:4f5ffc06a65b 934 uint8_t MFRC522::MIFARE_Increment(uint8_t blockAddr, uint32_t delta)
59340500048 0:4f5ffc06a65b 935 {
59340500048 0:4f5ffc06a65b 936 return MIFARE_TwoStepHelper(PICC_CMD_MF_INCREMENT, blockAddr, delta);
59340500048 0:4f5ffc06a65b 937 } // End MIFARE_Increment()
59340500048 0:4f5ffc06a65b 938
59340500048 0:4f5ffc06a65b 939 /**
59340500048 0:4f5ffc06a65b 940 * MIFARE Restore copies the value of the addressed block into a volatile memory.
59340500048 0:4f5ffc06a65b 941 */
59340500048 0:4f5ffc06a65b 942 uint8_t MFRC522::MIFARE_Restore(uint8_t blockAddr)
59340500048 0:4f5ffc06a65b 943 {
59340500048 0:4f5ffc06a65b 944 // The datasheet describes Restore as a two step operation, but does not explain what data to transfer in step 2.
59340500048 0:4f5ffc06a65b 945 // Doing only a single step does not work, so I chose to transfer 0L in step two.
59340500048 0:4f5ffc06a65b 946 return MIFARE_TwoStepHelper(PICC_CMD_MF_RESTORE, blockAddr, 0L);
59340500048 0:4f5ffc06a65b 947 } // End MIFARE_Restore()
59340500048 0:4f5ffc06a65b 948
59340500048 0:4f5ffc06a65b 949 /*
59340500048 0:4f5ffc06a65b 950 * Helper function for the two-step MIFARE Classic protocol operations Decrement, Increment and Restore.
59340500048 0:4f5ffc06a65b 951 */
59340500048 0:4f5ffc06a65b 952 uint8_t MFRC522::MIFARE_TwoStepHelper(uint8_t command, uint8_t blockAddr, uint32_t data)
59340500048 0:4f5ffc06a65b 953 {
59340500048 0:4f5ffc06a65b 954 uint8_t result;
59340500048 0:4f5ffc06a65b 955 uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
59340500048 0:4f5ffc06a65b 956
59340500048 0:4f5ffc06a65b 957 // Step 1: Tell the PICC the command and block address
59340500048 0:4f5ffc06a65b 958 cmdBuffer[0] = command;
59340500048 0:4f5ffc06a65b 959 cmdBuffer[1] = blockAddr;
59340500048 0:4f5ffc06a65b 960
59340500048 0:4f5ffc06a65b 961 // Adds CRC_A and checks that the response is MF_ACK.
59340500048 0:4f5ffc06a65b 962 result = PCD_MIFARE_Transceive(cmdBuffer, 2);
59340500048 0:4f5ffc06a65b 963 if (result != STATUS_OK)
59340500048 0:4f5ffc06a65b 964 {
59340500048 0:4f5ffc06a65b 965 return result;
59340500048 0:4f5ffc06a65b 966 }
59340500048 0:4f5ffc06a65b 967
59340500048 0:4f5ffc06a65b 968 // Step 2: Transfer the data
59340500048 0:4f5ffc06a65b 969 // Adds CRC_A and accept timeout as success.
59340500048 0:4f5ffc06a65b 970 result = PCD_MIFARE_Transceive((uint8_t *) &data, 4, true);
59340500048 0:4f5ffc06a65b 971 if (result != STATUS_OK)
59340500048 0:4f5ffc06a65b 972 {
59340500048 0:4f5ffc06a65b 973 return result;
59340500048 0:4f5ffc06a65b 974 }
59340500048 0:4f5ffc06a65b 975
59340500048 0:4f5ffc06a65b 976 return STATUS_OK;
59340500048 0:4f5ffc06a65b 977 } // End MIFARE_TwoStepHelper()
59340500048 0:4f5ffc06a65b 978
59340500048 0:4f5ffc06a65b 979 /*
59340500048 0:4f5ffc06a65b 980 * MIFARE Transfer writes the value stored in the volatile memory into one MIFARE Classic block.
59340500048 0:4f5ffc06a65b 981 */
59340500048 0:4f5ffc06a65b 982 uint8_t MFRC522::MIFARE_Transfer(uint8_t blockAddr)
59340500048 0:4f5ffc06a65b 983 {
59340500048 0:4f5ffc06a65b 984 uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
59340500048 0:4f5ffc06a65b 985
59340500048 0:4f5ffc06a65b 986 // Tell the PICC we want to transfer the result into block blockAddr.
59340500048 0:4f5ffc06a65b 987 cmdBuffer[0] = PICC_CMD_MF_TRANSFER;
59340500048 0:4f5ffc06a65b 988 cmdBuffer[1] = blockAddr;
59340500048 0:4f5ffc06a65b 989
59340500048 0:4f5ffc06a65b 990 // Adds CRC_A and checks that the response is MF_ACK.
59340500048 0:4f5ffc06a65b 991 return PCD_MIFARE_Transceive(cmdBuffer, 2);
59340500048 0:4f5ffc06a65b 992 } // End MIFARE_Transfer()
59340500048 0:4f5ffc06a65b 993
59340500048 0:4f5ffc06a65b 994
59340500048 0:4f5ffc06a65b 995 /////////////////////////////////////////////////////////////////////////////////////
59340500048 0:4f5ffc06a65b 996 // Support functions
59340500048 0:4f5ffc06a65b 997 /////////////////////////////////////////////////////////////////////////////////////
59340500048 0:4f5ffc06a65b 998
59340500048 0:4f5ffc06a65b 999 /*
59340500048 0:4f5ffc06a65b 1000 * Wrapper for MIFARE protocol communication.
59340500048 0:4f5ffc06a65b 1001 * Adds CRC_A, executes the Transceive command and checks that the response is MF_ACK or a timeout.
59340500048 0:4f5ffc06a65b 1002 */
59340500048 0:4f5ffc06a65b 1003 uint8_t MFRC522::PCD_MIFARE_Transceive(uint8_t *sendData, uint8_t sendLen, bool acceptTimeout)
59340500048 0:4f5ffc06a65b 1004 {
59340500048 0:4f5ffc06a65b 1005 uint8_t result;
59340500048 0:4f5ffc06a65b 1006 uint8_t cmdBuffer[18]; // We need room for 16 bytes data and 2 bytes CRC_A.
59340500048 0:4f5ffc06a65b 1007
59340500048 0:4f5ffc06a65b 1008 // Sanity check
59340500048 0:4f5ffc06a65b 1009 if (sendData == NULL || sendLen > 16)
59340500048 0:4f5ffc06a65b 1010 {
59340500048 0:4f5ffc06a65b 1011 return STATUS_INVALID;
59340500048 0:4f5ffc06a65b 1012 }
59340500048 0:4f5ffc06a65b 1013
59340500048 0:4f5ffc06a65b 1014 // Copy sendData[] to cmdBuffer[] and add CRC_A
59340500048 0:4f5ffc06a65b 1015 memcpy(cmdBuffer, sendData, sendLen);
59340500048 0:4f5ffc06a65b 1016 result = PCD_CalculateCRC(cmdBuffer, sendLen, &cmdBuffer[sendLen]);
59340500048 0:4f5ffc06a65b 1017 if (result != STATUS_OK)
59340500048 0:4f5ffc06a65b 1018 {
59340500048 0:4f5ffc06a65b 1019 return result;
59340500048 0:4f5ffc06a65b 1020 }
59340500048 0:4f5ffc06a65b 1021
59340500048 0:4f5ffc06a65b 1022 sendLen += 2;
59340500048 0:4f5ffc06a65b 1023
59340500048 0:4f5ffc06a65b 1024 // Transceive the data, store the reply in cmdBuffer[]
59340500048 0:4f5ffc06a65b 1025 uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
59340500048 0:4f5ffc06a65b 1026 uint8_t cmdBufferSize = sizeof(cmdBuffer);
59340500048 0:4f5ffc06a65b 1027 uint8_t validBits = 0;
59340500048 0:4f5ffc06a65b 1028 result = PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, cmdBuffer, sendLen, cmdBuffer, &cmdBufferSize, &validBits);
59340500048 0:4f5ffc06a65b 1029 if (acceptTimeout && result == STATUS_TIMEOUT)
59340500048 0:4f5ffc06a65b 1030 {
59340500048 0:4f5ffc06a65b 1031 return STATUS_OK;
59340500048 0:4f5ffc06a65b 1032 }
59340500048 0:4f5ffc06a65b 1033
59340500048 0:4f5ffc06a65b 1034 if (result != STATUS_OK)
59340500048 0:4f5ffc06a65b 1035 {
59340500048 0:4f5ffc06a65b 1036 return result;
59340500048 0:4f5ffc06a65b 1037 }
59340500048 0:4f5ffc06a65b 1038
59340500048 0:4f5ffc06a65b 1039 // The PICC must reply with a 4 bit ACK
59340500048 0:4f5ffc06a65b 1040 if (cmdBufferSize != 1 || validBits != 4)
59340500048 0:4f5ffc06a65b 1041 {
59340500048 0:4f5ffc06a65b 1042 return STATUS_ERROR;
59340500048 0:4f5ffc06a65b 1043 }
59340500048 0:4f5ffc06a65b 1044
59340500048 0:4f5ffc06a65b 1045 if (cmdBuffer[0] != MF_ACK)
59340500048 0:4f5ffc06a65b 1046 {
59340500048 0:4f5ffc06a65b 1047 return STATUS_MIFARE_NACK;
59340500048 0:4f5ffc06a65b 1048 }
59340500048 0:4f5ffc06a65b 1049
59340500048 0:4f5ffc06a65b 1050 return STATUS_OK;
59340500048 0:4f5ffc06a65b 1051 } // End PCD_MIFARE_Transceive()
59340500048 0:4f5ffc06a65b 1052
59340500048 0:4f5ffc06a65b 1053
59340500048 0:4f5ffc06a65b 1054 /*
59340500048 0:4f5ffc06a65b 1055 * Translates the SAK (Select Acknowledge) to a PICC type.
59340500048 0:4f5ffc06a65b 1056 */
59340500048 0:4f5ffc06a65b 1057 uint8_t MFRC522::PICC_GetType(uint8_t sak)
59340500048 0:4f5ffc06a65b 1058 {
59340500048 0:4f5ffc06a65b 1059 uint8_t retType = PICC_TYPE_UNKNOWN;
59340500048 0:4f5ffc06a65b 1060
59340500048 0:4f5ffc06a65b 1061 if (sak & 0x04)
59340500048 0:4f5ffc06a65b 1062 { // UID not complete
59340500048 0:4f5ffc06a65b 1063 retType = PICC_TYPE_NOT_COMPLETE;
59340500048 0:4f5ffc06a65b 1064 }
59340500048 0:4f5ffc06a65b 1065 else
59340500048 0:4f5ffc06a65b 1066 {
59340500048 0:4f5ffc06a65b 1067 switch (sak)
59340500048 0:4f5ffc06a65b 1068 {
59340500048 0:4f5ffc06a65b 1069 case 0x09: retType = PICC_TYPE_MIFARE_MINI; break;
59340500048 0:4f5ffc06a65b 1070 case 0x08: retType = PICC_TYPE_MIFARE_1K; break;
59340500048 0:4f5ffc06a65b 1071 case 0x18: retType = PICC_TYPE_MIFARE_4K; break;
59340500048 0:4f5ffc06a65b 1072 case 0x00: retType = PICC_TYPE_MIFARE_UL; break;
59340500048 0:4f5ffc06a65b 1073 case 0x10:
59340500048 0:4f5ffc06a65b 1074 case 0x11: retType = PICC_TYPE_MIFARE_PLUS; break;
59340500048 0:4f5ffc06a65b 1075 case 0x01: retType = PICC_TYPE_TNP3XXX; break;
59340500048 0:4f5ffc06a65b 1076 default:
59340500048 0:4f5ffc06a65b 1077 if (sak & 0x20)
59340500048 0:4f5ffc06a65b 1078 {
59340500048 0:4f5ffc06a65b 1079 retType = PICC_TYPE_ISO_14443_4;
59340500048 0:4f5ffc06a65b 1080 }
59340500048 0:4f5ffc06a65b 1081 else if (sak & 0x40)
59340500048 0:4f5ffc06a65b 1082 {
59340500048 0:4f5ffc06a65b 1083 retType = PICC_TYPE_ISO_18092;
59340500048 0:4f5ffc06a65b 1084 }
59340500048 0:4f5ffc06a65b 1085 break;
59340500048 0:4f5ffc06a65b 1086 }
59340500048 0:4f5ffc06a65b 1087 }
59340500048 0:4f5ffc06a65b 1088
59340500048 0:4f5ffc06a65b 1089 return (retType);
59340500048 0:4f5ffc06a65b 1090 } // End PICC_GetType()
59340500048 0:4f5ffc06a65b 1091
59340500048 0:4f5ffc06a65b 1092 /*
59340500048 0:4f5ffc06a65b 1093 * Returns a string pointer to the PICC type name.
59340500048 0:4f5ffc06a65b 1094 */
59340500048 0:4f5ffc06a65b 1095 char* MFRC522::PICC_GetTypeName(uint8_t piccType)
59340500048 0:4f5ffc06a65b 1096 {
59340500048 0:4f5ffc06a65b 1097 if(piccType == PICC_TYPE_NOT_COMPLETE)
59340500048 0:4f5ffc06a65b 1098 {
59340500048 0:4f5ffc06a65b 1099 piccType = MFRC522_MaxPICCs - 1;
59340500048 0:4f5ffc06a65b 1100 }
59340500048 0:4f5ffc06a65b 1101
59340500048 0:4f5ffc06a65b 1102 return((char *) _TypeNamePICC[piccType]);
59340500048 0:4f5ffc06a65b 1103 } // End PICC_GetTypeName()
59340500048 0:4f5ffc06a65b 1104
59340500048 0:4f5ffc06a65b 1105 /*
59340500048 0:4f5ffc06a65b 1106 * Returns a string pointer to a status code name.
59340500048 0:4f5ffc06a65b 1107 */
59340500048 0:4f5ffc06a65b 1108 char* MFRC522::GetStatusCodeName(uint8_t code)
59340500048 0:4f5ffc06a65b 1109 {
59340500048 0:4f5ffc06a65b 1110 return((char *) _ErrorMessage[code]);
59340500048 0:4f5ffc06a65b 1111 } // End GetStatusCodeName()
59340500048 0:4f5ffc06a65b 1112
59340500048 0:4f5ffc06a65b 1113 /*
59340500048 0:4f5ffc06a65b 1114 * Calculates the bit pattern needed for the specified access bits. In the [C1 C2 C3] tupples C1 is MSB (=4) and C3 is LSB (=1).
59340500048 0:4f5ffc06a65b 1115 */
59340500048 0:4f5ffc06a65b 1116 void MFRC522::MIFARE_SetAccessBits(uint8_t *accessBitBuffer,
59340500048 0:4f5ffc06a65b 1117 uint8_t g0,
59340500048 0:4f5ffc06a65b 1118 uint8_t g1,
59340500048 0:4f5ffc06a65b 1119 uint8_t g2,
59340500048 0:4f5ffc06a65b 1120 uint8_t g3)
59340500048 0:4f5ffc06a65b 1121 {
59340500048 0:4f5ffc06a65b 1122 uint8_t c1 = ((g3 & 4) << 1) | ((g2 & 4) << 0) | ((g1 & 4) >> 1) | ((g0 & 4) >> 2);
59340500048 0:4f5ffc06a65b 1123 uint8_t c2 = ((g3 & 2) << 2) | ((g2 & 2) << 1) | ((g1 & 2) << 0) | ((g0 & 2) >> 1);
59340500048 0:4f5ffc06a65b 1124 uint8_t c3 = ((g3 & 1) << 3) | ((g2 & 1) << 2) | ((g1 & 1) << 1) | ((g0 & 1) << 0);
59340500048 0:4f5ffc06a65b 1125
59340500048 0:4f5ffc06a65b 1126 accessBitBuffer[0] = (~c2 & 0xF) << 4 | (~c1 & 0xF);
59340500048 0:4f5ffc06a65b 1127 accessBitBuffer[1] = c1 << 4 | (~c3 & 0xF);
59340500048 0:4f5ffc06a65b 1128 accessBitBuffer[2] = c3 << 4 | c2;
59340500048 0:4f5ffc06a65b 1129 } // End MIFARE_SetAccessBits()
59340500048 0:4f5ffc06a65b 1130
59340500048 0:4f5ffc06a65b 1131 /////////////////////////////////////////////////////////////////////////////////////
59340500048 0:4f5ffc06a65b 1132 // Convenience functions - does not add extra functionality
59340500048 0:4f5ffc06a65b 1133 /////////////////////////////////////////////////////////////////////////////////////
59340500048 0:4f5ffc06a65b 1134
59340500048 0:4f5ffc06a65b 1135 /*
59340500048 0:4f5ffc06a65b 1136 * Returns true if a PICC responds to PICC_CMD_REQA.
59340500048 0:4f5ffc06a65b 1137 * Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored.
59340500048 0:4f5ffc06a65b 1138 */
59340500048 0:4f5ffc06a65b 1139 bool MFRC522::PICC_IsNewCardPresent(void)
59340500048 0:4f5ffc06a65b 1140 {
59340500048 0:4f5ffc06a65b 1141 uint8_t bufferATQA[2];
59340500048 0:4f5ffc06a65b 1142 uint8_t bufferSize = sizeof(bufferATQA);
59340500048 0:4f5ffc06a65b 1143 uint8_t result = PICC_RequestA(bufferATQA, &bufferSize);
59340500048 0:4f5ffc06a65b 1144 return ((result == STATUS_OK) || (result == STATUS_COLLISION));
59340500048 0:4f5ffc06a65b 1145 } // End PICC_IsNewCardPresent()
59340500048 0:4f5ffc06a65b 1146
59340500048 0:4f5ffc06a65b 1147 /*
59340500048 0:4f5ffc06a65b 1148 * Simple wrapper around PICC_Select.
59340500048 0:4f5ffc06a65b 1149 */
59340500048 0:4f5ffc06a65b 1150 bool MFRC522::PICC_ReadCardSerial(void)
59340500048 0:4f5ffc06a65b 1151 {
59340500048 0:4f5ffc06a65b 1152 uint8_t result = PICC_Select(&uid);
59340500048 0:4f5ffc06a65b 1153 return (result == STATUS_OK);
59340500048 0:4f5ffc06a65b 1154 } // End PICC_ReadCardSerial()