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Dependencies:   N5110 mbed

Fork of DocTest by Craig Evans

PowerControl/EthernetPowerControl.h@4:a257abc56858, 2015-05-11 (annotated)

Committer:
200784123
Date:
Mon May 11 06:02:10 2015 +0000
Revision:
4:a257abc56858
Parent:
2:5446154a4028 
Fixed several notation issues

Who changed what in which revision?

UserRevisionLine numberNew contents of line
200784123 2:5446154a4028 1 /* mbed PowerControl Library
200784123 2:5446154a4028 2 * Copyright (c) 2010 Michael Wei
200784123 2:5446154a4028 3 */
200784123 2:5446154a4028 4
200784123 2:5446154a4028 5 #ifndef MBED_POWERCONTROL_ETH_H
200784123 2:5446154a4028 6 #define MBED_POWERCONTROL_ETH_H
200784123 2:5446154a4028 7
200784123 2:5446154a4028 8 #include "mbed.h"
200784123 2:5446154a4028 9 #include "PowerControl.h"
200784123 2:5446154a4028 10
200784123 2:5446154a4028 11 #define PHY_REG_BMCR_POWERDOWN 0xB
200784123 2:5446154a4028 12 #define PHY_REG_EDCR_ENABLE 0xF
200784123 2:5446154a4028 13
200784123 2:5446154a4028 14
200784123 2:5446154a4028 15 void EMAC_Init();
200784123 2:5446154a4028 16 static unsigned short read_PHY (unsigned int PhyReg);
200784123 2:5446154a4028 17 static void write_PHY (unsigned int PhyReg, unsigned short Value);
200784123 2:5446154a4028 18
200784123 2:5446154a4028 19 void PHY_PowerDown(void);
200784123 2:5446154a4028 20 void PHY_PowerUp(void);
200784123 2:5446154a4028 21 void PHY_EnergyDetect_Enable(void);
200784123 2:5446154a4028 22 void PHY_EnergyDetect_Disable(void);
200784123 2:5446154a4028 23
200784123 2:5446154a4028 24 //From NXP Sample Code .... Probably from KEIL sample code
200784123 2:5446154a4028 25 /* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
200784123 2:5446154a4028 26 #define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */
200784123 2:5446154a4028 27 #define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */
200784123 2:5446154a4028 28 #define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */
200784123 2:5446154a4028 29
200784123 2:5446154a4028 30 #define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
200784123 2:5446154a4028 31
200784123 2:5446154a4028 32 /* EMAC variables located in 16K Ethernet SRAM */
200784123 2:5446154a4028 33 #define RX_DESC_BASE 0x20080000
200784123 2:5446154a4028 34 #define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8)
200784123 2:5446154a4028 35 #define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8)
200784123 2:5446154a4028 36 #define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8)
200784123 2:5446154a4028 37 #define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4)
200784123 2:5446154a4028 38 #define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE)
200784123 2:5446154a4028 39
200784123 2:5446154a4028 40 /* RX and TX descriptor and status definitions. */
200784123 2:5446154a4028 41 #define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i))
200784123 2:5446154a4028 42 #define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i))
200784123 2:5446154a4028 43 #define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i))
200784123 2:5446154a4028 44 #define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i))
200784123 2:5446154a4028 45 #define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i))
200784123 2:5446154a4028 46 #define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i))
200784123 2:5446154a4028 47 #define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i))
200784123 2:5446154a4028 48 #define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i)
200784123 2:5446154a4028 49 #define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i)
200784123 2:5446154a4028 50
200784123 2:5446154a4028 51 /* MAC Configuration Register 1 */
200784123 2:5446154a4028 52 #define MAC1_REC_EN 0x00000001 /* Receive Enable */
200784123 2:5446154a4028 53 #define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */
200784123 2:5446154a4028 54 #define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */
200784123 2:5446154a4028 55 #define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */
200784123 2:5446154a4028 56 #define MAC1_LOOPB 0x00000010 /* Loop Back Mode */
200784123 2:5446154a4028 57 #define MAC1_RES_TX 0x00000100 /* Reset TX Logic */
200784123 2:5446154a4028 58 #define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */
200784123 2:5446154a4028 59 #define MAC1_RES_RX 0x00000400 /* Reset RX Logic */
200784123 2:5446154a4028 60 #define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */
200784123 2:5446154a4028 61 #define MAC1_SIM_RES 0x00004000 /* Simulation Reset */
200784123 2:5446154a4028 62 #define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */
200784123 2:5446154a4028 63
200784123 2:5446154a4028 64 /* MAC Configuration Register 2 */
200784123 2:5446154a4028 65 #define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */
200784123 2:5446154a4028 66 #define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */
200784123 2:5446154a4028 67 #define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */
200784123 2:5446154a4028 68 #define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */
200784123 2:5446154a4028 69 #define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */
200784123 2:5446154a4028 70 #define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */
200784123 2:5446154a4028 71 #define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */
200784123 2:5446154a4028 72 #define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */
200784123 2:5446154a4028 73 #define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */
200784123 2:5446154a4028 74 #define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */
200784123 2:5446154a4028 75 #define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */
200784123 2:5446154a4028 76 #define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */
200784123 2:5446154a4028 77 #define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */
200784123 2:5446154a4028 78
200784123 2:5446154a4028 79 /* Back-to-Back Inter-Packet-Gap Register */
200784123 2:5446154a4028 80 #define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */
200784123 2:5446154a4028 81 #define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */
200784123 2:5446154a4028 82
200784123 2:5446154a4028 83 /* Non Back-to-Back Inter-Packet-Gap Register */
200784123 2:5446154a4028 84 #define IPGR_DEF 0x00000012 /* Recommended value */
200784123 2:5446154a4028 85
200784123 2:5446154a4028 86 /* Collision Window/Retry Register */
200784123 2:5446154a4028 87 #define CLRT_DEF 0x0000370F /* Default value */
200784123 2:5446154a4028 88
200784123 2:5446154a4028 89 /* PHY Support Register */
200784123 2:5446154a4028 90 #define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */
200784123 2:5446154a4028 91 #define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */
200784123 2:5446154a4028 92
200784123 2:5446154a4028 93 /* Test Register */
200784123 2:5446154a4028 94 #define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */
200784123 2:5446154a4028 95 #define TEST_TST_PAUSE 0x00000002 /* Test Pause */
200784123 2:5446154a4028 96 #define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */
200784123 2:5446154a4028 97
200784123 2:5446154a4028 98 /* MII Management Configuration Register */
200784123 2:5446154a4028 99 #define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */
200784123 2:5446154a4028 100 #define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */
200784123 2:5446154a4028 101 #define MCFG_CLK_SEL 0x0000001C /* Clock Select Mask */
200784123 2:5446154a4028 102 #define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */
200784123 2:5446154a4028 103
200784123 2:5446154a4028 104 /* MII Management Command Register */
200784123 2:5446154a4028 105 #define MCMD_READ 0x00000001 /* MII Read */
200784123 2:5446154a4028 106 #define MCMD_SCAN 0x00000002 /* MII Scan continuously */
200784123 2:5446154a4028 107
200784123 2:5446154a4028 108 #define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
200784123 2:5446154a4028 109 #define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
200784123 2:5446154a4028 110
200784123 2:5446154a4028 111 /* MII Management Address Register */
200784123 2:5446154a4028 112 #define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */
200784123 2:5446154a4028 113 #define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
200784123 2:5446154a4028 114
200784123 2:5446154a4028 115 /* MII Management Indicators Register */
200784123 2:5446154a4028 116 #define MIND_BUSY 0x00000001 /* MII is Busy */
200784123 2:5446154a4028 117 #define MIND_SCAN 0x00000002 /* MII Scanning in Progress */
200784123 2:5446154a4028 118 #define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */
200784123 2:5446154a4028 119 #define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */
200784123 2:5446154a4028 120
200784123 2:5446154a4028 121 /* Command Register */
200784123 2:5446154a4028 122 #define CR_RX_EN 0x00000001 /* Enable Receive */
200784123 2:5446154a4028 123 #define CR_TX_EN 0x00000002 /* Enable Transmit */
200784123 2:5446154a4028 124 #define CR_REG_RES 0x00000008 /* Reset Host Registers */
200784123 2:5446154a4028 125 #define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */
200784123 2:5446154a4028 126 #define CR_RX_RES 0x00000020 /* Reset Receive Datapath */
200784123 2:5446154a4028 127 #define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */
200784123 2:5446154a4028 128 #define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */
200784123 2:5446154a4028 129 #define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */
200784123 2:5446154a4028 130 #define CR_RMII 0x00000200 /* Reduced MII Interface */
200784123 2:5446154a4028 131 #define CR_FULL_DUP 0x00000400 /* Full Duplex */
200784123 2:5446154a4028 132
200784123 2:5446154a4028 133 /* Status Register */
200784123 2:5446154a4028 134 #define SR_RX_EN 0x00000001 /* Enable Receive */
200784123 2:5446154a4028 135 #define SR_TX_EN 0x00000002 /* Enable Transmit */
200784123 2:5446154a4028 136
200784123 2:5446154a4028 137 /* Transmit Status Vector 0 Register */
200784123 2:5446154a4028 138 #define TSV0_CRC_ERR 0x00000001 /* CRC error */
200784123 2:5446154a4028 139 #define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */
200784123 2:5446154a4028 140 #define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */
200784123 2:5446154a4028 141 #define TSV0_DONE 0x00000008 /* Tramsmission Completed */
200784123 2:5446154a4028 142 #define TSV0_MCAST 0x00000010 /* Multicast Destination */
200784123 2:5446154a4028 143 #define TSV0_BCAST 0x00000020 /* Broadcast Destination */
200784123 2:5446154a4028 144 #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */
200784123 2:5446154a4028 145 #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */
200784123 2:5446154a4028 146 #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */
200784123 2:5446154a4028 147 #define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */
200784123 2:5446154a4028 148 #define TSV0_GIANT 0x00000400 /* Giant Frame */
200784123 2:5446154a4028 149 #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */
200784123 2:5446154a4028 150 #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */
200784123 2:5446154a4028 151 #define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */
200784123 2:5446154a4028 152 #define TSV0_PAUSE 0x20000000 /* Pause Frame */
200784123 2:5446154a4028 153 #define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */
200784123 2:5446154a4028 154 #define TSV0_VLAN 0x80000000 /* VLAN Frame */
200784123 2:5446154a4028 155
200784123 2:5446154a4028 156 /* Transmit Status Vector 1 Register */
200784123 2:5446154a4028 157 #define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */
200784123 2:5446154a4028 158 #define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */
200784123 2:5446154a4028 159
200784123 2:5446154a4028 160 /* Receive Status Vector Register */
200784123 2:5446154a4028 161 #define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */
200784123 2:5446154a4028 162 #define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */
200784123 2:5446154a4028 163 #define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */
200784123 2:5446154a4028 164 #define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */
200784123 2:5446154a4028 165 #define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */
200784123 2:5446154a4028 166 #define RSV_CRC_ERR 0x00100000 /* CRC Error */
200784123 2:5446154a4028 167 #define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */
200784123 2:5446154a4028 168 #define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */
200784123 2:5446154a4028 169 #define RSV_REC_OK 0x00800000 /* Frame Received OK */
200784123 2:5446154a4028 170 #define RSV_MCAST 0x01000000 /* Multicast Frame */
200784123 2:5446154a4028 171 #define RSV_BCAST 0x02000000 /* Broadcast Frame */
200784123 2:5446154a4028 172 #define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */
200784123 2:5446154a4028 173 #define RSV_CTRL_FRAME 0x08000000 /* Control Frame */
200784123 2:5446154a4028 174 #define RSV_PAUSE 0x10000000 /* Pause Frame */
200784123 2:5446154a4028 175 #define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */
200784123 2:5446154a4028 176 #define RSV_VLAN 0x40000000 /* VLAN Frame */
200784123 2:5446154a4028 177
200784123 2:5446154a4028 178 /* Flow Control Counter Register */
200784123 2:5446154a4028 179 #define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */
200784123 2:5446154a4028 180 #define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */
200784123 2:5446154a4028 181
200784123 2:5446154a4028 182 /* Flow Control Status Register */
200784123 2:5446154a4028 183 #define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */
200784123 2:5446154a4028 184
200784123 2:5446154a4028 185 /* Receive Filter Control Register */
200784123 2:5446154a4028 186 #define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */
200784123 2:5446154a4028 187 #define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */
200784123 2:5446154a4028 188 #define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */
200784123 2:5446154a4028 189 #define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */
200784123 2:5446154a4028 190 #define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/
200784123 2:5446154a4028 191 #define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */
200784123 2:5446154a4028 192 #define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */
200784123 2:5446154a4028 193 #define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */
200784123 2:5446154a4028 194
200784123 2:5446154a4028 195 /* Receive Filter WoL Status/Clear Registers */
200784123 2:5446154a4028 196 #define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */
200784123 2:5446154a4028 197 #define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */
200784123 2:5446154a4028 198 #define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */
200784123 2:5446154a4028 199 #define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */
200784123 2:5446154a4028 200 #define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */
200784123 2:5446154a4028 201 #define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */
200784123 2:5446154a4028 202 #define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */
200784123 2:5446154a4028 203 #define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */
200784123 2:5446154a4028 204
200784123 2:5446154a4028 205 /* Interrupt Status/Enable/Clear/Set Registers */
200784123 2:5446154a4028 206 #define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */
200784123 2:5446154a4028 207 #define INT_RX_ERR 0x00000002 /* Receive Error */
200784123 2:5446154a4028 208 #define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */
200784123 2:5446154a4028 209 #define INT_RX_DONE 0x00000008 /* Receive Done */
200784123 2:5446154a4028 210 #define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */
200784123 2:5446154a4028 211 #define INT_TX_ERR 0x00000020 /* Transmit Error */
200784123 2:5446154a4028 212 #define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */
200784123 2:5446154a4028 213 #define INT_TX_DONE 0x00000080 /* Transmit Done */
200784123 2:5446154a4028 214 #define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */
200784123 2:5446154a4028 215 #define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */
200784123 2:5446154a4028 216
200784123 2:5446154a4028 217 /* Power Down Register */
200784123 2:5446154a4028 218 #define PD_POWER_DOWN 0x80000000 /* Power Down MAC */
200784123 2:5446154a4028 219
200784123 2:5446154a4028 220 /* RX Descriptor Control Word */
200784123 2:5446154a4028 221 #define RCTRL_SIZE 0x000007FF /* Buffer size mask */
200784123 2:5446154a4028 222 #define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */
200784123 2:5446154a4028 223
200784123 2:5446154a4028 224 /* RX Status Hash CRC Word */
200784123 2:5446154a4028 225 #define RHASH_SA 0x000001FF /* Hash CRC for Source Address */
200784123 2:5446154a4028 226 #define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */
200784123 2:5446154a4028 227
200784123 2:5446154a4028 228 /* RX Status Information Word */
200784123 2:5446154a4028 229 #define RINFO_SIZE 0x000007FF /* Data size in bytes */
200784123 2:5446154a4028 230 #define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */
200784123 2:5446154a4028 231 #define RINFO_VLAN 0x00080000 /* VLAN Frame */
200784123 2:5446154a4028 232 #define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */
200784123 2:5446154a4028 233 #define RINFO_MCAST 0x00200000 /* Multicast Frame */
200784123 2:5446154a4028 234 #define RINFO_BCAST 0x00400000 /* Broadcast Frame */
200784123 2:5446154a4028 235 #define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */
200784123 2:5446154a4028 236 #define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */
200784123 2:5446154a4028 237 #define RINFO_LEN_ERR 0x02000000 /* Length Error */
200784123 2:5446154a4028 238 #define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */
200784123 2:5446154a4028 239 #define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */
200784123 2:5446154a4028 240 #define RINFO_OVERRUN 0x10000000 /* Receive overrun */
200784123 2:5446154a4028 241 #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */
200784123 2:5446154a4028 242 #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */
200784123 2:5446154a4028 243 #define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
200784123 2:5446154a4028 244
200784123 2:5446154a4028 245 #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \
200784123 2:5446154a4028 246 RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
200784123 2:5446154a4028 247
200784123 2:5446154a4028 248 /* TX Descriptor Control Word */
200784123 2:5446154a4028 249 #define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */
200784123 2:5446154a4028 250 #define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */
200784123 2:5446154a4028 251 #define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */
200784123 2:5446154a4028 252 #define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */
200784123 2:5446154a4028 253 #define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */
200784123 2:5446154a4028 254 #define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */
200784123 2:5446154a4028 255 #define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */
200784123 2:5446154a4028 256
200784123 2:5446154a4028 257 /* TX Status Information Word */
200784123 2:5446154a4028 258 #define TINFO_COL_CNT 0x01E00000 /* Collision Count */
200784123 2:5446154a4028 259 #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */
200784123 2:5446154a4028 260 #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */
200784123 2:5446154a4028 261 #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */
200784123 2:5446154a4028 262 #define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */
200784123 2:5446154a4028 263 #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */
200784123 2:5446154a4028 264 #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */
200784123 2:5446154a4028 265 #define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
200784123 2:5446154a4028 266
200784123 2:5446154a4028 267 /* DP83848C PHY Registers */
200784123 2:5446154a4028 268 #define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
200784123 2:5446154a4028 269 #define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
200784123 2:5446154a4028 270 #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
200784123 2:5446154a4028 271 #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
200784123 2:5446154a4028 272 #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
200784123 2:5446154a4028 273 #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
200784123 2:5446154a4028 274 #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
200784123 2:5446154a4028 275 #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
200784123 2:5446154a4028 276
200784123 2:5446154a4028 277 /* PHY Extended Registers */
200784123 2:5446154a4028 278 #define PHY_REG_STS 0x10 /* Status Register */
200784123 2:5446154a4028 279 #define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */
200784123 2:5446154a4028 280 #define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */
200784123 2:5446154a4028 281 #define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */
200784123 2:5446154a4028 282 #define PHY_REG_RECR 0x15 /* Receive Error Counter */
200784123 2:5446154a4028 283 #define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
200784123 2:5446154a4028 284 #define PHY_REG_RBR 0x17 /* RMII and Bypass Register */
200784123 2:5446154a4028 285 #define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */
200784123 2:5446154a4028 286 #define PHY_REG_PHYCR 0x19 /* PHY Control Register */
200784123 2:5446154a4028 287 #define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */
200784123 2:5446154a4028 288 #define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */
200784123 2:5446154a4028 289 #define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */
200784123 2:5446154a4028 290
200784123 2:5446154a4028 291 #define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
200784123 2:5446154a4028 292 #define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
200784123 2:5446154a4028 293 #define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
200784123 2:5446154a4028 294 #define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
200784123 2:5446154a4028 295 #define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */
200784123 2:5446154a4028 296
200784123 2:5446154a4028 297 #define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */
200784123 2:5446154a4028 298 #define DP83848C_ID 0x20005C90 /* PHY Identifier */
200784123 2:5446154a4028 299 #endif