Tomo Yamanaka
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mbed-dev
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targets/hal/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_pwm.c@0:9b334a45a8ff, 2015-10-01 (annotated)
- Committer:
- bogdanm
- Date:
- Thu Oct 01 15:25:22 2015 +0300
- Revision:
- 0:9b334a45a8ff
Initial commit on mbed-dev
Replaces mbed-src (now inactive)
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 0:9b334a45a8ff | 1 | /** |
| bogdanm | 0:9b334a45a8ff | 2 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 3 | * @file |
| bogdanm | 0:9b334a45a8ff | 4 | * @author |
| bogdanm | 0:9b334a45a8ff | 5 | * @version |
| bogdanm | 0:9b334a45a8ff | 6 | * @date |
| bogdanm | 0:9b334a45a8ff | 7 | * @brief This file contains all the functions prototypes for the UART |
| bogdanm | 0:9b334a45a8ff | 8 | * firmware library. |
| bogdanm | 0:9b334a45a8ff | 9 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 10 | * |
| bogdanm | 0:9b334a45a8ff | 11 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 12 | */ |
| bogdanm | 0:9b334a45a8ff | 13 | |
| bogdanm | 0:9b334a45a8ff | 14 | /* Includes -------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 15 | #include "W7500x.h" |
| bogdanm | 0:9b334a45a8ff | 16 | #include "W7500x_pwm.h" |
| bogdanm | 0:9b334a45a8ff | 17 | |
| bogdanm | 0:9b334a45a8ff | 18 | void PWM_DeInit(PWM_CHn_TypeDef* PWM_CHn) |
| bogdanm | 0:9b334a45a8ff | 19 | { |
| bogdanm | 0:9b334a45a8ff | 20 | if( PWM_CHn == PWM_CH0 ) |
| bogdanm | 0:9b334a45a8ff | 21 | { |
| bogdanm | 0:9b334a45a8ff | 22 | PWM->IER &= PWM_IER_IE0_Disable; ///< Interrupt enable register |
| bogdanm | 0:9b334a45a8ff | 23 | PWM->SSR &= PWM_SSR_SS0_Stop; ///< Start Stop register |
| bogdanm | 0:9b334a45a8ff | 24 | PWM->PSR &= PWM_PSR_PS0_Restart; ///< Pause register |
| bogdanm | 0:9b334a45a8ff | 25 | PWM_CH0->IER = 0; ///< Interrupt enable register |
| bogdanm | 0:9b334a45a8ff | 26 | PWM_CH0->ICR = PWM_CHn_ICR_MatchInterruptClear | |
| bogdanm | 0:9b334a45a8ff | 27 | PWM_CHn_ICR_OverflowInterruptClear | |
| bogdanm | 0:9b334a45a8ff | 28 | PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register |
| bogdanm | 0:9b334a45a8ff | 29 | PWM_CH0->PR = 0; ///< Prescale register |
| bogdanm | 0:9b334a45a8ff | 30 | PWM_CH0->MR = 0; ///< Match register |
| bogdanm | 0:9b334a45a8ff | 31 | PWM_CH0->LR = 0xFFFFFFFF; ///< Limit register |
| bogdanm | 0:9b334a45a8ff | 32 | PWM_CH0->UDMR = 0; ///< Up Dowm mode register |
| bogdanm | 0:9b334a45a8ff | 33 | PWM_CH0->TCMR = 0; ///< Timer Counter mode register |
| bogdanm | 0:9b334a45a8ff | 34 | PWM_CH0->PEEER = 0; ///< PWM output Enable and External input Enable register |
| bogdanm | 0:9b334a45a8ff | 35 | PWM_CH0->CMR = 0; ///< Capture mode register |
| bogdanm | 0:9b334a45a8ff | 36 | PWM_CH0->PDMR = 0; ///< Periodic Mode register |
| bogdanm | 0:9b334a45a8ff | 37 | PWM_CH0->DZER = 0; ///< Dead Zone Enable register |
| bogdanm | 0:9b334a45a8ff | 38 | PWM_CH0->DZCR = 0; ///< Dead Zone Counter register |
| bogdanm | 0:9b334a45a8ff | 39 | } |
| bogdanm | 0:9b334a45a8ff | 40 | else if( PWM_CHn == PWM_CH1 ) |
| bogdanm | 0:9b334a45a8ff | 41 | { |
| bogdanm | 0:9b334a45a8ff | 42 | PWM->IER &= PWM_IER_IE1_Disable; ///< Reset Interrupt enable register |
| bogdanm | 0:9b334a45a8ff | 43 | PWM->SSR &= PWM_SSR_SS1_Stop; ///< Reset Start Stop register |
| bogdanm | 0:9b334a45a8ff | 44 | PWM->PSR &= PWM_PSR_PS1_Restart; ///< Reset Pause register |
| bogdanm | 0:9b334a45a8ff | 45 | PWM_CH1->IER = 0; ///< Interrupt enable register |
| bogdanm | 0:9b334a45a8ff | 46 | PWM_CH1->ICR = PWM_CHn_ICR_MatchInterruptClear | |
| bogdanm | 0:9b334a45a8ff | 47 | PWM_CHn_ICR_OverflowInterruptClear | |
| bogdanm | 0:9b334a45a8ff | 48 | PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register |
| bogdanm | 0:9b334a45a8ff | 49 | PWM_CH1->PR = 0; ///< Prescale register |
| bogdanm | 0:9b334a45a8ff | 50 | PWM_CH1->MR = 0; ///< Match register |
| bogdanm | 0:9b334a45a8ff | 51 | PWM_CH1->LR = 0xFFFFFFFF; ///< Limit register |
| bogdanm | 0:9b334a45a8ff | 52 | PWM_CH1->UDMR = 0; ///< Up Dowm mode register |
| bogdanm | 0:9b334a45a8ff | 53 | PWM_CH1->TCMR = 0; ///< Timer Counter mode register |
| bogdanm | 0:9b334a45a8ff | 54 | PWM_CH1->PEEER = 0; ///< PWM output Enable and External input Enable register |
| bogdanm | 0:9b334a45a8ff | 55 | PWM_CH1->CMR = 0; ///< Capture mode register |
| bogdanm | 0:9b334a45a8ff | 56 | PWM_CH1->PDMR = 0; ///< Periodic Mode register |
| bogdanm | 0:9b334a45a8ff | 57 | PWM_CH1->DZER = 0; ///< Dead Zone Enable register |
| bogdanm | 0:9b334a45a8ff | 58 | PWM_CH1->DZCR = 0; ///< Dead Zone Counter register |
| bogdanm | 0:9b334a45a8ff | 59 | } |
| bogdanm | 0:9b334a45a8ff | 60 | else if( PWM_CHn == PWM_CH2) |
| bogdanm | 0:9b334a45a8ff | 61 | { |
| bogdanm | 0:9b334a45a8ff | 62 | PWM->IER &= PWM_IER_IE2_Disable; ///< Interrupt enable register |
| bogdanm | 0:9b334a45a8ff | 63 | PWM->SSR &= PWM_SSR_SS2_Stop; ///< Start Stop register |
| bogdanm | 0:9b334a45a8ff | 64 | PWM->PSR &= PWM_PSR_PS2_Restart; ///< Pause register |
| bogdanm | 0:9b334a45a8ff | 65 | PWM_CH2->IER = 0; ///< Interrupt enable register |
| bogdanm | 0:9b334a45a8ff | 66 | PWM_CH2->ICR = PWM_CHn_ICR_MatchInterruptClear | |
| bogdanm | 0:9b334a45a8ff | 67 | PWM_CHn_ICR_OverflowInterruptClear | |
| bogdanm | 0:9b334a45a8ff | 68 | PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register |
| bogdanm | 0:9b334a45a8ff | 69 | PWM_CH2->PR = 0; ///< Prescale register |
| bogdanm | 0:9b334a45a8ff | 70 | PWM_CH2->MR = 0; ///< Match register |
| bogdanm | 0:9b334a45a8ff | 71 | PWM_CH2->LR = 0xFFFFFFFF; ///< Limit register |
| bogdanm | 0:9b334a45a8ff | 72 | PWM_CH2->UDMR = 0; ///< Up Dowm mode register |
| bogdanm | 0:9b334a45a8ff | 73 | PWM_CH2->TCMR = 0; ///< Timer Counter mode register |
| bogdanm | 0:9b334a45a8ff | 74 | PWM_CH2->PEEER = 0; ///< PWM output Enable and External input Enable register |
| bogdanm | 0:9b334a45a8ff | 75 | PWM_CH2->CMR = 0; ///< Capture mode register |
| bogdanm | 0:9b334a45a8ff | 76 | PWM_CH2->PDMR = 0; ///< Periodic Mode register |
| bogdanm | 0:9b334a45a8ff | 77 | PWM_CH2->DZER = 0; ///< Dead Zone Enable register |
| bogdanm | 0:9b334a45a8ff | 78 | PWM_CH2->DZCR = 0; ///< Dead Zone Counter register |
| bogdanm | 0:9b334a45a8ff | 79 | } |
| bogdanm | 0:9b334a45a8ff | 80 | else if( PWM_CHn == PWM_CH3 ) |
| bogdanm | 0:9b334a45a8ff | 81 | { |
| bogdanm | 0:9b334a45a8ff | 82 | PWM->IER &= PWM_IER_IE3_Disable; ///< Interrupt enable register |
| bogdanm | 0:9b334a45a8ff | 83 | PWM->SSR &= PWM_SSR_SS3_Stop; ///< Start Stop register |
| bogdanm | 0:9b334a45a8ff | 84 | PWM->PSR &= PWM_PSR_PS3_Restart; ///< Pause register |
| bogdanm | 0:9b334a45a8ff | 85 | PWM_CH3->IER = 0; ///< Interrupt enable register |
| bogdanm | 0:9b334a45a8ff | 86 | PWM_CH3->ICR = PWM_CHn_ICR_MatchInterruptClear | |
| bogdanm | 0:9b334a45a8ff | 87 | PWM_CHn_ICR_OverflowInterruptClear | |
| bogdanm | 0:9b334a45a8ff | 88 | PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register |
| bogdanm | 0:9b334a45a8ff | 89 | PWM_CH3->MR = 0; ///< Match register |
| bogdanm | 0:9b334a45a8ff | 90 | PWM_CH3->LR = 0xFFFFFFFF; ///< Limit register |
| bogdanm | 0:9b334a45a8ff | 91 | PWM_CH3->UDMR = 0; ///< Up Dowm mode register |
| bogdanm | 0:9b334a45a8ff | 92 | PWM_CH3->TCMR = 0; ///< Timer Counter mode register |
| bogdanm | 0:9b334a45a8ff | 93 | PWM_CH3->PEEER = 0; ///< PWM output Enable and External input Enable register |
| bogdanm | 0:9b334a45a8ff | 94 | PWM_CH3->CMR = 0; ///< Capture mode register |
| bogdanm | 0:9b334a45a8ff | 95 | PWM_CH3->PDMR = 0; ///< Periodic Mode register |
| bogdanm | 0:9b334a45a8ff | 96 | PWM_CH3->DZER = 0; ///< Dead Zone Enable register |
| bogdanm | 0:9b334a45a8ff | 97 | PWM_CH3->DZCR = 0; ///< Dead Zone Counter register |
| bogdanm | 0:9b334a45a8ff | 98 | } |
| bogdanm | 0:9b334a45a8ff | 99 | else if( PWM_CHn == PWM_CH4 ) |
| bogdanm | 0:9b334a45a8ff | 100 | { |
| bogdanm | 0:9b334a45a8ff | 101 | PWM->SSR &= PWM_IER_IE4_Disable; ///< Start Stop register |
| bogdanm | 0:9b334a45a8ff | 102 | PWM->PSR &= PWM_SSR_SS4_Stop; ///< Pause register |
| bogdanm | 0:9b334a45a8ff | 103 | PWM->IER &= PWM_PSR_PS4_Restart; ///< Interrupt enable register |
| bogdanm | 0:9b334a45a8ff | 104 | PWM_CH4->IER = 0; ///< Interrupt enable register |
| bogdanm | 0:9b334a45a8ff | 105 | PWM_CH4->ICR = PWM_CHn_ICR_MatchInterruptClear | |
| bogdanm | 0:9b334a45a8ff | 106 | PWM_CHn_ICR_OverflowInterruptClear | |
| bogdanm | 0:9b334a45a8ff | 107 | PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register |
| bogdanm | 0:9b334a45a8ff | 108 | PWM_CH4->PR = 0; ///< Prescale register |
| bogdanm | 0:9b334a45a8ff | 109 | PWM_CH4->MR = 0; ///< Match register |
| bogdanm | 0:9b334a45a8ff | 110 | PWM_CH4->LR = 0xFFFF; ///< Limit register |
| bogdanm | 0:9b334a45a8ff | 111 | PWM_CH4->UDMR = 0; ///< Up Dowm mode register |
| bogdanm | 0:9b334a45a8ff | 112 | PWM_CH4->TCMR = 0; ///< Timer Counter mode register |
| bogdanm | 0:9b334a45a8ff | 113 | PWM_CH4->PEEER = 0; ///< PWM output Enable and External input Enable register |
| bogdanm | 0:9b334a45a8ff | 114 | PWM_CH4->CMR = 0; ///< Capture mode register |
| bogdanm | 0:9b334a45a8ff | 115 | PWM_CH4->PDMR = 0; ///< Periodic Mode register |
| bogdanm | 0:9b334a45a8ff | 116 | PWM_CH4->DZER = 0; ///< Dead Zone Enable register |
| bogdanm | 0:9b334a45a8ff | 117 | PWM_CH4->DZCR = 0; ///< Dead Zone Counter register |
| bogdanm | 0:9b334a45a8ff | 118 | } |
| bogdanm | 0:9b334a45a8ff | 119 | else if( PWM_CHn == PWM_CH5 ) |
| bogdanm | 0:9b334a45a8ff | 120 | { |
| bogdanm | 0:9b334a45a8ff | 121 | PWM->SSR &= PWM_IER_IE5_Disable; ///< Start Stop register |
| bogdanm | 0:9b334a45a8ff | 122 | PWM->PSR &= PWM_SSR_SS5_Stop; ///< Pause register |
| bogdanm | 0:9b334a45a8ff | 123 | PWM->IER &= PWM_PSR_PS5_Restart; ///< Interrupt enable register |
| bogdanm | 0:9b334a45a8ff | 124 | PWM_CH5->IER = 0; ///< Interrupt enable register |
| bogdanm | 0:9b334a45a8ff | 125 | PWM_CH5->ICR = PWM_CHn_ICR_MatchInterruptClear | |
| bogdanm | 0:9b334a45a8ff | 126 | PWM_CHn_ICR_OverflowInterruptClear | |
| bogdanm | 0:9b334a45a8ff | 127 | PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register |
| bogdanm | 0:9b334a45a8ff | 128 | PWM_CH5->PR = 0; ///< Prescale register |
| bogdanm | 0:9b334a45a8ff | 129 | PWM_CH5->MR = 0; ///< Match register |
| bogdanm | 0:9b334a45a8ff | 130 | PWM_CH5->LR = 0xFFFFFFFF; ///< Limit register |
| bogdanm | 0:9b334a45a8ff | 131 | PWM_CH5->UDMR = 0; ///< Up Dowm mode register |
| bogdanm | 0:9b334a45a8ff | 132 | PWM_CH5->TCMR = 0; ///< Timer Counter mode register |
| bogdanm | 0:9b334a45a8ff | 133 | PWM_CH5->PEEER = 0; ///< PWM output Enable and External input Enable register |
| bogdanm | 0:9b334a45a8ff | 134 | PWM_CH5->CMR = 0; ///< Capture mode register |
| bogdanm | 0:9b334a45a8ff | 135 | PWM_CH5->PDMR = 0; ///< Periodic Mode register |
| bogdanm | 0:9b334a45a8ff | 136 | PWM_CH5->DZER = 0; ///< Dead Zone Enable register |
| bogdanm | 0:9b334a45a8ff | 137 | PWM_CH5->DZCR = 0; ///< Dead Zone Counter register |
| bogdanm | 0:9b334a45a8ff | 138 | } |
| bogdanm | 0:9b334a45a8ff | 139 | else if( PWM_CHn == PWM_CH6 ) |
| bogdanm | 0:9b334a45a8ff | 140 | { |
| bogdanm | 0:9b334a45a8ff | 141 | PWM->SSR &= PWM_IER_IE6_Disable; ///< Start Stop register |
| bogdanm | 0:9b334a45a8ff | 142 | PWM->PSR &= PWM_SSR_SS6_Stop; ///< Pause register |
| bogdanm | 0:9b334a45a8ff | 143 | PWM->IER &= PWM_PSR_PS6_Restart; ///< Interrupt enable register |
| bogdanm | 0:9b334a45a8ff | 144 | PWM_CH6->IER = 0; ///< Interrupt enable register |
| bogdanm | 0:9b334a45a8ff | 145 | PWM_CH6->ICR = PWM_CHn_ICR_MatchInterruptClear | |
| bogdanm | 0:9b334a45a8ff | 146 | PWM_CHn_ICR_OverflowInterruptClear | |
| bogdanm | 0:9b334a45a8ff | 147 | PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register |
| bogdanm | 0:9b334a45a8ff | 148 | PWM_CH6->PR = 0; ///< Prescale register |
| bogdanm | 0:9b334a45a8ff | 149 | PWM_CH6->MR = 0; ///< Match register |
| bogdanm | 0:9b334a45a8ff | 150 | PWM_CH6->LR = 0xFFFFFFFF; ///< Limit register |
| bogdanm | 0:9b334a45a8ff | 151 | PWM_CH6->UDMR = 0; ///< Up Dowm mode register |
| bogdanm | 0:9b334a45a8ff | 152 | PWM_CH6->TCMR = 0; ///< Timer Counter mode register |
| bogdanm | 0:9b334a45a8ff | 153 | PWM_CH6->PEEER = 0; ///< PWM output Enable and External input Enable register |
| bogdanm | 0:9b334a45a8ff | 154 | PWM_CH6->CMR = 0; ///< Capture mode register |
| bogdanm | 0:9b334a45a8ff | 155 | PWM_CH6->PDMR = 0; ///< Periodic Mode register |
| bogdanm | 0:9b334a45a8ff | 156 | PWM_CH6->DZER = 0; ///< Dead Zone Enable register |
| bogdanm | 0:9b334a45a8ff | 157 | PWM_CH6->DZCR = 0; ///< Dead Zone Counter register |
| bogdanm | 0:9b334a45a8ff | 158 | } |
| bogdanm | 0:9b334a45a8ff | 159 | else if( PWM_CHn == PWM_CH7 ) |
| bogdanm | 0:9b334a45a8ff | 160 | { |
| bogdanm | 0:9b334a45a8ff | 161 | PWM->SSR &= PWM_IER_IE7_Disable; ///< Start Stop register |
| bogdanm | 0:9b334a45a8ff | 162 | PWM->PSR &= PWM_SSR_SS7_Stop; ///< Pause register |
| bogdanm | 0:9b334a45a8ff | 163 | PWM->IER &= PWM_PSR_PS7_Restart; ///< Interrupt enable register |
| bogdanm | 0:9b334a45a8ff | 164 | PWM_CH7->IER = 0; ///< Interrupt enable register |
| bogdanm | 0:9b334a45a8ff | 165 | PWM_CH7->ICR = PWM_CHn_ICR_MatchInterruptClear | |
| bogdanm | 0:9b334a45a8ff | 166 | PWM_CHn_ICR_OverflowInterruptClear | |
| bogdanm | 0:9b334a45a8ff | 167 | PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register |
| bogdanm | 0:9b334a45a8ff | 168 | PWM_CH7->PR = 0; ///< Prescale register |
| bogdanm | 0:9b334a45a8ff | 169 | PWM_CH7->MR = 0; ///< Match register |
| bogdanm | 0:9b334a45a8ff | 170 | PWM_CH7->LR = 0xFFFFFFFF; ///< Limit register |
| bogdanm | 0:9b334a45a8ff | 171 | PWM_CH7->UDMR = 0; ///< Up Dowm mode register |
| bogdanm | 0:9b334a45a8ff | 172 | PWM_CH7->TCMR = 0; ///< Timer Counter mode register |
| bogdanm | 0:9b334a45a8ff | 173 | PWM_CH7->PEEER = 0; ///< PWM output Enable and External input Enable register |
| bogdanm | 0:9b334a45a8ff | 174 | PWM_CH7->CMR = 0; ///< Capture mode register |
| bogdanm | 0:9b334a45a8ff | 175 | PWM_CH7->PDMR = 0; ///< Periodic Mode register |
| bogdanm | 0:9b334a45a8ff | 176 | PWM_CH7->DZER = 0; ///< Dead Zone Enable register |
| bogdanm | 0:9b334a45a8ff | 177 | PWM_CH7->DZCR = 0; ///< Dead Zone Counter register |
| bogdanm | 0:9b334a45a8ff | 178 | } |
| bogdanm | 0:9b334a45a8ff | 179 | } |
| bogdanm | 0:9b334a45a8ff | 180 | |
| bogdanm | 0:9b334a45a8ff | 181 | |
| bogdanm | 0:9b334a45a8ff | 182 | void PWM_TimerModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_TimerModeInitTypeDef* PWM_TimerModeInitStruct) //complet |
| bogdanm | 0:9b334a45a8ff | 183 | { |
| bogdanm | 0:9b334a45a8ff | 184 | /* Stop PWM_CHn */ |
| bogdanm | 0:9b334a45a8ff | 185 | PWM_CHn_Stop(PWM_CHn); |
| bogdanm | 0:9b334a45a8ff | 186 | /* Select Timer/Counter mode as Timer mode */ |
| bogdanm | 0:9b334a45a8ff | 187 | PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode; |
| bogdanm | 0:9b334a45a8ff | 188 | /* Set Prescale register value */ |
| bogdanm | 0:9b334a45a8ff | 189 | PWM_CHn->PR = PWM_TimerModeInitStruct->PWM_CHn_PR; |
| bogdanm | 0:9b334a45a8ff | 190 | /* Set Match register value */ |
| bogdanm | 0:9b334a45a8ff | 191 | PWM_CHn->MR = PWM_TimerModeInitStruct->PWM_CHn_MR; |
| bogdanm | 0:9b334a45a8ff | 192 | /* Set Limit register value */ |
| bogdanm | 0:9b334a45a8ff | 193 | PWM_CHn->LR = PWM_TimerModeInitStruct->PWM_CHn_LR; |
| bogdanm | 0:9b334a45a8ff | 194 | /* Select Up-down mode */ |
| bogdanm | 0:9b334a45a8ff | 195 | PWM_CHn->UDMR = PWM_TimerModeInitStruct->PWM_CHn_UDMR; |
| bogdanm | 0:9b334a45a8ff | 196 | /* Select Periodic mode */ |
| bogdanm | 0:9b334a45a8ff | 197 | PWM_CHn->PDMR = PWM_TimerModeInitStruct->PWM_CHn_PDMR; |
| bogdanm | 0:9b334a45a8ff | 198 | } |
| bogdanm | 0:9b334a45a8ff | 199 | |
| bogdanm | 0:9b334a45a8ff | 200 | void PWM_CaptureModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CaptureModeInitTypeDef* PWM_CaptureModeInitStruct) //complete |
| bogdanm | 0:9b334a45a8ff | 201 | { |
| bogdanm | 0:9b334a45a8ff | 202 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 203 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 204 | assert_param(IS_PWM_PR_FILTER(PWM_CaptureModeInitStruct->PWM_CHn_PR)); |
| bogdanm | 0:9b334a45a8ff | 205 | assert_param(IS_PWM_MR_FILTER(PWM_CHn, PWM_CaptureModeInitStruct->PWM_CHn_MR)); |
| bogdanm | 0:9b334a45a8ff | 206 | assert_param(IS_PWM_LR_FILTER(PWM_CHn, PWM_CaptureModeInitStruct->PWM_CHn_LR)); |
| bogdanm | 0:9b334a45a8ff | 207 | assert_param(IS_PWM_CHn_UDMR(PWM_CaptureModeInitStruct->PWM_CHn_UDMR)); |
| bogdanm | 0:9b334a45a8ff | 208 | assert_param(IS_PWM_CHn_PDMR(PWM_CaptureModeInitStruct->PWM_CHn_PDMR)); |
| bogdanm | 0:9b334a45a8ff | 209 | assert_param(IS_PWM_CHn_CMR(PWM_CaptureModeInitStruct->PWM_CHn_CMR)); |
| bogdanm | 0:9b334a45a8ff | 210 | |
| bogdanm | 0:9b334a45a8ff | 211 | /* Stop PWM_CHn */ |
| bogdanm | 0:9b334a45a8ff | 212 | PWM_CHn_Stop(PWM_CHn); |
| bogdanm | 0:9b334a45a8ff | 213 | /* Select Timer/Counter mode as Timer mode */ |
| bogdanm | 0:9b334a45a8ff | 214 | PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode; |
| bogdanm | 0:9b334a45a8ff | 215 | /* Set Prescale register value */ |
| bogdanm | 0:9b334a45a8ff | 216 | PWM_CHn->PR = PWM_CaptureModeInitStruct->PWM_CHn_PR; |
| bogdanm | 0:9b334a45a8ff | 217 | /* Set Match register value */ |
| bogdanm | 0:9b334a45a8ff | 218 | PWM_CHn->MR = PWM_CaptureModeInitStruct->PWM_CHn_MR; |
| bogdanm | 0:9b334a45a8ff | 219 | /* Set Limit register value */ |
| bogdanm | 0:9b334a45a8ff | 220 | PWM_CHn->LR = PWM_CaptureModeInitStruct->PWM_CHn_LR; |
| bogdanm | 0:9b334a45a8ff | 221 | /* Select Up-down mode */ |
| bogdanm | 0:9b334a45a8ff | 222 | PWM_CHn->UDMR = PWM_CaptureModeInitStruct->PWM_CHn_UDMR; |
| bogdanm | 0:9b334a45a8ff | 223 | /* Select Periodic mode */ |
| bogdanm | 0:9b334a45a8ff | 224 | PWM_CHn->PDMR = PWM_CaptureModeInitStruct->PWM_CHn_PDMR; |
| bogdanm | 0:9b334a45a8ff | 225 | /* Select Capture mode */ |
| bogdanm | 0:9b334a45a8ff | 226 | PWM_CHn->CMR = PWM_CaptureModeInitStruct->PWM_CHn_CMR; |
| bogdanm | 0:9b334a45a8ff | 227 | /* External input enable */ |
| bogdanm | 0:9b334a45a8ff | 228 | PWM_CHn->PEEER = PWM_CHn_PEEER_ExtEnable; |
| bogdanm | 0:9b334a45a8ff | 229 | } |
| bogdanm | 0:9b334a45a8ff | 230 | |
| bogdanm | 0:9b334a45a8ff | 231 | void PWM_CounterModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CounterModeInitTypeDef* PWM_CounterModeInitStruct) //complete |
| bogdanm | 0:9b334a45a8ff | 232 | { |
| bogdanm | 0:9b334a45a8ff | 233 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 234 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 235 | |
| bogdanm | 0:9b334a45a8ff | 236 | /* Stop PWM_CHn */ |
| bogdanm | 0:9b334a45a8ff | 237 | PWM_CHn_Stop(PWM_CHn); |
| bogdanm | 0:9b334a45a8ff | 238 | /* Select Timer/Counter mode as Timer mode */ |
| bogdanm | 0:9b334a45a8ff | 239 | PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode; |
| bogdanm | 0:9b334a45a8ff | 240 | /* Set Match register value */ |
| bogdanm | 0:9b334a45a8ff | 241 | PWM_CHn->MR = PWM_CounterModeInitStruct->PWM_CHn_MR; |
| bogdanm | 0:9b334a45a8ff | 242 | /* Set Limit register value */ |
| bogdanm | 0:9b334a45a8ff | 243 | PWM_CHn->LR = PWM_CounterModeInitStruct->PWM_CHn_LR; |
| bogdanm | 0:9b334a45a8ff | 244 | /* Select Up-down mode */ |
| bogdanm | 0:9b334a45a8ff | 245 | PWM_CHn->UDMR = PWM_CounterModeInitStruct->PWM_CHn_UDMR; |
| bogdanm | 0:9b334a45a8ff | 246 | /* Select Periodic mode */ |
| bogdanm | 0:9b334a45a8ff | 247 | PWM_CHn->PDMR = PWM_CounterModeInitStruct->PWM_CHn_PDMR; |
| bogdanm | 0:9b334a45a8ff | 248 | /* Select Counter mode */ |
| bogdanm | 0:9b334a45a8ff | 249 | PWM_CHn->TCMR = PWM_CounterModeInitStruct->PWM_CHn_TCMR; |
| bogdanm | 0:9b334a45a8ff | 250 | /* Enable external input */ |
| bogdanm | 0:9b334a45a8ff | 251 | PWM_CHn->PEEER = PWM_CHn_PEEER_ExtEnable; |
| bogdanm | 0:9b334a45a8ff | 252 | } |
| bogdanm | 0:9b334a45a8ff | 253 | |
| bogdanm | 0:9b334a45a8ff | 254 | void PWM_DeadzoneModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_DeadzoneModeInitTypDef* PWM_DeadzoneModeInitStruct) //complete |
| bogdanm | 0:9b334a45a8ff | 255 | { |
| bogdanm | 0:9b334a45a8ff | 256 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 257 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 258 | assert_param(IS_PWM_PR_FILTER(PWM_DeadzoneModeInitStruct->PWM_CHn_PR)); |
| bogdanm | 0:9b334a45a8ff | 259 | assert_param(IS_PWM_MR_FILTER(PWM_CHn, PWM_DeadzoneModeInitStruct->PWM_CHn_MR)); |
| bogdanm | 0:9b334a45a8ff | 260 | assert_param(IS_PWM_LR_FILTER(PWM_CHn, PWM_DeadzoneModeInitStruct->PWM_CHn_LR)); |
| bogdanm | 0:9b334a45a8ff | 261 | assert_param(IS_PWM_CHn_UDMR(PWM_DeadzoneModeInitStruct->PWM_CHn_UDMR)); |
| bogdanm | 0:9b334a45a8ff | 262 | assert_param(IS_PWM_CHn_PDMR(PWM_DeadzoneModeInitStruct->PWM_CHn_PDMR)); |
| bogdanm | 0:9b334a45a8ff | 263 | assert_param(IS_PWM_Deadznoe(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 264 | |
| bogdanm | 0:9b334a45a8ff | 265 | /* Stop PWM_CHn */ |
| bogdanm | 0:9b334a45a8ff | 266 | PWM_CHn_Stop(PWM_CHn); |
| bogdanm | 0:9b334a45a8ff | 267 | /* Select Timer/Counter mode as Timer mode */ |
| bogdanm | 0:9b334a45a8ff | 268 | PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode; |
| bogdanm | 0:9b334a45a8ff | 269 | /* Set Prescale register value */ |
| bogdanm | 0:9b334a45a8ff | 270 | PWM_CHn->PR = PWM_DeadzoneModeInitStruct->PWM_CHn_PR; |
| bogdanm | 0:9b334a45a8ff | 271 | /* Set Match register value */ |
| bogdanm | 0:9b334a45a8ff | 272 | PWM_CHn->MR = PWM_DeadzoneModeInitStruct->PWM_CHn_MR; |
| bogdanm | 0:9b334a45a8ff | 273 | /* Set Limit register value */ |
| bogdanm | 0:9b334a45a8ff | 274 | PWM_CHn->LR = PWM_DeadzoneModeInitStruct->PWM_CHn_LR; |
| bogdanm | 0:9b334a45a8ff | 275 | /* Select Up-down mode */ |
| bogdanm | 0:9b334a45a8ff | 276 | PWM_CHn->UDMR = PWM_DeadzoneModeInitStruct->PWM_CHn_UDMR; |
| bogdanm | 0:9b334a45a8ff | 277 | /* Select Periodic mode */ |
| bogdanm | 0:9b334a45a8ff | 278 | PWM_CHn->PDMR = PWM_DeadzoneModeInitStruct->PWM_CHn_PDMR; |
| bogdanm | 0:9b334a45a8ff | 279 | /* Enable Dead Zone generation */ |
| bogdanm | 0:9b334a45a8ff | 280 | PWM_CHn->DZER = PWM_CHn_DZER_Enable; |
| bogdanm | 0:9b334a45a8ff | 281 | /* Set Dead Zone Counter */ |
| bogdanm | 0:9b334a45a8ff | 282 | PWM_CHn->DZCR = PWM_DeadzoneModeInitStruct->PWM_CHn_DZCR; |
| bogdanm | 0:9b334a45a8ff | 283 | } |
| bogdanm | 0:9b334a45a8ff | 284 | |
| bogdanm | 0:9b334a45a8ff | 285 | void PWM_CtrlPWMOutput(PWM_CHn_TypeDef* PWM_CHn, uint32_t outputEnDisable ) //complete |
| bogdanm | 0:9b334a45a8ff | 286 | { |
| bogdanm | 0:9b334a45a8ff | 287 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 288 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 289 | assert_param(IS_PWM_Output(outputEnDisable)); |
| bogdanm | 0:9b334a45a8ff | 290 | if( PWM_CHn->DZER ) |
| bogdanm | 0:9b334a45a8ff | 291 | assert_param(IS_PWM_Deadznoe(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 292 | |
| bogdanm | 0:9b334a45a8ff | 293 | /* Stop PWM_CHn */ |
| bogdanm | 0:9b334a45a8ff | 294 | PWM_CHn_Stop(PWM_CHn); |
| bogdanm | 0:9b334a45a8ff | 295 | /*Config PWM output and External input */ |
| bogdanm | 0:9b334a45a8ff | 296 | PWM_CHn->PEEER = outputEnDisable; |
| bogdanm | 0:9b334a45a8ff | 297 | } |
| bogdanm | 0:9b334a45a8ff | 298 | |
| bogdanm | 0:9b334a45a8ff | 299 | void PWM_CtrlPWMOutputEnable(PWM_CHn_TypeDef* PWM_CHn) |
| bogdanm | 0:9b334a45a8ff | 300 | { |
| bogdanm | 0:9b334a45a8ff | 301 | PWM_CtrlPWMOutput(PWM_CHn, PWM_CHn_PEEER_PWMEnable); |
| bogdanm | 0:9b334a45a8ff | 302 | } |
| bogdanm | 0:9b334a45a8ff | 303 | |
| bogdanm | 0:9b334a45a8ff | 304 | void PWM_CtrlPWMOutputDisable(PWM_CHn_TypeDef* PWM_CHn) |
| bogdanm | 0:9b334a45a8ff | 305 | { |
| bogdanm | 0:9b334a45a8ff | 306 | PWM_CtrlPWMOutput(PWM_CHn, PWM_CHn_PEEER_Disable); |
| bogdanm | 0:9b334a45a8ff | 307 | } |
| bogdanm | 0:9b334a45a8ff | 308 | |
| bogdanm | 0:9b334a45a8ff | 309 | void PWM_IntConfig(PWM_CHn_TypeDef* PWM_CHn, FunctionalState state) //complete |
| bogdanm | 0:9b334a45a8ff | 310 | { |
| bogdanm | 0:9b334a45a8ff | 311 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 312 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 313 | |
| bogdanm | 0:9b334a45a8ff | 314 | /* Stop PWM_CHn */ |
| bogdanm | 0:9b334a45a8ff | 315 | PWM_CHn_Stop(PWM_CHn); |
| bogdanm | 0:9b334a45a8ff | 316 | |
| bogdanm | 0:9b334a45a8ff | 317 | if(state == ENABLE) |
| bogdanm | 0:9b334a45a8ff | 318 | { |
| bogdanm | 0:9b334a45a8ff | 319 | if(PWM_CHn == PWM_CH0) { |
| bogdanm | 0:9b334a45a8ff | 320 | PWM->IER |= PWM_IER_IE0_Enable; |
| bogdanm | 0:9b334a45a8ff | 321 | } |
| bogdanm | 0:9b334a45a8ff | 322 | else if(PWM_CHn == PWM_CH1) { |
| bogdanm | 0:9b334a45a8ff | 323 | PWM->IER |= PWM_IER_IE1_Enable; |
| bogdanm | 0:9b334a45a8ff | 324 | } |
| bogdanm | 0:9b334a45a8ff | 325 | else if(PWM_CHn == PWM_CH2) { |
| bogdanm | 0:9b334a45a8ff | 326 | PWM->IER |= PWM_IER_IE2_Enable; |
| bogdanm | 0:9b334a45a8ff | 327 | } |
| bogdanm | 0:9b334a45a8ff | 328 | else if(PWM_CHn == PWM_CH3) { |
| bogdanm | 0:9b334a45a8ff | 329 | PWM->IER |= PWM_IER_IE3_Enable; |
| bogdanm | 0:9b334a45a8ff | 330 | } |
| bogdanm | 0:9b334a45a8ff | 331 | else if(PWM_CHn == PWM_CH4) { |
| bogdanm | 0:9b334a45a8ff | 332 | PWM->IER |= PWM_IER_IE4_Enable; |
| bogdanm | 0:9b334a45a8ff | 333 | } |
| bogdanm | 0:9b334a45a8ff | 334 | else if(PWM_CHn == PWM_CH5) { |
| bogdanm | 0:9b334a45a8ff | 335 | PWM->IER |= PWM_IER_IE5_Enable; |
| bogdanm | 0:9b334a45a8ff | 336 | } |
| bogdanm | 0:9b334a45a8ff | 337 | else if(PWM_CHn == PWM_CH6) { |
| bogdanm | 0:9b334a45a8ff | 338 | PWM->IER |= PWM_IER_IE6_Enable; |
| bogdanm | 0:9b334a45a8ff | 339 | } |
| bogdanm | 0:9b334a45a8ff | 340 | else if(PWM_CHn == PWM_CH7) { |
| bogdanm | 0:9b334a45a8ff | 341 | PWM->IER |= PWM_IER_IE7_Enable; |
| bogdanm | 0:9b334a45a8ff | 342 | } |
| bogdanm | 0:9b334a45a8ff | 343 | } |
| bogdanm | 0:9b334a45a8ff | 344 | else |
| bogdanm | 0:9b334a45a8ff | 345 | { |
| bogdanm | 0:9b334a45a8ff | 346 | if(PWM_CHn == PWM_CH0) { |
| bogdanm | 0:9b334a45a8ff | 347 | PWM->IER &= PWM_IER_IE0_Disable; |
| bogdanm | 0:9b334a45a8ff | 348 | } |
| bogdanm | 0:9b334a45a8ff | 349 | else if(PWM_CHn == PWM_CH1) { |
| bogdanm | 0:9b334a45a8ff | 350 | PWM->IER &= PWM_IER_IE1_Disable; |
| bogdanm | 0:9b334a45a8ff | 351 | } |
| bogdanm | 0:9b334a45a8ff | 352 | else if(PWM_CHn == PWM_CH2) { |
| bogdanm | 0:9b334a45a8ff | 353 | PWM->IER &= PWM_IER_IE2_Disable; |
| bogdanm | 0:9b334a45a8ff | 354 | } |
| bogdanm | 0:9b334a45a8ff | 355 | else if(PWM_CHn == PWM_CH3) { |
| bogdanm | 0:9b334a45a8ff | 356 | PWM->IER &= PWM_IER_IE3_Disable; |
| bogdanm | 0:9b334a45a8ff | 357 | } |
| bogdanm | 0:9b334a45a8ff | 358 | else if(PWM_CHn == PWM_CH4) { |
| bogdanm | 0:9b334a45a8ff | 359 | PWM->IER &= PWM_IER_IE4_Disable; |
| bogdanm | 0:9b334a45a8ff | 360 | } |
| bogdanm | 0:9b334a45a8ff | 361 | else if(PWM_CHn == PWM_CH5) { |
| bogdanm | 0:9b334a45a8ff | 362 | PWM->IER &= PWM_IER_IE5_Disable; |
| bogdanm | 0:9b334a45a8ff | 363 | } |
| bogdanm | 0:9b334a45a8ff | 364 | else if(PWM_CHn == PWM_CH6) { |
| bogdanm | 0:9b334a45a8ff | 365 | PWM->IER &= PWM_IER_IE6_Disable; |
| bogdanm | 0:9b334a45a8ff | 366 | } |
| bogdanm | 0:9b334a45a8ff | 367 | else if(PWM_CHn == PWM_CH7) { |
| bogdanm | 0:9b334a45a8ff | 368 | PWM->IER &= PWM_IER_IE7_Disable; |
| bogdanm | 0:9b334a45a8ff | 369 | } |
| bogdanm | 0:9b334a45a8ff | 370 | } |
| bogdanm | 0:9b334a45a8ff | 371 | } |
| bogdanm | 0:9b334a45a8ff | 372 | |
| bogdanm | 0:9b334a45a8ff | 373 | FlagStatus PWM_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn) |
| bogdanm | 0:9b334a45a8ff | 374 | { |
| bogdanm | 0:9b334a45a8ff | 375 | FlagStatus ret_val = RESET; |
| bogdanm | 0:9b334a45a8ff | 376 | |
| bogdanm | 0:9b334a45a8ff | 377 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 378 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 379 | |
| bogdanm | 0:9b334a45a8ff | 380 | if(PWM_CHn == PWM_CH0) { |
| bogdanm | 0:9b334a45a8ff | 381 | ret_val = (FlagStatus)((PWM->IER & 0x01) >> 0); |
| bogdanm | 0:9b334a45a8ff | 382 | } |
| bogdanm | 0:9b334a45a8ff | 383 | else if(PWM_CHn == PWM_CH1) { |
| bogdanm | 0:9b334a45a8ff | 384 | ret_val = (FlagStatus)((PWM->IER & 0x02) >> 1); |
| bogdanm | 0:9b334a45a8ff | 385 | } |
| bogdanm | 0:9b334a45a8ff | 386 | else if(PWM_CHn == PWM_CH2) { |
| bogdanm | 0:9b334a45a8ff | 387 | ret_val = (FlagStatus)((PWM->IER & 0x04) >> 2); |
| bogdanm | 0:9b334a45a8ff | 388 | } |
| bogdanm | 0:9b334a45a8ff | 389 | else if(PWM_CHn == PWM_CH3) { |
| bogdanm | 0:9b334a45a8ff | 390 | ret_val = (FlagStatus)((PWM->IER & 0x08) >> 3); |
| bogdanm | 0:9b334a45a8ff | 391 | } |
| bogdanm | 0:9b334a45a8ff | 392 | else if(PWM_CHn == PWM_CH4) { |
| bogdanm | 0:9b334a45a8ff | 393 | ret_val = (FlagStatus)((PWM->IER & 0x10) >> 4); |
| bogdanm | 0:9b334a45a8ff | 394 | } |
| bogdanm | 0:9b334a45a8ff | 395 | else if(PWM_CHn == PWM_CH5) { |
| bogdanm | 0:9b334a45a8ff | 396 | ret_val = (FlagStatus)((PWM->IER & 0x20) >> 5); |
| bogdanm | 0:9b334a45a8ff | 397 | } |
| bogdanm | 0:9b334a45a8ff | 398 | else if(PWM_CHn == PWM_CH6) { |
| bogdanm | 0:9b334a45a8ff | 399 | ret_val = (FlagStatus)((PWM->IER & 0x40) >> 6); |
| bogdanm | 0:9b334a45a8ff | 400 | } |
| bogdanm | 0:9b334a45a8ff | 401 | else if(PWM_CHn == PWM_CH7) { |
| bogdanm | 0:9b334a45a8ff | 402 | ret_val = (FlagStatus)((PWM->IER & 0x80) >> 7); |
| bogdanm | 0:9b334a45a8ff | 403 | } |
| bogdanm | 0:9b334a45a8ff | 404 | |
| bogdanm | 0:9b334a45a8ff | 405 | return ret_val; |
| bogdanm | 0:9b334a45a8ff | 406 | } |
| bogdanm | 0:9b334a45a8ff | 407 | |
| bogdanm | 0:9b334a45a8ff | 408 | void PWM_CHn_IntConfig(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_IER, FunctionalState state) //complete |
| bogdanm | 0:9b334a45a8ff | 409 | { |
| bogdanm | 0:9b334a45a8ff | 410 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 411 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 412 | |
| bogdanm | 0:9b334a45a8ff | 413 | |
| bogdanm | 0:9b334a45a8ff | 414 | assert_param(IS_PWM_CHn_IER(PWM_CHn_IER)); |
| bogdanm | 0:9b334a45a8ff | 415 | |
| bogdanm | 0:9b334a45a8ff | 416 | /* Stop PWM_CHn */ |
| bogdanm | 0:9b334a45a8ff | 417 | PWM_CHn_Stop(PWM_CHn); |
| bogdanm | 0:9b334a45a8ff | 418 | |
| bogdanm | 0:9b334a45a8ff | 419 | if(state == ENABLE) |
| bogdanm | 0:9b334a45a8ff | 420 | PWM_CHn->IER |= PWM_CHn_IER; |
| bogdanm | 0:9b334a45a8ff | 421 | else |
| bogdanm | 0:9b334a45a8ff | 422 | PWM_CHn->IER &= ~PWM_CHn_IER; |
| bogdanm | 0:9b334a45a8ff | 423 | } |
| bogdanm | 0:9b334a45a8ff | 424 | |
| bogdanm | 0:9b334a45a8ff | 425 | uint32_t PWM_CHn_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn) //complete |
| bogdanm | 0:9b334a45a8ff | 426 | { |
| bogdanm | 0:9b334a45a8ff | 427 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 428 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 429 | |
| bogdanm | 0:9b334a45a8ff | 430 | return PWM_CHn->IER; |
| bogdanm | 0:9b334a45a8ff | 431 | } |
| bogdanm | 0:9b334a45a8ff | 432 | |
| bogdanm | 0:9b334a45a8ff | 433 | uint32_t PWM_CHn_GetIntFlagStatus(PWM_CHn_TypeDef* PWM_CHn) //complete |
| bogdanm | 0:9b334a45a8ff | 434 | { |
| bogdanm | 0:9b334a45a8ff | 435 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 436 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 437 | |
| bogdanm | 0:9b334a45a8ff | 438 | return PWM_CHn->IR; |
| bogdanm | 0:9b334a45a8ff | 439 | } |
| bogdanm | 0:9b334a45a8ff | 440 | |
| bogdanm | 0:9b334a45a8ff | 441 | void PWM_CHn_ClearInt(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_ICR) |
| bogdanm | 0:9b334a45a8ff | 442 | { |
| bogdanm | 0:9b334a45a8ff | 443 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 444 | |
| bogdanm | 0:9b334a45a8ff | 445 | PWM_CHn->ICR = PWM_CHn_ICR; |
| bogdanm | 0:9b334a45a8ff | 446 | } |
| bogdanm | 0:9b334a45a8ff | 447 | |
| bogdanm | 0:9b334a45a8ff | 448 | void PWM_CHn_Start(PWM_CHn_TypeDef* PWM_CHn) //complete |
| bogdanm | 0:9b334a45a8ff | 449 | { |
| bogdanm | 0:9b334a45a8ff | 450 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 451 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 452 | |
| bogdanm | 0:9b334a45a8ff | 453 | /* Set Start Stop register */ |
| bogdanm | 0:9b334a45a8ff | 454 | if(PWM_CHn == PWM_CH0) { |
| bogdanm | 0:9b334a45a8ff | 455 | PWM->SSR |= PWM_SSR_SS0_Start; |
| bogdanm | 0:9b334a45a8ff | 456 | } |
| bogdanm | 0:9b334a45a8ff | 457 | else if(PWM_CHn == PWM_CH1) { |
| bogdanm | 0:9b334a45a8ff | 458 | PWM->SSR |= PWM_SSR_SS1_Start; |
| bogdanm | 0:9b334a45a8ff | 459 | } |
| bogdanm | 0:9b334a45a8ff | 460 | else if(PWM_CHn == PWM_CH2) { |
| bogdanm | 0:9b334a45a8ff | 461 | PWM->SSR |= PWM_SSR_SS2_Start; |
| bogdanm | 0:9b334a45a8ff | 462 | } |
| bogdanm | 0:9b334a45a8ff | 463 | else if(PWM_CHn == PWM_CH3) { |
| bogdanm | 0:9b334a45a8ff | 464 | PWM->SSR |= PWM_SSR_SS3_Start; |
| bogdanm | 0:9b334a45a8ff | 465 | } |
| bogdanm | 0:9b334a45a8ff | 466 | else if(PWM_CHn == PWM_CH4) { |
| bogdanm | 0:9b334a45a8ff | 467 | PWM->SSR |= PWM_SSR_SS4_Start; |
| bogdanm | 0:9b334a45a8ff | 468 | } |
| bogdanm | 0:9b334a45a8ff | 469 | else if(PWM_CHn == PWM_CH5) { |
| bogdanm | 0:9b334a45a8ff | 470 | PWM->SSR |= PWM_SSR_SS5_Start; |
| bogdanm | 0:9b334a45a8ff | 471 | } |
| bogdanm | 0:9b334a45a8ff | 472 | else if(PWM_CHn == PWM_CH6) { |
| bogdanm | 0:9b334a45a8ff | 473 | PWM->SSR |= PWM_SSR_SS6_Start; |
| bogdanm | 0:9b334a45a8ff | 474 | } |
| bogdanm | 0:9b334a45a8ff | 475 | else if(PWM_CHn == PWM_CH7) { |
| bogdanm | 0:9b334a45a8ff | 476 | PWM->SSR |= PWM_SSR_SS7_Start; |
| bogdanm | 0:9b334a45a8ff | 477 | } |
| bogdanm | 0:9b334a45a8ff | 478 | } |
| bogdanm | 0:9b334a45a8ff | 479 | |
| bogdanm | 0:9b334a45a8ff | 480 | void PWM_Multi_Start(uint32_t ssr_bit_flag) //complete |
| bogdanm | 0:9b334a45a8ff | 481 | { |
| bogdanm | 0:9b334a45a8ff | 482 | /* Set Start Stop register */ |
| bogdanm | 0:9b334a45a8ff | 483 | PWM->SSR |= ssr_bit_flag; |
| bogdanm | 0:9b334a45a8ff | 484 | } |
| bogdanm | 0:9b334a45a8ff | 485 | |
| bogdanm | 0:9b334a45a8ff | 486 | void PWM_CHn_Stop(PWM_CHn_TypeDef* PWM_CHn) //complete |
| bogdanm | 0:9b334a45a8ff | 487 | { |
| bogdanm | 0:9b334a45a8ff | 488 | /* Reset Start Stop register */ |
| bogdanm | 0:9b334a45a8ff | 489 | if(PWM_CHn == PWM_CH0) { |
| bogdanm | 0:9b334a45a8ff | 490 | PWM->SSR &= PWM_SSR_SS0_Stop; |
| bogdanm | 0:9b334a45a8ff | 491 | } |
| bogdanm | 0:9b334a45a8ff | 492 | else if(PWM_CHn == PWM_CH1) { |
| bogdanm | 0:9b334a45a8ff | 493 | PWM->SSR &= PWM_SSR_SS1_Stop; |
| bogdanm | 0:9b334a45a8ff | 494 | } |
| bogdanm | 0:9b334a45a8ff | 495 | else if(PWM_CHn == PWM_CH2) { |
| bogdanm | 0:9b334a45a8ff | 496 | PWM->SSR &= PWM_SSR_SS2_Stop; |
| bogdanm | 0:9b334a45a8ff | 497 | } |
| bogdanm | 0:9b334a45a8ff | 498 | else if(PWM_CHn == PWM_CH3) { |
| bogdanm | 0:9b334a45a8ff | 499 | PWM->SSR &= PWM_SSR_SS3_Stop; |
| bogdanm | 0:9b334a45a8ff | 500 | } |
| bogdanm | 0:9b334a45a8ff | 501 | else if(PWM_CHn == PWM_CH4) { |
| bogdanm | 0:9b334a45a8ff | 502 | PWM->SSR &= PWM_SSR_SS4_Stop; |
| bogdanm | 0:9b334a45a8ff | 503 | } |
| bogdanm | 0:9b334a45a8ff | 504 | else if(PWM_CHn == PWM_CH5) { |
| bogdanm | 0:9b334a45a8ff | 505 | PWM->SSR &= PWM_SSR_SS5_Stop; |
| bogdanm | 0:9b334a45a8ff | 506 | } |
| bogdanm | 0:9b334a45a8ff | 507 | else if(PWM_CHn == PWM_CH6) { |
| bogdanm | 0:9b334a45a8ff | 508 | PWM->SSR &= PWM_SSR_SS6_Stop; |
| bogdanm | 0:9b334a45a8ff | 509 | } |
| bogdanm | 0:9b334a45a8ff | 510 | else if(PWM_CHn == PWM_CH7) { |
| bogdanm | 0:9b334a45a8ff | 511 | PWM->SSR &= PWM_SSR_SS7_Stop; |
| bogdanm | 0:9b334a45a8ff | 512 | } |
| bogdanm | 0:9b334a45a8ff | 513 | } |
| bogdanm | 0:9b334a45a8ff | 514 | |
| bogdanm | 0:9b334a45a8ff | 515 | void PWM_Multi_Stop(uint32_t ssr_bit_flag) //complete |
| bogdanm | 0:9b334a45a8ff | 516 | { |
| bogdanm | 0:9b334a45a8ff | 517 | /* Reset Start Stop register */ |
| bogdanm | 0:9b334a45a8ff | 518 | PWM->SSR &= ~ssr_bit_flag; |
| bogdanm | 0:9b334a45a8ff | 519 | } |
| bogdanm | 0:9b334a45a8ff | 520 | |
| bogdanm | 0:9b334a45a8ff | 521 | void PWM_CHn_Pause(PWM_CHn_TypeDef* PWM_CHn) |
| bogdanm | 0:9b334a45a8ff | 522 | { |
| bogdanm | 0:9b334a45a8ff | 523 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 524 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 525 | |
| bogdanm | 0:9b334a45a8ff | 526 | /* Set Pause register */ |
| bogdanm | 0:9b334a45a8ff | 527 | if(PWM_CHn == PWM_CH0) { |
| bogdanm | 0:9b334a45a8ff | 528 | PWM->PSR |= PWM_PSR_PS0_Pause; |
| bogdanm | 0:9b334a45a8ff | 529 | } |
| bogdanm | 0:9b334a45a8ff | 530 | else if(PWM_CHn == PWM_CH1) { |
| bogdanm | 0:9b334a45a8ff | 531 | PWM->PSR |= PWM_PSR_PS1_Pause; |
| bogdanm | 0:9b334a45a8ff | 532 | } |
| bogdanm | 0:9b334a45a8ff | 533 | else if(PWM_CHn == PWM_CH2) { |
| bogdanm | 0:9b334a45a8ff | 534 | PWM->PSR |= PWM_PSR_PS2_Pause; |
| bogdanm | 0:9b334a45a8ff | 535 | } |
| bogdanm | 0:9b334a45a8ff | 536 | else if(PWM_CHn == PWM_CH3) { |
| bogdanm | 0:9b334a45a8ff | 537 | PWM->PSR |= PWM_PSR_PS3_Pause; |
| bogdanm | 0:9b334a45a8ff | 538 | } |
| bogdanm | 0:9b334a45a8ff | 539 | else if(PWM_CHn == PWM_CH4) { |
| bogdanm | 0:9b334a45a8ff | 540 | PWM->PSR |= PWM_PSR_PS4_Pause; |
| bogdanm | 0:9b334a45a8ff | 541 | } |
| bogdanm | 0:9b334a45a8ff | 542 | else if(PWM_CHn == PWM_CH5) { |
| bogdanm | 0:9b334a45a8ff | 543 | PWM->PSR |= PWM_PSR_PS5_Pause; |
| bogdanm | 0:9b334a45a8ff | 544 | } |
| bogdanm | 0:9b334a45a8ff | 545 | else if(PWM_CHn == PWM_CH6) { |
| bogdanm | 0:9b334a45a8ff | 546 | PWM->PSR |= PWM_PSR_PS6_Pause; |
| bogdanm | 0:9b334a45a8ff | 547 | } |
| bogdanm | 0:9b334a45a8ff | 548 | else if(PWM_CHn == PWM_CH7) { |
| bogdanm | 0:9b334a45a8ff | 549 | PWM->PSR |= PWM_PSR_PS7_Pause; |
| bogdanm | 0:9b334a45a8ff | 550 | } |
| bogdanm | 0:9b334a45a8ff | 551 | } |
| bogdanm | 0:9b334a45a8ff | 552 | |
| bogdanm | 0:9b334a45a8ff | 553 | void PWM_Multi_Pause(uint32_t psr_bit_flag) |
| bogdanm | 0:9b334a45a8ff | 554 | { |
| bogdanm | 0:9b334a45a8ff | 555 | PWM->PSR |= psr_bit_flag; |
| bogdanm | 0:9b334a45a8ff | 556 | } |
| bogdanm | 0:9b334a45a8ff | 557 | |
| bogdanm | 0:9b334a45a8ff | 558 | void PWM_CHn_Restart(PWM_CHn_TypeDef* PWM_CHn) |
| bogdanm | 0:9b334a45a8ff | 559 | { |
| bogdanm | 0:9b334a45a8ff | 560 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 561 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 562 | |
| bogdanm | 0:9b334a45a8ff | 563 | /* Reset Pause register */ |
| bogdanm | 0:9b334a45a8ff | 564 | if(PWM_CHn == PWM_CH0) { |
| bogdanm | 0:9b334a45a8ff | 565 | PWM->PSR &= PWM_PSR_PS0_Restart; |
| bogdanm | 0:9b334a45a8ff | 566 | } |
| bogdanm | 0:9b334a45a8ff | 567 | else if(PWM_CHn == PWM_CH1) { |
| bogdanm | 0:9b334a45a8ff | 568 | PWM->PSR &= PWM_PSR_PS1_Restart; |
| bogdanm | 0:9b334a45a8ff | 569 | } |
| bogdanm | 0:9b334a45a8ff | 570 | else if(PWM_CHn == PWM_CH2) { |
| bogdanm | 0:9b334a45a8ff | 571 | PWM->PSR &= PWM_PSR_PS2_Restart; |
| bogdanm | 0:9b334a45a8ff | 572 | } |
| bogdanm | 0:9b334a45a8ff | 573 | else if(PWM_CHn == PWM_CH3) { |
| bogdanm | 0:9b334a45a8ff | 574 | PWM->PSR &= PWM_PSR_PS3_Restart; |
| bogdanm | 0:9b334a45a8ff | 575 | } |
| bogdanm | 0:9b334a45a8ff | 576 | else if(PWM_CHn == PWM_CH4) { |
| bogdanm | 0:9b334a45a8ff | 577 | PWM->PSR &= PWM_PSR_PS4_Restart; |
| bogdanm | 0:9b334a45a8ff | 578 | } |
| bogdanm | 0:9b334a45a8ff | 579 | else if(PWM_CHn == PWM_CH5) { |
| bogdanm | 0:9b334a45a8ff | 580 | PWM->PSR &= PWM_PSR_PS5_Restart; |
| bogdanm | 0:9b334a45a8ff | 581 | } |
| bogdanm | 0:9b334a45a8ff | 582 | else if(PWM_CHn == PWM_CH6) { |
| bogdanm | 0:9b334a45a8ff | 583 | PWM->PSR &= PWM_PSR_PS6_Restart; |
| bogdanm | 0:9b334a45a8ff | 584 | } |
| bogdanm | 0:9b334a45a8ff | 585 | else if(PWM_CHn == PWM_CH7) { |
| bogdanm | 0:9b334a45a8ff | 586 | PWM->PSR &= PWM_PSR_PS7_Restart; |
| bogdanm | 0:9b334a45a8ff | 587 | } |
| bogdanm | 0:9b334a45a8ff | 588 | } |
| bogdanm | 0:9b334a45a8ff | 589 | |
| bogdanm | 0:9b334a45a8ff | 590 | void PWM_Multi_Restart(uint32_t psr_bit_flag) |
| bogdanm | 0:9b334a45a8ff | 591 | { |
| bogdanm | 0:9b334a45a8ff | 592 | PWM->PSR &= ~psr_bit_flag; |
| bogdanm | 0:9b334a45a8ff | 593 | } |
| bogdanm | 0:9b334a45a8ff | 594 | |
| bogdanm | 0:9b334a45a8ff | 595 | |
| bogdanm | 0:9b334a45a8ff | 596 | uint32_t PWM_CHn_GetTCR(PWM_CHn_TypeDef* PWM_CHn) //complete |
| bogdanm | 0:9b334a45a8ff | 597 | { |
| bogdanm | 0:9b334a45a8ff | 598 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 599 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 600 | |
| bogdanm | 0:9b334a45a8ff | 601 | return PWM_CHn->TCR; |
| bogdanm | 0:9b334a45a8ff | 602 | } |
| bogdanm | 0:9b334a45a8ff | 603 | |
| bogdanm | 0:9b334a45a8ff | 604 | uint32_t PWM_CHn_GetPCR(PWM_CHn_TypeDef* PWM_CHn) //complete |
| bogdanm | 0:9b334a45a8ff | 605 | { |
| bogdanm | 0:9b334a45a8ff | 606 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 607 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 608 | |
| bogdanm | 0:9b334a45a8ff | 609 | return PWM_CHn->PCR; |
| bogdanm | 0:9b334a45a8ff | 610 | } |
| bogdanm | 0:9b334a45a8ff | 611 | |
| bogdanm | 0:9b334a45a8ff | 612 | uint32_t PWM_CHn_GetPR(PWM_CHn_TypeDef* PWM_CHn) //complete |
| bogdanm | 0:9b334a45a8ff | 613 | { |
| bogdanm | 0:9b334a45a8ff | 614 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 615 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 616 | |
| bogdanm | 0:9b334a45a8ff | 617 | return PWM_CHn->PR; |
| bogdanm | 0:9b334a45a8ff | 618 | } |
| bogdanm | 0:9b334a45a8ff | 619 | |
| bogdanm | 0:9b334a45a8ff | 620 | void PWM_CHn_SetPR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PR) //complete |
| bogdanm | 0:9b334a45a8ff | 621 | { |
| bogdanm | 0:9b334a45a8ff | 622 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 623 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 624 | assert_param(IS_PWM_PR_FILTER(PR)); |
| bogdanm | 0:9b334a45a8ff | 625 | |
| bogdanm | 0:9b334a45a8ff | 626 | PWM_CHn->PR = PR; |
| bogdanm | 0:9b334a45a8ff | 627 | } |
| bogdanm | 0:9b334a45a8ff | 628 | |
| bogdanm | 0:9b334a45a8ff | 629 | uint32_t PWM_CHn_GetMR(PWM_CHn_TypeDef* PWM_CHn) //complete |
| bogdanm | 0:9b334a45a8ff | 630 | { |
| bogdanm | 0:9b334a45a8ff | 631 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 632 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 633 | |
| bogdanm | 0:9b334a45a8ff | 634 | return PWM_CHn->MR; |
| bogdanm | 0:9b334a45a8ff | 635 | } |
| bogdanm | 0:9b334a45a8ff | 636 | |
| bogdanm | 0:9b334a45a8ff | 637 | void PWM_CHn_SetMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t MR) //complete |
| bogdanm | 0:9b334a45a8ff | 638 | { |
| bogdanm | 0:9b334a45a8ff | 639 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 640 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 641 | |
| bogdanm | 0:9b334a45a8ff | 642 | PWM_CHn->MR = MR; |
| bogdanm | 0:9b334a45a8ff | 643 | } |
| bogdanm | 0:9b334a45a8ff | 644 | |
| bogdanm | 0:9b334a45a8ff | 645 | uint32_t PWM_CHn_GetLR(PWM_CHn_TypeDef* PWM_CHn) //complete |
| bogdanm | 0:9b334a45a8ff | 646 | { |
| bogdanm | 0:9b334a45a8ff | 647 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 648 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 649 | |
| bogdanm | 0:9b334a45a8ff | 650 | return PWM_CHn->LR; |
| bogdanm | 0:9b334a45a8ff | 651 | } |
| bogdanm | 0:9b334a45a8ff | 652 | |
| bogdanm | 0:9b334a45a8ff | 653 | void PWM_CHn_SetLR(PWM_CHn_TypeDef* PWM_CHn, uint32_t LR) //complete |
| bogdanm | 0:9b334a45a8ff | 654 | { |
| bogdanm | 0:9b334a45a8ff | 655 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 656 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 657 | |
| bogdanm | 0:9b334a45a8ff | 658 | PWM_CHn->LR = LR; |
| bogdanm | 0:9b334a45a8ff | 659 | } |
| bogdanm | 0:9b334a45a8ff | 660 | |
| bogdanm | 0:9b334a45a8ff | 661 | uint32_t PWM_CHn_GetUDMR(PWM_CHn_TypeDef* PWM_CHn) //complete |
| bogdanm | 0:9b334a45a8ff | 662 | { |
| bogdanm | 0:9b334a45a8ff | 663 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 664 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 665 | |
| bogdanm | 0:9b334a45a8ff | 666 | return PWM_CHn->UDMR; |
| bogdanm | 0:9b334a45a8ff | 667 | } |
| bogdanm | 0:9b334a45a8ff | 668 | |
| bogdanm | 0:9b334a45a8ff | 669 | void PWM_CHn_SetUDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t UDMR) //complete |
| bogdanm | 0:9b334a45a8ff | 670 | { |
| bogdanm | 0:9b334a45a8ff | 671 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 672 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 673 | assert_param(IS_PWM_CHn_UDMR(UDMR)); |
| bogdanm | 0:9b334a45a8ff | 674 | |
| bogdanm | 0:9b334a45a8ff | 675 | PWM_CHn->UDMR = UDMR; |
| bogdanm | 0:9b334a45a8ff | 676 | } |
| bogdanm | 0:9b334a45a8ff | 677 | |
| bogdanm | 0:9b334a45a8ff | 678 | uint32_t PWM_CHn_GetTCMR(PWM_CHn_TypeDef* PWM_CHn) //complete |
| bogdanm | 0:9b334a45a8ff | 679 | { |
| bogdanm | 0:9b334a45a8ff | 680 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 681 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 682 | |
| bogdanm | 0:9b334a45a8ff | 683 | return PWM_CHn->TCMR; |
| bogdanm | 0:9b334a45a8ff | 684 | } |
| bogdanm | 0:9b334a45a8ff | 685 | |
| bogdanm | 0:9b334a45a8ff | 686 | void PWM_CHn_SetTCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t TCMR) //complete |
| bogdanm | 0:9b334a45a8ff | 687 | { |
| bogdanm | 0:9b334a45a8ff | 688 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 689 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 690 | assert_param(IS_PWM_CHn_TCMR(TCMR)); |
| bogdanm | 0:9b334a45a8ff | 691 | |
| bogdanm | 0:9b334a45a8ff | 692 | PWM_CHn->TCMR = TCMR; |
| bogdanm | 0:9b334a45a8ff | 693 | } |
| bogdanm | 0:9b334a45a8ff | 694 | |
| bogdanm | 0:9b334a45a8ff | 695 | uint32_t PWM_CHn_GetPEEER(PWM_CHn_TypeDef* PWM_CHn) //complete |
| bogdanm | 0:9b334a45a8ff | 696 | { |
| bogdanm | 0:9b334a45a8ff | 697 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 698 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 699 | |
| bogdanm | 0:9b334a45a8ff | 700 | return PWM_CHn->PEEER; |
| bogdanm | 0:9b334a45a8ff | 701 | } |
| bogdanm | 0:9b334a45a8ff | 702 | |
| bogdanm | 0:9b334a45a8ff | 703 | void PWM_CHn_SetPEEER(PWM_CHn_TypeDef* PWM_CHn, uint32_t PEEER) //complete |
| bogdanm | 0:9b334a45a8ff | 704 | { |
| bogdanm | 0:9b334a45a8ff | 705 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 706 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 707 | assert_param(IS_PWM_CHn_PEEER(PEEER)); |
| bogdanm | 0:9b334a45a8ff | 708 | |
| bogdanm | 0:9b334a45a8ff | 709 | PWM_CHn->PEEER = PEEER; |
| bogdanm | 0:9b334a45a8ff | 710 | } |
| bogdanm | 0:9b334a45a8ff | 711 | |
| bogdanm | 0:9b334a45a8ff | 712 | uint32_t PWM_CHn_GetCMR(PWM_CHn_TypeDef* PWM_CHn) //complete |
| bogdanm | 0:9b334a45a8ff | 713 | { |
| bogdanm | 0:9b334a45a8ff | 714 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 715 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 716 | |
| bogdanm | 0:9b334a45a8ff | 717 | return PWM_CHn->CMR; |
| bogdanm | 0:9b334a45a8ff | 718 | } |
| bogdanm | 0:9b334a45a8ff | 719 | |
| bogdanm | 0:9b334a45a8ff | 720 | void PWM_CHn_SetCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t CMR) //complete |
| bogdanm | 0:9b334a45a8ff | 721 | { |
| bogdanm | 0:9b334a45a8ff | 722 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 723 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 724 | assert_param(IS_PWM_CHn_CMR(CMR)); |
| bogdanm | 0:9b334a45a8ff | 725 | |
| bogdanm | 0:9b334a45a8ff | 726 | PWM_CHn->CMR = CMR; |
| bogdanm | 0:9b334a45a8ff | 727 | } |
| bogdanm | 0:9b334a45a8ff | 728 | |
| bogdanm | 0:9b334a45a8ff | 729 | uint32_t PWM_CHn_GetCR(PWM_CHn_TypeDef* PWM_CHn) |
| bogdanm | 0:9b334a45a8ff | 730 | { |
| bogdanm | 0:9b334a45a8ff | 731 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 732 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 733 | |
| bogdanm | 0:9b334a45a8ff | 734 | return PWM_CHn->CR; |
| bogdanm | 0:9b334a45a8ff | 735 | } |
| bogdanm | 0:9b334a45a8ff | 736 | |
| bogdanm | 0:9b334a45a8ff | 737 | uint32_t PWM_CHn_GetPDMR(PWM_CHn_TypeDef* PWM_CHn) //complete |
| bogdanm | 0:9b334a45a8ff | 738 | { |
| bogdanm | 0:9b334a45a8ff | 739 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 740 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 741 | |
| bogdanm | 0:9b334a45a8ff | 742 | return PWM_CHn->PDMR; |
| bogdanm | 0:9b334a45a8ff | 743 | } |
| bogdanm | 0:9b334a45a8ff | 744 | |
| bogdanm | 0:9b334a45a8ff | 745 | void PWM_CHn_SetPDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PDMR) //complete |
| bogdanm | 0:9b334a45a8ff | 746 | { |
| bogdanm | 0:9b334a45a8ff | 747 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 748 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 749 | assert_param(IS_PWM_CHn_PDMR(PDMR)); |
| bogdanm | 0:9b334a45a8ff | 750 | |
| bogdanm | 0:9b334a45a8ff | 751 | PWM_CHn->PDMR = PDMR; |
| bogdanm | 0:9b334a45a8ff | 752 | } |
| bogdanm | 0:9b334a45a8ff | 753 | |
| bogdanm | 0:9b334a45a8ff | 754 | uint32_t PWM_CHn_GetDZER(PWM_CHn_TypeDef* PWM_CHn) //complete |
| bogdanm | 0:9b334a45a8ff | 755 | { |
| bogdanm | 0:9b334a45a8ff | 756 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 757 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 758 | |
| bogdanm | 0:9b334a45a8ff | 759 | return PWM_CHn->DZER; |
| bogdanm | 0:9b334a45a8ff | 760 | } |
| bogdanm | 0:9b334a45a8ff | 761 | |
| bogdanm | 0:9b334a45a8ff | 762 | void PWM_CHn_SetDZER(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZER) //complete |
| bogdanm | 0:9b334a45a8ff | 763 | { |
| bogdanm | 0:9b334a45a8ff | 764 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 765 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 766 | assert_param(IS_PWM_CHn_DZER(DZER)); |
| bogdanm | 0:9b334a45a8ff | 767 | |
| bogdanm | 0:9b334a45a8ff | 768 | PWM_CHn->DZER = DZER; |
| bogdanm | 0:9b334a45a8ff | 769 | } |
| bogdanm | 0:9b334a45a8ff | 770 | |
| bogdanm | 0:9b334a45a8ff | 771 | uint32_t PWM_CHn_GetDZCR(PWM_CHn_TypeDef* PWM_CHn) //complete |
| bogdanm | 0:9b334a45a8ff | 772 | { |
| bogdanm | 0:9b334a45a8ff | 773 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 774 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 775 | |
| bogdanm | 0:9b334a45a8ff | 776 | return PWM_CHn->DZCR; |
| bogdanm | 0:9b334a45a8ff | 777 | } |
| bogdanm | 0:9b334a45a8ff | 778 | |
| bogdanm | 0:9b334a45a8ff | 779 | void PWM_CHn_SetDZCR(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZCR) //complete |
| bogdanm | 0:9b334a45a8ff | 780 | { |
| bogdanm | 0:9b334a45a8ff | 781 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 782 | assert_param(IS_PWM_ALL_CH(PWM_CHn)); |
| bogdanm | 0:9b334a45a8ff | 783 | assert_param(IS_PWM_CHn_DZCR_FILTER(DZCR)); |
| bogdanm | 0:9b334a45a8ff | 784 | |
| bogdanm | 0:9b334a45a8ff | 785 | PWM_CHn->DZCR = DZCR; |
| bogdanm | 0:9b334a45a8ff | 786 | } |
| bogdanm | 0:9b334a45a8ff | 787 | |
| bogdanm | 0:9b334a45a8ff | 788 | void PWM_CH0_ClearMatchInt(void) |
| bogdanm | 0:9b334a45a8ff | 789 | { |
| bogdanm | 0:9b334a45a8ff | 790 | PWM_CHn_ClearInt(PWM_CH0, PWM_CHn_ICR_MatchInterruptClear); |
| bogdanm | 0:9b334a45a8ff | 791 | } |
| bogdanm | 0:9b334a45a8ff | 792 | |
| bogdanm | 0:9b334a45a8ff | 793 | void PWM_CH0_ClearOverflowInt(void) |
| bogdanm | 0:9b334a45a8ff | 794 | { |
| bogdanm | 0:9b334a45a8ff | 795 | PWM_CHn_ClearInt(PWM_CH0, PWM_CHn_ICR_OverflowInterruptClear); |
| bogdanm | 0:9b334a45a8ff | 796 | } |
| bogdanm | 0:9b334a45a8ff | 797 | |
| bogdanm | 0:9b334a45a8ff | 798 | void PWM_CH0_ClearCaptureInt(void) |
| bogdanm | 0:9b334a45a8ff | 799 | { |
| bogdanm | 0:9b334a45a8ff | 800 | PWM_CHn_ClearInt(PWM_CH0, PWM_CHn_ICR_CaptureInterruptClear); |
| bogdanm | 0:9b334a45a8ff | 801 | } |
| bogdanm | 0:9b334a45a8ff | 802 | |
| bogdanm | 0:9b334a45a8ff | 803 | void PWM_CH1_ClearMatchInt(void) |
| bogdanm | 0:9b334a45a8ff | 804 | { |
| bogdanm | 0:9b334a45a8ff | 805 | PWM_CHn_ClearInt(PWM_CH1, PWM_CHn_ICR_MatchInterruptClear); |
| bogdanm | 0:9b334a45a8ff | 806 | } |
| bogdanm | 0:9b334a45a8ff | 807 | |
| bogdanm | 0:9b334a45a8ff | 808 | void PWM_CH1_ClearOverflowInt(void) |
| bogdanm | 0:9b334a45a8ff | 809 | { |
| bogdanm | 0:9b334a45a8ff | 810 | PWM_CHn_ClearInt(PWM_CH1, PWM_CHn_ICR_OverflowInterruptClear); |
| bogdanm | 0:9b334a45a8ff | 811 | } |
| bogdanm | 0:9b334a45a8ff | 812 | |
| bogdanm | 0:9b334a45a8ff | 813 | void PWM_CH1_ClearCaptureInt(void) |
| bogdanm | 0:9b334a45a8ff | 814 | { |
| bogdanm | 0:9b334a45a8ff | 815 | PWM_CHn_ClearInt(PWM_CH1, PWM_CHn_ICR_CaptureInterruptClear); |
| bogdanm | 0:9b334a45a8ff | 816 | } |
| bogdanm | 0:9b334a45a8ff | 817 | |
| bogdanm | 0:9b334a45a8ff | 818 | void PWM_CH2_ClearMatchInt(void) |
| bogdanm | 0:9b334a45a8ff | 819 | { |
| bogdanm | 0:9b334a45a8ff | 820 | PWM_CHn_ClearInt(PWM_CH2, PWM_CHn_ICR_MatchInterruptClear); |
| bogdanm | 0:9b334a45a8ff | 821 | } |
| bogdanm | 0:9b334a45a8ff | 822 | |
| bogdanm | 0:9b334a45a8ff | 823 | void PWM_CH2_ClearOverflowInt(void) |
| bogdanm | 0:9b334a45a8ff | 824 | { |
| bogdanm | 0:9b334a45a8ff | 825 | PWM_CHn_ClearInt(PWM_CH2, PWM_CHn_ICR_OverflowInterruptClear); |
| bogdanm | 0:9b334a45a8ff | 826 | } |
| bogdanm | 0:9b334a45a8ff | 827 | |
| bogdanm | 0:9b334a45a8ff | 828 | void PWM_CH2_ClearCaptureInt(void) |
| bogdanm | 0:9b334a45a8ff | 829 | { |
| bogdanm | 0:9b334a45a8ff | 830 | PWM_CHn_ClearInt(PWM_CH2, PWM_CHn_ICR_CaptureInterruptClear); |
| bogdanm | 0:9b334a45a8ff | 831 | } |
| bogdanm | 0:9b334a45a8ff | 832 | |
| bogdanm | 0:9b334a45a8ff | 833 | void PWM_CH3_ClearMatchInt(void) |
| bogdanm | 0:9b334a45a8ff | 834 | { |
| bogdanm | 0:9b334a45a8ff | 835 | PWM_CHn_ClearInt(PWM_CH3, PWM_CHn_ICR_MatchInterruptClear); |
| bogdanm | 0:9b334a45a8ff | 836 | } |
| bogdanm | 0:9b334a45a8ff | 837 | |
| bogdanm | 0:9b334a45a8ff | 838 | void PWM_CH3_ClearOverflowInt(void) |
| bogdanm | 0:9b334a45a8ff | 839 | { |
| bogdanm | 0:9b334a45a8ff | 840 | PWM_CHn_ClearInt(PWM_CH3, PWM_CHn_ICR_OverflowInterruptClear); |
| bogdanm | 0:9b334a45a8ff | 841 | } |
| bogdanm | 0:9b334a45a8ff | 842 | |
| bogdanm | 0:9b334a45a8ff | 843 | void PWM_CH3_ClearCaptureInt(void) |
| bogdanm | 0:9b334a45a8ff | 844 | { |
| bogdanm | 0:9b334a45a8ff | 845 | PWM_CHn_ClearInt(PWM_CH3, PWM_CHn_ICR_CaptureInterruptClear); |
| bogdanm | 0:9b334a45a8ff | 846 | } |
| bogdanm | 0:9b334a45a8ff | 847 | |
| bogdanm | 0:9b334a45a8ff | 848 | void PWM_CH4_ClearMatchInt(void) |
| bogdanm | 0:9b334a45a8ff | 849 | { |
| bogdanm | 0:9b334a45a8ff | 850 | PWM_CHn_ClearInt(PWM_CH4, PWM_CHn_ICR_MatchInterruptClear); |
| bogdanm | 0:9b334a45a8ff | 851 | } |
| bogdanm | 0:9b334a45a8ff | 852 | |
| bogdanm | 0:9b334a45a8ff | 853 | void PWM_CH4_ClearOverflowInt(void) |
| bogdanm | 0:9b334a45a8ff | 854 | { |
| bogdanm | 0:9b334a45a8ff | 855 | PWM_CHn_ClearInt(PWM_CH4, PWM_CHn_ICR_OverflowInterruptClear); |
| bogdanm | 0:9b334a45a8ff | 856 | } |
| bogdanm | 0:9b334a45a8ff | 857 | |
| bogdanm | 0:9b334a45a8ff | 858 | void PWM_CH4_ClearCaptureInt(void) |
| bogdanm | 0:9b334a45a8ff | 859 | { |
| bogdanm | 0:9b334a45a8ff | 860 | PWM_CHn_ClearInt(PWM_CH4, PWM_CHn_ICR_CaptureInterruptClear); |
| bogdanm | 0:9b334a45a8ff | 861 | } |
| bogdanm | 0:9b334a45a8ff | 862 | |
| bogdanm | 0:9b334a45a8ff | 863 | void PWM_CH5_ClearMatchInt(void) |
| bogdanm | 0:9b334a45a8ff | 864 | { |
| bogdanm | 0:9b334a45a8ff | 865 | PWM_CHn_ClearInt(PWM_CH5, PWM_CHn_ICR_MatchInterruptClear); |
| bogdanm | 0:9b334a45a8ff | 866 | } |
| bogdanm | 0:9b334a45a8ff | 867 | |
| bogdanm | 0:9b334a45a8ff | 868 | void PWM_CH5_ClearOverflowInt(void) |
| bogdanm | 0:9b334a45a8ff | 869 | { |
| bogdanm | 0:9b334a45a8ff | 870 | PWM_CHn_ClearInt(PWM_CH5, PWM_CHn_ICR_OverflowInterruptClear); |
| bogdanm | 0:9b334a45a8ff | 871 | } |
| bogdanm | 0:9b334a45a8ff | 872 | |
| bogdanm | 0:9b334a45a8ff | 873 | void PWM_CH5_ClearCaptureInt(void) |
| bogdanm | 0:9b334a45a8ff | 874 | { |
| bogdanm | 0:9b334a45a8ff | 875 | PWM_CHn_ClearInt(PWM_CH5, PWM_CHn_ICR_CaptureInterruptClear); |
| bogdanm | 0:9b334a45a8ff | 876 | } |
| bogdanm | 0:9b334a45a8ff | 877 | |
| bogdanm | 0:9b334a45a8ff | 878 | void PWM_CH6_ClearMatchInt(void) |
| bogdanm | 0:9b334a45a8ff | 879 | { |
| bogdanm | 0:9b334a45a8ff | 880 | PWM_CHn_ClearInt(PWM_CH6, PWM_CHn_ICR_MatchInterruptClear); |
| bogdanm | 0:9b334a45a8ff | 881 | } |
| bogdanm | 0:9b334a45a8ff | 882 | |
| bogdanm | 0:9b334a45a8ff | 883 | void PWM_CH6_ClearOverflowInt(void) |
| bogdanm | 0:9b334a45a8ff | 884 | { |
| bogdanm | 0:9b334a45a8ff | 885 | PWM_CHn_ClearInt(PWM_CH6, PWM_CHn_ICR_OverflowInterruptClear); |
| bogdanm | 0:9b334a45a8ff | 886 | } |
| bogdanm | 0:9b334a45a8ff | 887 | |
| bogdanm | 0:9b334a45a8ff | 888 | void PWM_CH6_ClearCaptureInt(void) |
| bogdanm | 0:9b334a45a8ff | 889 | { |
| bogdanm | 0:9b334a45a8ff | 890 | PWM_CHn_ClearInt(PWM_CH6, PWM_CHn_ICR_CaptureInterruptClear); |
| bogdanm | 0:9b334a45a8ff | 891 | } |
| bogdanm | 0:9b334a45a8ff | 892 | |
| bogdanm | 0:9b334a45a8ff | 893 | void PWM_CH7_ClearMatchInt(void) |
| bogdanm | 0:9b334a45a8ff | 894 | { |
| bogdanm | 0:9b334a45a8ff | 895 | PWM_CHn_ClearInt(PWM_CH7, PWM_CHn_ICR_MatchInterruptClear); |
| bogdanm | 0:9b334a45a8ff | 896 | } |
| bogdanm | 0:9b334a45a8ff | 897 | |
| bogdanm | 0:9b334a45a8ff | 898 | void PWM_CH7_ClearOverflowInt(void) |
| bogdanm | 0:9b334a45a8ff | 899 | { |
| bogdanm | 0:9b334a45a8ff | 900 | PWM_CHn_ClearInt(PWM_CH7, PWM_CHn_ICR_OverflowInterruptClear); |
| bogdanm | 0:9b334a45a8ff | 901 | } |
| bogdanm | 0:9b334a45a8ff | 902 | |
| bogdanm | 0:9b334a45a8ff | 903 | void PWM_CH7_ClearCaptureInt(void) |
| bogdanm | 0:9b334a45a8ff | 904 | { |
| bogdanm | 0:9b334a45a8ff | 905 | PWM_CHn_ClearInt(PWM_CH7, PWM_CHn_ICR_CaptureInterruptClear); |
| bogdanm | 0:9b334a45a8ff | 906 | } |