Tomo Yamanaka / mbed-dev

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targets/hal/TARGET_NXP/TARGET_LPC2460/spi_api.c@103:493a29d2d4d7, 2016-03-30 (annotated)

Committer:
1050186
Date:
Wed Mar 30 11:41:25 2016 +0000
Revision:
103:493a29d2d4d7
Parent:
0:9b334a45a8ff 
GR-PEACH runs on RAM.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* mbed Microcontroller Library
bogdanm 0:9b334a45a8ff 2 * Copyright (c) 2006-2015 ARM Limited
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Licensed under the Apache License, Version 2.0 (the "License");
bogdanm 0:9b334a45a8ff 5 * you may not use this file except in compliance with the License.
bogdanm 0:9b334a45a8ff 6 * You may obtain a copy of the License at
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * http://www.apache.org/licenses/LICENSE-2.0
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Unless required by applicable law or agreed to in writing, software
bogdanm 0:9b334a45a8ff 11 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 0:9b334a45a8ff 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 0:9b334a45a8ff 13 * See the License for the specific language governing permissions and
bogdanm 0:9b334a45a8ff 14 * limitations under the License.
bogdanm 0:9b334a45a8ff 15 */
bogdanm 0:9b334a45a8ff 16 #include "mbed_assert.h"
bogdanm 0:9b334a45a8ff 17 #include <math.h>
bogdanm 0:9b334a45a8ff 18
bogdanm 0:9b334a45a8ff 19 #include "spi_api.h"
bogdanm 0:9b334a45a8ff 20 #include "cmsis.h"
bogdanm 0:9b334a45a8ff 21 #include "pinmap.h"
bogdanm 0:9b334a45a8ff 22 #include "mbed_error.h"
bogdanm 0:9b334a45a8ff 23
bogdanm 0:9b334a45a8ff 24 static const PinMap PinMap_SPI_SCLK[] = {
bogdanm 0:9b334a45a8ff 25 {P0_7 , SPI_1, 2},
bogdanm 0:9b334a45a8ff 26 {P0_15, SPI_0, 2},
bogdanm 0:9b334a45a8ff 27 {P1_20, SPI_0, 3},
bogdanm 0:9b334a45a8ff 28 {P1_31, SPI_1, 2},
bogdanm 0:9b334a45a8ff 29 {NC , NC , 0}
bogdanm 0:9b334a45a8ff 30 };
bogdanm 0:9b334a45a8ff 31
bogdanm 0:9b334a45a8ff 32 static const PinMap PinMap_SPI_MOSI[] = {
bogdanm 0:9b334a45a8ff 33 {P0_9 , SPI_1, 2},
bogdanm 0:9b334a45a8ff 34 {P0_13, SPI_1, 2},
bogdanm 0:9b334a45a8ff 35 {P0_18, SPI_0, 2},
bogdanm 0:9b334a45a8ff 36 {P1_24, SPI_0, 3},
bogdanm 0:9b334a45a8ff 37 {NC , NC , 0}
bogdanm 0:9b334a45a8ff 38 };
bogdanm 0:9b334a45a8ff 39
bogdanm 0:9b334a45a8ff 40 static const PinMap PinMap_SPI_MISO[] = {
bogdanm 0:9b334a45a8ff 41 {P0_8 , SPI_1, 2},
bogdanm 0:9b334a45a8ff 42 {P0_12, SPI_1, 2},
bogdanm 0:9b334a45a8ff 43 {P0_17, SPI_0, 2},
bogdanm 0:9b334a45a8ff 44 {P1_23, SPI_0, 3},
bogdanm 0:9b334a45a8ff 45 {NC , NC , 0}
bogdanm 0:9b334a45a8ff 46 };
bogdanm 0:9b334a45a8ff 47
bogdanm 0:9b334a45a8ff 48 static const PinMap PinMap_SPI_SSEL[] = {
bogdanm 0:9b334a45a8ff 49 {P0_6 , SPI_1, 2},
bogdanm 0:9b334a45a8ff 50 {P0_14, SPI_1, 3},
bogdanm 0:9b334a45a8ff 51 {P0_16, SPI_0, 2},
bogdanm 0:9b334a45a8ff 52 {P1_21, SPI_0, 3},
bogdanm 0:9b334a45a8ff 53 {NC , NC , 0}
bogdanm 0:9b334a45a8ff 54 };
bogdanm 0:9b334a45a8ff 55
bogdanm 0:9b334a45a8ff 56 static inline int ssp_disable(spi_t *obj);
bogdanm 0:9b334a45a8ff 57 static inline int ssp_enable(spi_t *obj);
bogdanm 0:9b334a45a8ff 58
bogdanm 0:9b334a45a8ff 59 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
bogdanm 0:9b334a45a8ff 60 // determine the SPI to use
bogdanm 0:9b334a45a8ff 61 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
bogdanm 0:9b334a45a8ff 62 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
bogdanm 0:9b334a45a8ff 63 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
bogdanm 0:9b334a45a8ff 64 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
bogdanm 0:9b334a45a8ff 65 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
bogdanm 0:9b334a45a8ff 66 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
bogdanm 0:9b334a45a8ff 67 obj->spi = (LPC_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
bogdanm 0:9b334a45a8ff 68 MBED_ASSERT((int)obj->spi != NC);
bogdanm 0:9b334a45a8ff 69
bogdanm 0:9b334a45a8ff 70 // enable power and clocking
bogdanm 0:9b334a45a8ff 71 switch ((int)obj->spi) {
bogdanm 0:9b334a45a8ff 72 case SPI_0: LPC_SC->PCONP |= 1 << PCSSP0; break;
bogdanm 0:9b334a45a8ff 73 case SPI_1: LPC_SC->PCONP |= 1 << PCSSP1; break;
bogdanm 0:9b334a45a8ff 74 }
bogdanm 0:9b334a45a8ff 75
bogdanm 0:9b334a45a8ff 76 // set default format and frequency
bogdanm 0:9b334a45a8ff 77 if (ssel == NC) {
bogdanm 0:9b334a45a8ff 78 spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
bogdanm 0:9b334a45a8ff 79 } else {
bogdanm 0:9b334a45a8ff 80 spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
bogdanm 0:9b334a45a8ff 81 }
bogdanm 0:9b334a45a8ff 82 spi_frequency(obj, 1000000);
bogdanm 0:9b334a45a8ff 83
bogdanm 0:9b334a45a8ff 84 // enable the ssp channel
bogdanm 0:9b334a45a8ff 85 ssp_enable(obj);
bogdanm 0:9b334a45a8ff 86
bogdanm 0:9b334a45a8ff 87 // pin out the spi pins
bogdanm 0:9b334a45a8ff 88 pinmap_pinout(mosi, PinMap_SPI_MOSI);
bogdanm 0:9b334a45a8ff 89 pinmap_pinout(miso, PinMap_SPI_MISO);
bogdanm 0:9b334a45a8ff 90 pinmap_pinout(sclk, PinMap_SPI_SCLK);
bogdanm 0:9b334a45a8ff 91 if (ssel != NC) {
bogdanm 0:9b334a45a8ff 92 pinmap_pinout(ssel, PinMap_SPI_SSEL);
bogdanm 0:9b334a45a8ff 93 }
bogdanm 0:9b334a45a8ff 94 }
bogdanm 0:9b334a45a8ff 95
bogdanm 0:9b334a45a8ff 96 void spi_free(spi_t *obj) {}
bogdanm 0:9b334a45a8ff 97
bogdanm 0:9b334a45a8ff 98 void spi_format(spi_t *obj, int bits, int mode, int slave) {
bogdanm 0:9b334a45a8ff 99 MBED_ASSERT(((bits >= 4) && (bits <= 16)) && ((mode >= 0) && (mode <= 3)));
bogdanm 0:9b334a45a8ff 100 ssp_disable(obj);
bogdanm 0:9b334a45a8ff 101
bogdanm 0:9b334a45a8ff 102 int polarity = (mode & 0x2) ? 1 : 0;
bogdanm 0:9b334a45a8ff 103 int phase = (mode & 0x1) ? 1 : 0;
bogdanm 0:9b334a45a8ff 104
bogdanm 0:9b334a45a8ff 105 // set it up
bogdanm 0:9b334a45a8ff 106 int DSS = bits - 1; // DSS (data select size)
bogdanm 0:9b334a45a8ff 107 int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
bogdanm 0:9b334a45a8ff 108 int SPH = (phase) ? 1 : 0; // SPH - clock out phase
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110 int FRF = 0; // FRF (frame format) = SPI
bogdanm 0:9b334a45a8ff 111 uint32_t tmp = obj->spi->CR0;
bogdanm 0:9b334a45a8ff 112 tmp &= ~(0xFFFF);
bogdanm 0:9b334a45a8ff 113 tmp |= DSS << 0
bogdanm 0:9b334a45a8ff 114 | FRF << 4
bogdanm 0:9b334a45a8ff 115 | SPO << 6
bogdanm 0:9b334a45a8ff 116 | SPH << 7;
bogdanm 0:9b334a45a8ff 117 obj->spi->CR0 = tmp;
bogdanm 0:9b334a45a8ff 118
bogdanm 0:9b334a45a8ff 119 tmp = obj->spi->CR1;
bogdanm 0:9b334a45a8ff 120 tmp &= ~(0xD);
bogdanm 0:9b334a45a8ff 121 tmp |= 0 << 0 // LBM - loop back mode - off
bogdanm 0:9b334a45a8ff 122 | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
bogdanm 0:9b334a45a8ff 123 | 0 << 3; // SOD - slave output disable - na
bogdanm 0:9b334a45a8ff 124 obj->spi->CR1 = tmp;
bogdanm 0:9b334a45a8ff 125
bogdanm 0:9b334a45a8ff 126 ssp_enable(obj);
bogdanm 0:9b334a45a8ff 127 }
bogdanm 0:9b334a45a8ff 128
bogdanm 0:9b334a45a8ff 129 void spi_frequency(spi_t *obj, int hz) {
bogdanm 0:9b334a45a8ff 130 ssp_disable(obj);
bogdanm 0:9b334a45a8ff 131
bogdanm 0:9b334a45a8ff 132 // setup the spi clock diveder to /1
bogdanm 0:9b334a45a8ff 133 switch ((int)obj->spi) {
bogdanm 0:9b334a45a8ff 134 case SPI_0:
bogdanm 0:9b334a45a8ff 135 LPC_SC->PCLKSEL1 &= ~(3 << 10);
bogdanm 0:9b334a45a8ff 136 LPC_SC->PCLKSEL1 |= (1 << 10);
bogdanm 0:9b334a45a8ff 137 break;
bogdanm 0:9b334a45a8ff 138 case SPI_1:
bogdanm 0:9b334a45a8ff 139 LPC_SC->PCLKSEL0 &= ~(3 << 20);
bogdanm 0:9b334a45a8ff 140 LPC_SC->PCLKSEL0 |= (1 << 20);
bogdanm 0:9b334a45a8ff 141 break;
bogdanm 0:9b334a45a8ff 142 }
bogdanm 0:9b334a45a8ff 143
bogdanm 0:9b334a45a8ff 144 uint32_t PCLK = SystemCoreClock;
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 int prescaler;
bogdanm 0:9b334a45a8ff 147
bogdanm 0:9b334a45a8ff 148 for (prescaler = 2; prescaler <= 254; prescaler += 2) {
bogdanm 0:9b334a45a8ff 149 int prescale_hz = PCLK / prescaler;
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151 // calculate the divider
bogdanm 0:9b334a45a8ff 152 int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
bogdanm 0:9b334a45a8ff 153
bogdanm 0:9b334a45a8ff 154 // check we can support the divider
bogdanm 0:9b334a45a8ff 155 if (divider < 256) {
bogdanm 0:9b334a45a8ff 156 // prescaler
bogdanm 0:9b334a45a8ff 157 obj->spi->CPSR = prescaler;
bogdanm 0:9b334a45a8ff 158
bogdanm 0:9b334a45a8ff 159 // divider
bogdanm 0:9b334a45a8ff 160 obj->spi->CR0 &= ~(0xFFFF << 8);
bogdanm 0:9b334a45a8ff 161 obj->spi->CR0 |= (divider - 1) << 8;
bogdanm 0:9b334a45a8ff 162 ssp_enable(obj);
bogdanm 0:9b334a45a8ff 163 return;
bogdanm 0:9b334a45a8ff 164 }
bogdanm 0:9b334a45a8ff 165 }
bogdanm 0:9b334a45a8ff 166 error("Couldn't setup requested SPI frequency");
bogdanm 0:9b334a45a8ff 167 }
bogdanm 0:9b334a45a8ff 168
bogdanm 0:9b334a45a8ff 169 static inline int ssp_disable(spi_t *obj) {
bogdanm 0:9b334a45a8ff 170 return obj->spi->CR1 &= ~(1 << 1);
bogdanm 0:9b334a45a8ff 171 }
bogdanm 0:9b334a45a8ff 172
bogdanm 0:9b334a45a8ff 173 static inline int ssp_enable(spi_t *obj) {
bogdanm 0:9b334a45a8ff 174 return obj->spi->CR1 |= (1 << 1);
bogdanm 0:9b334a45a8ff 175 }
bogdanm 0:9b334a45a8ff 176
bogdanm 0:9b334a45a8ff 177 static inline int ssp_readable(spi_t *obj) {
bogdanm 0:9b334a45a8ff 178 return obj->spi->SR & (1 << 2);
bogdanm 0:9b334a45a8ff 179 }
bogdanm 0:9b334a45a8ff 180
bogdanm 0:9b334a45a8ff 181 static inline int ssp_writeable(spi_t *obj) {
bogdanm 0:9b334a45a8ff 182 return obj->spi->SR & (1 << 1);
bogdanm 0:9b334a45a8ff 183 }
bogdanm 0:9b334a45a8ff 184
bogdanm 0:9b334a45a8ff 185 static inline void ssp_write(spi_t *obj, int value) {
bogdanm 0:9b334a45a8ff 186 while (!ssp_writeable(obj));
bogdanm 0:9b334a45a8ff 187 obj->spi->DR = value;
bogdanm 0:9b334a45a8ff 188 }
bogdanm 0:9b334a45a8ff 189
bogdanm 0:9b334a45a8ff 190 static inline int ssp_read(spi_t *obj) {
bogdanm 0:9b334a45a8ff 191 while (!ssp_readable(obj));
bogdanm 0:9b334a45a8ff 192 return obj->spi->DR;
bogdanm 0:9b334a45a8ff 193 }
bogdanm 0:9b334a45a8ff 194
bogdanm 0:9b334a45a8ff 195 static inline int ssp_busy(spi_t *obj) {
bogdanm 0:9b334a45a8ff 196 return (obj->spi->SR & (1 << 4)) ? (1) : (0);
bogdanm 0:9b334a45a8ff 197 }
bogdanm 0:9b334a45a8ff 198
bogdanm 0:9b334a45a8ff 199 int spi_master_write(spi_t *obj, int value) {
bogdanm 0:9b334a45a8ff 200 ssp_write(obj, value);
bogdanm 0:9b334a45a8ff 201 return ssp_read(obj);
bogdanm 0:9b334a45a8ff 202 }
bogdanm 0:9b334a45a8ff 203
bogdanm 0:9b334a45a8ff 204 int spi_slave_receive(spi_t *obj) {
bogdanm 0:9b334a45a8ff 205 return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
bogdanm 0:9b334a45a8ff 206 }
bogdanm 0:9b334a45a8ff 207
bogdanm 0:9b334a45a8ff 208 int spi_slave_read(spi_t *obj) {
bogdanm 0:9b334a45a8ff 209 return obj->spi->DR;
bogdanm 0:9b334a45a8ff 210 }
bogdanm 0:9b334a45a8ff 211
bogdanm 0:9b334a45a8ff 212 void spi_slave_write(spi_t *obj, int value) {
bogdanm 0:9b334a45a8ff 213 while (ssp_writeable(obj) == 0) ;
bogdanm 0:9b334a45a8ff 214 obj->spi->DR = value;
bogdanm 0:9b334a45a8ff 215 }
bogdanm 0:9b334a45a8ff 216
bogdanm 0:9b334a45a8ff 217 int spi_busy(spi_t *obj) {
bogdanm 0:9b334a45a8ff 218 return ssp_busy(obj);
bogdanm 0:9b334a45a8ff 219 }