Tomo Yamanaka / mbed-dev

mbed library sources. Supersedes mbed-src. GR-PEACH runs on RAM.

Fork of mbed-dev by mbed official

Files at this revision

API Documentation at this revision

Revision 56:05912f50f004, committed 2016-01-29

Comitter:
mbed_official
Date:
Fri Jan 29 14:15:09 2016 +0000
Parent:
55:814265bf5462
Child:
57:791e51e3acc9
Commit message:
Synchronized with git revision d465cb53a3a479b9456cb456ded8d71a53f2bdee

Full URL: https://github.com/mbedmicro/mbed/commit/d465cb53a3a479b9456cb456ded8d71a53f2bdee/

Update rtc_api.c

Changed in this revision

targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.c Show annotated file Show diff for this revision Revisions of this file
targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.c Show annotated file Show diff for this revision Revisions of this file
targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/system_stm32f0xx.c Show annotated file Show diff for this revision Revisions of this file
targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/system_stm32f0xx.c Show annotated file Show diff for this revision Revisions of this file
targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.c Show annotated file Show diff for this revision Revisions of this file
targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.c Show annotated file Show diff for this revision Revisions of this file
targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/system_stm32f0xx.c Show annotated file Show diff for this revision Revisions of this file
targets/hal/TARGET_Freescale/TARGET_KLXX/rtc_api.c Show annotated file Show diff for this revision Revisions of this file 
--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.c	Fri Jan 29 13:30:11 2016 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.c	Fri Jan 29 14:15:09 2016 +0000
@@ -426,12 +426,19 @@
   RCC_OscInitTypeDef RCC_OscInitStruct;
  
   // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
-  RCC_OscInitStruct.HSIState       = RCC_HSI_ON;
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSI; // HSI div 2
-  RCC_OscInitStruct.PLL.PREDIV     = RCC_PREDIV_DIV1;
-  RCC_OscInitStruct.PLL.PLLMUL     = RCC_PLL_MUL12;
+  RCC_OscInitStruct.OscillatorType          = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSEState                = RCC_HSE_OFF;
+  RCC_OscInitStruct.LSEState                = RCC_LSE_OFF;
+  RCC_OscInitStruct.HSIState                = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue     = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI14State              = RCC_HSI_OFF;
+  RCC_OscInitStruct.HSI14CalibrationValue   = RCC_HSI14CALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI48State              = RCC_HSI_ON;
+  RCC_OscInitStruct.LSIState                = RCC_LSI_OFF;
+  RCC_OscInitStruct.PLL.PLLState            = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource           = RCC_PLLSOURCE_HSI; // HSI div 2
+  RCC_OscInitStruct.PLL.PREDIV              = RCC_PREDIV_DIV1;
+  RCC_OscInitStruct.PLL.PLLMUL              = RCC_PLL_MUL12;
   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
       return 0; // FAIL
   }

--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.c	Fri Jan 29 13:30:11 2016 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.c	Fri Jan 29 14:15:09 2016 +0000
@@ -430,12 +430,19 @@
   RCC_OscInitTypeDef RCC_OscInitStruct;
  
   // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
-  RCC_OscInitStruct.HSIState       = RCC_HSI_ON;
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSI; // HSI div 2
-  RCC_OscInitStruct.PLL.PREDIV     = RCC_PREDIV_DIV1;
-  RCC_OscInitStruct.PLL.PLLMUL     = RCC_PLL_MUL12;
+  RCC_OscInitStruct.OscillatorType          = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSEState                = RCC_HSE_OFF;
+  RCC_OscInitStruct.LSEState                = RCC_LSE_OFF;
+  RCC_OscInitStruct.HSIState                = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue     = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI14State              = RCC_HSI_OFF;
+  RCC_OscInitStruct.HSI14CalibrationValue   = RCC_HSI14CALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI48State              = RCC_HSI_ON;
+  RCC_OscInitStruct.LSIState                = RCC_LSI_OFF;
+  RCC_OscInitStruct.PLL.PLLState            = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource           = RCC_PLLSOURCE_HSI; // HSI div 2
+  RCC_OscInitStruct.PLL.PREDIV              = RCC_PREDIV_DIV1;
+  RCC_OscInitStruct.PLL.PLLMUL              = RCC_PLL_MUL12;
   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
       return 0; // FAIL
   }

--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/system_stm32f0xx.c	Fri Jan 29 13:30:11 2016 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/system_stm32f0xx.c	Fri Jan 29 14:15:09 2016 +0000
@@ -430,13 +430,19 @@
   RCC_OscInitTypeDef RCC_OscInitStruct;
  
   // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
-  RCC_OscInitStruct.HSIState       = RCC_HSI_ON;
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSI; // HSI div 2
-  RCC_OscInitStruct.PLL.PREDIV     = RCC_PREDIV_DIV1;
-  RCC_OscInitStruct.PLL.PLLMUL     = RCC_PLL_MUL12;
-  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.OscillatorType          = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSEState                = RCC_HSE_OFF;
+  RCC_OscInitStruct.LSEState                = RCC_LSE_OFF;
+  RCC_OscInitStruct.HSIState                = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue     = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI14State              = RCC_HSI_OFF;
+  RCC_OscInitStruct.HSI14CalibrationValue   = RCC_HSI14CALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI48State              = RCC_HSI_ON;
+  RCC_OscInitStruct.LSIState                = RCC_LSI_OFF;
+  RCC_OscInitStruct.PLL.PLLState            = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource           = RCC_PLLSOURCE_HSI; // HSI div 2
+  RCC_OscInitStruct.PLL.PREDIV              = RCC_PREDIV_DIV1;
+  RCC_OscInitStruct.PLL.PLLMUL              = RCC_PLL_MUL12;
   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
       return 0; // FAIL
   }

--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/system_stm32f0xx.c	Fri Jan 29 13:30:11 2016 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/system_stm32f0xx.c	Fri Jan 29 14:15:09 2016 +0000
@@ -429,14 +429,20 @@
   RCC_ClkInitTypeDef RCC_ClkInitStruct;
   RCC_OscInitTypeDef RCC_OscInitStruct;
  
-  // Select PLLCLK = 48 MHz ((HSI 8 MHz) * 6)
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
-  RCC_OscInitStruct.HSIState       = RCC_HSI_ON;
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSI;
-  RCC_OscInitStruct.PLL.PREDIV     = RCC_PREDIV_DIV1;
-  RCC_OscInitStruct.PLL.PLLMUL     = RCC_PLL_MUL6;
-  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+  // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
+  RCC_OscInitStruct.OscillatorType          = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSEState                = RCC_HSE_OFF;
+  RCC_OscInitStruct.LSEState                = RCC_LSE_OFF;
+  RCC_OscInitStruct.HSIState                = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue     = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI14State              = RCC_HSI_OFF;
+  RCC_OscInitStruct.HSI14CalibrationValue   = RCC_HSI14CALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI48State              = RCC_HSI_ON;
+  RCC_OscInitStruct.LSIState                = RCC_LSI_OFF;
+  RCC_OscInitStruct.PLL.PLLState            = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource           = RCC_PLLSOURCE_HSI; // HSI div 2
+  RCC_OscInitStruct.PLL.PREDIV              = RCC_PREDIV_DIV1;
+  RCC_OscInitStruct.PLL.PLLMUL              = RCC_PLL_MUL6;
   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
       return 0; // FAIL
   }

--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.c	Fri Jan 29 13:30:11 2016 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.c	Fri Jan 29 14:15:09 2016 +0000
@@ -434,12 +434,19 @@
   RCC_OscInitTypeDef RCC_OscInitStruct;
  
   // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
-  RCC_OscInitStruct.HSIState       = RCC_HSI_ON;
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSI; // HSI div 2
-  RCC_OscInitStruct.PLL.PREDIV     = RCC_PREDIV_DIV1;
-  RCC_OscInitStruct.PLL.PLLMUL     = RCC_PLL_MUL12;
+  RCC_OscInitStruct.OscillatorType          = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSEState                = RCC_HSE_OFF;
+  RCC_OscInitStruct.LSEState                = RCC_LSE_OFF;
+  RCC_OscInitStruct.HSIState                = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue     = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI14State              = RCC_HSI_OFF;
+  RCC_OscInitStruct.HSI14CalibrationValue   = RCC_HSI14CALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI48State              = RCC_HSI_ON;
+  RCC_OscInitStruct.LSIState                = RCC_LSI_OFF;
+  RCC_OscInitStruct.PLL.PLLState            = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource           = RCC_PLLSOURCE_HSI; // HSI div 2
+  RCC_OscInitStruct.PLL.PREDIV              = RCC_PREDIV_DIV1;
+  RCC_OscInitStruct.PLL.PLLMUL              = RCC_PLL_MUL12;
   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
       return 0; // FAIL
   }

--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.c	Fri Jan 29 13:30:11 2016 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.c	Fri Jan 29 14:15:09 2016 +0000
@@ -433,12 +433,19 @@
   RCC_OscInitTypeDef RCC_OscInitStruct;
  
   // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
-  RCC_OscInitStruct.HSIState       = RCC_HSI_ON;
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSI; // HSI div 2
-  RCC_OscInitStruct.PLL.PREDIV     = RCC_PREDIV_DIV1;
-  RCC_OscInitStruct.PLL.PLLMUL     = RCC_PLL_MUL12;
+  RCC_OscInitStruct.OscillatorType          = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSEState                = RCC_HSE_OFF;
+  RCC_OscInitStruct.LSEState                = RCC_LSE_OFF;
+  RCC_OscInitStruct.HSIState                = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue     = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI14State              = RCC_HSI_OFF;
+  RCC_OscInitStruct.HSI14CalibrationValue   = RCC_HSI14CALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI48State              = RCC_HSI_ON;
+  RCC_OscInitStruct.LSIState                = RCC_LSI_OFF;
+  RCC_OscInitStruct.PLL.PLLState            = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource           = RCC_PLLSOURCE_HSI; // HSI div 2
+  RCC_OscInitStruct.PLL.PREDIV              = RCC_PREDIV_DIV1;
+  RCC_OscInitStruct.PLL.PLLMUL              = RCC_PLL_MUL12;
   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
       return 0; // FAIL
   }

--- a/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/system_stm32f0xx.c	Fri Jan 29 13:30:11 2016 +0000
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/system_stm32f0xx.c	Fri Jan 29 14:15:09 2016 +0000
@@ -433,12 +433,19 @@
   RCC_OscInitTypeDef RCC_OscInitStruct;
  
   // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
-  RCC_OscInitStruct.HSIState       = RCC_HSI_ON;
-  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSI; // HSI div 2
-  RCC_OscInitStruct.PLL.PREDIV     = RCC_PREDIV_DIV1;
-  RCC_OscInitStruct.PLL.PLLMUL     = RCC_PLL_MUL12;
+  RCC_OscInitStruct.OscillatorType          = RCC_OSCILLATORTYPE_HSI;
+  RCC_OscInitStruct.HSEState                = RCC_HSE_OFF;
+  RCC_OscInitStruct.LSEState                = RCC_LSE_OFF;
+  RCC_OscInitStruct.HSIState                = RCC_HSI_ON;
+  RCC_OscInitStruct.HSICalibrationValue     = RCC_HSICALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI14State              = RCC_HSI_OFF;
+  RCC_OscInitStruct.HSI14CalibrationValue   = RCC_HSI14CALIBRATION_DEFAULT;
+  RCC_OscInitStruct.HSI48State              = RCC_HSI_ON;
+  RCC_OscInitStruct.LSIState                = RCC_LSI_OFF;
+  RCC_OscInitStruct.PLL.PLLState            = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource           = RCC_PLLSOURCE_HSI; // HSI div 2
+  RCC_OscInitStruct.PLL.PREDIV              = RCC_PREDIV_DIV1;
+  RCC_OscInitStruct.PLL.PLLMUL              = RCC_PLL_MUL12;
   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
       return 0; // FAIL
   }

--- a/targets/hal/TARGET_Freescale/TARGET_KLXX/rtc_api.c	Fri Jan 29 13:30:11 2016 +0000
+++ b/targets/hal/TARGET_Freescale/TARGET_KLXX/rtc_api.c	Fri Jan 29 14:15:09 2016 +0000
@@ -38,14 +38,32 @@
 void rtc_init(void) {
     init();
 
-    //Configure the TSR. default value: 1
+    // Configure the TSR. default value: 1
     RTC->TSR = 1;
-    
-    if (PinMap_RTC[0].pin == NC) {        //Use OSC32K
-        RTC->CR |= RTC_CR_OSCE_MASK;
-        //delay for OSCE stabilization
-        for(int i=0; i<0x1000; i++) __NOP();
-    }
+
+    // Configure Time Compensation Register to calibrate RTC accuracy
+
+    // dissable LRL lock
+    RTC->LR &= ~RTC_LR_LRL_MASK;
+    // RTC->TCR: RTC_TCR_CIR_MASK,RTC_TCR_CIR(x)=0,RTC_TCR_TCR(x)=0  Default no correction
+    RTC->TCR = RTC_TCR_CIR(0) | RTC_TCR_TCR(0);
+    /*
+        RTC_TCR_CIR(x) sets the compensation interval in seconds from 1 to 256.
+        0x05 will apply the compensation once every 4 seconds.
+
+        RTC_TCR_TCR(x) sets the Register Overflow
+        0x80 Time Prescaler Register overflows every 32896 clock cycles. (+128)
+        ... ... RTC runs slower
+        0xFF Time Prescaler Register overflows every 32769 clock cycles.
+        0x00 Time Prescaler Register overflows every 32768 clock cycles, Default.
+        0x01 Time Prescaler Register overflows every 32767 clock cycles.
+        ... ... RTC runs faster
+        0x7F Time Prescaler Register overflows every 32641 clock cycles. (-128)
+    */
+    // enable TCL lock
+    RTC->LR |= RTC_LR_TCL_MASK;
+    // enable LRL lock
+    RTC->LR |= RTC_LR_LRL_MASK;
 
     // enable counter
     RTC->SR |= RTC_SR_TCE_MASK;