Tomo Yamanaka / mbed-dev

mbed library sources. Supersedes mbed-src. GR-PEACH runs on RAM.

Fork of mbed-dev by mbed official

targets/hal/TARGET_NXP/TARGET_LPC23XX/gpio_irq_api.c@103:493a29d2d4d7, 2016-03-30 (annotated)

Committer:
1050186
Date:
Wed Mar 30 11:41:25 2016 +0000
Revision:
103:493a29d2d4d7
Parent:
0:9b334a45a8ff 
GR-PEACH runs on RAM.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* mbed Microcontroller Library
bogdanm 0:9b334a45a8ff 2 * Copyright (c) 2006-2013 ARM Limited
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Licensed under the Apache License, Version 2.0 (the "License");
bogdanm 0:9b334a45a8ff 5 * you may not use this file except in compliance with the License.
bogdanm 0:9b334a45a8ff 6 * You may obtain a copy of the License at
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * http://www.apache.org/licenses/LICENSE-2.0
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Unless required by applicable law or agreed to in writing, software
bogdanm 0:9b334a45a8ff 11 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 0:9b334a45a8ff 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 0:9b334a45a8ff 13 * See the License for the specific language governing permissions and
bogdanm 0:9b334a45a8ff 14 * limitations under the License.
bogdanm 0:9b334a45a8ff 15 */
bogdanm 0:9b334a45a8ff 16 #include "gpio_irq_api.h"
bogdanm 0:9b334a45a8ff 17 #include "mbed_error.h"
bogdanm 0:9b334a45a8ff 18 #include <stddef.h>
bogdanm 0:9b334a45a8ff 19 #include "cmsis.h"
bogdanm 0:9b334a45a8ff 20
bogdanm 0:9b334a45a8ff 21 #define CHANNEL_NUM 48
bogdanm 0:9b334a45a8ff 22
bogdanm 0:9b334a45a8ff 23 static uint32_t channel_ids[CHANNEL_NUM] = {0};
bogdanm 0:9b334a45a8ff 24 static gpio_irq_handler irq_handler;
bogdanm 0:9b334a45a8ff 25
bogdanm 0:9b334a45a8ff 26 static void handle_interrupt_in(void) {
bogdanm 0:9b334a45a8ff 27 // Read in all current interrupt registers. We do this once as the
bogdanm 0:9b334a45a8ff 28 // GPIO interrupt registers are on the APB bus, and this is slow.
bogdanm 0:9b334a45a8ff 29 uint32_t rise0 = LPC_GPIOINT->IO0IntStatR;
bogdanm 0:9b334a45a8ff 30 uint32_t fall0 = LPC_GPIOINT->IO0IntStatF;
bogdanm 0:9b334a45a8ff 31 uint32_t rise2 = LPC_GPIOINT->IO2IntStatR;
bogdanm 0:9b334a45a8ff 32 uint32_t fall2 = LPC_GPIOINT->IO2IntStatF;
bogdanm 0:9b334a45a8ff 33 uint32_t mask0 = 0;
bogdanm 0:9b334a45a8ff 34 uint32_t mask2 = 0;
bogdanm 0:9b334a45a8ff 35 int i;
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 // P0.0-0.31
bogdanm 0:9b334a45a8ff 38 for (i = 0; i < 32; i++) {
bogdanm 0:9b334a45a8ff 39 uint32_t pmask = (1 << i);
bogdanm 0:9b334a45a8ff 40 if (rise0 & pmask) {
bogdanm 0:9b334a45a8ff 41 mask0 |= pmask;
bogdanm 0:9b334a45a8ff 42 if (channel_ids[i] != 0)
bogdanm 0:9b334a45a8ff 43 irq_handler(channel_ids[i], IRQ_RISE);
bogdanm 0:9b334a45a8ff 44 }
bogdanm 0:9b334a45a8ff 45 if (fall0 & pmask) {
bogdanm 0:9b334a45a8ff 46 mask0 |= pmask;
bogdanm 0:9b334a45a8ff 47 if (channel_ids[i] != 0)
bogdanm 0:9b334a45a8ff 48 irq_handler(channel_ids[i], IRQ_FALL);
bogdanm 0:9b334a45a8ff 49 }
bogdanm 0:9b334a45a8ff 50 }
bogdanm 0:9b334a45a8ff 51
bogdanm 0:9b334a45a8ff 52 // P2.0-2.15
bogdanm 0:9b334a45a8ff 53 for (i = 0; i < 16; i++) {
bogdanm 0:9b334a45a8ff 54 uint32_t pmask = (1 << i);
bogdanm 0:9b334a45a8ff 55 int channel_index = i + 32;
bogdanm 0:9b334a45a8ff 56 if (rise2 & pmask) {
bogdanm 0:9b334a45a8ff 57 mask2 |= pmask;
bogdanm 0:9b334a45a8ff 58 if (channel_ids[channel_index] != 0)
bogdanm 0:9b334a45a8ff 59 irq_handler(channel_ids[channel_index], IRQ_RISE);
bogdanm 0:9b334a45a8ff 60 }
bogdanm 0:9b334a45a8ff 61 if (fall2 & pmask) {
bogdanm 0:9b334a45a8ff 62 mask2 |= pmask;
bogdanm 0:9b334a45a8ff 63 if (channel_ids[channel_index] != 0)
bogdanm 0:9b334a45a8ff 64 irq_handler(channel_ids[channel_index], IRQ_FALL);
bogdanm 0:9b334a45a8ff 65 }
bogdanm 0:9b334a45a8ff 66 }
bogdanm 0:9b334a45a8ff 67
bogdanm 0:9b334a45a8ff 68 // Clear the interrupts we just handled
bogdanm 0:9b334a45a8ff 69 LPC_GPIOINT->IO0IntClr = mask0;
bogdanm 0:9b334a45a8ff 70 LPC_GPIOINT->IO2IntClr = mask2;
bogdanm 0:9b334a45a8ff 71 }
bogdanm 0:9b334a45a8ff 72
bogdanm 0:9b334a45a8ff 73 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
bogdanm 0:9b334a45a8ff 74 if (pin == NC) return -1;
bogdanm 0:9b334a45a8ff 75
bogdanm 0:9b334a45a8ff 76 irq_handler = handler;
bogdanm 0:9b334a45a8ff 77
bogdanm 0:9b334a45a8ff 78 obj->port = (int)pin & ~0x1F;
bogdanm 0:9b334a45a8ff 79 obj->pin = (int)pin & 0x1F;
bogdanm 0:9b334a45a8ff 80
bogdanm 0:9b334a45a8ff 81 // Interrupts available only on GPIO0 and GPIO2
bogdanm 0:9b334a45a8ff 82 if (obj->port != LPC_GPIO0_BASE && obj->port != LPC_GPIO2_BASE) {
bogdanm 0:9b334a45a8ff 83 error("pins on this port cannot generate interrupts");
bogdanm 0:9b334a45a8ff 84 }
bogdanm 0:9b334a45a8ff 85
bogdanm 0:9b334a45a8ff 86 // put us in the interrupt table
bogdanm 0:9b334a45a8ff 87 int index = (obj->port == LPC_GPIO0_BASE) ? obj->pin : obj->pin + 32;
bogdanm 0:9b334a45a8ff 88 channel_ids[index] = id;
bogdanm 0:9b334a45a8ff 89 obj->ch = index;
bogdanm 0:9b334a45a8ff 90
bogdanm 0:9b334a45a8ff 91 NVIC_SetVector(EINT3_IRQn, (uint32_t)handle_interrupt_in);
bogdanm 0:9b334a45a8ff 92 NVIC_EnableIRQ(EINT3_IRQn);
bogdanm 0:9b334a45a8ff 93
bogdanm 0:9b334a45a8ff 94 return 0;
bogdanm 0:9b334a45a8ff 95 }
bogdanm 0:9b334a45a8ff 96
bogdanm 0:9b334a45a8ff 97 void gpio_irq_free(gpio_irq_t *obj) {
bogdanm 0:9b334a45a8ff 98 channel_ids[obj->ch] = 0;
bogdanm 0:9b334a45a8ff 99 }
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
bogdanm 0:9b334a45a8ff 102 // ensure nothing is pending
bogdanm 0:9b334a45a8ff 103 switch (obj->port) {
bogdanm 0:9b334a45a8ff 104 case LPC_GPIO0_BASE: LPC_GPIOINT->IO0IntClr = 1 << obj->pin; break;
bogdanm 0:9b334a45a8ff 105 case LPC_GPIO2_BASE: LPC_GPIOINT->IO2IntClr = 1 << obj->pin; break;
bogdanm 0:9b334a45a8ff 106 }
bogdanm 0:9b334a45a8ff 107
bogdanm 0:9b334a45a8ff 108 // enable the pin interrupt
bogdanm 0:9b334a45a8ff 109 if (event == IRQ_RISE) {
bogdanm 0:9b334a45a8ff 110 switch (obj->port) {
bogdanm 0:9b334a45a8ff 111 case LPC_GPIO0_BASE:
bogdanm 0:9b334a45a8ff 112 if (enable) {
bogdanm 0:9b334a45a8ff 113 LPC_GPIOINT->IO0IntEnR |= 1 << obj->pin;
bogdanm 0:9b334a45a8ff 114 } else {
bogdanm 0:9b334a45a8ff 115 LPC_GPIOINT->IO0IntEnR &= ~(1 << obj->pin);
bogdanm 0:9b334a45a8ff 116 }
bogdanm 0:9b334a45a8ff 117 break;
bogdanm 0:9b334a45a8ff 118 case LPC_GPIO2_BASE:
bogdanm 0:9b334a45a8ff 119 if (enable) {
bogdanm 0:9b334a45a8ff 120 LPC_GPIOINT->IO2IntEnR |= 1 << obj->pin;
bogdanm 0:9b334a45a8ff 121 } else {
bogdanm 0:9b334a45a8ff 122 LPC_GPIOINT->IO2IntEnR &= ~(1 << obj->pin);
bogdanm 0:9b334a45a8ff 123 }
bogdanm 0:9b334a45a8ff 124 break;
bogdanm 0:9b334a45a8ff 125 }
bogdanm 0:9b334a45a8ff 126 } else {
bogdanm 0:9b334a45a8ff 127 switch (obj->port) {
bogdanm 0:9b334a45a8ff 128 case LPC_GPIO0_BASE:
bogdanm 0:9b334a45a8ff 129 if (enable) {
bogdanm 0:9b334a45a8ff 130 LPC_GPIOINT->IO0IntEnF |= 1 << obj->pin;
bogdanm 0:9b334a45a8ff 131 } else {
bogdanm 0:9b334a45a8ff 132 LPC_GPIOINT->IO0IntEnF &= ~(1 << obj->pin);
bogdanm 0:9b334a45a8ff 133 }
bogdanm 0:9b334a45a8ff 134 break;
bogdanm 0:9b334a45a8ff 135
bogdanm 0:9b334a45a8ff 136 case LPC_GPIO2_BASE:
bogdanm 0:9b334a45a8ff 137 if (enable) {
bogdanm 0:9b334a45a8ff 138 LPC_GPIOINT->IO2IntEnF |= 1 << obj->pin;
bogdanm 0:9b334a45a8ff 139 } else {
bogdanm 0:9b334a45a8ff 140 LPC_GPIOINT->IO2IntEnF &= ~(1 << obj->pin);
bogdanm 0:9b334a45a8ff 141 }
bogdanm 0:9b334a45a8ff 142 break;
bogdanm 0:9b334a45a8ff 143 }
bogdanm 0:9b334a45a8ff 144 }
bogdanm 0:9b334a45a8ff 145 }
bogdanm 0:9b334a45a8ff 146
bogdanm 0:9b334a45a8ff 147 void gpio_irq_enable(gpio_irq_t *obj) {
bogdanm 0:9b334a45a8ff 148 NVIC_EnableIRQ(EINT3_IRQn);
bogdanm 0:9b334a45a8ff 149 }
bogdanm 0:9b334a45a8ff 150
bogdanm 0:9b334a45a8ff 151 void gpio_irq_disable(gpio_irq_t *obj) {
bogdanm 0:9b334a45a8ff 152 NVIC_DisableIRQ(EINT3_IRQn);
bogdanm 0:9b334a45a8ff 153 }
bogdanm 0:9b334a45a8ff 154