Tomo Yamanaka / mbed-dev

mbed library sources. Supersedes mbed-src. GR-PEACH runs on RAM.

Fork of mbed-dev by mbed official

targets/hal/TARGET_NXP/TARGET_LPC23XX/ethernet_api.c@103:493a29d2d4d7, 2016-03-30 (annotated)

Committer:
1050186
Date:
Wed Mar 30 11:41:25 2016 +0000
Revision:
103:493a29d2d4d7
Parent:
0:9b334a45a8ff 
GR-PEACH runs on RAM.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* mbed Microcontroller Library
bogdanm 0:9b334a45a8ff 2 * Copyright (c) 2006-2013 ARM Limited
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Licensed under the Apache License, Version 2.0 (the "License");
bogdanm 0:9b334a45a8ff 5 * you may not use this file except in compliance with the License.
bogdanm 0:9b334a45a8ff 6 * You may obtain a copy of the License at
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * http://www.apache.org/licenses/LICENSE-2.0
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Unless required by applicable law or agreed to in writing, software
bogdanm 0:9b334a45a8ff 11 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 0:9b334a45a8ff 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 0:9b334a45a8ff 13 * See the License for the specific language governing permissions and
bogdanm 0:9b334a45a8ff 14 * limitations under the License.
bogdanm 0:9b334a45a8ff 15 */
bogdanm 0:9b334a45a8ff 16 #include <string.h>
bogdanm 0:9b334a45a8ff 17
bogdanm 0:9b334a45a8ff 18 #include "ethernet_api.h"
bogdanm 0:9b334a45a8ff 19 #include "cmsis.h"
bogdanm 0:9b334a45a8ff 20 #include "mbed_interface.h"
bogdanm 0:9b334a45a8ff 21 #include "toolchain.h"
bogdanm 0:9b334a45a8ff 22 #include "mbed_error.h"
bogdanm 0:9b334a45a8ff 23
bogdanm 0:9b334a45a8ff 24 #define NEW_LOGIC 0
bogdanm 0:9b334a45a8ff 25 #define NEW_ETH_BUFFER 0
bogdanm 0:9b334a45a8ff 26
bogdanm 0:9b334a45a8ff 27 #if NEW_ETH_BUFFER
bogdanm 0:9b334a45a8ff 28
bogdanm 0:9b334a45a8ff 29 #define NUM_RX_FRAG 4 // Number of Rx Fragments (== packets)
bogdanm 0:9b334a45a8ff 30 #define NUM_TX_FRAG 3 // Number of Tx Fragments (== packets)
bogdanm 0:9b334a45a8ff 31
bogdanm 0:9b334a45a8ff 32 #define ETH_MAX_FLEN 1536 // Maximum Ethernet Frame Size
bogdanm 0:9b334a45a8ff 33 #define ETH_FRAG_SIZE ETH_MAX_FLEN // Packet Fragment size (same as packet length)
bogdanm 0:9b334a45a8ff 34
bogdanm 0:9b334a45a8ff 35 #else
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 // Memfree calculation:
bogdanm 0:9b334a45a8ff 38 // (16 * 1024) - ((2 * 4 * NUM_RX) + (2 * 4 * NUM_RX) + (0x300 * NUM_RX) +
bogdanm 0:9b334a45a8ff 39 // (2 * 4 * NUM_TX) + (1 * 4 * NUM_TX) + (0x300 * NUM_TX)) = 8556
bogdanm 0:9b334a45a8ff 40 /* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
bogdanm 0:9b334a45a8ff 41 #define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */
bogdanm 0:9b334a45a8ff 42 #define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */
bogdanm 0:9b334a45a8ff 43 //#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */
bogdanm 0:9b334a45a8ff 44
bogdanm 0:9b334a45a8ff 45 //#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
bogdanm 0:9b334a45a8ff 46 #define ETH_FRAG_SIZE 0x300 /* Packet Fragment size 1536/2 Bytes */
bogdanm 0:9b334a45a8ff 47 #define ETH_MAX_FLEN 0x300 /* Max. Ethernet Frame Size */
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 const int ethernet_MTU_SIZE = 0x300;
bogdanm 0:9b334a45a8ff 50
bogdanm 0:9b334a45a8ff 51 #endif
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 #define ETHERNET_ADDR_SIZE 6
bogdanm 0:9b334a45a8ff 54
bogdanm 0:9b334a45a8ff 55 PACKED struct RX_DESC_TypeDef { /* RX Descriptor struct */
bogdanm 0:9b334a45a8ff 56 unsigned int Packet;
bogdanm 0:9b334a45a8ff 57 unsigned int Ctrl;
bogdanm 0:9b334a45a8ff 58 };
bogdanm 0:9b334a45a8ff 59 typedef struct RX_DESC_TypeDef RX_DESC_TypeDef;
bogdanm 0:9b334a45a8ff 60
bogdanm 0:9b334a45a8ff 61 PACKED struct RX_STAT_TypeDef { /* RX Status struct */
bogdanm 0:9b334a45a8ff 62 unsigned int Info;
bogdanm 0:9b334a45a8ff 63 unsigned int HashCRC;
bogdanm 0:9b334a45a8ff 64 };
bogdanm 0:9b334a45a8ff 65 typedef struct RX_STAT_TypeDef RX_STAT_TypeDef;
bogdanm 0:9b334a45a8ff 66
bogdanm 0:9b334a45a8ff 67 PACKED struct TX_DESC_TypeDef { /* TX Descriptor struct */
bogdanm 0:9b334a45a8ff 68 unsigned int Packet;
bogdanm 0:9b334a45a8ff 69 unsigned int Ctrl;
bogdanm 0:9b334a45a8ff 70 };
bogdanm 0:9b334a45a8ff 71 typedef struct TX_DESC_TypeDef TX_DESC_TypeDef;
bogdanm 0:9b334a45a8ff 72
bogdanm 0:9b334a45a8ff 73 PACKED struct TX_STAT_TypeDef { /* TX Status struct */
bogdanm 0:9b334a45a8ff 74 unsigned int Info;
bogdanm 0:9b334a45a8ff 75 };
bogdanm 0:9b334a45a8ff 76 typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
bogdanm 0:9b334a45a8ff 77
bogdanm 0:9b334a45a8ff 78 /* MAC Configuration Register 1 */
bogdanm 0:9b334a45a8ff 79 #define MAC1_REC_EN 0x00000001 /* Receive Enable */
bogdanm 0:9b334a45a8ff 80 #define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */
bogdanm 0:9b334a45a8ff 81 #define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */
bogdanm 0:9b334a45a8ff 82 #define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */
bogdanm 0:9b334a45a8ff 83 #define MAC1_LOOPB 0x00000010 /* Loop Back Mode */
bogdanm 0:9b334a45a8ff 84 #define MAC1_RES_TX 0x00000100 /* Reset TX Logic */
bogdanm 0:9b334a45a8ff 85 #define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */
bogdanm 0:9b334a45a8ff 86 #define MAC1_RES_RX 0x00000400 /* Reset RX Logic */
bogdanm 0:9b334a45a8ff 87 #define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */
bogdanm 0:9b334a45a8ff 88 #define MAC1_SIM_RES 0x00004000 /* Simulation Reset */
bogdanm 0:9b334a45a8ff 89 #define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */
bogdanm 0:9b334a45a8ff 90
bogdanm 0:9b334a45a8ff 91 /* MAC Configuration Register 2 */
bogdanm 0:9b334a45a8ff 92 #define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */
bogdanm 0:9b334a45a8ff 93 #define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */
bogdanm 0:9b334a45a8ff 94 #define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */
bogdanm 0:9b334a45a8ff 95 #define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */
bogdanm 0:9b334a45a8ff 96 #define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */
bogdanm 0:9b334a45a8ff 97 #define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */
bogdanm 0:9b334a45a8ff 98 #define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */
bogdanm 0:9b334a45a8ff 99 #define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */
bogdanm 0:9b334a45a8ff 100 #define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */
bogdanm 0:9b334a45a8ff 101 #define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */
bogdanm 0:9b334a45a8ff 102 #define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */
bogdanm 0:9b334a45a8ff 103 #define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */
bogdanm 0:9b334a45a8ff 104 #define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */
bogdanm 0:9b334a45a8ff 105
bogdanm 0:9b334a45a8ff 106 /* Back-to-Back Inter-Packet-Gap Register */
bogdanm 0:9b334a45a8ff 107 #define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */
bogdanm 0:9b334a45a8ff 108 #define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110 /* Non Back-to-Back Inter-Packet-Gap Register */
bogdanm 0:9b334a45a8ff 111 #define IPGR_DEF 0x00000012 /* Recommended value */
bogdanm 0:9b334a45a8ff 112
bogdanm 0:9b334a45a8ff 113 /* Collision Window/Retry Register */
bogdanm 0:9b334a45a8ff 114 #define CLRT_DEF 0x0000370F /* Default value */
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116 /* PHY Support Register */
bogdanm 0:9b334a45a8ff 117 #define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */
bogdanm 0:9b334a45a8ff 118 //#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */
bogdanm 0:9b334a45a8ff 119 #define SUPP_RES_RMII 0x00000000 /* Reset Reduced MII Logic */
bogdanm 0:9b334a45a8ff 120
bogdanm 0:9b334a45a8ff 121 /* Test Register */
bogdanm 0:9b334a45a8ff 122 #define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */
bogdanm 0:9b334a45a8ff 123 #define TEST_TST_PAUSE 0x00000002 /* Test Pause */
bogdanm 0:9b334a45a8ff 124 #define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */
bogdanm 0:9b334a45a8ff 125
bogdanm 0:9b334a45a8ff 126 /* MII Management Configuration Register */
bogdanm 0:9b334a45a8ff 127 #define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */
bogdanm 0:9b334a45a8ff 128 #define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */
bogdanm 0:9b334a45a8ff 129 #define MCFG_CLK_SEL 0x0000003C /* Clock Select Mask */
bogdanm 0:9b334a45a8ff 130 #define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */
bogdanm 0:9b334a45a8ff 131
bogdanm 0:9b334a45a8ff 132 /* MII Management Command Register */
bogdanm 0:9b334a45a8ff 133 #define MCMD_READ 0x00000001 /* MII Read */
bogdanm 0:9b334a45a8ff 134 #define MCMD_SCAN 0x00000002 /* MII Scan continuously */
bogdanm 0:9b334a45a8ff 135
bogdanm 0:9b334a45a8ff 136 #define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
bogdanm 0:9b334a45a8ff 137 #define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
bogdanm 0:9b334a45a8ff 138
bogdanm 0:9b334a45a8ff 139 /* MII Management Address Register */
bogdanm 0:9b334a45a8ff 140 #define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */
bogdanm 0:9b334a45a8ff 141 #define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
bogdanm 0:9b334a45a8ff 142
bogdanm 0:9b334a45a8ff 143 /* MII Management Indicators Register */
bogdanm 0:9b334a45a8ff 144 #define MIND_BUSY 0x00000001 /* MII is Busy */
bogdanm 0:9b334a45a8ff 145 #define MIND_SCAN 0x00000002 /* MII Scanning in Progress */
bogdanm 0:9b334a45a8ff 146 #define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */
bogdanm 0:9b334a45a8ff 147 #define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */
bogdanm 0:9b334a45a8ff 148
bogdanm 0:9b334a45a8ff 149 /* Command Register */
bogdanm 0:9b334a45a8ff 150 #define CR_RX_EN 0x00000001 /* Enable Receive */
bogdanm 0:9b334a45a8ff 151 #define CR_TX_EN 0x00000002 /* Enable Transmit */
bogdanm 0:9b334a45a8ff 152 #define CR_REG_RES 0x00000008 /* Reset Host Registers */
bogdanm 0:9b334a45a8ff 153 #define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */
bogdanm 0:9b334a45a8ff 154 #define CR_RX_RES 0x00000020 /* Reset Receive Datapath */
bogdanm 0:9b334a45a8ff 155 #define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */
bogdanm 0:9b334a45a8ff 156 #define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */
bogdanm 0:9b334a45a8ff 157 #define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */
bogdanm 0:9b334a45a8ff 158 #define CR_RMII 0x00000200 /* Reduced MII Interface */
bogdanm 0:9b334a45a8ff 159 #define CR_FULL_DUP 0x00000400 /* Full Duplex */
bogdanm 0:9b334a45a8ff 160
bogdanm 0:9b334a45a8ff 161 /* Status Register */
bogdanm 0:9b334a45a8ff 162 #define SR_RX_EN 0x00000001 /* Enable Receive */
bogdanm 0:9b334a45a8ff 163 #define SR_TX_EN 0x00000002 /* Enable Transmit */
bogdanm 0:9b334a45a8ff 164
bogdanm 0:9b334a45a8ff 165 /* Transmit Status Vector 0 Register */
bogdanm 0:9b334a45a8ff 166 #define TSV0_CRC_ERR 0x00000001 /* CRC error */
bogdanm 0:9b334a45a8ff 167 #define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */
bogdanm 0:9b334a45a8ff 168 #define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */
bogdanm 0:9b334a45a8ff 169 #define TSV0_DONE 0x00000008 /* Tramsmission Completed */
bogdanm 0:9b334a45a8ff 170 #define TSV0_MCAST 0x00000010 /* Multicast Destination */
bogdanm 0:9b334a45a8ff 171 #define TSV0_BCAST 0x00000020 /* Broadcast Destination */
bogdanm 0:9b334a45a8ff 172 #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */
bogdanm 0:9b334a45a8ff 173 #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */
bogdanm 0:9b334a45a8ff 174 #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */
bogdanm 0:9b334a45a8ff 175 #define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */
bogdanm 0:9b334a45a8ff 176 #define TSV0_GIANT 0x00000400 /* Giant Frame */
bogdanm 0:9b334a45a8ff 177 #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */
bogdanm 0:9b334a45a8ff 178 #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */
bogdanm 0:9b334a45a8ff 179 #define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */
bogdanm 0:9b334a45a8ff 180 #define TSV0_PAUSE 0x20000000 /* Pause Frame */
bogdanm 0:9b334a45a8ff 181 #define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */
bogdanm 0:9b334a45a8ff 182 #define TSV0_VLAN 0x80000000 /* VLAN Frame */
bogdanm 0:9b334a45a8ff 183
bogdanm 0:9b334a45a8ff 184 /* Transmit Status Vector 1 Register */
bogdanm 0:9b334a45a8ff 185 #define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */
bogdanm 0:9b334a45a8ff 186 #define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */
bogdanm 0:9b334a45a8ff 187
bogdanm 0:9b334a45a8ff 188 /* Receive Status Vector Register */
bogdanm 0:9b334a45a8ff 189 #define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */
bogdanm 0:9b334a45a8ff 190 #define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */
bogdanm 0:9b334a45a8ff 191 #define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */
bogdanm 0:9b334a45a8ff 192 #define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */
bogdanm 0:9b334a45a8ff 193 #define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */
bogdanm 0:9b334a45a8ff 194 #define RSV_CRC_ERR 0x00100000 /* CRC Error */
bogdanm 0:9b334a45a8ff 195 #define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */
bogdanm 0:9b334a45a8ff 196 #define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */
bogdanm 0:9b334a45a8ff 197 #define RSV_REC_OK 0x00800000 /* Frame Received OK */
bogdanm 0:9b334a45a8ff 198 #define RSV_MCAST 0x01000000 /* Multicast Frame */
bogdanm 0:9b334a45a8ff 199 #define RSV_BCAST 0x02000000 /* Broadcast Frame */
bogdanm 0:9b334a45a8ff 200 #define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */
bogdanm 0:9b334a45a8ff 201 #define RSV_CTRL_FRAME 0x08000000 /* Control Frame */
bogdanm 0:9b334a45a8ff 202 #define RSV_PAUSE 0x10000000 /* Pause Frame */
bogdanm 0:9b334a45a8ff 203 #define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */
bogdanm 0:9b334a45a8ff 204 #define RSV_VLAN 0x40000000 /* VLAN Frame */
bogdanm 0:9b334a45a8ff 205
bogdanm 0:9b334a45a8ff 206 /* Flow Control Counter Register */
bogdanm 0:9b334a45a8ff 207 #define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */
bogdanm 0:9b334a45a8ff 208 #define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */
bogdanm 0:9b334a45a8ff 209
bogdanm 0:9b334a45a8ff 210 /* Flow Control Status Register */
bogdanm 0:9b334a45a8ff 211 #define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */
bogdanm 0:9b334a45a8ff 212
bogdanm 0:9b334a45a8ff 213 /* Receive Filter Control Register */
bogdanm 0:9b334a45a8ff 214 #define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */
bogdanm 0:9b334a45a8ff 215 #define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */
bogdanm 0:9b334a45a8ff 216 #define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */
bogdanm 0:9b334a45a8ff 217 #define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */
bogdanm 0:9b334a45a8ff 218 #define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/
bogdanm 0:9b334a45a8ff 219 #define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */
bogdanm 0:9b334a45a8ff 220 #define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */
bogdanm 0:9b334a45a8ff 221 #define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */
bogdanm 0:9b334a45a8ff 222
bogdanm 0:9b334a45a8ff 223 /* Receive Filter WoL Status/Clear Registers */
bogdanm 0:9b334a45a8ff 224 #define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */
bogdanm 0:9b334a45a8ff 225 #define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */
bogdanm 0:9b334a45a8ff 226 #define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */
bogdanm 0:9b334a45a8ff 227 #define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */
bogdanm 0:9b334a45a8ff 228 #define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */
bogdanm 0:9b334a45a8ff 229 #define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */
bogdanm 0:9b334a45a8ff 230 #define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */
bogdanm 0:9b334a45a8ff 231 #define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */
bogdanm 0:9b334a45a8ff 232
bogdanm 0:9b334a45a8ff 233 /* Interrupt Status/Enable/Clear/Set Registers */
bogdanm 0:9b334a45a8ff 234 #define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */
bogdanm 0:9b334a45a8ff 235 #define INT_RX_ERR 0x00000002 /* Receive Error */
bogdanm 0:9b334a45a8ff 236 #define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */
bogdanm 0:9b334a45a8ff 237 #define INT_RX_DONE 0x00000008 /* Receive Done */
bogdanm 0:9b334a45a8ff 238 #define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */
bogdanm 0:9b334a45a8ff 239 #define INT_TX_ERR 0x00000020 /* Transmit Error */
bogdanm 0:9b334a45a8ff 240 #define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */
bogdanm 0:9b334a45a8ff 241 #define INT_TX_DONE 0x00000080 /* Transmit Done */
bogdanm 0:9b334a45a8ff 242 #define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */
bogdanm 0:9b334a45a8ff 243 #define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */
bogdanm 0:9b334a45a8ff 244
bogdanm 0:9b334a45a8ff 245 /* Power Down Register */
bogdanm 0:9b334a45a8ff 246 #define PD_POWER_DOWN 0x80000000 /* Power Down MAC */
bogdanm 0:9b334a45a8ff 247
bogdanm 0:9b334a45a8ff 248 /* RX Descriptor Control Word */
bogdanm 0:9b334a45a8ff 249 #define RCTRL_SIZE 0x000007FF /* Buffer size mask */
bogdanm 0:9b334a45a8ff 250 #define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */
bogdanm 0:9b334a45a8ff 251
bogdanm 0:9b334a45a8ff 252 /* RX Status Hash CRC Word */
bogdanm 0:9b334a45a8ff 253 #define RHASH_SA 0x000001FF /* Hash CRC for Source Address */
bogdanm 0:9b334a45a8ff 254 #define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */
bogdanm 0:9b334a45a8ff 255
bogdanm 0:9b334a45a8ff 256 /* RX Status Information Word */
bogdanm 0:9b334a45a8ff 257 #define RINFO_SIZE 0x000007FF /* Data size in bytes */
bogdanm 0:9b334a45a8ff 258 #define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */
bogdanm 0:9b334a45a8ff 259 #define RINFO_VLAN 0x00080000 /* VLAN Frame */
bogdanm 0:9b334a45a8ff 260 #define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */
bogdanm 0:9b334a45a8ff 261 #define RINFO_MCAST 0x00200000 /* Multicast Frame */
bogdanm 0:9b334a45a8ff 262 #define RINFO_BCAST 0x00400000 /* Broadcast Frame */
bogdanm 0:9b334a45a8ff 263 #define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */
bogdanm 0:9b334a45a8ff 264 #define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */
bogdanm 0:9b334a45a8ff 265 #define RINFO_LEN_ERR 0x02000000 /* Length Error */
bogdanm 0:9b334a45a8ff 266 #define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */
bogdanm 0:9b334a45a8ff 267 #define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */
bogdanm 0:9b334a45a8ff 268 #define RINFO_OVERRUN 0x10000000 /* Receive overrun */
bogdanm 0:9b334a45a8ff 269 #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */
bogdanm 0:9b334a45a8ff 270 #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */
bogdanm 0:9b334a45a8ff 271 #define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
bogdanm 0:9b334a45a8ff 272
bogdanm 0:9b334a45a8ff 273 //#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
bogdanm 0:9b334a45a8ff 274 #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | \
bogdanm 0:9b334a45a8ff 275 RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
bogdanm 0:9b334a45a8ff 276
bogdanm 0:9b334a45a8ff 277
bogdanm 0:9b334a45a8ff 278 /* TX Descriptor Control Word */
bogdanm 0:9b334a45a8ff 279 #define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */
bogdanm 0:9b334a45a8ff 280 #define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */
bogdanm 0:9b334a45a8ff 281 #define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */
bogdanm 0:9b334a45a8ff 282 #define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */
bogdanm 0:9b334a45a8ff 283 #define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */
bogdanm 0:9b334a45a8ff 284 #define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */
bogdanm 0:9b334a45a8ff 285 #define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */
bogdanm 0:9b334a45a8ff 286
bogdanm 0:9b334a45a8ff 287 /* TX Status Information Word */
bogdanm 0:9b334a45a8ff 288 #define TINFO_COL_CNT 0x01E00000 /* Collision Count */
bogdanm 0:9b334a45a8ff 289 #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */
bogdanm 0:9b334a45a8ff 290 #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */
bogdanm 0:9b334a45a8ff 291 #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */
bogdanm 0:9b334a45a8ff 292 #define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */
bogdanm 0:9b334a45a8ff 293 #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */
bogdanm 0:9b334a45a8ff 294 #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */
bogdanm 0:9b334a45a8ff 295 #define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
bogdanm 0:9b334a45a8ff 296
bogdanm 0:9b334a45a8ff 297 /* ENET Device Revision ID */
bogdanm 0:9b334a45a8ff 298 #define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */
bogdanm 0:9b334a45a8ff 299
bogdanm 0:9b334a45a8ff 300 /* DP83848C PHY Registers */
bogdanm 0:9b334a45a8ff 301 #define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
bogdanm 0:9b334a45a8ff 302 #define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
bogdanm 0:9b334a45a8ff 303 #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
bogdanm 0:9b334a45a8ff 304 #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
bogdanm 0:9b334a45a8ff 305 #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
bogdanm 0:9b334a45a8ff 306 #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
bogdanm 0:9b334a45a8ff 307 #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
bogdanm 0:9b334a45a8ff 308 #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
bogdanm 0:9b334a45a8ff 309
bogdanm 0:9b334a45a8ff 310 /* PHY Extended Registers */
bogdanm 0:9b334a45a8ff 311 #define PHY_REG_STS 0x10 /* Status Register */
bogdanm 0:9b334a45a8ff 312 #define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */
bogdanm 0:9b334a45a8ff 313 #define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */
bogdanm 0:9b334a45a8ff 314 #define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */
bogdanm 0:9b334a45a8ff 315 #define PHY_REG_RECR 0x15 /* Receive Error Counter */
bogdanm 0:9b334a45a8ff 316 #define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
bogdanm 0:9b334a45a8ff 317 #define PHY_REG_RBR 0x17 /* RMII and Bypass Register */
bogdanm 0:9b334a45a8ff 318 #define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */
bogdanm 0:9b334a45a8ff 319 #define PHY_REG_PHYCR 0x19 /* PHY Control Register */
bogdanm 0:9b334a45a8ff 320 #define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */
bogdanm 0:9b334a45a8ff 321 #define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */
bogdanm 0:9b334a45a8ff 322 #define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */
bogdanm 0:9b334a45a8ff 323
bogdanm 0:9b334a45a8ff 324 #define PHY_REG_SCSR 0x1F /* PHY Special Control/Status Register */
bogdanm 0:9b334a45a8ff 325
bogdanm 0:9b334a45a8ff 326 #define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
bogdanm 0:9b334a45a8ff 327 #define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
bogdanm 0:9b334a45a8ff 328 #define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
bogdanm 0:9b334a45a8ff 329 #define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
bogdanm 0:9b334a45a8ff 330 #define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */
bogdanm 0:9b334a45a8ff 331
bogdanm 0:9b334a45a8ff 332 #define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */
bogdanm 0:9b334a45a8ff 333 #define DP83848C_ID 0x20005C90 /* PHY Identifier - DP83848C */
bogdanm 0:9b334a45a8ff 334
bogdanm 0:9b334a45a8ff 335 #define LAN8720_ID 0x0007C0F0 /* PHY Identifier - LAN8720 */
bogdanm 0:9b334a45a8ff 336
bogdanm 0:9b334a45a8ff 337 #define PHY_STS_LINK 0x0001 /* PHY Status Link Mask */
bogdanm 0:9b334a45a8ff 338 #define PHY_STS_SPEED 0x0002 /* PHY Status Speed Mask */
bogdanm 0:9b334a45a8ff 339 #define PHY_STS_DUPLEX 0x0004 /* PHY Status Duplex Mask */
bogdanm 0:9b334a45a8ff 340
bogdanm 0:9b334a45a8ff 341 #define PHY_BMCR_RESET 0x8000 /* PHY Reset */
bogdanm 0:9b334a45a8ff 342
bogdanm 0:9b334a45a8ff 343 #define PHY_BMSR_LINK 0x0004 /* PHY BMSR Link valid */
bogdanm 0:9b334a45a8ff 344
bogdanm 0:9b334a45a8ff 345 #define PHY_SCSR_100MBIT 0x0008 /* Speed: 1=100 MBit, 0=10Mbit */
bogdanm 0:9b334a45a8ff 346 #define PHY_SCSR_DUPLEX 0x0010 /* PHY Duplex Mask */
bogdanm 0:9b334a45a8ff 347
bogdanm 0:9b334a45a8ff 348
bogdanm 0:9b334a45a8ff 349 static int phy_read(unsigned int PhyReg);
bogdanm 0:9b334a45a8ff 350 static int phy_write(unsigned int PhyReg, unsigned short Data);
bogdanm 0:9b334a45a8ff 351
bogdanm 0:9b334a45a8ff 352 static void txdscr_init(void);
bogdanm 0:9b334a45a8ff 353 static void rxdscr_init(void);
bogdanm 0:9b334a45a8ff 354
bogdanm 0:9b334a45a8ff 355 #if defined (__ICCARM__)
bogdanm 0:9b334a45a8ff 356 # define AHBSRAM1
bogdanm 0:9b334a45a8ff 357 #elif defined(TOOLCHAIN_GCC_CR)
bogdanm 0:9b334a45a8ff 358 # define AHBSRAM1 __attribute__((section(".data.$RamPeriph32")))
bogdanm 0:9b334a45a8ff 359 #else
bogdanm 0:9b334a45a8ff 360 # define AHBSRAM1 __attribute__((section("AHBSRAM1"),aligned))
bogdanm 0:9b334a45a8ff 361 #endif
bogdanm 0:9b334a45a8ff 362
bogdanm 0:9b334a45a8ff 363 AHBSRAM1 volatile uint8_t rxbuf[NUM_RX_FRAG][ETH_FRAG_SIZE];
bogdanm 0:9b334a45a8ff 364 AHBSRAM1 volatile uint8_t txbuf[NUM_TX_FRAG][ETH_FRAG_SIZE];
bogdanm 0:9b334a45a8ff 365 AHBSRAM1 volatile RX_DESC_TypeDef rxdesc[NUM_RX_FRAG];
bogdanm 0:9b334a45a8ff 366 AHBSRAM1 volatile RX_STAT_TypeDef rxstat[NUM_RX_FRAG];
bogdanm 0:9b334a45a8ff 367 AHBSRAM1 volatile TX_DESC_TypeDef txdesc[NUM_TX_FRAG];
bogdanm 0:9b334a45a8ff 368 AHBSRAM1 volatile TX_STAT_TypeDef txstat[NUM_TX_FRAG];
bogdanm 0:9b334a45a8ff 369
bogdanm 0:9b334a45a8ff 370
bogdanm 0:9b334a45a8ff 371 #if NEW_LOGIC
bogdanm 0:9b334a45a8ff 372 static int rx_consume_offset = -1;
bogdanm 0:9b334a45a8ff 373 static int tx_produce_offset = -1;
bogdanm 0:9b334a45a8ff 374 #else
bogdanm 0:9b334a45a8ff 375 static int send_doff = 0;
bogdanm 0:9b334a45a8ff 376 static int send_idx = -1;
bogdanm 0:9b334a45a8ff 377 static int send_size = 0;
bogdanm 0:9b334a45a8ff 378
bogdanm 0:9b334a45a8ff 379 static int receive_soff = 0;
bogdanm 0:9b334a45a8ff 380 static int receive_idx = -1;
bogdanm 0:9b334a45a8ff 381 #endif
bogdanm 0:9b334a45a8ff 382
bogdanm 0:9b334a45a8ff 383 static uint32_t phy_id = 0;
bogdanm 0:9b334a45a8ff 384
bogdanm 0:9b334a45a8ff 385 static inline int rinc(int idx, int mod) {
bogdanm 0:9b334a45a8ff 386 ++idx;
bogdanm 0:9b334a45a8ff 387 idx %= mod;
bogdanm 0:9b334a45a8ff 388 return idx;
bogdanm 0:9b334a45a8ff 389 }
bogdanm 0:9b334a45a8ff 390
bogdanm 0:9b334a45a8ff 391 //extern unsigned int SystemFrequency;
bogdanm 0:9b334a45a8ff 392 static inline unsigned int clockselect() {
bogdanm 0:9b334a45a8ff 393 if(SystemCoreClock < 10000000) {
bogdanm 0:9b334a45a8ff 394 return 1;
bogdanm 0:9b334a45a8ff 395 } else if(SystemCoreClock < 15000000) {
bogdanm 0:9b334a45a8ff 396 return 2;
bogdanm 0:9b334a45a8ff 397 } else if(SystemCoreClock < 20000000) {
bogdanm 0:9b334a45a8ff 398 return 3;
bogdanm 0:9b334a45a8ff 399 } else if(SystemCoreClock < 25000000) {
bogdanm 0:9b334a45a8ff 400 return 4;
bogdanm 0:9b334a45a8ff 401 } else if(SystemCoreClock < 35000000) {
bogdanm 0:9b334a45a8ff 402 return 5;
bogdanm 0:9b334a45a8ff 403 } else if(SystemCoreClock < 50000000) {
bogdanm 0:9b334a45a8ff 404 return 6;
bogdanm 0:9b334a45a8ff 405 } else if(SystemCoreClock < 70000000) {
bogdanm 0:9b334a45a8ff 406 return 7;
bogdanm 0:9b334a45a8ff 407 } else if(SystemCoreClock < 80000000) {
bogdanm 0:9b334a45a8ff 408 return 8;
bogdanm 0:9b334a45a8ff 409 } else if(SystemCoreClock < 90000000) {
bogdanm 0:9b334a45a8ff 410 return 9;
bogdanm 0:9b334a45a8ff 411 } else if(SystemCoreClock < 100000000) {
bogdanm 0:9b334a45a8ff 412 return 10;
bogdanm 0:9b334a45a8ff 413 } else if(SystemCoreClock < 120000000) {
bogdanm 0:9b334a45a8ff 414 return 11;
bogdanm 0:9b334a45a8ff 415 } else if(SystemCoreClock < 130000000) {
bogdanm 0:9b334a45a8ff 416 return 12;
bogdanm 0:9b334a45a8ff 417 } else if(SystemCoreClock < 140000000) {
bogdanm 0:9b334a45a8ff 418 return 13;
bogdanm 0:9b334a45a8ff 419 } else if(SystemCoreClock < 150000000) {
bogdanm 0:9b334a45a8ff 420 return 15;
bogdanm 0:9b334a45a8ff 421 } else if(SystemCoreClock < 160000000) {
bogdanm 0:9b334a45a8ff 422 return 16;
bogdanm 0:9b334a45a8ff 423 } else {
bogdanm 0:9b334a45a8ff 424 return 0;
bogdanm 0:9b334a45a8ff 425 }
bogdanm 0:9b334a45a8ff 426 }
bogdanm 0:9b334a45a8ff 427
bogdanm 0:9b334a45a8ff 428 #ifndef min
bogdanm 0:9b334a45a8ff 429 #define min(x, y) (((x)<(y))?(x):(y))
bogdanm 0:9b334a45a8ff 430 #endif
bogdanm 0:9b334a45a8ff 431
bogdanm 0:9b334a45a8ff 432 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 433 Ethernet Device initialize
bogdanm 0:9b334a45a8ff 434 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 435 int ethernet_init() {
bogdanm 0:9b334a45a8ff 436 int regv, tout;
bogdanm 0:9b334a45a8ff 437 char mac[ETHERNET_ADDR_SIZE];
bogdanm 0:9b334a45a8ff 438 unsigned int clock = clockselect();
bogdanm 0:9b334a45a8ff 439
bogdanm 0:9b334a45a8ff 440 LPC_SC->PCONP |= 0x40000000; /* Power Up the EMAC controller. */
bogdanm 0:9b334a45a8ff 441
bogdanm 0:9b334a45a8ff 442 LPC_PINCON->PINSEL2 = 0x50150105; /* Enable P1 Ethernet Pins. */
bogdanm 0:9b334a45a8ff 443 LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005;
bogdanm 0:9b334a45a8ff 444
bogdanm 0:9b334a45a8ff 445 /* Reset all EMAC internal modules. */
bogdanm 0:9b334a45a8ff 446 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX |
bogdanm 0:9b334a45a8ff 447 MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
bogdanm 0:9b334a45a8ff 448 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
bogdanm 0:9b334a45a8ff 449
bogdanm 0:9b334a45a8ff 450 for(tout = 100; tout; tout--) __NOP(); /* A short delay after reset. */
bogdanm 0:9b334a45a8ff 451
bogdanm 0:9b334a45a8ff 452 LPC_EMAC->MAC1 = MAC1_PASS_ALL; /* Initialize MAC control registers. */
bogdanm 0:9b334a45a8ff 453 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
bogdanm 0:9b334a45a8ff 454 LPC_EMAC->MAXF = ETH_MAX_FLEN;
bogdanm 0:9b334a45a8ff 455 LPC_EMAC->CLRT = CLRT_DEF;
bogdanm 0:9b334a45a8ff 456 LPC_EMAC->IPGR = IPGR_DEF;
bogdanm 0:9b334a45a8ff 457
bogdanm 0:9b334a45a8ff 458 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM; /* Enable Reduced MII interface. */
bogdanm 0:9b334a45a8ff 459
bogdanm 0:9b334a45a8ff 460 LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL; /* Set clock */
bogdanm 0:9b334a45a8ff 461 LPC_EMAC->MCFG |= MCFG_RES_MII; /* and reset */
bogdanm 0:9b334a45a8ff 462
bogdanm 0:9b334a45a8ff 463 for(tout = 100; tout; tout--) __NOP(); /* A short delay */
bogdanm 0:9b334a45a8ff 464
bogdanm 0:9b334a45a8ff 465 LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL;
bogdanm 0:9b334a45a8ff 466 LPC_EMAC->MCMD = 0;
bogdanm 0:9b334a45a8ff 467
bogdanm 0:9b334a45a8ff 468 LPC_EMAC->SUPP = SUPP_RES_RMII; /* Reset Reduced MII Logic. */
bogdanm 0:9b334a45a8ff 469
bogdanm 0:9b334a45a8ff 470 for (tout = 100; tout; tout--) __NOP(); /* A short delay */
bogdanm 0:9b334a45a8ff 471
bogdanm 0:9b334a45a8ff 472 LPC_EMAC->SUPP = 0;
bogdanm 0:9b334a45a8ff 473
bogdanm 0:9b334a45a8ff 474 phy_write(PHY_REG_BMCR, PHY_BMCR_RESET); /* perform PHY reset */
bogdanm 0:9b334a45a8ff 475 for(tout = 0x20000; ; tout--) { /* Wait for hardware reset to end. */
bogdanm 0:9b334a45a8ff 476 regv = phy_read(PHY_REG_BMCR);
bogdanm 0:9b334a45a8ff 477 if(regv < 0 || tout == 0) {
bogdanm 0:9b334a45a8ff 478 return -1; /* Error */
bogdanm 0:9b334a45a8ff 479 }
bogdanm 0:9b334a45a8ff 480 if(!(regv & PHY_BMCR_RESET)) {
bogdanm 0:9b334a45a8ff 481 break; /* Reset complete. */
bogdanm 0:9b334a45a8ff 482 }
bogdanm 0:9b334a45a8ff 483 }
bogdanm 0:9b334a45a8ff 484
bogdanm 0:9b334a45a8ff 485 phy_id = (phy_read(PHY_REG_IDR1) << 16);
bogdanm 0:9b334a45a8ff 486 phy_id |= (phy_read(PHY_REG_IDR2) & 0XFFF0);
bogdanm 0:9b334a45a8ff 487
bogdanm 0:9b334a45a8ff 488 if (phy_id != DP83848C_ID && phy_id != LAN8720_ID) {
bogdanm 0:9b334a45a8ff 489 error("Unknown Ethernet PHY (%x)", (unsigned int)phy_id);
bogdanm 0:9b334a45a8ff 490 }
bogdanm 0:9b334a45a8ff 491
bogdanm 0:9b334a45a8ff 492 ethernet_set_link(-1, 0);
bogdanm 0:9b334a45a8ff 493
bogdanm 0:9b334a45a8ff 494 /* Set the Ethernet MAC Address registers */
bogdanm 0:9b334a45a8ff 495 ethernet_address(mac);
bogdanm 0:9b334a45a8ff 496 LPC_EMAC->SA0 = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4];
bogdanm 0:9b334a45a8ff 497 LPC_EMAC->SA1 = ((uint32_t)mac[3] << 8) | (uint32_t)mac[2];
bogdanm 0:9b334a45a8ff 498 LPC_EMAC->SA2 = ((uint32_t)mac[1] << 8) | (uint32_t)mac[0];
bogdanm 0:9b334a45a8ff 499
bogdanm 0:9b334a45a8ff 500 txdscr_init(); /* initialize DMA TX Descriptor */
bogdanm 0:9b334a45a8ff 501 rxdscr_init(); /* initialize DMA RX Descriptor */
bogdanm 0:9b334a45a8ff 502
bogdanm 0:9b334a45a8ff 503 LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_MCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
bogdanm 0:9b334a45a8ff 504 /* Receive Broadcast, Perfect Match Packets */
bogdanm 0:9b334a45a8ff 505
bogdanm 0:9b334a45a8ff 506 LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; /* Enable EMAC interrupts. */
bogdanm 0:9b334a45a8ff 507 LPC_EMAC->IntClear = 0xFFFF; /* Reset all interrupts */
bogdanm 0:9b334a45a8ff 508
bogdanm 0:9b334a45a8ff 509
bogdanm 0:9b334a45a8ff 510 LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN); /* Enable receive and transmit mode of MAC Ethernet core */
bogdanm 0:9b334a45a8ff 511 LPC_EMAC->MAC1 |= MAC1_REC_EN;
bogdanm 0:9b334a45a8ff 512
bogdanm 0:9b334a45a8ff 513 #if NEW_LOGIC
bogdanm 0:9b334a45a8ff 514 rx_consume_offset = -1;
bogdanm 0:9b334a45a8ff 515 tx_produce_offset = -1;
bogdanm 0:9b334a45a8ff 516 #else
bogdanm 0:9b334a45a8ff 517 send_doff = 0;
bogdanm 0:9b334a45a8ff 518 send_idx = -1;
bogdanm 0:9b334a45a8ff 519 send_size = 0;
bogdanm 0:9b334a45a8ff 520
bogdanm 0:9b334a45a8ff 521 receive_soff = 0;
bogdanm 0:9b334a45a8ff 522 receive_idx = -1;
bogdanm 0:9b334a45a8ff 523 #endif
bogdanm 0:9b334a45a8ff 524
bogdanm 0:9b334a45a8ff 525 return 0;
bogdanm 0:9b334a45a8ff 526 }
bogdanm 0:9b334a45a8ff 527
bogdanm 0:9b334a45a8ff 528 /*----------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 529 Ethernet Device Uninitialize
bogdanm 0:9b334a45a8ff 530 *----------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 531 void ethernet_free() {
bogdanm 0:9b334a45a8ff 532 LPC_EMAC->IntEnable &= ~(INT_RX_DONE | INT_TX_DONE);
bogdanm 0:9b334a45a8ff 533 LPC_EMAC->IntClear = 0xFFFF;
bogdanm 0:9b334a45a8ff 534
bogdanm 0:9b334a45a8ff 535 LPC_SC->PCONP &= ~0x40000000; /* Power down the EMAC controller. */
bogdanm 0:9b334a45a8ff 536
bogdanm 0:9b334a45a8ff 537 LPC_PINCON->PINSEL2 &= ~0x50150105; /* Disable P1 ethernet pins. */
bogdanm 0:9b334a45a8ff 538 LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000000;
bogdanm 0:9b334a45a8ff 539 }
bogdanm 0:9b334a45a8ff 540
bogdanm 0:9b334a45a8ff 541 // if(TxProduceIndex == TxConsumeIndex) buffer array is empty
bogdanm 0:9b334a45a8ff 542 // if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill
bogdanm 0:9b334a45a8ff 543 // TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment
bogdanm 0:9b334a45a8ff 544 // TxConsumeIndex - The buffer that will/is beign sent by hardware
bogdanm 0:9b334a45a8ff 545
bogdanm 0:9b334a45a8ff 546 int ethernet_write(const char *data, int slen) {
bogdanm 0:9b334a45a8ff 547
bogdanm 0:9b334a45a8ff 548 #if NEW_LOGIC
bogdanm 0:9b334a45a8ff 549
bogdanm 0:9b334a45a8ff 550 if(tx_produce_offset < 0) { // mark as active if not already
bogdanm 0:9b334a45a8ff 551 tx_produce_offset = 0;
bogdanm 0:9b334a45a8ff 552 }
bogdanm 0:9b334a45a8ff 553
bogdanm 0:9b334a45a8ff 554 int index = LPC_EMAC->TxProduceIndex;
bogdanm 0:9b334a45a8ff 555
bogdanm 0:9b334a45a8ff 556 int remaining = ETH_MAX_FLEN - tx_produce_offset - 4; // bytes written plus checksum
bogdanm 0:9b334a45a8ff 557 int requested = slen;
bogdanm 0:9b334a45a8ff 558 int ncopy = min(remaining, requested);
bogdanm 0:9b334a45a8ff 559
bogdanm 0:9b334a45a8ff 560 void *pdst = (void *)(txdesc[index].Packet + tx_produce_offset);
bogdanm 0:9b334a45a8ff 561 void *psrc = (void *)(data);
bogdanm 0:9b334a45a8ff 562
bogdanm 0:9b334a45a8ff 563 if(ncopy > 0 ){
bogdanm 0:9b334a45a8ff 564 if(data != NULL) {
bogdanm 0:9b334a45a8ff 565 memcpy(pdst, psrc, ncopy);
bogdanm 0:9b334a45a8ff 566 } else {
bogdanm 0:9b334a45a8ff 567 memset(pdst, 0, ncopy);
bogdanm 0:9b334a45a8ff 568 }
bogdanm 0:9b334a45a8ff 569 }
bogdanm 0:9b334a45a8ff 570
bogdanm 0:9b334a45a8ff 571 tx_produce_offset += ncopy;
bogdanm 0:9b334a45a8ff 572
bogdanm 0:9b334a45a8ff 573 return ncopy;
bogdanm 0:9b334a45a8ff 574
bogdanm 0:9b334a45a8ff 575 #else
bogdanm 0:9b334a45a8ff 576 void *pdst, *psrc;
bogdanm 0:9b334a45a8ff 577 const int dlen = ETH_FRAG_SIZE;
bogdanm 0:9b334a45a8ff 578 int copy = 0;
bogdanm 0:9b334a45a8ff 579 int soff = 0;
bogdanm 0:9b334a45a8ff 580
bogdanm 0:9b334a45a8ff 581 if(send_idx == -1) {
bogdanm 0:9b334a45a8ff 582 send_idx = LPC_EMAC->TxProduceIndex;
bogdanm 0:9b334a45a8ff 583 }
bogdanm 0:9b334a45a8ff 584
bogdanm 0:9b334a45a8ff 585 if(slen + send_doff > ethernet_MTU_SIZE) {
bogdanm 0:9b334a45a8ff 586 return -1;
bogdanm 0:9b334a45a8ff 587 }
bogdanm 0:9b334a45a8ff 588
bogdanm 0:9b334a45a8ff 589 do {
bogdanm 0:9b334a45a8ff 590 copy = min(slen - soff, dlen - send_doff);
bogdanm 0:9b334a45a8ff 591 pdst = (void *)(txdesc[send_idx].Packet + send_doff);
bogdanm 0:9b334a45a8ff 592 psrc = (void *)(data + soff);
bogdanm 0:9b334a45a8ff 593 if(send_doff + copy > ETH_FRAG_SIZE) {
bogdanm 0:9b334a45a8ff 594 txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT);
bogdanm 0:9b334a45a8ff 595 send_idx = rinc(send_idx, NUM_TX_FRAG);
bogdanm 0:9b334a45a8ff 596 send_doff = 0;
bogdanm 0:9b334a45a8ff 597 }
bogdanm 0:9b334a45a8ff 598
bogdanm 0:9b334a45a8ff 599 if(data != NULL) {
bogdanm 0:9b334a45a8ff 600 memcpy(pdst, psrc, copy);
bogdanm 0:9b334a45a8ff 601 } else {
bogdanm 0:9b334a45a8ff 602 memset(pdst, 0, copy);
bogdanm 0:9b334a45a8ff 603 }
bogdanm 0:9b334a45a8ff 604
bogdanm 0:9b334a45a8ff 605 soff += copy;
bogdanm 0:9b334a45a8ff 606 send_doff += copy;
bogdanm 0:9b334a45a8ff 607 send_size += copy;
bogdanm 0:9b334a45a8ff 608 } while(soff != slen);
bogdanm 0:9b334a45a8ff 609
bogdanm 0:9b334a45a8ff 610 return soff;
bogdanm 0:9b334a45a8ff 611 #endif
bogdanm 0:9b334a45a8ff 612 }
bogdanm 0:9b334a45a8ff 613
bogdanm 0:9b334a45a8ff 614 int ethernet_send() {
bogdanm 0:9b334a45a8ff 615
bogdanm 0:9b334a45a8ff 616 #if NEW_LOGIC
bogdanm 0:9b334a45a8ff 617 if(tx_produce_offset < 0) { // no buffer active
bogdanm 0:9b334a45a8ff 618 return -1;
bogdanm 0:9b334a45a8ff 619 }
bogdanm 0:9b334a45a8ff 620
bogdanm 0:9b334a45a8ff 621 // ensure there is a link
bogdanm 0:9b334a45a8ff 622 if(!ethernet_link()) {
bogdanm 0:9b334a45a8ff 623 return -2;
bogdanm 0:9b334a45a8ff 624 }
bogdanm 0:9b334a45a8ff 625
bogdanm 0:9b334a45a8ff 626 // we have been writing in to a buffer, so finalise it
bogdanm 0:9b334a45a8ff 627 int size = tx_produce_offset;
bogdanm 0:9b334a45a8ff 628 int index = LPC_EMAC->TxProduceIndex;
bogdanm 0:9b334a45a8ff 629 txdesc[index].Ctrl = (tx_produce_offset-1) | (TCTRL_INT | TCTRL_LAST);
bogdanm 0:9b334a45a8ff 630
bogdanm 0:9b334a45a8ff 631 // Increment ProduceIndex to allow it to be sent
bogdanm 0:9b334a45a8ff 632 // We can only do this if the next slot is free
bogdanm 0:9b334a45a8ff 633 int next = rinc(index, NUM_TX_FRAG);
bogdanm 0:9b334a45a8ff 634 while(next == LPC_EMAC->TxConsumeIndex) {
bogdanm 0:9b334a45a8ff 635 for(int i=0; i<1000; i++) { __NOP(); }
bogdanm 0:9b334a45a8ff 636 }
bogdanm 0:9b334a45a8ff 637
bogdanm 0:9b334a45a8ff 638 LPC_EMAC->TxProduceIndex = next;
bogdanm 0:9b334a45a8ff 639 tx_produce_offset = -1;
bogdanm 0:9b334a45a8ff 640 return size;
bogdanm 0:9b334a45a8ff 641
bogdanm 0:9b334a45a8ff 642 #else
bogdanm 0:9b334a45a8ff 643 int s = send_size;
bogdanm 0:9b334a45a8ff 644 txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT | TCTRL_LAST);
bogdanm 0:9b334a45a8ff 645 send_idx = rinc(send_idx, NUM_TX_FRAG);
bogdanm 0:9b334a45a8ff 646 LPC_EMAC->TxProduceIndex = send_idx;
bogdanm 0:9b334a45a8ff 647 send_doff = 0;
bogdanm 0:9b334a45a8ff 648 send_idx = -1;
bogdanm 0:9b334a45a8ff 649 send_size = 0;
bogdanm 0:9b334a45a8ff 650 return s;
bogdanm 0:9b334a45a8ff 651 #endif
bogdanm 0:9b334a45a8ff 652 }
bogdanm 0:9b334a45a8ff 653
bogdanm 0:9b334a45a8ff 654 // RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read
bogdanm 0:9b334a45a8ff 655 // RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd
bogdanm 0:9b334a45a8ff 656 //
bogdanm 0:9b334a45a8ff 657 // if(RxConsumeIndex == RxProduceIndex) buffer array is empty
bogdanm 0:9b334a45a8ff 658 // if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full
bogdanm 0:9b334a45a8ff 659
bogdanm 0:9b334a45a8ff 660 // Recevies an arrived ethernet packet.
bogdanm 0:9b334a45a8ff 661 // Receiving an ethernet packet will drop the last received ethernet packet
bogdanm 0:9b334a45a8ff 662 // and make a new ethernet packet ready to read.
bogdanm 0:9b334a45a8ff 663 // Returns size of packet, else 0 if nothing to receive
bogdanm 0:9b334a45a8ff 664
bogdanm 0:9b334a45a8ff 665 // We read from RxConsumeIndex from position rx_consume_offset
bogdanm 0:9b334a45a8ff 666 // if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading
bogdanm 0:9b334a45a8ff 667 // rx_consume_offset = -1 // no frame
bogdanm 0:9b334a45a8ff 668 // rx_consume_offset = 0 // start of frame
bogdanm 0:9b334a45a8ff 669 // Assumption: A fragment should alway be a whole frame
bogdanm 0:9b334a45a8ff 670
bogdanm 0:9b334a45a8ff 671 int ethernet_receive() {
bogdanm 0:9b334a45a8ff 672 #if NEW_LOGIC
bogdanm 0:9b334a45a8ff 673
bogdanm 0:9b334a45a8ff 674 // if we are currently reading a valid RxConsume buffer, increment to the next one
bogdanm 0:9b334a45a8ff 675 if(rx_consume_offset >= 0) {
bogdanm 0:9b334a45a8ff 676 LPC_EMAC->RxConsumeIndex = rinc(LPC_EMAC->RxConsumeIndex, NUM_RX_FRAG);
bogdanm 0:9b334a45a8ff 677 }
bogdanm 0:9b334a45a8ff 678
bogdanm 0:9b334a45a8ff 679 // if the buffer is empty, mark it as no valid buffer
bogdanm 0:9b334a45a8ff 680 if(LPC_EMAC->RxConsumeIndex == LPC_EMAC->RxProduceIndex) {
bogdanm 0:9b334a45a8ff 681 rx_consume_offset = -1;
bogdanm 0:9b334a45a8ff 682 return 0;
bogdanm 0:9b334a45a8ff 683 }
bogdanm 0:9b334a45a8ff 684
bogdanm 0:9b334a45a8ff 685 uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
bogdanm 0:9b334a45a8ff 686 rx_consume_offset = 0;
bogdanm 0:9b334a45a8ff 687
bogdanm 0:9b334a45a8ff 688 // check if it is not marked as last or for errors
bogdanm 0:9b334a45a8ff 689 if(!(info & RINFO_LAST_FLAG) || (info & RINFO_ERR_MASK)) {
bogdanm 0:9b334a45a8ff 690 return -1;
bogdanm 0:9b334a45a8ff 691 }
bogdanm 0:9b334a45a8ff 692
bogdanm 0:9b334a45a8ff 693 int size = (info & RINFO_SIZE) + 1;
bogdanm 0:9b334a45a8ff 694 return size - 4; // don't include checksum bytes
bogdanm 0:9b334a45a8ff 695
bogdanm 0:9b334a45a8ff 696 #else
bogdanm 0:9b334a45a8ff 697 if(receive_idx == -1) {
bogdanm 0:9b334a45a8ff 698 receive_idx = LPC_EMAC->RxConsumeIndex;
bogdanm 0:9b334a45a8ff 699 } else {
bogdanm 0:9b334a45a8ff 700 while(!(rxstat[receive_idx].Info & RINFO_LAST_FLAG) && ((uint32_t)receive_idx != LPC_EMAC->RxProduceIndex)) {
bogdanm 0:9b334a45a8ff 701 receive_idx = rinc(receive_idx, NUM_RX_FRAG);
bogdanm 0:9b334a45a8ff 702 }
bogdanm 0:9b334a45a8ff 703 unsigned int info = rxstat[receive_idx].Info;
bogdanm 0:9b334a45a8ff 704 int slen = (info & RINFO_SIZE) + 1;
bogdanm 0:9b334a45a8ff 705
bogdanm 0:9b334a45a8ff 706 if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
bogdanm 0:9b334a45a8ff 707 /* Invalid frame, ignore it and free buffer. */
bogdanm 0:9b334a45a8ff 708 receive_idx = rinc(receive_idx, NUM_RX_FRAG);
bogdanm 0:9b334a45a8ff 709 }
bogdanm 0:9b334a45a8ff 710 receive_idx = rinc(receive_idx, NUM_RX_FRAG);
bogdanm 0:9b334a45a8ff 711 receive_soff = 0;
bogdanm 0:9b334a45a8ff 712
bogdanm 0:9b334a45a8ff 713 LPC_EMAC->RxConsumeIndex = receive_idx;
bogdanm 0:9b334a45a8ff 714 }
bogdanm 0:9b334a45a8ff 715
bogdanm 0:9b334a45a8ff 716 if((uint32_t)receive_idx == LPC_EMAC->RxProduceIndex) {
bogdanm 0:9b334a45a8ff 717 receive_idx = -1;
bogdanm 0:9b334a45a8ff 718 return 0;
bogdanm 0:9b334a45a8ff 719 }
bogdanm 0:9b334a45a8ff 720
bogdanm 0:9b334a45a8ff 721 return (rxstat[receive_idx].Info & RINFO_SIZE) - 3;
bogdanm 0:9b334a45a8ff 722 #endif
bogdanm 0:9b334a45a8ff 723 }
bogdanm 0:9b334a45a8ff 724
bogdanm 0:9b334a45a8ff 725 // Read from an recevied ethernet packet.
bogdanm 0:9b334a45a8ff 726 // After receive returnd a number bigger than 0 it is
bogdanm 0:9b334a45a8ff 727 // possible to read bytes from this packet.
bogdanm 0:9b334a45a8ff 728 // Read will write up to size bytes into data.
bogdanm 0:9b334a45a8ff 729 // It is possible to use read multible times.
bogdanm 0:9b334a45a8ff 730 // Each time read will start reading after the last read byte before.
bogdanm 0:9b334a45a8ff 731
bogdanm 0:9b334a45a8ff 732 int ethernet_read(char *data, int dlen) {
bogdanm 0:9b334a45a8ff 733 #if NEW_LOGIC
bogdanm 0:9b334a45a8ff 734 // Check we have a valid buffer to read
bogdanm 0:9b334a45a8ff 735 if(rx_consume_offset < 0) {
bogdanm 0:9b334a45a8ff 736 return 0;
bogdanm 0:9b334a45a8ff 737 }
bogdanm 0:9b334a45a8ff 738
bogdanm 0:9b334a45a8ff 739 // Assume 1 fragment block
bogdanm 0:9b334a45a8ff 740 uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
bogdanm 0:9b334a45a8ff 741 int size = (info & RINFO_SIZE) + 1 - 4; // exclude checksum
bogdanm 0:9b334a45a8ff 742
bogdanm 0:9b334a45a8ff 743 int remaining = size - rx_consume_offset;
bogdanm 0:9b334a45a8ff 744 int requested = dlen;
bogdanm 0:9b334a45a8ff 745 int ncopy = min(remaining, requested);
bogdanm 0:9b334a45a8ff 746
bogdanm 0:9b334a45a8ff 747 void *psrc = (void *)(rxdesc[LPC_EMAC->RxConsumeIndex].Packet + rx_consume_offset);
bogdanm 0:9b334a45a8ff 748 void *pdst = (void *)(data);
bogdanm 0:9b334a45a8ff 749
bogdanm 0:9b334a45a8ff 750 if(data != NULL && ncopy > 0) {
bogdanm 0:9b334a45a8ff 751 memcpy(pdst, psrc, ncopy);
bogdanm 0:9b334a45a8ff 752 }
bogdanm 0:9b334a45a8ff 753
bogdanm 0:9b334a45a8ff 754 rx_consume_offset += ncopy;
bogdanm 0:9b334a45a8ff 755
bogdanm 0:9b334a45a8ff 756 return ncopy;
bogdanm 0:9b334a45a8ff 757 #else
bogdanm 0:9b334a45a8ff 758 int slen;
bogdanm 0:9b334a45a8ff 759 int copy = 0;
bogdanm 0:9b334a45a8ff 760 unsigned int more;
bogdanm 0:9b334a45a8ff 761 unsigned int info;
bogdanm 0:9b334a45a8ff 762 void *pdst, *psrc;
bogdanm 0:9b334a45a8ff 763 int doff = 0;
bogdanm 0:9b334a45a8ff 764
bogdanm 0:9b334a45a8ff 765 if((uint32_t)receive_idx == LPC_EMAC->RxProduceIndex || receive_idx == -1) {
bogdanm 0:9b334a45a8ff 766 return 0;
bogdanm 0:9b334a45a8ff 767 }
bogdanm 0:9b334a45a8ff 768
bogdanm 0:9b334a45a8ff 769 do {
bogdanm 0:9b334a45a8ff 770 info = rxstat[receive_idx].Info;
bogdanm 0:9b334a45a8ff 771 more = !(info & RINFO_LAST_FLAG);
bogdanm 0:9b334a45a8ff 772 slen = (info & RINFO_SIZE) + 1;
bogdanm 0:9b334a45a8ff 773
bogdanm 0:9b334a45a8ff 774 if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
bogdanm 0:9b334a45a8ff 775 /* Invalid frame, ignore it and free buffer. */
bogdanm 0:9b334a45a8ff 776 receive_idx = rinc(receive_idx, NUM_RX_FRAG);
bogdanm 0:9b334a45a8ff 777 } else {
bogdanm 0:9b334a45a8ff 778
bogdanm 0:9b334a45a8ff 779 copy = min(slen - receive_soff, dlen - doff);
bogdanm 0:9b334a45a8ff 780 psrc = (void *)(rxdesc[receive_idx].Packet + receive_soff);
bogdanm 0:9b334a45a8ff 781 pdst = (void *)(data + doff);
bogdanm 0:9b334a45a8ff 782
bogdanm 0:9b334a45a8ff 783 if(data != NULL) {
bogdanm 0:9b334a45a8ff 784 /* check if Buffer available */
bogdanm 0:9b334a45a8ff 785 memcpy(pdst, psrc, copy);
bogdanm 0:9b334a45a8ff 786 }
bogdanm 0:9b334a45a8ff 787
bogdanm 0:9b334a45a8ff 788 receive_soff += copy;
bogdanm 0:9b334a45a8ff 789 doff += copy;
bogdanm 0:9b334a45a8ff 790
bogdanm 0:9b334a45a8ff 791 if((more && (receive_soff == slen))) {
bogdanm 0:9b334a45a8ff 792 receive_idx = rinc(receive_idx, NUM_RX_FRAG);
bogdanm 0:9b334a45a8ff 793 receive_soff = 0;
bogdanm 0:9b334a45a8ff 794 }
bogdanm 0:9b334a45a8ff 795 }
bogdanm 0:9b334a45a8ff 796 } while(more && !(doff == dlen) && !receive_soff);
bogdanm 0:9b334a45a8ff 797
bogdanm 0:9b334a45a8ff 798 return doff;
bogdanm 0:9b334a45a8ff 799 #endif
bogdanm 0:9b334a45a8ff 800 }
bogdanm 0:9b334a45a8ff 801
bogdanm 0:9b334a45a8ff 802 int ethernet_link(void) {
bogdanm 0:9b334a45a8ff 803 if (phy_id == DP83848C_ID) {
bogdanm 0:9b334a45a8ff 804 return (phy_read(PHY_REG_STS) & PHY_STS_LINK);
bogdanm 0:9b334a45a8ff 805 }
bogdanm 0:9b334a45a8ff 806 else { // LAN8720_ID
bogdanm 0:9b334a45a8ff 807 return (phy_read(PHY_REG_BMSR) & PHY_BMSR_LINK);
bogdanm 0:9b334a45a8ff 808 }
bogdanm 0:9b334a45a8ff 809 }
bogdanm 0:9b334a45a8ff 810
bogdanm 0:9b334a45a8ff 811 static int phy_write(unsigned int PhyReg, unsigned short Data) {
bogdanm 0:9b334a45a8ff 812 unsigned int timeOut;
bogdanm 0:9b334a45a8ff 813
bogdanm 0:9b334a45a8ff 814 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
bogdanm 0:9b334a45a8ff 815 LPC_EMAC->MWTD = Data;
bogdanm 0:9b334a45a8ff 816
bogdanm 0:9b334a45a8ff 817 for(timeOut = 0; timeOut < MII_WR_TOUT; timeOut++) { /* Wait until operation completed */
bogdanm 0:9b334a45a8ff 818 if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
bogdanm 0:9b334a45a8ff 819 return 0;
bogdanm 0:9b334a45a8ff 820 }
bogdanm 0:9b334a45a8ff 821 }
bogdanm 0:9b334a45a8ff 822
bogdanm 0:9b334a45a8ff 823 return -1;
bogdanm 0:9b334a45a8ff 824 }
bogdanm 0:9b334a45a8ff 825
bogdanm 0:9b334a45a8ff 826 static int phy_read(unsigned int PhyReg) {
bogdanm 0:9b334a45a8ff 827 unsigned int timeOut;
bogdanm 0:9b334a45a8ff 828
bogdanm 0:9b334a45a8ff 829 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
bogdanm 0:9b334a45a8ff 830 LPC_EMAC->MCMD = MCMD_READ;
bogdanm 0:9b334a45a8ff 831
bogdanm 0:9b334a45a8ff 832 for(timeOut = 0; timeOut < MII_RD_TOUT; timeOut++) { /* Wait until operation completed */
bogdanm 0:9b334a45a8ff 833 if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
bogdanm 0:9b334a45a8ff 834 LPC_EMAC->MCMD = 0;
bogdanm 0:9b334a45a8ff 835 return LPC_EMAC->MRDD; /* Return a 16-bit value. */
bogdanm 0:9b334a45a8ff 836 }
bogdanm 0:9b334a45a8ff 837 }
bogdanm 0:9b334a45a8ff 838
bogdanm 0:9b334a45a8ff 839 return -1;
bogdanm 0:9b334a45a8ff 840 }
bogdanm 0:9b334a45a8ff 841
bogdanm 0:9b334a45a8ff 842
bogdanm 0:9b334a45a8ff 843 static void txdscr_init() {
bogdanm 0:9b334a45a8ff 844 int i;
bogdanm 0:9b334a45a8ff 845
bogdanm 0:9b334a45a8ff 846 for(i = 0; i < NUM_TX_FRAG; i++) {
bogdanm 0:9b334a45a8ff 847 txdesc[i].Packet = (uint32_t)&txbuf[i];
bogdanm 0:9b334a45a8ff 848 txdesc[i].Ctrl = 0;
bogdanm 0:9b334a45a8ff 849 txstat[i].Info = 0;
bogdanm 0:9b334a45a8ff 850 }
bogdanm 0:9b334a45a8ff 851
bogdanm 0:9b334a45a8ff 852 LPC_EMAC->TxDescriptor = (uint32_t)txdesc; /* Set EMAC Transmit Descriptor Registers. */
bogdanm 0:9b334a45a8ff 853 LPC_EMAC->TxStatus = (uint32_t)txstat;
bogdanm 0:9b334a45a8ff 854 LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
bogdanm 0:9b334a45a8ff 855
bogdanm 0:9b334a45a8ff 856 LPC_EMAC->TxProduceIndex = 0; /* Tx Descriptors Point to 0 */
bogdanm 0:9b334a45a8ff 857 }
bogdanm 0:9b334a45a8ff 858
bogdanm 0:9b334a45a8ff 859 static void rxdscr_init() {
bogdanm 0:9b334a45a8ff 860 int i;
bogdanm 0:9b334a45a8ff 861
bogdanm 0:9b334a45a8ff 862 for(i = 0; i < NUM_RX_FRAG; i++) {
bogdanm 0:9b334a45a8ff 863 rxdesc[i].Packet = (uint32_t)&rxbuf[i];
bogdanm 0:9b334a45a8ff 864 rxdesc[i].Ctrl = RCTRL_INT | (ETH_FRAG_SIZE-1);
bogdanm 0:9b334a45a8ff 865 rxstat[i].Info = 0;
bogdanm 0:9b334a45a8ff 866 rxstat[i].HashCRC = 0;
bogdanm 0:9b334a45a8ff 867 }
bogdanm 0:9b334a45a8ff 868
bogdanm 0:9b334a45a8ff 869 LPC_EMAC->RxDescriptor = (uint32_t)rxdesc; /* Set EMAC Receive Descriptor Registers. */
bogdanm 0:9b334a45a8ff 870 LPC_EMAC->RxStatus = (uint32_t)rxstat;
bogdanm 0:9b334a45a8ff 871 LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
bogdanm 0:9b334a45a8ff 872
bogdanm 0:9b334a45a8ff 873 LPC_EMAC->RxConsumeIndex = 0; /* Rx Descriptors Point to 0 */
bogdanm 0:9b334a45a8ff 874 }
bogdanm 0:9b334a45a8ff 875
bogdanm 0:9b334a45a8ff 876 void ethernet_address(char *mac) {
bogdanm 0:9b334a45a8ff 877 mbed_mac_address(mac);
bogdanm 0:9b334a45a8ff 878 }
bogdanm 0:9b334a45a8ff 879
bogdanm 0:9b334a45a8ff 880 void ethernet_set_link(int speed, int duplex) {
bogdanm 0:9b334a45a8ff 881 unsigned short phy_data;
bogdanm 0:9b334a45a8ff 882 int tout;
bogdanm 0:9b334a45a8ff 883
bogdanm 0:9b334a45a8ff 884 if((speed < 0) || (speed > 1)) {
bogdanm 0:9b334a45a8ff 885 phy_data = PHY_AUTO_NEG;
bogdanm 0:9b334a45a8ff 886 } else {
bogdanm 0:9b334a45a8ff 887 phy_data = (((unsigned short) speed << 13) |
bogdanm 0:9b334a45a8ff 888 ((unsigned short) duplex << 8));
bogdanm 0:9b334a45a8ff 889 }
bogdanm 0:9b334a45a8ff 890
bogdanm 0:9b334a45a8ff 891 phy_write(PHY_REG_BMCR, phy_data);
bogdanm 0:9b334a45a8ff 892
bogdanm 0:9b334a45a8ff 893 for(tout = 100; tout; tout--) { __NOP(); } /* A short delay */
bogdanm 0:9b334a45a8ff 894
bogdanm 0:9b334a45a8ff 895 switch(phy_id) {
bogdanm 0:9b334a45a8ff 896 case DP83848C_ID:
bogdanm 0:9b334a45a8ff 897 phy_data = phy_read(PHY_REG_STS);
bogdanm 0:9b334a45a8ff 898
bogdanm 0:9b334a45a8ff 899 if(phy_data & PHY_STS_DUPLEX) {
bogdanm 0:9b334a45a8ff 900 LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
bogdanm 0:9b334a45a8ff 901 LPC_EMAC->Command |= CR_FULL_DUP;
bogdanm 0:9b334a45a8ff 902 LPC_EMAC->IPGT = IPGT_FULL_DUP;
bogdanm 0:9b334a45a8ff 903 } else {
bogdanm 0:9b334a45a8ff 904 LPC_EMAC->MAC2 &= ~MAC2_FULL_DUP;
bogdanm 0:9b334a45a8ff 905 LPC_EMAC->Command &= ~CR_FULL_DUP;
bogdanm 0:9b334a45a8ff 906 LPC_EMAC->IPGT = IPGT_HALF_DUP;
bogdanm 0:9b334a45a8ff 907 }
bogdanm 0:9b334a45a8ff 908
bogdanm 0:9b334a45a8ff 909 if(phy_data & PHY_STS_SPEED) {
bogdanm 0:9b334a45a8ff 910 LPC_EMAC->SUPP &= ~SUPP_SPEED;
bogdanm 0:9b334a45a8ff 911 } else {
bogdanm 0:9b334a45a8ff 912 LPC_EMAC->SUPP |= SUPP_SPEED;
bogdanm 0:9b334a45a8ff 913 }
bogdanm 0:9b334a45a8ff 914 break;
bogdanm 0:9b334a45a8ff 915
bogdanm 0:9b334a45a8ff 916 case LAN8720_ID:
bogdanm 0:9b334a45a8ff 917 phy_data = phy_read(PHY_REG_SCSR);
bogdanm 0:9b334a45a8ff 918
bogdanm 0:9b334a45a8ff 919 if (phy_data & PHY_SCSR_DUPLEX) {
bogdanm 0:9b334a45a8ff 920 LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
bogdanm 0:9b334a45a8ff 921 LPC_EMAC->Command |= CR_FULL_DUP;
bogdanm 0:9b334a45a8ff 922 LPC_EMAC->IPGT = IPGT_FULL_DUP;
bogdanm 0:9b334a45a8ff 923 } else {
bogdanm 0:9b334a45a8ff 924 LPC_EMAC->Command &= ~CR_FULL_DUP;
bogdanm 0:9b334a45a8ff 925 LPC_EMAC->IPGT = IPGT_HALF_DUP;
bogdanm 0:9b334a45a8ff 926 }
bogdanm 0:9b334a45a8ff 927
bogdanm 0:9b334a45a8ff 928 if(phy_data & PHY_SCSR_100MBIT) {
bogdanm 0:9b334a45a8ff 929 LPC_EMAC->SUPP |= SUPP_SPEED;
bogdanm 0:9b334a45a8ff 930 } else {
bogdanm 0:9b334a45a8ff 931 LPC_EMAC->SUPP &= ~SUPP_SPEED;
bogdanm 0:9b334a45a8ff 932 }
bogdanm 0:9b334a45a8ff 933 break;
bogdanm 0:9b334a45a8ff 934 }
bogdanm 0:9b334a45a8ff 935 }