Tomo Yamanaka / mbed-dev

mbed library sources. Supersedes mbed-src. GR-PEACH runs on RAM.

Fork of mbed-dev by mbed official

targets/hal/TARGET_NXP/TARGET_LPC23XX/PeripheralNames.h@103:493a29d2d4d7, 2016-03-30 (annotated)

Committer:
1050186
Date:
Wed Mar 30 11:41:25 2016 +0000
Revision:
103:493a29d2d4d7
Parent:
0:9b334a45a8ff 
GR-PEACH runs on RAM.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* mbed Microcontroller Library
bogdanm 0:9b334a45a8ff 2 * Copyright (c) 2006-2013 ARM Limited
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Licensed under the Apache License, Version 2.0 (the "License");
bogdanm 0:9b334a45a8ff 5 * you may not use this file except in compliance with the License.
bogdanm 0:9b334a45a8ff 6 * You may obtain a copy of the License at
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * http://www.apache.org/licenses/LICENSE-2.0
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Unless required by applicable law or agreed to in writing, software
bogdanm 0:9b334a45a8ff 11 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 0:9b334a45a8ff 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 0:9b334a45a8ff 13 * See the License for the specific language governing permissions and
bogdanm 0:9b334a45a8ff 14 * limitations under the License.
bogdanm 0:9b334a45a8ff 15 */
bogdanm 0:9b334a45a8ff 16 #ifndef MBED_PERIPHERALNAMES_H
bogdanm 0:9b334a45a8ff 17 #define MBED_PERIPHERALNAMES_H
bogdanm 0:9b334a45a8ff 18
bogdanm 0:9b334a45a8ff 19 #include "cmsis.h"
bogdanm 0:9b334a45a8ff 20
bogdanm 0:9b334a45a8ff 21 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 22 extern "C" {
bogdanm 0:9b334a45a8ff 23 #endif
bogdanm 0:9b334a45a8ff 24
bogdanm 0:9b334a45a8ff 25 typedef enum {
bogdanm 0:9b334a45a8ff 26 UART_0 = (int)LPC_UART0_BASE,
bogdanm 0:9b334a45a8ff 27 UART_1 = (int)LPC_UART1_BASE,
bogdanm 0:9b334a45a8ff 28 UART_2 = (int)LPC_UART2_BASE,
bogdanm 0:9b334a45a8ff 29 UART_3 = (int)LPC_UART3_BASE
bogdanm 0:9b334a45a8ff 30 } UARTName;
bogdanm 0:9b334a45a8ff 31
bogdanm 0:9b334a45a8ff 32 typedef enum {
bogdanm 0:9b334a45a8ff 33 ADC0_0 = 0,
bogdanm 0:9b334a45a8ff 34 ADC0_1,
bogdanm 0:9b334a45a8ff 35 ADC0_2,
bogdanm 0:9b334a45a8ff 36 ADC0_3,
bogdanm 0:9b334a45a8ff 37 ADC0_4,
bogdanm 0:9b334a45a8ff 38 ADC0_5,
bogdanm 0:9b334a45a8ff 39 ADC0_6,
bogdanm 0:9b334a45a8ff 40 ADC0_7
bogdanm 0:9b334a45a8ff 41 } ADCName;
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 typedef enum {
bogdanm 0:9b334a45a8ff 44 DAC_0 = 0
bogdanm 0:9b334a45a8ff 45 } DACName;
bogdanm 0:9b334a45a8ff 46
bogdanm 0:9b334a45a8ff 47 typedef enum {
bogdanm 0:9b334a45a8ff 48 SPI_0 = (int)LPC_SSP0_BASE,
bogdanm 0:9b334a45a8ff 49 SPI_1 = (int)LPC_SSP1_BASE
bogdanm 0:9b334a45a8ff 50 } SPIName;
bogdanm 0:9b334a45a8ff 51
bogdanm 0:9b334a45a8ff 52 typedef enum {
bogdanm 0:9b334a45a8ff 53 I2C_0 = (int)LPC_I2C0_BASE,
bogdanm 0:9b334a45a8ff 54 I2C_1 = (int)LPC_I2C1_BASE,
bogdanm 0:9b334a45a8ff 55 I2C_2 = (int)LPC_I2C2_BASE
bogdanm 0:9b334a45a8ff 56 } I2CName;
bogdanm 0:9b334a45a8ff 57
bogdanm 0:9b334a45a8ff 58 typedef enum {
bogdanm 0:9b334a45a8ff 59 PWM_1 = 1,
bogdanm 0:9b334a45a8ff 60 PWM_2,
bogdanm 0:9b334a45a8ff 61 PWM_3,
bogdanm 0:9b334a45a8ff 62 PWM_4,
bogdanm 0:9b334a45a8ff 63 PWM_5,
bogdanm 0:9b334a45a8ff 64 PWM_6
bogdanm 0:9b334a45a8ff 65 } PWMName;
bogdanm 0:9b334a45a8ff 66
bogdanm 0:9b334a45a8ff 67 typedef enum {
bogdanm 0:9b334a45a8ff 68 CAN_1 = (int)LPC_CAN1_BASE,
bogdanm 0:9b334a45a8ff 69 CAN_2 = (int)LPC_CAN2_BASE
bogdanm 0:9b334a45a8ff 70 } CANName;
bogdanm 0:9b334a45a8ff 71
bogdanm 0:9b334a45a8ff 72 #define STDIO_UART_TX USBTX
bogdanm 0:9b334a45a8ff 73 #define STDIO_UART_RX USBRX
bogdanm 0:9b334a45a8ff 74 #define STDIO_UART UART_0
bogdanm 0:9b334a45a8ff 75
bogdanm 0:9b334a45a8ff 76 // Default peripherals
bogdanm 0:9b334a45a8ff 77 #define MBED_SPI0 p5, p6, p7, p8
bogdanm 0:9b334a45a8ff 78 #define MBED_SPI1 p11, p12, p13, p14
bogdanm 0:9b334a45a8ff 79
bogdanm 0:9b334a45a8ff 80 #define MBED_UART0 p9, p10
bogdanm 0:9b334a45a8ff 81 #define MBED_UART1 p13, p14
bogdanm 0:9b334a45a8ff 82 #define MBED_UART2 p28, p27
bogdanm 0:9b334a45a8ff 83 #define MBED_UARTUSB USBTX, USBRX
bogdanm 0:9b334a45a8ff 84
bogdanm 0:9b334a45a8ff 85 #define MBED_I2C0 p28, p27
bogdanm 0:9b334a45a8ff 86 #define MBED_I2C1 p9, p10
bogdanm 0:9b334a45a8ff 87
bogdanm 0:9b334a45a8ff 88 #define MBED_CAN0 p30, p29
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90 #define MBED_ANALOGOUT0 p18
bogdanm 0:9b334a45a8ff 91
bogdanm 0:9b334a45a8ff 92 #define MBED_ANALOGIN0 p15
bogdanm 0:9b334a45a8ff 93 #define MBED_ANALOGIN1 p16
bogdanm 0:9b334a45a8ff 94 #define MBED_ANALOGIN2 p17
bogdanm 0:9b334a45a8ff 95 #define MBED_ANALOGIN3 p18
bogdanm 0:9b334a45a8ff 96 #define MBED_ANALOGIN4 p19
bogdanm 0:9b334a45a8ff 97 #define MBED_ANALOGIN5 p20
bogdanm 0:9b334a45a8ff 98
bogdanm 0:9b334a45a8ff 99 #define MBED_PWMOUT0 p26
bogdanm 0:9b334a45a8ff 100 #define MBED_PWMOUT1 p25
bogdanm 0:9b334a45a8ff 101 #define MBED_PWMOUT2 p24
bogdanm 0:9b334a45a8ff 102 #define MBED_PWMOUT3 p23
bogdanm 0:9b334a45a8ff 103 #define MBED_PWMOUT4 p22
bogdanm 0:9b334a45a8ff 104 #define MBED_PWMOUT5 p21
bogdanm 0:9b334a45a8ff 105
bogdanm 0:9b334a45a8ff 106 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 107 }
bogdanm 0:9b334a45a8ff 108 #endif
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110 #endif