xLAB - acutators / led-mrf-osc_full_Latest_2

ese519

Dependencies:   addressable_leds

Dependents:   led-mrf-osc_full

MRF24J40/MRF24J40.cpp@1:d4c1d8dc8ced, 2015-03-21 (annotated)

Committer:
Jing_Qiu
Date:
Sat Mar 21 02:42:59 2015 +0000
Revision:
1:d4c1d8dc8ced
Parent:
0:284274252007 
revised

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Jing_Qiu 0:284274252007 1 /* mbed MRF24J40 (IEEE 802.15.4 tranceiver) Library
Jing_Qiu 0:284274252007 2 * Copyright (c) 2011 Jeroen Hilgers
Jing_Qiu 0:284274252007 3 *
Jing_Qiu 0:284274252007 4 * Permission is hereby granted, free of charge, to any person obtaining a copy
Jing_Qiu 0:284274252007 5 * of this software and associated documentation files (the "Software"), to deal
Jing_Qiu 0:284274252007 6 * in the Software without restriction, including without limitation the rights
Jing_Qiu 0:284274252007 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
Jing_Qiu 0:284274252007 8 * copies of the Software, and to permit persons to whom the Software is
Jing_Qiu 0:284274252007 9 * furnished to do so, subject to the following conditions:
Jing_Qiu 0:284274252007 10 *
Jing_Qiu 0:284274252007 11 * The above copyright notice and this permission notice shall be included in
Jing_Qiu 0:284274252007 12 * all copies or substantial portions of the Software.
Jing_Qiu 0:284274252007 13 *
Jing_Qiu 0:284274252007 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
Jing_Qiu 0:284274252007 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
Jing_Qiu 0:284274252007 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
Jing_Qiu 0:284274252007 17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
Jing_Qiu 0:284274252007 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
Jing_Qiu 0:284274252007 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
Jing_Qiu 0:284274252007 20 * THE SOFTWARE.
Jing_Qiu 0:284274252007 21 */
Jing_Qiu 0:284274252007 22
Jing_Qiu 0:284274252007 23 #include "MRF24J40.h"
Jing_Qiu 0:284274252007 24
Jing_Qiu 0:284274252007 25 // MRF20J40 Short address control register mapping.
Jing_Qiu 0:284274252007 26 #define RXMCR 0x00
Jing_Qiu 0:284274252007 27 #define PANIDL 0x01
Jing_Qiu 0:284274252007 28 #define PANIDH 0x02
Jing_Qiu 0:284274252007 29 #define SADRL 0x03
Jing_Qiu 0:284274252007 30 #define SADRH 0x04
Jing_Qiu 0:284274252007 31 #define EADR0 0x05
Jing_Qiu 0:284274252007 32 #define EADR1 0x06
Jing_Qiu 0:284274252007 33 #define EADR2 0x07
Jing_Qiu 0:284274252007 34 #define EADR3 0x08
Jing_Qiu 0:284274252007 35 #define EADR4 0x09
Jing_Qiu 0:284274252007 36 #define EADR5 0x0a
Jing_Qiu 0:284274252007 37 #define EADR6 0x0b
Jing_Qiu 0:284274252007 38 #define EADR7 0x0c
Jing_Qiu 0:284274252007 39 #define RXFLUSH 0x0d
Jing_Qiu 0:284274252007 40
Jing_Qiu 0:284274252007 41 #define TXNMTRIG 0x1b
Jing_Qiu 0:284274252007 42 #define TXSR 0x24
Jing_Qiu 0:284274252007 43
Jing_Qiu 0:284274252007 44 #define ISRSTS 0x31
Jing_Qiu 0:284274252007 45 #define INTMSK 0x32
Jing_Qiu 0:284274252007 46 #define GPIO 0x33
Jing_Qiu 0:284274252007 47 #define TRISGPIO 0x34
Jing_Qiu 0:284274252007 48
Jing_Qiu 0:284274252007 49 #define RFCTL 0x36
Jing_Qiu 0:284274252007 50
Jing_Qiu 0:284274252007 51 #define BBREG2 0x3A
Jing_Qiu 0:284274252007 52
Jing_Qiu 0:284274252007 53 #define BBREG6 0x3E
Jing_Qiu 0:284274252007 54 #define RSSITHCCA 0x3F
Jing_Qiu 0:284274252007 55
Jing_Qiu 0:284274252007 56 // MRF20J40 Long address control register mapping.
Jing_Qiu 0:284274252007 57 #define RFCTRL0 0x200
Jing_Qiu 0:284274252007 58
Jing_Qiu 0:284274252007 59 #define RFCTRL2 0x202
Jing_Qiu 0:284274252007 60 #define RFCTRL3 0x203
Jing_Qiu 0:284274252007 61
Jing_Qiu 0:284274252007 62 #define RFCTRL6 0x206
Jing_Qiu 0:284274252007 63 #define RFCTRL7 0x207
Jing_Qiu 0:284274252007 64 #define RFCTRL8 0x208
Jing_Qiu 0:284274252007 65
Jing_Qiu 0:284274252007 66 #define CLKINTCR 0x211
Jing_Qiu 0:284274252007 67 #define CLCCTRL 0x220
Jing_Qiu 0:284274252007 68
Jing_Qiu 0:284274252007 69 MRF24J40::MRF24J40(PinName mosi, PinName miso, PinName sck, PinName cs, PinName reset) ://, PinName irq, PinName wake) :
Jing_Qiu 0:284274252007 70 mSpi(mosi, miso, sck), // mosi, miso, sclk
Jing_Qiu 0:284274252007 71 mCs(cs),
Jing_Qiu 0:284274252007 72 mReset(reset)
Jing_Qiu 0:284274252007 73 // mIrq(irq),
Jing_Qiu 0:284274252007 74 // mWake(wake)
Jing_Qiu 0:284274252007 75 {
Jing_Qiu 0:284274252007 76 mSpi.format(8, 0); // 8 bits, cpol=0; cpha=0
Jing_Qiu 0:284274252007 77 mSpi.frequency(500000);
Jing_Qiu 0:284274252007 78 Reset();
Jing_Qiu 0:284274252007 79 }
Jing_Qiu 0:284274252007 80
Jing_Qiu 0:284274252007 81 /*
Jing_Qiu 0:284274252007 82 void MRF24J40::DebugDump(Serial &ser)
Jing_Qiu 0:284274252007 83 {
Jing_Qiu 0:284274252007 84 ser.printf("MRF24J40 registers:\r");
Jing_Qiu 0:284274252007 85 ser.printf("RXMCR=0x%X\r", MrfReadShort(RXMCR));
Jing_Qiu 0:284274252007 86 ser.printf("RXFLUSH=0x%X\r", MrfReadShort(RXFLUSH));
Jing_Qiu 0:284274252007 87 ser.printf("TXNMTRIG=0x%X\r", MrfReadShort(TXNMTRIG));
Jing_Qiu 0:284274252007 88 ser.printf("TXSR=0x%X\r", MrfReadShort(TXSR));
Jing_Qiu 0:284274252007 89 ser.printf("ISRSTS=0x%X\r", MrfReadShort(ISRSTS));
Jing_Qiu 0:284274252007 90 ser.printf("INTMSK=0x%X\r", MrfReadShort(INTMSK));
Jing_Qiu 0:284274252007 91 ser.printf("GPIO=0x%X\r", MrfReadShort(GPIO));
Jing_Qiu 0:284274252007 92 ser.printf("TRISGPIO=0x%X\r", MrfReadShort(TRISGPIO));
Jing_Qiu 0:284274252007 93 ser.printf("RFCTL=0x%X\r", MrfReadShort(RFCTL));
Jing_Qiu 0:284274252007 94 ser.printf("BBREG2=0x%X\r", MrfReadShort(BBREG2));
Jing_Qiu 0:284274252007 95 ser.printf("BBREG6=0x%X\r", MrfReadShort(BBREG6));
Jing_Qiu 0:284274252007 96 ser.printf("RSSITHCCA=0x%X\r", MrfReadShort(RSSITHCCA));
Jing_Qiu 0:284274252007 97
Jing_Qiu 0:284274252007 98
Jing_Qiu 0:284274252007 99 ser.printf("RFCTRL0=0x%X\r", MrfReadLong(RFCTRL0));
Jing_Qiu 0:284274252007 100 ser.printf("RFCTRL2=0x%X\r", MrfReadLong(RFCTRL2));
Jing_Qiu 0:284274252007 101 ser.printf("RFCTRL3=0x%X\r", MrfReadLong(RFCTRL3));
Jing_Qiu 0:284274252007 102 ser.printf("RFCTRL6=0x%X\r", MrfReadLong(RFCTRL6));
Jing_Qiu 0:284274252007 103 ser.printf("RFCTRL7=0x%X\r", MrfReadLong(RFCTRL7));
Jing_Qiu 0:284274252007 104 ser.printf("RFCTRL8=0x%X\r", MrfReadLong(RFCTRL8));
Jing_Qiu 0:284274252007 105 ser.printf("CLKINTCR=0x%X\r", MrfReadLong(CLKINTCR));
Jing_Qiu 0:284274252007 106 ser.printf("CLCCTRL=0x%X\r", MrfReadLong(CLCCTRL));
Jing_Qiu 0:284274252007 107 ser.printf("\r");
Jing_Qiu 0:284274252007 108 }
Jing_Qiu 0:284274252007 109 */
Jing_Qiu 0:284274252007 110
Jing_Qiu 0:284274252007 111 void MRF24J40::Reset(void)
Jing_Qiu 0:284274252007 112 {
Jing_Qiu 0:284274252007 113 mCs = 1;
Jing_Qiu 0:284274252007 114 // Pulse hardware reset.
Jing_Qiu 0:284274252007 115 mReset = 0;
Jing_Qiu 0:284274252007 116 wait_us(100);
Jing_Qiu 0:284274252007 117 mReset = 1;
Jing_Qiu 0:284274252007 118 wait_us(100);
Jing_Qiu 0:284274252007 119
Jing_Qiu 0:284274252007 120 // Reset RF module.
Jing_Qiu 0:284274252007 121 WriteShort(RFCTL, 0x04);
Jing_Qiu 0:284274252007 122 WriteShort(RFCTL, 0x00);
Jing_Qiu 0:284274252007 123
Jing_Qiu 0:284274252007 124 WriteShort(RFCTL, 0x00);
Jing_Qiu 0:284274252007 125
Jing_Qiu 0:284274252007 126 WriteShort(PANIDL, 0xAA);
Jing_Qiu 0:284274252007 127 WriteShort(PANIDH, 0xAA);
Jing_Qiu 0:284274252007 128 WriteShort(SADRL, 0xAA);
Jing_Qiu 0:284274252007 129 WriteShort(SADRH, 0xAA);
Jing_Qiu 0:284274252007 130
Jing_Qiu 0:284274252007 131 // Flush RX fifo.
Jing_Qiu 0:284274252007 132 WriteShort(RXFLUSH, 0x01);
Jing_Qiu 0:284274252007 133
Jing_Qiu 0:284274252007 134 // Write MAC addresses here. We don't care.
Jing_Qiu 0:284274252007 135
Jing_Qiu 0:284274252007 136 WriteLong(RFCTRL2, 0x80); // Enable RF PLL.
Jing_Qiu 0:284274252007 137
Jing_Qiu 0:284274252007 138 WriteLong(RFCTRL3, 0x00); // Full power.
Jing_Qiu 0:284274252007 139 WriteLong(RFCTRL6, 0x80); // Enable TX filter (recommended)
Jing_Qiu 0:284274252007 140 WriteLong(RFCTRL8, 0x10); // Enhanced VCO (recommended)
Jing_Qiu 0:284274252007 141
Jing_Qiu 0:284274252007 142 WriteShort(BBREG2,0x78); // Clear Channel Assesment use carrier sense.
Jing_Qiu 0:284274252007 143 WriteShort(BBREG6,0x40); // Calculate RSSI for Rx packet.
Jing_Qiu 0:284274252007 144 WriteShort(RSSITHCCA,0x00);// RSSI threshold for CCA.
Jing_Qiu 0:284274252007 145
Jing_Qiu 0:284274252007 146 WriteLong(RFCTRL0, 0x00); // Channel 11.
Jing_Qiu 0:284274252007 147
Jing_Qiu 0:284274252007 148 WriteShort(RXMCR, 0x01); // Don't check address upon reception.
Jing_Qiu 0:284274252007 149 // MrfWriteShort(RXMCR, 0x00); // Check address upon reception.
Jing_Qiu 0:284274252007 150
Jing_Qiu 0:284274252007 151 // Reset RF module with new settings.
Jing_Qiu 0:284274252007 152 WriteShort(RFCTL, 0x04);
Jing_Qiu 0:284274252007 153 WriteShort(RFCTL, 0x00);
Jing_Qiu 0:284274252007 154 }
Jing_Qiu 0:284274252007 155
Jing_Qiu 0:284274252007 156 void MRF24J40::Send(uint8_t *data, uint8_t length)
Jing_Qiu 0:284274252007 157 {
Jing_Qiu 0:284274252007 158 uint8_t i;
Jing_Qiu 0:284274252007 159
Jing_Qiu 0:284274252007 160 WriteLong(0x000, 0); // No addresses in header.
Jing_Qiu 0:284274252007 161 WriteLong(0x001, length); // 11 bytes
Jing_Qiu 0:284274252007 162 for(i=0; i<length; i++)
Jing_Qiu 0:284274252007 163 WriteLong(0x002+i, data[i]);
Jing_Qiu 0:284274252007 164
Jing_Qiu 0:284274252007 165 WriteShort(TXNMTRIG, 0x01);
Jing_Qiu 0:284274252007 166 }
Jing_Qiu 0:284274252007 167
Jing_Qiu 0:284274252007 168 uint8_t MRF24J40::Receive(uint8_t *data, uint8_t maxLength)
Jing_Qiu 0:284274252007 169 {
Jing_Qiu 0:284274252007 170 uint8_t i, length;
Jing_Qiu 0:284274252007 171 uint8_t lqi, rssi;
Jing_Qiu 0:284274252007 172
Jing_Qiu 0:284274252007 173 if(ReadShort(ISRSTS)& 0x08)
Jing_Qiu 0:284274252007 174 {
Jing_Qiu 0:284274252007 175 length = ReadLong(0x300);
Jing_Qiu 0:284274252007 176 lqi = ReadLong(0x301 + length);
Jing_Qiu 0:284274252007 177 rssi = ReadLong(0x302 + length);
Jing_Qiu 0:284274252007 178 for(i=0; i<length; i++)
Jing_Qiu 0:284274252007 179 if(i<maxLength)
Jing_Qiu 0:284274252007 180 *data++ = ReadLong(0x301 + (uint16_t)i);
Jing_Qiu 0:284274252007 181 else
Jing_Qiu 0:284274252007 182 ReadLong(0x301 + (uint16_t)i);
Jing_Qiu 0:284274252007 183 if(length < maxLength)
Jing_Qiu 0:284274252007 184 return length;
Jing_Qiu 0:284274252007 185 }
Jing_Qiu 0:284274252007 186 return 0;
Jing_Qiu 0:284274252007 187 }
Jing_Qiu 0:284274252007 188
Jing_Qiu 0:284274252007 189 uint8_t MRF24J40::ReadShort (uint8_t address)
Jing_Qiu 0:284274252007 190 {
Jing_Qiu 0:284274252007 191 uint8_t value;
Jing_Qiu 0:284274252007 192 mCs = 0;
Jing_Qiu 0:284274252007 193 wait_us(1);
Jing_Qiu 0:284274252007 194 mSpi.write((address<<1) & 0x7E);
Jing_Qiu 0:284274252007 195 wait_us(1);
Jing_Qiu 0:284274252007 196 value = mSpi.write(0xFF);
Jing_Qiu 0:284274252007 197 wait_us(1);
Jing_Qiu 0:284274252007 198 mCs = 1;
Jing_Qiu 0:284274252007 199 wait_us(1);
Jing_Qiu 0:284274252007 200 return value;
Jing_Qiu 0:284274252007 201 }
Jing_Qiu 0:284274252007 202
Jing_Qiu 0:284274252007 203 void MRF24J40::WriteShort (uint8_t address, uint8_t data)
Jing_Qiu 0:284274252007 204 {
Jing_Qiu 0:284274252007 205 mCs = 0;
Jing_Qiu 0:284274252007 206 wait_us(1);
Jing_Qiu 0:284274252007 207 mSpi.write(((address<<1) & 0x7E) | 0x01);
Jing_Qiu 0:284274252007 208 wait_us(1);
Jing_Qiu 0:284274252007 209 mSpi.write(data);
Jing_Qiu 0:284274252007 210 wait_us(1);
Jing_Qiu 0:284274252007 211 mCs = 1;
Jing_Qiu 0:284274252007 212 wait_us(1);
Jing_Qiu 0:284274252007 213 }
Jing_Qiu 0:284274252007 214
Jing_Qiu 0:284274252007 215 uint8_t MRF24J40::ReadLong (uint16_t address)
Jing_Qiu 0:284274252007 216 {
Jing_Qiu 0:284274252007 217 uint8_t value;
Jing_Qiu 0:284274252007 218 mCs = 0;
Jing_Qiu 0:284274252007 219 wait_us(1);
Jing_Qiu 0:284274252007 220 mSpi.write((address>>3) | 0x80);
Jing_Qiu 0:284274252007 221 wait_us(1);
Jing_Qiu 0:284274252007 222 mSpi.write((address<<5) & 0xE0);
Jing_Qiu 0:284274252007 223 wait_us(1);
Jing_Qiu 0:284274252007 224 value = mSpi.write(0xFF);
Jing_Qiu 0:284274252007 225 wait_us(1);
Jing_Qiu 0:284274252007 226 mCs = 1;
Jing_Qiu 0:284274252007 227 wait_us(1);
Jing_Qiu 0:284274252007 228 return value;
Jing_Qiu 0:284274252007 229 }
Jing_Qiu 0:284274252007 230
Jing_Qiu 0:284274252007 231 void MRF24J40::WriteLong (uint16_t address, uint8_t data)
Jing_Qiu 0:284274252007 232 {
Jing_Qiu 0:284274252007 233 mCs = 0;
Jing_Qiu 0:284274252007 234 wait_us(1);
Jing_Qiu 0:284274252007 235 mSpi.write((address>>3) | 0x80);
Jing_Qiu 0:284274252007 236 wait_us(1);
Jing_Qiu 0:284274252007 237 mSpi.write(((address<<5) & 0xE0) | 0x10);
Jing_Qiu 0:284274252007 238 wait_us(1);
Jing_Qiu 0:284274252007 239 mSpi.write(data);
Jing_Qiu 0:284274252007 240 wait_us(1);
Jing_Qiu 0:284274252007 241 mCs = 1;
Jing_Qiu 0:284274252007 242 wait_us(1);
Jing_Qiu 0:284274252007 243 }