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ITM_Type Struct Reference
[Instrumentation Trace Macrocell (ITM)]
Structure type to access the Instrumentation Trace Macrocell Register (ITM). More...
#include <core_cm4.h>
Data Fields | |
| union { | |
| __O uint8_t u8 | |
| __O uint16_t u16 | |
| __O uint32_t u32 | |
| } | PORT [32] |
| __IO uint32_t | TER |
| __IO uint32_t | TPR |
| __IO uint32_t | TCR |
| __O uint32_t | IWR |
| __I uint32_t | IRR |
| __IO uint32_t | IMCR |
| __O uint32_t | LAR |
| __I uint32_t | LSR |
| __I uint32_t | PID4 |
| __I uint32_t | PID5 |
| __I uint32_t | PID6 |
| __I uint32_t | PID7 |
| __I uint32_t | PID0 |
| __I uint32_t | PID1 |
| __I uint32_t | PID2 |
| __I uint32_t | PID3 |
| __I uint32_t | CID0 |
| __I uint32_t | CID1 |
| __I uint32_t | CID2 |
| __I uint32_t | CID3 |
Detailed Description
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition at line 673 of file core_cm4.h.
Field Documentation
| __I uint32_t CID0 |
Offset: 0xFF0 (R/ ) ITM Component Identification Register #0
Definition at line 703 of file core_cm4.h.
| __I uint32_t CID1 |
Offset: 0xFF4 (R/ ) ITM Component Identification Register #1
Definition at line 704 of file core_cm4.h.
| __I uint32_t CID2 |
Offset: 0xFF8 (R/ ) ITM Component Identification Register #2
Definition at line 705 of file core_cm4.h.
| __I uint32_t CID3 |
Offset: 0xFFC (R/ ) ITM Component Identification Register #3
Definition at line 706 of file core_cm4.h.
| __IO uint32_t IMCR |
Offset: 0xF00 (R/W) ITM Integration Mode Control Register
Definition at line 690 of file core_cm4.h.
| __I uint32_t IRR |
Offset: 0xEFC (R/ ) ITM Integration Read Register
Definition at line 689 of file core_cm4.h.
| __O uint32_t IWR |
Offset: 0xEF8 ( /W) ITM Integration Write Register
Definition at line 688 of file core_cm4.h.
| __O uint32_t LAR |
Offset: 0xFB0 ( /W) ITM Lock Access Register
Definition at line 692 of file core_cm4.h.
| __I uint32_t LSR |
Offset: 0xFB4 (R/ ) ITM Lock Status Register
Definition at line 693 of file core_cm4.h.
| __I uint32_t PID0 |
Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0
Definition at line 699 of file core_cm4.h.
| __I uint32_t PID1 |
Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1
Definition at line 700 of file core_cm4.h.
| __I uint32_t PID2 |
Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2
Definition at line 701 of file core_cm4.h.
| __I uint32_t PID3 |
Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3
Definition at line 702 of file core_cm4.h.
| __I uint32_t PID4 |
Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4
Definition at line 695 of file core_cm4.h.
| __I uint32_t PID5 |
Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5
Definition at line 696 of file core_cm4.h.
| __I uint32_t PID6 |
Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6
Definition at line 697 of file core_cm4.h.
| __I uint32_t PID7 |
Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7
Definition at line 698 of file core_cm4.h.
| __O { ... } PORT[32] |
Offset: 0x000 ( /W) ITM Stimulus Port Registers
| __IO uint32_t TCR |
Offset: 0xE80 (R/W) ITM Trace Control Register
Definition at line 686 of file core_cm4.h.
| __IO uint32_t TER |
Offset: 0xE00 (R/W) ITM Trace Enable Register
Definition at line 682 of file core_cm4.h.
| __IO uint32_t TPR |
Offset: 0xE40 (R/W) ITM Trace Privilege Register
Definition at line 684 of file core_cm4.h.
| __O uint16_t u16 |
Offset: 0x000 ( /W) ITM Stimulus Port 16-bit
Definition at line 678 of file core_cm4.h.
| __O uint32_t u32 |
Offset: 0x000 ( /W) ITM Stimulus Port 32-bit
Definition at line 679 of file core_cm4.h.
| __O uint8_t u8 |
Offset: 0x000 ( /W) ITM Stimulus Port 8-bit
Definition at line 677 of file core_cm4.h.
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