test / EALib

A library with drivers for different peripherals on the LPC4088 QuickStart Board or related add-on boards.

Dependencies:   FATFileSystem

Dependents:   bare

Fork of EALib by EmbeddedArtists AB

sdram.cpp@6:405c6e5a4eaf, 2013-10-31 (annotated)

Committer:
embeddedartists
Date:
Thu Oct 31 13:23:11 2013 +0000
Revision:
6:405c6e5a4eaf
Parent:
0:0fdadbc3d852
Child:
11:2d4d65173195
Updated SPI clock frequency for TSC2046

Who changed what in which revision?

UserRevisionLine numberNew contents of line
embeddedartists 0:0fdadbc3d852 1 /*****************************************************************************
embeddedartists 0:0fdadbc3d852 2 *
embeddedartists 0:0fdadbc3d852 3 * Copyright(C) 2011, Embedded Artists AB
embeddedartists 0:0fdadbc3d852 4 * All rights reserved.
embeddedartists 0:0fdadbc3d852 5 *
embeddedartists 0:0fdadbc3d852 6 ******************************************************************************
embeddedartists 0:0fdadbc3d852 7 * Software that is described herein is for illustrative purposes only
embeddedartists 0:0fdadbc3d852 8 * which provides customers with programming information regarding the
embeddedartists 0:0fdadbc3d852 9 * products. This software is supplied "AS IS" without any warranties.
embeddedartists 0:0fdadbc3d852 10 * Embedded Artists AB assumes no responsibility or liability for the
embeddedartists 0:0fdadbc3d852 11 * use of the software, conveys no license or title under any patent,
embeddedartists 0:0fdadbc3d852 12 * copyright, or mask work right to the product. Embedded Artists AB
embeddedartists 0:0fdadbc3d852 13 * reserves the right to make changes in the software without
embeddedartists 0:0fdadbc3d852 14 * notification. Embedded Artists AB also make no representation or
embeddedartists 0:0fdadbc3d852 15 * warranty that such application will be suitable for the specified
embeddedartists 0:0fdadbc3d852 16 * use without further testing or modification.
embeddedartists 0:0fdadbc3d852 17 *****************************************************************************/
embeddedartists 0:0fdadbc3d852 18
embeddedartists 0:0fdadbc3d852 19
embeddedartists 0:0fdadbc3d852 20
embeddedartists 0:0fdadbc3d852 21 /******************************************************************************
embeddedartists 0:0fdadbc3d852 22 * Includes
embeddedartists 0:0fdadbc3d852 23 *****************************************************************************/
embeddedartists 0:0fdadbc3d852 24
embeddedartists 0:0fdadbc3d852 25 #include "mbed.h"
embeddedartists 0:0fdadbc3d852 26 #include "sdram.h"
embeddedartists 0:0fdadbc3d852 27
embeddedartists 0:0fdadbc3d852 28
embeddedartists 0:0fdadbc3d852 29 /******************************************************************************
embeddedartists 0:0fdadbc3d852 30 * Defines and typedefs
embeddedartists 0:0fdadbc3d852 31 *****************************************************************************/
embeddedartists 0:0fdadbc3d852 32
embeddedartists 0:0fdadbc3d852 33
embeddedartists 0:0fdadbc3d852 34 /******************************************************************************
embeddedartists 0:0fdadbc3d852 35 * External global variables
embeddedartists 0:0fdadbc3d852 36 *****************************************************************************/
embeddedartists 0:0fdadbc3d852 37
embeddedartists 0:0fdadbc3d852 38 /******************************************************************************
embeddedartists 0:0fdadbc3d852 39 * Local variables
embeddedartists 0:0fdadbc3d852 40 *****************************************************************************/
embeddedartists 0:0fdadbc3d852 41
embeddedartists 0:0fdadbc3d852 42 static volatile uint32_t ringosccount[2] = {0,0};
embeddedartists 0:0fdadbc3d852 43
embeddedartists 0:0fdadbc3d852 44 static bool okToUseSdramForHeap = true;
embeddedartists 0:0fdadbc3d852 45 static bool initialized = false;
embeddedartists 0:0fdadbc3d852 46
embeddedartists 0:0fdadbc3d852 47 /******************************************************************************
embeddedartists 0:0fdadbc3d852 48 * Overridden Global Functions
embeddedartists 0:0fdadbc3d852 49 *****************************************************************************/
embeddedartists 0:0fdadbc3d852 50
embeddedartists 0:0fdadbc3d852 51 #if defined(TOOLCHAIN_ARM) /* KEIL uVision and mbed online compiler */
embeddedartists 0:0fdadbc3d852 52 //http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0349c/Cihehbce.html
embeddedartists 0:0fdadbc3d852 53
embeddedartists 0:0fdadbc3d852 54 extern "C" unsigned __rt_heap_extend(unsigned size, void **block) {
embeddedartists 0:0fdadbc3d852 55 static uint32_t lastReturnedBlock = 0;
embeddedartists 0:0fdadbc3d852 56
embeddedartists 0:0fdadbc3d852 57 if (okToUseSdramForHeap && !initialized) {
embeddedartists 0:0fdadbc3d852 58 sdram_init();
embeddedartists 0:0fdadbc3d852 59 }
embeddedartists 0:0fdadbc3d852 60
embeddedartists 0:0fdadbc3d852 61 // Make sure that SDRAM is only returned once (as all of it is returned
embeddedartists 0:0fdadbc3d852 62 // the first time) and only if the user has chosen to do it (via the
embeddedartists 0:0fdadbc3d852 63 // okToUseSdramForHeap variable.
embeddedartists 0:0fdadbc3d852 64 if (okToUseSdramForHeap && lastReturnedBlock==0) {
embeddedartists 0:0fdadbc3d852 65 *block = (void*)SDRAM_BASE;
embeddedartists 0:0fdadbc3d852 66 lastReturnedBlock = SDRAM_BASE;
embeddedartists 0:0fdadbc3d852 67 return SDRAM_SIZE;
embeddedartists 0:0fdadbc3d852 68 }
embeddedartists 0:0fdadbc3d852 69 return 0;
embeddedartists 0:0fdadbc3d852 70 }
embeddedartists 0:0fdadbc3d852 71 #elif defined(TOOLCHAIN_GCC_CR) /* CodeRed's RedSuite or LPCXpresso IDE */
embeddedartists 0:0fdadbc3d852 72
embeddedartists 0:0fdadbc3d852 73 // NOTE: This way of overriding the implementation of malloc in NEWLIB
embeddedartists 0:0fdadbc3d852 74 // will prevent the internal RAM from being used by malloc as
embeddedartists 0:0fdadbc3d852 75 // it only exposes the SDRAM.
embeddedartists 0:0fdadbc3d852 76
embeddedartists 0:0fdadbc3d852 77 // Dynamic memory allocation related syscall.
embeddedartists 0:0fdadbc3d852 78 extern "C" caddr_t _sbrk(int incr) {
embeddedartists 0:0fdadbc3d852 79 static unsigned char* heap = (unsigned char*)SDRAM_BASE;
embeddedartists 0:0fdadbc3d852 80 unsigned char* prev_heap = heap;
embeddedartists 0:0fdadbc3d852 81 unsigned char* new_heap = heap + incr;
embeddedartists 0:0fdadbc3d852 82
embeddedartists 0:0fdadbc3d852 83 if (okToUseSdramForHeap && !initialized) {
embeddedartists 0:0fdadbc3d852 84 sdram_init();
embeddedartists 0:0fdadbc3d852 85 }
embeddedartists 0:0fdadbc3d852 86 if (!okToUseSdramForHeap) {
embeddedartists 0:0fdadbc3d852 87 //errno = ENOMEM;
embeddedartists 0:0fdadbc3d852 88 return (caddr_t)-1;
embeddedartists 0:0fdadbc3d852 89 }
embeddedartists 0:0fdadbc3d852 90 if (new_heap >= (unsigned char*)(SDRAM_BASE + SDRAM_SIZE)) {
embeddedartists 0:0fdadbc3d852 91 //errno = ENOMEM;
embeddedartists 0:0fdadbc3d852 92 return (caddr_t)-1;
embeddedartists 0:0fdadbc3d852 93 }
embeddedartists 0:0fdadbc3d852 94
embeddedartists 0:0fdadbc3d852 95 heap = new_heap;
embeddedartists 0:0fdadbc3d852 96 return (caddr_t) prev_heap;
embeddedartists 0:0fdadbc3d852 97 }
embeddedartists 0:0fdadbc3d852 98 #endif
embeddedartists 0:0fdadbc3d852 99
embeddedartists 0:0fdadbc3d852 100 /******************************************************************************
embeddedartists 0:0fdadbc3d852 101 * Local Functions
embeddedartists 0:0fdadbc3d852 102 *****************************************************************************/
embeddedartists 0:0fdadbc3d852 103
embeddedartists 0:0fdadbc3d852 104 static void pinConfig(void)
embeddedartists 0:0fdadbc3d852 105 {
embeddedartists 0:0fdadbc3d852 106 LPC_IOCON->P3_0 |= 1; /* D0 @ P3.0 */
embeddedartists 0:0fdadbc3d852 107 LPC_IOCON->P3_1 |= 1; /* D1 @ P3.1 */
embeddedartists 0:0fdadbc3d852 108 LPC_IOCON->P3_2 |= 1; /* D2 @ P3.2 */
embeddedartists 0:0fdadbc3d852 109 LPC_IOCON->P3_3 |= 1; /* D3 @ P3.3 */
embeddedartists 0:0fdadbc3d852 110
embeddedartists 0:0fdadbc3d852 111 LPC_IOCON->P3_4 |= 1; /* D4 @ P3.4 */
embeddedartists 0:0fdadbc3d852 112 LPC_IOCON->P3_5 |= 1; /* D5 @ P3.5 */
embeddedartists 0:0fdadbc3d852 113 LPC_IOCON->P3_6 |= 1; /* D6 @ P3.6 */
embeddedartists 0:0fdadbc3d852 114 LPC_IOCON->P3_7 |= 1; /* D7 @ P3.7 */
embeddedartists 0:0fdadbc3d852 115
embeddedartists 0:0fdadbc3d852 116 LPC_IOCON->P3_8 |= 1; /* D8 @ P3.8 */
embeddedartists 0:0fdadbc3d852 117 LPC_IOCON->P3_9 |= 1; /* D9 @ P3.9 */
embeddedartists 0:0fdadbc3d852 118 LPC_IOCON->P3_10 |= 1; /* D10 @ P3.10 */
embeddedartists 0:0fdadbc3d852 119 LPC_IOCON->P3_11 |= 1; /* D11 @ P3.11 */
embeddedartists 0:0fdadbc3d852 120
embeddedartists 0:0fdadbc3d852 121 LPC_IOCON->P3_12 |= 1; /* D12 @ P3.12 */
embeddedartists 0:0fdadbc3d852 122 LPC_IOCON->P3_13 |= 1; /* D13 @ P3.13 */
embeddedartists 0:0fdadbc3d852 123 LPC_IOCON->P3_14 |= 1; /* D14 @ P3.14 */
embeddedartists 0:0fdadbc3d852 124 LPC_IOCON->P3_15 |= 1; /* D15 @ P3.15 */
embeddedartists 0:0fdadbc3d852 125
embeddedartists 0:0fdadbc3d852 126 LPC_IOCON->P3_16 |= 1; /* D16 @ P3.16 */
embeddedartists 0:0fdadbc3d852 127 LPC_IOCON->P3_17 |= 1; /* D17 @ P3.17 */
embeddedartists 0:0fdadbc3d852 128 LPC_IOCON->P3_18 |= 1; /* D18 @ P3.18 */
embeddedartists 0:0fdadbc3d852 129 LPC_IOCON->P3_19 |= 1; /* D19 @ P3.19 */
embeddedartists 0:0fdadbc3d852 130
embeddedartists 0:0fdadbc3d852 131 LPC_IOCON->P3_20 |= 1; /* D20 @ P3.20 */
embeddedartists 0:0fdadbc3d852 132 LPC_IOCON->P3_21 |= 1; /* D21 @ P3.21 */
embeddedartists 0:0fdadbc3d852 133 LPC_IOCON->P3_22 |= 1; /* D22 @ P3.22 */
embeddedartists 0:0fdadbc3d852 134 LPC_IOCON->P3_23 |= 1; /* D23 @ P3.23 */
embeddedartists 0:0fdadbc3d852 135
embeddedartists 0:0fdadbc3d852 136 LPC_IOCON->P3_24 |= 1; /* D24 @ P3.24 */
embeddedartists 0:0fdadbc3d852 137 LPC_IOCON->P3_25 |= 1; /* D25 @ P3.25 */
embeddedartists 0:0fdadbc3d852 138 LPC_IOCON->P3_26 |= 1; /* D26 @ P3.26 */
embeddedartists 0:0fdadbc3d852 139 LPC_IOCON->P3_27 |= 1; /* D27 @ P3.27 */
embeddedartists 0:0fdadbc3d852 140
embeddedartists 0:0fdadbc3d852 141 LPC_IOCON->P3_28 |= 1; /* D28 @ P3.28 */
embeddedartists 0:0fdadbc3d852 142 LPC_IOCON->P3_29 |= 1; /* D29 @ P3.29 */
embeddedartists 0:0fdadbc3d852 143 LPC_IOCON->P3_30 |= 1; /* D30 @ P3.30 */
embeddedartists 0:0fdadbc3d852 144 LPC_IOCON->P3_31 |= 1; /* D31 @ P3.31 */
embeddedartists 0:0fdadbc3d852 145
embeddedartists 0:0fdadbc3d852 146 LPC_IOCON->P4_0 |= 1; /* A0 @ P4.0 */
embeddedartists 0:0fdadbc3d852 147 LPC_IOCON->P4_1 |= 1; /* A1 @ P4.1 */
embeddedartists 0:0fdadbc3d852 148 LPC_IOCON->P4_2 |= 1; /* A2 @ P4.2 */
embeddedartists 0:0fdadbc3d852 149 LPC_IOCON->P4_3 |= 1; /* A3 @ P4.3 */
embeddedartists 0:0fdadbc3d852 150
embeddedartists 0:0fdadbc3d852 151 LPC_IOCON->P4_4 |= 1; /* A4 @ P4.4 */
embeddedartists 0:0fdadbc3d852 152 LPC_IOCON->P4_5 |= 1; /* A5 @ P4.5 */
embeddedartists 0:0fdadbc3d852 153 LPC_IOCON->P4_6 |= 1; /* A6 @ P4.6 */
embeddedartists 0:0fdadbc3d852 154 LPC_IOCON->P4_7 |= 1; /* A7 @ P4.7 */
embeddedartists 0:0fdadbc3d852 155
embeddedartists 0:0fdadbc3d852 156 LPC_IOCON->P4_8 |= 1; /* A8 @ P4.8 */
embeddedartists 0:0fdadbc3d852 157 LPC_IOCON->P4_9 |= 1; /* A9 @ P4.9 */
embeddedartists 0:0fdadbc3d852 158 LPC_IOCON->P4_10 |= 1; /* A10 @ P4.10 */
embeddedartists 0:0fdadbc3d852 159 LPC_IOCON->P4_11 |= 1; /* A11 @ P4.11 */
embeddedartists 0:0fdadbc3d852 160
embeddedartists 0:0fdadbc3d852 161 LPC_IOCON->P4_12 |= 1; /* A12 @ P4.12 */
embeddedartists 0:0fdadbc3d852 162 LPC_IOCON->P4_13 |= 1; /* A13 @ P4.13 */
embeddedartists 0:0fdadbc3d852 163 LPC_IOCON->P4_14 |= 1; /* A14 @ P4.14 */
embeddedartists 0:0fdadbc3d852 164 #if 0 // not used for SDRAM
embeddedartists 0:0fdadbc3d852 165 LPC_IOCON->P4_15 |= 1; /* A15 @ P4.15 */
embeddedartists 0:0fdadbc3d852 166
embeddedartists 0:0fdadbc3d852 167 LPC_IOCON->P4_16 |= 1; /* A16 @ P4.16 */
embeddedartists 0:0fdadbc3d852 168 LPC_IOCON->P4_17 |= 1; /* A17 @ P4.17 */
embeddedartists 0:0fdadbc3d852 169 LPC_IOCON->P4_18 |= 1; /* A18 @ P4.18 */
embeddedartists 0:0fdadbc3d852 170 LPC_IOCON->P4_19 |= 1; /* A19 @ P4.19 */
embeddedartists 0:0fdadbc3d852 171
embeddedartists 0:0fdadbc3d852 172 LPC_IOCON->P4_20 |= 1; /* A20 @ P4.20 */
embeddedartists 0:0fdadbc3d852 173 LPC_IOCON->P4_21 |= 1; /* A21 @ P4.21 */
embeddedartists 0:0fdadbc3d852 174 LPC_IOCON->P4_22 |= 1; /* A22 @ P4.22 */
embeddedartists 0:0fdadbc3d852 175 LPC_IOCON->P4_23 |= 1; /* A23 @ P4.23 */
embeddedartists 0:0fdadbc3d852 176 #endif
embeddedartists 0:0fdadbc3d852 177
embeddedartists 0:0fdadbc3d852 178 LPC_IOCON->P4_24 |= 1; /* OEN @ P4.24 */
embeddedartists 0:0fdadbc3d852 179 LPC_IOCON->P4_25 |= 1; /* WEN @ P4.25 */
embeddedartists 0:0fdadbc3d852 180 #if 0 // not used for SDRAM
embeddedartists 0:0fdadbc3d852 181 LPC_IOCON->P4_26 |= 1; /* BLSN[0] @ P4.26 */
embeddedartists 0:0fdadbc3d852 182 LPC_IOCON->P4_27 |= 1; /* BLSN[1] @ P4.27 */
embeddedartists 0:0fdadbc3d852 183
embeddedartists 0:0fdadbc3d852 184
embeddedartists 0:0fdadbc3d852 185 LPC_IOCON->P4_28 |= 1; /* BLSN[2] @ P4.28 */
embeddedartists 0:0fdadbc3d852 186 LPC_IOCON->P4_29 |= 1; /* BLSN[3] @ P4.29 */
embeddedartists 0:0fdadbc3d852 187 LPC_IOCON->P4_30 |= 1; /* CSN[0] @ P4.30 */
embeddedartists 0:0fdadbc3d852 188 LPC_IOCON->P4_31 |= 1; /* CSN[1] @ P4.31 */
embeddedartists 0:0fdadbc3d852 189 #endif
embeddedartists 0:0fdadbc3d852 190
embeddedartists 0:0fdadbc3d852 191 LPC_IOCON->P2_14 |= 1; /* CSN[2] @ P2.14 */
embeddedartists 0:0fdadbc3d852 192 LPC_IOCON->P2_15 |= 1; /* CSN[3] @ P2.15 */
embeddedartists 0:0fdadbc3d852 193
embeddedartists 0:0fdadbc3d852 194 LPC_IOCON->P2_16 |= 1; /* CASN @ P2.16 */
embeddedartists 0:0fdadbc3d852 195 LPC_IOCON->P2_17 |= 1; /* RASN @ P2.17 */
embeddedartists 0:0fdadbc3d852 196 LPC_IOCON->P2_18 |= 1; /* CLK[0] @ P2.18 */
embeddedartists 0:0fdadbc3d852 197 #if 0 // not used for SDRAM
embeddedartists 0:0fdadbc3d852 198 LPC_IOCON->P2_19 |= 1; /* CLK[1] @ P2.19 */
embeddedartists 0:0fdadbc3d852 199 #endif
embeddedartists 0:0fdadbc3d852 200
embeddedartists 0:0fdadbc3d852 201 LPC_IOCON->P2_20 |= 1; /* DYCSN[0] @ P2.20 */
embeddedartists 0:0fdadbc3d852 202 #if 0 // not used for SDRAM
embeddedartists 0:0fdadbc3d852 203 LPC_IOCON->P2_21 |= 1; /* DYCSN[1] @ P2.21 */
embeddedartists 0:0fdadbc3d852 204 LPC_IOCON->P2_22 |= 1; /* DYCSN[2] @ P2.22 */
embeddedartists 0:0fdadbc3d852 205 LPC_IOCON->P2_23 |= 1; /* DYCSN[3] @ P2.23 */
embeddedartists 0:0fdadbc3d852 206 #endif
embeddedartists 0:0fdadbc3d852 207
embeddedartists 0:0fdadbc3d852 208 LPC_IOCON->P2_24 |= 1; /* CKE[0] @ P2.24 */
embeddedartists 0:0fdadbc3d852 209 #if 0 // not used for SDRAM
embeddedartists 0:0fdadbc3d852 210 LPC_IOCON->P2_25 |= 1; /* CKE[1] @ P2.25 */
embeddedartists 0:0fdadbc3d852 211 LPC_IOCON->P2_26 |= 1; /* CKE[2] @ P2.26 */
embeddedartists 0:0fdadbc3d852 212 LPC_IOCON->P2_27 |= 1; /* CKE[3] @ P2.27 */
embeddedartists 0:0fdadbc3d852 213 #endif
embeddedartists 0:0fdadbc3d852 214
embeddedartists 0:0fdadbc3d852 215 LPC_IOCON->P2_28 |= 1; /* DQM[0] @ P2.28 */
embeddedartists 0:0fdadbc3d852 216 LPC_IOCON->P2_29 |= 1; /* DQM[1] @ P2.29 */
embeddedartists 0:0fdadbc3d852 217 LPC_IOCON->P2_30 |= 1; /* DQM[2] @ P2.30 */
embeddedartists 0:0fdadbc3d852 218 LPC_IOCON->P2_31 |= 1; /* DQM[3] @ P2.31 */
embeddedartists 0:0fdadbc3d852 219 }
embeddedartists 0:0fdadbc3d852 220
embeddedartists 0:0fdadbc3d852 221
embeddedartists 0:0fdadbc3d852 222 static uint32_t sdram_test( void )
embeddedartists 0:0fdadbc3d852 223 {
embeddedartists 0:0fdadbc3d852 224 volatile uint32_t *wr_ptr;
embeddedartists 0:0fdadbc3d852 225 volatile uint16_t *short_wr_ptr;
embeddedartists 0:0fdadbc3d852 226 uint32_t data;
embeddedartists 0:0fdadbc3d852 227 uint32_t i, j;
embeddedartists 0:0fdadbc3d852 228
embeddedartists 0:0fdadbc3d852 229 wr_ptr = (uint32_t *)SDRAM_BASE;
embeddedartists 0:0fdadbc3d852 230 short_wr_ptr = (uint16_t *)wr_ptr;
embeddedartists 0:0fdadbc3d852 231 /* Clear content before 16 bit access test */
embeddedartists 0:0fdadbc3d852 232 // for (i = 0; i < SDRAM_SIZE/4; i++)
embeddedartists 0:0fdadbc3d852 233 // {
embeddedartists 0:0fdadbc3d852 234 // *wr_ptr++ = 0;
embeddedartists 0:0fdadbc3d852 235 // }
embeddedartists 0:0fdadbc3d852 236
embeddedartists 0:0fdadbc3d852 237 /* 16 bit write */
embeddedartists 0:0fdadbc3d852 238 for (i = 0; i < SDRAM_SIZE/0x40000; i++)
embeddedartists 0:0fdadbc3d852 239 {
embeddedartists 0:0fdadbc3d852 240 for (j = 0; j < 0x100; j++)
embeddedartists 0:0fdadbc3d852 241 {
embeddedartists 0:0fdadbc3d852 242 *short_wr_ptr++ = (i + j);
embeddedartists 0:0fdadbc3d852 243 *short_wr_ptr++ = (i + j) + 1;
embeddedartists 0:0fdadbc3d852 244 }
embeddedartists 0:0fdadbc3d852 245 }
embeddedartists 0:0fdadbc3d852 246
embeddedartists 0:0fdadbc3d852 247 /* Verifying */
embeddedartists 0:0fdadbc3d852 248 wr_ptr = (uint32_t *)SDRAM_BASE;
embeddedartists 0:0fdadbc3d852 249 for (i = 0; i < SDRAM_SIZE/0x40000; i++)
embeddedartists 0:0fdadbc3d852 250 {
embeddedartists 0:0fdadbc3d852 251 for (j = 0; j < 0x100; j++)
embeddedartists 0:0fdadbc3d852 252 {
embeddedartists 0:0fdadbc3d852 253 data = *wr_ptr;
embeddedartists 0:0fdadbc3d852 254 if (data != (((((i + j) + 1) & 0xFFFF) << 16) | ((i + j) & 0xFFFF)))
embeddedartists 0:0fdadbc3d852 255 {
embeddedartists 0:0fdadbc3d852 256 return 0x0;
embeddedartists 0:0fdadbc3d852 257 }
embeddedartists 0:0fdadbc3d852 258 wr_ptr++;
embeddedartists 0:0fdadbc3d852 259 }
embeddedartists 0:0fdadbc3d852 260 }
embeddedartists 0:0fdadbc3d852 261 return 0x1;
embeddedartists 0:0fdadbc3d852 262 }
embeddedartists 0:0fdadbc3d852 263
embeddedartists 0:0fdadbc3d852 264 static uint32_t find_cmddly(void)
embeddedartists 0:0fdadbc3d852 265 {
embeddedartists 0:0fdadbc3d852 266 uint32_t cmddly, cmddlystart, cmddlyend, dwtemp;
embeddedartists 0:0fdadbc3d852 267 uint32_t ppass = 0x0, pass = 0x0;
embeddedartists 0:0fdadbc3d852 268
embeddedartists 0:0fdadbc3d852 269 cmddly = 0x0;
embeddedartists 0:0fdadbc3d852 270 cmddlystart = cmddlyend = 0xFF;
embeddedartists 0:0fdadbc3d852 271
embeddedartists 0:0fdadbc3d852 272 while (cmddly < 32)
embeddedartists 0:0fdadbc3d852 273 {
embeddedartists 0:0fdadbc3d852 274 dwtemp = LPC_SC->EMCDLYCTL & ~0x1F;
embeddedartists 0:0fdadbc3d852 275 LPC_SC->EMCDLYCTL = dwtemp | cmddly;
embeddedartists 0:0fdadbc3d852 276
embeddedartists 0:0fdadbc3d852 277 if (sdram_test() == 0x1)
embeddedartists 0:0fdadbc3d852 278 {
embeddedartists 0:0fdadbc3d852 279 /* Test passed */
embeddedartists 0:0fdadbc3d852 280 if (cmddlystart == 0xFF)
embeddedartists 0:0fdadbc3d852 281 {
embeddedartists 0:0fdadbc3d852 282 cmddlystart = cmddly;
embeddedartists 0:0fdadbc3d852 283 }
embeddedartists 0:0fdadbc3d852 284 ppass = 0x1;
embeddedartists 0:0fdadbc3d852 285 }
embeddedartists 0:0fdadbc3d852 286 else
embeddedartists 0:0fdadbc3d852 287 {
embeddedartists 0:0fdadbc3d852 288 /* Test failed */
embeddedartists 0:0fdadbc3d852 289 if (ppass == 1)
embeddedartists 0:0fdadbc3d852 290 {
embeddedartists 0:0fdadbc3d852 291 cmddlyend = cmddly;
embeddedartists 0:0fdadbc3d852 292 pass = 0x1;
embeddedartists 0:0fdadbc3d852 293 ppass = 0x0;
embeddedartists 0:0fdadbc3d852 294 }
embeddedartists 0:0fdadbc3d852 295 }
embeddedartists 0:0fdadbc3d852 296
embeddedartists 0:0fdadbc3d852 297 /* Try next value */
embeddedartists 0:0fdadbc3d852 298 cmddly++;
embeddedartists 0:0fdadbc3d852 299 }
embeddedartists 0:0fdadbc3d852 300
embeddedartists 0:0fdadbc3d852 301 /* If the test passed, the we can use the average of the min and max values to get an optimal DQSIN delay */
embeddedartists 0:0fdadbc3d852 302 if (pass == 0x1)
embeddedartists 0:0fdadbc3d852 303 {
embeddedartists 0:0fdadbc3d852 304 cmddly = (cmddlystart + cmddlyend) / 2;
embeddedartists 0:0fdadbc3d852 305 }
embeddedartists 0:0fdadbc3d852 306 else if (ppass == 0x1)
embeddedartists 0:0fdadbc3d852 307 {
embeddedartists 0:0fdadbc3d852 308 cmddly = (cmddlystart + 0x1F) / 2;
embeddedartists 0:0fdadbc3d852 309 }
embeddedartists 0:0fdadbc3d852 310 else
embeddedartists 0:0fdadbc3d852 311 {
embeddedartists 0:0fdadbc3d852 312 /* A working value couldn't be found, just pick something safe so the system doesn't become unstable */
embeddedartists 0:0fdadbc3d852 313 cmddly = 0x10;
embeddedartists 0:0fdadbc3d852 314 }
embeddedartists 0:0fdadbc3d852 315
embeddedartists 0:0fdadbc3d852 316 dwtemp = LPC_SC->EMCDLYCTL & ~0x1F;
embeddedartists 0:0fdadbc3d852 317 LPC_SC->EMCDLYCTL = dwtemp | cmddly;
embeddedartists 0:0fdadbc3d852 318
embeddedartists 0:0fdadbc3d852 319 return (pass | ppass);
embeddedartists 0:0fdadbc3d852 320 }
embeddedartists 0:0fdadbc3d852 321
embeddedartists 0:0fdadbc3d852 322 static uint32_t find_fbclkdly(void)
embeddedartists 0:0fdadbc3d852 323 {
embeddedartists 0:0fdadbc3d852 324 uint32_t fbclkdly, fbclkdlystart, fbclkdlyend, dwtemp;
embeddedartists 0:0fdadbc3d852 325 uint32_t ppass = 0x0, pass = 0x0;
embeddedartists 0:0fdadbc3d852 326
embeddedartists 0:0fdadbc3d852 327 fbclkdly = 0x0;
embeddedartists 0:0fdadbc3d852 328 fbclkdlystart = fbclkdlyend = 0xFF;
embeddedartists 0:0fdadbc3d852 329
embeddedartists 0:0fdadbc3d852 330 while (fbclkdly < 32)
embeddedartists 0:0fdadbc3d852 331 {
embeddedartists 0:0fdadbc3d852 332 dwtemp = LPC_SC->EMCDLYCTL & ~0x1F00;
embeddedartists 0:0fdadbc3d852 333 LPC_SC->EMCDLYCTL = dwtemp | (fbclkdly << 8);
embeddedartists 0:0fdadbc3d852 334
embeddedartists 0:0fdadbc3d852 335 if (sdram_test() == 0x1)
embeddedartists 0:0fdadbc3d852 336 {
embeddedartists 0:0fdadbc3d852 337 /* Test passed */
embeddedartists 0:0fdadbc3d852 338 if (fbclkdlystart == 0xFF)
embeddedartists 0:0fdadbc3d852 339 {
embeddedartists 0:0fdadbc3d852 340 fbclkdlystart = fbclkdly;
embeddedartists 0:0fdadbc3d852 341 }
embeddedartists 0:0fdadbc3d852 342 ppass = 0x1;
embeddedartists 0:0fdadbc3d852 343 }
embeddedartists 0:0fdadbc3d852 344 else
embeddedartists 0:0fdadbc3d852 345 {
embeddedartists 0:0fdadbc3d852 346 /* Test failed */
embeddedartists 0:0fdadbc3d852 347 if (ppass == 1)
embeddedartists 0:0fdadbc3d852 348 {
embeddedartists 0:0fdadbc3d852 349 fbclkdlyend = fbclkdly;
embeddedartists 0:0fdadbc3d852 350 pass = 0x1;
embeddedartists 0:0fdadbc3d852 351 ppass = 0x0;
embeddedartists 0:0fdadbc3d852 352 }
embeddedartists 0:0fdadbc3d852 353 }
embeddedartists 0:0fdadbc3d852 354
embeddedartists 0:0fdadbc3d852 355 /* Try next value */
embeddedartists 0:0fdadbc3d852 356 fbclkdly++;
embeddedartists 0:0fdadbc3d852 357 }
embeddedartists 0:0fdadbc3d852 358
embeddedartists 0:0fdadbc3d852 359 /* If the test passed, the we can use the average of the min and max values to get an optimal DQSIN delay */
embeddedartists 0:0fdadbc3d852 360 if (pass == 0x1)
embeddedartists 0:0fdadbc3d852 361 {
embeddedartists 0:0fdadbc3d852 362 fbclkdly = (fbclkdlystart + fbclkdlyend) / 2;
embeddedartists 0:0fdadbc3d852 363 }
embeddedartists 0:0fdadbc3d852 364 else if (ppass == 0x1)
embeddedartists 0:0fdadbc3d852 365 {
embeddedartists 0:0fdadbc3d852 366 fbclkdly = (fbclkdlystart + 0x1F) / 2;
embeddedartists 0:0fdadbc3d852 367 }
embeddedartists 0:0fdadbc3d852 368 else
embeddedartists 0:0fdadbc3d852 369 {
embeddedartists 0:0fdadbc3d852 370 /* A working value couldn't be found, just pick something safe so the system doesn't become unstable */
embeddedartists 0:0fdadbc3d852 371 fbclkdly = 0x10;
embeddedartists 0:0fdadbc3d852 372 }
embeddedartists 0:0fdadbc3d852 373
embeddedartists 0:0fdadbc3d852 374 dwtemp = LPC_SC->EMCDLYCTL & ~0x1F00;
embeddedartists 0:0fdadbc3d852 375 LPC_SC->EMCDLYCTL = dwtemp | (fbclkdly << 8);
embeddedartists 0:0fdadbc3d852 376
embeddedartists 0:0fdadbc3d852 377 return (pass | ppass);
embeddedartists 0:0fdadbc3d852 378 }
embeddedartists 0:0fdadbc3d852 379
embeddedartists 0:0fdadbc3d852 380 static uint32_t calibration( void )
embeddedartists 0:0fdadbc3d852 381 {
embeddedartists 0:0fdadbc3d852 382 uint32_t dwtemp, i;
embeddedartists 0:0fdadbc3d852 383 uint32_t cnt = 0;
embeddedartists 0:0fdadbc3d852 384
embeddedartists 0:0fdadbc3d852 385 for (i = 0; i < 10; i++)
embeddedartists 0:0fdadbc3d852 386 {
embeddedartists 0:0fdadbc3d852 387 dwtemp = LPC_SC->EMCCAL & ~0x4000;
embeddedartists 0:0fdadbc3d852 388 LPC_SC->EMCCAL = dwtemp | 0x4000;
embeddedartists 0:0fdadbc3d852 389
embeddedartists 0:0fdadbc3d852 390 dwtemp = LPC_SC->EMCCAL;
embeddedartists 0:0fdadbc3d852 391 while ((dwtemp & 0x8000) == 0x0000)
embeddedartists 0:0fdadbc3d852 392 {
embeddedartists 0:0fdadbc3d852 393 dwtemp = LPC_SC->EMCCAL;
embeddedartists 0:0fdadbc3d852 394 }
embeddedartists 0:0fdadbc3d852 395 cnt += (dwtemp & 0xFF);
embeddedartists 0:0fdadbc3d852 396 }
embeddedartists 0:0fdadbc3d852 397 return (cnt / 10);
embeddedartists 0:0fdadbc3d852 398 }
embeddedartists 0:0fdadbc3d852 399
embeddedartists 0:0fdadbc3d852 400 /******************************************************************************
embeddedartists 0:0fdadbc3d852 401 * Public Functions
embeddedartists 0:0fdadbc3d852 402 *****************************************************************************/
embeddedartists 0:0fdadbc3d852 403
embeddedartists 0:0fdadbc3d852 404
embeddedartists 0:0fdadbc3d852 405 void adjust_timing( void )
embeddedartists 0:0fdadbc3d852 406 {
embeddedartists 0:0fdadbc3d852 407 uint32_t dwtemp, cmddly, fbclkdly;
embeddedartists 0:0fdadbc3d852 408
embeddedartists 0:0fdadbc3d852 409 /* Current value */
embeddedartists 0:0fdadbc3d852 410 ringosccount[1] = calibration();
embeddedartists 0:0fdadbc3d852 411
embeddedartists 0:0fdadbc3d852 412 dwtemp = LPC_SC->EMCDLYCTL;
embeddedartists 0:0fdadbc3d852 413 cmddly = ((dwtemp & 0x1F) * ringosccount[0] / ringosccount[1]) & 0x1F;
embeddedartists 0:0fdadbc3d852 414 fbclkdly = ((dwtemp & 0x1F00) * ringosccount[0] / ringosccount[1]) & 0x1F00;
embeddedartists 0:0fdadbc3d852 415 LPC_SC->EMCDLYCTL = (dwtemp & ~0x1F1F) | fbclkdly | cmddly;
embeddedartists 0:0fdadbc3d852 416 }
embeddedartists 0:0fdadbc3d852 417
embeddedartists 0:0fdadbc3d852 418 /******************************************************************************
embeddedartists 0:0fdadbc3d852 419 *
embeddedartists 0:0fdadbc3d852 420 * Description:
embeddedartists 0:0fdadbc3d852 421 * Initialize the SDRAM
embeddedartists 0:0fdadbc3d852 422 *
embeddedartists 0:0fdadbc3d852 423 *****************************************************************************/
embeddedartists 0:0fdadbc3d852 424 uint32_t sdram_init (void)
embeddedartists 0:0fdadbc3d852 425 {
embeddedartists 0:0fdadbc3d852 426 uint32_t i;
embeddedartists 0:0fdadbc3d852 427 uint32_t dwtemp = 0;
embeddedartists 0:0fdadbc3d852 428 //uint16_t wtemp = 0;
embeddedartists 0:0fdadbc3d852 429
embeddedartists 0:0fdadbc3d852 430 if (initialized) {
embeddedartists 0:0fdadbc3d852 431 return 0;
embeddedartists 0:0fdadbc3d852 432 }
embeddedartists 0:0fdadbc3d852 433
embeddedartists 0:0fdadbc3d852 434 LPC_SC->PCONP |= 0x00000800;
embeddedartists 0:0fdadbc3d852 435 LPC_SC->EMCDLYCTL = 0x00001010;
embeddedartists 0:0fdadbc3d852 436 LPC_EMC->Control = 0x00000001;
embeddedartists 0:0fdadbc3d852 437 LPC_EMC->Config = 0x00000000;
embeddedartists 0:0fdadbc3d852 438
embeddedartists 0:0fdadbc3d852 439 pinConfig(); //Full 32-bit Data bus, 24-bit Address
embeddedartists 0:0fdadbc3d852 440
embeddedartists 0:0fdadbc3d852 441 /* Configure memory layout, but MUST DISABLE BUFFERs during configuration */
embeddedartists 0:0fdadbc3d852 442 /* 256MB, 8Mx32, 4 banks, row=12, column=9 */
embeddedartists 0:0fdadbc3d852 443 LPC_EMC->DynamicConfig0 = 0x00004480;
embeddedartists 0:0fdadbc3d852 444
embeddedartists 0:0fdadbc3d852 445 /*Configure timing for ISSI IS4x32800D SDRAM*/
embeddedartists 0:0fdadbc3d852 446
embeddedartists 0:0fdadbc3d852 447 #if (SDRAM_SPEED==SDRAM_SPEED_48)
embeddedartists 0:0fdadbc3d852 448 //Timing for 48MHz Bus
embeddedartists 0:0fdadbc3d852 449 LPC_EMC->DynamicRasCas0 = 0x00000201; /* 1 RAS, 2 CAS latency */
embeddedartists 0:0fdadbc3d852 450 LPC_EMC->DynamicReadConfig = 0x00000001; /* Command delayed strategy, using EMCCLKDELAY */
embeddedartists 0:0fdadbc3d852 451 LPC_EMC->DynamicRP = 0x00000000; /* ( n + 1 ) -> 1 clock cycles */
embeddedartists 0:0fdadbc3d852 452 LPC_EMC->DynamicRAS = 0x00000002; /* ( n + 1 ) -> 3 clock cycles */
embeddedartists 0:0fdadbc3d852 453 LPC_EMC->DynamicSREX = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
embeddedartists 0:0fdadbc3d852 454 LPC_EMC->DynamicAPR = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:0fdadbc3d852 455 LPC_EMC->DynamicDAL = 0x00000002; /* ( n ) -> 2 clock cycles */
embeddedartists 0:0fdadbc3d852 456 LPC_EMC->DynamicWR = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:0fdadbc3d852 457 LPC_EMC->DynamicRC = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
embeddedartists 0:0fdadbc3d852 458 LPC_EMC->DynamicRFC = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
embeddedartists 0:0fdadbc3d852 459 LPC_EMC->DynamicXSR = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
embeddedartists 0:0fdadbc3d852 460 LPC_EMC->DynamicRRD = 0x00000000; /* ( n + 1 ) -> 1 clock cycles */
embeddedartists 0:0fdadbc3d852 461 LPC_EMC->DynamicMRD = 0x00000000; /* ( n + 1 ) -> 1 clock cycles */
embeddedartists 0:0fdadbc3d852 462 #elif (SDRAM_SPEED==SDRAM_SPEED_50)
embeddedartists 0:0fdadbc3d852 463 //Timing for 50MHz Bus (with 100MHz M3 Core)
embeddedartists 0:0fdadbc3d852 464 LPC_EMC->DynamicRasCas0 = 0x00000201; /* 1 RAS, 2 CAS latency */
embeddedartists 0:0fdadbc3d852 465 LPC_EMC->DynamicReadConfig = 0x00000001; /* Command delayed strategy, using EMCCLKDELAY */
embeddedartists 0:0fdadbc3d852 466 LPC_EMC->DynamicRP = 0x00000000; /* ( n + 1 ) -> 1 clock cycles */
embeddedartists 0:0fdadbc3d852 467 LPC_EMC->DynamicRAS = 0x00000002; /* ( n + 1 ) -> 3 clock cycles */
embeddedartists 0:0fdadbc3d852 468 LPC_EMC->DynamicSREX = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
embeddedartists 0:0fdadbc3d852 469 LPC_EMC->DynamicAPR = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:0fdadbc3d852 470 LPC_EMC->DynamicDAL = 0x00000002; /* ( n ) -> 2 clock cycles */
embeddedartists 0:0fdadbc3d852 471 LPC_EMC->DynamicWR = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:0fdadbc3d852 472 LPC_EMC->DynamicRC = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
embeddedartists 0:0fdadbc3d852 473 LPC_EMC->DynamicRFC = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
embeddedartists 0:0fdadbc3d852 474 LPC_EMC->DynamicXSR = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
embeddedartists 0:0fdadbc3d852 475 LPC_EMC->DynamicRRD = 0x00000000; /* ( n + 1 ) -> 1 clock cycles */
embeddedartists 0:0fdadbc3d852 476 LPC_EMC->DynamicMRD = 0x00000000; /* ( n + 1 ) -> 1 clock cycles */
embeddedartists 0:0fdadbc3d852 477 #elif (SDRAM_SPEED==SDRAM_SPEED_60)
embeddedartists 0:0fdadbc3d852 478 //Timing for 60 MHz Bus (same as 72MHz)
embeddedartists 0:0fdadbc3d852 479 LPC_EMC->DynamicRasCas0 = 0x00000202; /* 2 RAS, 2 CAS latency */
embeddedartists 0:0fdadbc3d852 480 LPC_EMC->DynamicReadConfig = 0x00000001; /* Command delayed strategy, using EMCCLKDELAY */
embeddedartists 0:0fdadbc3d852 481 LPC_EMC->DynamicRP = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:0fdadbc3d852 482 LPC_EMC->DynamicRAS = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
embeddedartists 0:0fdadbc3d852 483 LPC_EMC->DynamicSREX = 0x00000005; /* ( n + 1 ) -> 6 clock cycles */
embeddedartists 0:0fdadbc3d852 484 LPC_EMC->DynamicAPR = 0x00000002; /* ( n + 1 ) -> 3 clock cycles */
embeddedartists 0:0fdadbc3d852 485 LPC_EMC->DynamicDAL = 0x00000003; /* ( n ) -> 3 clock cycles */
embeddedartists 0:0fdadbc3d852 486 LPC_EMC->DynamicWR = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:0fdadbc3d852 487 LPC_EMC->DynamicRC = 0x00000004; /* ( n + 1 ) -> 5 clock cycles */
embeddedartists 0:0fdadbc3d852 488 LPC_EMC->DynamicRFC = 0x00000004; /* ( n + 1 ) -> 5 clock cycles */
embeddedartists 0:0fdadbc3d852 489 LPC_EMC->DynamicXSR = 0x00000005; /* ( n + 1 ) -> 6 clock cycles */
embeddedartists 0:0fdadbc3d852 490 LPC_EMC->DynamicRRD = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:0fdadbc3d852 491 LPC_EMC->DynamicMRD = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:0fdadbc3d852 492 #elif (SDRAM_SPEED==SDRAM_SPEED_72)
embeddedartists 0:0fdadbc3d852 493 //Timing for 72 MHz Bus
embeddedartists 0:0fdadbc3d852 494 LPC_EMC->DynamicRasCas0 = 0x00000202; /* 2 RAS, 2 CAS latency */
embeddedartists 0:0fdadbc3d852 495 LPC_EMC->DynamicReadConfig = 0x00000001; /* Command delayed strategy, using EMCCLKDELAY */
embeddedartists 0:0fdadbc3d852 496 LPC_EMC->DynamicRP = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:0fdadbc3d852 497 LPC_EMC->DynamicRAS = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
embeddedartists 0:0fdadbc3d852 498 LPC_EMC->DynamicSREX = 0x00000005; /* ( n + 1 ) -> 6 clock cycles */
embeddedartists 0:0fdadbc3d852 499 LPC_EMC->DynamicAPR = 0x00000002; /* ( n + 1 ) -> 3 clock cycles */
embeddedartists 0:0fdadbc3d852 500 LPC_EMC->DynamicDAL = 0x00000003; /* ( n ) -> 3 clock cycles */
embeddedartists 0:0fdadbc3d852 501 LPC_EMC->DynamicWR = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:0fdadbc3d852 502 LPC_EMC->DynamicRC = 0x00000004; /* ( n + 1 ) -> 5 clock cycles */
embeddedartists 0:0fdadbc3d852 503 LPC_EMC->DynamicRFC = 0x00000004; /* ( n + 1 ) -> 5 clock cycles */
embeddedartists 0:0fdadbc3d852 504 LPC_EMC->DynamicXSR = 0x00000005; /* ( n + 1 ) -> 6 clock cycles */
embeddedartists 0:0fdadbc3d852 505 LPC_EMC->DynamicRRD = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:0fdadbc3d852 506 LPC_EMC->DynamicMRD = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:0fdadbc3d852 507 #elif (SDRAM_SPEED==SDRAM_SPEED_80)
embeddedartists 0:0fdadbc3d852 508 //Timing for 80 MHz Bus (same as 72MHz)
embeddedartists 0:0fdadbc3d852 509 LPC_EMC->DynamicRasCas0 = 0x00000202; /* 2 RAS, 2 CAS latency */
embeddedartists 0:0fdadbc3d852 510 LPC_EMC->DynamicReadConfig = 0x00000001; /* Command delayed strategy, using EMCCLKDELAY */
embeddedartists 0:0fdadbc3d852 511 LPC_EMC->DynamicRP = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:0fdadbc3d852 512 LPC_EMC->DynamicRAS = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
embeddedartists 0:0fdadbc3d852 513 LPC_EMC->DynamicSREX = 0x00000005; /* ( n + 1 ) -> 6 clock cycles */
embeddedartists 0:0fdadbc3d852 514 LPC_EMC->DynamicAPR = 0x00000002; /* ( n + 1 ) -> 3 clock cycles */
embeddedartists 0:0fdadbc3d852 515 LPC_EMC->DynamicDAL = 0x00000003; /* ( n ) -> 3 clock cycles */
embeddedartists 0:0fdadbc3d852 516 LPC_EMC->DynamicWR = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:0fdadbc3d852 517 LPC_EMC->DynamicRC = 0x00000004; /* ( n + 1 ) -> 5 clock cycles */
embeddedartists 0:0fdadbc3d852 518 LPC_EMC->DynamicRFC = 0x00000004; /* ( n + 1 ) -> 5 clock cycles */
embeddedartists 0:0fdadbc3d852 519 LPC_EMC->DynamicXSR = 0x00000005; /* ( n + 1 ) -> 6 clock cycles */
embeddedartists 0:0fdadbc3d852 520 LPC_EMC->DynamicRRD = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:0fdadbc3d852 521 LPC_EMC->DynamicMRD = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:0fdadbc3d852 522 #else
embeddedartists 0:0fdadbc3d852 523 #error UNSUPPORTED SDRAM FREQ
embeddedartists 0:0fdadbc3d852 524 #endif
embeddedartists 0:0fdadbc3d852 525
embeddedartists 0:0fdadbc3d852 526 LPC_EMC->DynamicControl = 0x00000183; /* Issue NOP command */
embeddedartists 0:0fdadbc3d852 527 wait(0.2); /* wait 200ms */
embeddedartists 0:0fdadbc3d852 528 LPC_EMC->DynamicControl = 0x00000103; /* Issue PALL command */
embeddedartists 0:0fdadbc3d852 529 LPC_EMC->DynamicRefresh = 0x00000002; /* ( n * 16 ) -> 32 clock cycles */
embeddedartists 0:0fdadbc3d852 530 for(i = 0; i < 0x80; i++); /* wait 128 AHB clock cycles */
embeddedartists 0:0fdadbc3d852 531
embeddedartists 0:0fdadbc3d852 532
embeddedartists 0:0fdadbc3d852 533 #if (SDRAM_SPEED==SDRAM_SPEED_48)
embeddedartists 0:0fdadbc3d852 534 //Timing for 48MHz Bus
embeddedartists 0:0fdadbc3d852 535 LPC_EMC->DynamicRefresh = 0x0000002E; /* ( n * 16 ) -> 736 clock cycles -> 15.330uS at 48MHz <= 15.625uS ( 64ms / 4096 row ) */
embeddedartists 0:0fdadbc3d852 536 #elif (SDRAM_SPEED==SDRAM_SPEED_50)
embeddedartists 0:0fdadbc3d852 537 //Timing for 50MHz Bus
embeddedartists 0:0fdadbc3d852 538 LPC_EMC->DynamicRefresh = 0x0000003A; /* ( n * 16 ) -> 768 clock cycles -> 15.360uS at 50MHz <= 15.625uS ( 64ms / 4096 row ) */
embeddedartists 0:0fdadbc3d852 539 #elif (SDRAM_SPEED==SDRAM_SPEED_60)
embeddedartists 0:0fdadbc3d852 540 //Timing for 60MHz Bus
embeddedartists 0:0fdadbc3d852 541 LPC_EMC->DynamicRefresh = 0x0000003A; /* ( n * 16 ) -> 928 clock cycles -> 15.466uS at 60MHz <= 15.625uS ( 64ms / 4096 row ) */
embeddedartists 0:0fdadbc3d852 542 #elif (SDRAM_SPEED==SDRAM_SPEED_72)
embeddedartists 0:0fdadbc3d852 543 //Timing for 72MHz Bus
embeddedartists 0:0fdadbc3d852 544 LPC_EMC->DynamicRefresh = 0x00000046; /* ( n * 16 ) -> 1120 clock cycles -> 15.556uS at 72MHz <= 15.625uS ( 64ms / 4096 row ) */
embeddedartists 0:0fdadbc3d852 545 #elif (SDRAM_SPEED==SDRAM_SPEED_80)
embeddedartists 0:0fdadbc3d852 546 //Timing for 80MHz Bus
embeddedartists 0:0fdadbc3d852 547 LPC_EMC->DynamicRefresh = 0x0000004E; /* ( n * 16 ) -> 1248 clock cycles -> 15.600uS at 80MHz <= 15.625uS ( 64ms / 4096 row ) */
embeddedartists 0:0fdadbc3d852 548 #else
embeddedartists 0:0fdadbc3d852 549 #error UNSUPPORTED SDRAM FREQ
embeddedartists 0:0fdadbc3d852 550 #endif
embeddedartists 0:0fdadbc3d852 551
embeddedartists 0:0fdadbc3d852 552 LPC_EMC->DynamicControl = 0x00000083; /* Issue MODE command */
embeddedartists 0:0fdadbc3d852 553 //Timing for 48/60/72MHZ Bus
embeddedartists 0:0fdadbc3d852 554 dwtemp = *((volatile uint32_t *)(SDRAM_BASE | (0x22<<(2+2+9)))); /* 4 burst, 2 CAS latency */
embeddedartists 0:0fdadbc3d852 555 dwtemp = dwtemp;
embeddedartists 0:0fdadbc3d852 556 LPC_EMC->DynamicControl = 0x00000000; /* Issue NORMAL command */
embeddedartists 0:0fdadbc3d852 557 //[re]enable buffers
embeddedartists 0:0fdadbc3d852 558 LPC_EMC->DynamicConfig0 = 0x00084480; /* 256MB, 8Mx32, 4 banks, row=12, column=9 */
embeddedartists 0:0fdadbc3d852 559
embeddedartists 0:0fdadbc3d852 560 /* Nominal value */
embeddedartists 0:0fdadbc3d852 561 ringosccount[0] = calibration();
embeddedartists 0:0fdadbc3d852 562
embeddedartists 0:0fdadbc3d852 563 if (find_cmddly() == 0x0)
embeddedartists 0:0fdadbc3d852 564 {
embeddedartists 0:0fdadbc3d852 565 //while (1); /* fatal error */
embeddedartists 0:0fdadbc3d852 566 return 1;//FALSE;
embeddedartists 0:0fdadbc3d852 567 }
embeddedartists 0:0fdadbc3d852 568
embeddedartists 0:0fdadbc3d852 569 if (find_fbclkdly() == 0x0)
embeddedartists 0:0fdadbc3d852 570 {
embeddedartists 0:0fdadbc3d852 571 //while (1); /* fatal error */
embeddedartists 0:0fdadbc3d852 572 return 1;//FALSE;
embeddedartists 0:0fdadbc3d852 573 }
embeddedartists 0:0fdadbc3d852 574
embeddedartists 0:0fdadbc3d852 575 adjust_timing();
embeddedartists 0:0fdadbc3d852 576
embeddedartists 0:0fdadbc3d852 577 initialized = true;
embeddedartists 0:0fdadbc3d852 578
embeddedartists 0:0fdadbc3d852 579 return 0;//TRUE;
embeddedartists 0:0fdadbc3d852 580 }
embeddedartists 0:0fdadbc3d852 581
embeddedartists 0:0fdadbc3d852 582 void sdram_disableMallocSdram()
embeddedartists 0:0fdadbc3d852 583 {
embeddedartists 0:0fdadbc3d852 584 okToUseSdramForHeap = false;
embeddedartists 0:0fdadbc3d852 585 }
embeddedartists 0:0fdadbc3d852 586
embeddedartists 0:0fdadbc3d852 587