EALib - A library with drivers for different peripherals …

test » Code » EALib

test / EALib

A library with drivers for different peripherals on the LPC4088 QuickStart Board or related add-on boards.

Dependencies: FATFileSystem

Dependents: bare

Fork of EALib by EmbeddedArtists AB

MCIFileSystem.cpp@2:1c6134c80dc5, 2013-09-27 (annotated)

Committer:: embeddedartists
Date:: Fri Sep 27 14:07:07 2013 +0000
Revision:: 2:1c6134c80dc5
Parent:: 0:0fdadbc3d852
Child:: 3:9d31a3c5013e

Added documentation of QSPIFileSystem

Who changed what in which revision?

User	Revision	Line number	New contents of line
embeddedartists	0:0fdadbc3d852	1
embeddedartists	0:0fdadbc3d852	2	/******************************************************************************
embeddedartists	0:0fdadbc3d852	3	* Includes
embeddedartists	0:0fdadbc3d852	4	*****************************************************************************/
embeddedartists	0:0fdadbc3d852	5
embeddedartists	0:0fdadbc3d852	6	#include "MCIFileSystem.h"
embeddedartists	0:0fdadbc3d852	7	#include "mbed_debug.h"
embeddedartists	0:0fdadbc3d852	8
embeddedartists	0:0fdadbc3d852	9	#include "diskio.h" //STA_* defines
embeddedartists	0:0fdadbc3d852	10	#include "gpdma.h"
embeddedartists	0:0fdadbc3d852	11
embeddedartists	0:0fdadbc3d852	12	/******************************************************************************
embeddedartists	0:0fdadbc3d852	13	* Defines and typedefs
embeddedartists	0:0fdadbc3d852	14	*****************************************************************************/
embeddedartists	0:0fdadbc3d852	15
embeddedartists	0:0fdadbc3d852	16	#define MCI_DBG 0
embeddedartists	0:0fdadbc3d852	17
embeddedartists	0:0fdadbc3d852	18	#define CMD_TIMEOUT (0x10000)
embeddedartists	0:0fdadbc3d852	19
embeddedartists	0:0fdadbc3d852	20	#define DATA_TIMER_VALUE_R (SDC_TRAN_CLOCK_RATE / 4) // 250ms
embeddedartists	0:0fdadbc3d852	21	#define DATA_TIMER_VALUE_W (SDC_TRAN_CLOCK_RATE) // 1000ms
embeddedartists	0:0fdadbc3d852	22	#define ACQUIRE_DELAY (0.100f) /!< inter-command acquire oper condition delay in seconds /
embeddedartists	0:0fdadbc3d852	23
embeddedartists	0:0fdadbc3d852	24	#define SYSCTL_CLOCK_SDC (1<<28)
embeddedartists	0:0fdadbc3d852	25
embeddedartists	0:0fdadbc3d852	26	/**
embeddedartists	0:0fdadbc3d852	27	* @brief SDC Clear Register bit definitions
embeddedartists	0:0fdadbc3d852	28	*/
embeddedartists	0:0fdadbc3d852	29	/** Clear all status flag*/
embeddedartists	0:0fdadbc3d852	30	#define SDC_CLEAR_ALL ((uint32_t) 0x7FF)
embeddedartists	0:0fdadbc3d852	31
embeddedartists	0:0fdadbc3d852	32	/*
embeddedartists	0:0fdadbc3d852	33	* SDMMC Card bus clock rate definitions
embeddedartists	0:0fdadbc3d852	34	*/
embeddedartists	0:0fdadbc3d852	35	/** Card bus clock in Card Identification Mode */
embeddedartists	0:0fdadbc3d852	36	#define SDC_IDENT_CLOCK_RATE (400000) /* 400KHz */
embeddedartists	0:0fdadbc3d852	37	/** Card bus clock in Data Transfer Mode */
embeddedartists	0:0fdadbc3d852	38	#define SDC_TRAN_CLOCK_RATE (20000000) /* 20MHz */
embeddedartists	0:0fdadbc3d852	39
embeddedartists	0:0fdadbc3d852	40	/**
embeddedartists	0:0fdadbc3d852	41	* @brief SDC Power Control Register bit definitions
embeddedartists	0:0fdadbc3d852	42	*/
embeddedartists	0:0fdadbc3d852	43	/** SD_CMD Output Control */
embeddedartists	0:0fdadbc3d852	44	#define SDC_PWR_OPENDRAIN (((uint32_t) 1) << 6)
embeddedartists	0:0fdadbc3d852	45
embeddedartists	0:0fdadbc3d852	46	/**
embeddedartists	0:0fdadbc3d852	47	* @brief SDC Command Register bit definitions
embeddedartists	0:0fdadbc3d852	48	*/
embeddedartists	0:0fdadbc3d852	49	/** SDC Command Register Bitmask */
embeddedartists	0:0fdadbc3d852	50	#define SDC_COMMAND_BITMASK ((uint32_t) 0x7FF)
embeddedartists	0:0fdadbc3d852	51	/** SDC Command Index Bitmask */
embeddedartists	0:0fdadbc3d852	52	#define SDC_COMMAND_INDEX_BITMASK ((uint32_t) 0x3F)
embeddedartists	0:0fdadbc3d852	53	/** Set SDC Command Index */
embeddedartists	0:0fdadbc3d852	54	#define SDC_COMMAND_INDEX(n) ((uint32_t) n & 0x3F)
embeddedartists	0:0fdadbc3d852	55	/** No response is expected */
embeddedartists	0:0fdadbc3d852	56	#define SDC_COMMAND_NO_RSP (((uint32_t) 0 ) << 6)
embeddedartists	0:0fdadbc3d852	57	/** Short response is expected */
embeddedartists	0:0fdadbc3d852	58	#define SDC_COMMAND_SHORT_RSP (((uint32_t) 1 ) << 6)
embeddedartists	0:0fdadbc3d852	59	/** Long response is expected */
embeddedartists	0:0fdadbc3d852	60	#define SDC_COMMAND_LONG_RSP (((uint32_t) 3 ) << 6)
embeddedartists	0:0fdadbc3d852	61	/** Response bit mask */
embeddedartists	0:0fdadbc3d852	62	#define SDC_COMMAND_RSP_BITMASK (((uint32_t) 3 ) << 6)
embeddedartists	0:0fdadbc3d852	63	/** Mark that command timer is disabled and CPSM waits for interrupt request */
embeddedartists	0:0fdadbc3d852	64	#define SDC_COMMAND_INTERRUPT (((uint32_t) 1 ) << 8)
embeddedartists	0:0fdadbc3d852	65	/** Mark that CPSM waits for CmdPend before starting sending a command*/
embeddedartists	0:0fdadbc3d852	66	#define SDC_COMMAND_PENDING (((uint32_t) 1 ) << 9)
embeddedartists	0:0fdadbc3d852	67	/** Enable CPSM */
embeddedartists	0:0fdadbc3d852	68	#define SDC_COMMAND_ENABLE (((uint32_t) 1 ) << 10)
embeddedartists	0:0fdadbc3d852	69
embeddedartists	0:0fdadbc3d852	70	/**
embeddedartists	0:0fdadbc3d852	71	* @brief SDC Command Response Register bit definitions
embeddedartists	0:0fdadbc3d852	72	*/
embeddedartists	0:0fdadbc3d852	73	/** SDC Command Response value */
embeddedartists	0:0fdadbc3d852	74	#define SDC_RESPCOMMAND_VAL(n) ((uint32_t) n & 0x3F)
embeddedartists	0:0fdadbc3d852	75
embeddedartists	0:0fdadbc3d852	76	/*
embeddedartists	0:0fdadbc3d852	77	* SD/MMC Response type definitions
embeddedartists	0:0fdadbc3d852	78	*/
embeddedartists	0:0fdadbc3d852	79	#define CMDRESP_NONE_TYPE (SDC_COMMAND_NO_RSP)
embeddedartists	0:0fdadbc3d852	80	#define CMDRESP_R1_TYPE (SDC_COMMAND_SHORT_RSP)
embeddedartists	0:0fdadbc3d852	81	#define CMDRESP_R1b_TYPE (SDC_COMMAND_SHORT_RSP)
embeddedartists	0:0fdadbc3d852	82	#define CMDRESP_R2_TYPE (SDC_COMMAND_LONG_RSP)
embeddedartists	0:0fdadbc3d852	83	#define CMDRESP_R3_TYPE (SDC_COMMAND_SHORT_RSP)
embeddedartists	0:0fdadbc3d852	84	#define CMDRESP_R6_TYPE (SDC_COMMAND_SHORT_RSP)
embeddedartists	0:0fdadbc3d852	85	#define CMDRESP_R7_TYPE (SDC_COMMAND_SHORT_RSP)
embeddedartists	0:0fdadbc3d852	86
embeddedartists	0:0fdadbc3d852	87	/*
embeddedartists	0:0fdadbc3d852	88	* SD command values (Command Index, Response)
embeddedartists	0:0fdadbc3d852	89	*/
embeddedartists	0:0fdadbc3d852	90	#define SD_GO_IDLE_STATE (SDC_COMMAND_INDEX(MMC_GO_IDLE_STATE) \| CMDRESP_NONE_TYPE \| SDC_COMMAND_INTERRUPT) /!< GO_IDLE_STATE(MMC) or RESET(SD) /
embeddedartists	0:0fdadbc3d852	91	#define SD_CMD1_SEND_OP_COND (SDC_COMMAND_INDEX(MMC_SEND_OP_COND) \| CMDRESP_R3_TYPE \| 0) /!< SEND_OP_COND(MMC) or ACMD41(SD) /
embeddedartists	0:0fdadbc3d852	92	#define SD_CMD2_ALL_SEND_CID (SDC_COMMAND_INDEX(MMC_ALL_SEND_CID) \| CMDRESP_R2_TYPE \| 0) /!< ALL_SEND_CID /
embeddedartists	0:0fdadbc3d852	93	#define SD_CMD3_SET_RELATIVE_ADDR (SDC_COMMAND_INDEX(MMC_SET_RELATIVE_ADDR) \| CMDRESP_R1_TYPE \| 0) /!< SET_RELATE_ADDR /
embeddedartists	0:0fdadbc3d852	94	#define SD_CMD3_SEND_RELATIVE_ADDR (SDC_COMMAND_INDEX(SD_SEND_RELATIVE_ADDR) \| CMDRESP_R6_TYPE \| 0) /!< SEND_RELATE_ADDR /
embeddedartists	0:0fdadbc3d852	95	#define SD_CMD7_SELECT_CARD (SDC_COMMAND_INDEX(MMC_SELECT_CARD) \| CMDRESP_R1b_TYPE \| 0) /!< SELECT/DESELECT_CARD /
embeddedartists	0:0fdadbc3d852	96	#define SD_CMD8_SEND_IF_COND (SDC_COMMAND_INDEX(SD_CMD8) \| CMDRESP_R7_TYPE \| 0) /!< SEND_IF_COND /
embeddedartists	0:0fdadbc3d852	97	#define SD_CMD9_SEND_CSD (SDC_COMMAND_INDEX(MMC_SEND_CSD) \| CMDRESP_R2_TYPE \| 0) /!< SEND_CSD /
embeddedartists	0:0fdadbc3d852	98	#define SD_CMD12_STOP_TRANSMISSION (SDC_COMMAND_INDEX(MMC_STOP_TRANSMISSION) \| CMDRESP_R1_TYPE \| 0) /!< STOP_TRANSMISSION /
embeddedartists	0:0fdadbc3d852	99	#define SD_CMD13_SEND_STATUS (SDC_COMMAND_INDEX(MMC_SEND_STATUS) \| CMDRESP_R1_TYPE \| 0) /!< SEND_STATUS /
embeddedartists	0:0fdadbc3d852	100
embeddedartists	0:0fdadbc3d852	101	/* Block-Oriented Read Commands (class 2) */
embeddedartists	0:0fdadbc3d852	102	#define SD_CMD16_SET_BLOCKLEN (SDC_COMMAND_INDEX(MMC_SET_BLOCKLEN) \| CMDRESP_R1_TYPE \| 0) /!< SET_BLOCK_LEN /
embeddedartists	0:0fdadbc3d852	103	#define SD_CMD17_READ_SINGLE_BLOCK (SDC_COMMAND_INDEX(MMC_READ_SINGLE_BLOCK) \| CMDRESP_R1_TYPE \| 0) /!< READ_SINGLE_BLOCK /
embeddedartists	0:0fdadbc3d852	104	#define SD_CMD18_READ_MULTIPLE_BLOCK (SDC_COMMAND_INDEX(MMC_READ_MULTIPLE_BLOCK) \| CMDRESP_R1_TYPE \| 0) /!< READ_MULTIPLE_BLOCK /
embeddedartists	0:0fdadbc3d852	105
embeddedartists	0:0fdadbc3d852	106	/* Block-Oriented Write Commands (class 4) */
embeddedartists	0:0fdadbc3d852	107	#define SD_CMD24_WRITE_BLOCK (SDC_COMMAND_INDEX(MMC_WRITE_BLOCK) \| CMDRESP_R1_TYPE \| 0) /!< WRITE_BLOCK /
embeddedartists	0:0fdadbc3d852	108	#define SD_CMD25_WRITE_MULTIPLE_BLOCK (SDC_COMMAND_INDEX(MMC_WRITE_MULTIPLE_BLOCK) \| CMDRESP_R1_TYPE \| 0) /!< WRITE_MULTIPLE_BLOCK /
embeddedartists	0:0fdadbc3d852	109
embeddedartists	0:0fdadbc3d852	110	/* Erase Commands (class 5) */
embeddedartists	0:0fdadbc3d852	111	#define SD_CMD32_ERASE_WR_BLK_START (SDC_COMMAND_INDEX(SD_ERASE_WR_BLK_START) \| CMDRESP_R1_TYPE \| 0) /!< ERASE_WR_BLK_START /
embeddedartists	0:0fdadbc3d852	112	#define SD_CMD33_ERASE_WR_BLK_END (SDC_COMMAND_INDEX(SD_ERASE_WR_BLK_END) \| CMDRESP_R1_TYPE \| 0) /!< ERASE_WR_BLK_END /
embeddedartists	0:0fdadbc3d852	113	#define SD_CMD38_ERASE (SDC_COMMAND_INDEX(SD_ERASE) \| CMDRESP_R1b_TYPE \| 0) /!< ERASE /
embeddedartists	0:0fdadbc3d852	114
embeddedartists	0:0fdadbc3d852	115	/* Application-Specific Commands (class 8) */
embeddedartists	0:0fdadbc3d852	116	#define SD_CMD55_APP_CMD (SDC_COMMAND_INDEX(MMC_APP_CMD) \| CMDRESP_R1_TYPE \| 0) /!< APP_CMD /
embeddedartists	0:0fdadbc3d852	117	#define SD_ACMD6_SET_BUS_WIDTH (SDC_COMMAND_INDEX(SD_APP_SET_BUS_WIDTH) \| CMDRESP_R1_TYPE \| 0) /!< SET_BUS_WIDTH /
embeddedartists	0:0fdadbc3d852	118	#define SD_ACMD13_SEND_SD_STATUS (SDC_COMMAND_INDEX(MMC_SEND_STATUS) \| CMDRESP_R1_TYPE \| 0) /!< SEND_SD_STATUS /
embeddedartists	0:0fdadbc3d852	119	#define SD_ACMD41_SD_SEND_OP_COND (SDC_COMMAND_INDEX(SD_APP_OP_COND) \| CMDRESP_R3_TYPE \| 0) /!< SD_SEND_OP_COND /
embeddedartists	0:0fdadbc3d852	120
embeddedartists	0:0fdadbc3d852	121	/**
embeddedartists	0:0fdadbc3d852	122	* @brief SDC Interrupt Mask Register bit definitions
embeddedartists	0:0fdadbc3d852	123	*/
embeddedartists	0:0fdadbc3d852	124	/** Mask CmdCrcFail flag.*/
embeddedartists	0:0fdadbc3d852	125	#define SDC_MASK0_CMDCRCFAIL (((uint32_t) 1 ) << 0)
embeddedartists	0:0fdadbc3d852	126	/** Mask DataCrcFail flag. */
embeddedartists	0:0fdadbc3d852	127	#define SDC_MASK0_DATACRCFAIL (((uint32_t) 1 ) << 1)
embeddedartists	0:0fdadbc3d852	128	/** Mask CmdTimeOut flag. */
embeddedartists	0:0fdadbc3d852	129	#define SDC_MASK0_CMDTIMEOUT (((uint32_t) 1 ) << 2)
embeddedartists	0:0fdadbc3d852	130	/** Mask DataTimeOut flag. */
embeddedartists	0:0fdadbc3d852	131	#define SDC_MASK0_DATATIMEOUT (((uint32_t) 1 ) << 3)
embeddedartists	0:0fdadbc3d852	132	/** Mask TxUnderrun flag. */
embeddedartists	0:0fdadbc3d852	133	#define SDC_MASK0_TXUNDERRUN (((uint32_t) 1 ) << 4)
embeddedartists	0:0fdadbc3d852	134	/** Mask RxOverrun flag. */
embeddedartists	0:0fdadbc3d852	135	#define SDC_MASK0_RXOVERRUN (((uint32_t) 1 ) << 5)
embeddedartists	0:0fdadbc3d852	136	/** Mask CmdRespEnd flag. */
embeddedartists	0:0fdadbc3d852	137	#define SDC_MASK0_CMDRESPEND (((uint32_t) 1 ) << 6)
embeddedartists	0:0fdadbc3d852	138	/** Mask CmdSent flag.*/
embeddedartists	0:0fdadbc3d852	139	#define SDC_MASK0_CMDSENT (((uint32_t) 1 ) << 7)
embeddedartists	0:0fdadbc3d852	140	/** Mask DataEnd flag.*/
embeddedartists	0:0fdadbc3d852	141	#define SDC_MASK0_DATAEND (((uint32_t) 1 ) << 8)
embeddedartists	0:0fdadbc3d852	142	/** Mask StartBitErr flag.*/
embeddedartists	0:0fdadbc3d852	143	#define SDC_MASK0_STARTBITERR (((uint32_t) 1 ) << 9)
embeddedartists	0:0fdadbc3d852	144	/** Mask DataBlockEnd flag.*/
embeddedartists	0:0fdadbc3d852	145	#define SDC_MASK0_DATABLOCKEND (((uint32_t) 1 ) << 10)
embeddedartists	0:0fdadbc3d852	146	/** Mask CmdActive flag.*/
embeddedartists	0:0fdadbc3d852	147	#define SDC_MASK0_CMDACTIVE (((uint32_t) 1 ) << 11)
embeddedartists	0:0fdadbc3d852	148	/** Mask TxActive flag.*/
embeddedartists	0:0fdadbc3d852	149	#define SDC_MASK0_TXACTIVE (((uint32_t) 1 ) << 12)
embeddedartists	0:0fdadbc3d852	150	/** Mask RxActive flag.*/
embeddedartists	0:0fdadbc3d852	151	#define SDC_MASK0_RXACTIVE (((uint32_t) 1 ) << 13)
embeddedartists	0:0fdadbc3d852	152	/** Mask TxFifoHalfEmpty flag.*/
embeddedartists	0:0fdadbc3d852	153	#define SDC_MASK0_TXFIFOHALFEMPTY (((uint32_t) 1 ) << 14)
embeddedartists	0:0fdadbc3d852	154	/** Mask RxFifoHalfFull flag.*/
embeddedartists	0:0fdadbc3d852	155	#define SDC_MASK0_RXFIFOHALFFULL (((uint32_t) 1 ) << 15)
embeddedartists	0:0fdadbc3d852	156	/** Mask TxFifoFull flag.*/
embeddedartists	0:0fdadbc3d852	157	#define SDC_MASK0_TXFIFOFULL (((uint32_t) 1 ) << 16)
embeddedartists	0:0fdadbc3d852	158	/** Mask RxFifoFull flag.*/
embeddedartists	0:0fdadbc3d852	159	#define SDC_MASK0_RXFIFOFULL (((uint32_t) 1 ) << 17)
embeddedartists	0:0fdadbc3d852	160	/** Mask TxFifoEmpty flag.*/
embeddedartists	0:0fdadbc3d852	161	#define SDC_MASK0_TXFIFOEMPTY (((uint32_t) 1 ) << 18)
embeddedartists	0:0fdadbc3d852	162	/** Mask RxFifoEmpty flag.*/
embeddedartists	0:0fdadbc3d852	163	#define SDC_MASK0_RXFIFOEMPTY (((uint32_t) 1 ) << 19)
embeddedartists	0:0fdadbc3d852	164	/** Mask TxDataAvlbl flag.*/
embeddedartists	0:0fdadbc3d852	165	#define SDC_MASK0_TXDATAAVLBL (((uint32_t) 1 ) << 20)
embeddedartists	0:0fdadbc3d852	166	/** Mask RxDataAvlbl flag.*/
embeddedartists	0:0fdadbc3d852	167	#define SDC_MASK0_RXDATAAVLBL (((uint32_t) 1 ) << 21)
embeddedartists	0:0fdadbc3d852	168	/** CMD error interrupt mask */
embeddedartists	0:0fdadbc3d852	169	#define SDC_MASK0_CMDERR (SDC_MASK0_CMDCRCFAIL \| SDC_MASK0_CMDTIMEOUT \| SDC_MASK0_STARTBITERR)
embeddedartists	0:0fdadbc3d852	170	/** Data Transmit Error interrupt mask */
embeddedartists	0:0fdadbc3d852	171	#define SDC_MASK0_TXDATAERR (SDC_MASK0_DATACRCFAIL \| SDC_MASK0_DATATIMEOUT \| SDC_MASK0_TXUNDERRUN \| SDC_MASK0_STARTBITERR)
embeddedartists	0:0fdadbc3d852	172	/** Data Receive Error interrupt mask */
embeddedartists	0:0fdadbc3d852	173	#define SDC_MASK0_RXDATAERR (SDC_MASK0_DATACRCFAIL \| SDC_MASK0_DATATIMEOUT \| SDC_MASK0_RXOVERRUN \| SDC_MASK0_STARTBITERR)
embeddedartists	0:0fdadbc3d852	174	/** Data Transfer interrupt mask*/
embeddedartists	0:0fdadbc3d852	175	#define SDC_MASK0_DATA (SDC_MASK0_DATAEND \| SDC_MASK0_DATABLOCKEND )
embeddedartists	0:0fdadbc3d852	176
embeddedartists	0:0fdadbc3d852	177	/**
embeddedartists	0:0fdadbc3d852	178	* @brief SDC Clock Control Register bit definitions
embeddedartists	0:0fdadbc3d852	179	*/
embeddedartists	0:0fdadbc3d852	180	/** SDC Clock Control Register Bitmask */
embeddedartists	0:0fdadbc3d852	181	#define SDC_CLOCK_BITMASK ((uint32_t) 0xFFF)
embeddedartists	0:0fdadbc3d852	182	/** SDC Clock Divider Bitmask */
embeddedartists	0:0fdadbc3d852	183	#define SDC_CLOCK_CLKDIV_BITMASK (((uint32_t) 0xFF ) << 0)
embeddedartists	0:0fdadbc3d852	184	/** Set SDC Clock Divide value */
embeddedartists	0:0fdadbc3d852	185	#define SDC_CLOCK_CLKDIV(n) (((uint32_t) (n & 0x0FF)) << 0)
embeddedartists	0:0fdadbc3d852	186
embeddedartists	0:0fdadbc3d852	187	/**
embeddedartists	0:0fdadbc3d852	188	* @brief SDC Status Register bit definitions
embeddedartists	0:0fdadbc3d852	189	*/
embeddedartists	0:0fdadbc3d852	190	/** Command Response received (CRC check failed) */
embeddedartists	0:0fdadbc3d852	191	#define SDC_STATUS_CMDCRCFAIL (((uint32_t) 1 ) << 0)
embeddedartists	0:0fdadbc3d852	192	/** Data block sent/received (CRC check failed). */
embeddedartists	0:0fdadbc3d852	193	#define SDC_STATUS_DATACRCFAIL (((uint32_t) 1 ) << 1)
embeddedartists	0:0fdadbc3d852	194	/** Command response timeout.. */
embeddedartists	0:0fdadbc3d852	195	#define SDC_STATUS_CMDTIMEOUT (((uint32_t) 1 ) << 2)
embeddedartists	0:0fdadbc3d852	196	/** Data timeout. */
embeddedartists	0:0fdadbc3d852	197	#define SDC_STATUS_DATATIMEOUT (((uint32_t) 1 ) << 3)
embeddedartists	0:0fdadbc3d852	198	/** Transmit FIFO underrun error. */
embeddedartists	0:0fdadbc3d852	199	#define SDC_STATUS_TXUNDERRUN (((uint32_t) 1 ) << 4)
embeddedartists	0:0fdadbc3d852	200	/** Receive FIFO overrun error. */
embeddedartists	0:0fdadbc3d852	201	#define SDC_STATUS_RXOVERRUN (((uint32_t) 1 ) << 5)
embeddedartists	0:0fdadbc3d852	202	/** Command response received (CRC check passed). */
embeddedartists	0:0fdadbc3d852	203	#define SDC_STATUS_CMDRESPEND (((uint32_t) 1 ) << 6)
embeddedartists	0:0fdadbc3d852	204	/** Command sent (no response required).*/
embeddedartists	0:0fdadbc3d852	205	#define SDC_STATUS_CMDSENT (((uint32_t) 1 ) << 7)
embeddedartists	0:0fdadbc3d852	206	/** Data end (data counter is zero).*/
embeddedartists	0:0fdadbc3d852	207	#define SDC_STATUS_DATAEND (((uint32_t) 1 ) << 8)
embeddedartists	0:0fdadbc3d852	208	/** Start bit not detected on all data signals in wide bus mode..*/
embeddedartists	0:0fdadbc3d852	209	#define SDC_STATUS_STARTBITERR (((uint32_t) 1 ) << 9)
embeddedartists	0:0fdadbc3d852	210	/** Data block sent/received (CRC check passed).*/
embeddedartists	0:0fdadbc3d852	211	#define SDC_STATUS_DATABLOCKEND (((uint32_t) 1 ) << 10)
embeddedartists	0:0fdadbc3d852	212	/** Command transfer in progress.*/
embeddedartists	0:0fdadbc3d852	213	#define SDC_STATUS_CMDACTIVE (((uint32_t) 1 ) << 11)
embeddedartists	0:0fdadbc3d852	214	/** Data transmit in progress.*/
embeddedartists	0:0fdadbc3d852	215	#define SDC_STATUS_TXACTIVE (((uint32_t) 1 ) << 12)
embeddedartists	0:0fdadbc3d852	216	/** Data receive in progress.*/
embeddedartists	0:0fdadbc3d852	217	#define SDC_STATUS_RXACTIVE (((uint32_t) 1 ) << 13)
embeddedartists	0:0fdadbc3d852	218	/** Transmit FIFO half empty.*/
embeddedartists	0:0fdadbc3d852	219	#define SDC_STATUS_TXFIFOHALFEMPTY (((uint32_t) 1 ) << 14)
embeddedartists	0:0fdadbc3d852	220	/** Receive FIFO half full.*/
embeddedartists	0:0fdadbc3d852	221	#define SDC_STATUS_RXFIFOHALFFULL (((uint32_t) 1 ) << 15)
embeddedartists	0:0fdadbc3d852	222	/** Transmit FIFO full.*/
embeddedartists	0:0fdadbc3d852	223	#define SDC_STATUS_TXFIFOFULL (((uint32_t) 1 ) << 16)
embeddedartists	0:0fdadbc3d852	224	/** Receive FIFO full.*/
embeddedartists	0:0fdadbc3d852	225	#define SDC_STATUS_RXFIFOFULL (((uint32_t) 1 ) << 17)
embeddedartists	0:0fdadbc3d852	226	/** Transmit FIFO empty.*/
embeddedartists	0:0fdadbc3d852	227	#define SDC_STATUS_TXFIFOEMPTY (((uint32_t) 1 ) << 18)
embeddedartists	0:0fdadbc3d852	228	/** Receive FIFO empty.*/
embeddedartists	0:0fdadbc3d852	229	#define SDC_STATUS_RXFIFOEMPTY (((uint32_t) 1 ) << 19)
embeddedartists	0:0fdadbc3d852	230	/** Data available in transmit FIFO.*/
embeddedartists	0:0fdadbc3d852	231	#define SDC_STATUS_TXDATAAVLBL (((uint32_t) 1 ) << 20)
embeddedartists	0:0fdadbc3d852	232	/** Data available in receive FIFO.*/
embeddedartists	0:0fdadbc3d852	233	#define SDC_STATUS_RXDATAAVLBL (((uint32_t) 1 ) << 21)
embeddedartists	0:0fdadbc3d852	234	/** Command Error Status */
embeddedartists	0:0fdadbc3d852	235	#define SDC_STATUS_CMDERR (SDC_STATUS_CMDCRCFAIL \| SDC_STATUS_CMDTIMEOUT \| SDC_STATUS_STARTBITERR)
embeddedartists	0:0fdadbc3d852	236	/** Data Error Status */
embeddedartists	0:0fdadbc3d852	237	#define SDC_STATUS_DATAERR (SDC_STATUS_DATACRCFAIL \| SDC_STATUS_DATATIMEOUT \| SDC_STATUS_TXUNDERRUN \
embeddedartists	0:0fdadbc3d852	238	\| SDC_STATUS_RXOVERRUN \| SDC_STATUS_STARTBITERR)
embeddedartists	0:0fdadbc3d852	239	/** FIFO Status*/
embeddedartists	0:0fdadbc3d852	240	#define SDC_STATUS_FIFO (SDC_STATUS_TXFIFOHALFEMPTY \| SDC_STATUS_RXFIFOHALFFULL \
embeddedartists	0:0fdadbc3d852	241	\| SDC_STATUS_TXFIFOFULL \| SDC_STATUS_RXFIFOFULL \
embeddedartists	0:0fdadbc3d852	242	\| SDC_STATUS_TXFIFOEMPTY \| SDC_STATUS_RXFIFOEMPTY \
embeddedartists	0:0fdadbc3d852	243	\| SDC_STATUS_DATABLOCKEND)
embeddedartists	0:0fdadbc3d852	244
embeddedartists	0:0fdadbc3d852	245	/** Data Transfer Status*/
embeddedartists	0:0fdadbc3d852	246	#define SDC_STATUS_DATA (SDC_STATUS_DATAEND )
embeddedartists	0:0fdadbc3d852	247
embeddedartists	0:0fdadbc3d852	248	/**
embeddedartists	0:0fdadbc3d852	249	* @brief SDC Data Control Register bit definitions
embeddedartists	0:0fdadbc3d852	250	*/
embeddedartists	0:0fdadbc3d852	251	/** SDC Data Control Register Bitmask */
embeddedartists	0:0fdadbc3d852	252	#define SDC_DATACTRL_BITMASK ((uint32_t) 0xFF)
embeddedartists	0:0fdadbc3d852	253	/** Enable Data Transfer */
embeddedartists	0:0fdadbc3d852	254	#define SDC_DATACTRL_ENABLE (((uint32_t) 1 ) << 0)
embeddedartists	0:0fdadbc3d852	255	/** Mark that Data is transfer from card to controller */
embeddedartists	0:0fdadbc3d852	256	#define SDC_DATACTRL_DIR_FROMCARD (((uint32_t) 1 ) << 1)
embeddedartists	0:0fdadbc3d852	257	/** Mark that Data is transfer from controller to card */
embeddedartists	0:0fdadbc3d852	258	#define SDC_DATACTRL_DIR_TOCARD ((uint32_t) 0)
embeddedartists	0:0fdadbc3d852	259	/** Mark that the transfer mode is Stream Data Transfer */
embeddedartists	0:0fdadbc3d852	260	#define SDC_DATACTRL_XFER_MODE_STREAM (((uint32_t) 1 ) << 2)
embeddedartists	0:0fdadbc3d852	261	/** Mark that the transfer mode is Block Data Transfer */
embeddedartists	0:0fdadbc3d852	262	#define SDC_DATACTRL_XFER_MODE_BLOCK ((uint32_t) 0)
embeddedartists	0:0fdadbc3d852	263	/** Enable DMA */
embeddedartists	0:0fdadbc3d852	264	#define SDC_DATACTRL_DMA_ENABLE (((uint32_t) 1 ) << 3)
embeddedartists	0:0fdadbc3d852	265	/** Set Data Block size */
embeddedartists	0:0fdadbc3d852	266	#define SDC_DATACTRL_BLOCKSIZE(n) (((uint32_t) (n & 0x0F) ) << 4)
embeddedartists	0:0fdadbc3d852	267	/** Get Data Block size value */
embeddedartists	0:0fdadbc3d852	268	#define SDC_DATACTRL_BLOCKSIZE_VAL(n) (((uint32_t) 1) << n)
embeddedartists	0:0fdadbc3d852	269
embeddedartists	0:0fdadbc3d852	270	/**
embeddedartists	0:0fdadbc3d852	271	* @brief OCR Register definitions
embeddedartists	0:0fdadbc3d852	272	*/
embeddedartists	0:0fdadbc3d852	273	/** Support voltage range 2.7-3.6 */
embeddedartists	0:0fdadbc3d852	274	#define SDC_OCR_27_36 ((uint32_t) 0x00FF8000)
embeddedartists	0:0fdadbc3d852	275	/** Card power up status bit */
embeddedartists	0:0fdadbc3d852	276	#define SDC_OCR_IDLE (((uint32_t) 1) << 31)
embeddedartists	0:0fdadbc3d852	277	#define SDC_OCR_BUSY (((uint32_t) 0) << 31)
embeddedartists	0:0fdadbc3d852	278
embeddedartists	0:0fdadbc3d852	279
embeddedartists	0:0fdadbc3d852	280	/* SD/MMC commands - this matrix shows the command, response types, and
embeddedartists	0:0fdadbc3d852	281	supported card type for that command.
embeddedartists	0:0fdadbc3d852	282	Command Number Resp SD MMC
embeddedartists	0:0fdadbc3d852	283	----------------------- ------ ----- --- ---
embeddedartists	0:0fdadbc3d852	284	Reset (go idle) CMD0 NA x x
embeddedartists	0:0fdadbc3d852	285	Send op condition CMD1 R3 x
embeddedartists	0:0fdadbc3d852	286	All send CID CMD2 R2 x x
embeddedartists	0:0fdadbc3d852	287	Send relative address CMD3 R1 x
embeddedartists	0:0fdadbc3d852	288	Send relative address CMD3 R6 x
embeddedartists	0:0fdadbc3d852	289	Program DSR CMD4 NA x
embeddedartists	0:0fdadbc3d852	290	Select/deselect card CMD7 R1b x
embeddedartists	0:0fdadbc3d852	291	Select/deselect card CMD7 R1 x
embeddedartists	0:0fdadbc3d852	292	Send CSD CMD9 R2 x x
embeddedartists	0:0fdadbc3d852	293	Send CID CMD10 R2 x x
embeddedartists	0:0fdadbc3d852	294	Read data until stop CMD11 R1 x x
embeddedartists	0:0fdadbc3d852	295	Stop transmission CMD12 R1/b x x
embeddedartists	0:0fdadbc3d852	296	Send status CMD13 R1 x x
embeddedartists	0:0fdadbc3d852	297	Go inactive state CMD15 NA x x
embeddedartists	0:0fdadbc3d852	298	Set block length CMD16 R1 x x
embeddedartists	0:0fdadbc3d852	299	Read single block CMD17 R1 x x
embeddedartists	0:0fdadbc3d852	300	Read multiple blocks CMD18 R1 x x
embeddedartists	0:0fdadbc3d852	301	Write data until stop CMD20 R1 x
embeddedartists	0:0fdadbc3d852	302	Setblock count CMD23 R1 x
embeddedartists	0:0fdadbc3d852	303	Write single block CMD24 R1 x x
embeddedartists	0:0fdadbc3d852	304	Write multiple blocks CMD25 R1 x x
embeddedartists	0:0fdadbc3d852	305	Program CID CMD26 R1 x
embeddedartists	0:0fdadbc3d852	306	Program CSD CMD27 R1 x x
embeddedartists	0:0fdadbc3d852	307	Set write protection CMD28 R1b x x
embeddedartists	0:0fdadbc3d852	308	Clear write protection CMD29 R1b x x
embeddedartists	0:0fdadbc3d852	309	Send write protection CMD30 R1 x x
embeddedartists	0:0fdadbc3d852	310	Erase block start CMD32 R1 x
embeddedartists	0:0fdadbc3d852	311	Erase block end CMD33 R1 x
embeddedartists	0:0fdadbc3d852	312	Erase block start CMD35 R1 x
embeddedartists	0:0fdadbc3d852	313	Erase block end CMD36 R1 x
embeddedartists	0:0fdadbc3d852	314	Erase blocks CMD38 R1b x
embeddedartists	0:0fdadbc3d852	315	Fast IO CMD39 R4 x
embeddedartists	0:0fdadbc3d852	316	Go IRQ state CMD40 R5 x
embeddedartists	0:0fdadbc3d852	317	Lock/unlock CMD42 R1b x
embeddedartists	0:0fdadbc3d852	318	Application command CMD55 R1 x
embeddedartists	0:0fdadbc3d852	319	General command CMD56 R1b x
embeddedartists	0:0fdadbc3d852	320
embeddedartists	0:0fdadbc3d852	321	* SD card application commands - these must be preceded with *
embeddedartists	0:0fdadbc3d852	322	* MMC CMD55 application specific command first *
embeddedartists	0:0fdadbc3d852	323	Set bus width ACMD6 R1 x
embeddedartists	0:0fdadbc3d852	324	Send SD status ACMD13 R1 x
embeddedartists	0:0fdadbc3d852	325	Send number WR blocks ACMD22 R1 x
embeddedartists	0:0fdadbc3d852	326	Set WR block erase cnt ACMD23 R1 x
embeddedartists	0:0fdadbc3d852	327	Send op condition ACMD41 R3 x
embeddedartists	0:0fdadbc3d852	328	Set clear card detect ACMD42 R1 x
embeddedartists	0:0fdadbc3d852	329	Send CSR ACMD51 R1 x */
embeddedartists	0:0fdadbc3d852	330
embeddedartists	0:0fdadbc3d852	331	/**
embeddedartists	0:0fdadbc3d852	332	* @brief Possible SDMMC card state types
embeddedartists	0:0fdadbc3d852	333	*/
embeddedartists	0:0fdadbc3d852	334	typedef enum {
embeddedartists	0:0fdadbc3d852	335	SDMMC_IDLE_ST = 0, /!< Idle state /
embeddedartists	0:0fdadbc3d852	336	SDMMC_READY_ST, /!< Ready state /
embeddedartists	0:0fdadbc3d852	337	SDMMC_IDENT_ST, /!< Identification State /
embeddedartists	0:0fdadbc3d852	338	SDMMC_STBY_ST, /!< standby state /
embeddedartists	0:0fdadbc3d852	339	SDMMC_TRAN_ST, /!< transfer state /
embeddedartists	0:0fdadbc3d852	340	SDMMC_DATA_ST, /!< Sending-data State /
embeddedartists	0:0fdadbc3d852	341	SDMMC_RCV_ST, /!< Receive-data State /
embeddedartists	0:0fdadbc3d852	342	SDMMC_PRG_ST, /!< Programming State /
embeddedartists	0:0fdadbc3d852	343	SDMMC_DIS_ST /!< Disconnect State /
embeddedartists	0:0fdadbc3d852	344	} SDMMC_STATE_T;
embeddedartists	0:0fdadbc3d852	345
embeddedartists	0:0fdadbc3d852	346
embeddedartists	0:0fdadbc3d852	347	/**
embeddedartists	0:0fdadbc3d852	348	* @brief SD/MMC commands, arguments and responses
embeddedartists	0:0fdadbc3d852	349	* Standard SD/MMC commands (3.1) type argument response
embeddedartists	0:0fdadbc3d852	350	*/
embeddedartists	0:0fdadbc3d852	351	/* class 1 */
embeddedartists	0:0fdadbc3d852	352	#define MMC_GO_IDLE_STATE 0 /* bc */
embeddedartists	0:0fdadbc3d852	353	#define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */
embeddedartists	0:0fdadbc3d852	354	#define MMC_ALL_SEND_CID 2 /* bcr R2 */
embeddedartists	0:0fdadbc3d852	355	#define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */
embeddedartists	0:0fdadbc3d852	356	#define MMC_SET_DSR 4 /* bc [31:16] RCA */
embeddedartists	0:0fdadbc3d852	357	#define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */
embeddedartists	0:0fdadbc3d852	358	#define MMC_SEND_EXT_CSD 8 /* bc R1 */
embeddedartists	0:0fdadbc3d852	359	#define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */
embeddedartists	0:0fdadbc3d852	360	#define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */
embeddedartists	0:0fdadbc3d852	361	#define MMC_STOP_TRANSMISSION 12 /* ac R1b */
embeddedartists	0:0fdadbc3d852	362	#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */
embeddedartists	0:0fdadbc3d852	363	#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
embeddedartists	0:0fdadbc3d852	364
embeddedartists	0:0fdadbc3d852	365	/* class 2 */
embeddedartists	0:0fdadbc3d852	366	#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
embeddedartists	0:0fdadbc3d852	367	#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
embeddedartists	0:0fdadbc3d852	368	#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
embeddedartists	0:0fdadbc3d852	369
embeddedartists	0:0fdadbc3d852	370	/* class 3 */
embeddedartists	0:0fdadbc3d852	371	#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
embeddedartists	0:0fdadbc3d852	372
embeddedartists	0:0fdadbc3d852	373	/* class 4 */
embeddedartists	0:0fdadbc3d852	374	#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */
embeddedartists	0:0fdadbc3d852	375	#define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */
embeddedartists	0:0fdadbc3d852	376	#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */
embeddedartists	0:0fdadbc3d852	377	#define MMC_PROGRAM_CID 26 /* adtc R1 */
embeddedartists	0:0fdadbc3d852	378	#define MMC_PROGRAM_CSD 27 /* adtc R1 */
embeddedartists	0:0fdadbc3d852	379
embeddedartists	0:0fdadbc3d852	380	/* class 6 */
embeddedartists	0:0fdadbc3d852	381	#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */
embeddedartists	0:0fdadbc3d852	382	#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */
embeddedartists	0:0fdadbc3d852	383	#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */
embeddedartists	0:0fdadbc3d852	384
embeddedartists	0:0fdadbc3d852	385	/* class 5 */
embeddedartists	0:0fdadbc3d852	386	#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
embeddedartists	0:0fdadbc3d852	387	#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */
embeddedartists	0:0fdadbc3d852	388	#define MMC_ERASE 37 /* ac R1b */
embeddedartists	0:0fdadbc3d852	389	#define SD_ERASE_WR_BLK_START 32 /* ac [31:0] data addr R1 */
embeddedartists	0:0fdadbc3d852	390	#define SD_ERASE_WR_BLK_END 33 /* ac [31:0] data addr R1 */
embeddedartists	0:0fdadbc3d852	391	#define SD_ERASE 38 /* ac R1b */
embeddedartists	0:0fdadbc3d852	392
embeddedartists	0:0fdadbc3d852	393	/* class 9 */
embeddedartists	0:0fdadbc3d852	394	#define MMC_FAST_IO 39 /* ac <Complex> R4 */
embeddedartists	0:0fdadbc3d852	395	#define MMC_GO_IRQ_STATE 40 /* bcr R5 */
embeddedartists	0:0fdadbc3d852	396
embeddedartists	0:0fdadbc3d852	397	/* class 7 */
embeddedartists	0:0fdadbc3d852	398	#define MMC_LOCK_UNLOCK 42 /* adtc R1b */
embeddedartists	0:0fdadbc3d852	399
embeddedartists	0:0fdadbc3d852	400	/* class 8 */
embeddedartists	0:0fdadbc3d852	401	#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */
embeddedartists	0:0fdadbc3d852	402	#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1b */
embeddedartists	0:0fdadbc3d852	403
embeddedartists	0:0fdadbc3d852	404	/* SD commands type argument response */
embeddedartists	0:0fdadbc3d852	405	/* class 8 */
embeddedartists	0:0fdadbc3d852	406	/* This is basically the same command as for MMC with some quirks. */
embeddedartists	0:0fdadbc3d852	407	#define SD_SEND_RELATIVE_ADDR 3 /* ac R6 */
embeddedartists	0:0fdadbc3d852	408	#define SD_CMD8 8 /* bcr [31:0] OCR R3 */
embeddedartists	0:0fdadbc3d852	409
embeddedartists	0:0fdadbc3d852	410	/* Application commands */
embeddedartists	0:0fdadbc3d852	411	#define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */
embeddedartists	0:0fdadbc3d852	412	#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R1 (R4) */
embeddedartists	0:0fdadbc3d852	413	#define SD_APP_SEND_SCR 51 /* adtc R1 */
embeddedartists	0:0fdadbc3d852	414
embeddedartists	0:0fdadbc3d852	415
embeddedartists	0:0fdadbc3d852	416	/**
embeddedartists	0:0fdadbc3d852	417	* @brief MMC status in R1<br>
embeddedartists	0:0fdadbc3d852	418	* Type<br>
embeddedartists	0:0fdadbc3d852	419	* e : error bit<br>
embeddedartists	0:0fdadbc3d852	420	* s : status bit<br>
embeddedartists	0:0fdadbc3d852	421	* r : detected and set for the actual command response<br>
embeddedartists	0:0fdadbc3d852	422	* x : detected and set during command execution. the host must poll
embeddedartists	0:0fdadbc3d852	423	* the card by sending status command in order to read these bits.
embeddedartists	0:0fdadbc3d852	424	* Clear condition<br>
embeddedartists	0:0fdadbc3d852	425	* a : according to the card state<br>
embeddedartists	0:0fdadbc3d852	426	* b : always related to the previous command. Reception of
embeddedartists	0:0fdadbc3d852	427	* a valid command will clear it (with a delay of one command)<br>
embeddedartists	0:0fdadbc3d852	428	* c : clear by read<br>
embeddedartists	0:0fdadbc3d852	429	*/
embeddedartists	0:0fdadbc3d852	430
embeddedartists	0:0fdadbc3d852	431	#define R1_OUT_OF_RANGE (1UL << 31) /* er, c */
embeddedartists	0:0fdadbc3d852	432	#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
embeddedartists	0:0fdadbc3d852	433	#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
embeddedartists	0:0fdadbc3d852	434	#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
embeddedartists	0:0fdadbc3d852	435	#define R1_ERASE_PARAM (1 << 27) /* ex, c */
embeddedartists	0:0fdadbc3d852	436	#define R1_WP_VIOLATION (1 << 26) /* erx, c */
embeddedartists	0:0fdadbc3d852	437	#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
embeddedartists	0:0fdadbc3d852	438	#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
embeddedartists	0:0fdadbc3d852	439	#define R1_COM_CRC_ERROR (1 << 23) /* er, b */
embeddedartists	0:0fdadbc3d852	440	#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
embeddedartists	0:0fdadbc3d852	441	#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
embeddedartists	0:0fdadbc3d852	442	#define R1_CC_ERROR (1 << 20) /* erx, c */
embeddedartists	0:0fdadbc3d852	443	#define R1_ERROR (1 << 19) /* erx, c */
embeddedartists	0:0fdadbc3d852	444	#define R1_UNDERRUN (1 << 18) /* ex, c */
embeddedartists	0:0fdadbc3d852	445	#define R1_OVERRUN (1 << 17) /* ex, c */
embeddedartists	0:0fdadbc3d852	446	#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
embeddedartists	0:0fdadbc3d852	447	#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
embeddedartists	0:0fdadbc3d852	448	#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
embeddedartists	0:0fdadbc3d852	449	#define R1_ERASE_RESET (1 << 13) /* sr, c */
embeddedartists	0:0fdadbc3d852	450	#define R1_STATUS(x) (x & 0xFFFFE000)
embeddedartists	0:0fdadbc3d852	451	#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
embeddedartists	0:0fdadbc3d852	452	#define R1_READY_FOR_DATA (1 << 8) /* sx, a */
embeddedartists	0:0fdadbc3d852	453	#define R1_APP_CMD (1 << 5) /* sr, c */
embeddedartists	0:0fdadbc3d852	454
embeddedartists	0:0fdadbc3d852	455
embeddedartists	0:0fdadbc3d852	456	/**
embeddedartists	0:0fdadbc3d852	457	* @brief SD/MMC card OCR register bits
embeddedartists	0:0fdadbc3d852	458	*/
embeddedartists	0:0fdadbc3d852	459	#define OCR_ALL_READY (1UL << 31) /* Card Power up status bit */
embeddedartists	0:0fdadbc3d852	460	#define OCR_HC_CCS (1 << 30) /* High capacity card */
embeddedartists	0:0fdadbc3d852	461	#define OCR_VOLTAGE_RANGE_MSK (0x00FF8000)
embeddedartists	0:0fdadbc3d852	462
embeddedartists	0:0fdadbc3d852	463	#define SD_SEND_IF_ARG 0x000001AA
embeddedartists	0:0fdadbc3d852	464	#define SD_SEND_IF_ECHO_MSK 0x000000FF
embeddedartists	0:0fdadbc3d852	465	#define SD_SEND_IF_RESP 0x000000AA
embeddedartists	0:0fdadbc3d852	466
embeddedartists	0:0fdadbc3d852	467	/**
embeddedartists	0:0fdadbc3d852	468	* @brief R3 response definitions
embeddedartists	0:0fdadbc3d852	469	*/
embeddedartists	0:0fdadbc3d852	470	#define CMDRESP_R3_OCR_VAL(n) (((uint32_t) n) & 0xFFFFFF)
embeddedartists	0:0fdadbc3d852	471	#define CMDRESP_R3_S18A (((uint32_t) 1 ) << 24)
embeddedartists	0:0fdadbc3d852	472	#define CMDRESP_R3_HC_CCS (((uint32_t) 1 ) << 30)
embeddedartists	0:0fdadbc3d852	473	#define CMDRESP_R3_INIT_COMPLETE (((uint32_t) 1 ) << 31)
embeddedartists	0:0fdadbc3d852	474
embeddedartists	0:0fdadbc3d852	475	/**
embeddedartists	0:0fdadbc3d852	476	* @brief R6 response definitions
embeddedartists	0:0fdadbc3d852	477	*/
embeddedartists	0:0fdadbc3d852	478	#define CMDRESP_R6_RCA_VAL(n) (((uint32_t) (n >> 16)) & 0xFFFF)
embeddedartists	0:0fdadbc3d852	479	#define CMDRESP_R6_CARD_STATUS(n) (((uint32_t) (n & 0x1FFF)) \| \
embeddedartists	0:0fdadbc3d852	480	((n & (1 << 13)) ? (1 << 19) : 0) \| \
embeddedartists	0:0fdadbc3d852	481	((n & (1 << 14)) ? (1 << 22) : 0) \| \
embeddedartists	0:0fdadbc3d852	482	((n & (1 << 15)) ? (1 << 23) : 0))
embeddedartists	0:0fdadbc3d852	483
embeddedartists	0:0fdadbc3d852	484	/**
embeddedartists	0:0fdadbc3d852	485	* @brief R7 response definitions
embeddedartists	0:0fdadbc3d852	486	*/
embeddedartists	0:0fdadbc3d852	487	/** Echo-back of check-pattern */
embeddedartists	0:0fdadbc3d852	488	#define CMDRESP_R7_CHECK_PATTERN(n) (((uint32_t) n ) & 0xFF)
embeddedartists	0:0fdadbc3d852	489	/** Voltage accepted */
embeddedartists	0:0fdadbc3d852	490	#define CMDRESP_R7_VOLTAGE_ACCEPTED (((uint32_t) 1 ) << 8)
embeddedartists	0:0fdadbc3d852	491
embeddedartists	0:0fdadbc3d852	492	/**
embeddedartists	0:0fdadbc3d852	493	* @brief CMD3 command definitions
embeddedartists	0:0fdadbc3d852	494	*/
embeddedartists	0:0fdadbc3d852	495	/** Card Address */
embeddedartists	0:0fdadbc3d852	496	#define CMD3_RCA(n) (((uint32_t) (n & 0xFFFF) ) << 16)
embeddedartists	0:0fdadbc3d852	497
embeddedartists	0:0fdadbc3d852	498	/**
embeddedartists	0:0fdadbc3d852	499	* @brief CMD7 command definitions
embeddedartists	0:0fdadbc3d852	500	*/
embeddedartists	0:0fdadbc3d852	501	/** Card Address */
embeddedartists	0:0fdadbc3d852	502	#define CMD7_RCA(n) (((uint32_t) (n & 0xFFFF) ) << 16)
embeddedartists	0:0fdadbc3d852	503
embeddedartists	0:0fdadbc3d852	504	/**
embeddedartists	0:0fdadbc3d852	505	* @brief CMD8 command definitions
embeddedartists	0:0fdadbc3d852	506	*/
embeddedartists	0:0fdadbc3d852	507	/** Check pattern */
embeddedartists	0:0fdadbc3d852	508	#define CMD8_CHECKPATTERN(n) (((uint32_t) (n & 0xFF) ) << 0)
embeddedartists	0:0fdadbc3d852	509	/** Recommended pattern */
embeddedartists	0:0fdadbc3d852	510	#define CMD8_DEF_PATTERN (0xAA)
embeddedartists	0:0fdadbc3d852	511	/** Voltage supplied.*/
embeddedartists	0:0fdadbc3d852	512	#define CMD8_VOLTAGESUPPLIED_27_36 (((uint32_t) 1 ) << 8)
embeddedartists	0:0fdadbc3d852	513
embeddedartists	0:0fdadbc3d852	514	/**
embeddedartists	0:0fdadbc3d852	515	* @brief CMD9 command definitions
embeddedartists	0:0fdadbc3d852	516	*/
embeddedartists	0:0fdadbc3d852	517	#define CMD9_RCA(n) (((uint32_t) (n & 0xFFFF) ) << 16)
embeddedartists	0:0fdadbc3d852	518
embeddedartists	0:0fdadbc3d852	519	/**
embeddedartists	0:0fdadbc3d852	520	* @brief CMD13 command definitions
embeddedartists	0:0fdadbc3d852	521	*/
embeddedartists	0:0fdadbc3d852	522	#define CMD13_RCA(n) (((uint32_t) (n & 0xFFFF) ) << 16)
embeddedartists	0:0fdadbc3d852	523
embeddedartists	0:0fdadbc3d852	524	/**
embeddedartists	0:0fdadbc3d852	525	* @brief APP_CMD command definitions
embeddedartists	0:0fdadbc3d852	526	*/
embeddedartists	0:0fdadbc3d852	527	#define CMD55_RCA(n) (((uint32_t) (n & 0xFFFF) ) << 16)
embeddedartists	0:0fdadbc3d852	528
embeddedartists	0:0fdadbc3d852	529	/**
embeddedartists	0:0fdadbc3d852	530	* @brief ACMD41 command definitions
embeddedartists	0:0fdadbc3d852	531	*/
embeddedartists	0:0fdadbc3d852	532	#define ACMD41_OCR(n) (((uint32_t) n) & 0xFFFFFF)
embeddedartists	0:0fdadbc3d852	533	#define ACMD41_S18R (((uint32_t) 1 ) << 24)
embeddedartists	0:0fdadbc3d852	534	#define ACMD41_XPC (((uint32_t) 1 ) << 28)
embeddedartists	0:0fdadbc3d852	535	#define ACMD41_HCS (((uint32_t) 1 ) << 30)
embeddedartists	0:0fdadbc3d852	536
embeddedartists	0:0fdadbc3d852	537	/**
embeddedartists	0:0fdadbc3d852	538	* @brief ACMD6 command definitions
embeddedartists	0:0fdadbc3d852	539	*/
embeddedartists	0:0fdadbc3d852	540	#define ACMD6_BUS_WIDTH(n) ((uint32_t) n & 0x03)
embeddedartists	0:0fdadbc3d852	541	#define ACMD6_BUS_WIDTH_1 (0)
embeddedartists	0:0fdadbc3d852	542	#define ACMD6_BUS_WIDTH_4 (2)
embeddedartists	0:0fdadbc3d852	543
embeddedartists	0:0fdadbc3d852	544	/** @brief Card type defines
embeddedartists	0:0fdadbc3d852	545	*/
embeddedartists	0:0fdadbc3d852	546	#define CARD_TYPE_SD (1 << 0)
embeddedartists	0:0fdadbc3d852	547	#define CARD_TYPE_4BIT (1 << 1)
embeddedartists	0:0fdadbc3d852	548	#define CARD_TYPE_8BIT (1 << 2)
embeddedartists	0:0fdadbc3d852	549	#define CARD_TYPE_HC (OCR_HC_CCS)/!< high capacity card > 2GB /
embeddedartists	0:0fdadbc3d852	550
embeddedartists	0:0fdadbc3d852	551	/**
embeddedartists	0:0fdadbc3d852	552	* @brief SD/MMC sector size in bytes
embeddedartists	0:0fdadbc3d852	553	*/
embeddedartists	0:0fdadbc3d852	554	#define MMC_SECTOR_SIZE 512
embeddedartists	0:0fdadbc3d852	555
embeddedartists	0:0fdadbc3d852	556	/******************************************************************************
embeddedartists	0:0fdadbc3d852	557	* External global variables
embeddedartists	0:0fdadbc3d852	558	*****************************************************************************/
embeddedartists	0:0fdadbc3d852	559
embeddedartists	0:0fdadbc3d852	560	/******************************************************************************
embeddedartists	0:0fdadbc3d852	561	* Local variables
embeddedartists	0:0fdadbc3d852	562	*****************************************************************************/
embeddedartists	0:0fdadbc3d852	563
embeddedartists	0:0fdadbc3d852	564	static MCIFileSystem* pUglyForIRQ = NULL;
embeddedartists	0:0fdadbc3d852	565
embeddedartists	0:0fdadbc3d852	566	/******************************************************************************
embeddedartists	0:0fdadbc3d852	567	* Local Functions
embeddedartists	0:0fdadbc3d852	568	*****************************************************************************/
embeddedartists	0:0fdadbc3d852	569
embeddedartists	0:0fdadbc3d852	570	static void mymciirq()
embeddedartists	0:0fdadbc3d852	571	{
embeddedartists	0:0fdadbc3d852	572	pUglyForIRQ->mci_MCIIRQHandler();
embeddedartists	0:0fdadbc3d852	573	}
embeddedartists	0:0fdadbc3d852	574
embeddedartists	0:0fdadbc3d852	575	static void mydmairq()
embeddedartists	0:0fdadbc3d852	576	{
embeddedartists	0:0fdadbc3d852	577	pUglyForIRQ->mci_DMAIRQHandler();
embeddedartists	0:0fdadbc3d852	578	}
embeddedartists	0:0fdadbc3d852	579
embeddedartists	0:0fdadbc3d852	580	/******************************************************************************
embeddedartists	0:0fdadbc3d852	581	* Public Functions
embeddedartists	0:0fdadbc3d852	582	*****************************************************************************/
embeddedartists	0:0fdadbc3d852	583
embeddedartists	0:0fdadbc3d852	584	MCIFileSystem::MCIFileSystem(const char* name, PinName cd) :
embeddedartists	0:0fdadbc3d852	585	FATFileSystem(name)
embeddedartists	0:0fdadbc3d852	586	{
embeddedartists	0:0fdadbc3d852	587	pUglyForIRQ = this;
embeddedartists	0:0fdadbc3d852	588
embeddedartists	0:0fdadbc3d852	589	_Stat = STA_NOINIT;
embeddedartists	0:0fdadbc3d852	590	memset(&_sdCardInfo, 0, sizeof(SDMMC_CARD_T));
embeddedartists	0:0fdadbc3d852	591	_eventReceived = false;
embeddedartists	0:0fdadbc3d852	592	_eventSuccess = false;
embeddedartists	0:0fdadbc3d852	593
embeddedartists	0:0fdadbc3d852	594	initMCI();
embeddedartists	0:0fdadbc3d852	595
embeddedartists	0:0fdadbc3d852	596	if (cd != NC)
embeddedartists	0:0fdadbc3d852	597	{
embeddedartists	0:0fdadbc3d852	598	_cardDetect = new DigitalIn(cd);
embeddedartists	0:0fdadbc3d852	599	}
embeddedartists	0:0fdadbc3d852	600	}
embeddedartists	0:0fdadbc3d852	601
embeddedartists	0:0fdadbc3d852	602	MCIFileSystem::~MCIFileSystem()
embeddedartists	0:0fdadbc3d852	603	{
embeddedartists	0:0fdadbc3d852	604	if (_cardDetect != NULL)
embeddedartists	0:0fdadbc3d852	605	{
embeddedartists	0:0fdadbc3d852	606	delete _cardDetect;
embeddedartists	0:0fdadbc3d852	607	}
embeddedartists	0:0fdadbc3d852	608	}
embeddedartists	0:0fdadbc3d852	609	void MCIFileSystem::initMCI()
embeddedartists	0:0fdadbc3d852	610	{
embeddedartists	0:0fdadbc3d852	611	// Pinsel for MCI
embeddedartists	0:0fdadbc3d852	612	LPC_IOCON->P1_2 = 2; /* SD_CLK @ P1.2 */
embeddedartists	0:0fdadbc3d852	613	LPC_IOCON->P1_3 = 2; /* SD_CMD @ P1.3 */
embeddedartists	0:0fdadbc3d852	614	LPC_IOCON->P1_5 = 2 \| (1<<7); /* SD_PWR @ P1.5 - digital mode */
embeddedartists	0:0fdadbc3d852	615	LPC_IOCON->P1_6 = 2 \| (1<<7); /* SD_DAT[0] @ P1.6 - digital mode */
embeddedartists	0:0fdadbc3d852	616	LPC_IOCON->P1_7 = 2 \| (1<<7); /* SD_DAT[1] @ P1.7 - digital mode */
embeddedartists	0:0fdadbc3d852	617	LPC_IOCON->P1_11 = 2; /* SD_DAT[2] @ P1.11 */
embeddedartists	0:0fdadbc3d852	618	LPC_IOCON->P1_12 = 2; /* SD_DAT[3] @ P1.12 */
embeddedartists	0:0fdadbc3d852	619
embeddedartists	0:0fdadbc3d852	620	LPC_SC->PCONP \|= SYSCTL_CLOCK_SDC;
embeddedartists	0:0fdadbc3d852	621	LPC_SC->RSTCON0 = (1<<28);
embeddedartists	0:0fdadbc3d852	622	LPC_SC->RSTCON0 &= ~(1<<28);
embeddedartists	0:0fdadbc3d852	623
embeddedartists	0:0fdadbc3d852	624	/* Initialize GPDMA controller */
embeddedartists	0:0fdadbc3d852	625	gpdma_init();
embeddedartists	0:0fdadbc3d852	626
embeddedartists	0:0fdadbc3d852	627	/* Initialize SDC peripheral */
embeddedartists	0:0fdadbc3d852	628	LPC_SC->PCONP \|= SYSCTL_CLOCK_SDC;
embeddedartists	0:0fdadbc3d852	629
embeddedartists	0:0fdadbc3d852	630	/* Disable SD_CLK */
embeddedartists	0:0fdadbc3d852	631	mci_ClockControl(SDC_CLOCK_ENABLE, false);
embeddedartists	0:0fdadbc3d852	632
embeddedartists	0:0fdadbc3d852	633	/* Power-off */
embeddedartists	0:0fdadbc3d852	634	mci_PowerControl(PowerOff, 0);
embeddedartists	0:0fdadbc3d852	635	mci_WriteDelay();
embeddedartists	0:0fdadbc3d852	636
embeddedartists	0:0fdadbc3d852	637	/* Disable all interrupts */
embeddedartists	0:0fdadbc3d852	638	LPC_MCI->MASK0 = 0;
embeddedartists	0:0fdadbc3d852	639
embeddedartists	0:0fdadbc3d852	640	/Setting for timeout problem /
embeddedartists	0:0fdadbc3d852	641	LPC_MCI->DATATMR = 0x1FFFFFFF;
embeddedartists	0:0fdadbc3d852	642
embeddedartists	0:0fdadbc3d852	643	LPC_MCI->COMMAND = 0;
embeddedartists	0:0fdadbc3d852	644	mci_WriteDelay();
embeddedartists	0:0fdadbc3d852	645
embeddedartists	0:0fdadbc3d852	646	LPC_MCI->DATACTRL = 0;
embeddedartists	0:0fdadbc3d852	647	mci_WriteDelay();
embeddedartists	0:0fdadbc3d852	648
embeddedartists	0:0fdadbc3d852	649	/* clear all pending interrupts */
embeddedartists	0:0fdadbc3d852	650	LPC_MCI->CLEAR = SDC_CLEAR_ALL;
embeddedartists	0:0fdadbc3d852	651
embeddedartists	0:0fdadbc3d852	652	/* Power-up SDC Peripheral */
embeddedartists	0:0fdadbc3d852	653	mci_PowerControl(PowerUp, 0);
embeddedartists	0:0fdadbc3d852	654
embeddedartists	0:0fdadbc3d852	655	/* delays for the supply output is stable*/
embeddedartists	0:0fdadbc3d852	656	for (uint32_t i = 0; i < 0x80000; i++ ) {}
embeddedartists	0:0fdadbc3d852	657
embeddedartists	0:0fdadbc3d852	658	mci_SetClock(SDC_IDENT_CLOCK_RATE);
embeddedartists	0:0fdadbc3d852	659	mci_ClockControl(SDC_CLOCK_ENABLE, true);
embeddedartists	0:0fdadbc3d852	660
embeddedartists	0:0fdadbc3d852	661	/* Power-on SDC Interface */
embeddedartists	0:0fdadbc3d852	662	mci_PowerControl(PowerOn, 0);
embeddedartists	0:0fdadbc3d852	663
embeddedartists	0:0fdadbc3d852	664	NVIC_SetVector(MCI_IRQn, (uint32_t) mymciirq);
embeddedartists	0:0fdadbc3d852	665	NVIC_EnableIRQ(MCI_IRQn);
embeddedartists	0:0fdadbc3d852	666
embeddedartists	0:0fdadbc3d852	667	NVIC_SetVector(DMA_IRQn, (uint32_t) mydmairq);
embeddedartists	0:0fdadbc3d852	668	NVIC_EnableIRQ(DMA_IRQn);
embeddedartists	0:0fdadbc3d852	669	}
embeddedartists	0:0fdadbc3d852	670
embeddedartists	0:0fdadbc3d852	671	int MCIFileSystem::disk_initialize() {
embeddedartists	0:0fdadbc3d852	672
embeddedartists	0:0fdadbc3d852	673	debug_if(MCI_DBG, "mcifs:disk_initialize(), _Stat = %#x\n", _Stat);
embeddedartists	0:0fdadbc3d852	674
embeddedartists	0:0fdadbc3d852	675	if (!cardInserted()) {
embeddedartists	0:0fdadbc3d852	676	/* No card in the socket */
embeddedartists	0:0fdadbc3d852	677	_Stat = STA_NODISK \| STA_NOINIT;
embeddedartists	0:0fdadbc3d852	678	}
embeddedartists	0:0fdadbc3d852	679
embeddedartists	0:0fdadbc3d852	680	if (_Stat != STA_NOINIT) {
embeddedartists	0:0fdadbc3d852	681	return _Stat; /* card is already enumerated */
embeddedartists	0:0fdadbc3d852	682	}
embeddedartists	0:0fdadbc3d852	683
embeddedartists	0:0fdadbc3d852	684	//rtc_init();
embeddedartists	0:0fdadbc3d852	685
embeddedartists	0:0fdadbc3d852	686	/* Initialize the Card Data Strucutre */
embeddedartists	0:0fdadbc3d852	687	memset(&_sdCardInfo, 0, sizeof(SDMMC_CARD_T));
embeddedartists	0:0fdadbc3d852	688
embeddedartists	0:0fdadbc3d852	689	/* Reset */
embeddedartists	0:0fdadbc3d852	690	_Stat = STA_NOINIT;
embeddedartists	0:0fdadbc3d852	691
embeddedartists	0:0fdadbc3d852	692	/* Enumerate the card once detected. Note this function may block for a little while. */
embeddedartists	0:0fdadbc3d852	693	int ret = mci_Acquire();
embeddedartists	0:0fdadbc3d852	694	if (ret != 1) {
embeddedartists	0:0fdadbc3d852	695	debug("Card Acquire failed... got %d, but expected 1\r\n", ret);
embeddedartists	0:0fdadbc3d852	696	return 1;//Stat;
embeddedartists	0:0fdadbc3d852	697	}
embeddedartists	0:0fdadbc3d852	698
embeddedartists	0:0fdadbc3d852	699	_Stat &= ~STA_NOINIT;
embeddedartists	0:0fdadbc3d852	700	return _Stat;
embeddedartists	0:0fdadbc3d852	701	}
embeddedartists	0:0fdadbc3d852	702
embeddedartists	0:0fdadbc3d852	703	int MCIFileSystem::disk_write(const uint8_t *buffer, uint64_t block_number) {
embeddedartists	0:0fdadbc3d852	704	debug_if(MCI_DBG, "mcifs:disk_write(%#x, %llu), _Stat = %#x\n", (uint32_t)buffer, block_number, _Stat);
embeddedartists	0:0fdadbc3d852	705	if (_Stat & STA_NOINIT) {
embeddedartists	0:0fdadbc3d852	706	// not ready
embeddedartists	0:0fdadbc3d852	707	return 1;
embeddedartists	0:0fdadbc3d852	708	}
embeddedartists	0:0fdadbc3d852	709	if (mci_WriteBlocks((void*)buffer, block_number, 1) == SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	710	return 0;
embeddedartists	0:0fdadbc3d852	711	}
embeddedartists	0:0fdadbc3d852	712
embeddedartists	0:0fdadbc3d852	713	return 1;
embeddedartists	0:0fdadbc3d852	714	}
embeddedartists	0:0fdadbc3d852	715
embeddedartists	0:0fdadbc3d852	716	int MCIFileSystem::disk_read(uint8_t *buffer, uint64_t block_number) {
embeddedartists	0:0fdadbc3d852	717	debug_if(MCI_DBG, "mcifs:disk_read(%#x, %llu), _Stat = %#x\n", (uint32_t)buffer, block_number, _Stat);
embeddedartists	0:0fdadbc3d852	718	if (_Stat & STA_NOINIT) {
embeddedartists	0:0fdadbc3d852	719	// not ready
embeddedartists	0:0fdadbc3d852	720	return _Stat;
embeddedartists	0:0fdadbc3d852	721	}
embeddedartists	0:0fdadbc3d852	722	if (mci_ReadBlocks(buffer, block_number, 1) == SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	723	return 0;
embeddedartists	0:0fdadbc3d852	724	}
embeddedartists	0:0fdadbc3d852	725
embeddedartists	0:0fdadbc3d852	726	return 1;
embeddedartists	0:0fdadbc3d852	727	}
embeddedartists	0:0fdadbc3d852	728
embeddedartists	0:0fdadbc3d852	729	int MCIFileSystem::disk_status()
embeddedartists	0:0fdadbc3d852	730	{
embeddedartists	0:0fdadbc3d852	731	debug_if(MCI_DBG, "mcifs:disk_status(), _Stat = %#x\n", _Stat);
embeddedartists	0:0fdadbc3d852	732	return _Stat;
embeddedartists	0:0fdadbc3d852	733	}
embeddedartists	0:0fdadbc3d852	734
embeddedartists	0:0fdadbc3d852	735	int MCIFileSystem::disk_sync()
embeddedartists	0:0fdadbc3d852	736	{
embeddedartists	0:0fdadbc3d852	737	debug_if(MCI_DBG, "mcifs:disk_sync(), _Stat = %#x\n", _Stat);
embeddedartists	0:0fdadbc3d852	738	uint32_t end = us_ticker_read() + 50*1000; // 50ms
embeddedartists	0:0fdadbc3d852	739	while (us_ticker_read() < end)
embeddedartists	0:0fdadbc3d852	740	{
embeddedartists	0:0fdadbc3d852	741	if (mci_GetCardStatus() & R1_READY_FOR_DATA)
embeddedartists	0:0fdadbc3d852	742	{
embeddedartists	0:0fdadbc3d852	743	// card is ready
embeddedartists	0:0fdadbc3d852	744	return 0;
embeddedartists	0:0fdadbc3d852	745	}
embeddedartists	0:0fdadbc3d852	746	}
embeddedartists	0:0fdadbc3d852	747	// timeout while waiting for card to get ready
embeddedartists	0:0fdadbc3d852	748	return 1;
embeddedartists	0:0fdadbc3d852	749	}
embeddedartists	0:0fdadbc3d852	750
embeddedartists	0:0fdadbc3d852	751	uint64_t MCIFileSystem::disk_sectors()
embeddedartists	0:0fdadbc3d852	752	{
embeddedartists	0:0fdadbc3d852	753	debug_if(MCI_DBG, "mcifs:disk_sectors(), _Stat = %#x, returning %llu\n", _Stat, _sdCardInfo.blocknr);
embeddedartists	0:0fdadbc3d852	754	return _sdCardInfo.blocknr;
embeddedartists	0:0fdadbc3d852	755	}
embeddedartists	0:0fdadbc3d852	756
embeddedartists	0:0fdadbc3d852	757	void MCIFileSystem::mci_MCIIRQHandler()
embeddedartists	0:0fdadbc3d852	758	{
embeddedartists	0:0fdadbc3d852	759	int32_t Ret;
embeddedartists	0:0fdadbc3d852	760
embeddedartists	0:0fdadbc3d852	761	Ret = mci_IRQHandler(NULL, 0, NULL, 0);
embeddedartists	0:0fdadbc3d852	762	if(Ret < 0) {
embeddedartists	0:0fdadbc3d852	763	_eventSuccess = false;
embeddedartists	0:0fdadbc3d852	764	_eventReceived = true;
embeddedartists	0:0fdadbc3d852	765	}
embeddedartists	0:0fdadbc3d852	766	}
embeddedartists	0:0fdadbc3d852	767
embeddedartists	0:0fdadbc3d852	768	void MCIFileSystem::mci_DMAIRQHandler()
embeddedartists	0:0fdadbc3d852	769	{
embeddedartists	0:0fdadbc3d852	770	_eventSuccess = gpdma_interrupt(_eventDmaChannel);
embeddedartists	0:0fdadbc3d852	771	_eventReceived = true;
embeddedartists	0:0fdadbc3d852	772	NVIC_DisableIRQ(DMA_IRQn);
embeddedartists	0:0fdadbc3d852	773	}
embeddedartists	0:0fdadbc3d852	774
embeddedartists	0:0fdadbc3d852	775	/******************************************************************************
embeddedartists	0:0fdadbc3d852	776	* Private Functions
embeddedartists	0:0fdadbc3d852	777	*****************************************************************************/
embeddedartists	0:0fdadbc3d852	778
embeddedartists	0:0fdadbc3d852	779	bool MCIFileSystem::cardInserted() const
embeddedartists	0:0fdadbc3d852	780	{
embeddedartists	0:0fdadbc3d852	781	// If no card detect pin is given, then assume that a card is inserted.
embeddedartists	0:0fdadbc3d852	782	// If a pin is specified then use that to determing the presence of a card.
embeddedartists	0:0fdadbc3d852	783	return ((_cardDetect == NULL) \|\| (_cardDetect->read() == 0));
embeddedartists	0:0fdadbc3d852	784	}
embeddedartists	0:0fdadbc3d852	785
embeddedartists	0:0fdadbc3d852	786
embeddedartists	0:0fdadbc3d852	787
embeddedartists	0:0fdadbc3d852	788	int32_t MCIFileSystem::mci_Acquire()
embeddedartists	0:0fdadbc3d852	789	{
embeddedartists	0:0fdadbc3d852	790	int32_t Ret;
embeddedartists	0:0fdadbc3d852	791
embeddedartists	0:0fdadbc3d852	792	/* Initialize card info */
embeddedartists	0:0fdadbc3d852	793	_sdCardInfo.speed = SDC_TRAN_CLOCK_RATE;
embeddedartists	0:0fdadbc3d852	794	_sdCardInfo.card_type = 0;
embeddedartists	0:0fdadbc3d852	795
embeddedartists	0:0fdadbc3d852	796	/* During identification phase, the clock should be less than
embeddedartists	0:0fdadbc3d852	797	400Khz. Once we pass this phase, the normal clock can be set up
embeddedartists	0:0fdadbc3d852	798	to 25Mhz on SD card and 20Mhz on MMC card. */
embeddedartists	0:0fdadbc3d852	799	mci_SetClock(SDC_IDENT_CLOCK_RATE);
embeddedartists	0:0fdadbc3d852	800
embeddedartists	0:0fdadbc3d852	801	/* Clear Open Drain output control for SD */
embeddedartists	0:0fdadbc3d852	802	mci_PowerControl(PowerOn, 0);
embeddedartists	0:0fdadbc3d852	803
embeddedartists	0:0fdadbc3d852	804	/* Card Reset */
embeddedartists	0:0fdadbc3d852	805	Ret = mci_ExecuteCmd(SD_GO_IDLE_STATE, 0, NULL);
embeddedartists	0:0fdadbc3d852	806	if (Ret != 0) {
embeddedartists	0:0fdadbc3d852	807	return Ret;
embeddedartists	0:0fdadbc3d852	808	}
embeddedartists	0:0fdadbc3d852	809
embeddedartists	0:0fdadbc3d852	810	wait(ACQUIRE_DELAY);
embeddedartists	0:0fdadbc3d852	811
embeddedartists	0:0fdadbc3d852	812	/* Send interface operation condiftion */
embeddedartists	0:0fdadbc3d852	813	Ret = mci_SendIfCond();
embeddedartists	0:0fdadbc3d852	814	if (Ret == SDC_RET_BAD_PARAMETERS) {
embeddedartists	0:0fdadbc3d852	815	return Ret; /* Non-compatible voltage range or check pattern is not correct */
embeddedartists	0:0fdadbc3d852	816
embeddedartists	0:0fdadbc3d852	817	}
embeddedartists	0:0fdadbc3d852	818	/* Get Card Type */
embeddedartists	0:0fdadbc3d852	819	if (Ret == SDC_RET_OK) {/* Ver2.00 or later SD Memory Card*/
embeddedartists	0:0fdadbc3d852	820	bool CCS;
embeddedartists	0:0fdadbc3d852	821	uint32_t OCR = SDC_OCR_27_36;
embeddedartists	0:0fdadbc3d852	822	_sdCardInfo.card_type \|= CARD_TYPE_SD;
embeddedartists	0:0fdadbc3d852	823	Ret = mci_SendAppOpCond(0, true, &OCR, &CCS);
embeddedartists	0:0fdadbc3d852	824	if (CCS) { /* High Capacity or Extended Capacity SD Memory Card */
embeddedartists	0:0fdadbc3d852	825	_sdCardInfo.card_type \|= CARD_TYPE_HC;
embeddedartists	0:0fdadbc3d852	826	}
embeddedartists	0:0fdadbc3d852	827	}
embeddedartists	0:0fdadbc3d852	828	else { /*Ver2.00 or later SD Memory Card(voltage mismatch) or Ver1.X SD Memory Card
embeddedartists	0:0fdadbc3d852	829	or not SD Memory Card*/
embeddedartists	0:0fdadbc3d852	830	bool CCS;
embeddedartists	0:0fdadbc3d852	831	uint32_t OCR = SDC_OCR_27_36;
embeddedartists	0:0fdadbc3d852	832	Ret = mci_SendAppOpCond(0, false, &OCR, &CCS);
embeddedartists	0:0fdadbc3d852	833	if (Ret == SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	834	_sdCardInfo.card_type \|= CARD_TYPE_SD;
embeddedartists	0:0fdadbc3d852	835	}
embeddedartists	0:0fdadbc3d852	836	else if (Ret == SDC_RET_BAD_PARAMETERS) {
embeddedartists	0:0fdadbc3d852	837	return Ret;
embeddedartists	0:0fdadbc3d852	838	}
embeddedartists	0:0fdadbc3d852	839	else { /* MMC Card setup */
embeddedartists	0:0fdadbc3d852	840	uint32_t OCR;
embeddedartists	0:0fdadbc3d852	841	/* Enter to Open Drain mode */
embeddedartists	0:0fdadbc3d852	842	mci_PowerControl(PowerOn, SDC_PWR_OPENDRAIN);
embeddedartists	0:0fdadbc3d852	843	wait(ACQUIRE_DELAY);
embeddedartists	0:0fdadbc3d852	844	Ret = mci_SendOpCond(&OCR);
embeddedartists	0:0fdadbc3d852	845	if (Ret != SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	846	return Ret;
embeddedartists	0:0fdadbc3d852	847	}
embeddedartists	0:0fdadbc3d852	848
embeddedartists	0:0fdadbc3d852	849	}
embeddedartists	0:0fdadbc3d852	850	}
embeddedartists	0:0fdadbc3d852	851
embeddedartists	0:0fdadbc3d852	852	/* Read CID */
embeddedartists	0:0fdadbc3d852	853	mci_GetCID(_sdCardInfo.cid);
embeddedartists	0:0fdadbc3d852	854
embeddedartists	0:0fdadbc3d852	855	/* RCA send, for SD get RCA */
embeddedartists	0:0fdadbc3d852	856	if (_sdCardInfo.card_type & CARD_TYPE_SD) {
embeddedartists	0:0fdadbc3d852	857	mci_GetAddr(&_sdCardInfo.rca);
embeddedartists	0:0fdadbc3d852	858	}
embeddedartists	0:0fdadbc3d852	859	else {
embeddedartists	0:0fdadbc3d852	860	_sdCardInfo.rca = 1;
embeddedartists	0:0fdadbc3d852	861	mci_SetAddr(_sdCardInfo.rca);
embeddedartists	0:0fdadbc3d852	862	mci_PowerControl(PowerOn, 0); /* enter to push-pull mode */
embeddedartists	0:0fdadbc3d852	863	}
embeddedartists	0:0fdadbc3d852	864
embeddedartists	0:0fdadbc3d852	865	/* Get CSD */
embeddedartists	0:0fdadbc3d852	866	mci_GetCSD(_sdCardInfo.rca, _sdCardInfo.csd);
embeddedartists	0:0fdadbc3d852	867
embeddedartists	0:0fdadbc3d852	868	/* Compute card size, block size and no. of blocks based on CSD response recived. */
embeddedartists	0:0fdadbc3d852	869	if (_sdCardInfo.cid[0]) {
embeddedartists	0:0fdadbc3d852	870	mci_ProcessCSD();
embeddedartists	0:0fdadbc3d852	871
embeddedartists	0:0fdadbc3d852	872	if (mci_SetTranState(_sdCardInfo.rca) != SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	873	return 0;
embeddedartists	0:0fdadbc3d852	874	}
embeddedartists	0:0fdadbc3d852	875
embeddedartists	0:0fdadbc3d852	876	if (mci_GetCardState() != SDMMC_TRAN_ST) {
embeddedartists	0:0fdadbc3d852	877	return 0;
embeddedartists	0:0fdadbc3d852	878	}
embeddedartists	0:0fdadbc3d852	879
embeddedartists	0:0fdadbc3d852	880	if (mci_SetCardParams() != 0) {
embeddedartists	0:0fdadbc3d852	881	return 0;
embeddedartists	0:0fdadbc3d852	882	}
embeddedartists	0:0fdadbc3d852	883	}
embeddedartists	0:0fdadbc3d852	884
embeddedartists	0:0fdadbc3d852	885	return (_sdCardInfo.cid[0]) ? 1 : 0;
embeddedartists	0:0fdadbc3d852	886	}
embeddedartists	0:0fdadbc3d852	887
embeddedartists	0:0fdadbc3d852	888	uint32_t MCIFileSystem::mci_GetCardStatus() const
embeddedartists	0:0fdadbc3d852	889	{
embeddedartists	0:0fdadbc3d852	890	uint32_t Status;
embeddedartists	0:0fdadbc3d852	891	mci_GetStatus(_sdCardInfo.rca, &Status);
embeddedartists	0:0fdadbc3d852	892	return Status;
embeddedartists	0:0fdadbc3d852	893	}
embeddedartists	0:0fdadbc3d852	894
embeddedartists	0:0fdadbc3d852	895	MCIFileSystem::CardState MCIFileSystem::mci_GetCardState() const
embeddedartists	0:0fdadbc3d852	896	{
embeddedartists	0:0fdadbc3d852	897	uint32_t Status;
embeddedartists	0:0fdadbc3d852	898	volatile int32_t Ret;
embeddedartists	0:0fdadbc3d852	899
embeddedartists	0:0fdadbc3d852	900	/* get current state of the card */
embeddedartists	0:0fdadbc3d852	901	Ret = mci_GetStatus(_sdCardInfo.rca, &Status);
embeddedartists	0:0fdadbc3d852	902
embeddedartists	0:0fdadbc3d852	903	/* check card state in response */
embeddedartists	0:0fdadbc3d852	904	return (CardState) R1_CURRENT_STATE(Status);
embeddedartists	0:0fdadbc3d852	905	}
embeddedartists	0:0fdadbc3d852	906
embeddedartists	0:0fdadbc3d852	907	MCIFileSystem::ReturnCode MCIFileSystem::mci_StopTransmission(uint32_t rca) const
embeddedartists	0:0fdadbc3d852	908	{
embeddedartists	0:0fdadbc3d852	909	uint32_t Status;
embeddedartists	0:0fdadbc3d852	910	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:0fdadbc3d852	911	response_t Response;
embeddedartists	0:0fdadbc3d852	912	uint32_t RetryCnt = 20;
embeddedartists	0:0fdadbc3d852	913
embeddedartists	0:0fdadbc3d852	914	Ret = mci_GetStatus(rca, &Status);
embeddedartists	0:0fdadbc3d852	915	if (Ret != SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	916	return SDC_RET_ERR_STATE;
embeddedartists	0:0fdadbc3d852	917	}
embeddedartists	0:0fdadbc3d852	918
embeddedartists	0:0fdadbc3d852	919	if (R1_CURRENT_STATE(Status) == SDMMC_TRAN_ST) {
embeddedartists	0:0fdadbc3d852	920	return SDC_RET_OK;
embeddedartists	0:0fdadbc3d852	921	}
embeddedartists	0:0fdadbc3d852	922
embeddedartists	0:0fdadbc3d852	923	if ((R1_CURRENT_STATE(Status) != SDMMC_DATA_ST) &&
embeddedartists	0:0fdadbc3d852	924	(R1_CURRENT_STATE(Status) != SDMMC_RCV_ST)) {
embeddedartists	0:0fdadbc3d852	925	return SDC_RET_ERR_STATE;
embeddedartists	0:0fdadbc3d852	926	}
embeddedartists	0:0fdadbc3d852	927
embeddedartists	0:0fdadbc3d852	928	while (RetryCnt > 0) {
embeddedartists	0:0fdadbc3d852	929	Ret = mci_ExecuteCmd(SD_CMD12_STOP_TRANSMISSION, 0, &Response);
embeddedartists	0:0fdadbc3d852	930	if (Ret == SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	931	if (mci_CheckR1Response(Response.Data[0], &Ret)) {
embeddedartists	0:0fdadbc3d852	932	if (Ret != SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	933	return Ret;
embeddedartists	0:0fdadbc3d852	934	}
embeddedartists	0:0fdadbc3d852	935	Ret = mci_GetStatus(rca, &Status);
embeddedartists	0:0fdadbc3d852	936	if ((R1_CURRENT_STATE(Status) == SDMMC_TRAN_ST) \|\| (R1_CURRENT_STATE(Status) == SDMMC_PRG_ST)) {
embeddedartists	0:0fdadbc3d852	937	return SDC_RET_OK;
embeddedartists	0:0fdadbc3d852	938	}
embeddedartists	0:0fdadbc3d852	939	return SDC_RET_ERR_STATE;
embeddedartists	0:0fdadbc3d852	940	}
embeddedartists	0:0fdadbc3d852	941	}
embeddedartists	0:0fdadbc3d852	942	RetryCnt--;
embeddedartists	0:0fdadbc3d852	943	}
embeddedartists	0:0fdadbc3d852	944	return Ret;
embeddedartists	0:0fdadbc3d852	945	}
embeddedartists	0:0fdadbc3d852	946
embeddedartists	0:0fdadbc3d852	947	MCIFileSystem::ReturnCode MCIFileSystem::mci_ReadBlocks(void *buffer, int32_t startBlock, int32_t blockNum)
embeddedartists	0:0fdadbc3d852	948	{
embeddedartists	0:0fdadbc3d852	949	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:0fdadbc3d852	950	uint8_t dmaChannel;
embeddedartists	0:0fdadbc3d852	951	int32_t ByteNum = blockNum * MMC_SECTOR_SIZE;
embeddedartists	0:0fdadbc3d852	952
embeddedartists	0:0fdadbc3d852	953	do
embeddedartists	0:0fdadbc3d852	954	{
embeddedartists	0:0fdadbc3d852	955	/* if card is not acquired return immediately */
embeddedartists	0:0fdadbc3d852	956	if (( startBlock < 0) \|\| ( (startBlock + blockNum) > _sdCardInfo.blocknr) ) {
embeddedartists	0:0fdadbc3d852	957	Ret = SDC_RET_NOT_READY;
embeddedartists	0:0fdadbc3d852	958	break;
embeddedartists	0:0fdadbc3d852	959	}
embeddedartists	0:0fdadbc3d852	960
embeddedartists	0:0fdadbc3d852	961	/* Put to tran state */
embeddedartists	0:0fdadbc3d852	962	Ret = mci_SetTranState(_sdCardInfo.rca);
embeddedartists	0:0fdadbc3d852	963	if (Ret != SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	964	break;
embeddedartists	0:0fdadbc3d852	965	}
embeddedartists	0:0fdadbc3d852	966
embeddedartists	0:0fdadbc3d852	967	LPC_MCI->MASK0 = SDC_MASK0_DATA \| SDC_MASK0_RXDATAERR;
embeddedartists	0:0fdadbc3d852	968
embeddedartists	0:0fdadbc3d852	969	/* DMA Setup */
embeddedartists	0:0fdadbc3d852	970	gpdma_getFreeChannel(&dmaChannel);
embeddedartists	0:0fdadbc3d852	971	gpdma_transfer_from_mci(dmaChannel, (uint32_t)buffer, ByteNum);
embeddedartists	0:0fdadbc3d852	972	mci_SetupEventWakeup(dmaChannel);
embeddedartists	0:0fdadbc3d852	973
embeddedartists	0:0fdadbc3d852	974	/* set transfer information */
embeddedartists	0:0fdadbc3d852	975	mci_SetDataTransfer(blockNum, true, DATA_TIMER_VALUE_R);
embeddedartists	0:0fdadbc3d852	976
embeddedartists	0:0fdadbc3d852	977	Ret = _readBlocks(_sdCardInfo.card_type, startBlock, blockNum);
embeddedartists	0:0fdadbc3d852	978	if (Ret == SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	979	/* Wait for transfer Finish */
embeddedartists	0:0fdadbc3d852	980	if (mci_WaitForEvent() != 0) {
embeddedartists	0:0fdadbc3d852	981	Ret = SDC_RET_FAILED;
embeddedartists	0:0fdadbc3d852	982	}
embeddedartists	0:0fdadbc3d852	983	} else {
embeddedartists	0:0fdadbc3d852	984	Ret = SDC_RET_FAILED;
embeddedartists	0:0fdadbc3d852	985	}
embeddedartists	0:0fdadbc3d852	986
embeddedartists	0:0fdadbc3d852	987	gpdma_stop(dmaChannel);
embeddedartists	0:0fdadbc3d852	988
embeddedartists	0:0fdadbc3d852	989	if ((blockNum > 1) \|\| (mci_GetCardState() == SDMMC_DATA_ST)) {
embeddedartists	0:0fdadbc3d852	990	/* Send Stop transmission command */
embeddedartists	0:0fdadbc3d852	991	mci_StopTransmission(_sdCardInfo.rca);
embeddedartists	0:0fdadbc3d852	992	}
embeddedartists	0:0fdadbc3d852	993
embeddedartists	0:0fdadbc3d852	994	/* Wait for card to enter tran state */
embeddedartists	0:0fdadbc3d852	995	while (mci_GetCardState() != SDMMC_TRAN_ST) {}
embeddedartists	0:0fdadbc3d852	996
embeddedartists	0:0fdadbc3d852	997	} while(false);
embeddedartists	0:0fdadbc3d852	998
embeddedartists	0:0fdadbc3d852	999	return Ret;
embeddedartists	0:0fdadbc3d852	1000	}
embeddedartists	0:0fdadbc3d852	1001
embeddedartists	0:0fdadbc3d852	1002	MCIFileSystem::ReturnCode MCIFileSystem::mci_WriteBlocks(void *buffer, int32_t startBlock, int32_t blockNum)
embeddedartists	0:0fdadbc3d852	1003	{
embeddedartists	0:0fdadbc3d852	1004	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:0fdadbc3d852	1005	uint8_t dmaChannel;
embeddedartists	0:0fdadbc3d852	1006
embeddedartists	0:0fdadbc3d852	1007	do
embeddedartists	0:0fdadbc3d852	1008	{
embeddedartists	0:0fdadbc3d852	1009	/* if card is not acquired return immediately */
embeddedartists	0:0fdadbc3d852	1010	if (( startBlock < 0) \|\| ( (startBlock + blockNum) > _sdCardInfo.blocknr) ) {
embeddedartists	0:0fdadbc3d852	1011	Ret = SDC_RET_NOT_READY;
embeddedartists	0:0fdadbc3d852	1012	break;
embeddedartists	0:0fdadbc3d852	1013	}
embeddedartists	0:0fdadbc3d852	1014
embeddedartists	0:0fdadbc3d852	1015	/* Put to tran state */
embeddedartists	0:0fdadbc3d852	1016	Ret = mci_SetTranState(_sdCardInfo.rca);
embeddedartists	0:0fdadbc3d852	1017	if (Ret != SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	1018	break;
embeddedartists	0:0fdadbc3d852	1019	}
embeddedartists	0:0fdadbc3d852	1020
embeddedartists	0:0fdadbc3d852	1021	Ret = _writeBlocks(_sdCardInfo.card_type, startBlock, blockNum);
embeddedartists	0:0fdadbc3d852	1022	if (Ret != SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	1023	break;
embeddedartists	0:0fdadbc3d852	1024	}
embeddedartists	0:0fdadbc3d852	1025
embeddedartists	0:0fdadbc3d852	1026	/Wait for card enter to rcv state/
embeddedartists	0:0fdadbc3d852	1027	while (mci_GetCardState() != SDMMC_RCV_ST) {}
embeddedartists	0:0fdadbc3d852	1028
embeddedartists	0:0fdadbc3d852	1029	LPC_MCI->MASK0 = SDC_MASK0_DATA \| SDC_MASK0_TXDATAERR;
embeddedartists	0:0fdadbc3d852	1030
embeddedartists	0:0fdadbc3d852	1031	/* DMA Setup */
embeddedartists	0:0fdadbc3d852	1032	gpdma_getFreeChannel(&dmaChannel);
embeddedartists	0:0fdadbc3d852	1033	gpdma_transfer_to_mci(dmaChannel, (uint32_t)buffer, blockNum*MMC_SECTOR_SIZE);
embeddedartists	0:0fdadbc3d852	1034	mci_SetupEventWakeup(dmaChannel);
embeddedartists	0:0fdadbc3d852	1035
embeddedartists	0:0fdadbc3d852	1036	/* set transfer information */
embeddedartists	0:0fdadbc3d852	1037	mci_SetDataTransfer(blockNum, false, DATA_TIMER_VALUE_W);
embeddedartists	0:0fdadbc3d852	1038
embeddedartists	0:0fdadbc3d852	1039	/* Wait for transfer done */
embeddedartists	0:0fdadbc3d852	1040	if (mci_WaitForEvent() != 0) {
embeddedartists	0:0fdadbc3d852	1041	Ret = SDC_RET_FAILED;
embeddedartists	0:0fdadbc3d852	1042	}
embeddedartists	0:0fdadbc3d852	1043	gpdma_stop(dmaChannel);
embeddedartists	0:0fdadbc3d852	1044
embeddedartists	0:0fdadbc3d852	1045	if ((blockNum > 1) \|\| (mci_GetCardState() == SDMMC_RCV_ST)) {
embeddedartists	0:0fdadbc3d852	1046	/* Send Stop transmission command */
embeddedartists	0:0fdadbc3d852	1047	mci_StopTransmission(_sdCardInfo.rca);
embeddedartists	0:0fdadbc3d852	1048	}
embeddedartists	0:0fdadbc3d852	1049
embeddedartists	0:0fdadbc3d852	1050	/* Wait for card to enter tran state */
embeddedartists	0:0fdadbc3d852	1051	while (mci_GetCardState() != SDMMC_TRAN_ST) {}
embeddedartists	0:0fdadbc3d852	1052
embeddedartists	0:0fdadbc3d852	1053	} while (false);
embeddedartists	0:0fdadbc3d852	1054
embeddedartists	0:0fdadbc3d852	1055	return Ret;
embeddedartists	0:0fdadbc3d852	1056	}
embeddedartists	0:0fdadbc3d852	1057
embeddedartists	0:0fdadbc3d852	1058	void MCIFileSystem::mci_SetClock(uint32_t freq) const
embeddedartists	0:0fdadbc3d852	1059	{
embeddedartists	0:0fdadbc3d852	1060	uint32_t PClk;
embeddedartists	0:0fdadbc3d852	1061	uint32_t ClkValue = 0;
embeddedartists	0:0fdadbc3d852	1062
embeddedartists	0:0fdadbc3d852	1063	PClk = PeripheralClock;
embeddedartists	0:0fdadbc3d852	1064
embeddedartists	0:0fdadbc3d852	1065	ClkValue = (PClk + 2 * freq - 1) / (2 * freq);
embeddedartists	0:0fdadbc3d852	1066	if (ClkValue > 0) {
embeddedartists	0:0fdadbc3d852	1067	ClkValue -= 1;
embeddedartists	0:0fdadbc3d852	1068	}
embeddedartists	0:0fdadbc3d852	1069	uint32_t temp;
embeddedartists	0:0fdadbc3d852	1070	temp = (LPC_MCI->CLOCK & (~SDC_CLOCK_CLKDIV_BITMASK));
embeddedartists	0:0fdadbc3d852	1071	LPC_MCI->CLOCK = temp \| (SDC_CLOCK_CLKDIV(ClkValue));
embeddedartists	0:0fdadbc3d852	1072	mci_WriteDelay();
embeddedartists	0:0fdadbc3d852	1073	}
embeddedartists	0:0fdadbc3d852	1074
embeddedartists	0:0fdadbc3d852	1075	void MCIFileSystem::mci_ClockControl(ClockControl ctrlType, bool enable) const
embeddedartists	0:0fdadbc3d852	1076	{
embeddedartists	0:0fdadbc3d852	1077	if (enable) {
embeddedartists	0:0fdadbc3d852	1078	LPC_MCI->CLOCK \|= (1 << ctrlType);
embeddedartists	0:0fdadbc3d852	1079	}
embeddedartists	0:0fdadbc3d852	1080	else {
embeddedartists	0:0fdadbc3d852	1081	LPC_MCI->CLOCK &= (~(1 << ctrlType));
embeddedartists	0:0fdadbc3d852	1082	}
embeddedartists	0:0fdadbc3d852	1083	mci_WriteDelay();
embeddedartists	0:0fdadbc3d852	1084	}
embeddedartists	0:0fdadbc3d852	1085
embeddedartists	0:0fdadbc3d852	1086	void MCIFileSystem::mci_PowerControl(power_ctrl_t powerMode, uint32_t flag) const
embeddedartists	0:0fdadbc3d852	1087	{
embeddedartists	0:0fdadbc3d852	1088	LPC_MCI->POWER = (powerMode & 0x3) \| flag;
embeddedartists	0:0fdadbc3d852	1089	mci_WriteDelay();
embeddedartists	0:0fdadbc3d852	1090	}
embeddedartists	0:0fdadbc3d852	1091
embeddedartists	0:0fdadbc3d852	1092	MCIFileSystem::ReturnCode MCIFileSystem::mci_ExecuteCmd(uint32_t Command, uint32_t Arg, response_t* pResp) const
embeddedartists	0:0fdadbc3d852	1093	{
embeddedartists	0:0fdadbc3d852	1094	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:0fdadbc3d852	1095
embeddedartists	0:0fdadbc3d852	1096	/* Send Command to card */
embeddedartists	0:0fdadbc3d852	1097	Ret = mci_SendCmd(Command, Arg, CMD_TIMEOUT);
embeddedartists	0:0fdadbc3d852	1098	if (Ret != SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	1099	return Ret;
embeddedartists	0:0fdadbc3d852	1100	}
embeddedartists	0:0fdadbc3d852	1101
embeddedartists	0:0fdadbc3d852	1102	/* Get response (if any) */
embeddedartists	0:0fdadbc3d852	1103	if ((Command & SDC_COMMAND_RSP_BITMASK) != SDC_COMMAND_NO_RSP) {
embeddedartists	0:0fdadbc3d852	1104
embeddedartists	0:0fdadbc3d852	1105	mci_GetResp(pResp);
embeddedartists	0:0fdadbc3d852	1106
embeddedartists	0:0fdadbc3d852	1107	/* If the response is not R1, in the response field, the Expected Cmd data
embeddedartists	0:0fdadbc3d852	1108	won't be the same as the CMD data in SendCmd(). Below four cmds have
embeddedartists	0:0fdadbc3d852	1109	R2 or R3 response. We don't need to check if MCI_RESP_CMD is the same
embeddedartists	0:0fdadbc3d852	1110	as the Expected or not. */
embeddedartists	0:0fdadbc3d852	1111	if ((SDC_COMMAND_INDEX(Command) != MMC_SEND_OP_COND) &&
embeddedartists	0:0fdadbc3d852	1112	(SDC_COMMAND_INDEX(Command) != SD_APP_OP_COND) &&
embeddedartists	0:0fdadbc3d852	1113	(SDC_COMMAND_INDEX(Command) != MMC_ALL_SEND_CID) &&
embeddedartists	0:0fdadbc3d852	1114	(SDC_COMMAND_INDEX(Command) != MMC_SEND_CSD) &&
embeddedartists	0:0fdadbc3d852	1115	(pResp->CmdIndex != SDC_COMMAND_INDEX(Command))) {
embeddedartists	0:0fdadbc3d852	1116	return SDC_RET_CMD_FAILED;
embeddedartists	0:0fdadbc3d852	1117	}
embeddedartists	0:0fdadbc3d852	1118	}
embeddedartists	0:0fdadbc3d852	1119
embeddedartists	0:0fdadbc3d852	1120	return SDC_RET_OK;
embeddedartists	0:0fdadbc3d852	1121	}
embeddedartists	0:0fdadbc3d852	1122
embeddedartists	0:0fdadbc3d852	1123	MCIFileSystem::ReturnCode MCIFileSystem::mci_SendIfCond() const
embeddedartists	0:0fdadbc3d852	1124	{
embeddedartists	0:0fdadbc3d852	1125	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:0fdadbc3d852	1126	response_t Response;
embeddedartists	0:0fdadbc3d852	1127	uint32_t RetryCnt = 20;
embeddedartists	0:0fdadbc3d852	1128
embeddedartists	0:0fdadbc3d852	1129	while (RetryCnt > 0) {
embeddedartists	0:0fdadbc3d852	1130	Ret = mci_ExecuteCmd(SD_CMD8_SEND_IF_COND, (CMD8_VOLTAGESUPPLIED_27_36 \| CMD8_CHECKPATTERN(
embeddedartists	0:0fdadbc3d852	1131	CMD8_DEF_PATTERN)), &Response);
embeddedartists	0:0fdadbc3d852	1132	if (Ret == SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	1133	if ((Response.Data[0] & CMDRESP_R7_VOLTAGE_ACCEPTED) &&
embeddedartists	0:0fdadbc3d852	1134	(CMDRESP_R7_CHECK_PATTERN(Response.Data[0]) == CMD8_DEF_PATTERN)) {
embeddedartists	0:0fdadbc3d852	1135	return SDC_RET_OK;
embeddedartists	0:0fdadbc3d852	1136	}
embeddedartists	0:0fdadbc3d852	1137	return SDC_RET_BAD_PARAMETERS;
embeddedartists	0:0fdadbc3d852	1138	}
embeddedartists	0:0fdadbc3d852	1139	RetryCnt--;
embeddedartists	0:0fdadbc3d852	1140	}
embeddedartists	0:0fdadbc3d852	1141	return Ret;
embeddedartists	0:0fdadbc3d852	1142	}
embeddedartists	0:0fdadbc3d852	1143
embeddedartists	0:0fdadbc3d852	1144	MCIFileSystem::ReturnCode MCIFileSystem::mci_SendOpCond(uint32_t *pOCR) const
embeddedartists	0:0fdadbc3d852	1145	{
embeddedartists	0:0fdadbc3d852	1146	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:0fdadbc3d852	1147	response_t Response;
embeddedartists	0:0fdadbc3d852	1148	uint32_t RetryCnt = 0x200;
embeddedartists	0:0fdadbc3d852	1149
embeddedartists	0:0fdadbc3d852	1150	while (RetryCnt > 0) {
embeddedartists	0:0fdadbc3d852	1151	Ret = mci_ExecuteCmd(SD_CMD1_SEND_OP_COND, SDC_OCR_27_36, &Response);
embeddedartists	0:0fdadbc3d852	1152	if (Ret == SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	1153	*pOCR = Response.Data[0];
embeddedartists	0:0fdadbc3d852	1154	if (*pOCR & SDC_OCR_IDLE) {
embeddedartists	0:0fdadbc3d852	1155	if ((Response.Data[0] & SDC_OCR_27_36) != SDC_OCR_27_36) {
embeddedartists	0:0fdadbc3d852	1156	return SDC_RET_BAD_PARAMETERS;
embeddedartists	0:0fdadbc3d852	1157	}
embeddedartists	0:0fdadbc3d852	1158	return SDC_RET_OK;
embeddedartists	0:0fdadbc3d852	1159	}
embeddedartists	0:0fdadbc3d852	1160	}
embeddedartists	0:0fdadbc3d852	1161	RetryCnt--;
embeddedartists	0:0fdadbc3d852	1162	}
embeddedartists	0:0fdadbc3d852	1163	return SDC_RET_FAILED;
embeddedartists	0:0fdadbc3d852	1164	}
embeddedartists	0:0fdadbc3d852	1165
embeddedartists	0:0fdadbc3d852	1166	MCIFileSystem::ReturnCode MCIFileSystem::mci_SendAppOpCond(uint16_t rca, bool hcs, uint32_t pOcr, bool pCCS) const
embeddedartists	0:0fdadbc3d852	1167	{
embeddedartists	0:0fdadbc3d852	1168	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:0fdadbc3d852	1169	response_t Response;
embeddedartists	0:0fdadbc3d852	1170	uint32_t Argument;
embeddedartists	0:0fdadbc3d852	1171	uint32_t RetryCnt = 0x2000; /* The host repeatedly issues ACMD41 for at least 1 second or
embeddedartists	0:0fdadbc3d852	1172	until the busy bit are set to 1 */
embeddedartists	0:0fdadbc3d852	1173
embeddedartists	0:0fdadbc3d852	1174	Argument = ACMD41_OCR(*pOcr);
embeddedartists	0:0fdadbc3d852	1175	if (hcs) {
embeddedartists	0:0fdadbc3d852	1176	Argument \|= ACMD41_HCS;
embeddedartists	0:0fdadbc3d852	1177	}
embeddedartists	0:0fdadbc3d852	1178
embeddedartists	0:0fdadbc3d852	1179	while (RetryCnt > 0) {
embeddedartists	0:0fdadbc3d852	1180	Ret = mci_SendAppCmd(rca);
embeddedartists	0:0fdadbc3d852	1181	if (Ret == SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	1182	Ret = mci_ExecuteCmd(SD_ACMD41_SD_SEND_OP_COND, Argument, &Response);
embeddedartists	0:0fdadbc3d852	1183	if (Ret == SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	1184	if (Response.Data[0] & CMDRESP_R3_INIT_COMPLETE) {
embeddedartists	0:0fdadbc3d852	1185	if (*pOcr == 0) {
embeddedartists	0:0fdadbc3d852	1186	*pOcr = CMDRESP_R3_OCR_VAL(Response.Data[0]);
embeddedartists	0:0fdadbc3d852	1187	return SDC_RET_OK;
embeddedartists	0:0fdadbc3d852	1188	}
embeddedartists	0:0fdadbc3d852	1189	if ((CMDRESP_R3_OCR_VAL(Response.Data[0]) & pOcr) != pOcr) {
embeddedartists	0:0fdadbc3d852	1190	return SDC_RET_BAD_PARAMETERS;
embeddedartists	0:0fdadbc3d852	1191	}
embeddedartists	0:0fdadbc3d852	1192	*pCCS = (Response.Data[0] & CMDRESP_R3_HC_CCS) ? true : false;
embeddedartists	0:0fdadbc3d852	1193	return SDC_RET_OK;
embeddedartists	0:0fdadbc3d852	1194	}
embeddedartists	0:0fdadbc3d852	1195	}
embeddedartists	0:0fdadbc3d852	1196	}
embeddedartists	0:0fdadbc3d852	1197	else {
embeddedartists	0:0fdadbc3d852	1198	//If we abort here then some cards will go undetected, better to keep retrying
embeddedartists	0:0fdadbc3d852	1199	//return Ret;
embeddedartists	0:0fdadbc3d852	1200	}
embeddedartists	0:0fdadbc3d852	1201	RetryCnt--;
embeddedartists	0:0fdadbc3d852	1202	}
embeddedartists	0:0fdadbc3d852	1203	return SDC_RET_FAILED;
embeddedartists	0:0fdadbc3d852	1204	}
embeddedartists	0:0fdadbc3d852	1205
embeddedartists	0:0fdadbc3d852	1206	MCIFileSystem::ReturnCode MCIFileSystem::mci_GetCID(uint32_t *pCID) const
embeddedartists	0:0fdadbc3d852	1207	{
embeddedartists	0:0fdadbc3d852	1208	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:0fdadbc3d852	1209	response_t Response;
embeddedartists	0:0fdadbc3d852	1210	uint32_t RetryCnt = 20;
embeddedartists	0:0fdadbc3d852	1211
embeddedartists	0:0fdadbc3d852	1212	while (RetryCnt > 0) {
embeddedartists	0:0fdadbc3d852	1213	Ret = mci_ExecuteCmd(SD_CMD2_ALL_SEND_CID, 0, &Response);
embeddedartists	0:0fdadbc3d852	1214	if (Ret == SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	1215	pCID[3] = Response.Data[0];
embeddedartists	0:0fdadbc3d852	1216	pCID[2] = Response.Data[1];
embeddedartists	0:0fdadbc3d852	1217	pCID[1] = Response.Data[2];
embeddedartists	0:0fdadbc3d852	1218	pCID[0] = Response.Data[3];
embeddedartists	0:0fdadbc3d852	1219	return SDC_RET_OK;
embeddedartists	0:0fdadbc3d852	1220	}
embeddedartists	0:0fdadbc3d852	1221	RetryCnt--;
embeddedartists	0:0fdadbc3d852	1222	}
embeddedartists	0:0fdadbc3d852	1223	return Ret;
embeddedartists	0:0fdadbc3d852	1224	}
embeddedartists	0:0fdadbc3d852	1225
embeddedartists	0:0fdadbc3d852	1226	MCIFileSystem::ReturnCode MCIFileSystem::mci_SetAddr(uint16_t addr) const
embeddedartists	0:0fdadbc3d852	1227	{
embeddedartists	0:0fdadbc3d852	1228	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:0fdadbc3d852	1229	response_t Response;
embeddedartists	0:0fdadbc3d852	1230	uint32_t RetryCnt = 20;
embeddedartists	0:0fdadbc3d852	1231
embeddedartists	0:0fdadbc3d852	1232	while (RetryCnt > 0) {
embeddedartists	0:0fdadbc3d852	1233	Ret = mci_ExecuteCmd(SD_CMD3_SET_RELATIVE_ADDR, CMD3_RCA(addr), &Response);
embeddedartists	0:0fdadbc3d852	1234	if (Ret == SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	1235	if (mci_CheckR1Response(Response.Data[0], &Ret)) {
embeddedartists	0:0fdadbc3d852	1236	return Ret;
embeddedartists	0:0fdadbc3d852	1237	}
embeddedartists	0:0fdadbc3d852	1238	}
embeddedartists	0:0fdadbc3d852	1239	RetryCnt--;
embeddedartists	0:0fdadbc3d852	1240	}
embeddedartists	0:0fdadbc3d852	1241	return Ret;
embeddedartists	0:0fdadbc3d852	1242	}
embeddedartists	0:0fdadbc3d852	1243
embeddedartists	0:0fdadbc3d852	1244	MCIFileSystem::ReturnCode MCIFileSystem::mci_GetAddr(uint16_t *pRCA) const
embeddedartists	0:0fdadbc3d852	1245	{
embeddedartists	0:0fdadbc3d852	1246	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:0fdadbc3d852	1247	response_t Response;
embeddedartists	0:0fdadbc3d852	1248	uint32_t RetryCnt = 20;
embeddedartists	0:0fdadbc3d852	1249
embeddedartists	0:0fdadbc3d852	1250	*pRCA = 0;
embeddedartists	0:0fdadbc3d852	1251	while (RetryCnt > 0) {
embeddedartists	0:0fdadbc3d852	1252	Ret = mci_ExecuteCmd(SD_CMD3_SEND_RELATIVE_ADDR, 0, &Response);
embeddedartists	0:0fdadbc3d852	1253	if (Ret == SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	1254	if (!(CMDRESP_R6_CARD_STATUS(Response.Data[0]) & R1_READY_FOR_DATA)) {
embeddedartists	0:0fdadbc3d852	1255	Ret = SDC_RET_NOT_READY;
embeddedartists	0:0fdadbc3d852	1256	}
embeddedartists	0:0fdadbc3d852	1257	else if (R1_CURRENT_STATE(CMDRESP_R6_CARD_STATUS(Response.Data[0])) != SDMMC_STBY_ST) {
embeddedartists	0:0fdadbc3d852	1258	Ret = SDC_RET_ERR_STATE;
embeddedartists	0:0fdadbc3d852	1259	}
embeddedartists	0:0fdadbc3d852	1260	else {
embeddedartists	0:0fdadbc3d852	1261	*pRCA = CMDRESP_R6_RCA_VAL(Response.Data[0]);
embeddedartists	0:0fdadbc3d852	1262	return SDC_RET_OK;
embeddedartists	0:0fdadbc3d852	1263	}
embeddedartists	0:0fdadbc3d852	1264	}
embeddedartists	0:0fdadbc3d852	1265	RetryCnt--;
embeddedartists	0:0fdadbc3d852	1266	}
embeddedartists	0:0fdadbc3d852	1267	return Ret;
embeddedartists	0:0fdadbc3d852	1268	}
embeddedartists	0:0fdadbc3d852	1269
embeddedartists	0:0fdadbc3d852	1270	MCIFileSystem::ReturnCode MCIFileSystem::mci_GetCSD(uint16_t rca, uint32_t *pCSD) const
embeddedartists	0:0fdadbc3d852	1271	{
embeddedartists	0:0fdadbc3d852	1272	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:0fdadbc3d852	1273	response_t Response;
embeddedartists	0:0fdadbc3d852	1274	uint32_t RetryCnt = 20;
embeddedartists	0:0fdadbc3d852	1275
embeddedartists	0:0fdadbc3d852	1276	while (RetryCnt > 0) {
embeddedartists	0:0fdadbc3d852	1277	Ret = mci_ExecuteCmd(SD_CMD9_SEND_CSD, CMD9_RCA(rca), &Response);
embeddedartists	0:0fdadbc3d852	1278	if (Ret == SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	1279	pCSD[3] = Response.Data[0];
embeddedartists	0:0fdadbc3d852	1280	pCSD[2] = Response.Data[1];
embeddedartists	0:0fdadbc3d852	1281	pCSD[1] = Response.Data[2];
embeddedartists	0:0fdadbc3d852	1282	pCSD[0] = Response.Data[3];
embeddedartists	0:0fdadbc3d852	1283	return Ret;
embeddedartists	0:0fdadbc3d852	1284	}
embeddedartists	0:0fdadbc3d852	1285	RetryCnt--;
embeddedartists	0:0fdadbc3d852	1286	}
embeddedartists	0:0fdadbc3d852	1287	return Ret;
embeddedartists	0:0fdadbc3d852	1288	}
embeddedartists	0:0fdadbc3d852	1289
embeddedartists	0:0fdadbc3d852	1290	MCIFileSystem::ReturnCode MCIFileSystem::mci_SelectCard(uint16_t addr) const
embeddedartists	0:0fdadbc3d852	1291	{
embeddedartists	0:0fdadbc3d852	1292	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:0fdadbc3d852	1293	response_t Response;
embeddedartists	0:0fdadbc3d852	1294	uint32_t RetryCnt = 20;
embeddedartists	0:0fdadbc3d852	1295
embeddedartists	0:0fdadbc3d852	1296	while (RetryCnt > 0) {
embeddedartists	0:0fdadbc3d852	1297	Ret = mci_ExecuteCmd(SD_CMD7_SELECT_CARD, CMD7_RCA(addr), &Response);
embeddedartists	0:0fdadbc3d852	1298	if (Ret == SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	1299	if (mci_CheckR1Response(Response.Data[0], &Ret)) {
embeddedartists	0:0fdadbc3d852	1300	return Ret;
embeddedartists	0:0fdadbc3d852	1301	}
embeddedartists	0:0fdadbc3d852	1302	}
embeddedartists	0:0fdadbc3d852	1303	RetryCnt--;
embeddedartists	0:0fdadbc3d852	1304	}
embeddedartists	0:0fdadbc3d852	1305	return Ret;
embeddedartists	0:0fdadbc3d852	1306	}
embeddedartists	0:0fdadbc3d852	1307
embeddedartists	0:0fdadbc3d852	1308	MCIFileSystem::ReturnCode MCIFileSystem::mci_GetStatus(uint16_t rca, uint32_t *pStatus) const
embeddedartists	0:0fdadbc3d852	1309	{
embeddedartists	0:0fdadbc3d852	1310	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:0fdadbc3d852	1311	response_t Response;
embeddedartists	0:0fdadbc3d852	1312	uint32_t RetryCnt = 20;
embeddedartists	0:0fdadbc3d852	1313
embeddedartists	0:0fdadbc3d852	1314	*pStatus = (uint32_t) -1;
embeddedartists	0:0fdadbc3d852	1315	while (RetryCnt > 0) {
embeddedartists	0:0fdadbc3d852	1316	Ret = mci_ExecuteCmd(SD_CMD13_SEND_STATUS, CMD13_RCA(rca), &Response);
embeddedartists	0:0fdadbc3d852	1317	if (Ret == SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	1318	mci_CheckR1Response(Response.Data[0], &Ret);
embeddedartists	0:0fdadbc3d852	1319	*pStatus = Response.Data[0];
embeddedartists	0:0fdadbc3d852	1320	return Ret;
embeddedartists	0:0fdadbc3d852	1321	}
embeddedartists	0:0fdadbc3d852	1322	RetryCnt--;
embeddedartists	0:0fdadbc3d852	1323	}
embeddedartists	0:0fdadbc3d852	1324	return Ret;
embeddedartists	0:0fdadbc3d852	1325	}
embeddedartists	0:0fdadbc3d852	1326
embeddedartists	0:0fdadbc3d852	1327	void MCIFileSystem::mci_ProcessCSD()
embeddedartists	0:0fdadbc3d852	1328	{
embeddedartists	0:0fdadbc3d852	1329	int32_t CSize = 0;
embeddedartists	0:0fdadbc3d852	1330	int32_t CSizeMult = 0;
embeddedartists	0:0fdadbc3d852	1331	int32_t Mult = 0;
embeddedartists	0:0fdadbc3d852	1332
embeddedartists	0:0fdadbc3d852	1333	/* compute block length based on CSD response */
embeddedartists	0:0fdadbc3d852	1334	_sdCardInfo.block_len = 1 << mci_GetBits(80, 83, _sdCardInfo.csd);
embeddedartists	0:0fdadbc3d852	1335
embeddedartists	0:0fdadbc3d852	1336	if ((_sdCardInfo.card_type & CARD_TYPE_HC) && (_sdCardInfo.card_type & CARD_TYPE_SD)) {
embeddedartists	0:0fdadbc3d852	1337	/* See section 5.3.3 CSD Register (CSD Version 2.0) of SD2.0 spec an explanation for the calculation of these values */
embeddedartists	0:0fdadbc3d852	1338	CSize = mci_GetBits(48, 63, (uint32_t *) _sdCardInfo.csd) + 1;
embeddedartists	0:0fdadbc3d852	1339	_sdCardInfo.blocknr = CSize << 10; /* 512 byte blocks */
embeddedartists	0:0fdadbc3d852	1340	}
embeddedartists	0:0fdadbc3d852	1341	else {
embeddedartists	0:0fdadbc3d852	1342	/* See section 5.3 of the 4.1 revision of the MMC specs for an explanation for the calculation of these values */
embeddedartists	0:0fdadbc3d852	1343	CSize = mci_GetBits(62, 73, (uint32_t *) _sdCardInfo.csd);
embeddedartists	0:0fdadbc3d852	1344	CSizeMult = mci_GetBits(47, 49, (uint32_t *) _sdCardInfo.csd);
embeddedartists	0:0fdadbc3d852	1345	Mult = 1 << (CSizeMult + 2);
embeddedartists	0:0fdadbc3d852	1346	_sdCardInfo.blocknr = (CSize + 1) * Mult;
embeddedartists	0:0fdadbc3d852	1347
embeddedartists	0:0fdadbc3d852	1348	/* adjust blocknr to 512/block */
embeddedartists	0:0fdadbc3d852	1349	if (_sdCardInfo.block_len > MMC_SECTOR_SIZE) {
embeddedartists	0:0fdadbc3d852	1350	_sdCardInfo.blocknr = _sdCardInfo.blocknr * (_sdCardInfo.block_len >> 9);
embeddedartists	0:0fdadbc3d852	1351	}
embeddedartists	0:0fdadbc3d852	1352	}
embeddedartists	0:0fdadbc3d852	1353
embeddedartists	0:0fdadbc3d852	1354	_sdCardInfo.device_size = _sdCardInfo.blocknr << 9; /* blocknr * 512 */
embeddedartists	0:0fdadbc3d852	1355	}
embeddedartists	0:0fdadbc3d852	1356
embeddedartists	0:0fdadbc3d852	1357	MCIFileSystem::ReturnCode MCIFileSystem::mci_SetBusWidth(uint16_t rca, uint8_t width) const
embeddedartists	0:0fdadbc3d852	1358	{
embeddedartists	0:0fdadbc3d852	1359	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:0fdadbc3d852	1360	response_t Response;
embeddedartists	0:0fdadbc3d852	1361	uint8_t RetryCnt = 0x20;
embeddedartists	0:0fdadbc3d852	1362
embeddedartists	0:0fdadbc3d852	1363	while (RetryCnt > 0) {
embeddedartists	0:0fdadbc3d852	1364	Ret = mci_SendAppCmd(rca);
embeddedartists	0:0fdadbc3d852	1365	if (Ret == SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	1366	Ret = mci_ExecuteCmd(SD_ACMD6_SET_BUS_WIDTH, ACMD6_BUS_WIDTH(width), &Response);
embeddedartists	0:0fdadbc3d852	1367	if (Ret == SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	1368	if (mci_CheckR1Response(Response.Data[0], &Ret)) {
embeddedartists	0:0fdadbc3d852	1369	return Ret;
embeddedartists	0:0fdadbc3d852	1370	}
embeddedartists	0:0fdadbc3d852	1371	}
embeddedartists	0:0fdadbc3d852	1372	}
embeddedartists	0:0fdadbc3d852	1373	RetryCnt--;
embeddedartists	0:0fdadbc3d852	1374	}
embeddedartists	0:0fdadbc3d852	1375	return SDC_RET_FAILED;
embeddedartists	0:0fdadbc3d852	1376	}
embeddedartists	0:0fdadbc3d852	1377
embeddedartists	0:0fdadbc3d852	1378	MCIFileSystem::ReturnCode MCIFileSystem::mci_SetTranState(uint16_t rca) const
embeddedartists	0:0fdadbc3d852	1379	{
embeddedartists	0:0fdadbc3d852	1380	ReturnCode Ret = SDC_RET_OK;
embeddedartists	0:0fdadbc3d852	1381	uint32_t status = 0;
embeddedartists	0:0fdadbc3d852	1382	SDMMC_STATE_T state;
embeddedartists	0:0fdadbc3d852	1383
embeddedartists	0:0fdadbc3d852	1384	/* get current state of the card */
embeddedartists	0:0fdadbc3d852	1385	Ret = mci_GetStatus(rca, &status);
embeddedartists	0:0fdadbc3d852	1386	if (Ret != SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	1387	/* unable to get the card state. So return immediatly. */
embeddedartists	0:0fdadbc3d852	1388	return Ret;
embeddedartists	0:0fdadbc3d852	1389	}
embeddedartists	0:0fdadbc3d852	1390
embeddedartists	0:0fdadbc3d852	1391	/* check card state in response */
embeddedartists	0:0fdadbc3d852	1392	state = (SDMMC_STATE_T) R1_CURRENT_STATE(status);
embeddedartists	0:0fdadbc3d852	1393	switch (state) {
embeddedartists	0:0fdadbc3d852	1394	case SDMMC_STBY_ST:
embeddedartists	0:0fdadbc3d852	1395	/* put card in 'Trans' state */
embeddedartists	0:0fdadbc3d852	1396	Ret = mci_SelectCard(rca);
embeddedartists	0:0fdadbc3d852	1397	if (Ret != SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	1398	/* unable to put the card in Trans state. So return immediatly. */
embeddedartists	0:0fdadbc3d852	1399	return Ret;
embeddedartists	0:0fdadbc3d852	1400	}
embeddedartists	0:0fdadbc3d852	1401	mci_GetStatus(rca, &status);
embeddedartists	0:0fdadbc3d852	1402	if (((SDMMC_STATE_T) R1_CURRENT_STATE(status)) != SDMMC_TRAN_ST) {
embeddedartists	0:0fdadbc3d852	1403	return SDC_RET_ERR_STATE;
embeddedartists	0:0fdadbc3d852	1404	}
embeddedartists	0:0fdadbc3d852	1405	break;
embeddedartists	0:0fdadbc3d852	1406
embeddedartists	0:0fdadbc3d852	1407	case SDMMC_TRAN_ST:
embeddedartists	0:0fdadbc3d852	1408	/do nothing /
embeddedartists	0:0fdadbc3d852	1409	break;
embeddedartists	0:0fdadbc3d852	1410
embeddedartists	0:0fdadbc3d852	1411	default:
embeddedartists	0:0fdadbc3d852	1412	/* card shouldn't be in other states so return */
embeddedartists	0:0fdadbc3d852	1413	return SDC_RET_ERR_STATE;
embeddedartists	0:0fdadbc3d852	1414	}
embeddedartists	0:0fdadbc3d852	1415
embeddedartists	0:0fdadbc3d852	1416	return SDC_RET_OK;
embeddedartists	0:0fdadbc3d852	1417	}
embeddedartists	0:0fdadbc3d852	1418
embeddedartists	0:0fdadbc3d852	1419	MCIFileSystem::ReturnCode MCIFileSystem::mci_SetBlockLength(uint32_t rca, uint32_t block_len) const
embeddedartists	0:0fdadbc3d852	1420	{
embeddedartists	0:0fdadbc3d852	1421	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:0fdadbc3d852	1422	response_t Response;
embeddedartists	0:0fdadbc3d852	1423	uint8_t RetryCnt = 0x20;
embeddedartists	0:0fdadbc3d852	1424
embeddedartists	0:0fdadbc3d852	1425	while (RetryCnt > 0) {
embeddedartists	0:0fdadbc3d852	1426	Ret = mci_ExecuteCmd(SD_CMD16_SET_BLOCKLEN, block_len, &Response);
embeddedartists	0:0fdadbc3d852	1427	if (Ret == SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	1428	if (mci_CheckR1Response(Response.Data[0], &Ret)) {
embeddedartists	0:0fdadbc3d852	1429	return Ret;
embeddedartists	0:0fdadbc3d852	1430	}
embeddedartists	0:0fdadbc3d852	1431	}
embeddedartists	0:0fdadbc3d852	1432	RetryCnt--;
embeddedartists	0:0fdadbc3d852	1433	}
embeddedartists	0:0fdadbc3d852	1434	return SDC_RET_FAILED;
embeddedartists	0:0fdadbc3d852	1435	}
embeddedartists	0:0fdadbc3d852	1436
embeddedartists	0:0fdadbc3d852	1437	MCIFileSystem::ReturnCode MCIFileSystem::mci_SetCardParams() const
embeddedartists	0:0fdadbc3d852	1438	{
embeddedartists	0:0fdadbc3d852	1439	ReturnCode Ret;
embeddedartists	0:0fdadbc3d852	1440
embeddedartists	0:0fdadbc3d852	1441	mci_SetClock(SDC_TRAN_CLOCK_RATE);
embeddedartists	0:0fdadbc3d852	1442	if (_sdCardInfo.card_type & CARD_TYPE_SD) {
embeddedartists	0:0fdadbc3d852	1443	mci_ClockControl(SDC_CLOCK_WIDEBUS_MODE, true);
embeddedartists	0:0fdadbc3d852	1444	Ret = mci_SetBusWidth(_sdCardInfo.rca, ACMD6_BUS_WIDTH_4);
embeddedartists	0:0fdadbc3d852	1445	if (Ret != SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	1446	return Ret;
embeddedartists	0:0fdadbc3d852	1447	}
embeddedartists	0:0fdadbc3d852	1448	}
embeddedartists	0:0fdadbc3d852	1449	else {
embeddedartists	0:0fdadbc3d852	1450	mci_ClockControl(SDC_CLOCK_WIDEBUS_MODE, false);
embeddedartists	0:0fdadbc3d852	1451	}
embeddedartists	0:0fdadbc3d852	1452
embeddedartists	0:0fdadbc3d852	1453	/* set block length */
embeddedartists	0:0fdadbc3d852	1454	Ret = mci_SetBlockLength(_sdCardInfo.rca, MMC_SECTOR_SIZE);
embeddedartists	0:0fdadbc3d852	1455	return Ret;
embeddedartists	0:0fdadbc3d852	1456	}
embeddedartists	0:0fdadbc3d852	1457
embeddedartists	0:0fdadbc3d852	1458	bool MCIFileSystem::mci_CheckR1Response(uint32_t resp, ReturnCode* pCheckResult) const
embeddedartists	0:0fdadbc3d852	1459	{
embeddedartists	0:0fdadbc3d852	1460	bool Ret = true;
embeddedartists	0:0fdadbc3d852	1461
embeddedartists	0:0fdadbc3d852	1462	if (!(resp & R1_READY_FOR_DATA)) {
embeddedartists	0:0fdadbc3d852	1463	*pCheckResult = SDC_RET_NOT_READY;
embeddedartists	0:0fdadbc3d852	1464	Ret = false;
embeddedartists	0:0fdadbc3d852	1465	}
embeddedartists	0:0fdadbc3d852	1466	else if (R1_STATUS(resp)) {
embeddedartists	0:0fdadbc3d852	1467	*pCheckResult = SDC_RET_FAILED;
embeddedartists	0:0fdadbc3d852	1468	}
embeddedartists	0:0fdadbc3d852	1469	else {
embeddedartists	0:0fdadbc3d852	1470	*pCheckResult = SDC_RET_OK;
embeddedartists	0:0fdadbc3d852	1471	}
embeddedartists	0:0fdadbc3d852	1472	return Ret;
embeddedartists	0:0fdadbc3d852	1473	}
embeddedartists	0:0fdadbc3d852	1474
embeddedartists	0:0fdadbc3d852	1475	void MCIFileSystem::mci_WriteDelay() const
embeddedartists	0:0fdadbc3d852	1476	{
embeddedartists	0:0fdadbc3d852	1477	// volatile uint8_t i;
embeddedartists	0:0fdadbc3d852	1478	// for ( i = 0; i < 0x10; i++ ) { /* delay 3MCLK + 2PCLK */
embeddedartists	0:0fdadbc3d852	1479	// }
embeddedartists	0:0fdadbc3d852	1480	wait(0.00001f); /* delay 10 us */
embeddedartists	0:0fdadbc3d852	1481	}
embeddedartists	0:0fdadbc3d852	1482
embeddedartists	0:0fdadbc3d852	1483	MCIFileSystem::ReturnCode MCIFileSystem::mci_SendCmd(uint32_t Command, uint32_t Arg, uint32_t timeout) const
embeddedartists	0:0fdadbc3d852	1484	{
embeddedartists	0:0fdadbc3d852	1485	ReturnCode ret = SDC_RET_TIMEOUT;
embeddedartists	0:0fdadbc3d852	1486	uint32_t Status;
embeddedartists	0:0fdadbc3d852	1487
embeddedartists	0:0fdadbc3d852	1488	/* Set Command Info */
embeddedartists	0:0fdadbc3d852	1489	mci_SetCommand(Command, Arg);
embeddedartists	0:0fdadbc3d852	1490
embeddedartists	0:0fdadbc3d852	1491	while (timeout) {
embeddedartists	0:0fdadbc3d852	1492
embeddedartists	0:0fdadbc3d852	1493	Status = LPC_MCI->STATUS;
embeddedartists	0:0fdadbc3d852	1494
embeddedartists	0:0fdadbc3d852	1495	/* check if command was sent */
embeddedartists	0:0fdadbc3d852	1496	if (((Command & SDC_COMMAND_RSP_BITMASK) == SDC_COMMAND_NO_RSP) && (Status & SDC_STATUS_CMDSENT)) {
embeddedartists	0:0fdadbc3d852	1497	ret = SDC_RET_OK;
embeddedartists	0:0fdadbc3d852	1498	break;
embeddedartists	0:0fdadbc3d852	1499	}
embeddedartists	0:0fdadbc3d852	1500	/* check if response was received */
embeddedartists	0:0fdadbc3d852	1501	if (Status & SDC_STATUS_CMDRESPEND) {
embeddedartists	0:0fdadbc3d852	1502	ret = SDC_RET_OK;
embeddedartists	0:0fdadbc3d852	1503	break;
embeddedartists	0:0fdadbc3d852	1504	}
embeddedartists	0:0fdadbc3d852	1505
embeddedartists	0:0fdadbc3d852	1506	/* check command sending status */
embeddedartists	0:0fdadbc3d852	1507	if (Status & SDC_STATUS_CMDERR) {
embeddedartists	0:0fdadbc3d852	1508	if (Status & SDC_STATUS_CMDCRCFAIL) {
embeddedartists	0:0fdadbc3d852	1509	if ((SDC_COMMAND_INDEX(Command) == MMC_SEND_OP_COND) \|\|
embeddedartists	0:0fdadbc3d852	1510	(SDC_COMMAND_INDEX(Command) == SD_APP_OP_COND) \|\|
embeddedartists	0:0fdadbc3d852	1511	(SDC_COMMAND_INDEX(Command) == MMC_STOP_TRANSMISSION)) {
embeddedartists	0:0fdadbc3d852	1512	ret = SDC_RET_OK; /* ignore CRC error if it's a resp for SEND_OP_COND or STOP_TRANSMISSION. */
embeddedartists	0:0fdadbc3d852	1513	break;
embeddedartists	0:0fdadbc3d852	1514	}
embeddedartists	0:0fdadbc3d852	1515	}
embeddedartists	0:0fdadbc3d852	1516	ret = SDC_RET_CMD_FAILED;
embeddedartists	0:0fdadbc3d852	1517	break;
embeddedartists	0:0fdadbc3d852	1518	}
embeddedartists	0:0fdadbc3d852	1519
embeddedartists	0:0fdadbc3d852	1520	timeout--;
embeddedartists	0:0fdadbc3d852	1521	}
embeddedartists	0:0fdadbc3d852	1522
embeddedartists	0:0fdadbc3d852	1523	mci_ResetCommand();
embeddedartists	0:0fdadbc3d852	1524
embeddedartists	0:0fdadbc3d852	1525	return ret;
embeddedartists	0:0fdadbc3d852	1526	}
embeddedartists	0:0fdadbc3d852	1527
embeddedartists	0:0fdadbc3d852	1528	MCIFileSystem::ReturnCode MCIFileSystem::mci_SendAppCmd(uint16_t rca) const
embeddedartists	0:0fdadbc3d852	1529	{
embeddedartists	0:0fdadbc3d852	1530	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:0fdadbc3d852	1531	response_t Response;
embeddedartists	0:0fdadbc3d852	1532	uint32_t RetryCnt = 20;
embeddedartists	0:0fdadbc3d852	1533
embeddedartists	0:0fdadbc3d852	1534	while (RetryCnt > 0) {
embeddedartists	0:0fdadbc3d852	1535	Ret = mci_ExecuteCmd(SD_CMD55_APP_CMD, CMD55_RCA(rca), &Response);
embeddedartists	0:0fdadbc3d852	1536	if (Ret == SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	1537	if (mci_CheckR1Response(Response.Data[0], &Ret)) {
embeddedartists	0:0fdadbc3d852	1538	if (Ret != SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	1539	return Ret;
embeddedartists	0:0fdadbc3d852	1540	}
embeddedartists	0:0fdadbc3d852	1541	if (Response.Data[0] & R1_APP_CMD) {
embeddedartists	0:0fdadbc3d852	1542	return SDC_RET_OK;
embeddedartists	0:0fdadbc3d852	1543	}
embeddedartists	0:0fdadbc3d852	1544	else {
embeddedartists	0:0fdadbc3d852	1545	Ret = SDC_RET_FAILED;
embeddedartists	0:0fdadbc3d852	1546	}
embeddedartists	0:0fdadbc3d852	1547	}
embeddedartists	0:0fdadbc3d852	1548	}
embeddedartists	0:0fdadbc3d852	1549	RetryCnt--;
embeddedartists	0:0fdadbc3d852	1550	}
embeddedartists	0:0fdadbc3d852	1551	return SDC_RET_FAILED;
embeddedartists	0:0fdadbc3d852	1552	}
embeddedartists	0:0fdadbc3d852	1553
embeddedartists	0:0fdadbc3d852	1554	void MCIFileSystem::mci_SetDataTransfer(uint16_t BlockNum, bool DirFromCard, uint32_t Timeout) const
embeddedartists	0:0fdadbc3d852	1555	{
embeddedartists	0:0fdadbc3d852	1556	uint32_t DataCtrl = 0;
embeddedartists	0:0fdadbc3d852	1557	LPC_MCI->DATATMR = Timeout;
embeddedartists	0:0fdadbc3d852	1558	LPC_MCI->DATALEN = BlockNum * 512;
embeddedartists	0:0fdadbc3d852	1559
embeddedartists	0:0fdadbc3d852	1560	DataCtrl = SDC_DATACTRL_ENABLE;
embeddedartists	0:0fdadbc3d852	1561	// DataCtrl mode=block, block size=512byte
embeddedartists	0:0fdadbc3d852	1562	DataCtrl \|= (0x9 << 4);
embeddedartists	0:0fdadbc3d852	1563	if (DirFromCard) {
embeddedartists	0:0fdadbc3d852	1564	DataCtrl \|= (0x1 << 1);
embeddedartists	0:0fdadbc3d852	1565	}
embeddedartists	0:0fdadbc3d852	1566	DataCtrl \|= SDC_DATACTRL_DMA_ENABLE;
embeddedartists	0:0fdadbc3d852	1567	LPC_MCI->DATACTRL = DataCtrl;
embeddedartists	0:0fdadbc3d852	1568	mci_WriteDelay();
embeddedartists	0:0fdadbc3d852	1569	}
embeddedartists	0:0fdadbc3d852	1570
embeddedartists	0:0fdadbc3d852	1571	void MCIFileSystem::mci_GetResp(response_t* pResp) const
embeddedartists	0:0fdadbc3d852	1572	{
embeddedartists	0:0fdadbc3d852	1573	pResp->CmdIndex = SDC_RESPCOMMAND_VAL(LPC_MCI->RESP_CMD);
embeddedartists	0:0fdadbc3d852	1574	pResp->Data[0] = LPC_MCI->RESP0;
embeddedartists	0:0fdadbc3d852	1575	if (CardStatusNumBytes == 4) {
embeddedartists	0:0fdadbc3d852	1576	pResp->Data[1] = LPC_MCI->RESP1;
embeddedartists	0:0fdadbc3d852	1577	pResp->Data[2] = LPC_MCI->RESP2;
embeddedartists	0:0fdadbc3d852	1578	pResp->Data[3] = LPC_MCI->RESP3;
embeddedartists	0:0fdadbc3d852	1579	}
embeddedartists	0:0fdadbc3d852	1580	}
embeddedartists	0:0fdadbc3d852	1581
embeddedartists	0:0fdadbc3d852	1582	uint32_t MCIFileSystem::mci_GetBits(int32_t start, int32_t end, uint32_t *data) const
embeddedartists	0:0fdadbc3d852	1583	{
embeddedartists	0:0fdadbc3d852	1584	uint32_t v;
embeddedartists	0:0fdadbc3d852	1585	uint32_t i = end >> 5;
embeddedartists	0:0fdadbc3d852	1586	uint32_t j = start & 0x1f;
embeddedartists	0:0fdadbc3d852	1587
embeddedartists	0:0fdadbc3d852	1588	if (i == (start >> 5)) {
embeddedartists	0:0fdadbc3d852	1589	v = (data[i] >> j);
embeddedartists	0:0fdadbc3d852	1590	}
embeddedartists	0:0fdadbc3d852	1591	else {
embeddedartists	0:0fdadbc3d852	1592	v = ((data[i] << (32 - j)) \| (data[start >> 5] >> j));
embeddedartists	0:0fdadbc3d852	1593	}
embeddedartists	0:0fdadbc3d852	1594
embeddedartists	0:0fdadbc3d852	1595	return v & ((1 << (end - start + 1)) - 1);
embeddedartists	0:0fdadbc3d852	1596	}
embeddedartists	0:0fdadbc3d852	1597
embeddedartists	0:0fdadbc3d852	1598	void MCIFileSystem::mci_SetCommand(uint32_t Cmd, uint32_t Arg) const
embeddedartists	0:0fdadbc3d852	1599	{
embeddedartists	0:0fdadbc3d852	1600	/* Clear status register */
embeddedartists	0:0fdadbc3d852	1601	LPC_MCI->CLEAR = SDC_CLEAR_ALL;
embeddedartists	0:0fdadbc3d852	1602
embeddedartists	0:0fdadbc3d852	1603	/* Set the argument first, finally command */
embeddedartists	0:0fdadbc3d852	1604	LPC_MCI->ARGUMENT = Arg;
embeddedartists	0:0fdadbc3d852	1605
embeddedartists	0:0fdadbc3d852	1606	/* Write command value, enable the command */
embeddedartists	0:0fdadbc3d852	1607	LPC_MCI->COMMAND = Cmd \| SDC_COMMAND_ENABLE;
embeddedartists	0:0fdadbc3d852	1608
embeddedartists	0:0fdadbc3d852	1609	mci_WriteDelay();
embeddedartists	0:0fdadbc3d852	1610	}
embeddedartists	0:0fdadbc3d852	1611
embeddedartists	0:0fdadbc3d852	1612	void MCIFileSystem::mci_ResetCommand() const
embeddedartists	0:0fdadbc3d852	1613	{
embeddedartists	0:0fdadbc3d852	1614	LPC_MCI->CLEAR = SDC_CLEAR_ALL;
embeddedartists	0:0fdadbc3d852	1615
embeddedartists	0:0fdadbc3d852	1616	LPC_MCI->ARGUMENT = 0xFFFFFFFF;
embeddedartists	0:0fdadbc3d852	1617
embeddedartists	0:0fdadbc3d852	1618	LPC_MCI->COMMAND = 0;
embeddedartists	0:0fdadbc3d852	1619
embeddedartists	0:0fdadbc3d852	1620	mci_WriteDelay();
embeddedartists	0:0fdadbc3d852	1621	}
embeddedartists	0:0fdadbc3d852	1622
embeddedartists	0:0fdadbc3d852	1623	int32_t MCIFileSystem::mci_IRQHandler(uint8_t txBuf, uint32_t txCnt, uint8_t rxBuf, uint32_t rxCnt)
embeddedartists	0:0fdadbc3d852	1624	{
embeddedartists	0:0fdadbc3d852	1625	uint32_t Status;
embeddedartists	0:0fdadbc3d852	1626
embeddedartists	0:0fdadbc3d852	1627	Status = LPC_MCI->STATUS;
embeddedartists	0:0fdadbc3d852	1628
embeddedartists	0:0fdadbc3d852	1629	if ( Status & SDC_STATUS_DATAERR) {
embeddedartists	0:0fdadbc3d852	1630	LPC_MCI->CLEAR = SDC_STATUS_DATAERR;
embeddedartists	0:0fdadbc3d852	1631	return -1; /* Data transfer error */
embeddedartists	0:0fdadbc3d852	1632	}
embeddedartists	0:0fdadbc3d852	1633
embeddedartists	0:0fdadbc3d852	1634	if ( Status & SDC_STATUS_DATAEND) {
embeddedartists	0:0fdadbc3d852	1635	LPC_MCI->CLEAR = SDC_STATUS_DATAEND;
embeddedartists	0:0fdadbc3d852	1636	LPC_MCI->MASK0 = 0;
embeddedartists	0:0fdadbc3d852	1637	return 0;
embeddedartists	0:0fdadbc3d852	1638	}
embeddedartists	0:0fdadbc3d852	1639
embeddedartists	0:0fdadbc3d852	1640	if ( Status & SDC_STATUS_DATABLOCKEND) {
embeddedartists	0:0fdadbc3d852	1641	LPC_MCI->CLEAR = SDC_STATUS_DATABLOCKEND;
embeddedartists	0:0fdadbc3d852	1642	return 1;
embeddedartists	0:0fdadbc3d852	1643	}
embeddedartists	0:0fdadbc3d852	1644
embeddedartists	0:0fdadbc3d852	1645	if (Status & SDC_STATUS_FIFO) {
embeddedartists	0:0fdadbc3d852	1646	return mci_FIFOIRQHandler(txBuf, txCnt, rxBuf, rxCnt);
embeddedartists	0:0fdadbc3d852	1647	}
embeddedartists	0:0fdadbc3d852	1648
embeddedartists	0:0fdadbc3d852	1649	return 1;
embeddedartists	0:0fdadbc3d852	1650	}
embeddedartists	0:0fdadbc3d852	1651
embeddedartists	0:0fdadbc3d852	1652	int32_t MCIFileSystem::mci_FIFOIRQHandler(uint8_t txBuf, uint32_t txCnt, uint8_t rxBuf, uint32_t rxCnt)
embeddedartists	0:0fdadbc3d852	1653	{
embeddedartists	0:0fdadbc3d852	1654	uint32_t Status;
embeddedartists	0:0fdadbc3d852	1655	Status = LPC_MCI->STATUS;
embeddedartists	0:0fdadbc3d852	1656
embeddedartists	0:0fdadbc3d852	1657	if (txBuf) {
embeddedartists	0:0fdadbc3d852	1658	if (Status & SDC_STATUS_TXFIFOHALFEMPTY) {
embeddedartists	0:0fdadbc3d852	1659	if (*txCnt % 64) {
embeddedartists	0:0fdadbc3d852	1660	mci_WriteFIFO((uint32_t ) &txBuf[txCnt], false);
embeddedartists	0:0fdadbc3d852	1661	}
embeddedartists	0:0fdadbc3d852	1662	else {
embeddedartists	0:0fdadbc3d852	1663	mci_WriteFIFO((uint32_t ) &txBuf[txCnt], true);
embeddedartists	0:0fdadbc3d852	1664	}
embeddedartists	0:0fdadbc3d852	1665	*txCnt += 32;
embeddedartists	0:0fdadbc3d852	1666	}
embeddedartists	0:0fdadbc3d852	1667	}
embeddedartists	0:0fdadbc3d852	1668
embeddedartists	0:0fdadbc3d852	1669	if (rxBuf) {
embeddedartists	0:0fdadbc3d852	1670	if (Status & SDC_STATUS_RXFIFOHALFFULL) {
embeddedartists	0:0fdadbc3d852	1671	if (*rxCnt % 64) {
embeddedartists	0:0fdadbc3d852	1672	mci_ReadFIFO((uint32_t ) &rxBuf[rxCnt], false);
embeddedartists	0:0fdadbc3d852	1673	}
embeddedartists	0:0fdadbc3d852	1674	else {
embeddedartists	0:0fdadbc3d852	1675	mci_ReadFIFO((uint32_t ) &rxBuf[rxCnt], true);
embeddedartists	0:0fdadbc3d852	1676	}
embeddedartists	0:0fdadbc3d852	1677	*rxCnt += 32;
embeddedartists	0:0fdadbc3d852	1678	}
embeddedartists	0:0fdadbc3d852	1679	}
embeddedartists	0:0fdadbc3d852	1680
embeddedartists	0:0fdadbc3d852	1681	LPC_MCI->CLEAR = SDC_STATUS_FIFO;
embeddedartists	0:0fdadbc3d852	1682
embeddedartists	0:0fdadbc3d852	1683	return 1;
embeddedartists	0:0fdadbc3d852	1684	}
embeddedartists	0:0fdadbc3d852	1685
embeddedartists	0:0fdadbc3d852	1686	void MCIFileSystem::mci_ReadFIFO(uint32_t *pDst, bool bFirstHalf) const
embeddedartists	0:0fdadbc3d852	1687	{
embeddedartists	0:0fdadbc3d852	1688	uint8_t start = 0, end = 7;
embeddedartists	0:0fdadbc3d852	1689
embeddedartists	0:0fdadbc3d852	1690	if (!bFirstHalf) {
embeddedartists	0:0fdadbc3d852	1691	start += 8;
embeddedartists	0:0fdadbc3d852	1692	end += 8;
embeddedartists	0:0fdadbc3d852	1693	}
embeddedartists	0:0fdadbc3d852	1694	for (; start <= end; start++) {
embeddedartists	0:0fdadbc3d852	1695	*pDst = LPC_MCI->FIFO[start];
embeddedartists	0:0fdadbc3d852	1696	pDst++;
embeddedartists	0:0fdadbc3d852	1697	}
embeddedartists	0:0fdadbc3d852	1698	}
embeddedartists	0:0fdadbc3d852	1699
embeddedartists	0:0fdadbc3d852	1700	void MCIFileSystem::mci_WriteFIFO(uint32_t *pSrc, bool bFirstHalf) const
embeddedartists	0:0fdadbc3d852	1701	{
embeddedartists	0:0fdadbc3d852	1702	uint8_t start = 0, end = 7;
embeddedartists	0:0fdadbc3d852	1703	if (!bFirstHalf) {
embeddedartists	0:0fdadbc3d852	1704	start += 8;
embeddedartists	0:0fdadbc3d852	1705	end += 8;
embeddedartists	0:0fdadbc3d852	1706	}
embeddedartists	0:0fdadbc3d852	1707	for (; start <= end; start++) {
embeddedartists	0:0fdadbc3d852	1708	LPC_MCI->FIFO[start] = *pSrc;
embeddedartists	0:0fdadbc3d852	1709	pSrc++;
embeddedartists	0:0fdadbc3d852	1710	}
embeddedartists	0:0fdadbc3d852	1711	}
embeddedartists	0:0fdadbc3d852	1712
embeddedartists	0:0fdadbc3d852	1713	void MCIFileSystem::mci_SetupEventWakeup(uint8_t dmaChannel)
embeddedartists	0:0fdadbc3d852	1714	{
embeddedartists	0:0fdadbc3d852	1715	/* Wait for IRQ - for an RTOS, you would pend on an event here with a IRQ based wakeup. */
embeddedartists	0:0fdadbc3d852	1716	NVIC_ClearPendingIRQ(DMA_IRQn);
embeddedartists	0:0fdadbc3d852	1717
embeddedartists	0:0fdadbc3d852	1718	_eventDmaChannel = dmaChannel;
embeddedartists	0:0fdadbc3d852	1719	_eventReceived = false;
embeddedartists	0:0fdadbc3d852	1720	_eventSuccess = false;
embeddedartists	0:0fdadbc3d852	1721
embeddedartists	0:0fdadbc3d852	1722	NVIC_EnableIRQ(DMA_IRQn);
embeddedartists	0:0fdadbc3d852	1723	}
embeddedartists	0:0fdadbc3d852	1724
embeddedartists	0:0fdadbc3d852	1725	uint32_t MCIFileSystem::mci_WaitForEvent() const
embeddedartists	0:0fdadbc3d852	1726	{
embeddedartists	0:0fdadbc3d852	1727	/* Wait for the event (DMA or MCI interrupt) for a maximum of 2 seconds */
embeddedartists	0:0fdadbc3d852	1728	uint32_t end = us_ticker_read() + 210001000;
embeddedartists	0:0fdadbc3d852	1729	while ((us_ticker_read() < end) && (!_eventReceived))
embeddedartists	0:0fdadbc3d852	1730	{
embeddedartists	0:0fdadbc3d852	1731	wait(0.01);
embeddedartists	0:0fdadbc3d852	1732	}
embeddedartists	0:0fdadbc3d852	1733
embeddedartists	0:0fdadbc3d852	1734	if (_eventReceived && _eventSuccess) {
embeddedartists	0:0fdadbc3d852	1735	return 0;
embeddedartists	0:0fdadbc3d852	1736	}
embeddedartists	0:0fdadbc3d852	1737
embeddedartists	0:0fdadbc3d852	1738	return 1;
embeddedartists	0:0fdadbc3d852	1739	}
embeddedartists	0:0fdadbc3d852	1740
embeddedartists	0:0fdadbc3d852	1741	MCIFileSystem::ReturnCode MCIFileSystem::_readBlocks(uint32_t card_type, uint32_t startBlock, uint32_t blockNum) const
embeddedartists	0:0fdadbc3d852	1742	{
embeddedartists	0:0fdadbc3d852	1743	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:0fdadbc3d852	1744	response_t Response;
embeddedartists	0:0fdadbc3d852	1745	uint32_t Command, Argument;
embeddedartists	0:0fdadbc3d852	1746	uint8_t RetryCnt = 0x20;
embeddedartists	0:0fdadbc3d852	1747
embeddedartists	0:0fdadbc3d852	1748	if (blockNum == 1) {
embeddedartists	0:0fdadbc3d852	1749	Command = SD_CMD17_READ_SINGLE_BLOCK;
embeddedartists	0:0fdadbc3d852	1750	}
embeddedartists	0:0fdadbc3d852	1751	else {
embeddedartists	0:0fdadbc3d852	1752	Command = SD_CMD18_READ_MULTIPLE_BLOCK;
embeddedartists	0:0fdadbc3d852	1753	}
embeddedartists	0:0fdadbc3d852	1754
embeddedartists	0:0fdadbc3d852	1755	/* Select single or multiple read based on number of blocks */
embeddedartists	0:0fdadbc3d852	1756	/* if high capacity card use block indexing */
embeddedartists	0:0fdadbc3d852	1757	if (card_type & CARD_TYPE_HC) {
embeddedartists	0:0fdadbc3d852	1758	Argument = startBlock;
embeddedartists	0:0fdadbc3d852	1759	}
embeddedartists	0:0fdadbc3d852	1760	else { /fix at 512 bytes/
embeddedartists	0:0fdadbc3d852	1761	Argument = startBlock << 9;
embeddedartists	0:0fdadbc3d852	1762	}
embeddedartists	0:0fdadbc3d852	1763
embeddedartists	0:0fdadbc3d852	1764	while (RetryCnt > 0) {
embeddedartists	0:0fdadbc3d852	1765	Ret = mci_ExecuteCmd(Command, Argument, &Response);
embeddedartists	0:0fdadbc3d852	1766	if (Ret == SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	1767	if (mci_CheckR1Response(Response.Data[0], &Ret)) {
embeddedartists	0:0fdadbc3d852	1768	return Ret;
embeddedartists	0:0fdadbc3d852	1769	}
embeddedartists	0:0fdadbc3d852	1770	}
embeddedartists	0:0fdadbc3d852	1771	RetryCnt--;
embeddedartists	0:0fdadbc3d852	1772	}
embeddedartists	0:0fdadbc3d852	1773	return Ret;
embeddedartists	0:0fdadbc3d852	1774	}
embeddedartists	0:0fdadbc3d852	1775
embeddedartists	0:0fdadbc3d852	1776	MCIFileSystem::ReturnCode MCIFileSystem::_writeBlocks(uint32_t card_type, uint32_t startBlock, uint32_t blockNum) const
embeddedartists	0:0fdadbc3d852	1777	{
embeddedartists	0:0fdadbc3d852	1778	ReturnCode Ret = SDC_RET_FAILED;
embeddedartists	0:0fdadbc3d852	1779	response_t Response;
embeddedartists	0:0fdadbc3d852	1780	uint32_t Command, Argument;
embeddedartists	0:0fdadbc3d852	1781	uint8_t RetryCnt = 0x20;
embeddedartists	0:0fdadbc3d852	1782
embeddedartists	0:0fdadbc3d852	1783	if (blockNum == 1) {
embeddedartists	0:0fdadbc3d852	1784	Command = SD_CMD24_WRITE_BLOCK;
embeddedartists	0:0fdadbc3d852	1785	}
embeddedartists	0:0fdadbc3d852	1786	else {
embeddedartists	0:0fdadbc3d852	1787	Command = SD_CMD25_WRITE_MULTIPLE_BLOCK;
embeddedartists	0:0fdadbc3d852	1788	}
embeddedartists	0:0fdadbc3d852	1789
embeddedartists	0:0fdadbc3d852	1790	/* if high capacity card use block indexing */
embeddedartists	0:0fdadbc3d852	1791	if (card_type & CARD_TYPE_HC) {
embeddedartists	0:0fdadbc3d852	1792	Argument = startBlock;
embeddedartists	0:0fdadbc3d852	1793	}
embeddedartists	0:0fdadbc3d852	1794	else { /fix at 512 bytes/
embeddedartists	0:0fdadbc3d852	1795	Argument = startBlock << 9;
embeddedartists	0:0fdadbc3d852	1796
embeddedartists	0:0fdadbc3d852	1797	}
embeddedartists	0:0fdadbc3d852	1798
embeddedartists	0:0fdadbc3d852	1799	while (RetryCnt > 0) {
embeddedartists	0:0fdadbc3d852	1800	Ret = mci_ExecuteCmd(Command, Argument, &Response);
embeddedartists	0:0fdadbc3d852	1801	if (Ret == SDC_RET_OK) {
embeddedartists	0:0fdadbc3d852	1802	if (mci_CheckR1Response(Response.Data[0], &Ret)) {
embeddedartists	0:0fdadbc3d852	1803	return Ret;
embeddedartists	0:0fdadbc3d852	1804	}
embeddedartists	0:0fdadbc3d852	1805	}
embeddedartists	0:0fdadbc3d852	1806	RetryCnt--;
embeddedartists	0:0fdadbc3d852	1807	}
embeddedartists	0:0fdadbc3d852	1808	return Ret;
embeddedartists	0:0fdadbc3d852	1809	}
embeddedartists	0:0fdadbc3d852	1810

Repository toolbox

Import into Keil Studio

Export to desktop IDE

Repository details

Type:	Library
Created:	29 Jun 2014
Imports:	9
Forks:	0
Commits:	14
Dependents:	1
Dependencies:	1
Followers:	3

MCIFileSystem.cpp@2:1c6134c80dc5, 2013-09-27 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning