robocon_2016 / Mbed 2 deprecated 2016_slave_MD

MD

Dependencies:   i2cslave mbed

main.cpp@2:f2b42e387d08, 2016-09-30 (annotated)

Committer:
sgrsn
Date:
Fri Sep 30 12:30:41 2016 +0000
Revision:
2:f2b42e387d08
Parent:
1:770e1fc380ff 
MD_9/30

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sgrsn 0:41f2e835aa5d 1 #include "mbed.h"
sgrsn 0:41f2e835aa5d 2 #include "i2cslave.h"
sgrsn 0:41f2e835aa5d 3 #include "define.h"
sgrsn 0:41f2e835aa5d 4
sgrsn 0:41f2e835aa5d 5 char Registar[128]= {};
sgrsn 0:41f2e835aa5d 6 void check();
sgrsn 0:41f2e835aa5d 7
sgrsn 0:41f2e835aa5d 8 int main()
sgrsn 0:41f2e835aa5d 9 {
sgrsn 0:41f2e835aa5d 10 BusOut motor1(dp4, dp9, dp13, dp14);
sgrsn 0:41f2e835aa5d 11 BusOut motor2(dp25, dp24, dp18, dp17);
sgrsn 0:41f2e835aa5d 12 PwmOut pwm1(dp2);
sgrsn 0:41f2e835aa5d 13 PwmOut pwm2(dp1);
sgrsn 0:41f2e835aa5d 14 motor1 = 0;
sgrsn 0:41f2e835aa5d 15 motor2 = 0;
sgrsn 0:41f2e835aa5d 16 NVIC_SetPriority(TIMER_16_0_IRQn, 20);
sgrsn 0:41f2e835aa5d 17 NVIC_SetPriority(TIMER_16_1_IRQn, 20);
sgrsn 0:41f2e835aa5d 18 NVIC_SetPriority(TIMER_32_0_IRQn, 20);
sgrsn 0:41f2e835aa5d 19 NVIC_SetPriority(TIMER_32_1_IRQn, 20);
sgrsn 0:41f2e835aa5d 20 NVIC_SetPriority(I2C_IRQn, 10);
sgrsn 0:41f2e835aa5d 21 i2cslave i2c(dp5, dp27, Registar);
sgrsn 0:41f2e835aa5d 22 /*change address every micon***********/
sgrsn 2:f2b42e387d08 23 i2c.address(MD10_addr);
sgrsn 0:41f2e835aa5d 24 /**************************************/
sgrsn 0:41f2e835aa5d 25 i2c.frequency(1000000);
sgrsn 0:41f2e835aa5d 26 Ticker tic;
sgrsn 0:41f2e835aa5d 27 tic.attach(check, 0.1);
sgrsn 1:770e1fc380ff 28 char prev_motor1_state = 0;
sgrsn 1:770e1fc380ff 29 char prev_motor2_state = 0;
sgrsn 0:41f2e835aa5d 30 while(1)
sgrsn 0:41f2e835aa5d 31 {
sgrsn 0:41f2e835aa5d 32 pwm1 = (float)(Registar[motor1_pwm]) / 255;
sgrsn 0:41f2e835aa5d 33 pwm2 = (float)(Registar[motor2_pwm]) / 255;
sgrsn 1:770e1fc380ff 34 if(Registar[motor1_state] != prev_motor1_state)
sgrsn 1:770e1fc380ff 35 {
sgrsn 1:770e1fc380ff 36 motor1 = 0;
sgrsn 1:770e1fc380ff 37 wait_ms(5);
sgrsn 1:770e1fc380ff 38 }
sgrsn 1:770e1fc380ff 39 if(Registar[motor2_state] != prev_motor2_state)
sgrsn 1:770e1fc380ff 40 {
sgrsn 1:770e1fc380ff 41 motor2 = 0;
sgrsn 1:770e1fc380ff 42 wait_ms(1);
sgrsn 1:770e1fc380ff 43 }
sgrsn 0:41f2e835aa5d 44 motor1 = Registar[motor1_state];
sgrsn 0:41f2e835aa5d 45 motor2 = Registar[motor2_state];
sgrsn 1:770e1fc380ff 46 prev_motor1_state = Registar[motor1_state];
sgrsn 1:770e1fc380ff 47 prev_motor2_state = Registar[motor2_state];
sgrsn 0:41f2e835aa5d 48 wait_ms(40);
sgrsn 0:41f2e835aa5d 49 }
sgrsn 0:41f2e835aa5d 50 }
sgrsn 0:41f2e835aa5d 51
sgrsn 0:41f2e835aa5d 52 void check()
sgrsn 0:41f2e835aa5d 53 {
sgrsn 0:41f2e835aa5d 54 Registar[check_reg]++;
sgrsn 0:41f2e835aa5d 55 if(Registar[check_reg] > 2)
sgrsn 0:41f2e835aa5d 56 {
sgrsn 0:41f2e835aa5d 57 NVIC_SystemReset();
sgrsn 0:41f2e835aa5d 58 }
sgrsn 0:41f2e835aa5d 59 }