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Dependents:   Nucleo_L432KC_Quadrature_Decoder_with_ADC_and_DAC

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targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.c@151:5eaa88a5bcc7, 2016-11-24 (annotated)

Committer:
<>
Date:
Thu Nov 24 17:03:03 2016 +0000
Revision:
151:5eaa88a5bcc7
Parent:
150:02e0a0aed4ec
Child:
153:fa9ff456f731
This updates the lib to the mbed lib v130

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ***************************************************************************
<> 149:156823d33999 3 * @file ncs36510_init.c
<> 149:156823d33999 4 * @brief Initialization of Orion SoC
<> 149:156823d33999 5 * @internal
<> 149:156823d33999 6 * @author ON Semiconductor
<> 149:156823d33999 7 * $Rev:
<> 149:156823d33999 8 * $Date: $
<> 149:156823d33999 9 ******************************************************************************
<> 149:156823d33999 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 149:156823d33999 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 149:156823d33999 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 149:156823d33999 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 149:156823d33999 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 149:156823d33999 15 * if applicable the software license agreement. Do not use this software and/or
<> 149:156823d33999 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 149:156823d33999 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 149:156823d33999 18 * terms and conditions.
<> 149:156823d33999 19 *
<> 149:156823d33999 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 149:156823d33999 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 149:156823d33999 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 149:156823d33999 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 149:156823d33999 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 149:156823d33999 25 * @endinternal
<> 149:156823d33999 26 *
<> 149:156823d33999 27 * @ingroup main
<> 149:156823d33999 28 *
<> 149:156823d33999 29 * @details
<> 149:156823d33999 30 */
<> 149:156823d33999 31
<> 149:156823d33999 32 /*************************************************************************************************
<> 149:156823d33999 33 * *
<> 149:156823d33999 34 * Header files *
<> 149:156823d33999 35 * *
<> 149:156823d33999 36 *************************************************************************************************/
<> 149:156823d33999 37 #include "ncs36510Init.h"
<> 149:156823d33999 38
<> 149:156823d33999 39 void fPmuInit(void);
<> 151:5eaa88a5bcc7 40 uint32_t ADC_Trim_Offset;
<> 149:156823d33999 41 /**
<> 149:156823d33999 42 * @brief
<> 149:156823d33999 43 * Hardware trimming function
<> 149:156823d33999 44 * This function copies trim codes from specific flash location
<> 149:156823d33999 45 * where they are stored to proper hw registers.
<> 149:156823d33999 46 */
<> 149:156823d33999 47 boolean fTrim()
<> 149:156823d33999 48 {
<> 151:5eaa88a5bcc7 49 boolean status = False;
<> 149:156823d33999 50
<> 149:156823d33999 51 /**- Check if trim values are present */
<> 149:156823d33999 52 /**- If Trim data is present. Only trim if valid trim values are present. */
<> 149:156823d33999 53 /**- Copy trims in registers */
<> 149:156823d33999 54 if (TRIMREG->REVISION_CODE != 0xFFFFFFFF) {
<> 149:156823d33999 55
<> 151:5eaa88a5bcc7 56 if ( TRIMREG->MAC_ADDR_LOW != 0xFFFFFFFF ) {
<> 151:5eaa88a5bcc7 57 MACHWREG->LONG_ADDRESS_LOW = TRIMREG->MAC_ADDR_LOW;
<> 151:5eaa88a5bcc7 58 }
<> 151:5eaa88a5bcc7 59
<> 151:5eaa88a5bcc7 60 if ( TRIMREG->MAC_ADDR_HIGH != 0xFFFFFFFF ) {
<> 151:5eaa88a5bcc7 61 MACHWREG->LONG_ADDRESS_HIGH = TRIMREG->MAC_ADDR_HIGH;
<> 151:5eaa88a5bcc7 62 }
<> 151:5eaa88a5bcc7 63
<> 149:156823d33999 64 /**- board specific clock trims may only be done when present, writing all 1's is not good */
<> 149:156823d33999 65 if ((TRIMREG->TRIM_32K_EXT & 0xFFFF0000) != 0xFFFF0000) {
<> 151:5eaa88a5bcc7 66 CLOCKREG->TRIM_32K_EXT.WORD = TRIMREG->TRIM_32K_EXT;
<> 149:156823d33999 67 }
<> 149:156823d33999 68
<> 149:156823d33999 69 if ((TRIMREG->TRIM_32M_EXT & 0xFFFF0000) != 0xFFFF0000) {
<> 151:5eaa88a5bcc7 70 CLOCKREG->TRIM_32M_EXT.WORD = TRIMREG->TRIM_32M_EXT;
<> 149:156823d33999 71 }
<> 149:156823d33999 72
<> 149:156823d33999 73 MACHWREG->TX_LENGTH.BITS.TX_PRE_CHIPS = TRIMREG->TX_PRE_CHIPS;
<> 149:156823d33999 74
<> 151:5eaa88a5bcc7 75 if ((TRIMREG->TX_TRIM & 0xFFFF0000) != 0xFFFF0000) {
<> 151:5eaa88a5bcc7 76 RFANATRIMREG->TX_TRIM.WORD = TRIMREG->TX_TRIM;
<> 151:5eaa88a5bcc7 77 }
<> 149:156823d33999 78 RFANATRIMREG->PLL_VCO_TAP_LOCATION = TRIMREG->PLL_VCO_TAP_LOCATION;
<> 149:156823d33999 79 RFANATRIMREG->PLL_TRIM.WORD = TRIMREG->PLL_TRIM;
<> 149:156823d33999 80
<> 149:156823d33999 81 /**- board specific RSSI trims may only be done when present, writing all 1's is not good */
<> 149:156823d33999 82 if ((TRIMREG->RSSI_OFFSET & 0xFFFF0000) != 0xFFFF0000) {
<> 149:156823d33999 83 DMDREG->DMD_CONTROL2.BITS.RSSI_OFFSET = TRIMREG->RSSI_OFFSET;
<> 149:156823d33999 84 }
<> 149:156823d33999 85
<> 149:156823d33999 86 RFANATRIMREG->RX_CHAIN_TRIM = TRIMREG->RX_CHAIN_TRIM;
<> 149:156823d33999 87 RFANATRIMREG->PMU_TRIM = TRIMREG->PMU_TRIM;
<> 149:156823d33999 88 RANDREG->WR_SEED_RD_RAND = TRIMREG->WR_SEED_RD_RAND;
<> 149:156823d33999 89
<> 151:5eaa88a5bcc7 90 /* High side injection settings */
<> 149:156823d33999 91 RFANATRIMREG->RX_VCO_TRIM_LUT1 = TRIMREG->RX_VCO_LUT1.WORD;;
<> 149:156823d33999 92 RFANATRIMREG->RX_VCO_TRIM_LUT2 = TRIMREG->RX_VCO_LUT2.WORD;;
<> 149:156823d33999 93
<> 149:156823d33999 94 RFANATRIMREG->TX_VCO_TRIM_LUT1 = TRIMREG->TX_VCO_LUT1.WORD;;
<> 149:156823d33999 95 RFANATRIMREG->TX_VCO_TRIM_LUT2 = TRIMREG->TX_VCO_LUT2.WORD;;
<> 149:156823d33999 96
<> 151:5eaa88a5bcc7 97 ADC_Trim_Offset = TRIMREG->ADC_OFFSET_TRIM;
<> 151:5eaa88a5bcc7 98
<> 151:5eaa88a5bcc7 99 status = True;
<> 151:5eaa88a5bcc7 100
<> 151:5eaa88a5bcc7 101 } else {
<> 151:5eaa88a5bcc7 102
<> 151:5eaa88a5bcc7 103 return(False);
<> 151:5eaa88a5bcc7 104 }
<> 151:5eaa88a5bcc7 105
<> 151:5eaa88a5bcc7 106 /** Read in user trim values programmed in the flash memory
<> 151:5eaa88a5bcc7 107 The user trim values take precedence over factory trim for MAC address
<> 151:5eaa88a5bcc7 108 */
<> 151:5eaa88a5bcc7 109 if (( USERTRIMREG->MAC_ADDRESS_LOW != 0xFFFFFFFF ) &&
<> 151:5eaa88a5bcc7 110 (USERTRIMREG->MAC_ADDRESS_HIGH != 0xFFFFFFFF)) {
<> 150:02e0a0aed4ec 111
<> 151:5eaa88a5bcc7 112 MACHWREG->LONG_ADDRESS_LOW = USERTRIMREG->MAC_ADDRESS_LOW;
<> 151:5eaa88a5bcc7 113 MACHWREG->LONG_ADDRESS_HIGH = USERTRIMREG->MAC_ADDRESS_HIGH;
<> 151:5eaa88a5bcc7 114 }
<> 151:5eaa88a5bcc7 115
<> 151:5eaa88a5bcc7 116 if (USERTRIMREG->TRIM_32K_EXT != 0xFFFFFFFF) {
<> 151:5eaa88a5bcc7 117 CLOCKREG->TRIM_32K_EXT.WORD = (USERTRIMREG->TRIM_32K_EXT & 0x00000FFF);
<> 151:5eaa88a5bcc7 118 }
<> 149:156823d33999 119
<> 151:5eaa88a5bcc7 120 if (USERTRIMREG->TRIM_32K_EXT != 0xFFFFFFFF) {
<> 151:5eaa88a5bcc7 121 CLOCKREG->TRIM_32K_EXT.WORD = (USERTRIMREG->TRIM_32K_EXT & 0x00000FFF);
<> 149:156823d33999 122 }
<> 151:5eaa88a5bcc7 123
<> 151:5eaa88a5bcc7 124 if (USERTRIMREG->RSSI_OFFSET != 0xFFFFFFFF) {
<> 151:5eaa88a5bcc7 125 DMDREG->DMD_CONTROL2.BITS.RSSI_OFFSET = (USERTRIMREG->RSSI_OFFSET & 0x0000003F);
<> 151:5eaa88a5bcc7 126 }
<> 151:5eaa88a5bcc7 127
<> 151:5eaa88a5bcc7 128 if (USERTRIMREG->TX_TRIM != 0xFFFFFFFF) {
<> 151:5eaa88a5bcc7 129 RFANATRIMREG->TX_TRIM.BITS.TX_TUNE = (USERTRIMREG->TX_TRIM & 0x0000000F);
<> 151:5eaa88a5bcc7 130 }
<> 151:5eaa88a5bcc7 131 return(status);
<> 149:156823d33999 132 }
<> 149:156823d33999 133
<> 149:156823d33999 134 /* See clock.h for documentation. */
<> 149:156823d33999 135 void fClockInit()
<> 149:156823d33999 136 {
<> 149:156823d33999 137
<> 149:156823d33999 138 /** Enable external 32MHz oscillator */
<> 149:156823d33999 139 CLOCKREG->CCR.BITS.OSC_SEL = 1;
<> 149:156823d33999 140
<> 149:156823d33999 141 /** - Wait external 32MHz oscillator to be ready */
<> 149:156823d33999 142 while(CLOCKREG->CSR.BITS.XTAL32M != 1) {} /* If you get stuck here, something is wrong with board or trim values */
<> 149:156823d33999 143
<> 149:156823d33999 144 /** Internal 32MHz calibration \n *//** - Enable internal 32MHz clock */
<> 149:156823d33999 145 PMUREG->CONTROL.BITS.INT32M = 0;
<> 149:156823d33999 146
<> 149:156823d33999 147 /** - Wait 5 uSec for clock to stabilize */
<> 149:156823d33999 148 volatile uint8_t Timer;
<> 149:156823d33999 149 for(Timer = 0; Timer < 10; Timer++);
<> 149:156823d33999 150
<> 149:156823d33999 151 /** - Enable calibration */
<> 149:156823d33999 152 CLOCKREG->CCR.BITS.CAL32M = True;
<> 149:156823d33999 153
<> 149:156823d33999 154 /** - Wait calibration to be completed */
<> 149:156823d33999 155 while(CLOCKREG->CSR.BITS.CAL32MDONE == False); /* If you stuck here, issue with internal 32M calibration */
<> 149:156823d33999 156
<> 149:156823d33999 157 /** - Check calibration status */
<> 149:156823d33999 158 while(CLOCKREG->CSR.BITS.CAL32MFAIL == True); /* If you stuck here, issue with internal 32M calibration */
<> 149:156823d33999 159
<> 149:156823d33999 160 /** - Power down internal 32MHz osc */
<> 149:156823d33999 161 PMUREG->CONTROL.BITS.INT32M = 1;
<> 149:156823d33999 162
<> 149:156823d33999 163 /** Internal 32KHz calibration \n */ /** - Enable internal 32KHz clock */
<> 149:156823d33999 164 PMUREG->CONTROL.BITS.INT32K = 0;
<> 149:156823d33999 165
<> 149:156823d33999 166 /** - Wait 5 uSec for clock to stabilize */
<> 149:156823d33999 167 for(Timer = 0; Timer < 10; Timer++);
<> 149:156823d33999 168
<> 149:156823d33999 169 /** - Enable calibration */
<> 149:156823d33999 170 CLOCKREG->CCR.BITS.CAL32K = True;
<> 149:156823d33999 171
<> 149:156823d33999 172 /** - Wait calibration to be completed */
<> 149:156823d33999 173 while(CLOCKREG->CSR.BITS.DONE32K == False); /* If you stuck here, issue with internal 32K calibration */
<> 149:156823d33999 174
<> 149:156823d33999 175 /** - Check calibration status */
<> 149:156823d33999 176 while(CLOCKREG->CSR.BITS.CAL32K == True); /* If you stuck here, issue with internal 32M calibration */
<> 149:156823d33999 177
<> 149:156823d33999 178 /** - Power down external 32KHz osc */
<> 149:156823d33999 179 PMUREG->CONTROL.BITS.EXT32K = 1;
<> 149:156823d33999 180
<> 149:156823d33999 181 /** Disable all peripheral clocks by default */
<> 149:156823d33999 182 CLOCKREG->PDIS.WORD = 0xFFFFFFFF;
<> 149:156823d33999 183
<> 149:156823d33999 184 /** Set core frequency */
<> 149:156823d33999 185 CLOCKREG->FDIV = CPU_CLOCK_DIV - 1;
<> 149:156823d33999 186 }
<> 149:156823d33999 187
<> 149:156823d33999 188 /* Initializes PMU module */
<> 149:156823d33999 189 void fPmuInit()
<> 149:156823d33999 190 {
<> 149:156823d33999 191 /** Enable the clock for PMU peripheral device */
<> 149:156823d33999 192 CLOCK_ENABLE(CLOCK_PMU);
<> 149:156823d33999 193
<> 149:156823d33999 194 /** Unset wakeup on pending (only enabled irq can wakeup) */
<> 149:156823d33999 195 SCB->SCR &= ~SCB_SCR_SEVONPEND_Msk;
<> 149:156823d33999 196
<> 149:156823d33999 197 /** Unset auto sleep when returning from wakeup irq */
<> 149:156823d33999 198 SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
<> 149:156823d33999 199
<> 149:156823d33999 200 /** Set regulator timings */
<> 150:02e0a0aed4ec 201 PMUREG->FVDD_TSETTLE = 160;
<> 150:02e0a0aed4ec 202 PMUREG->FVDD_TSTARTUP = 400;
<> 150:02e0a0aed4ec 203
<> 149:156823d33999 204
<> 149:156823d33999 205 /** Keep SRAMA & SRAMB powered in coma mode */
<> 149:156823d33999 206 PMUREG->CONTROL.BITS.SRAMA = False;
<> 149:156823d33999 207 PMUREG->CONTROL.BITS.SRAMB = False;
<> 149:156823d33999 208
<> 150:02e0a0aed4ec 209 PMUREG->CONTROL.BITS.N1V1 = True; /* Enable ACTIVE mode switching regulator */
<> 150:02e0a0aed4ec 210 PMUREG->CONTROL.BITS.C1V1 = True; /* Enable COMA mode switching regulator */
<> 149:156823d33999 211
<> 149:156823d33999 212 /** Disable the clock for PMU peripheral device, all settings are done */
<> 149:156823d33999 213 CLOCK_DISABLE(CLOCK_PMU);
<> 149:156823d33999 214 }
<> 149:156823d33999 215
<> 149:156823d33999 216 /* See clock.h for documentation. */
<> 149:156823d33999 217 uint32_t fClockGetPeriphClockfrequency()
<> 149:156823d33999 218 {
<> 149:156823d33999 219 return (CPU_CLOCK_ROOT_HZ / CPU_CLOCK_DIV);
<> 149:156823d33999 220 }
<> 149:156823d33999 221
<> 149:156823d33999 222
<> 149:156823d33999 223 /**
<> 149:156823d33999 224 * @brief
<> 149:156823d33999 225 * Hardware initialization function
<> 149:156823d33999 226 * This function initializes hardware at application start up prior
<> 149:156823d33999 227 * to other initializations or OS operations.
<> 149:156823d33999 228 */
<> 149:156823d33999 229 static void fHwInit(void)
<> 149:156823d33999 230 {
<> 149:156823d33999 231
<> 149:156823d33999 232 /* Trim register settings */
<> 149:156823d33999 233 fTrim();
<> 149:156823d33999 234
<> 149:156823d33999 235 /* Clock setting */
<> 149:156823d33999 236 /** - Initialize clock */
<> 149:156823d33999 237 fClockInit();
<> 149:156823d33999 238
<> 149:156823d33999 239 /** - Initialize pmu */
<> 149:156823d33999 240 fPmuInit();
<> 149:156823d33999 241
<> 149:156823d33999 242 /** Orion has 4 interrupt bits in interrupt priority register
<> 149:156823d33999 243 * The lowest 4 bits are not used.
<> 149:156823d33999 244 *
<> 149:156823d33999 245 @verbatim
<> 149:156823d33999 246 +-----+-----+-----+-----+-----+-----+-----+-----+
<> 149:156823d33999 247 |bit 7|bit 6|bit 5|bit 4|bit 3|bit 2|bit 1|bit 0|
<> 149:156823d33999 248 | | | | | 0 | 0 | 0 | 0 |
<> 149:156823d33999 249 +-----+-----+-----+-----+-----+-----+-----+-----+
<> 149:156823d33999 250 |
<> 149:156823d33999 251 INTERRUPT PRIORITY | NOT IMPLEMENTED,
<> 149:156823d33999 252 | read as 0
<> 149:156823d33999 253 Valid priorities are 0x00, 0x10, 0x20, 0x30
<> 149:156823d33999 254 0x40, 0x50, 0x60, 0x70
<> 149:156823d33999 255 0x80, 0x90, 0xA0, 0xB0
<> 149:156823d33999 256 0xC0, 0xD0, 0xE0, 0xF0
<> 149:156823d33999 257 @endverbatim
<> 149:156823d33999 258 * Lowest number is highest priority
<> 149:156823d33999 259 *
<> 149:156823d33999 260 *
<> 149:156823d33999 261 * This range is defined by
<> 149:156823d33999 262 * configKERNEL_INTERRUPT_PRIORITY (lowest)
<> 149:156823d33999 263 * and configMAX_SYSCALL_INTERRUPT_PRIORITY (highest). All interrupt
<> 149:156823d33999 264 * priorities need to fall in that range.
<> 149:156823d33999 265 *
<> 149:156823d33999 266 * To be future safe, the LSbits of the priority are set to 0xF.
<> 149:156823d33999 267 * This wil lmake sure that if more interrupt bits are used, the
<> 149:156823d33999 268 * priority is maintained.
<> 149:156823d33999 269 */
<> 149:156823d33999 270
<> 149:156823d33999 271 /** - Set IRQs priorities */
<> 149:156823d33999 272 NVIC_SetPriority(Tim0_IRQn, 14);
<> 149:156823d33999 273 NVIC_SetPriority(Tim1_IRQn, 14);
<> 149:156823d33999 274 NVIC_SetPriority(Tim2_IRQn, 14);
<> 149:156823d33999 275 NVIC_SetPriority(Uart1_IRQn,14);
<> 149:156823d33999 276 NVIC_SetPriority(Spi_IRQn, 14);
<> 149:156823d33999 277 NVIC_SetPriority(I2C_IRQn, 14);
<> 149:156823d33999 278 NVIC_SetPriority(Gpio_IRQn, 14);
<> 149:156823d33999 279 NVIC_SetPriority(Rtc_IRQn, 14);
<> 149:156823d33999 280 NVIC_SetPriority(MacHw_IRQn, 13);
<> 149:156823d33999 281 NVIC_SetPriority(Aes_IRQn, 13);
<> 149:156823d33999 282 NVIC_SetPriority(Adc_IRQn, 14);
<> 149:156823d33999 283 NVIC_SetPriority(ClockCal_IRQn, 14);
<> 149:156823d33999 284 NVIC_SetPriority(Uart2_IRQn, 14);
<> 149:156823d33999 285 NVIC_SetPriority(Dma_IRQn, 14);
<> 149:156823d33999 286 NVIC_SetPriority(Uvi_IRQn, 14);
<> 149:156823d33999 287 NVIC_SetPriority(DbgPwrUp_IRQn, 14);
<> 149:156823d33999 288 NVIC_SetPriority(Spi2_IRQn, 14);
<> 149:156823d33999 289 NVIC_SetPriority(I2C2_IRQn, 14);
<> 149:156823d33999 290 }
<> 149:156823d33999 291
<> 149:156823d33999 292 extern void __Vectors;
<> 149:156823d33999 293
<> 149:156823d33999 294 void fNcs36510Init(void)
<> 149:156823d33999 295 {
<> 149:156823d33999 296 /** Setting this register is helping to debug imprecise bus access faults
<> 149:156823d33999 297 * making them precise bus access faults. It has an impact on application
<> 149:156823d33999 298 * performance. */
<> 149:156823d33999 299 // SCnSCB->ACTLR |= SCnSCB_ACTLR_DISDEFWBUF_Msk;
<> 149:156823d33999 300
<> 149:156823d33999 301 /** This main function implements: */
<> 149:156823d33999 302 /**- Disable all interrupts */
<> 149:156823d33999 303 NVIC->ICER[0] = 0x1F;
<> 149:156823d33999 304
<> 149:156823d33999 305 /**- Clear all Pending interrupts */
<> 149:156823d33999 306 NVIC->ICPR[0] = 0x1F;
<> 149:156823d33999 307
<> 149:156823d33999 308 /**- Clear all pending SV and systick */
<> 149:156823d33999 309 SCB->ICSR = (uint32_t)0x0A000000;
<> 149:156823d33999 310 SCB->VTOR = (uint32_t) (&__Vectors);
<> 149:156823d33999 311
<> 149:156823d33999 312 /**- Initialize hardware */
<> 149:156823d33999 313 fHwInit();
<> 149:156823d33999 314 }