raspiezo / mbed-dev

hal_tick.h changed for the L432KC target in TARGET/../device/ in order to reassign the system ticker from TIM2 to TIM7, since TIM2 was needed as a 32bit encoder counter.

Dependents:   Nucleo_L432KC_Quadrature_Decoder_with_ADC_and_DAC

Fork of mbed-dev by mbed official

drivers/SPI.cpp@161:bd0311f1ad86, 2017-05-27 (annotated)

Committer:
tonnyleonard
Date:
Sat May 27 01:26:18 2017 +0000
Revision:
161:bd0311f1ad86
Parent:
149:156823d33999 
Testing ADC with shunt

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /* mbed Microcontroller Library
<> 149:156823d33999 2 * Copyright (c) 2006-2013 ARM Limited
<> 149:156823d33999 3 *
<> 149:156823d33999 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 149:156823d33999 5 * you may not use this file except in compliance with the License.
<> 149:156823d33999 6 * You may obtain a copy of the License at
<> 149:156823d33999 7 *
<> 149:156823d33999 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 149:156823d33999 9 *
<> 149:156823d33999 10 * Unless required by applicable law or agreed to in writing, software
<> 149:156823d33999 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 149:156823d33999 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 149:156823d33999 13 * See the License for the specific language governing permissions and
<> 149:156823d33999 14 * limitations under the License.
<> 149:156823d33999 15 */
<> 149:156823d33999 16 #include "drivers/SPI.h"
<> 149:156823d33999 17 #include "platform/critical.h"
<> 149:156823d33999 18
<> 149:156823d33999 19 #if DEVICE_SPI
<> 149:156823d33999 20
<> 149:156823d33999 21 namespace mbed {
<> 149:156823d33999 22
<> 149:156823d33999 23 #if DEVICE_SPI_ASYNCH && TRANSACTION_QUEUE_SIZE_SPI
<> 149:156823d33999 24 CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> SPI::_transaction_buffer;
<> 149:156823d33999 25 #endif
<> 149:156823d33999 26
<> 149:156823d33999 27 SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
<> 149:156823d33999 28 _spi(),
<> 149:156823d33999 29 #if DEVICE_SPI_ASYNCH
<> 149:156823d33999 30 _irq(this),
<> 149:156823d33999 31 _usage(DMA_USAGE_NEVER),
<> 149:156823d33999 32 #endif
<> 149:156823d33999 33 _bits(8),
<> 149:156823d33999 34 _mode(0),
<> 149:156823d33999 35 _hz(1000000) {
<> 149:156823d33999 36 // No lock needed in the constructor
<> 149:156823d33999 37
<> 149:156823d33999 38 spi_init(&_spi, mosi, miso, sclk, ssel);
<> 149:156823d33999 39 aquire();
<> 149:156823d33999 40 }
<> 149:156823d33999 41
<> 149:156823d33999 42 void SPI::format(int bits, int mode) {
<> 149:156823d33999 43 lock();
<> 149:156823d33999 44 _bits = bits;
<> 149:156823d33999 45 _mode = mode;
<> 149:156823d33999 46 SPI::_owner = NULL; // Not that elegant, but works. rmeyer
<> 149:156823d33999 47 aquire();
<> 149:156823d33999 48 unlock();
<> 149:156823d33999 49 }
<> 149:156823d33999 50
<> 149:156823d33999 51 void SPI::frequency(int hz) {
<> 149:156823d33999 52 lock();
<> 149:156823d33999 53 _hz = hz;
<> 149:156823d33999 54 SPI::_owner = NULL; // Not that elegant, but works. rmeyer
<> 149:156823d33999 55 aquire();
<> 149:156823d33999 56 unlock();
<> 149:156823d33999 57 }
<> 149:156823d33999 58
<> 149:156823d33999 59 SPI* SPI::_owner = NULL;
<> 149:156823d33999 60 SingletonPtr<PlatformMutex> SPI::_mutex;
<> 149:156823d33999 61
<> 149:156823d33999 62 // ignore the fact there are multiple physical spis, and always update if it wasnt us last
<> 149:156823d33999 63 void SPI::aquire() {
<> 149:156823d33999 64 lock();
<> 149:156823d33999 65 if (_owner != this) {
<> 149:156823d33999 66 spi_format(&_spi, _bits, _mode, 0);
<> 149:156823d33999 67 spi_frequency(&_spi, _hz);
<> 149:156823d33999 68 _owner = this;
<> 149:156823d33999 69 }
<> 149:156823d33999 70 unlock();
<> 149:156823d33999 71 }
<> 149:156823d33999 72
<> 149:156823d33999 73 int SPI::write(int value) {
<> 149:156823d33999 74 lock();
<> 149:156823d33999 75 aquire();
<> 149:156823d33999 76 int ret = spi_master_write(&_spi, value);
<> 149:156823d33999 77 unlock();
<> 149:156823d33999 78 return ret;
<> 149:156823d33999 79 }
<> 149:156823d33999 80
<> 149:156823d33999 81 void SPI::lock() {
<> 149:156823d33999 82 _mutex->lock();
<> 149:156823d33999 83 }
<> 149:156823d33999 84
<> 149:156823d33999 85 void SPI::unlock() {
<> 149:156823d33999 86 _mutex->unlock();
<> 149:156823d33999 87 }
<> 149:156823d33999 88
<> 149:156823d33999 89 #if DEVICE_SPI_ASYNCH
<> 149:156823d33999 90
<> 149:156823d33999 91 int SPI::transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
<> 149:156823d33999 92 {
<> 149:156823d33999 93 if (spi_active(&_spi)) {
<> 149:156823d33999 94 return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
<> 149:156823d33999 95 }
<> 149:156823d33999 96 start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
<> 149:156823d33999 97 return 0;
<> 149:156823d33999 98 }
<> 149:156823d33999 99
<> 149:156823d33999 100 void SPI::abort_transfer()
<> 149:156823d33999 101 {
<> 149:156823d33999 102 spi_abort_asynch(&_spi);
<> 149:156823d33999 103 #if TRANSACTION_QUEUE_SIZE_SPI
<> 149:156823d33999 104 dequeue_transaction();
<> 149:156823d33999 105 #endif
<> 149:156823d33999 106 }
<> 149:156823d33999 107
<> 149:156823d33999 108
<> 149:156823d33999 109 void SPI::clear_transfer_buffer()
<> 149:156823d33999 110 {
<> 149:156823d33999 111 #if TRANSACTION_QUEUE_SIZE_SPI
<> 149:156823d33999 112 _transaction_buffer.reset();
<> 149:156823d33999 113 #endif
<> 149:156823d33999 114 }
<> 149:156823d33999 115
<> 149:156823d33999 116 void SPI::abort_all_transfers()
<> 149:156823d33999 117 {
<> 149:156823d33999 118 clear_transfer_buffer();
<> 149:156823d33999 119 abort_transfer();
<> 149:156823d33999 120 }
<> 149:156823d33999 121
<> 149:156823d33999 122 int SPI::set_dma_usage(DMAUsage usage)
<> 149:156823d33999 123 {
<> 149:156823d33999 124 if (spi_active(&_spi)) {
<> 149:156823d33999 125 return -1;
<> 149:156823d33999 126 }
<> 149:156823d33999 127 _usage = usage;
<> 149:156823d33999 128 return 0;
<> 149:156823d33999 129 }
<> 149:156823d33999 130
<> 149:156823d33999 131 int SPI::queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
<> 149:156823d33999 132 {
<> 149:156823d33999 133 #if TRANSACTION_QUEUE_SIZE_SPI
<> 149:156823d33999 134 transaction_t t;
<> 149:156823d33999 135
<> 149:156823d33999 136 t.tx_buffer = const_cast<void *>(tx_buffer);
<> 149:156823d33999 137 t.tx_length = tx_length;
<> 149:156823d33999 138 t.rx_buffer = rx_buffer;
<> 149:156823d33999 139 t.rx_length = rx_length;
<> 149:156823d33999 140 t.event = event;
<> 149:156823d33999 141 t.callback = callback;
<> 149:156823d33999 142 t.width = bit_width;
<> 149:156823d33999 143 Transaction<SPI> transaction(this, t);
<> 149:156823d33999 144 if (_transaction_buffer.full()) {
<> 149:156823d33999 145 return -1; // the buffer is full
<> 149:156823d33999 146 } else {
<> 149:156823d33999 147 core_util_critical_section_enter();
<> 149:156823d33999 148 _transaction_buffer.push(transaction);
<> 149:156823d33999 149 if (!spi_active(&_spi)) {
<> 149:156823d33999 150 dequeue_transaction();
<> 149:156823d33999 151 }
<> 149:156823d33999 152 core_util_critical_section_exit();
<> 149:156823d33999 153 return 0;
<> 149:156823d33999 154 }
<> 149:156823d33999 155 #else
<> 149:156823d33999 156 return -1;
<> 149:156823d33999 157 #endif
<> 149:156823d33999 158 }
<> 149:156823d33999 159
<> 149:156823d33999 160 void SPI::start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
<> 149:156823d33999 161 {
<> 149:156823d33999 162 aquire();
<> 149:156823d33999 163 _callback = callback;
<> 149:156823d33999 164 _irq.callback(&SPI::irq_handler_asynch);
<> 149:156823d33999 165 spi_master_transfer(&_spi, tx_buffer, tx_length, rx_buffer, rx_length, bit_width, _irq.entry(), event , _usage);
<> 149:156823d33999 166 }
<> 149:156823d33999 167
<> 149:156823d33999 168 #if TRANSACTION_QUEUE_SIZE_SPI
<> 149:156823d33999 169
<> 149:156823d33999 170 void SPI::start_transaction(transaction_t *data)
<> 149:156823d33999 171 {
<> 149:156823d33999 172 start_transfer(data->tx_buffer, data->tx_length, data->rx_buffer, data->rx_length, data->width, data->callback, data->event);
<> 149:156823d33999 173 }
<> 149:156823d33999 174
<> 149:156823d33999 175 void SPI::dequeue_transaction()
<> 149:156823d33999 176 {
<> 149:156823d33999 177 Transaction<SPI> t;
<> 149:156823d33999 178 if (_transaction_buffer.pop(t)) {
<> 149:156823d33999 179 SPI* obj = t.get_object();
<> 149:156823d33999 180 transaction_t* data = t.get_transaction();
<> 149:156823d33999 181 obj->start_transaction(data);
<> 149:156823d33999 182 }
<> 149:156823d33999 183 }
<> 149:156823d33999 184
<> 149:156823d33999 185 #endif
<> 149:156823d33999 186
<> 149:156823d33999 187 void SPI::irq_handler_asynch(void)
<> 149:156823d33999 188 {
<> 149:156823d33999 189 int event = spi_irq_handler_asynch(&_spi);
<> 149:156823d33999 190 if (_callback && (event & SPI_EVENT_ALL)) {
<> 149:156823d33999 191 _callback.call(event & SPI_EVENT_ALL);
<> 149:156823d33999 192 }
<> 149:156823d33999 193 #if TRANSACTION_QUEUE_SIZE_SPI
<> 149:156823d33999 194 if (event & (SPI_EVENT_ALL | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE)) {
<> 149:156823d33999 195 // SPI peripheral is free (event happend), dequeue transaction
<> 149:156823d33999 196 dequeue_transaction();
<> 149:156823d33999 197 }
<> 149:156823d33999 198 #endif
<> 149:156823d33999 199 }
<> 149:156823d33999 200
<> 149:156823d33999 201 #endif
<> 149:156823d33999 202
<> 149:156823d33999 203 } // namespace mbed
<> 149:156823d33999 204
<> 149:156823d33999 205 #endif