raspiezo / mbed-dev

hal_tick.h changed for the L432KC target in TARGET/../device/ in order to reassign the system ticker from TIM2 to TIM7, since TIM2 was needed as a 32bit encoder counter.

Dependents:   Nucleo_L432KC_Quadrature_Decoder_with_ADC_and_DAC

Fork of mbed-dev by mbed official

targets/cmsis/core_cm0plus.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
19:112740acecfa
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 2 * @file core_cm0plus.h
bogdanm 0:9b334a45a8ff 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
bogdanm 0:9b334a45a8ff 4 * @version V3.20
bogdanm 0:9b334a45a8ff 5 * @date 25. February 2013
bogdanm 0:9b334a45a8ff 6 *
bogdanm 0:9b334a45a8ff 7 * @note
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 ******************************************************************************/
bogdanm 0:9b334a45a8ff 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
bogdanm 0:9b334a45a8ff 11
bogdanm 0:9b334a45a8ff 12 All rights reserved.
bogdanm 0:9b334a45a8ff 13 Redistribution and use in source and binary forms, with or without
bogdanm 0:9b334a45a8ff 14 modification, are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 15 - Redistributions of source code must retain the above copyright
bogdanm 0:9b334a45a8ff 16 notice, this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 0:9b334a45a8ff 18 notice, this list of conditions and the following disclaimer in the
bogdanm 0:9b334a45a8ff 19 documentation and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 0:9b334a45a8ff 21 to endorse or promote products derived from this software without
bogdanm 0:9b334a45a8ff 22 specific prior written permission.
bogdanm 0:9b334a45a8ff 23 *
bogdanm 0:9b334a45a8ff 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 0:9b334a45a8ff 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 0:9b334a45a8ff 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 0:9b334a45a8ff 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 0:9b334a45a8ff 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 0:9b334a45a8ff 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 0:9b334a45a8ff 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 0:9b334a45a8ff 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 0:9b334a45a8ff 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 35 ---------------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 #if defined ( __ICCARM__ )
bogdanm 0:9b334a45a8ff 39 #pragma system_include /* treat file as system include file for MISRA check */
bogdanm 0:9b334a45a8ff 40 #endif
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 43 extern "C" {
bogdanm 0:9b334a45a8ff 44 #endif
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 #ifndef __CORE_CM0PLUS_H_GENERIC
bogdanm 0:9b334a45a8ff 47 #define __CORE_CM0PLUS_H_GENERIC
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
bogdanm 0:9b334a45a8ff 50 CMSIS violates the following MISRA-C:2004 rules:
bogdanm 0:9b334a45a8ff 51
bogdanm 0:9b334a45a8ff 52 \li Required Rule 8.5, object/function definition in header file.<br>
bogdanm 0:9b334a45a8ff 53 Function definitions in header files are used to allow 'inlining'.
bogdanm 0:9b334a45a8ff 54
bogdanm 0:9b334a45a8ff 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
bogdanm 0:9b334a45a8ff 56 Unions are used for effective representation of core registers.
bogdanm 0:9b334a45a8ff 57
bogdanm 0:9b334a45a8ff 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
bogdanm 0:9b334a45a8ff 59 Function-like macros are used to allow more efficient code.
bogdanm 0:9b334a45a8ff 60 */
bogdanm 0:9b334a45a8ff 61
bogdanm 0:9b334a45a8ff 62
bogdanm 0:9b334a45a8ff 63 /*******************************************************************************
bogdanm 0:9b334a45a8ff 64 * CMSIS definitions
bogdanm 0:9b334a45a8ff 65 ******************************************************************************/
bogdanm 0:9b334a45a8ff 66 /** \ingroup Cortex-M0+
bogdanm 0:9b334a45a8ff 67 @{
bogdanm 0:9b334a45a8ff 68 */
bogdanm 0:9b334a45a8ff 69
bogdanm 0:9b334a45a8ff 70 /* CMSIS CM0P definitions */
bogdanm 0:9b334a45a8ff 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
bogdanm 0:9b334a45a8ff 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
bogdanm 0:9b334a45a8ff 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
bogdanm 0:9b334a45a8ff 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
bogdanm 0:9b334a45a8ff 75
bogdanm 0:9b334a45a8ff 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
bogdanm 0:9b334a45a8ff 77
bogdanm 0:9b334a45a8ff 78
bogdanm 0:9b334a45a8ff 79 #if defined ( __CC_ARM )
bogdanm 0:9b334a45a8ff 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
bogdanm 0:9b334a45a8ff 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
bogdanm 0:9b334a45a8ff 82 #define __STATIC_INLINE static __inline
bogdanm 0:9b334a45a8ff 83
bogdanm 0:9b334a45a8ff 84 #elif defined ( __ICCARM__ )
bogdanm 0:9b334a45a8ff 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
bogdanm 0:9b334a45a8ff 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
bogdanm 0:9b334a45a8ff 87 #define __STATIC_INLINE static inline
bogdanm 0:9b334a45a8ff 88
bogdanm 0:9b334a45a8ff 89 #elif defined ( __GNUC__ )
bogdanm 0:9b334a45a8ff 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
bogdanm 0:9b334a45a8ff 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
bogdanm 0:9b334a45a8ff 92 #define __STATIC_INLINE static inline
bogdanm 0:9b334a45a8ff 93
bogdanm 0:9b334a45a8ff 94 #elif defined ( __TASKING__ )
bogdanm 0:9b334a45a8ff 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
bogdanm 0:9b334a45a8ff 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
bogdanm 0:9b334a45a8ff 97 #define __STATIC_INLINE static inline
bogdanm 0:9b334a45a8ff 98
bogdanm 0:9b334a45a8ff 99 #endif
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
bogdanm 0:9b334a45a8ff 102 */
bogdanm 0:9b334a45a8ff 103 #define __FPU_USED 0
bogdanm 0:9b334a45a8ff 104
bogdanm 0:9b334a45a8ff 105 #if defined ( __CC_ARM )
bogdanm 0:9b334a45a8ff 106 #if defined __TARGET_FPU_VFP
bogdanm 0:9b334a45a8ff 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 0:9b334a45a8ff 108 #endif
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110 #elif defined ( __ICCARM__ )
bogdanm 0:9b334a45a8ff 111 #if defined __ARMVFP__
bogdanm 0:9b334a45a8ff 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 0:9b334a45a8ff 113 #endif
bogdanm 0:9b334a45a8ff 114
bogdanm 0:9b334a45a8ff 115 #elif defined ( __GNUC__ )
bogdanm 0:9b334a45a8ff 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
bogdanm 0:9b334a45a8ff 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 0:9b334a45a8ff 118 #endif
bogdanm 0:9b334a45a8ff 119
bogdanm 0:9b334a45a8ff 120 #elif defined ( __TASKING__ )
bogdanm 0:9b334a45a8ff 121 #if defined __FPU_VFP__
bogdanm 0:9b334a45a8ff 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 0:9b334a45a8ff 123 #endif
bogdanm 0:9b334a45a8ff 124 #endif
bogdanm 0:9b334a45a8ff 125
bogdanm 0:9b334a45a8ff 126 #include <stdint.h> /* standard types definitions */
bogdanm 0:9b334a45a8ff 127 #include <core_cmInstr.h> /* Core Instruction Access */
bogdanm 0:9b334a45a8ff 128 #include <core_cmFunc.h> /* Core Function Access */
bogdanm 0:9b334a45a8ff 129
bogdanm 0:9b334a45a8ff 130 #endif /* __CORE_CM0PLUS_H_GENERIC */
bogdanm 0:9b334a45a8ff 131
bogdanm 0:9b334a45a8ff 132 #ifndef __CMSIS_GENERIC
bogdanm 0:9b334a45a8ff 133
bogdanm 0:9b334a45a8ff 134 #ifndef __CORE_CM0PLUS_H_DEPENDANT
bogdanm 0:9b334a45a8ff 135 #define __CORE_CM0PLUS_H_DEPENDANT
bogdanm 0:9b334a45a8ff 136
bogdanm 0:9b334a45a8ff 137 /* check device defines and use defaults */
bogdanm 0:9b334a45a8ff 138 #if defined __CHECK_DEVICE_DEFINES
bogdanm 0:9b334a45a8ff 139 #ifndef __CM0PLUS_REV
bogdanm 0:9b334a45a8ff 140 #define __CM0PLUS_REV 0x0000
bogdanm 0:9b334a45a8ff 141 #warning "__CM0PLUS_REV not defined in device header file; using default!"
bogdanm 0:9b334a45a8ff 142 #endif
bogdanm 0:9b334a45a8ff 143
bogdanm 0:9b334a45a8ff 144 #ifndef __MPU_PRESENT
bogdanm 0:9b334a45a8ff 145 #define __MPU_PRESENT 0
bogdanm 0:9b334a45a8ff 146 #warning "__MPU_PRESENT not defined in device header file; using default!"
bogdanm 0:9b334a45a8ff 147 #endif
bogdanm 0:9b334a45a8ff 148
bogdanm 0:9b334a45a8ff 149 #ifndef __VTOR_PRESENT
bogdanm 0:9b334a45a8ff 150 #define __VTOR_PRESENT 0
bogdanm 0:9b334a45a8ff 151 #warning "__VTOR_PRESENT not defined in device header file; using default!"
bogdanm 0:9b334a45a8ff 152 #endif
bogdanm 0:9b334a45a8ff 153
bogdanm 0:9b334a45a8ff 154 #ifndef __NVIC_PRIO_BITS
bogdanm 0:9b334a45a8ff 155 #define __NVIC_PRIO_BITS 2
bogdanm 0:9b334a45a8ff 156 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
bogdanm 0:9b334a45a8ff 157 #endif
bogdanm 0:9b334a45a8ff 158
bogdanm 0:9b334a45a8ff 159 #ifndef __Vendor_SysTickConfig
bogdanm 0:9b334a45a8ff 160 #define __Vendor_SysTickConfig 0
bogdanm 0:9b334a45a8ff 161 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
bogdanm 0:9b334a45a8ff 162 #endif
bogdanm 0:9b334a45a8ff 163 #endif
bogdanm 0:9b334a45a8ff 164
bogdanm 0:9b334a45a8ff 165 /* IO definitions (access restrictions to peripheral registers) */
bogdanm 0:9b334a45a8ff 166 /**
bogdanm 0:9b334a45a8ff 167 \defgroup CMSIS_glob_defs CMSIS Global Defines
bogdanm 0:9b334a45a8ff 168
bogdanm 0:9b334a45a8ff 169 <strong>IO Type Qualifiers</strong> are used
bogdanm 0:9b334a45a8ff 170 \li to specify the access to peripheral variables.
bogdanm 0:9b334a45a8ff 171 \li for automatic generation of peripheral register debug information.
bogdanm 0:9b334a45a8ff 172 */
bogdanm 0:9b334a45a8ff 173 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 174 #define __I volatile /*!< Defines 'read only' permissions */
bogdanm 0:9b334a45a8ff 175 #else
bogdanm 0:9b334a45a8ff 176 #define __I volatile const /*!< Defines 'read only' permissions */
bogdanm 0:9b334a45a8ff 177 #endif
bogdanm 0:9b334a45a8ff 178 #define __O volatile /*!< Defines 'write only' permissions */
bogdanm 0:9b334a45a8ff 179 #define __IO volatile /*!< Defines 'read / write' permissions */
bogdanm 0:9b334a45a8ff 180
bogdanm 0:9b334a45a8ff 181 /*@} end of group Cortex-M0+ */
bogdanm 0:9b334a45a8ff 182
bogdanm 0:9b334a45a8ff 183
bogdanm 0:9b334a45a8ff 184
bogdanm 0:9b334a45a8ff 185 /*******************************************************************************
bogdanm 0:9b334a45a8ff 186 * Register Abstraction
bogdanm 0:9b334a45a8ff 187 Core Register contain:
bogdanm 0:9b334a45a8ff 188 - Core Register
bogdanm 0:9b334a45a8ff 189 - Core NVIC Register
bogdanm 0:9b334a45a8ff 190 - Core SCB Register
bogdanm 0:9b334a45a8ff 191 - Core SysTick Register
bogdanm 0:9b334a45a8ff 192 - Core MPU Register
bogdanm 0:9b334a45a8ff 193 ******************************************************************************/
bogdanm 0:9b334a45a8ff 194 /** \defgroup CMSIS_core_register Defines and Type Definitions
bogdanm 0:9b334a45a8ff 195 \brief Type definitions and defines for Cortex-M processor based devices.
bogdanm 0:9b334a45a8ff 196 */
bogdanm 0:9b334a45a8ff 197
bogdanm 0:9b334a45a8ff 198 /** \ingroup CMSIS_core_register
bogdanm 0:9b334a45a8ff 199 \defgroup CMSIS_CORE Status and Control Registers
bogdanm 0:9b334a45a8ff 200 \brief Core Register type definitions.
bogdanm 0:9b334a45a8ff 201 @{
bogdanm 0:9b334a45a8ff 202 */
bogdanm 0:9b334a45a8ff 203
bogdanm 0:9b334a45a8ff 204 /** \brief Union type to access the Application Program Status Register (APSR).
bogdanm 0:9b334a45a8ff 205 */
bogdanm 0:9b334a45a8ff 206 typedef union
bogdanm 0:9b334a45a8ff 207 {
bogdanm 0:9b334a45a8ff 208 struct
bogdanm 0:9b334a45a8ff 209 {
bogdanm 0:9b334a45a8ff 210 #if (__CORTEX_M != 0x04)
bogdanm 0:9b334a45a8ff 211 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
bogdanm 0:9b334a45a8ff 212 #else
bogdanm 0:9b334a45a8ff 213 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
bogdanm 0:9b334a45a8ff 214 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
bogdanm 0:9b334a45a8ff 215 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
bogdanm 0:9b334a45a8ff 216 #endif
bogdanm 0:9b334a45a8ff 217 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
bogdanm 0:9b334a45a8ff 218 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 0:9b334a45a8ff 219 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 0:9b334a45a8ff 220 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 0:9b334a45a8ff 221 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 0:9b334a45a8ff 222 } b; /*!< Structure used for bit access */
bogdanm 0:9b334a45a8ff 223 uint32_t w; /*!< Type used for word access */
bogdanm 0:9b334a45a8ff 224 } APSR_Type;
bogdanm 0:9b334a45a8ff 225
bogdanm 0:9b334a45a8ff 226
bogdanm 0:9b334a45a8ff 227 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
bogdanm 0:9b334a45a8ff 228 */
bogdanm 0:9b334a45a8ff 229 typedef union
bogdanm 0:9b334a45a8ff 230 {
bogdanm 0:9b334a45a8ff 231 struct
bogdanm 0:9b334a45a8ff 232 {
bogdanm 0:9b334a45a8ff 233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 0:9b334a45a8ff 234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
bogdanm 0:9b334a45a8ff 235 } b; /*!< Structure used for bit access */
bogdanm 0:9b334a45a8ff 236 uint32_t w; /*!< Type used for word access */
bogdanm 0:9b334a45a8ff 237 } IPSR_Type;
bogdanm 0:9b334a45a8ff 238
bogdanm 0:9b334a45a8ff 239
bogdanm 0:9b334a45a8ff 240 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
bogdanm 0:9b334a45a8ff 241 */
bogdanm 0:9b334a45a8ff 242 typedef union
bogdanm 0:9b334a45a8ff 243 {
bogdanm 0:9b334a45a8ff 244 struct
bogdanm 0:9b334a45a8ff 245 {
bogdanm 0:9b334a45a8ff 246 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 0:9b334a45a8ff 247 #if (__CORTEX_M != 0x04)
bogdanm 0:9b334a45a8ff 248 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
bogdanm 0:9b334a45a8ff 249 #else
bogdanm 0:9b334a45a8ff 250 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
bogdanm 0:9b334a45a8ff 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
bogdanm 0:9b334a45a8ff 252 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
bogdanm 0:9b334a45a8ff 253 #endif
bogdanm 0:9b334a45a8ff 254 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
bogdanm 0:9b334a45a8ff 255 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
bogdanm 0:9b334a45a8ff 256 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
bogdanm 0:9b334a45a8ff 257 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 0:9b334a45a8ff 258 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 0:9b334a45a8ff 259 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 0:9b334a45a8ff 260 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 0:9b334a45a8ff 261 } b; /*!< Structure used for bit access */
bogdanm 0:9b334a45a8ff 262 uint32_t w; /*!< Type used for word access */
bogdanm 0:9b334a45a8ff 263 } xPSR_Type;
bogdanm 0:9b334a45a8ff 264
bogdanm 0:9b334a45a8ff 265
bogdanm 0:9b334a45a8ff 266 /** \brief Union type to access the Control Registers (CONTROL).
bogdanm 0:9b334a45a8ff 267 */
bogdanm 0:9b334a45a8ff 268 typedef union
bogdanm 0:9b334a45a8ff 269 {
bogdanm 0:9b334a45a8ff 270 struct
bogdanm 0:9b334a45a8ff 271 {
bogdanm 0:9b334a45a8ff 272 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
bogdanm 0:9b334a45a8ff 273 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
bogdanm 0:9b334a45a8ff 274 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
bogdanm 0:9b334a45a8ff 275 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
bogdanm 0:9b334a45a8ff 276 } b; /*!< Structure used for bit access */
bogdanm 0:9b334a45a8ff 277 uint32_t w; /*!< Type used for word access */
bogdanm 0:9b334a45a8ff 278 } CONTROL_Type;
bogdanm 0:9b334a45a8ff 279
bogdanm 0:9b334a45a8ff 280 /*@} end of group CMSIS_CORE */
bogdanm 0:9b334a45a8ff 281
bogdanm 0:9b334a45a8ff 282
bogdanm 0:9b334a45a8ff 283 /** \ingroup CMSIS_core_register
bogdanm 0:9b334a45a8ff 284 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
bogdanm 0:9b334a45a8ff 285 \brief Type definitions for the NVIC Registers
bogdanm 0:9b334a45a8ff 286 @{
bogdanm 0:9b334a45a8ff 287 */
bogdanm 0:9b334a45a8ff 288
bogdanm 0:9b334a45a8ff 289 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
bogdanm 0:9b334a45a8ff 290 */
bogdanm 0:9b334a45a8ff 291 typedef struct
bogdanm 0:9b334a45a8ff 292 {
bogdanm 0:9b334a45a8ff 293 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
bogdanm 0:9b334a45a8ff 294 uint32_t RESERVED0[31];
bogdanm 0:9b334a45a8ff 295 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
bogdanm 0:9b334a45a8ff 296 uint32_t RSERVED1[31];
bogdanm 0:9b334a45a8ff 297 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
bogdanm 0:9b334a45a8ff 298 uint32_t RESERVED2[31];
bogdanm 0:9b334a45a8ff 299 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
bogdanm 0:9b334a45a8ff 300 uint32_t RESERVED3[31];
bogdanm 0:9b334a45a8ff 301 uint32_t RESERVED4[64];
bogdanm 0:9b334a45a8ff 302 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
bogdanm 0:9b334a45a8ff 303 } NVIC_Type;
bogdanm 0:9b334a45a8ff 304
bogdanm 0:9b334a45a8ff 305 /*@} end of group CMSIS_NVIC */
bogdanm 0:9b334a45a8ff 306
bogdanm 0:9b334a45a8ff 307
bogdanm 0:9b334a45a8ff 308 /** \ingroup CMSIS_core_register
bogdanm 0:9b334a45a8ff 309 \defgroup CMSIS_SCB System Control Block (SCB)
bogdanm 0:9b334a45a8ff 310 \brief Type definitions for the System Control Block Registers
bogdanm 0:9b334a45a8ff 311 @{
bogdanm 0:9b334a45a8ff 312 */
bogdanm 0:9b334a45a8ff 313
bogdanm 0:9b334a45a8ff 314 /** \brief Structure type to access the System Control Block (SCB).
bogdanm 0:9b334a45a8ff 315 */
bogdanm 0:9b334a45a8ff 316 typedef struct
bogdanm 0:9b334a45a8ff 317 {
bogdanm 0:9b334a45a8ff 318 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
bogdanm 0:9b334a45a8ff 319 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
bogdanm 0:9b334a45a8ff 320 #if (__VTOR_PRESENT == 1)
bogdanm 0:9b334a45a8ff 321 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
bogdanm 0:9b334a45a8ff 322 #else
bogdanm 0:9b334a45a8ff 323 uint32_t RESERVED0;
bogdanm 0:9b334a45a8ff 324 #endif
bogdanm 0:9b334a45a8ff 325 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
bogdanm 0:9b334a45a8ff 326 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
bogdanm 0:9b334a45a8ff 327 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
bogdanm 0:9b334a45a8ff 328 uint32_t RESERVED1;
bogdanm 0:9b334a45a8ff 329 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
bogdanm 0:9b334a45a8ff 330 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
bogdanm 0:9b334a45a8ff 331 } SCB_Type;
bogdanm 0:9b334a45a8ff 332
bogdanm 0:9b334a45a8ff 333 /* SCB CPUID Register Definitions */
bogdanm 0:9b334a45a8ff 334 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
bogdanm 0:9b334a45a8ff 335 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
bogdanm 0:9b334a45a8ff 336
bogdanm 0:9b334a45a8ff 337 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
bogdanm 0:9b334a45a8ff 338 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
bogdanm 0:9b334a45a8ff 339
bogdanm 0:9b334a45a8ff 340 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
bogdanm 0:9b334a45a8ff 341 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
bogdanm 0:9b334a45a8ff 342
bogdanm 0:9b334a45a8ff 343 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
bogdanm 0:9b334a45a8ff 344 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
bogdanm 0:9b334a45a8ff 345
bogdanm 0:9b334a45a8ff 346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
bogdanm 0:9b334a45a8ff 347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
bogdanm 0:9b334a45a8ff 348
bogdanm 0:9b334a45a8ff 349 /* SCB Interrupt Control State Register Definitions */
bogdanm 0:9b334a45a8ff 350 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
bogdanm 0:9b334a45a8ff 351 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
bogdanm 0:9b334a45a8ff 352
bogdanm 0:9b334a45a8ff 353 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
bogdanm 0:9b334a45a8ff 354 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
bogdanm 0:9b334a45a8ff 355
bogdanm 0:9b334a45a8ff 356 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
bogdanm 0:9b334a45a8ff 357 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
bogdanm 0:9b334a45a8ff 358
bogdanm 0:9b334a45a8ff 359 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
bogdanm 0:9b334a45a8ff 360 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
bogdanm 0:9b334a45a8ff 361
bogdanm 0:9b334a45a8ff 362 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
bogdanm 0:9b334a45a8ff 363 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
bogdanm 0:9b334a45a8ff 364
bogdanm 0:9b334a45a8ff 365 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
bogdanm 0:9b334a45a8ff 366 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
bogdanm 0:9b334a45a8ff 367
bogdanm 0:9b334a45a8ff 368 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
bogdanm 0:9b334a45a8ff 369 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
bogdanm 0:9b334a45a8ff 370
bogdanm 0:9b334a45a8ff 371 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
bogdanm 0:9b334a45a8ff 372 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
bogdanm 0:9b334a45a8ff 373
bogdanm 0:9b334a45a8ff 374 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
bogdanm 0:9b334a45a8ff 375 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
bogdanm 0:9b334a45a8ff 376
bogdanm 0:9b334a45a8ff 377 #if (__VTOR_PRESENT == 1)
bogdanm 0:9b334a45a8ff 378 /* SCB Interrupt Control State Register Definitions */
bogdanm 0:9b334a45a8ff 379 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
bogdanm 0:9b334a45a8ff 380 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
bogdanm 0:9b334a45a8ff 381 #endif
bogdanm 0:9b334a45a8ff 382
bogdanm 0:9b334a45a8ff 383 /* SCB Application Interrupt and Reset Control Register Definitions */
bogdanm 0:9b334a45a8ff 384 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
bogdanm 0:9b334a45a8ff 385 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
bogdanm 0:9b334a45a8ff 386
bogdanm 0:9b334a45a8ff 387 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
bogdanm 0:9b334a45a8ff 388 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
bogdanm 0:9b334a45a8ff 389
bogdanm 0:9b334a45a8ff 390 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
bogdanm 0:9b334a45a8ff 391 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
bogdanm 0:9b334a45a8ff 392
bogdanm 0:9b334a45a8ff 393 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
bogdanm 0:9b334a45a8ff 394 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
bogdanm 0:9b334a45a8ff 395
bogdanm 0:9b334a45a8ff 396 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
bogdanm 0:9b334a45a8ff 397 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
bogdanm 0:9b334a45a8ff 398
bogdanm 0:9b334a45a8ff 399 /* SCB System Control Register Definitions */
bogdanm 0:9b334a45a8ff 400 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
bogdanm 0:9b334a45a8ff 401 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
bogdanm 0:9b334a45a8ff 402
bogdanm 0:9b334a45a8ff 403 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
bogdanm 0:9b334a45a8ff 404 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
bogdanm 0:9b334a45a8ff 405
bogdanm 0:9b334a45a8ff 406 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
bogdanm 0:9b334a45a8ff 407 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
bogdanm 0:9b334a45a8ff 408
bogdanm 0:9b334a45a8ff 409 /* SCB Configuration Control Register Definitions */
bogdanm 0:9b334a45a8ff 410 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
bogdanm 0:9b334a45a8ff 411 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
bogdanm 0:9b334a45a8ff 412
bogdanm 0:9b334a45a8ff 413 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
bogdanm 0:9b334a45a8ff 414 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
bogdanm 0:9b334a45a8ff 415
bogdanm 0:9b334a45a8ff 416 /* SCB System Handler Control and State Register Definitions */
bogdanm 0:9b334a45a8ff 417 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
bogdanm 0:9b334a45a8ff 418 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
bogdanm 0:9b334a45a8ff 419
bogdanm 0:9b334a45a8ff 420 /*@} end of group CMSIS_SCB */
bogdanm 0:9b334a45a8ff 421
bogdanm 0:9b334a45a8ff 422
bogdanm 0:9b334a45a8ff 423 /** \ingroup CMSIS_core_register
bogdanm 0:9b334a45a8ff 424 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
bogdanm 0:9b334a45a8ff 425 \brief Type definitions for the System Timer Registers.
bogdanm 0:9b334a45a8ff 426 @{
bogdanm 0:9b334a45a8ff 427 */
bogdanm 0:9b334a45a8ff 428
bogdanm 0:9b334a45a8ff 429 /** \brief Structure type to access the System Timer (SysTick).
bogdanm 0:9b334a45a8ff 430 */
bogdanm 0:9b334a45a8ff 431 typedef struct
bogdanm 0:9b334a45a8ff 432 {
bogdanm 0:9b334a45a8ff 433 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
bogdanm 0:9b334a45a8ff 434 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
bogdanm 0:9b334a45a8ff 435 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
bogdanm 0:9b334a45a8ff 436 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
bogdanm 0:9b334a45a8ff 437 } SysTick_Type;
bogdanm 0:9b334a45a8ff 438
bogdanm 0:9b334a45a8ff 439 /* SysTick Control / Status Register Definitions */
bogdanm 0:9b334a45a8ff 440 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
bogdanm 0:9b334a45a8ff 441 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
bogdanm 0:9b334a45a8ff 442
bogdanm 0:9b334a45a8ff 443 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
bogdanm 0:9b334a45a8ff 444 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
bogdanm 0:9b334a45a8ff 445
bogdanm 0:9b334a45a8ff 446 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
bogdanm 0:9b334a45a8ff 447 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
bogdanm 0:9b334a45a8ff 448
bogdanm 0:9b334a45a8ff 449 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
bogdanm 0:9b334a45a8ff 450 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
bogdanm 0:9b334a45a8ff 451
bogdanm 0:9b334a45a8ff 452 /* SysTick Reload Register Definitions */
bogdanm 0:9b334a45a8ff 453 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
bogdanm 0:9b334a45a8ff 454 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
bogdanm 0:9b334a45a8ff 455
bogdanm 0:9b334a45a8ff 456 /* SysTick Current Register Definitions */
bogdanm 0:9b334a45a8ff 457 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
bogdanm 0:9b334a45a8ff 458 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
bogdanm 0:9b334a45a8ff 459
bogdanm 0:9b334a45a8ff 460 /* SysTick Calibration Register Definitions */
bogdanm 0:9b334a45a8ff 461 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
bogdanm 0:9b334a45a8ff 462 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
bogdanm 0:9b334a45a8ff 463
bogdanm 0:9b334a45a8ff 464 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
bogdanm 0:9b334a45a8ff 465 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
bogdanm 0:9b334a45a8ff 466
bogdanm 0:9b334a45a8ff 467 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
bogdanm 0:9b334a45a8ff 468 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
bogdanm 0:9b334a45a8ff 469
bogdanm 0:9b334a45a8ff 470 /*@} end of group CMSIS_SysTick */
bogdanm 0:9b334a45a8ff 471
bogdanm 0:9b334a45a8ff 472 #if (__MPU_PRESENT == 1)
bogdanm 0:9b334a45a8ff 473 /** \ingroup CMSIS_core_register
bogdanm 0:9b334a45a8ff 474 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
bogdanm 0:9b334a45a8ff 475 \brief Type definitions for the Memory Protection Unit (MPU)
bogdanm 0:9b334a45a8ff 476 @{
bogdanm 0:9b334a45a8ff 477 */
bogdanm 0:9b334a45a8ff 478
bogdanm 0:9b334a45a8ff 479 /** \brief Structure type to access the Memory Protection Unit (MPU).
bogdanm 0:9b334a45a8ff 480 */
bogdanm 0:9b334a45a8ff 481 typedef struct
bogdanm 0:9b334a45a8ff 482 {
bogdanm 0:9b334a45a8ff 483 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
bogdanm 0:9b334a45a8ff 484 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
bogdanm 0:9b334a45a8ff 485 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
bogdanm 0:9b334a45a8ff 486 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
bogdanm 0:9b334a45a8ff 487 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
bogdanm 0:9b334a45a8ff 488 } MPU_Type;
bogdanm 0:9b334a45a8ff 489
bogdanm 0:9b334a45a8ff 490 /* MPU Type Register */
bogdanm 0:9b334a45a8ff 491 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
bogdanm 0:9b334a45a8ff 492 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
bogdanm 0:9b334a45a8ff 493
bogdanm 0:9b334a45a8ff 494 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
bogdanm 0:9b334a45a8ff 495 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
bogdanm 0:9b334a45a8ff 496
bogdanm 0:9b334a45a8ff 497 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
bogdanm 0:9b334a45a8ff 498 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
bogdanm 0:9b334a45a8ff 499
bogdanm 0:9b334a45a8ff 500 /* MPU Control Register */
bogdanm 0:9b334a45a8ff 501 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
bogdanm 0:9b334a45a8ff 502 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
bogdanm 0:9b334a45a8ff 503
bogdanm 0:9b334a45a8ff 504 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
bogdanm 0:9b334a45a8ff 505 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
bogdanm 0:9b334a45a8ff 506
bogdanm 0:9b334a45a8ff 507 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
bogdanm 0:9b334a45a8ff 508 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
bogdanm 0:9b334a45a8ff 509
bogdanm 0:9b334a45a8ff 510 /* MPU Region Number Register */
bogdanm 0:9b334a45a8ff 511 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
bogdanm 0:9b334a45a8ff 512 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
bogdanm 0:9b334a45a8ff 513
bogdanm 0:9b334a45a8ff 514 /* MPU Region Base Address Register */
bogdanm 0:9b334a45a8ff 515 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
bogdanm 0:9b334a45a8ff 516 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
bogdanm 0:9b334a45a8ff 517
bogdanm 0:9b334a45a8ff 518 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
bogdanm 0:9b334a45a8ff 519 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
bogdanm 0:9b334a45a8ff 520
bogdanm 0:9b334a45a8ff 521 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
bogdanm 0:9b334a45a8ff 522 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
bogdanm 0:9b334a45a8ff 523
bogdanm 0:9b334a45a8ff 524 /* MPU Region Attribute and Size Register */
bogdanm 0:9b334a45a8ff 525 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
bogdanm 0:9b334a45a8ff 526 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
bogdanm 0:9b334a45a8ff 527
bogdanm 0:9b334a45a8ff 528 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
bogdanm 0:9b334a45a8ff 529 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
bogdanm 0:9b334a45a8ff 530
bogdanm 0:9b334a45a8ff 531 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
bogdanm 0:9b334a45a8ff 532 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
bogdanm 0:9b334a45a8ff 533
bogdanm 0:9b334a45a8ff 534 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
bogdanm 0:9b334a45a8ff 535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
bogdanm 0:9b334a45a8ff 536
bogdanm 0:9b334a45a8ff 537 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
bogdanm 0:9b334a45a8ff 538 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
bogdanm 0:9b334a45a8ff 539
bogdanm 0:9b334a45a8ff 540 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
bogdanm 0:9b334a45a8ff 541 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
bogdanm 0:9b334a45a8ff 542
bogdanm 0:9b334a45a8ff 543 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
bogdanm 0:9b334a45a8ff 544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
bogdanm 0:9b334a45a8ff 545
bogdanm 0:9b334a45a8ff 546 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
bogdanm 0:9b334a45a8ff 547 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
bogdanm 0:9b334a45a8ff 548
bogdanm 0:9b334a45a8ff 549 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
bogdanm 0:9b334a45a8ff 550 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
bogdanm 0:9b334a45a8ff 551
bogdanm 0:9b334a45a8ff 552 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
bogdanm 0:9b334a45a8ff 553 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
bogdanm 0:9b334a45a8ff 554
bogdanm 0:9b334a45a8ff 555 /*@} end of group CMSIS_MPU */
bogdanm 0:9b334a45a8ff 556 #endif
bogdanm 0:9b334a45a8ff 557
bogdanm 0:9b334a45a8ff 558
bogdanm 0:9b334a45a8ff 559 /** \ingroup CMSIS_core_register
bogdanm 0:9b334a45a8ff 560 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
bogdanm 0:9b334a45a8ff 561 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
bogdanm 0:9b334a45a8ff 562 are only accessible over DAP and not via processor. Therefore
bogdanm 0:9b334a45a8ff 563 they are not covered by the Cortex-M0 header file.
bogdanm 0:9b334a45a8ff 564 @{
bogdanm 0:9b334a45a8ff 565 */
bogdanm 0:9b334a45a8ff 566 /*@} end of group CMSIS_CoreDebug */
bogdanm 0:9b334a45a8ff 567
bogdanm 0:9b334a45a8ff 568
bogdanm 0:9b334a45a8ff 569 /** \ingroup CMSIS_core_register
bogdanm 0:9b334a45a8ff 570 \defgroup CMSIS_core_base Core Definitions
bogdanm 0:9b334a45a8ff 571 \brief Definitions for base addresses, unions, and structures.
bogdanm 0:9b334a45a8ff 572 @{
bogdanm 0:9b334a45a8ff 573 */
bogdanm 0:9b334a45a8ff 574
bogdanm 0:9b334a45a8ff 575 /* Memory mapping of Cortex-M0+ Hardware */
bogdanm 0:9b334a45a8ff 576 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
bogdanm 0:9b334a45a8ff 577 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
bogdanm 0:9b334a45a8ff 578 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
bogdanm 0:9b334a45a8ff 579 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
bogdanm 0:9b334a45a8ff 580
bogdanm 0:9b334a45a8ff 581 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
bogdanm 0:9b334a45a8ff 582 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
bogdanm 0:9b334a45a8ff 583 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
bogdanm 0:9b334a45a8ff 584
bogdanm 0:9b334a45a8ff 585 #if (__MPU_PRESENT == 1)
bogdanm 0:9b334a45a8ff 586 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
bogdanm 0:9b334a45a8ff 587 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
bogdanm 0:9b334a45a8ff 588 #endif
bogdanm 0:9b334a45a8ff 589
bogdanm 0:9b334a45a8ff 590 /*@} */
bogdanm 0:9b334a45a8ff 591
bogdanm 0:9b334a45a8ff 592
bogdanm 0:9b334a45a8ff 593
bogdanm 0:9b334a45a8ff 594 /*******************************************************************************
bogdanm 0:9b334a45a8ff 595 * Hardware Abstraction Layer
bogdanm 0:9b334a45a8ff 596 Core Function Interface contains:
bogdanm 0:9b334a45a8ff 597 - Core NVIC Functions
bogdanm 0:9b334a45a8ff 598 - Core SysTick Functions
bogdanm 0:9b334a45a8ff 599 - Core Register Access Functions
bogdanm 0:9b334a45a8ff 600 ******************************************************************************/
bogdanm 0:9b334a45a8ff 601 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
bogdanm 0:9b334a45a8ff 602 */
bogdanm 0:9b334a45a8ff 603
bogdanm 0:9b334a45a8ff 604
bogdanm 0:9b334a45a8ff 605
bogdanm 0:9b334a45a8ff 606 /* ########################## NVIC functions #################################### */
bogdanm 0:9b334a45a8ff 607 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 0:9b334a45a8ff 608 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
bogdanm 0:9b334a45a8ff 609 \brief Functions that manage interrupts and exceptions via the NVIC.
bogdanm 0:9b334a45a8ff 610 @{
bogdanm 0:9b334a45a8ff 611 */
bogdanm 0:9b334a45a8ff 612
bogdanm 0:9b334a45a8ff 613 /* Interrupt Priorities are WORD accessible only under ARMv6M */
bogdanm 0:9b334a45a8ff 614 /* The following MACROS handle generation of the register offset and byte masks */
bogdanm 0:9b334a45a8ff 615 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
bogdanm 0:9b334a45a8ff 616 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
bogdanm 0:9b334a45a8ff 617 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
bogdanm 0:9b334a45a8ff 618
bogdanm 0:9b334a45a8ff 619
bogdanm 0:9b334a45a8ff 620 /** \brief Enable External Interrupt
bogdanm 0:9b334a45a8ff 621
bogdanm 0:9b334a45a8ff 622 The function enables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 0:9b334a45a8ff 623
bogdanm 0:9b334a45a8ff 624 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 0:9b334a45a8ff 625 */
bogdanm 0:9b334a45a8ff 626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
bogdanm 0:9b334a45a8ff 627 {
bogdanm 0:9b334a45a8ff 628 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
bogdanm 0:9b334a45a8ff 629 }
bogdanm 0:9b334a45a8ff 630
bogdanm 0:9b334a45a8ff 631
bogdanm 0:9b334a45a8ff 632 /** \brief Disable External Interrupt
bogdanm 0:9b334a45a8ff 633
bogdanm 0:9b334a45a8ff 634 The function disables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 0:9b334a45a8ff 635
bogdanm 0:9b334a45a8ff 636 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 0:9b334a45a8ff 637 */
bogdanm 0:9b334a45a8ff 638 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
bogdanm 0:9b334a45a8ff 639 {
bogdanm 0:9b334a45a8ff 640 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
bogdanm 0:9b334a45a8ff 641 }
bogdanm 0:9b334a45a8ff 642
bogdanm 0:9b334a45a8ff 643
bogdanm 0:9b334a45a8ff 644 /** \brief Get Pending Interrupt
bogdanm 0:9b334a45a8ff 645
bogdanm 0:9b334a45a8ff 646 The function reads the pending register in the NVIC and returns the pending bit
bogdanm 0:9b334a45a8ff 647 for the specified interrupt.
bogdanm 0:9b334a45a8ff 648
bogdanm 0:9b334a45a8ff 649 \param [in] IRQn Interrupt number.
bogdanm 0:9b334a45a8ff 650
bogdanm 0:9b334a45a8ff 651 \return 0 Interrupt status is not pending.
bogdanm 0:9b334a45a8ff 652 \return 1 Interrupt status is pending.
bogdanm 0:9b334a45a8ff 653 */
bogdanm 0:9b334a45a8ff 654 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
bogdanm 0:9b334a45a8ff 655 {
bogdanm 0:9b334a45a8ff 656 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
bogdanm 0:9b334a45a8ff 657 }
bogdanm 0:9b334a45a8ff 658
bogdanm 0:9b334a45a8ff 659
bogdanm 0:9b334a45a8ff 660 /** \brief Set Pending Interrupt
bogdanm 0:9b334a45a8ff 661
bogdanm 0:9b334a45a8ff 662 The function sets the pending bit of an external interrupt.
bogdanm 0:9b334a45a8ff 663
bogdanm 0:9b334a45a8ff 664 \param [in] IRQn Interrupt number. Value cannot be negative.
bogdanm 0:9b334a45a8ff 665 */
bogdanm 0:9b334a45a8ff 666 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
bogdanm 0:9b334a45a8ff 667 {
bogdanm 0:9b334a45a8ff 668 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
bogdanm 0:9b334a45a8ff 669 }
bogdanm 0:9b334a45a8ff 670
bogdanm 0:9b334a45a8ff 671
bogdanm 0:9b334a45a8ff 672 /** \brief Clear Pending Interrupt
bogdanm 0:9b334a45a8ff 673
bogdanm 0:9b334a45a8ff 674 The function clears the pending bit of an external interrupt.
bogdanm 0:9b334a45a8ff 675
bogdanm 0:9b334a45a8ff 676 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 0:9b334a45a8ff 677 */
bogdanm 0:9b334a45a8ff 678 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
bogdanm 0:9b334a45a8ff 679 {
bogdanm 0:9b334a45a8ff 680 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
bogdanm 0:9b334a45a8ff 681 }
bogdanm 0:9b334a45a8ff 682
bogdanm 0:9b334a45a8ff 683
bogdanm 0:9b334a45a8ff 684 /** \brief Set Interrupt Priority
bogdanm 0:9b334a45a8ff 685
bogdanm 0:9b334a45a8ff 686 The function sets the priority of an interrupt.
bogdanm 0:9b334a45a8ff 687
bogdanm 0:9b334a45a8ff 688 \note The priority cannot be set for every core interrupt.
bogdanm 0:9b334a45a8ff 689
bogdanm 0:9b334a45a8ff 690 \param [in] IRQn Interrupt number.
bogdanm 0:9b334a45a8ff 691 \param [in] priority Priority to set.
bogdanm 0:9b334a45a8ff 692 */
bogdanm 0:9b334a45a8ff 693 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
bogdanm 0:9b334a45a8ff 694 {
bogdanm 0:9b334a45a8ff 695 if(IRQn < 0) {
bogdanm 0:9b334a45a8ff 696 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
bogdanm 0:9b334a45a8ff 697 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
bogdanm 0:9b334a45a8ff 698 else {
bogdanm 0:9b334a45a8ff 699 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
bogdanm 0:9b334a45a8ff 700 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
bogdanm 0:9b334a45a8ff 701 }
bogdanm 0:9b334a45a8ff 702
bogdanm 0:9b334a45a8ff 703
bogdanm 0:9b334a45a8ff 704 /** \brief Get Interrupt Priority
bogdanm 0:9b334a45a8ff 705
bogdanm 0:9b334a45a8ff 706 The function reads the priority of an interrupt. The interrupt
bogdanm 0:9b334a45a8ff 707 number can be positive to specify an external (device specific)
bogdanm 0:9b334a45a8ff 708 interrupt, or negative to specify an internal (core) interrupt.
bogdanm 0:9b334a45a8ff 709
bogdanm 0:9b334a45a8ff 710
bogdanm 0:9b334a45a8ff 711 \param [in] IRQn Interrupt number.
bogdanm 0:9b334a45a8ff 712 \return Interrupt Priority. Value is aligned automatically to the implemented
bogdanm 0:9b334a45a8ff 713 priority bits of the microcontroller.
bogdanm 0:9b334a45a8ff 714 */
bogdanm 0:9b334a45a8ff 715 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
bogdanm 0:9b334a45a8ff 716 {
bogdanm 0:9b334a45a8ff 717
bogdanm 0:9b334a45a8ff 718 if(IRQn < 0) {
bogdanm 0:9b334a45a8ff 719 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
bogdanm 0:9b334a45a8ff 720 else {
bogdanm 0:9b334a45a8ff 721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
bogdanm 0:9b334a45a8ff 722 }
bogdanm 0:9b334a45a8ff 723
bogdanm 0:9b334a45a8ff 724
bogdanm 0:9b334a45a8ff 725 /** \brief System Reset
bogdanm 0:9b334a45a8ff 726
bogdanm 0:9b334a45a8ff 727 The function initiates a system reset request to reset the MCU.
bogdanm 0:9b334a45a8ff 728 */
bogdanm 0:9b334a45a8ff 729 __STATIC_INLINE void NVIC_SystemReset(void)
bogdanm 0:9b334a45a8ff 730 {
bogdanm 0:9b334a45a8ff 731 __DSB(); /* Ensure all outstanding memory accesses included
bogdanm 0:9b334a45a8ff 732 buffered write are completed before reset */
bogdanm 0:9b334a45a8ff 733 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
bogdanm 0:9b334a45a8ff 734 SCB_AIRCR_SYSRESETREQ_Msk);
bogdanm 0:9b334a45a8ff 735 __DSB(); /* Ensure completion of memory access */
bogdanm 0:9b334a45a8ff 736 while(1); /* wait until reset */
bogdanm 0:9b334a45a8ff 737 }
bogdanm 0:9b334a45a8ff 738
bogdanm 0:9b334a45a8ff 739 /*@} end of CMSIS_Core_NVICFunctions */
bogdanm 0:9b334a45a8ff 740
bogdanm 0:9b334a45a8ff 741
bogdanm 0:9b334a45a8ff 742
bogdanm 0:9b334a45a8ff 743 /* ################################## SysTick function ############################################ */
bogdanm 0:9b334a45a8ff 744 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 0:9b334a45a8ff 745 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
bogdanm 0:9b334a45a8ff 746 \brief Functions that configure the System.
bogdanm 0:9b334a45a8ff 747 @{
bogdanm 0:9b334a45a8ff 748 */
bogdanm 0:9b334a45a8ff 749
bogdanm 0:9b334a45a8ff 750 #if (__Vendor_SysTickConfig == 0)
bogdanm 0:9b334a45a8ff 751
bogdanm 0:9b334a45a8ff 752 /** \brief System Tick Configuration
bogdanm 0:9b334a45a8ff 753
bogdanm 0:9b334a45a8ff 754 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
bogdanm 0:9b334a45a8ff 755 Counter is in free running mode to generate periodic interrupts.
bogdanm 0:9b334a45a8ff 756
bogdanm 0:9b334a45a8ff 757 \param [in] ticks Number of ticks between two interrupts.
bogdanm 0:9b334a45a8ff 758
bogdanm 0:9b334a45a8ff 759 \return 0 Function succeeded.
bogdanm 0:9b334a45a8ff 760 \return 1 Function failed.
bogdanm 0:9b334a45a8ff 761
bogdanm 0:9b334a45a8ff 762 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
bogdanm 0:9b334a45a8ff 763 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
bogdanm 0:9b334a45a8ff 764 must contain a vendor-specific implementation of this function.
bogdanm 0:9b334a45a8ff 765
bogdanm 0:9b334a45a8ff 766 */
bogdanm 0:9b334a45a8ff 767 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
bogdanm 0:9b334a45a8ff 768 {
bogdanm 0:9b334a45a8ff 769 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
bogdanm 0:9b334a45a8ff 770
bogdanm 0:9b334a45a8ff 771 SysTick->LOAD = ticks - 1; /* set reload register */
bogdanm 0:9b334a45a8ff 772 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
bogdanm 0:9b334a45a8ff 773 SysTick->VAL = 0; /* Load the SysTick Counter Value */
bogdanm 0:9b334a45a8ff 774 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
bogdanm 0:9b334a45a8ff 775 SysTick_CTRL_TICKINT_Msk |
bogdanm 0:9b334a45a8ff 776 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
bogdanm 0:9b334a45a8ff 777 return (0); /* Function successful */
bogdanm 0:9b334a45a8ff 778 }
bogdanm 0:9b334a45a8ff 779
bogdanm 0:9b334a45a8ff 780 #endif
bogdanm 0:9b334a45a8ff 781
bogdanm 0:9b334a45a8ff 782 /*@} end of CMSIS_Core_SysTickFunctions */
bogdanm 0:9b334a45a8ff 783
bogdanm 0:9b334a45a8ff 784
bogdanm 0:9b334a45a8ff 785
bogdanm 0:9b334a45a8ff 786
bogdanm 0:9b334a45a8ff 787 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
bogdanm 0:9b334a45a8ff 788
bogdanm 0:9b334a45a8ff 789 #endif /* __CMSIS_GENERIC */
bogdanm 0:9b334a45a8ff 790
bogdanm 0:9b334a45a8ff 791 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 792 }
bogdanm 0:9b334a45a8ff 793 #endif