raspiezo / mbed-dev

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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/device/TOOLCHAIN_GCC_ARM/startup_MK64F12.S@154:37f96f9d4de2, 2017-01-04 (annotated)

Committer:
<>
Date:
Wed Jan 04 16:58:05 2017 +0000
Revision:
154:37f96f9d4de2
This updates the lib to the mbed lib v133

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /* ---------------------------------------------------------------------------------------*/
<> 154:37f96f9d4de2 2 /* @file: startup_MK64F12.s */
<> 154:37f96f9d4de2 3 /* @purpose: CMSIS Cortex-M4 Core Device Startup File */
<> 154:37f96f9d4de2 4 /* MK64F12 */
<> 154:37f96f9d4de2 5 /* @version: 2.9 */
<> 154:37f96f9d4de2 6 /* @date: 2016-3-21 */
<> 154:37f96f9d4de2 7 /* @build: b160321 */
<> 154:37f96f9d4de2 8 /* ---------------------------------------------------------------------------------------*/
<> 154:37f96f9d4de2 9 /* */
<> 154:37f96f9d4de2 10 /* Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. */
<> 154:37f96f9d4de2 11 /* All rights reserved. */
<> 154:37f96f9d4de2 12 /* */
<> 154:37f96f9d4de2 13 /* Redistribution and use in source and binary forms, with or without modification, */
<> 154:37f96f9d4de2 14 /* are permitted provided that the following conditions are met: */
<> 154:37f96f9d4de2 15 /* */
<> 154:37f96f9d4de2 16 /* o Redistributions of source code must retain the above copyright notice, this list */
<> 154:37f96f9d4de2 17 /* of conditions and the following disclaimer. */
<> 154:37f96f9d4de2 18 /* */
<> 154:37f96f9d4de2 19 /* o Redistributions in binary form must reproduce the above copyright notice, this */
<> 154:37f96f9d4de2 20 /* list of conditions and the following disclaimer in the documentation and/or */
<> 154:37f96f9d4de2 21 /* other materials provided with the distribution. */
<> 154:37f96f9d4de2 22 /* */
<> 154:37f96f9d4de2 23 /* o Neither the name of Freescale Semiconductor, Inc. nor the names of its */
<> 154:37f96f9d4de2 24 /* contributors may be used to endorse or promote products derived from this */
<> 154:37f96f9d4de2 25 /* software without specific prior written permission. */
<> 154:37f96f9d4de2 26 /* */
<> 154:37f96f9d4de2 27 /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */
<> 154:37f96f9d4de2 28 /* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */
<> 154:37f96f9d4de2 29 /* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
<> 154:37f96f9d4de2 30 /* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */
<> 154:37f96f9d4de2 31 /* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
<> 154:37f96f9d4de2 32 /* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */
<> 154:37f96f9d4de2 33 /* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */
<> 154:37f96f9d4de2 34 /* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
<> 154:37f96f9d4de2 35 /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */
<> 154:37f96f9d4de2 36 /* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
<> 154:37f96f9d4de2 37 /*****************************************************************************/
<> 154:37f96f9d4de2 38 /* Version: GCC for ARM Embedded Processors */
<> 154:37f96f9d4de2 39 /*****************************************************************************/
<> 154:37f96f9d4de2 40 .syntax unified
<> 154:37f96f9d4de2 41 .arch armv7-m
<> 154:37f96f9d4de2 42
<> 154:37f96f9d4de2 43 .section .isr_vector, "a"
<> 154:37f96f9d4de2 44 .align 2
<> 154:37f96f9d4de2 45 .globl __isr_vector
<> 154:37f96f9d4de2 46 __isr_vector:
<> 154:37f96f9d4de2 47 .long __StackTop /* Top of Stack */
<> 154:37f96f9d4de2 48 .long Reset_Handler /* Reset Handler */
<> 154:37f96f9d4de2 49 .long NMI_Handler /* NMI Handler*/
<> 154:37f96f9d4de2 50 .long HardFault_Handler /* Hard Fault Handler*/
<> 154:37f96f9d4de2 51 .long MemManage_Handler /* MPU Fault Handler*/
<> 154:37f96f9d4de2 52 .long BusFault_Handler /* Bus Fault Handler*/
<> 154:37f96f9d4de2 53 .long UsageFault_Handler /* Usage Fault Handler*/
<> 154:37f96f9d4de2 54 .long 0 /* Reserved*/
<> 154:37f96f9d4de2 55 .long 0 /* Reserved*/
<> 154:37f96f9d4de2 56 .long 0 /* Reserved*/
<> 154:37f96f9d4de2 57 .long 0 /* Reserved*/
<> 154:37f96f9d4de2 58 .long SVC_Handler /* SVCall Handler*/
<> 154:37f96f9d4de2 59 .long DebugMon_Handler /* Debug Monitor Handler*/
<> 154:37f96f9d4de2 60 .long 0 /* Reserved*/
<> 154:37f96f9d4de2 61 .long PendSV_Handler /* PendSV Handler*/
<> 154:37f96f9d4de2 62 .long SysTick_Handler /* SysTick Handler*/
<> 154:37f96f9d4de2 63
<> 154:37f96f9d4de2 64 /* External Interrupts*/
<> 154:37f96f9d4de2 65 .long DMA0_IRQHandler /* DMA Channel 0 Transfer Complete*/
<> 154:37f96f9d4de2 66 .long DMA1_IRQHandler /* DMA Channel 1 Transfer Complete*/
<> 154:37f96f9d4de2 67 .long DMA2_IRQHandler /* DMA Channel 2 Transfer Complete*/
<> 154:37f96f9d4de2 68 .long DMA3_IRQHandler /* DMA Channel 3 Transfer Complete*/
<> 154:37f96f9d4de2 69 .long DMA4_IRQHandler /* DMA Channel 4 Transfer Complete*/
<> 154:37f96f9d4de2 70 .long DMA5_IRQHandler /* DMA Channel 5 Transfer Complete*/
<> 154:37f96f9d4de2 71 .long DMA6_IRQHandler /* DMA Channel 6 Transfer Complete*/
<> 154:37f96f9d4de2 72 .long DMA7_IRQHandler /* DMA Channel 7 Transfer Complete*/
<> 154:37f96f9d4de2 73 .long DMA8_IRQHandler /* DMA Channel 8 Transfer Complete*/
<> 154:37f96f9d4de2 74 .long DMA9_IRQHandler /* DMA Channel 9 Transfer Complete*/
<> 154:37f96f9d4de2 75 .long DMA10_IRQHandler /* DMA Channel 10 Transfer Complete*/
<> 154:37f96f9d4de2 76 .long DMA11_IRQHandler /* DMA Channel 11 Transfer Complete*/
<> 154:37f96f9d4de2 77 .long DMA12_IRQHandler /* DMA Channel 12 Transfer Complete*/
<> 154:37f96f9d4de2 78 .long DMA13_IRQHandler /* DMA Channel 13 Transfer Complete*/
<> 154:37f96f9d4de2 79 .long DMA14_IRQHandler /* DMA Channel 14 Transfer Complete*/
<> 154:37f96f9d4de2 80 .long DMA15_IRQHandler /* DMA Channel 15 Transfer Complete*/
<> 154:37f96f9d4de2 81 .long DMA_Error_IRQHandler /* DMA Error Interrupt*/
<> 154:37f96f9d4de2 82 .long MCM_IRQHandler /* Normal Interrupt*/
<> 154:37f96f9d4de2 83 .long FTFE_IRQHandler /* FTFE Command complete interrupt*/
<> 154:37f96f9d4de2 84 .long Read_Collision_IRQHandler /* Read Collision Interrupt*/
<> 154:37f96f9d4de2 85 .long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning*/
<> 154:37f96f9d4de2 86 .long LLWU_IRQHandler /* Low Leakage Wakeup Unit*/
<> 154:37f96f9d4de2 87 .long WDOG_EWM_IRQHandler /* WDOG Interrupt*/
<> 154:37f96f9d4de2 88 .long RNG_IRQHandler /* RNG Interrupt*/
<> 154:37f96f9d4de2 89 .long I2C0_IRQHandler /* I2C0 interrupt*/
<> 154:37f96f9d4de2 90 .long I2C1_IRQHandler /* I2C1 interrupt*/
<> 154:37f96f9d4de2 91 .long SPI0_IRQHandler /* SPI0 Interrupt*/
<> 154:37f96f9d4de2 92 .long SPI1_IRQHandler /* SPI1 Interrupt*/
<> 154:37f96f9d4de2 93 .long I2S0_Tx_IRQHandler /* I2S0 transmit interrupt*/
<> 154:37f96f9d4de2 94 .long I2S0_Rx_IRQHandler /* I2S0 receive interrupt*/
<> 154:37f96f9d4de2 95 .long UART0_LON_IRQHandler /* UART0 LON interrupt*/
<> 154:37f96f9d4de2 96 .long UART0_RX_TX_IRQHandler /* UART0 Receive/Transmit interrupt*/
<> 154:37f96f9d4de2 97 .long UART0_ERR_IRQHandler /* UART0 Error interrupt*/
<> 154:37f96f9d4de2 98 .long UART1_RX_TX_IRQHandler /* UART1 Receive/Transmit interrupt*/
<> 154:37f96f9d4de2 99 .long UART1_ERR_IRQHandler /* UART1 Error interrupt*/
<> 154:37f96f9d4de2 100 .long UART2_RX_TX_IRQHandler /* UART2 Receive/Transmit interrupt*/
<> 154:37f96f9d4de2 101 .long UART2_ERR_IRQHandler /* UART2 Error interrupt*/
<> 154:37f96f9d4de2 102 .long UART3_RX_TX_IRQHandler /* UART3 Receive/Transmit interrupt*/
<> 154:37f96f9d4de2 103 .long UART3_ERR_IRQHandler /* UART3 Error interrupt*/
<> 154:37f96f9d4de2 104 .long ADC0_IRQHandler /* ADC0 interrupt*/
<> 154:37f96f9d4de2 105 .long CMP0_IRQHandler /* CMP0 interrupt*/
<> 154:37f96f9d4de2 106 .long CMP1_IRQHandler /* CMP1 interrupt*/
<> 154:37f96f9d4de2 107 .long FTM0_IRQHandler /* FTM0 fault, overflow and channels interrupt*/
<> 154:37f96f9d4de2 108 .long FTM1_IRQHandler /* FTM1 fault, overflow and channels interrupt*/
<> 154:37f96f9d4de2 109 .long FTM2_IRQHandler /* FTM2 fault, overflow and channels interrupt*/
<> 154:37f96f9d4de2 110 .long CMT_IRQHandler /* CMT interrupt*/
<> 154:37f96f9d4de2 111 .long RTC_IRQHandler /* RTC interrupt*/
<> 154:37f96f9d4de2 112 .long RTC_Seconds_IRQHandler /* RTC seconds interrupt*/
<> 154:37f96f9d4de2 113 .long PIT0_IRQHandler /* PIT timer channel 0 interrupt*/
<> 154:37f96f9d4de2 114 .long PIT1_IRQHandler /* PIT timer channel 1 interrupt*/
<> 154:37f96f9d4de2 115 .long PIT2_IRQHandler /* PIT timer channel 2 interrupt*/
<> 154:37f96f9d4de2 116 .long PIT3_IRQHandler /* PIT timer channel 3 interrupt*/
<> 154:37f96f9d4de2 117 .long PDB0_IRQHandler /* PDB0 Interrupt*/
<> 154:37f96f9d4de2 118 .long USB0_IRQHandler /* USB0 interrupt*/
<> 154:37f96f9d4de2 119 .long USBDCD_IRQHandler /* USBDCD Interrupt*/
<> 154:37f96f9d4de2 120 .long Reserved71_IRQHandler /* Reserved interrupt 71*/
<> 154:37f96f9d4de2 121 .long DAC0_IRQHandler /* DAC0 interrupt*/
<> 154:37f96f9d4de2 122 .long MCG_IRQHandler /* MCG Interrupt*/
<> 154:37f96f9d4de2 123 .long LPTMR0_IRQHandler /* LPTimer interrupt*/
<> 154:37f96f9d4de2 124 .long PORTA_IRQHandler /* Port A interrupt*/
<> 154:37f96f9d4de2 125 .long PORTB_IRQHandler /* Port B interrupt*/
<> 154:37f96f9d4de2 126 .long PORTC_IRQHandler /* Port C interrupt*/
<> 154:37f96f9d4de2 127 .long PORTD_IRQHandler /* Port D interrupt*/
<> 154:37f96f9d4de2 128 .long PORTE_IRQHandler /* Port E interrupt*/
<> 154:37f96f9d4de2 129 .long SWI_IRQHandler /* Software interrupt*/
<> 154:37f96f9d4de2 130 .long SPI2_IRQHandler /* SPI2 Interrupt*/
<> 154:37f96f9d4de2 131 .long UART4_RX_TX_IRQHandler /* UART4 Receive/Transmit interrupt*/
<> 154:37f96f9d4de2 132 .long UART4_ERR_IRQHandler /* UART4 Error interrupt*/
<> 154:37f96f9d4de2 133 .long UART5_RX_TX_IRQHandler /* UART5 Receive/Transmit interrupt*/
<> 154:37f96f9d4de2 134 .long UART5_ERR_IRQHandler /* UART5 Error interrupt*/
<> 154:37f96f9d4de2 135 .long CMP2_IRQHandler /* CMP2 interrupt*/
<> 154:37f96f9d4de2 136 .long FTM3_IRQHandler /* FTM3 fault, overflow and channels interrupt*/
<> 154:37f96f9d4de2 137 .long DAC1_IRQHandler /* DAC1 interrupt*/
<> 154:37f96f9d4de2 138 .long ADC1_IRQHandler /* ADC1 interrupt*/
<> 154:37f96f9d4de2 139 .long I2C2_IRQHandler /* I2C2 interrupt*/
<> 154:37f96f9d4de2 140 .long CAN0_ORed_Message_buffer_IRQHandler /* CAN0 OR'd message buffers interrupt*/
<> 154:37f96f9d4de2 141 .long CAN0_Bus_Off_IRQHandler /* CAN0 bus off interrupt*/
<> 154:37f96f9d4de2 142 .long CAN0_Error_IRQHandler /* CAN0 error interrupt*/
<> 154:37f96f9d4de2 143 .long CAN0_Tx_Warning_IRQHandler /* CAN0 Tx warning interrupt*/
<> 154:37f96f9d4de2 144 .long CAN0_Rx_Warning_IRQHandler /* CAN0 Rx warning interrupt*/
<> 154:37f96f9d4de2 145 .long CAN0_Wake_Up_IRQHandler /* CAN0 wake up interrupt*/
<> 154:37f96f9d4de2 146 .long SDHC_IRQHandler /* SDHC interrupt*/
<> 154:37f96f9d4de2 147 .long ENET_1588_Timer_IRQHandler /* Ethernet MAC IEEE 1588 Timer Interrupt*/
<> 154:37f96f9d4de2 148 .long ENET_Transmit_IRQHandler /* Ethernet MAC Transmit Interrupt*/
<> 154:37f96f9d4de2 149 .long ENET_Receive_IRQHandler /* Ethernet MAC Receive Interrupt*/
<> 154:37f96f9d4de2 150 .long ENET_Error_IRQHandler /* Ethernet MAC Error and miscelaneous Interrupt*/
<> 154:37f96f9d4de2 151 .long DefaultISR /* 102*/
<> 154:37f96f9d4de2 152 .long DefaultISR /* 103*/
<> 154:37f96f9d4de2 153 .long DefaultISR /* 104*/
<> 154:37f96f9d4de2 154 .long DefaultISR /* 105*/
<> 154:37f96f9d4de2 155 .long DefaultISR /* 106*/
<> 154:37f96f9d4de2 156 .long DefaultISR /* 107*/
<> 154:37f96f9d4de2 157 .long DefaultISR /* 108*/
<> 154:37f96f9d4de2 158 .long DefaultISR /* 109*/
<> 154:37f96f9d4de2 159 .long DefaultISR /* 110*/
<> 154:37f96f9d4de2 160 .long DefaultISR /* 111*/
<> 154:37f96f9d4de2 161 .long DefaultISR /* 112*/
<> 154:37f96f9d4de2 162 .long DefaultISR /* 113*/
<> 154:37f96f9d4de2 163 .long DefaultISR /* 114*/
<> 154:37f96f9d4de2 164 .long DefaultISR /* 115*/
<> 154:37f96f9d4de2 165 .long DefaultISR /* 116*/
<> 154:37f96f9d4de2 166 .long DefaultISR /* 117*/
<> 154:37f96f9d4de2 167 .long DefaultISR /* 118*/
<> 154:37f96f9d4de2 168 .long DefaultISR /* 119*/
<> 154:37f96f9d4de2 169 .long DefaultISR /* 120*/
<> 154:37f96f9d4de2 170 .long DefaultISR /* 121*/
<> 154:37f96f9d4de2 171 .long DefaultISR /* 122*/
<> 154:37f96f9d4de2 172 .long DefaultISR /* 123*/
<> 154:37f96f9d4de2 173 .long DefaultISR /* 124*/
<> 154:37f96f9d4de2 174 .long DefaultISR /* 125*/
<> 154:37f96f9d4de2 175 .long DefaultISR /* 126*/
<> 154:37f96f9d4de2 176 .long DefaultISR /* 127*/
<> 154:37f96f9d4de2 177 .long DefaultISR /* 128*/
<> 154:37f96f9d4de2 178 .long DefaultISR /* 129*/
<> 154:37f96f9d4de2 179 .long DefaultISR /* 130*/
<> 154:37f96f9d4de2 180 .long DefaultISR /* 131*/
<> 154:37f96f9d4de2 181 .long DefaultISR /* 132*/
<> 154:37f96f9d4de2 182 .long DefaultISR /* 133*/
<> 154:37f96f9d4de2 183 .long DefaultISR /* 134*/
<> 154:37f96f9d4de2 184 .long DefaultISR /* 135*/
<> 154:37f96f9d4de2 185 .long DefaultISR /* 136*/
<> 154:37f96f9d4de2 186 .long DefaultISR /* 137*/
<> 154:37f96f9d4de2 187 .long DefaultISR /* 138*/
<> 154:37f96f9d4de2 188 .long DefaultISR /* 139*/
<> 154:37f96f9d4de2 189 .long DefaultISR /* 140*/
<> 154:37f96f9d4de2 190 .long DefaultISR /* 141*/
<> 154:37f96f9d4de2 191 .long DefaultISR /* 142*/
<> 154:37f96f9d4de2 192 .long DefaultISR /* 143*/
<> 154:37f96f9d4de2 193 .long DefaultISR /* 144*/
<> 154:37f96f9d4de2 194 .long DefaultISR /* 145*/
<> 154:37f96f9d4de2 195 .long DefaultISR /* 146*/
<> 154:37f96f9d4de2 196 .long DefaultISR /* 147*/
<> 154:37f96f9d4de2 197 .long DefaultISR /* 148*/
<> 154:37f96f9d4de2 198 .long DefaultISR /* 149*/
<> 154:37f96f9d4de2 199 .long DefaultISR /* 150*/
<> 154:37f96f9d4de2 200 .long DefaultISR /* 151*/
<> 154:37f96f9d4de2 201 .long DefaultISR /* 152*/
<> 154:37f96f9d4de2 202 .long DefaultISR /* 153*/
<> 154:37f96f9d4de2 203 .long DefaultISR /* 154*/
<> 154:37f96f9d4de2 204 .long DefaultISR /* 155*/
<> 154:37f96f9d4de2 205 .long DefaultISR /* 156*/
<> 154:37f96f9d4de2 206 .long DefaultISR /* 157*/
<> 154:37f96f9d4de2 207 .long DefaultISR /* 158*/
<> 154:37f96f9d4de2 208 .long DefaultISR /* 159*/
<> 154:37f96f9d4de2 209 .long DefaultISR /* 160*/
<> 154:37f96f9d4de2 210 .long DefaultISR /* 161*/
<> 154:37f96f9d4de2 211 .long DefaultISR /* 162*/
<> 154:37f96f9d4de2 212 .long DefaultISR /* 163*/
<> 154:37f96f9d4de2 213 .long DefaultISR /* 164*/
<> 154:37f96f9d4de2 214 .long DefaultISR /* 165*/
<> 154:37f96f9d4de2 215 .long DefaultISR /* 166*/
<> 154:37f96f9d4de2 216 .long DefaultISR /* 167*/
<> 154:37f96f9d4de2 217 .long DefaultISR /* 168*/
<> 154:37f96f9d4de2 218 .long DefaultISR /* 169*/
<> 154:37f96f9d4de2 219 .long DefaultISR /* 170*/
<> 154:37f96f9d4de2 220 .long DefaultISR /* 171*/
<> 154:37f96f9d4de2 221 .long DefaultISR /* 172*/
<> 154:37f96f9d4de2 222 .long DefaultISR /* 173*/
<> 154:37f96f9d4de2 223 .long DefaultISR /* 174*/
<> 154:37f96f9d4de2 224 .long DefaultISR /* 175*/
<> 154:37f96f9d4de2 225 .long DefaultISR /* 176*/
<> 154:37f96f9d4de2 226 .long DefaultISR /* 177*/
<> 154:37f96f9d4de2 227 .long DefaultISR /* 178*/
<> 154:37f96f9d4de2 228 .long DefaultISR /* 179*/
<> 154:37f96f9d4de2 229 .long DefaultISR /* 180*/
<> 154:37f96f9d4de2 230 .long DefaultISR /* 181*/
<> 154:37f96f9d4de2 231 .long DefaultISR /* 182*/
<> 154:37f96f9d4de2 232 .long DefaultISR /* 183*/
<> 154:37f96f9d4de2 233 .long DefaultISR /* 184*/
<> 154:37f96f9d4de2 234 .long DefaultISR /* 185*/
<> 154:37f96f9d4de2 235 .long DefaultISR /* 186*/
<> 154:37f96f9d4de2 236 .long DefaultISR /* 187*/
<> 154:37f96f9d4de2 237 .long DefaultISR /* 188*/
<> 154:37f96f9d4de2 238 .long DefaultISR /* 189*/
<> 154:37f96f9d4de2 239 .long DefaultISR /* 190*/
<> 154:37f96f9d4de2 240 .long DefaultISR /* 191*/
<> 154:37f96f9d4de2 241 .long DefaultISR /* 192*/
<> 154:37f96f9d4de2 242 .long DefaultISR /* 193*/
<> 154:37f96f9d4de2 243 .long DefaultISR /* 194*/
<> 154:37f96f9d4de2 244 .long DefaultISR /* 195*/
<> 154:37f96f9d4de2 245 .long DefaultISR /* 196*/
<> 154:37f96f9d4de2 246 .long DefaultISR /* 197*/
<> 154:37f96f9d4de2 247 .long DefaultISR /* 198*/
<> 154:37f96f9d4de2 248 .long DefaultISR /* 199*/
<> 154:37f96f9d4de2 249 .long DefaultISR /* 200*/
<> 154:37f96f9d4de2 250 .long DefaultISR /* 201*/
<> 154:37f96f9d4de2 251 .long DefaultISR /* 202*/
<> 154:37f96f9d4de2 252 .long DefaultISR /* 203*/
<> 154:37f96f9d4de2 253 .long DefaultISR /* 204*/
<> 154:37f96f9d4de2 254 .long DefaultISR /* 205*/
<> 154:37f96f9d4de2 255 .long DefaultISR /* 206*/
<> 154:37f96f9d4de2 256 .long DefaultISR /* 207*/
<> 154:37f96f9d4de2 257 .long DefaultISR /* 208*/
<> 154:37f96f9d4de2 258 .long DefaultISR /* 209*/
<> 154:37f96f9d4de2 259 .long DefaultISR /* 210*/
<> 154:37f96f9d4de2 260 .long DefaultISR /* 211*/
<> 154:37f96f9d4de2 261 .long DefaultISR /* 212*/
<> 154:37f96f9d4de2 262 .long DefaultISR /* 213*/
<> 154:37f96f9d4de2 263 .long DefaultISR /* 214*/
<> 154:37f96f9d4de2 264 .long DefaultISR /* 215*/
<> 154:37f96f9d4de2 265 .long DefaultISR /* 216*/
<> 154:37f96f9d4de2 266 .long DefaultISR /* 217*/
<> 154:37f96f9d4de2 267 .long DefaultISR /* 218*/
<> 154:37f96f9d4de2 268 .long DefaultISR /* 219*/
<> 154:37f96f9d4de2 269 .long DefaultISR /* 220*/
<> 154:37f96f9d4de2 270 .long DefaultISR /* 221*/
<> 154:37f96f9d4de2 271 .long DefaultISR /* 222*/
<> 154:37f96f9d4de2 272 .long DefaultISR /* 223*/
<> 154:37f96f9d4de2 273 .long DefaultISR /* 224*/
<> 154:37f96f9d4de2 274 .long DefaultISR /* 225*/
<> 154:37f96f9d4de2 275 .long DefaultISR /* 226*/
<> 154:37f96f9d4de2 276 .long DefaultISR /* 227*/
<> 154:37f96f9d4de2 277 .long DefaultISR /* 228*/
<> 154:37f96f9d4de2 278 .long DefaultISR /* 229*/
<> 154:37f96f9d4de2 279 .long DefaultISR /* 230*/
<> 154:37f96f9d4de2 280 .long DefaultISR /* 231*/
<> 154:37f96f9d4de2 281 .long DefaultISR /* 232*/
<> 154:37f96f9d4de2 282 .long DefaultISR /* 233*/
<> 154:37f96f9d4de2 283 .long DefaultISR /* 234*/
<> 154:37f96f9d4de2 284 .long DefaultISR /* 235*/
<> 154:37f96f9d4de2 285 .long DefaultISR /* 236*/
<> 154:37f96f9d4de2 286 .long DefaultISR /* 237*/
<> 154:37f96f9d4de2 287 .long DefaultISR /* 238*/
<> 154:37f96f9d4de2 288 .long DefaultISR /* 239*/
<> 154:37f96f9d4de2 289 .long DefaultISR /* 240*/
<> 154:37f96f9d4de2 290 .long DefaultISR /* 241*/
<> 154:37f96f9d4de2 291 .long DefaultISR /* 242*/
<> 154:37f96f9d4de2 292 .long DefaultISR /* 243*/
<> 154:37f96f9d4de2 293 .long DefaultISR /* 244*/
<> 154:37f96f9d4de2 294 .long DefaultISR /* 245*/
<> 154:37f96f9d4de2 295 .long DefaultISR /* 246*/
<> 154:37f96f9d4de2 296 .long DefaultISR /* 247*/
<> 154:37f96f9d4de2 297 .long DefaultISR /* 248*/
<> 154:37f96f9d4de2 298 .long DefaultISR /* 249*/
<> 154:37f96f9d4de2 299 .long DefaultISR /* 250*/
<> 154:37f96f9d4de2 300 .long DefaultISR /* 251*/
<> 154:37f96f9d4de2 301 .long DefaultISR /* 252*/
<> 154:37f96f9d4de2 302 .long DefaultISR /* 253*/
<> 154:37f96f9d4de2 303 .long DefaultISR /* 254*/
<> 154:37f96f9d4de2 304 .long 0xFFFFFFFF /* Reserved for user TRIM value*/
<> 154:37f96f9d4de2 305
<> 154:37f96f9d4de2 306 .size __isr_vector, . - __isr_vector
<> 154:37f96f9d4de2 307
<> 154:37f96f9d4de2 308 /* Flash Configuration */
<> 154:37f96f9d4de2 309 .section .FlashConfig, "a"
<> 154:37f96f9d4de2 310 .long 0xFFFFFFFF
<> 154:37f96f9d4de2 311 .long 0xFFFFFFFF
<> 154:37f96f9d4de2 312 .long 0xFFFFFFFF
<> 154:37f96f9d4de2 313 .long 0xFFFFFFFE
<> 154:37f96f9d4de2 314
<> 154:37f96f9d4de2 315 .text
<> 154:37f96f9d4de2 316 .thumb
<> 154:37f96f9d4de2 317
<> 154:37f96f9d4de2 318 /* Reset Handler */
<> 154:37f96f9d4de2 319
<> 154:37f96f9d4de2 320 .thumb_func
<> 154:37f96f9d4de2 321 .align 2
<> 154:37f96f9d4de2 322 .globl Reset_Handler
<> 154:37f96f9d4de2 323 .weak Reset_Handler
<> 154:37f96f9d4de2 324 .type Reset_Handler, %function
<> 154:37f96f9d4de2 325 Reset_Handler:
<> 154:37f96f9d4de2 326 cpsid i /* Mask interrupts */
<> 154:37f96f9d4de2 327 .equ VTOR, 0xE000ED08
<> 154:37f96f9d4de2 328 ldr r0, =VTOR
<> 154:37f96f9d4de2 329 ldr r1, =__isr_vector
<> 154:37f96f9d4de2 330 str r1, [r0]
<> 154:37f96f9d4de2 331 #ifndef __NO_SYSTEM_INIT
<> 154:37f96f9d4de2 332 ldr r0,=SystemInit
<> 154:37f96f9d4de2 333 blx r0
<> 154:37f96f9d4de2 334 #endif
<> 154:37f96f9d4de2 335
<> 154:37f96f9d4de2 336 /* The call to uvisor_init() happens independently of uVisor being enabled or
<> 154:37f96f9d4de2 337 * not, so it is conditionally compiled only based on FEATURE_UVISOR. */
<> 154:37f96f9d4de2 338 #ifdef FEATURE_UVISOR
<> 154:37f96f9d4de2 339 /* Call uvisor_init() */
<> 154:37f96f9d4de2 340 ldr r0, =uvisor_init
<> 154:37f96f9d4de2 341 blx r0
<> 154:37f96f9d4de2 342 #endif /* FEATURE_UVISOR */
<> 154:37f96f9d4de2 343
<> 154:37f96f9d4de2 344 /* Loop to copy data from read only memory to RAM. The ranges
<> 154:37f96f9d4de2 345 * of copy from/to are specified by following symbols evaluated in
<> 154:37f96f9d4de2 346 * linker script.
<> 154:37f96f9d4de2 347 * __etext: End of code section, i.e., begin of data sections to copy from.
<> 154:37f96f9d4de2 348 * __data_start__/__data_end__: RAM address range that data should be
<> 154:37f96f9d4de2 349 * copied to. Both must be aligned to 4 bytes boundary. */
<> 154:37f96f9d4de2 350
<> 154:37f96f9d4de2 351 ldr r1, =__etext
<> 154:37f96f9d4de2 352 ldr r2, =__data_start__
<> 154:37f96f9d4de2 353 ldr r3, =__data_end__
<> 154:37f96f9d4de2 354
<> 154:37f96f9d4de2 355 #if 1
<> 154:37f96f9d4de2 356 /* Here are two copies of loop implemenations. First one favors code size
<> 154:37f96f9d4de2 357 * and the second one favors performance. Default uses the first one.
<> 154:37f96f9d4de2 358 * Change to "#if 0" to use the second one */
<> 154:37f96f9d4de2 359 .LC0:
<> 154:37f96f9d4de2 360 cmp r2, r3
<> 154:37f96f9d4de2 361 ittt lt
<> 154:37f96f9d4de2 362 ldrlt r0, [r1], #4
<> 154:37f96f9d4de2 363 strlt r0, [r2], #4
<> 154:37f96f9d4de2 364 blt .LC0
<> 154:37f96f9d4de2 365 #else
<> 154:37f96f9d4de2 366 subs r3, r2
<> 154:37f96f9d4de2 367 ble .LC1
<> 154:37f96f9d4de2 368 .LC0:
<> 154:37f96f9d4de2 369 subs r3, #4
<> 154:37f96f9d4de2 370 ldr r0, [r1, r3]
<> 154:37f96f9d4de2 371 str r0, [r2, r3]
<> 154:37f96f9d4de2 372 bgt .LC0
<> 154:37f96f9d4de2 373 .LC1:
<> 154:37f96f9d4de2 374 #endif
<> 154:37f96f9d4de2 375
<> 154:37f96f9d4de2 376 #ifdef __STARTUP_CLEAR_BSS
<> 154:37f96f9d4de2 377 /* This part of work usually is done in C library startup code. Otherwise,
<> 154:37f96f9d4de2 378 * define this macro to enable it in this startup.
<> 154:37f96f9d4de2 379 *
<> 154:37f96f9d4de2 380 * Loop to zero out BSS section, which uses following symbols
<> 154:37f96f9d4de2 381 * in linker script:
<> 154:37f96f9d4de2 382 * __bss_start__: start of BSS section. Must align to 4
<> 154:37f96f9d4de2 383 * __bss_end__: end of BSS section. Must align to 4
<> 154:37f96f9d4de2 384 */
<> 154:37f96f9d4de2 385 ldr r1, =__bss_start__
<> 154:37f96f9d4de2 386 ldr r2, =__bss_end__
<> 154:37f96f9d4de2 387
<> 154:37f96f9d4de2 388 movs r0, 0
<> 154:37f96f9d4de2 389 .LC2:
<> 154:37f96f9d4de2 390 cmp r1, r2
<> 154:37f96f9d4de2 391 itt lt
<> 154:37f96f9d4de2 392 strlt r0, [r1], #4
<> 154:37f96f9d4de2 393 blt .LC2
<> 154:37f96f9d4de2 394 #endif /* __STARTUP_CLEAR_BSS */
<> 154:37f96f9d4de2 395
<> 154:37f96f9d4de2 396 cpsie i /* Unmask interrupts */
<> 154:37f96f9d4de2 397 #ifndef __START
<> 154:37f96f9d4de2 398 #define __START _start
<> 154:37f96f9d4de2 399 #endif
<> 154:37f96f9d4de2 400 #ifndef __ATOLLIC__
<> 154:37f96f9d4de2 401 ldr r0,=__START
<> 154:37f96f9d4de2 402 blx r0
<> 154:37f96f9d4de2 403 #else
<> 154:37f96f9d4de2 404 ldr r0,=__libc_init_array
<> 154:37f96f9d4de2 405 blx r0
<> 154:37f96f9d4de2 406 ldr r0,=main
<> 154:37f96f9d4de2 407 bx r0
<> 154:37f96f9d4de2 408 #endif
<> 154:37f96f9d4de2 409 .pool
<> 154:37f96f9d4de2 410 .size Reset_Handler, . - Reset_Handler
<> 154:37f96f9d4de2 411
<> 154:37f96f9d4de2 412 .align 1
<> 154:37f96f9d4de2 413 .thumb_func
<> 154:37f96f9d4de2 414 .weak DefaultISR
<> 154:37f96f9d4de2 415 .type DefaultISR, %function
<> 154:37f96f9d4de2 416 DefaultISR:
<> 154:37f96f9d4de2 417 b DefaultISR
<> 154:37f96f9d4de2 418 .size DefaultISR, . - DefaultISR
<> 154:37f96f9d4de2 419
<> 154:37f96f9d4de2 420 .align 1
<> 154:37f96f9d4de2 421 .thumb_func
<> 154:37f96f9d4de2 422 .weak NMI_Handler
<> 154:37f96f9d4de2 423 .type NMI_Handler, %function
<> 154:37f96f9d4de2 424 NMI_Handler:
<> 154:37f96f9d4de2 425 ldr r0,=NMI_Handler
<> 154:37f96f9d4de2 426 bx r0
<> 154:37f96f9d4de2 427 .size NMI_Handler, . - NMI_Handler
<> 154:37f96f9d4de2 428
<> 154:37f96f9d4de2 429 .align 1
<> 154:37f96f9d4de2 430 .thumb_func
<> 154:37f96f9d4de2 431 .weak HardFault_Handler
<> 154:37f96f9d4de2 432 .type HardFault_Handler, %function
<> 154:37f96f9d4de2 433 HardFault_Handler:
<> 154:37f96f9d4de2 434 ldr r0,=HardFault_Handler
<> 154:37f96f9d4de2 435 bx r0
<> 154:37f96f9d4de2 436 .size HardFault_Handler, . - HardFault_Handler
<> 154:37f96f9d4de2 437
<> 154:37f96f9d4de2 438 .align 1
<> 154:37f96f9d4de2 439 .thumb_func
<> 154:37f96f9d4de2 440 .weak SVC_Handler
<> 154:37f96f9d4de2 441 .type SVC_Handler, %function
<> 154:37f96f9d4de2 442 SVC_Handler:
<> 154:37f96f9d4de2 443 ldr r0,=SVC_Handler
<> 154:37f96f9d4de2 444 bx r0
<> 154:37f96f9d4de2 445 .size SVC_Handler, . - SVC_Handler
<> 154:37f96f9d4de2 446
<> 154:37f96f9d4de2 447 .align 1
<> 154:37f96f9d4de2 448 .thumb_func
<> 154:37f96f9d4de2 449 .weak PendSV_Handler
<> 154:37f96f9d4de2 450 .type PendSV_Handler, %function
<> 154:37f96f9d4de2 451 PendSV_Handler:
<> 154:37f96f9d4de2 452 ldr r0,=PendSV_Handler
<> 154:37f96f9d4de2 453 bx r0
<> 154:37f96f9d4de2 454 .size PendSV_Handler, . - PendSV_Handler
<> 154:37f96f9d4de2 455
<> 154:37f96f9d4de2 456 .align 1
<> 154:37f96f9d4de2 457 .thumb_func
<> 154:37f96f9d4de2 458 .weak SysTick_Handler
<> 154:37f96f9d4de2 459 .type SysTick_Handler, %function
<> 154:37f96f9d4de2 460 SysTick_Handler:
<> 154:37f96f9d4de2 461 ldr r0,=SysTick_Handler
<> 154:37f96f9d4de2 462 bx r0
<> 154:37f96f9d4de2 463 .size SysTick_Handler, . - SysTick_Handler
<> 154:37f96f9d4de2 464
<> 154:37f96f9d4de2 465 .align 1
<> 154:37f96f9d4de2 466 .thumb_func
<> 154:37f96f9d4de2 467 .weak DMA0_IRQHandler
<> 154:37f96f9d4de2 468 .type DMA0_IRQHandler, %function
<> 154:37f96f9d4de2 469 DMA0_IRQHandler:
<> 154:37f96f9d4de2 470 ldr r0,=DMA0_DriverIRQHandler
<> 154:37f96f9d4de2 471 bx r0
<> 154:37f96f9d4de2 472 .size DMA0_IRQHandler, . - DMA0_IRQHandler
<> 154:37f96f9d4de2 473
<> 154:37f96f9d4de2 474 .align 1
<> 154:37f96f9d4de2 475 .thumb_func
<> 154:37f96f9d4de2 476 .weak DMA1_IRQHandler
<> 154:37f96f9d4de2 477 .type DMA1_IRQHandler, %function
<> 154:37f96f9d4de2 478 DMA1_IRQHandler:
<> 154:37f96f9d4de2 479 ldr r0,=DMA1_DriverIRQHandler
<> 154:37f96f9d4de2 480 bx r0
<> 154:37f96f9d4de2 481 .size DMA1_IRQHandler, . - DMA1_IRQHandler
<> 154:37f96f9d4de2 482
<> 154:37f96f9d4de2 483 .align 1
<> 154:37f96f9d4de2 484 .thumb_func
<> 154:37f96f9d4de2 485 .weak DMA2_IRQHandler
<> 154:37f96f9d4de2 486 .type DMA2_IRQHandler, %function
<> 154:37f96f9d4de2 487 DMA2_IRQHandler:
<> 154:37f96f9d4de2 488 ldr r0,=DMA2_DriverIRQHandler
<> 154:37f96f9d4de2 489 bx r0
<> 154:37f96f9d4de2 490 .size DMA2_IRQHandler, . - DMA2_IRQHandler
<> 154:37f96f9d4de2 491
<> 154:37f96f9d4de2 492 .align 1
<> 154:37f96f9d4de2 493 .thumb_func
<> 154:37f96f9d4de2 494 .weak DMA3_IRQHandler
<> 154:37f96f9d4de2 495 .type DMA3_IRQHandler, %function
<> 154:37f96f9d4de2 496 DMA3_IRQHandler:
<> 154:37f96f9d4de2 497 ldr r0,=DMA3_DriverIRQHandler
<> 154:37f96f9d4de2 498 bx r0
<> 154:37f96f9d4de2 499 .size DMA3_IRQHandler, . - DMA3_IRQHandler
<> 154:37f96f9d4de2 500
<> 154:37f96f9d4de2 501 .align 1
<> 154:37f96f9d4de2 502 .thumb_func
<> 154:37f96f9d4de2 503 .weak DMA4_IRQHandler
<> 154:37f96f9d4de2 504 .type DMA4_IRQHandler, %function
<> 154:37f96f9d4de2 505 DMA4_IRQHandler:
<> 154:37f96f9d4de2 506 ldr r0,=DMA4_DriverIRQHandler
<> 154:37f96f9d4de2 507 bx r0
<> 154:37f96f9d4de2 508 .size DMA4_IRQHandler, . - DMA4_IRQHandler
<> 154:37f96f9d4de2 509
<> 154:37f96f9d4de2 510 .align 1
<> 154:37f96f9d4de2 511 .thumb_func
<> 154:37f96f9d4de2 512 .weak DMA5_IRQHandler
<> 154:37f96f9d4de2 513 .type DMA5_IRQHandler, %function
<> 154:37f96f9d4de2 514 DMA5_IRQHandler:
<> 154:37f96f9d4de2 515 ldr r0,=DMA5_DriverIRQHandler
<> 154:37f96f9d4de2 516 bx r0
<> 154:37f96f9d4de2 517 .size DMA5_IRQHandler, . - DMA5_IRQHandler
<> 154:37f96f9d4de2 518
<> 154:37f96f9d4de2 519 .align 1
<> 154:37f96f9d4de2 520 .thumb_func
<> 154:37f96f9d4de2 521 .weak DMA6_IRQHandler
<> 154:37f96f9d4de2 522 .type DMA6_IRQHandler, %function
<> 154:37f96f9d4de2 523 DMA6_IRQHandler:
<> 154:37f96f9d4de2 524 ldr r0,=DMA6_DriverIRQHandler
<> 154:37f96f9d4de2 525 bx r0
<> 154:37f96f9d4de2 526 .size DMA6_IRQHandler, . - DMA6_IRQHandler
<> 154:37f96f9d4de2 527
<> 154:37f96f9d4de2 528 .align 1
<> 154:37f96f9d4de2 529 .thumb_func
<> 154:37f96f9d4de2 530 .weak DMA7_IRQHandler
<> 154:37f96f9d4de2 531 .type DMA7_IRQHandler, %function
<> 154:37f96f9d4de2 532 DMA7_IRQHandler:
<> 154:37f96f9d4de2 533 ldr r0,=DMA7_DriverIRQHandler
<> 154:37f96f9d4de2 534 bx r0
<> 154:37f96f9d4de2 535 .size DMA7_IRQHandler, . - DMA7_IRQHandler
<> 154:37f96f9d4de2 536
<> 154:37f96f9d4de2 537 .align 1
<> 154:37f96f9d4de2 538 .thumb_func
<> 154:37f96f9d4de2 539 .weak DMA8_IRQHandler
<> 154:37f96f9d4de2 540 .type DMA8_IRQHandler, %function
<> 154:37f96f9d4de2 541 DMA8_IRQHandler:
<> 154:37f96f9d4de2 542 ldr r0,=DMA8_DriverIRQHandler
<> 154:37f96f9d4de2 543 bx r0
<> 154:37f96f9d4de2 544 .size DMA8_IRQHandler, . - DMA8_IRQHandler
<> 154:37f96f9d4de2 545
<> 154:37f96f9d4de2 546 .align 1
<> 154:37f96f9d4de2 547 .thumb_func
<> 154:37f96f9d4de2 548 .weak DMA9_IRQHandler
<> 154:37f96f9d4de2 549 .type DMA9_IRQHandler, %function
<> 154:37f96f9d4de2 550 DMA9_IRQHandler:
<> 154:37f96f9d4de2 551 ldr r0,=DMA9_DriverIRQHandler
<> 154:37f96f9d4de2 552 bx r0
<> 154:37f96f9d4de2 553 .size DMA9_IRQHandler, . - DMA9_IRQHandler
<> 154:37f96f9d4de2 554
<> 154:37f96f9d4de2 555 .align 1
<> 154:37f96f9d4de2 556 .thumb_func
<> 154:37f96f9d4de2 557 .weak DMA10_IRQHandler
<> 154:37f96f9d4de2 558 .type DMA10_IRQHandler, %function
<> 154:37f96f9d4de2 559 DMA10_IRQHandler:
<> 154:37f96f9d4de2 560 ldr r0,=DMA10_DriverIRQHandler
<> 154:37f96f9d4de2 561 bx r0
<> 154:37f96f9d4de2 562 .size DMA10_IRQHandler, . - DMA10_IRQHandler
<> 154:37f96f9d4de2 563
<> 154:37f96f9d4de2 564 .align 1
<> 154:37f96f9d4de2 565 .thumb_func
<> 154:37f96f9d4de2 566 .weak DMA11_IRQHandler
<> 154:37f96f9d4de2 567 .type DMA11_IRQHandler, %function
<> 154:37f96f9d4de2 568 DMA11_IRQHandler:
<> 154:37f96f9d4de2 569 ldr r0,=DMA11_DriverIRQHandler
<> 154:37f96f9d4de2 570 bx r0
<> 154:37f96f9d4de2 571 .size DMA11_IRQHandler, . - DMA11_IRQHandler
<> 154:37f96f9d4de2 572
<> 154:37f96f9d4de2 573 .align 1
<> 154:37f96f9d4de2 574 .thumb_func
<> 154:37f96f9d4de2 575 .weak DMA12_IRQHandler
<> 154:37f96f9d4de2 576 .type DMA12_IRQHandler, %function
<> 154:37f96f9d4de2 577 DMA12_IRQHandler:
<> 154:37f96f9d4de2 578 ldr r0,=DMA12_DriverIRQHandler
<> 154:37f96f9d4de2 579 bx r0
<> 154:37f96f9d4de2 580 .size DMA12_IRQHandler, . - DMA12_IRQHandler
<> 154:37f96f9d4de2 581
<> 154:37f96f9d4de2 582 .align 1
<> 154:37f96f9d4de2 583 .thumb_func
<> 154:37f96f9d4de2 584 .weak DMA13_IRQHandler
<> 154:37f96f9d4de2 585 .type DMA13_IRQHandler, %function
<> 154:37f96f9d4de2 586 DMA13_IRQHandler:
<> 154:37f96f9d4de2 587 ldr r0,=DMA13_DriverIRQHandler
<> 154:37f96f9d4de2 588 bx r0
<> 154:37f96f9d4de2 589 .size DMA13_IRQHandler, . - DMA13_IRQHandler
<> 154:37f96f9d4de2 590
<> 154:37f96f9d4de2 591 .align 1
<> 154:37f96f9d4de2 592 .thumb_func
<> 154:37f96f9d4de2 593 .weak DMA14_IRQHandler
<> 154:37f96f9d4de2 594 .type DMA14_IRQHandler, %function
<> 154:37f96f9d4de2 595 DMA14_IRQHandler:
<> 154:37f96f9d4de2 596 ldr r0,=DMA14_DriverIRQHandler
<> 154:37f96f9d4de2 597 bx r0
<> 154:37f96f9d4de2 598 .size DMA14_IRQHandler, . - DMA14_IRQHandler
<> 154:37f96f9d4de2 599
<> 154:37f96f9d4de2 600 .align 1
<> 154:37f96f9d4de2 601 .thumb_func
<> 154:37f96f9d4de2 602 .weak DMA15_IRQHandler
<> 154:37f96f9d4de2 603 .type DMA15_IRQHandler, %function
<> 154:37f96f9d4de2 604 DMA15_IRQHandler:
<> 154:37f96f9d4de2 605 ldr r0,=DMA15_DriverIRQHandler
<> 154:37f96f9d4de2 606 bx r0
<> 154:37f96f9d4de2 607 .size DMA15_IRQHandler, . - DMA15_IRQHandler
<> 154:37f96f9d4de2 608
<> 154:37f96f9d4de2 609 .align 1
<> 154:37f96f9d4de2 610 .thumb_func
<> 154:37f96f9d4de2 611 .weak DMA_Error_IRQHandler
<> 154:37f96f9d4de2 612 .type DMA_Error_IRQHandler, %function
<> 154:37f96f9d4de2 613 DMA_Error_IRQHandler:
<> 154:37f96f9d4de2 614 ldr r0,=DMA_Error_DriverIRQHandler
<> 154:37f96f9d4de2 615 bx r0
<> 154:37f96f9d4de2 616 .size DMA_Error_IRQHandler, . - DMA_Error_IRQHandler
<> 154:37f96f9d4de2 617
<> 154:37f96f9d4de2 618 .align 1
<> 154:37f96f9d4de2 619 .thumb_func
<> 154:37f96f9d4de2 620 .weak I2C0_IRQHandler
<> 154:37f96f9d4de2 621 .type I2C0_IRQHandler, %function
<> 154:37f96f9d4de2 622 I2C0_IRQHandler:
<> 154:37f96f9d4de2 623 ldr r0,=I2C0_DriverIRQHandler
<> 154:37f96f9d4de2 624 bx r0
<> 154:37f96f9d4de2 625 .size I2C0_IRQHandler, . - I2C0_IRQHandler
<> 154:37f96f9d4de2 626
<> 154:37f96f9d4de2 627 .align 1
<> 154:37f96f9d4de2 628 .thumb_func
<> 154:37f96f9d4de2 629 .weak I2C1_IRQHandler
<> 154:37f96f9d4de2 630 .type I2C1_IRQHandler, %function
<> 154:37f96f9d4de2 631 I2C1_IRQHandler:
<> 154:37f96f9d4de2 632 ldr r0,=I2C1_DriverIRQHandler
<> 154:37f96f9d4de2 633 bx r0
<> 154:37f96f9d4de2 634 .size I2C1_IRQHandler, . - I2C1_IRQHandler
<> 154:37f96f9d4de2 635
<> 154:37f96f9d4de2 636 .align 1
<> 154:37f96f9d4de2 637 .thumb_func
<> 154:37f96f9d4de2 638 .weak SPI0_IRQHandler
<> 154:37f96f9d4de2 639 .type SPI0_IRQHandler, %function
<> 154:37f96f9d4de2 640 SPI0_IRQHandler:
<> 154:37f96f9d4de2 641 ldr r0,=SPI0_DriverIRQHandler
<> 154:37f96f9d4de2 642 bx r0
<> 154:37f96f9d4de2 643 .size SPI0_IRQHandler, . - SPI0_IRQHandler
<> 154:37f96f9d4de2 644
<> 154:37f96f9d4de2 645 .align 1
<> 154:37f96f9d4de2 646 .thumb_func
<> 154:37f96f9d4de2 647 .weak SPI1_IRQHandler
<> 154:37f96f9d4de2 648 .type SPI1_IRQHandler, %function
<> 154:37f96f9d4de2 649 SPI1_IRQHandler:
<> 154:37f96f9d4de2 650 ldr r0,=SPI1_DriverIRQHandler
<> 154:37f96f9d4de2 651 bx r0
<> 154:37f96f9d4de2 652 .size SPI1_IRQHandler, . - SPI1_IRQHandler
<> 154:37f96f9d4de2 653
<> 154:37f96f9d4de2 654 .align 1
<> 154:37f96f9d4de2 655 .thumb_func
<> 154:37f96f9d4de2 656 .weak I2S0_Tx_IRQHandler
<> 154:37f96f9d4de2 657 .type I2S0_Tx_IRQHandler, %function
<> 154:37f96f9d4de2 658 I2S0_Tx_IRQHandler:
<> 154:37f96f9d4de2 659 ldr r0,=I2S0_Tx_DriverIRQHandler
<> 154:37f96f9d4de2 660 bx r0
<> 154:37f96f9d4de2 661 .size I2S0_Tx_IRQHandler, . - I2S0_Tx_IRQHandler
<> 154:37f96f9d4de2 662
<> 154:37f96f9d4de2 663 .align 1
<> 154:37f96f9d4de2 664 .thumb_func
<> 154:37f96f9d4de2 665 .weak I2S0_Rx_IRQHandler
<> 154:37f96f9d4de2 666 .type I2S0_Rx_IRQHandler, %function
<> 154:37f96f9d4de2 667 I2S0_Rx_IRQHandler:
<> 154:37f96f9d4de2 668 ldr r0,=I2S0_Rx_DriverIRQHandler
<> 154:37f96f9d4de2 669 bx r0
<> 154:37f96f9d4de2 670 .size I2S0_Rx_IRQHandler, . - I2S0_Rx_IRQHandler
<> 154:37f96f9d4de2 671
<> 154:37f96f9d4de2 672 .align 1
<> 154:37f96f9d4de2 673 .thumb_func
<> 154:37f96f9d4de2 674 .weak UART0_LON_IRQHandler
<> 154:37f96f9d4de2 675 .type UART0_LON_IRQHandler, %function
<> 154:37f96f9d4de2 676 UART0_LON_IRQHandler:
<> 154:37f96f9d4de2 677 ldr r0,=UART0_LON_DriverIRQHandler
<> 154:37f96f9d4de2 678 bx r0
<> 154:37f96f9d4de2 679 .size UART0_LON_IRQHandler, . - UART0_LON_IRQHandler
<> 154:37f96f9d4de2 680
<> 154:37f96f9d4de2 681 .align 1
<> 154:37f96f9d4de2 682 .thumb_func
<> 154:37f96f9d4de2 683 .weak UART0_RX_TX_IRQHandler
<> 154:37f96f9d4de2 684 .type UART0_RX_TX_IRQHandler, %function
<> 154:37f96f9d4de2 685 UART0_RX_TX_IRQHandler:
<> 154:37f96f9d4de2 686 ldr r0,=UART0_RX_TX_DriverIRQHandler
<> 154:37f96f9d4de2 687 bx r0
<> 154:37f96f9d4de2 688 .size UART0_RX_TX_IRQHandler, . - UART0_RX_TX_IRQHandler
<> 154:37f96f9d4de2 689
<> 154:37f96f9d4de2 690 .align 1
<> 154:37f96f9d4de2 691 .thumb_func
<> 154:37f96f9d4de2 692 .weak UART0_ERR_IRQHandler
<> 154:37f96f9d4de2 693 .type UART0_ERR_IRQHandler, %function
<> 154:37f96f9d4de2 694 UART0_ERR_IRQHandler:
<> 154:37f96f9d4de2 695 ldr r0,=UART0_ERR_DriverIRQHandler
<> 154:37f96f9d4de2 696 bx r0
<> 154:37f96f9d4de2 697 .size UART0_ERR_IRQHandler, . - UART0_ERR_IRQHandler
<> 154:37f96f9d4de2 698
<> 154:37f96f9d4de2 699 .align 1
<> 154:37f96f9d4de2 700 .thumb_func
<> 154:37f96f9d4de2 701 .weak UART1_RX_TX_IRQHandler
<> 154:37f96f9d4de2 702 .type UART1_RX_TX_IRQHandler, %function
<> 154:37f96f9d4de2 703 UART1_RX_TX_IRQHandler:
<> 154:37f96f9d4de2 704 ldr r0,=UART1_RX_TX_DriverIRQHandler
<> 154:37f96f9d4de2 705 bx r0
<> 154:37f96f9d4de2 706 .size UART1_RX_TX_IRQHandler, . - UART1_RX_TX_IRQHandler
<> 154:37f96f9d4de2 707
<> 154:37f96f9d4de2 708 .align 1
<> 154:37f96f9d4de2 709 .thumb_func
<> 154:37f96f9d4de2 710 .weak UART1_ERR_IRQHandler
<> 154:37f96f9d4de2 711 .type UART1_ERR_IRQHandler, %function
<> 154:37f96f9d4de2 712 UART1_ERR_IRQHandler:
<> 154:37f96f9d4de2 713 ldr r0,=UART1_ERR_DriverIRQHandler
<> 154:37f96f9d4de2 714 bx r0
<> 154:37f96f9d4de2 715 .size UART1_ERR_IRQHandler, . - UART1_ERR_IRQHandler
<> 154:37f96f9d4de2 716
<> 154:37f96f9d4de2 717 .align 1
<> 154:37f96f9d4de2 718 .thumb_func
<> 154:37f96f9d4de2 719 .weak UART2_RX_TX_IRQHandler
<> 154:37f96f9d4de2 720 .type UART2_RX_TX_IRQHandler, %function
<> 154:37f96f9d4de2 721 UART2_RX_TX_IRQHandler:
<> 154:37f96f9d4de2 722 ldr r0,=UART2_RX_TX_DriverIRQHandler
<> 154:37f96f9d4de2 723 bx r0
<> 154:37f96f9d4de2 724 .size UART2_RX_TX_IRQHandler, . - UART2_RX_TX_IRQHandler
<> 154:37f96f9d4de2 725
<> 154:37f96f9d4de2 726 .align 1
<> 154:37f96f9d4de2 727 .thumb_func
<> 154:37f96f9d4de2 728 .weak UART2_ERR_IRQHandler
<> 154:37f96f9d4de2 729 .type UART2_ERR_IRQHandler, %function
<> 154:37f96f9d4de2 730 UART2_ERR_IRQHandler:
<> 154:37f96f9d4de2 731 ldr r0,=UART2_ERR_DriverIRQHandler
<> 154:37f96f9d4de2 732 bx r0
<> 154:37f96f9d4de2 733 .size UART2_ERR_IRQHandler, . - UART2_ERR_IRQHandler
<> 154:37f96f9d4de2 734
<> 154:37f96f9d4de2 735 .align 1
<> 154:37f96f9d4de2 736 .thumb_func
<> 154:37f96f9d4de2 737 .weak UART3_RX_TX_IRQHandler
<> 154:37f96f9d4de2 738 .type UART3_RX_TX_IRQHandler, %function
<> 154:37f96f9d4de2 739 UART3_RX_TX_IRQHandler:
<> 154:37f96f9d4de2 740 ldr r0,=UART3_RX_TX_DriverIRQHandler
<> 154:37f96f9d4de2 741 bx r0
<> 154:37f96f9d4de2 742 .size UART3_RX_TX_IRQHandler, . - UART3_RX_TX_IRQHandler
<> 154:37f96f9d4de2 743
<> 154:37f96f9d4de2 744 .align 1
<> 154:37f96f9d4de2 745 .thumb_func
<> 154:37f96f9d4de2 746 .weak UART3_ERR_IRQHandler
<> 154:37f96f9d4de2 747 .type UART3_ERR_IRQHandler, %function
<> 154:37f96f9d4de2 748 UART3_ERR_IRQHandler:
<> 154:37f96f9d4de2 749 ldr r0,=UART3_ERR_DriverIRQHandler
<> 154:37f96f9d4de2 750 bx r0
<> 154:37f96f9d4de2 751 .size UART3_ERR_IRQHandler, . - UART3_ERR_IRQHandler
<> 154:37f96f9d4de2 752
<> 154:37f96f9d4de2 753 .align 1
<> 154:37f96f9d4de2 754 .thumb_func
<> 154:37f96f9d4de2 755 .weak SPI2_IRQHandler
<> 154:37f96f9d4de2 756 .type SPI2_IRQHandler, %function
<> 154:37f96f9d4de2 757 SPI2_IRQHandler:
<> 154:37f96f9d4de2 758 ldr r0,=SPI2_DriverIRQHandler
<> 154:37f96f9d4de2 759 bx r0
<> 154:37f96f9d4de2 760 .size SPI2_IRQHandler, . - SPI2_IRQHandler
<> 154:37f96f9d4de2 761
<> 154:37f96f9d4de2 762 .align 1
<> 154:37f96f9d4de2 763 .thumb_func
<> 154:37f96f9d4de2 764 .weak UART4_RX_TX_IRQHandler
<> 154:37f96f9d4de2 765 .type UART4_RX_TX_IRQHandler, %function
<> 154:37f96f9d4de2 766 UART4_RX_TX_IRQHandler:
<> 154:37f96f9d4de2 767 ldr r0,=UART4_RX_TX_DriverIRQHandler
<> 154:37f96f9d4de2 768 bx r0
<> 154:37f96f9d4de2 769 .size UART4_RX_TX_IRQHandler, . - UART4_RX_TX_IRQHandler
<> 154:37f96f9d4de2 770
<> 154:37f96f9d4de2 771 .align 1
<> 154:37f96f9d4de2 772 .thumb_func
<> 154:37f96f9d4de2 773 .weak UART4_ERR_IRQHandler
<> 154:37f96f9d4de2 774 .type UART4_ERR_IRQHandler, %function
<> 154:37f96f9d4de2 775 UART4_ERR_IRQHandler:
<> 154:37f96f9d4de2 776 ldr r0,=UART4_ERR_DriverIRQHandler
<> 154:37f96f9d4de2 777 bx r0
<> 154:37f96f9d4de2 778 .size UART4_ERR_IRQHandler, . - UART4_ERR_IRQHandler
<> 154:37f96f9d4de2 779
<> 154:37f96f9d4de2 780 .align 1
<> 154:37f96f9d4de2 781 .thumb_func
<> 154:37f96f9d4de2 782 .weak UART5_RX_TX_IRQHandler
<> 154:37f96f9d4de2 783 .type UART5_RX_TX_IRQHandler, %function
<> 154:37f96f9d4de2 784 UART5_RX_TX_IRQHandler:
<> 154:37f96f9d4de2 785 ldr r0,=UART5_RX_TX_DriverIRQHandler
<> 154:37f96f9d4de2 786 bx r0
<> 154:37f96f9d4de2 787 .size UART5_RX_TX_IRQHandler, . - UART5_RX_TX_IRQHandler
<> 154:37f96f9d4de2 788
<> 154:37f96f9d4de2 789 .align 1
<> 154:37f96f9d4de2 790 .thumb_func
<> 154:37f96f9d4de2 791 .weak UART5_ERR_IRQHandler
<> 154:37f96f9d4de2 792 .type UART5_ERR_IRQHandler, %function
<> 154:37f96f9d4de2 793 UART5_ERR_IRQHandler:
<> 154:37f96f9d4de2 794 ldr r0,=UART5_ERR_DriverIRQHandler
<> 154:37f96f9d4de2 795 bx r0
<> 154:37f96f9d4de2 796 .size UART5_ERR_IRQHandler, . - UART5_ERR_IRQHandler
<> 154:37f96f9d4de2 797
<> 154:37f96f9d4de2 798 .align 1
<> 154:37f96f9d4de2 799 .thumb_func
<> 154:37f96f9d4de2 800 .weak I2C2_IRQHandler
<> 154:37f96f9d4de2 801 .type I2C2_IRQHandler, %function
<> 154:37f96f9d4de2 802 I2C2_IRQHandler:
<> 154:37f96f9d4de2 803 ldr r0,=I2C2_DriverIRQHandler
<> 154:37f96f9d4de2 804 bx r0
<> 154:37f96f9d4de2 805 .size I2C2_IRQHandler, . - I2C2_IRQHandler
<> 154:37f96f9d4de2 806
<> 154:37f96f9d4de2 807 .align 1
<> 154:37f96f9d4de2 808 .thumb_func
<> 154:37f96f9d4de2 809 .weak CAN0_ORed_Message_buffer_IRQHandler
<> 154:37f96f9d4de2 810 .type CAN0_ORed_Message_buffer_IRQHandler, %function
<> 154:37f96f9d4de2 811 CAN0_ORed_Message_buffer_IRQHandler:
<> 154:37f96f9d4de2 812 ldr r0,=CAN0_DriverIRQHandler
<> 154:37f96f9d4de2 813 bx r0
<> 154:37f96f9d4de2 814 .size CAN0_ORed_Message_buffer_IRQHandler, . - CAN0_ORed_Message_buffer_IRQHandler
<> 154:37f96f9d4de2 815
<> 154:37f96f9d4de2 816 .align 1
<> 154:37f96f9d4de2 817 .thumb_func
<> 154:37f96f9d4de2 818 .weak CAN0_Bus_Off_IRQHandler
<> 154:37f96f9d4de2 819 .type CAN0_Bus_Off_IRQHandler, %function
<> 154:37f96f9d4de2 820 CAN0_Bus_Off_IRQHandler:
<> 154:37f96f9d4de2 821 ldr r0,=CAN0_DriverIRQHandler
<> 154:37f96f9d4de2 822 bx r0
<> 154:37f96f9d4de2 823 .size CAN0_Bus_Off_IRQHandler, . - CAN0_Bus_Off_IRQHandler
<> 154:37f96f9d4de2 824
<> 154:37f96f9d4de2 825 .align 1
<> 154:37f96f9d4de2 826 .thumb_func
<> 154:37f96f9d4de2 827 .weak CAN0_Error_IRQHandler
<> 154:37f96f9d4de2 828 .type CAN0_Error_IRQHandler, %function
<> 154:37f96f9d4de2 829 CAN0_Error_IRQHandler:
<> 154:37f96f9d4de2 830 ldr r0,=CAN0_DriverIRQHandler
<> 154:37f96f9d4de2 831 bx r0
<> 154:37f96f9d4de2 832 .size CAN0_Error_IRQHandler, . - CAN0_Error_IRQHandler
<> 154:37f96f9d4de2 833
<> 154:37f96f9d4de2 834 .align 1
<> 154:37f96f9d4de2 835 .thumb_func
<> 154:37f96f9d4de2 836 .weak CAN0_Tx_Warning_IRQHandler
<> 154:37f96f9d4de2 837 .type CAN0_Tx_Warning_IRQHandler, %function
<> 154:37f96f9d4de2 838 CAN0_Tx_Warning_IRQHandler:
<> 154:37f96f9d4de2 839 ldr r0,=CAN0_DriverIRQHandler
<> 154:37f96f9d4de2 840 bx r0
<> 154:37f96f9d4de2 841 .size CAN0_Tx_Warning_IRQHandler, . - CAN0_Tx_Warning_IRQHandler
<> 154:37f96f9d4de2 842
<> 154:37f96f9d4de2 843 .align 1
<> 154:37f96f9d4de2 844 .thumb_func
<> 154:37f96f9d4de2 845 .weak CAN0_Rx_Warning_IRQHandler
<> 154:37f96f9d4de2 846 .type CAN0_Rx_Warning_IRQHandler, %function
<> 154:37f96f9d4de2 847 CAN0_Rx_Warning_IRQHandler:
<> 154:37f96f9d4de2 848 ldr r0,=CAN0_DriverIRQHandler
<> 154:37f96f9d4de2 849 bx r0
<> 154:37f96f9d4de2 850 .size CAN0_Rx_Warning_IRQHandler, . - CAN0_Rx_Warning_IRQHandler
<> 154:37f96f9d4de2 851
<> 154:37f96f9d4de2 852 .align 1
<> 154:37f96f9d4de2 853 .thumb_func
<> 154:37f96f9d4de2 854 .weak CAN0_Wake_Up_IRQHandler
<> 154:37f96f9d4de2 855 .type CAN0_Wake_Up_IRQHandler, %function
<> 154:37f96f9d4de2 856 CAN0_Wake_Up_IRQHandler:
<> 154:37f96f9d4de2 857 ldr r0,=CAN0_DriverIRQHandler
<> 154:37f96f9d4de2 858 bx r0
<> 154:37f96f9d4de2 859 .size CAN0_Wake_Up_IRQHandler, . - CAN0_Wake_Up_IRQHandler
<> 154:37f96f9d4de2 860
<> 154:37f96f9d4de2 861 .align 1
<> 154:37f96f9d4de2 862 .thumb_func
<> 154:37f96f9d4de2 863 .weak SDHC_IRQHandler
<> 154:37f96f9d4de2 864 .type SDHC_IRQHandler, %function
<> 154:37f96f9d4de2 865 SDHC_IRQHandler:
<> 154:37f96f9d4de2 866 ldr r0,=SDHC_DriverIRQHandler
<> 154:37f96f9d4de2 867 bx r0
<> 154:37f96f9d4de2 868 .size SDHC_IRQHandler, . - SDHC_IRQHandler
<> 154:37f96f9d4de2 869
<> 154:37f96f9d4de2 870 .align 1
<> 154:37f96f9d4de2 871 .thumb_func
<> 154:37f96f9d4de2 872 .weak ENET_1588_Timer_IRQHandler
<> 154:37f96f9d4de2 873 .type ENET_1588_Timer_IRQHandler, %function
<> 154:37f96f9d4de2 874 ENET_1588_Timer_IRQHandler:
<> 154:37f96f9d4de2 875 ldr r0,=ENET_1588_Timer_DriverIRQHandler
<> 154:37f96f9d4de2 876 bx r0
<> 154:37f96f9d4de2 877 .size ENET_1588_Timer_IRQHandler, . - ENET_1588_Timer_IRQHandler
<> 154:37f96f9d4de2 878
<> 154:37f96f9d4de2 879 .align 1
<> 154:37f96f9d4de2 880 .thumb_func
<> 154:37f96f9d4de2 881 .weak ENET_Transmit_IRQHandler
<> 154:37f96f9d4de2 882 .type ENET_Transmit_IRQHandler, %function
<> 154:37f96f9d4de2 883 ENET_Transmit_IRQHandler:
<> 154:37f96f9d4de2 884 ldr r0,=ENET_Transmit_DriverIRQHandler
<> 154:37f96f9d4de2 885 bx r0
<> 154:37f96f9d4de2 886 .size ENET_Transmit_IRQHandler, . - ENET_Transmit_IRQHandler
<> 154:37f96f9d4de2 887
<> 154:37f96f9d4de2 888 .align 1
<> 154:37f96f9d4de2 889 .thumb_func
<> 154:37f96f9d4de2 890 .weak ENET_Receive_IRQHandler
<> 154:37f96f9d4de2 891 .type ENET_Receive_IRQHandler, %function
<> 154:37f96f9d4de2 892 ENET_Receive_IRQHandler:
<> 154:37f96f9d4de2 893 ldr r0,=ENET_Receive_DriverIRQHandler
<> 154:37f96f9d4de2 894 bx r0
<> 154:37f96f9d4de2 895 .size ENET_Receive_IRQHandler, . - ENET_Receive_IRQHandler
<> 154:37f96f9d4de2 896
<> 154:37f96f9d4de2 897 .align 1
<> 154:37f96f9d4de2 898 .thumb_func
<> 154:37f96f9d4de2 899 .weak ENET_Error_IRQHandler
<> 154:37f96f9d4de2 900 .type ENET_Error_IRQHandler, %function
<> 154:37f96f9d4de2 901 ENET_Error_IRQHandler:
<> 154:37f96f9d4de2 902 ldr r0,=ENET_Error_DriverIRQHandler
<> 154:37f96f9d4de2 903 bx r0
<> 154:37f96f9d4de2 904 .size ENET_Error_IRQHandler, . - ENET_Error_IRQHandler
<> 154:37f96f9d4de2 905
<> 154:37f96f9d4de2 906
<> 154:37f96f9d4de2 907 /* Macro to define default handlers. Default handler
<> 154:37f96f9d4de2 908 * will be weak symbol and just dead loops. They can be
<> 154:37f96f9d4de2 909 * overwritten by other handlers */
<> 154:37f96f9d4de2 910 .macro def_irq_handler handler_name
<> 154:37f96f9d4de2 911 .weak \handler_name
<> 154:37f96f9d4de2 912 .set \handler_name, DefaultISR
<> 154:37f96f9d4de2 913 .endm
<> 154:37f96f9d4de2 914
<> 154:37f96f9d4de2 915 /* Exception Handlers */
<> 154:37f96f9d4de2 916 def_irq_handler MemManage_Handler
<> 154:37f96f9d4de2 917 def_irq_handler BusFault_Handler
<> 154:37f96f9d4de2 918 def_irq_handler UsageFault_Handler
<> 154:37f96f9d4de2 919 def_irq_handler DebugMon_Handler
<> 154:37f96f9d4de2 920 def_irq_handler DMA0_DriverIRQHandler
<> 154:37f96f9d4de2 921 def_irq_handler DMA1_DriverIRQHandler
<> 154:37f96f9d4de2 922 def_irq_handler DMA2_DriverIRQHandler
<> 154:37f96f9d4de2 923 def_irq_handler DMA3_DriverIRQHandler
<> 154:37f96f9d4de2 924 def_irq_handler DMA4_DriverIRQHandler
<> 154:37f96f9d4de2 925 def_irq_handler DMA5_DriverIRQHandler
<> 154:37f96f9d4de2 926 def_irq_handler DMA6_DriverIRQHandler
<> 154:37f96f9d4de2 927 def_irq_handler DMA7_DriverIRQHandler
<> 154:37f96f9d4de2 928 def_irq_handler DMA8_DriverIRQHandler
<> 154:37f96f9d4de2 929 def_irq_handler DMA9_DriverIRQHandler
<> 154:37f96f9d4de2 930 def_irq_handler DMA10_DriverIRQHandler
<> 154:37f96f9d4de2 931 def_irq_handler DMA11_DriverIRQHandler
<> 154:37f96f9d4de2 932 def_irq_handler DMA12_DriverIRQHandler
<> 154:37f96f9d4de2 933 def_irq_handler DMA13_DriverIRQHandler
<> 154:37f96f9d4de2 934 def_irq_handler DMA14_DriverIRQHandler
<> 154:37f96f9d4de2 935 def_irq_handler DMA15_DriverIRQHandler
<> 154:37f96f9d4de2 936 def_irq_handler DMA_Error_DriverIRQHandler
<> 154:37f96f9d4de2 937 def_irq_handler MCM_IRQHandler
<> 154:37f96f9d4de2 938 def_irq_handler FTFE_IRQHandler
<> 154:37f96f9d4de2 939 def_irq_handler Read_Collision_IRQHandler
<> 154:37f96f9d4de2 940 def_irq_handler LVD_LVW_IRQHandler
<> 154:37f96f9d4de2 941 def_irq_handler LLWU_IRQHandler
<> 154:37f96f9d4de2 942 def_irq_handler WDOG_EWM_IRQHandler
<> 154:37f96f9d4de2 943 def_irq_handler RNG_IRQHandler
<> 154:37f96f9d4de2 944 def_irq_handler I2C0_DriverIRQHandler
<> 154:37f96f9d4de2 945 def_irq_handler I2C1_DriverIRQHandler
<> 154:37f96f9d4de2 946 def_irq_handler SPI0_DriverIRQHandler
<> 154:37f96f9d4de2 947 def_irq_handler SPI1_DriverIRQHandler
<> 154:37f96f9d4de2 948 def_irq_handler I2S0_Tx_DriverIRQHandler
<> 154:37f96f9d4de2 949 def_irq_handler I2S0_Rx_DriverIRQHandler
<> 154:37f96f9d4de2 950 def_irq_handler UART0_LON_DriverIRQHandler
<> 154:37f96f9d4de2 951 def_irq_handler UART0_RX_TX_DriverIRQHandler
<> 154:37f96f9d4de2 952 def_irq_handler UART0_ERR_DriverIRQHandler
<> 154:37f96f9d4de2 953 def_irq_handler UART1_RX_TX_DriverIRQHandler
<> 154:37f96f9d4de2 954 def_irq_handler UART1_ERR_DriverIRQHandler
<> 154:37f96f9d4de2 955 def_irq_handler UART2_RX_TX_DriverIRQHandler
<> 154:37f96f9d4de2 956 def_irq_handler UART2_ERR_DriverIRQHandler
<> 154:37f96f9d4de2 957 def_irq_handler UART3_RX_TX_DriverIRQHandler
<> 154:37f96f9d4de2 958 def_irq_handler UART3_ERR_DriverIRQHandler
<> 154:37f96f9d4de2 959 def_irq_handler ADC0_IRQHandler
<> 154:37f96f9d4de2 960 def_irq_handler CMP0_IRQHandler
<> 154:37f96f9d4de2 961 def_irq_handler CMP1_IRQHandler
<> 154:37f96f9d4de2 962 def_irq_handler FTM0_IRQHandler
<> 154:37f96f9d4de2 963 def_irq_handler FTM1_IRQHandler
<> 154:37f96f9d4de2 964 def_irq_handler FTM2_IRQHandler
<> 154:37f96f9d4de2 965 def_irq_handler CMT_IRQHandler
<> 154:37f96f9d4de2 966 def_irq_handler RTC_IRQHandler
<> 154:37f96f9d4de2 967 def_irq_handler RTC_Seconds_IRQHandler
<> 154:37f96f9d4de2 968 def_irq_handler PIT0_IRQHandler
<> 154:37f96f9d4de2 969 def_irq_handler PIT1_IRQHandler
<> 154:37f96f9d4de2 970 def_irq_handler PIT2_IRQHandler
<> 154:37f96f9d4de2 971 def_irq_handler PIT3_IRQHandler
<> 154:37f96f9d4de2 972 def_irq_handler PDB0_IRQHandler
<> 154:37f96f9d4de2 973 def_irq_handler USB0_IRQHandler
<> 154:37f96f9d4de2 974 def_irq_handler USBDCD_IRQHandler
<> 154:37f96f9d4de2 975 def_irq_handler Reserved71_IRQHandler
<> 154:37f96f9d4de2 976 def_irq_handler DAC0_IRQHandler
<> 154:37f96f9d4de2 977 def_irq_handler MCG_IRQHandler
<> 154:37f96f9d4de2 978 def_irq_handler LPTMR0_IRQHandler
<> 154:37f96f9d4de2 979 def_irq_handler PORTA_IRQHandler
<> 154:37f96f9d4de2 980 def_irq_handler PORTB_IRQHandler
<> 154:37f96f9d4de2 981 def_irq_handler PORTC_IRQHandler
<> 154:37f96f9d4de2 982 def_irq_handler PORTD_IRQHandler
<> 154:37f96f9d4de2 983 def_irq_handler PORTE_IRQHandler
<> 154:37f96f9d4de2 984 def_irq_handler SWI_IRQHandler
<> 154:37f96f9d4de2 985 def_irq_handler SPI2_DriverIRQHandler
<> 154:37f96f9d4de2 986 def_irq_handler UART4_RX_TX_DriverIRQHandler
<> 154:37f96f9d4de2 987 def_irq_handler UART4_ERR_DriverIRQHandler
<> 154:37f96f9d4de2 988 def_irq_handler UART5_RX_TX_DriverIRQHandler
<> 154:37f96f9d4de2 989 def_irq_handler UART5_ERR_DriverIRQHandler
<> 154:37f96f9d4de2 990 def_irq_handler CMP2_IRQHandler
<> 154:37f96f9d4de2 991 def_irq_handler FTM3_IRQHandler
<> 154:37f96f9d4de2 992 def_irq_handler DAC1_IRQHandler
<> 154:37f96f9d4de2 993 def_irq_handler ADC1_IRQHandler
<> 154:37f96f9d4de2 994 def_irq_handler I2C2_DriverIRQHandler
<> 154:37f96f9d4de2 995 def_irq_handler CAN0_DriverIRQHandler
<> 154:37f96f9d4de2 996 def_irq_handler SDHC_DriverIRQHandler
<> 154:37f96f9d4de2 997 def_irq_handler ENET_1588_Timer_DriverIRQHandler
<> 154:37f96f9d4de2 998 def_irq_handler ENET_Transmit_DriverIRQHandler
<> 154:37f96f9d4de2 999 def_irq_handler ENET_Receive_DriverIRQHandler
<> 154:37f96f9d4de2 1000 def_irq_handler ENET_Error_DriverIRQHandler
<> 154:37f96f9d4de2 1001
<> 154:37f96f9d4de2 1002 .end