raspiezo / mbed-dev

hal_tick.h changed for the L432KC target in TARGET/../device/ in order to reassign the system ticker from TIM2 to TIM7, since TIM2 was needed as a 32bit encoder counter.

Dependents:   Nucleo_L432KC_Quadrature_Decoder_with_ADC_and_DAC

Fork of mbed-dev by mbed official

cmsis/core_cmSimd.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/core_cmSimd.h@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file core_cmSimd.h
<> 144:ef7eb2e8f9f7 3 * @brief CMSIS Cortex-M SIMD Header File
<> 144:ef7eb2e8f9f7 4 * @version V4.10
<> 144:ef7eb2e8f9f7 5 * @date 18. March 2015
<> 144:ef7eb2e8f9f7 6 *
<> 144:ef7eb2e8f9f7 7 * @note
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 ******************************************************************************/
<> 144:ef7eb2e8f9f7 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
<> 144:ef7eb2e8f9f7 11
<> 144:ef7eb2e8f9f7 12 All rights reserved.
<> 144:ef7eb2e8f9f7 13 Redistribution and use in source and binary forms, with or without
<> 144:ef7eb2e8f9f7 14 modification, are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 - Redistributions of source code must retain the above copyright
<> 144:ef7eb2e8f9f7 16 notice, this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 - Redistributions in binary form must reproduce the above copyright
<> 144:ef7eb2e8f9f7 18 notice, this list of conditions and the following disclaimer in the
<> 144:ef7eb2e8f9f7 19 documentation and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 - Neither the name of ARM nor the names of its contributors may be used
<> 144:ef7eb2e8f9f7 21 to endorse or promote products derived from this software without
<> 144:ef7eb2e8f9f7 22 specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
<> 144:ef7eb2e8f9f7 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
<> 144:ef7eb2e8f9f7 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
<> 144:ef7eb2e8f9f7 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
<> 144:ef7eb2e8f9f7 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
<> 144:ef7eb2e8f9f7 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
<> 144:ef7eb2e8f9f7 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
<> 144:ef7eb2e8f9f7 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
<> 144:ef7eb2e8f9f7 34 POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 35 ---------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 #if defined ( __ICCARM__ )
<> 144:ef7eb2e8f9f7 39 #pragma system_include /* treat file as system include file for MISRA check */
<> 144:ef7eb2e8f9f7 40 #endif
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifndef __CORE_CMSIMD_H
<> 144:ef7eb2e8f9f7 43 #define __CORE_CMSIMD_H
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 46 extern "C" {
<> 144:ef7eb2e8f9f7 47 #endif
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /*******************************************************************************
<> 144:ef7eb2e8f9f7 51 * Hardware Abstraction Layer
<> 144:ef7eb2e8f9f7 52 ******************************************************************************/
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /* ################### Compiler specific Intrinsics ########################### */
<> 144:ef7eb2e8f9f7 56 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
<> 144:ef7eb2e8f9f7 57 Access to dedicated SIMD instructions
<> 144:ef7eb2e8f9f7 58 @{
<> 144:ef7eb2e8f9f7 59 */
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
<> 144:ef7eb2e8f9f7 62 /* ARM armcc specific functions */
<> 144:ef7eb2e8f9f7 63 #define __SADD8 __sadd8
<> 144:ef7eb2e8f9f7 64 #define __QADD8 __qadd8
<> 144:ef7eb2e8f9f7 65 #define __SHADD8 __shadd8
<> 144:ef7eb2e8f9f7 66 #define __UADD8 __uadd8
<> 144:ef7eb2e8f9f7 67 #define __UQADD8 __uqadd8
<> 144:ef7eb2e8f9f7 68 #define __UHADD8 __uhadd8
<> 144:ef7eb2e8f9f7 69 #define __SSUB8 __ssub8
<> 144:ef7eb2e8f9f7 70 #define __QSUB8 __qsub8
<> 144:ef7eb2e8f9f7 71 #define __SHSUB8 __shsub8
<> 144:ef7eb2e8f9f7 72 #define __USUB8 __usub8
<> 144:ef7eb2e8f9f7 73 #define __UQSUB8 __uqsub8
<> 144:ef7eb2e8f9f7 74 #define __UHSUB8 __uhsub8
<> 144:ef7eb2e8f9f7 75 #define __SADD16 __sadd16
<> 144:ef7eb2e8f9f7 76 #define __QADD16 __qadd16
<> 144:ef7eb2e8f9f7 77 #define __SHADD16 __shadd16
<> 144:ef7eb2e8f9f7 78 #define __UADD16 __uadd16
<> 144:ef7eb2e8f9f7 79 #define __UQADD16 __uqadd16
<> 144:ef7eb2e8f9f7 80 #define __UHADD16 __uhadd16
<> 144:ef7eb2e8f9f7 81 #define __SSUB16 __ssub16
<> 144:ef7eb2e8f9f7 82 #define __QSUB16 __qsub16
<> 144:ef7eb2e8f9f7 83 #define __SHSUB16 __shsub16
<> 144:ef7eb2e8f9f7 84 #define __USUB16 __usub16
<> 144:ef7eb2e8f9f7 85 #define __UQSUB16 __uqsub16
<> 144:ef7eb2e8f9f7 86 #define __UHSUB16 __uhsub16
<> 144:ef7eb2e8f9f7 87 #define __SASX __sasx
<> 144:ef7eb2e8f9f7 88 #define __QASX __qasx
<> 144:ef7eb2e8f9f7 89 #define __SHASX __shasx
<> 144:ef7eb2e8f9f7 90 #define __UASX __uasx
<> 144:ef7eb2e8f9f7 91 #define __UQASX __uqasx
<> 144:ef7eb2e8f9f7 92 #define __UHASX __uhasx
<> 144:ef7eb2e8f9f7 93 #define __SSAX __ssax
<> 144:ef7eb2e8f9f7 94 #define __QSAX __qsax
<> 144:ef7eb2e8f9f7 95 #define __SHSAX __shsax
<> 144:ef7eb2e8f9f7 96 #define __USAX __usax
<> 144:ef7eb2e8f9f7 97 #define __UQSAX __uqsax
<> 144:ef7eb2e8f9f7 98 #define __UHSAX __uhsax
<> 144:ef7eb2e8f9f7 99 #define __USAD8 __usad8
<> 144:ef7eb2e8f9f7 100 #define __USADA8 __usada8
<> 144:ef7eb2e8f9f7 101 #define __SSAT16 __ssat16
<> 144:ef7eb2e8f9f7 102 #define __USAT16 __usat16
<> 144:ef7eb2e8f9f7 103 #define __UXTB16 __uxtb16
<> 144:ef7eb2e8f9f7 104 #define __UXTAB16 __uxtab16
<> 144:ef7eb2e8f9f7 105 #define __SXTB16 __sxtb16
<> 144:ef7eb2e8f9f7 106 #define __SXTAB16 __sxtab16
<> 144:ef7eb2e8f9f7 107 #define __SMUAD __smuad
<> 144:ef7eb2e8f9f7 108 #define __SMUADX __smuadx
<> 144:ef7eb2e8f9f7 109 #define __SMLAD __smlad
<> 144:ef7eb2e8f9f7 110 #define __SMLADX __smladx
<> 144:ef7eb2e8f9f7 111 #define __SMLALD __smlald
<> 144:ef7eb2e8f9f7 112 #define __SMLALDX __smlaldx
<> 144:ef7eb2e8f9f7 113 #define __SMUSD __smusd
<> 144:ef7eb2e8f9f7 114 #define __SMUSDX __smusdx
<> 144:ef7eb2e8f9f7 115 #define __SMLSD __smlsd
<> 144:ef7eb2e8f9f7 116 #define __SMLSDX __smlsdx
<> 144:ef7eb2e8f9f7 117 #define __SMLSLD __smlsld
<> 144:ef7eb2e8f9f7 118 #define __SMLSLDX __smlsldx
<> 144:ef7eb2e8f9f7 119 #define __SEL __sel
<> 144:ef7eb2e8f9f7 120 #define __QADD __qadd
<> 144:ef7eb2e8f9f7 121 #define __QSUB __qsub
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
<> 144:ef7eb2e8f9f7 124 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
<> 144:ef7eb2e8f9f7 127 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
<> 144:ef7eb2e8f9f7 130 ((int64_t)(ARG3) << 32) ) >> 32))
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
<> 144:ef7eb2e8f9f7 134 /* GNU gcc specific functions */
<> 144:ef7eb2e8f9f7 135 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 136 {
<> 144:ef7eb2e8f9f7 137 uint32_t result;
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 140 return(result);
<> 144:ef7eb2e8f9f7 141 }
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 144 {
<> 144:ef7eb2e8f9f7 145 uint32_t result;
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 148 return(result);
<> 144:ef7eb2e8f9f7 149 }
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 152 {
<> 144:ef7eb2e8f9f7 153 uint32_t result;
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 156 return(result);
<> 144:ef7eb2e8f9f7 157 }
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 160 {
<> 144:ef7eb2e8f9f7 161 uint32_t result;
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 164 return(result);
<> 144:ef7eb2e8f9f7 165 }
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 168 {
<> 144:ef7eb2e8f9f7 169 uint32_t result;
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 172 return(result);
<> 144:ef7eb2e8f9f7 173 }
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 176 {
<> 144:ef7eb2e8f9f7 177 uint32_t result;
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 180 return(result);
<> 144:ef7eb2e8f9f7 181 }
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 185 {
<> 144:ef7eb2e8f9f7 186 uint32_t result;
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 189 return(result);
<> 144:ef7eb2e8f9f7 190 }
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 193 {
<> 144:ef7eb2e8f9f7 194 uint32_t result;
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 197 return(result);
<> 144:ef7eb2e8f9f7 198 }
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 201 {
<> 144:ef7eb2e8f9f7 202 uint32_t result;
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 205 return(result);
<> 144:ef7eb2e8f9f7 206 }
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 209 {
<> 144:ef7eb2e8f9f7 210 uint32_t result;
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 213 return(result);
<> 144:ef7eb2e8f9f7 214 }
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 217 {
<> 144:ef7eb2e8f9f7 218 uint32_t result;
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 221 return(result);
<> 144:ef7eb2e8f9f7 222 }
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 225 {
<> 144:ef7eb2e8f9f7 226 uint32_t result;
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 229 return(result);
<> 144:ef7eb2e8f9f7 230 }
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 234 {
<> 144:ef7eb2e8f9f7 235 uint32_t result;
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 238 return(result);
<> 144:ef7eb2e8f9f7 239 }
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 242 {
<> 144:ef7eb2e8f9f7 243 uint32_t result;
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 246 return(result);
<> 144:ef7eb2e8f9f7 247 }
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 250 {
<> 144:ef7eb2e8f9f7 251 uint32_t result;
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 254 return(result);
<> 144:ef7eb2e8f9f7 255 }
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 258 {
<> 144:ef7eb2e8f9f7 259 uint32_t result;
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 262 return(result);
<> 144:ef7eb2e8f9f7 263 }
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 266 {
<> 144:ef7eb2e8f9f7 267 uint32_t result;
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 270 return(result);
<> 144:ef7eb2e8f9f7 271 }
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 274 {
<> 144:ef7eb2e8f9f7 275 uint32_t result;
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 278 return(result);
<> 144:ef7eb2e8f9f7 279 }
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 282 {
<> 144:ef7eb2e8f9f7 283 uint32_t result;
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 286 return(result);
<> 144:ef7eb2e8f9f7 287 }
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 290 {
<> 144:ef7eb2e8f9f7 291 uint32_t result;
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 294 return(result);
<> 144:ef7eb2e8f9f7 295 }
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 298 {
<> 144:ef7eb2e8f9f7 299 uint32_t result;
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 302 return(result);
<> 144:ef7eb2e8f9f7 303 }
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 306 {
<> 144:ef7eb2e8f9f7 307 uint32_t result;
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 310 return(result);
<> 144:ef7eb2e8f9f7 311 }
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 314 {
<> 144:ef7eb2e8f9f7 315 uint32_t result;
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 318 return(result);
<> 144:ef7eb2e8f9f7 319 }
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 322 {
<> 144:ef7eb2e8f9f7 323 uint32_t result;
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 326 return(result);
<> 144:ef7eb2e8f9f7 327 }
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 330 {
<> 144:ef7eb2e8f9f7 331 uint32_t result;
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 334 return(result);
<> 144:ef7eb2e8f9f7 335 }
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 338 {
<> 144:ef7eb2e8f9f7 339 uint32_t result;
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 342 return(result);
<> 144:ef7eb2e8f9f7 343 }
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 346 {
<> 144:ef7eb2e8f9f7 347 uint32_t result;
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 350 return(result);
<> 144:ef7eb2e8f9f7 351 }
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 354 {
<> 144:ef7eb2e8f9f7 355 uint32_t result;
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 358 return(result);
<> 144:ef7eb2e8f9f7 359 }
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 362 {
<> 144:ef7eb2e8f9f7 363 uint32_t result;
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 366 return(result);
<> 144:ef7eb2e8f9f7 367 }
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 370 {
<> 144:ef7eb2e8f9f7 371 uint32_t result;
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 374 return(result);
<> 144:ef7eb2e8f9f7 375 }
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 378 {
<> 144:ef7eb2e8f9f7 379 uint32_t result;
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 382 return(result);
<> 144:ef7eb2e8f9f7 383 }
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 386 {
<> 144:ef7eb2e8f9f7 387 uint32_t result;
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 390 return(result);
<> 144:ef7eb2e8f9f7 391 }
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 394 {
<> 144:ef7eb2e8f9f7 395 uint32_t result;
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 398 return(result);
<> 144:ef7eb2e8f9f7 399 }
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 402 {
<> 144:ef7eb2e8f9f7 403 uint32_t result;
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 406 return(result);
<> 144:ef7eb2e8f9f7 407 }
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 410 {
<> 144:ef7eb2e8f9f7 411 uint32_t result;
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 414 return(result);
<> 144:ef7eb2e8f9f7 415 }
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 418 {
<> 144:ef7eb2e8f9f7 419 uint32_t result;
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 422 return(result);
<> 144:ef7eb2e8f9f7 423 }
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 426 {
<> 144:ef7eb2e8f9f7 427 uint32_t result;
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 430 return(result);
<> 144:ef7eb2e8f9f7 431 }
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
<> 144:ef7eb2e8f9f7 434 {
<> 144:ef7eb2e8f9f7 435 uint32_t result;
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 144:ef7eb2e8f9f7 438 return(result);
<> 144:ef7eb2e8f9f7 439 }
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 #define __SSAT16(ARG1,ARG2) \
<> 144:ef7eb2e8f9f7 442 ({ \
<> 144:ef7eb2e8f9f7 443 uint32_t __RES, __ARG1 = (ARG1); \
<> 144:ef7eb2e8f9f7 444 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
<> 144:ef7eb2e8f9f7 445 __RES; \
<> 144:ef7eb2e8f9f7 446 })
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 #define __USAT16(ARG1,ARG2) \
<> 144:ef7eb2e8f9f7 449 ({ \
<> 144:ef7eb2e8f9f7 450 uint32_t __RES, __ARG1 = (ARG1); \
<> 144:ef7eb2e8f9f7 451 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
<> 144:ef7eb2e8f9f7 452 __RES; \
<> 144:ef7eb2e8f9f7 453 })
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
<> 144:ef7eb2e8f9f7 456 {
<> 144:ef7eb2e8f9f7 457 uint32_t result;
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
<> 144:ef7eb2e8f9f7 460 return(result);
<> 144:ef7eb2e8f9f7 461 }
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 464 {
<> 144:ef7eb2e8f9f7 465 uint32_t result;
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 468 return(result);
<> 144:ef7eb2e8f9f7 469 }
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
<> 144:ef7eb2e8f9f7 472 {
<> 144:ef7eb2e8f9f7 473 uint32_t result;
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
<> 144:ef7eb2e8f9f7 476 return(result);
<> 144:ef7eb2e8f9f7 477 }
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 480 {
<> 144:ef7eb2e8f9f7 481 uint32_t result;
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 484 return(result);
<> 144:ef7eb2e8f9f7 485 }
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 488 {
<> 144:ef7eb2e8f9f7 489 uint32_t result;
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 492 return(result);
<> 144:ef7eb2e8f9f7 493 }
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 496 {
<> 144:ef7eb2e8f9f7 497 uint32_t result;
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 500 return(result);
<> 144:ef7eb2e8f9f7 501 }
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
<> 144:ef7eb2e8f9f7 504 {
<> 144:ef7eb2e8f9f7 505 uint32_t result;
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 144:ef7eb2e8f9f7 508 return(result);
<> 144:ef7eb2e8f9f7 509 }
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
<> 144:ef7eb2e8f9f7 512 {
<> 144:ef7eb2e8f9f7 513 uint32_t result;
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 144:ef7eb2e8f9f7 516 return(result);
<> 144:ef7eb2e8f9f7 517 }
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
<> 144:ef7eb2e8f9f7 520 {
<> 144:ef7eb2e8f9f7 521 union llreg_u{
<> 144:ef7eb2e8f9f7 522 uint32_t w32[2];
<> 144:ef7eb2e8f9f7 523 uint64_t w64;
<> 144:ef7eb2e8f9f7 524 } llr;
<> 144:ef7eb2e8f9f7 525 llr.w64 = acc;
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 #ifndef __ARMEB__ // Little endian
<> 144:ef7eb2e8f9f7 528 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
<> 144:ef7eb2e8f9f7 529 #else // Big endian
<> 144:ef7eb2e8f9f7 530 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
<> 144:ef7eb2e8f9f7 531 #endif
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 return(llr.w64);
<> 144:ef7eb2e8f9f7 534 }
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
<> 144:ef7eb2e8f9f7 537 {
<> 144:ef7eb2e8f9f7 538 union llreg_u{
<> 144:ef7eb2e8f9f7 539 uint32_t w32[2];
<> 144:ef7eb2e8f9f7 540 uint64_t w64;
<> 144:ef7eb2e8f9f7 541 } llr;
<> 144:ef7eb2e8f9f7 542 llr.w64 = acc;
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 #ifndef __ARMEB__ // Little endian
<> 144:ef7eb2e8f9f7 545 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
<> 144:ef7eb2e8f9f7 546 #else // Big endian
<> 144:ef7eb2e8f9f7 547 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
<> 144:ef7eb2e8f9f7 548 #endif
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 return(llr.w64);
<> 144:ef7eb2e8f9f7 551 }
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 554 {
<> 144:ef7eb2e8f9f7 555 uint32_t result;
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 558 return(result);
<> 144:ef7eb2e8f9f7 559 }
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 562 {
<> 144:ef7eb2e8f9f7 563 uint32_t result;
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 566 return(result);
<> 144:ef7eb2e8f9f7 567 }
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
<> 144:ef7eb2e8f9f7 570 {
<> 144:ef7eb2e8f9f7 571 uint32_t result;
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 144:ef7eb2e8f9f7 574 return(result);
<> 144:ef7eb2e8f9f7 575 }
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
<> 144:ef7eb2e8f9f7 578 {
<> 144:ef7eb2e8f9f7 579 uint32_t result;
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
<> 144:ef7eb2e8f9f7 582 return(result);
<> 144:ef7eb2e8f9f7 583 }
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
<> 144:ef7eb2e8f9f7 586 {
<> 144:ef7eb2e8f9f7 587 union llreg_u{
<> 144:ef7eb2e8f9f7 588 uint32_t w32[2];
<> 144:ef7eb2e8f9f7 589 uint64_t w64;
<> 144:ef7eb2e8f9f7 590 } llr;
<> 144:ef7eb2e8f9f7 591 llr.w64 = acc;
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593 #ifndef __ARMEB__ // Little endian
<> 144:ef7eb2e8f9f7 594 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
<> 144:ef7eb2e8f9f7 595 #else // Big endian
<> 144:ef7eb2e8f9f7 596 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
<> 144:ef7eb2e8f9f7 597 #endif
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599 return(llr.w64);
<> 144:ef7eb2e8f9f7 600 }
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
<> 144:ef7eb2e8f9f7 603 {
<> 144:ef7eb2e8f9f7 604 union llreg_u{
<> 144:ef7eb2e8f9f7 605 uint32_t w32[2];
<> 144:ef7eb2e8f9f7 606 uint64_t w64;
<> 144:ef7eb2e8f9f7 607 } llr;
<> 144:ef7eb2e8f9f7 608 llr.w64 = acc;
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 #ifndef __ARMEB__ // Little endian
<> 144:ef7eb2e8f9f7 611 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
<> 144:ef7eb2e8f9f7 612 #else // Big endian
<> 144:ef7eb2e8f9f7 613 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
<> 144:ef7eb2e8f9f7 614 #endif
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 return(llr.w64);
<> 144:ef7eb2e8f9f7 617 }
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 620 {
<> 144:ef7eb2e8f9f7 621 uint32_t result;
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 624 return(result);
<> 144:ef7eb2e8f9f7 625 }
<> 144:ef7eb2e8f9f7 626
<> 144:ef7eb2e8f9f7 627 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 628 {
<> 144:ef7eb2e8f9f7 629 uint32_t result;
<> 144:ef7eb2e8f9f7 630
<> 144:ef7eb2e8f9f7 631 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 632 return(result);
<> 144:ef7eb2e8f9f7 633 }
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
<> 144:ef7eb2e8f9f7 636 {
<> 144:ef7eb2e8f9f7 637 uint32_t result;
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
<> 144:ef7eb2e8f9f7 640 return(result);
<> 144:ef7eb2e8f9f7 641 }
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 #define __PKHBT(ARG1,ARG2,ARG3) \
<> 144:ef7eb2e8f9f7 644 ({ \
<> 144:ef7eb2e8f9f7 645 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
<> 144:ef7eb2e8f9f7 646 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
<> 144:ef7eb2e8f9f7 647 __RES; \
<> 144:ef7eb2e8f9f7 648 })
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650 #define __PKHTB(ARG1,ARG2,ARG3) \
<> 144:ef7eb2e8f9f7 651 ({ \
<> 144:ef7eb2e8f9f7 652 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
<> 144:ef7eb2e8f9f7 653 if (ARG3 == 0) \
<> 144:ef7eb2e8f9f7 654 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
<> 144:ef7eb2e8f9f7 655 else \
<> 144:ef7eb2e8f9f7 656 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
<> 144:ef7eb2e8f9f7 657 __RES; \
<> 144:ef7eb2e8f9f7 658 })
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
<> 144:ef7eb2e8f9f7 661 {
<> 144:ef7eb2e8f9f7 662 int32_t result;
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
<> 144:ef7eb2e8f9f7 665 return(result);
<> 144:ef7eb2e8f9f7 666 }
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
<> 144:ef7eb2e8f9f7 670 /* IAR iccarm specific functions */
<> 144:ef7eb2e8f9f7 671 #include <cmsis_iar.h>
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
<> 144:ef7eb2e8f9f7 675 /* TI CCS specific functions */
<> 144:ef7eb2e8f9f7 676 #include <cmsis_ccs.h>
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
<> 144:ef7eb2e8f9f7 680 /* TASKING carm specific functions */
<> 144:ef7eb2e8f9f7 681 /* not yet supported */
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
<> 144:ef7eb2e8f9f7 685 /* Cosmic specific functions */
<> 144:ef7eb2e8f9f7 686 #include <cmsis_csm.h>
<> 144:ef7eb2e8f9f7 687
<> 144:ef7eb2e8f9f7 688 #endif
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 /*@} end of group CMSIS_SIMD_intrinsics */
<> 144:ef7eb2e8f9f7 691
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 694 }
<> 144:ef7eb2e8f9f7 695 #endif
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 #endif /* __CORE_CMSIMD_H */