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targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/efm32zg_dma.h@1:f30bdcd2b33b, 2017-02-27 (annotated)
- Committer:
- jacobjohnson
- Date:
- Mon Feb 27 17:45:05 2017 +0000
- Revision:
- 1:f30bdcd2b33b
- Parent:
- 0:098463de4c5d
changed the inputscale from 1 to 7 in analogin_api.c. This will need to be changed later, and accessed from the main level, but for now this allows the adc to read a value from 0 to 3.7V, instead of just up to 1V.;
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| group-onsemi | 0:098463de4c5d | 1 | /**************************************************************************//** |
| group-onsemi | 0:098463de4c5d | 2 | * @file efm32zg_dma.h |
| group-onsemi | 0:098463de4c5d | 3 | * @brief EFM32ZG_DMA register and bit field definitions |
| group-onsemi | 0:098463de4c5d | 4 | * @version 5.0.0 |
| group-onsemi | 0:098463de4c5d | 5 | ****************************************************************************** |
| group-onsemi | 0:098463de4c5d | 6 | * @section License |
| group-onsemi | 0:098463de4c5d | 7 | * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| group-onsemi | 0:098463de4c5d | 8 | ****************************************************************************** |
| group-onsemi | 0:098463de4c5d | 9 | * |
| group-onsemi | 0:098463de4c5d | 10 | * Permission is granted to anyone to use this software for any purpose, |
| group-onsemi | 0:098463de4c5d | 11 | * including commercial applications, and to alter it and redistribute it |
| group-onsemi | 0:098463de4c5d | 12 | * freely, subject to the following restrictions: |
| group-onsemi | 0:098463de4c5d | 13 | * |
| group-onsemi | 0:098463de4c5d | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| group-onsemi | 0:098463de4c5d | 15 | * claim that you wrote the original software.@n |
| group-onsemi | 0:098463de4c5d | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| group-onsemi | 0:098463de4c5d | 17 | * misrepresented as being the original software.@n |
| group-onsemi | 0:098463de4c5d | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| group-onsemi | 0:098463de4c5d | 19 | * |
| group-onsemi | 0:098463de4c5d | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| group-onsemi | 0:098463de4c5d | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| group-onsemi | 0:098463de4c5d | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| group-onsemi | 0:098463de4c5d | 23 | * kind, including, but not limited to, any implied warranties of |
| group-onsemi | 0:098463de4c5d | 24 | * merchantability or fitness for any particular purpose or warranties against |
| group-onsemi | 0:098463de4c5d | 25 | * infringement of any proprietary rights of a third party. |
| group-onsemi | 0:098463de4c5d | 26 | * |
| group-onsemi | 0:098463de4c5d | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| group-onsemi | 0:098463de4c5d | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| group-onsemi | 0:098463de4c5d | 29 | * any third party, arising from your use of this Software. |
| group-onsemi | 0:098463de4c5d | 30 | * |
| group-onsemi | 0:098463de4c5d | 31 | *****************************************************************************/ |
| group-onsemi | 0:098463de4c5d | 32 | /**************************************************************************//** |
| group-onsemi | 0:098463de4c5d | 33 | * @addtogroup Parts |
| group-onsemi | 0:098463de4c5d | 34 | * @{ |
| group-onsemi | 0:098463de4c5d | 35 | ******************************************************************************/ |
| group-onsemi | 0:098463de4c5d | 36 | /**************************************************************************//** |
| group-onsemi | 0:098463de4c5d | 37 | * @defgroup EFM32ZG_DMA |
| group-onsemi | 0:098463de4c5d | 38 | * @{ |
| group-onsemi | 0:098463de4c5d | 39 | * @brief EFM32ZG_DMA Register Declaration |
| group-onsemi | 0:098463de4c5d | 40 | *****************************************************************************/ |
| group-onsemi | 0:098463de4c5d | 41 | typedef struct |
| group-onsemi | 0:098463de4c5d | 42 | { |
| group-onsemi | 0:098463de4c5d | 43 | __IM uint32_t STATUS; /**< DMA Status Registers */ |
| group-onsemi | 0:098463de4c5d | 44 | __OM uint32_t CONFIG; /**< DMA Configuration Register */ |
| group-onsemi | 0:098463de4c5d | 45 | __IOM uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */ |
| group-onsemi | 0:098463de4c5d | 46 | __IM uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */ |
| group-onsemi | 0:098463de4c5d | 47 | __IM uint32_t CHWAITSTATUS; /**< Channel Wait on Request Status Register */ |
| group-onsemi | 0:098463de4c5d | 48 | __OM uint32_t CHSWREQ; /**< Channel Software Request Register */ |
| group-onsemi | 0:098463de4c5d | 49 | __IOM uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */ |
| group-onsemi | 0:098463de4c5d | 50 | __OM uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */ |
| group-onsemi | 0:098463de4c5d | 51 | __IOM uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */ |
| group-onsemi | 0:098463de4c5d | 52 | __OM uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */ |
| group-onsemi | 0:098463de4c5d | 53 | __IOM uint32_t CHENS; /**< Channel Enable Set Register */ |
| group-onsemi | 0:098463de4c5d | 54 | __OM uint32_t CHENC; /**< Channel Enable Clear Register */ |
| group-onsemi | 0:098463de4c5d | 55 | __IOM uint32_t CHALTS; /**< Channel Alternate Set Register */ |
| group-onsemi | 0:098463de4c5d | 56 | __OM uint32_t CHALTC; /**< Channel Alternate Clear Register */ |
| group-onsemi | 0:098463de4c5d | 57 | __IOM uint32_t CHPRIS; /**< Channel Priority Set Register */ |
| group-onsemi | 0:098463de4c5d | 58 | __OM uint32_t CHPRIC; /**< Channel Priority Clear Register */ |
| group-onsemi | 0:098463de4c5d | 59 | uint32_t RESERVED0[3]; /**< Reserved for future use **/ |
| group-onsemi | 0:098463de4c5d | 60 | __IOM uint32_t ERRORC; /**< Bus Error Clear Register */ |
| group-onsemi | 0:098463de4c5d | 61 | |
| group-onsemi | 0:098463de4c5d | 62 | uint32_t RESERVED1[880]; /**< Reserved for future use **/ |
| group-onsemi | 0:098463de4c5d | 63 | __IM uint32_t CHREQSTATUS; /**< Channel Request Status */ |
| group-onsemi | 0:098463de4c5d | 64 | uint32_t RESERVED2[1]; /**< Reserved for future use **/ |
| group-onsemi | 0:098463de4c5d | 65 | __IM uint32_t CHSREQSTATUS; /**< Channel Single Request Status */ |
| group-onsemi | 0:098463de4c5d | 66 | |
| group-onsemi | 0:098463de4c5d | 67 | uint32_t RESERVED3[121]; /**< Reserved for future use **/ |
| group-onsemi | 0:098463de4c5d | 68 | __IM uint32_t IF; /**< Interrupt Flag Register */ |
| group-onsemi | 0:098463de4c5d | 69 | __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ |
| group-onsemi | 0:098463de4c5d | 70 | __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ |
| group-onsemi | 0:098463de4c5d | 71 | __IOM uint32_t IEN; /**< Interrupt Enable register */ |
| group-onsemi | 0:098463de4c5d | 72 | |
| group-onsemi | 0:098463de4c5d | 73 | uint32_t RESERVED4[60]; /**< Reserved registers */ |
| group-onsemi | 0:098463de4c5d | 74 | DMA_CH_TypeDef CH[4]; /**< Channel registers */ |
| group-onsemi | 0:098463de4c5d | 75 | } DMA_TypeDef; /** @} */ |
| group-onsemi | 0:098463de4c5d | 76 | |
| group-onsemi | 0:098463de4c5d | 77 | /**************************************************************************//** |
| group-onsemi | 0:098463de4c5d | 78 | * @defgroup EFM32ZG_DMA_BitFields |
| group-onsemi | 0:098463de4c5d | 79 | * @{ |
| group-onsemi | 0:098463de4c5d | 80 | *****************************************************************************/ |
| group-onsemi | 0:098463de4c5d | 81 | |
| group-onsemi | 0:098463de4c5d | 82 | /* Bit fields for DMA STATUS */ |
| group-onsemi | 0:098463de4c5d | 83 | #define _DMA_STATUS_RESETVALUE 0x10030000UL /**< Default value for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 84 | #define _DMA_STATUS_MASK 0x001F00F1UL /**< Mask for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 85 | #define DMA_STATUS_EN (0x1UL << 0) /**< DMA Enable Status */ |
| group-onsemi | 0:098463de4c5d | 86 | #define _DMA_STATUS_EN_SHIFT 0 /**< Shift value for DMA_EN */ |
| group-onsemi | 0:098463de4c5d | 87 | #define _DMA_STATUS_EN_MASK 0x1UL /**< Bit mask for DMA_EN */ |
| group-onsemi | 0:098463de4c5d | 88 | #define _DMA_STATUS_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 89 | #define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 90 | #define _DMA_STATUS_STATE_SHIFT 4 /**< Shift value for DMA_STATE */ |
| group-onsemi | 0:098463de4c5d | 91 | #define _DMA_STATUS_STATE_MASK 0xF0UL /**< Bit mask for DMA_STATE */ |
| group-onsemi | 0:098463de4c5d | 92 | #define _DMA_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 93 | #define _DMA_STATUS_STATE_IDLE 0x00000000UL /**< Mode IDLE for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 94 | #define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL /**< Mode RDCHCTRLDATA for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 95 | #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< Mode RDSRCENDPTR for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 96 | #define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL /**< Mode RDDSTENDPTR for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 97 | #define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL /**< Mode RDSRCDATA for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 98 | #define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL /**< Mode WRDSTDATA for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 99 | #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< Mode WAITREQCLR for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 100 | #define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL /**< Mode WRCHCTRLDATA for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 101 | #define _DMA_STATUS_STATE_STALLED 0x00000008UL /**< Mode STALLED for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 102 | #define _DMA_STATUS_STATE_DONE 0x00000009UL /**< Mode DONE for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 103 | #define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL /**< Mode PERSCATTRANS for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 104 | #define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 105 | #define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4) /**< Shifted mode IDLE for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 106 | #define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) /**< Shifted mode RDCHCTRLDATA for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 107 | #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< Shifted mode RDSRCENDPTR for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 108 | #define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4) /**< Shifted mode RDDSTENDPTR for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 109 | #define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4) /**< Shifted mode RDSRCDATA for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 110 | #define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4) /**< Shifted mode WRDSTDATA for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 111 | #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< Shifted mode WAITREQCLR for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 112 | #define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) /**< Shifted mode WRCHCTRLDATA for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 113 | #define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4) /**< Shifted mode STALLED for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 114 | #define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4) /**< Shifted mode DONE for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 115 | #define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4) /**< Shifted mode PERSCATTRANS for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 116 | #define _DMA_STATUS_CHNUM_SHIFT 16 /**< Shift value for DMA_CHNUM */ |
| group-onsemi | 0:098463de4c5d | 117 | #define _DMA_STATUS_CHNUM_MASK 0x1F0000UL /**< Bit mask for DMA_CHNUM */ |
| group-onsemi | 0:098463de4c5d | 118 | #define _DMA_STATUS_CHNUM_DEFAULT 0x00000003UL /**< Mode DEFAULT for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 119 | #define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_STATUS */ |
| group-onsemi | 0:098463de4c5d | 120 | |
| group-onsemi | 0:098463de4c5d | 121 | /* Bit fields for DMA CONFIG */ |
| group-onsemi | 0:098463de4c5d | 122 | #define _DMA_CONFIG_RESETVALUE 0x00000000UL /**< Default value for DMA_CONFIG */ |
| group-onsemi | 0:098463de4c5d | 123 | #define _DMA_CONFIG_MASK 0x00000021UL /**< Mask for DMA_CONFIG */ |
| group-onsemi | 0:098463de4c5d | 124 | #define DMA_CONFIG_EN (0x1UL << 0) /**< Enable DMA */ |
| group-onsemi | 0:098463de4c5d | 125 | #define _DMA_CONFIG_EN_SHIFT 0 /**< Shift value for DMA_EN */ |
| group-onsemi | 0:098463de4c5d | 126 | #define _DMA_CONFIG_EN_MASK 0x1UL /**< Bit mask for DMA_EN */ |
| group-onsemi | 0:098463de4c5d | 127 | #define _DMA_CONFIG_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */ |
| group-onsemi | 0:098463de4c5d | 128 | #define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CONFIG */ |
| group-onsemi | 0:098463de4c5d | 129 | #define DMA_CONFIG_CHPROT (0x1UL << 5) /**< Channel Protection Control */ |
| group-onsemi | 0:098463de4c5d | 130 | #define _DMA_CONFIG_CHPROT_SHIFT 5 /**< Shift value for DMA_CHPROT */ |
| group-onsemi | 0:098463de4c5d | 131 | #define _DMA_CONFIG_CHPROT_MASK 0x20UL /**< Bit mask for DMA_CHPROT */ |
| group-onsemi | 0:098463de4c5d | 132 | #define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */ |
| group-onsemi | 0:098463de4c5d | 133 | #define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CONFIG */ |
| group-onsemi | 0:098463de4c5d | 134 | |
| group-onsemi | 0:098463de4c5d | 135 | /* Bit fields for DMA CTRLBASE */ |
| group-onsemi | 0:098463de4c5d | 136 | #define _DMA_CTRLBASE_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRLBASE */ |
| group-onsemi | 0:098463de4c5d | 137 | #define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_CTRLBASE */ |
| group-onsemi | 0:098463de4c5d | 138 | #define _DMA_CTRLBASE_CTRLBASE_SHIFT 0 /**< Shift value for DMA_CTRLBASE */ |
| group-onsemi | 0:098463de4c5d | 139 | #define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_CTRLBASE */ |
| group-onsemi | 0:098463de4c5d | 140 | #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRLBASE */ |
| group-onsemi | 0:098463de4c5d | 141 | #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRLBASE */ |
| group-onsemi | 0:098463de4c5d | 142 | |
| group-onsemi | 0:098463de4c5d | 143 | /* Bit fields for DMA ALTCTRLBASE */ |
| group-onsemi | 0:098463de4c5d | 144 | #define _DMA_ALTCTRLBASE_RESETVALUE 0x00000040UL /**< Default value for DMA_ALTCTRLBASE */ |
| group-onsemi | 0:098463de4c5d | 145 | #define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_ALTCTRLBASE */ |
| group-onsemi | 0:098463de4c5d | 146 | #define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0 /**< Shift value for DMA_ALTCTRLBASE */ |
| group-onsemi | 0:098463de4c5d | 147 | #define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_ALTCTRLBASE */ |
| group-onsemi | 0:098463de4c5d | 148 | #define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000040UL /**< Mode DEFAULT for DMA_ALTCTRLBASE */ |
| group-onsemi | 0:098463de4c5d | 149 | #define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ALTCTRLBASE */ |
| group-onsemi | 0:098463de4c5d | 150 | |
| group-onsemi | 0:098463de4c5d | 151 | /* Bit fields for DMA CHWAITSTATUS */ |
| group-onsemi | 0:098463de4c5d | 152 | #define _DMA_CHWAITSTATUS_RESETVALUE 0x0000000FUL /**< Default value for DMA_CHWAITSTATUS */ |
| group-onsemi | 0:098463de4c5d | 153 | #define _DMA_CHWAITSTATUS_MASK 0x0000000FUL /**< Mask for DMA_CHWAITSTATUS */ |
| group-onsemi | 0:098463de4c5d | 154 | #define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0) /**< Channel 0 Wait on Request Status */ |
| group-onsemi | 0:098463de4c5d | 155 | #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0 /**< Shift value for DMA_CH0WAITSTATUS */ |
| group-onsemi | 0:098463de4c5d | 156 | #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0WAITSTATUS */ |
| group-onsemi | 0:098463de4c5d | 157 | #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */ |
| group-onsemi | 0:098463de4c5d | 158 | #define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */ |
| group-onsemi | 0:098463de4c5d | 159 | #define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1) /**< Channel 1 Wait on Request Status */ |
| group-onsemi | 0:098463de4c5d | 160 | #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1 /**< Shift value for DMA_CH1WAITSTATUS */ |
| group-onsemi | 0:098463de4c5d | 161 | #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1WAITSTATUS */ |
| group-onsemi | 0:098463de4c5d | 162 | #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */ |
| group-onsemi | 0:098463de4c5d | 163 | #define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */ |
| group-onsemi | 0:098463de4c5d | 164 | #define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2) /**< Channel 2 Wait on Request Status */ |
| group-onsemi | 0:098463de4c5d | 165 | #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2 /**< Shift value for DMA_CH2WAITSTATUS */ |
| group-onsemi | 0:098463de4c5d | 166 | #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2WAITSTATUS */ |
| group-onsemi | 0:098463de4c5d | 167 | #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */ |
| group-onsemi | 0:098463de4c5d | 168 | #define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */ |
| group-onsemi | 0:098463de4c5d | 169 | #define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3) /**< Channel 3 Wait on Request Status */ |
| group-onsemi | 0:098463de4c5d | 170 | #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3 /**< Shift value for DMA_CH3WAITSTATUS */ |
| group-onsemi | 0:098463de4c5d | 171 | #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3WAITSTATUS */ |
| group-onsemi | 0:098463de4c5d | 172 | #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */ |
| group-onsemi | 0:098463de4c5d | 173 | #define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */ |
| group-onsemi | 0:098463de4c5d | 174 | |
| group-onsemi | 0:098463de4c5d | 175 | /* Bit fields for DMA CHSWREQ */ |
| group-onsemi | 0:098463de4c5d | 176 | #define _DMA_CHSWREQ_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSWREQ */ |
| group-onsemi | 0:098463de4c5d | 177 | #define _DMA_CHSWREQ_MASK 0x0000000FUL /**< Mask for DMA_CHSWREQ */ |
| group-onsemi | 0:098463de4c5d | 178 | #define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0) /**< Channel 0 Software Request */ |
| group-onsemi | 0:098463de4c5d | 179 | #define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0 /**< Shift value for DMA_CH0SWREQ */ |
| group-onsemi | 0:098463de4c5d | 180 | #define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL /**< Bit mask for DMA_CH0SWREQ */ |
| group-onsemi | 0:098463de4c5d | 181 | #define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */ |
| group-onsemi | 0:098463de4c5d | 182 | #define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSWREQ */ |
| group-onsemi | 0:098463de4c5d | 183 | #define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1) /**< Channel 1 Software Request */ |
| group-onsemi | 0:098463de4c5d | 184 | #define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1 /**< Shift value for DMA_CH1SWREQ */ |
| group-onsemi | 0:098463de4c5d | 185 | #define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL /**< Bit mask for DMA_CH1SWREQ */ |
| group-onsemi | 0:098463de4c5d | 186 | #define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */ |
| group-onsemi | 0:098463de4c5d | 187 | #define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSWREQ */ |
| group-onsemi | 0:098463de4c5d | 188 | #define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2) /**< Channel 2 Software Request */ |
| group-onsemi | 0:098463de4c5d | 189 | #define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2 /**< Shift value for DMA_CH2SWREQ */ |
| group-onsemi | 0:098463de4c5d | 190 | #define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL /**< Bit mask for DMA_CH2SWREQ */ |
| group-onsemi | 0:098463de4c5d | 191 | #define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */ |
| group-onsemi | 0:098463de4c5d | 192 | #define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSWREQ */ |
| group-onsemi | 0:098463de4c5d | 193 | #define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3) /**< Channel 3 Software Request */ |
| group-onsemi | 0:098463de4c5d | 194 | #define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3 /**< Shift value for DMA_CH3SWREQ */ |
| group-onsemi | 0:098463de4c5d | 195 | #define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL /**< Bit mask for DMA_CH3SWREQ */ |
| group-onsemi | 0:098463de4c5d | 196 | #define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */ |
| group-onsemi | 0:098463de4c5d | 197 | #define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSWREQ */ |
| group-onsemi | 0:098463de4c5d | 198 | |
| group-onsemi | 0:098463de4c5d | 199 | /* Bit fields for DMA CHUSEBURSTS */ |
| group-onsemi | 0:098463de4c5d | 200 | #define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTS */ |
| group-onsemi | 0:098463de4c5d | 201 | #define _DMA_CHUSEBURSTS_MASK 0x0000000FUL /**< Mask for DMA_CHUSEBURSTS */ |
| group-onsemi | 0:098463de4c5d | 202 | #define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0) /**< Channel 0 Useburst Set */ |
| group-onsemi | 0:098463de4c5d | 203 | #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTS */ |
| group-onsemi | 0:098463de4c5d | 204 | #define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTS */ |
| group-onsemi | 0:098463de4c5d | 205 | #define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */ |
| group-onsemi | 0:098463de4c5d | 206 | #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL /**< Mode SINGLEANDBURST for DMA_CHUSEBURSTS */ |
| group-onsemi | 0:098463de4c5d | 207 | #define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL /**< Mode BURSTONLY for DMA_CHUSEBURSTS */ |
| group-onsemi | 0:098463de4c5d | 208 | #define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */ |
| group-onsemi | 0:098463de4c5d | 209 | #define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) /**< Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS */ |
| group-onsemi | 0:098463de4c5d | 210 | #define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0) /**< Shifted mode BURSTONLY for DMA_CHUSEBURSTS */ |
| group-onsemi | 0:098463de4c5d | 211 | #define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1) /**< Channel 1 Useburst Set */ |
| group-onsemi | 0:098463de4c5d | 212 | #define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTS */ |
| group-onsemi | 0:098463de4c5d | 213 | #define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTS */ |
| group-onsemi | 0:098463de4c5d | 214 | #define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */ |
| group-onsemi | 0:098463de4c5d | 215 | #define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */ |
| group-onsemi | 0:098463de4c5d | 216 | #define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2) /**< Channel 2 Useburst Set */ |
| group-onsemi | 0:098463de4c5d | 217 | #define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTS */ |
| group-onsemi | 0:098463de4c5d | 218 | #define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTS */ |
| group-onsemi | 0:098463de4c5d | 219 | #define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */ |
| group-onsemi | 0:098463de4c5d | 220 | #define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */ |
| group-onsemi | 0:098463de4c5d | 221 | #define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3) /**< Channel 3 Useburst Set */ |
| group-onsemi | 0:098463de4c5d | 222 | #define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTS */ |
| group-onsemi | 0:098463de4c5d | 223 | #define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTS */ |
| group-onsemi | 0:098463de4c5d | 224 | #define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */ |
| group-onsemi | 0:098463de4c5d | 225 | #define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */ |
| group-onsemi | 0:098463de4c5d | 226 | |
| group-onsemi | 0:098463de4c5d | 227 | /* Bit fields for DMA CHUSEBURSTC */ |
| group-onsemi | 0:098463de4c5d | 228 | #define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTC */ |
| group-onsemi | 0:098463de4c5d | 229 | #define _DMA_CHUSEBURSTC_MASK 0x0000000FUL /**< Mask for DMA_CHUSEBURSTC */ |
| group-onsemi | 0:098463de4c5d | 230 | #define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0) /**< Channel 0 Useburst Clear */ |
| group-onsemi | 0:098463de4c5d | 231 | #define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTC */ |
| group-onsemi | 0:098463de4c5d | 232 | #define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTC */ |
| group-onsemi | 0:098463de4c5d | 233 | #define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */ |
| group-onsemi | 0:098463de4c5d | 234 | #define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */ |
| group-onsemi | 0:098463de4c5d | 235 | #define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1) /**< Channel 1 Useburst Clear */ |
| group-onsemi | 0:098463de4c5d | 236 | #define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTC */ |
| group-onsemi | 0:098463de4c5d | 237 | #define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTC */ |
| group-onsemi | 0:098463de4c5d | 238 | #define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */ |
| group-onsemi | 0:098463de4c5d | 239 | #define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */ |
| group-onsemi | 0:098463de4c5d | 240 | #define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2) /**< Channel 2 Useburst Clear */ |
| group-onsemi | 0:098463de4c5d | 241 | #define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTC */ |
| group-onsemi | 0:098463de4c5d | 242 | #define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTC */ |
| group-onsemi | 0:098463de4c5d | 243 | #define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */ |
| group-onsemi | 0:098463de4c5d | 244 | #define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */ |
| group-onsemi | 0:098463de4c5d | 245 | #define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3) /**< Channel 3 Useburst Clear */ |
| group-onsemi | 0:098463de4c5d | 246 | #define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTC */ |
| group-onsemi | 0:098463de4c5d | 247 | #define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTC */ |
| group-onsemi | 0:098463de4c5d | 248 | #define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */ |
| group-onsemi | 0:098463de4c5d | 249 | #define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */ |
| group-onsemi | 0:098463de4c5d | 250 | |
| group-onsemi | 0:098463de4c5d | 251 | /* Bit fields for DMA CHREQMASKS */ |
| group-onsemi | 0:098463de4c5d | 252 | #define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKS */ |
| group-onsemi | 0:098463de4c5d | 253 | #define _DMA_CHREQMASKS_MASK 0x0000000FUL /**< Mask for DMA_CHREQMASKS */ |
| group-onsemi | 0:098463de4c5d | 254 | #define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0) /**< Channel 0 Request Mask Set */ |
| group-onsemi | 0:098463de4c5d | 255 | #define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0 /**< Shift value for DMA_CH0REQMASKS */ |
| group-onsemi | 0:098463de4c5d | 256 | #define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKS */ |
| group-onsemi | 0:098463de4c5d | 257 | #define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */ |
| group-onsemi | 0:098463de4c5d | 258 | #define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */ |
| group-onsemi | 0:098463de4c5d | 259 | #define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1) /**< Channel 1 Request Mask Set */ |
| group-onsemi | 0:098463de4c5d | 260 | #define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1 /**< Shift value for DMA_CH1REQMASKS */ |
| group-onsemi | 0:098463de4c5d | 261 | #define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKS */ |
| group-onsemi | 0:098463de4c5d | 262 | #define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */ |
| group-onsemi | 0:098463de4c5d | 263 | #define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */ |
| group-onsemi | 0:098463de4c5d | 264 | #define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2) /**< Channel 2 Request Mask Set */ |
| group-onsemi | 0:098463de4c5d | 265 | #define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2 /**< Shift value for DMA_CH2REQMASKS */ |
| group-onsemi | 0:098463de4c5d | 266 | #define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKS */ |
| group-onsemi | 0:098463de4c5d | 267 | #define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */ |
| group-onsemi | 0:098463de4c5d | 268 | #define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */ |
| group-onsemi | 0:098463de4c5d | 269 | #define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3) /**< Channel 3 Request Mask Set */ |
| group-onsemi | 0:098463de4c5d | 270 | #define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3 /**< Shift value for DMA_CH3REQMASKS */ |
| group-onsemi | 0:098463de4c5d | 271 | #define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKS */ |
| group-onsemi | 0:098463de4c5d | 272 | #define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */ |
| group-onsemi | 0:098463de4c5d | 273 | #define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */ |
| group-onsemi | 0:098463de4c5d | 274 | |
| group-onsemi | 0:098463de4c5d | 275 | /* Bit fields for DMA CHREQMASKC */ |
| group-onsemi | 0:098463de4c5d | 276 | #define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKC */ |
| group-onsemi | 0:098463de4c5d | 277 | #define _DMA_CHREQMASKC_MASK 0x0000000FUL /**< Mask for DMA_CHREQMASKC */ |
| group-onsemi | 0:098463de4c5d | 278 | #define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0) /**< Channel 0 Request Mask Clear */ |
| group-onsemi | 0:098463de4c5d | 279 | #define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0 /**< Shift value for DMA_CH0REQMASKC */ |
| group-onsemi | 0:098463de4c5d | 280 | #define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKC */ |
| group-onsemi | 0:098463de4c5d | 281 | #define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */ |
| group-onsemi | 0:098463de4c5d | 282 | #define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */ |
| group-onsemi | 0:098463de4c5d | 283 | #define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1) /**< Channel 1 Request Mask Clear */ |
| group-onsemi | 0:098463de4c5d | 284 | #define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1 /**< Shift value for DMA_CH1REQMASKC */ |
| group-onsemi | 0:098463de4c5d | 285 | #define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKC */ |
| group-onsemi | 0:098463de4c5d | 286 | #define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */ |
| group-onsemi | 0:098463de4c5d | 287 | #define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */ |
| group-onsemi | 0:098463de4c5d | 288 | #define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2) /**< Channel 2 Request Mask Clear */ |
| group-onsemi | 0:098463de4c5d | 289 | #define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2 /**< Shift value for DMA_CH2REQMASKC */ |
| group-onsemi | 0:098463de4c5d | 290 | #define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKC */ |
| group-onsemi | 0:098463de4c5d | 291 | #define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */ |
| group-onsemi | 0:098463de4c5d | 292 | #define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */ |
| group-onsemi | 0:098463de4c5d | 293 | #define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3) /**< Channel 3 Request Mask Clear */ |
| group-onsemi | 0:098463de4c5d | 294 | #define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3 /**< Shift value for DMA_CH3REQMASKC */ |
| group-onsemi | 0:098463de4c5d | 295 | #define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKC */ |
| group-onsemi | 0:098463de4c5d | 296 | #define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */ |
| group-onsemi | 0:098463de4c5d | 297 | #define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */ |
| group-onsemi | 0:098463de4c5d | 298 | |
| group-onsemi | 0:098463de4c5d | 299 | /* Bit fields for DMA CHENS */ |
| group-onsemi | 0:098463de4c5d | 300 | #define _DMA_CHENS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENS */ |
| group-onsemi | 0:098463de4c5d | 301 | #define _DMA_CHENS_MASK 0x0000000FUL /**< Mask for DMA_CHENS */ |
| group-onsemi | 0:098463de4c5d | 302 | #define DMA_CHENS_CH0ENS (0x1UL << 0) /**< Channel 0 Enable Set */ |
| group-onsemi | 0:098463de4c5d | 303 | #define _DMA_CHENS_CH0ENS_SHIFT 0 /**< Shift value for DMA_CH0ENS */ |
| group-onsemi | 0:098463de4c5d | 304 | #define _DMA_CHENS_CH0ENS_MASK 0x1UL /**< Bit mask for DMA_CH0ENS */ |
| group-onsemi | 0:098463de4c5d | 305 | #define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */ |
| group-onsemi | 0:098463de4c5d | 306 | #define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENS */ |
| group-onsemi | 0:098463de4c5d | 307 | #define DMA_CHENS_CH1ENS (0x1UL << 1) /**< Channel 1 Enable Set */ |
| group-onsemi | 0:098463de4c5d | 308 | #define _DMA_CHENS_CH1ENS_SHIFT 1 /**< Shift value for DMA_CH1ENS */ |
| group-onsemi | 0:098463de4c5d | 309 | #define _DMA_CHENS_CH1ENS_MASK 0x2UL /**< Bit mask for DMA_CH1ENS */ |
| group-onsemi | 0:098463de4c5d | 310 | #define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */ |
| group-onsemi | 0:098463de4c5d | 311 | #define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENS */ |
| group-onsemi | 0:098463de4c5d | 312 | #define DMA_CHENS_CH2ENS (0x1UL << 2) /**< Channel 2 Enable Set */ |
| group-onsemi | 0:098463de4c5d | 313 | #define _DMA_CHENS_CH2ENS_SHIFT 2 /**< Shift value for DMA_CH2ENS */ |
| group-onsemi | 0:098463de4c5d | 314 | #define _DMA_CHENS_CH2ENS_MASK 0x4UL /**< Bit mask for DMA_CH2ENS */ |
| group-onsemi | 0:098463de4c5d | 315 | #define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */ |
| group-onsemi | 0:098463de4c5d | 316 | #define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENS */ |
| group-onsemi | 0:098463de4c5d | 317 | #define DMA_CHENS_CH3ENS (0x1UL << 3) /**< Channel 3 Enable Set */ |
| group-onsemi | 0:098463de4c5d | 318 | #define _DMA_CHENS_CH3ENS_SHIFT 3 /**< Shift value for DMA_CH3ENS */ |
| group-onsemi | 0:098463de4c5d | 319 | #define _DMA_CHENS_CH3ENS_MASK 0x8UL /**< Bit mask for DMA_CH3ENS */ |
| group-onsemi | 0:098463de4c5d | 320 | #define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */ |
| group-onsemi | 0:098463de4c5d | 321 | #define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENS */ |
| group-onsemi | 0:098463de4c5d | 322 | |
| group-onsemi | 0:098463de4c5d | 323 | /* Bit fields for DMA CHENC */ |
| group-onsemi | 0:098463de4c5d | 324 | #define _DMA_CHENC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENC */ |
| group-onsemi | 0:098463de4c5d | 325 | #define _DMA_CHENC_MASK 0x0000000FUL /**< Mask for DMA_CHENC */ |
| group-onsemi | 0:098463de4c5d | 326 | #define DMA_CHENC_CH0ENC (0x1UL << 0) /**< Channel 0 Enable Clear */ |
| group-onsemi | 0:098463de4c5d | 327 | #define _DMA_CHENC_CH0ENC_SHIFT 0 /**< Shift value for DMA_CH0ENC */ |
| group-onsemi | 0:098463de4c5d | 328 | #define _DMA_CHENC_CH0ENC_MASK 0x1UL /**< Bit mask for DMA_CH0ENC */ |
| group-onsemi | 0:098463de4c5d | 329 | #define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */ |
| group-onsemi | 0:098463de4c5d | 330 | #define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENC */ |
| group-onsemi | 0:098463de4c5d | 331 | #define DMA_CHENC_CH1ENC (0x1UL << 1) /**< Channel 1 Enable Clear */ |
| group-onsemi | 0:098463de4c5d | 332 | #define _DMA_CHENC_CH1ENC_SHIFT 1 /**< Shift value for DMA_CH1ENC */ |
| group-onsemi | 0:098463de4c5d | 333 | #define _DMA_CHENC_CH1ENC_MASK 0x2UL /**< Bit mask for DMA_CH1ENC */ |
| group-onsemi | 0:098463de4c5d | 334 | #define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */ |
| group-onsemi | 0:098463de4c5d | 335 | #define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENC */ |
| group-onsemi | 0:098463de4c5d | 336 | #define DMA_CHENC_CH2ENC (0x1UL << 2) /**< Channel 2 Enable Clear */ |
| group-onsemi | 0:098463de4c5d | 337 | #define _DMA_CHENC_CH2ENC_SHIFT 2 /**< Shift value for DMA_CH2ENC */ |
| group-onsemi | 0:098463de4c5d | 338 | #define _DMA_CHENC_CH2ENC_MASK 0x4UL /**< Bit mask for DMA_CH2ENC */ |
| group-onsemi | 0:098463de4c5d | 339 | #define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */ |
| group-onsemi | 0:098463de4c5d | 340 | #define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENC */ |
| group-onsemi | 0:098463de4c5d | 341 | #define DMA_CHENC_CH3ENC (0x1UL << 3) /**< Channel 3 Enable Clear */ |
| group-onsemi | 0:098463de4c5d | 342 | #define _DMA_CHENC_CH3ENC_SHIFT 3 /**< Shift value for DMA_CH3ENC */ |
| group-onsemi | 0:098463de4c5d | 343 | #define _DMA_CHENC_CH3ENC_MASK 0x8UL /**< Bit mask for DMA_CH3ENC */ |
| group-onsemi | 0:098463de4c5d | 344 | #define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */ |
| group-onsemi | 0:098463de4c5d | 345 | #define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENC */ |
| group-onsemi | 0:098463de4c5d | 346 | |
| group-onsemi | 0:098463de4c5d | 347 | /* Bit fields for DMA CHALTS */ |
| group-onsemi | 0:098463de4c5d | 348 | #define _DMA_CHALTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTS */ |
| group-onsemi | 0:098463de4c5d | 349 | #define _DMA_CHALTS_MASK 0x0000000FUL /**< Mask for DMA_CHALTS */ |
| group-onsemi | 0:098463de4c5d | 350 | #define DMA_CHALTS_CH0ALTS (0x1UL << 0) /**< Channel 0 Alternate Structure Set */ |
| group-onsemi | 0:098463de4c5d | 351 | #define _DMA_CHALTS_CH0ALTS_SHIFT 0 /**< Shift value for DMA_CH0ALTS */ |
| group-onsemi | 0:098463de4c5d | 352 | #define _DMA_CHALTS_CH0ALTS_MASK 0x1UL /**< Bit mask for DMA_CH0ALTS */ |
| group-onsemi | 0:098463de4c5d | 353 | #define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */ |
| group-onsemi | 0:098463de4c5d | 354 | #define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTS */ |
| group-onsemi | 0:098463de4c5d | 355 | #define DMA_CHALTS_CH1ALTS (0x1UL << 1) /**< Channel 1 Alternate Structure Set */ |
| group-onsemi | 0:098463de4c5d | 356 | #define _DMA_CHALTS_CH1ALTS_SHIFT 1 /**< Shift value for DMA_CH1ALTS */ |
| group-onsemi | 0:098463de4c5d | 357 | #define _DMA_CHALTS_CH1ALTS_MASK 0x2UL /**< Bit mask for DMA_CH1ALTS */ |
| group-onsemi | 0:098463de4c5d | 358 | #define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */ |
| group-onsemi | 0:098463de4c5d | 359 | #define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTS */ |
| group-onsemi | 0:098463de4c5d | 360 | #define DMA_CHALTS_CH2ALTS (0x1UL << 2) /**< Channel 2 Alternate Structure Set */ |
| group-onsemi | 0:098463de4c5d | 361 | #define _DMA_CHALTS_CH2ALTS_SHIFT 2 /**< Shift value for DMA_CH2ALTS */ |
| group-onsemi | 0:098463de4c5d | 362 | #define _DMA_CHALTS_CH2ALTS_MASK 0x4UL /**< Bit mask for DMA_CH2ALTS */ |
| group-onsemi | 0:098463de4c5d | 363 | #define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */ |
| group-onsemi | 0:098463de4c5d | 364 | #define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTS */ |
| group-onsemi | 0:098463de4c5d | 365 | #define DMA_CHALTS_CH3ALTS (0x1UL << 3) /**< Channel 3 Alternate Structure Set */ |
| group-onsemi | 0:098463de4c5d | 366 | #define _DMA_CHALTS_CH3ALTS_SHIFT 3 /**< Shift value for DMA_CH3ALTS */ |
| group-onsemi | 0:098463de4c5d | 367 | #define _DMA_CHALTS_CH3ALTS_MASK 0x8UL /**< Bit mask for DMA_CH3ALTS */ |
| group-onsemi | 0:098463de4c5d | 368 | #define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */ |
| group-onsemi | 0:098463de4c5d | 369 | #define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTS */ |
| group-onsemi | 0:098463de4c5d | 370 | |
| group-onsemi | 0:098463de4c5d | 371 | /* Bit fields for DMA CHALTC */ |
| group-onsemi | 0:098463de4c5d | 372 | #define _DMA_CHALTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTC */ |
| group-onsemi | 0:098463de4c5d | 373 | #define _DMA_CHALTC_MASK 0x0000000FUL /**< Mask for DMA_CHALTC */ |
| group-onsemi | 0:098463de4c5d | 374 | #define DMA_CHALTC_CH0ALTC (0x1UL << 0) /**< Channel 0 Alternate Clear */ |
| group-onsemi | 0:098463de4c5d | 375 | #define _DMA_CHALTC_CH0ALTC_SHIFT 0 /**< Shift value for DMA_CH0ALTC */ |
| group-onsemi | 0:098463de4c5d | 376 | #define _DMA_CHALTC_CH0ALTC_MASK 0x1UL /**< Bit mask for DMA_CH0ALTC */ |
| group-onsemi | 0:098463de4c5d | 377 | #define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */ |
| group-onsemi | 0:098463de4c5d | 378 | #define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTC */ |
| group-onsemi | 0:098463de4c5d | 379 | #define DMA_CHALTC_CH1ALTC (0x1UL << 1) /**< Channel 1 Alternate Clear */ |
| group-onsemi | 0:098463de4c5d | 380 | #define _DMA_CHALTC_CH1ALTC_SHIFT 1 /**< Shift value for DMA_CH1ALTC */ |
| group-onsemi | 0:098463de4c5d | 381 | #define _DMA_CHALTC_CH1ALTC_MASK 0x2UL /**< Bit mask for DMA_CH1ALTC */ |
| group-onsemi | 0:098463de4c5d | 382 | #define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */ |
| group-onsemi | 0:098463de4c5d | 383 | #define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTC */ |
| group-onsemi | 0:098463de4c5d | 384 | #define DMA_CHALTC_CH2ALTC (0x1UL << 2) /**< Channel 2 Alternate Clear */ |
| group-onsemi | 0:098463de4c5d | 385 | #define _DMA_CHALTC_CH2ALTC_SHIFT 2 /**< Shift value for DMA_CH2ALTC */ |
| group-onsemi | 0:098463de4c5d | 386 | #define _DMA_CHALTC_CH2ALTC_MASK 0x4UL /**< Bit mask for DMA_CH2ALTC */ |
| group-onsemi | 0:098463de4c5d | 387 | #define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */ |
| group-onsemi | 0:098463de4c5d | 388 | #define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTC */ |
| group-onsemi | 0:098463de4c5d | 389 | #define DMA_CHALTC_CH3ALTC (0x1UL << 3) /**< Channel 3 Alternate Clear */ |
| group-onsemi | 0:098463de4c5d | 390 | #define _DMA_CHALTC_CH3ALTC_SHIFT 3 /**< Shift value for DMA_CH3ALTC */ |
| group-onsemi | 0:098463de4c5d | 391 | #define _DMA_CHALTC_CH3ALTC_MASK 0x8UL /**< Bit mask for DMA_CH3ALTC */ |
| group-onsemi | 0:098463de4c5d | 392 | #define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */ |
| group-onsemi | 0:098463de4c5d | 393 | #define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTC */ |
| group-onsemi | 0:098463de4c5d | 394 | |
| group-onsemi | 0:098463de4c5d | 395 | /* Bit fields for DMA CHPRIS */ |
| group-onsemi | 0:098463de4c5d | 396 | #define _DMA_CHPRIS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIS */ |
| group-onsemi | 0:098463de4c5d | 397 | #define _DMA_CHPRIS_MASK 0x0000000FUL /**< Mask for DMA_CHPRIS */ |
| group-onsemi | 0:098463de4c5d | 398 | #define DMA_CHPRIS_CH0PRIS (0x1UL << 0) /**< Channel 0 High Priority Set */ |
| group-onsemi | 0:098463de4c5d | 399 | #define _DMA_CHPRIS_CH0PRIS_SHIFT 0 /**< Shift value for DMA_CH0PRIS */ |
| group-onsemi | 0:098463de4c5d | 400 | #define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL /**< Bit mask for DMA_CH0PRIS */ |
| group-onsemi | 0:098463de4c5d | 401 | #define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */ |
| group-onsemi | 0:098463de4c5d | 402 | #define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIS */ |
| group-onsemi | 0:098463de4c5d | 403 | #define DMA_CHPRIS_CH1PRIS (0x1UL << 1) /**< Channel 1 High Priority Set */ |
| group-onsemi | 0:098463de4c5d | 404 | #define _DMA_CHPRIS_CH1PRIS_SHIFT 1 /**< Shift value for DMA_CH1PRIS */ |
| group-onsemi | 0:098463de4c5d | 405 | #define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL /**< Bit mask for DMA_CH1PRIS */ |
| group-onsemi | 0:098463de4c5d | 406 | #define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */ |
| group-onsemi | 0:098463de4c5d | 407 | #define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIS */ |
| group-onsemi | 0:098463de4c5d | 408 | #define DMA_CHPRIS_CH2PRIS (0x1UL << 2) /**< Channel 2 High Priority Set */ |
| group-onsemi | 0:098463de4c5d | 409 | #define _DMA_CHPRIS_CH2PRIS_SHIFT 2 /**< Shift value for DMA_CH2PRIS */ |
| group-onsemi | 0:098463de4c5d | 410 | #define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL /**< Bit mask for DMA_CH2PRIS */ |
| group-onsemi | 0:098463de4c5d | 411 | #define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */ |
| group-onsemi | 0:098463de4c5d | 412 | #define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIS */ |
| group-onsemi | 0:098463de4c5d | 413 | #define DMA_CHPRIS_CH3PRIS (0x1UL << 3) /**< Channel 3 High Priority Set */ |
| group-onsemi | 0:098463de4c5d | 414 | #define _DMA_CHPRIS_CH3PRIS_SHIFT 3 /**< Shift value for DMA_CH3PRIS */ |
| group-onsemi | 0:098463de4c5d | 415 | #define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL /**< Bit mask for DMA_CH3PRIS */ |
| group-onsemi | 0:098463de4c5d | 416 | #define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */ |
| group-onsemi | 0:098463de4c5d | 417 | #define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIS */ |
| group-onsemi | 0:098463de4c5d | 418 | |
| group-onsemi | 0:098463de4c5d | 419 | /* Bit fields for DMA CHPRIC */ |
| group-onsemi | 0:098463de4c5d | 420 | #define _DMA_CHPRIC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIC */ |
| group-onsemi | 0:098463de4c5d | 421 | #define _DMA_CHPRIC_MASK 0x0000000FUL /**< Mask for DMA_CHPRIC */ |
| group-onsemi | 0:098463de4c5d | 422 | #define DMA_CHPRIC_CH0PRIC (0x1UL << 0) /**< Channel 0 High Priority Clear */ |
| group-onsemi | 0:098463de4c5d | 423 | #define _DMA_CHPRIC_CH0PRIC_SHIFT 0 /**< Shift value for DMA_CH0PRIC */ |
| group-onsemi | 0:098463de4c5d | 424 | #define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL /**< Bit mask for DMA_CH0PRIC */ |
| group-onsemi | 0:098463de4c5d | 425 | #define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */ |
| group-onsemi | 0:098463de4c5d | 426 | #define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIC */ |
| group-onsemi | 0:098463de4c5d | 427 | #define DMA_CHPRIC_CH1PRIC (0x1UL << 1) /**< Channel 1 High Priority Clear */ |
| group-onsemi | 0:098463de4c5d | 428 | #define _DMA_CHPRIC_CH1PRIC_SHIFT 1 /**< Shift value for DMA_CH1PRIC */ |
| group-onsemi | 0:098463de4c5d | 429 | #define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL /**< Bit mask for DMA_CH1PRIC */ |
| group-onsemi | 0:098463de4c5d | 430 | #define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */ |
| group-onsemi | 0:098463de4c5d | 431 | #define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIC */ |
| group-onsemi | 0:098463de4c5d | 432 | #define DMA_CHPRIC_CH2PRIC (0x1UL << 2) /**< Channel 2 High Priority Clear */ |
| group-onsemi | 0:098463de4c5d | 433 | #define _DMA_CHPRIC_CH2PRIC_SHIFT 2 /**< Shift value for DMA_CH2PRIC */ |
| group-onsemi | 0:098463de4c5d | 434 | #define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL /**< Bit mask for DMA_CH2PRIC */ |
| group-onsemi | 0:098463de4c5d | 435 | #define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */ |
| group-onsemi | 0:098463de4c5d | 436 | #define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIC */ |
| group-onsemi | 0:098463de4c5d | 437 | #define DMA_CHPRIC_CH3PRIC (0x1UL << 3) /**< Channel 3 High Priority Clear */ |
| group-onsemi | 0:098463de4c5d | 438 | #define _DMA_CHPRIC_CH3PRIC_SHIFT 3 /**< Shift value for DMA_CH3PRIC */ |
| group-onsemi | 0:098463de4c5d | 439 | #define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL /**< Bit mask for DMA_CH3PRIC */ |
| group-onsemi | 0:098463de4c5d | 440 | #define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */ |
| group-onsemi | 0:098463de4c5d | 441 | #define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIC */ |
| group-onsemi | 0:098463de4c5d | 442 | |
| group-onsemi | 0:098463de4c5d | 443 | /* Bit fields for DMA ERRORC */ |
| group-onsemi | 0:098463de4c5d | 444 | #define _DMA_ERRORC_RESETVALUE 0x00000000UL /**< Default value for DMA_ERRORC */ |
| group-onsemi | 0:098463de4c5d | 445 | #define _DMA_ERRORC_MASK 0x00000001UL /**< Mask for DMA_ERRORC */ |
| group-onsemi | 0:098463de4c5d | 446 | #define DMA_ERRORC_ERRORC (0x1UL << 0) /**< Bus Error Clear */ |
| group-onsemi | 0:098463de4c5d | 447 | #define _DMA_ERRORC_ERRORC_SHIFT 0 /**< Shift value for DMA_ERRORC */ |
| group-onsemi | 0:098463de4c5d | 448 | #define _DMA_ERRORC_ERRORC_MASK 0x1UL /**< Bit mask for DMA_ERRORC */ |
| group-onsemi | 0:098463de4c5d | 449 | #define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_ERRORC */ |
| group-onsemi | 0:098463de4c5d | 450 | #define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ERRORC */ |
| group-onsemi | 0:098463de4c5d | 451 | |
| group-onsemi | 0:098463de4c5d | 452 | /* Bit fields for DMA CHREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 453 | #define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 454 | #define _DMA_CHREQSTATUS_MASK 0x0000000FUL /**< Mask for DMA_CHREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 455 | #define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0) /**< Channel 0 Request Status */ |
| group-onsemi | 0:098463de4c5d | 456 | #define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0REQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 457 | #define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0REQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 458 | #define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 459 | #define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 460 | #define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1) /**< Channel 1 Request Status */ |
| group-onsemi | 0:098463de4c5d | 461 | #define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1REQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 462 | #define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1REQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 463 | #define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 464 | #define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 465 | #define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2) /**< Channel 2 Request Status */ |
| group-onsemi | 0:098463de4c5d | 466 | #define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2REQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 467 | #define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2REQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 468 | #define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 469 | #define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 470 | #define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3) /**< Channel 3 Request Status */ |
| group-onsemi | 0:098463de4c5d | 471 | #define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3REQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 472 | #define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3REQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 473 | #define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 474 | #define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 475 | |
| group-onsemi | 0:098463de4c5d | 476 | /* Bit fields for DMA CHSREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 477 | #define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 478 | #define _DMA_CHSREQSTATUS_MASK 0x0000000FUL /**< Mask for DMA_CHSREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 479 | #define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0) /**< Channel 0 Single Request Status */ |
| group-onsemi | 0:098463de4c5d | 480 | #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0SREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 481 | #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0SREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 482 | #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 483 | #define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 484 | #define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1) /**< Channel 1 Single Request Status */ |
| group-onsemi | 0:098463de4c5d | 485 | #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1SREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 486 | #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1SREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 487 | #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 488 | #define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 489 | #define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2) /**< Channel 2 Single Request Status */ |
| group-onsemi | 0:098463de4c5d | 490 | #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2SREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 491 | #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2SREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 492 | #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 493 | #define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 494 | #define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3) /**< Channel 3 Single Request Status */ |
| group-onsemi | 0:098463de4c5d | 495 | #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3SREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 496 | #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3SREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 497 | #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 498 | #define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */ |
| group-onsemi | 0:098463de4c5d | 499 | |
| group-onsemi | 0:098463de4c5d | 500 | /* Bit fields for DMA IF */ |
| group-onsemi | 0:098463de4c5d | 501 | #define _DMA_IF_RESETVALUE 0x00000000UL /**< Default value for DMA_IF */ |
| group-onsemi | 0:098463de4c5d | 502 | #define _DMA_IF_MASK 0x8000000FUL /**< Mask for DMA_IF */ |
| group-onsemi | 0:098463de4c5d | 503 | #define DMA_IF_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag */ |
| group-onsemi | 0:098463de4c5d | 504 | #define _DMA_IF_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */ |
| group-onsemi | 0:098463de4c5d | 505 | #define _DMA_IF_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */ |
| group-onsemi | 0:098463de4c5d | 506 | #define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */ |
| group-onsemi | 0:098463de4c5d | 507 | #define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IF */ |
| group-onsemi | 0:098463de4c5d | 508 | #define DMA_IF_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag */ |
| group-onsemi | 0:098463de4c5d | 509 | #define _DMA_IF_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */ |
| group-onsemi | 0:098463de4c5d | 510 | #define _DMA_IF_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */ |
| group-onsemi | 0:098463de4c5d | 511 | #define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */ |
| group-onsemi | 0:098463de4c5d | 512 | #define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IF */ |
| group-onsemi | 0:098463de4c5d | 513 | #define DMA_IF_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag */ |
| group-onsemi | 0:098463de4c5d | 514 | #define _DMA_IF_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */ |
| group-onsemi | 0:098463de4c5d | 515 | #define _DMA_IF_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */ |
| group-onsemi | 0:098463de4c5d | 516 | #define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */ |
| group-onsemi | 0:098463de4c5d | 517 | #define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IF */ |
| group-onsemi | 0:098463de4c5d | 518 | #define DMA_IF_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag */ |
| group-onsemi | 0:098463de4c5d | 519 | #define _DMA_IF_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */ |
| group-onsemi | 0:098463de4c5d | 520 | #define _DMA_IF_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */ |
| group-onsemi | 0:098463de4c5d | 521 | #define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */ |
| group-onsemi | 0:098463de4c5d | 522 | #define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IF */ |
| group-onsemi | 0:098463de4c5d | 523 | #define DMA_IF_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag */ |
| group-onsemi | 0:098463de4c5d | 524 | #define _DMA_IF_ERR_SHIFT 31 /**< Shift value for DMA_ERR */ |
| group-onsemi | 0:098463de4c5d | 525 | #define _DMA_IF_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */ |
| group-onsemi | 0:098463de4c5d | 526 | #define _DMA_IF_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */ |
| group-onsemi | 0:098463de4c5d | 527 | #define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IF */ |
| group-onsemi | 0:098463de4c5d | 528 | |
| group-onsemi | 0:098463de4c5d | 529 | /* Bit fields for DMA IFS */ |
| group-onsemi | 0:098463de4c5d | 530 | #define _DMA_IFS_RESETVALUE 0x00000000UL /**< Default value for DMA_IFS */ |
| group-onsemi | 0:098463de4c5d | 531 | #define _DMA_IFS_MASK 0x8000000FUL /**< Mask for DMA_IFS */ |
| group-onsemi | 0:098463de4c5d | 532 | #define DMA_IFS_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Set */ |
| group-onsemi | 0:098463de4c5d | 533 | #define _DMA_IFS_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */ |
| group-onsemi | 0:098463de4c5d | 534 | #define _DMA_IFS_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */ |
| group-onsemi | 0:098463de4c5d | 535 | #define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */ |
| group-onsemi | 0:098463de4c5d | 536 | #define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFS */ |
| group-onsemi | 0:098463de4c5d | 537 | #define DMA_IFS_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Set */ |
| group-onsemi | 0:098463de4c5d | 538 | #define _DMA_IFS_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */ |
| group-onsemi | 0:098463de4c5d | 539 | #define _DMA_IFS_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */ |
| group-onsemi | 0:098463de4c5d | 540 | #define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */ |
| group-onsemi | 0:098463de4c5d | 541 | #define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFS */ |
| group-onsemi | 0:098463de4c5d | 542 | #define DMA_IFS_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Set */ |
| group-onsemi | 0:098463de4c5d | 543 | #define _DMA_IFS_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */ |
| group-onsemi | 0:098463de4c5d | 544 | #define _DMA_IFS_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */ |
| group-onsemi | 0:098463de4c5d | 545 | #define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */ |
| group-onsemi | 0:098463de4c5d | 546 | #define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFS */ |
| group-onsemi | 0:098463de4c5d | 547 | #define DMA_IFS_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Set */ |
| group-onsemi | 0:098463de4c5d | 548 | #define _DMA_IFS_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */ |
| group-onsemi | 0:098463de4c5d | 549 | #define _DMA_IFS_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */ |
| group-onsemi | 0:098463de4c5d | 550 | #define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */ |
| group-onsemi | 0:098463de4c5d | 551 | #define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFS */ |
| group-onsemi | 0:098463de4c5d | 552 | #define DMA_IFS_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Set */ |
| group-onsemi | 0:098463de4c5d | 553 | #define _DMA_IFS_ERR_SHIFT 31 /**< Shift value for DMA_ERR */ |
| group-onsemi | 0:098463de4c5d | 554 | #define _DMA_IFS_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */ |
| group-onsemi | 0:098463de4c5d | 555 | #define _DMA_IFS_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */ |
| group-onsemi | 0:098463de4c5d | 556 | #define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFS */ |
| group-onsemi | 0:098463de4c5d | 557 | |
| group-onsemi | 0:098463de4c5d | 558 | /* Bit fields for DMA IFC */ |
| group-onsemi | 0:098463de4c5d | 559 | #define _DMA_IFC_RESETVALUE 0x00000000UL /**< Default value for DMA_IFC */ |
| group-onsemi | 0:098463de4c5d | 560 | #define _DMA_IFC_MASK 0x8000000FUL /**< Mask for DMA_IFC */ |
| group-onsemi | 0:098463de4c5d | 561 | #define DMA_IFC_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Clear */ |
| group-onsemi | 0:098463de4c5d | 562 | #define _DMA_IFC_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */ |
| group-onsemi | 0:098463de4c5d | 563 | #define _DMA_IFC_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */ |
| group-onsemi | 0:098463de4c5d | 564 | #define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */ |
| group-onsemi | 0:098463de4c5d | 565 | #define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFC */ |
| group-onsemi | 0:098463de4c5d | 566 | #define DMA_IFC_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Clear */ |
| group-onsemi | 0:098463de4c5d | 567 | #define _DMA_IFC_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */ |
| group-onsemi | 0:098463de4c5d | 568 | #define _DMA_IFC_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */ |
| group-onsemi | 0:098463de4c5d | 569 | #define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */ |
| group-onsemi | 0:098463de4c5d | 570 | #define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFC */ |
| group-onsemi | 0:098463de4c5d | 571 | #define DMA_IFC_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Clear */ |
| group-onsemi | 0:098463de4c5d | 572 | #define _DMA_IFC_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */ |
| group-onsemi | 0:098463de4c5d | 573 | #define _DMA_IFC_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */ |
| group-onsemi | 0:098463de4c5d | 574 | #define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */ |
| group-onsemi | 0:098463de4c5d | 575 | #define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFC */ |
| group-onsemi | 0:098463de4c5d | 576 | #define DMA_IFC_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Clear */ |
| group-onsemi | 0:098463de4c5d | 577 | #define _DMA_IFC_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */ |
| group-onsemi | 0:098463de4c5d | 578 | #define _DMA_IFC_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */ |
| group-onsemi | 0:098463de4c5d | 579 | #define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */ |
| group-onsemi | 0:098463de4c5d | 580 | #define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFC */ |
| group-onsemi | 0:098463de4c5d | 581 | #define DMA_IFC_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Clear */ |
| group-onsemi | 0:098463de4c5d | 582 | #define _DMA_IFC_ERR_SHIFT 31 /**< Shift value for DMA_ERR */ |
| group-onsemi | 0:098463de4c5d | 583 | #define _DMA_IFC_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */ |
| group-onsemi | 0:098463de4c5d | 584 | #define _DMA_IFC_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */ |
| group-onsemi | 0:098463de4c5d | 585 | #define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFC */ |
| group-onsemi | 0:098463de4c5d | 586 | |
| group-onsemi | 0:098463de4c5d | 587 | /* Bit fields for DMA IEN */ |
| group-onsemi | 0:098463de4c5d | 588 | #define _DMA_IEN_RESETVALUE 0x00000000UL /**< Default value for DMA_IEN */ |
| group-onsemi | 0:098463de4c5d | 589 | #define _DMA_IEN_MASK 0x8000000FUL /**< Mask for DMA_IEN */ |
| group-onsemi | 0:098463de4c5d | 590 | #define DMA_IEN_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Enable */ |
| group-onsemi | 0:098463de4c5d | 591 | #define _DMA_IEN_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */ |
| group-onsemi | 0:098463de4c5d | 592 | #define _DMA_IEN_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */ |
| group-onsemi | 0:098463de4c5d | 593 | #define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */ |
| group-onsemi | 0:098463de4c5d | 594 | #define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IEN */ |
| group-onsemi | 0:098463de4c5d | 595 | #define DMA_IEN_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Enable */ |
| group-onsemi | 0:098463de4c5d | 596 | #define _DMA_IEN_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */ |
| group-onsemi | 0:098463de4c5d | 597 | #define _DMA_IEN_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */ |
| group-onsemi | 0:098463de4c5d | 598 | #define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */ |
| group-onsemi | 0:098463de4c5d | 599 | #define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IEN */ |
| group-onsemi | 0:098463de4c5d | 600 | #define DMA_IEN_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Enable */ |
| group-onsemi | 0:098463de4c5d | 601 | #define _DMA_IEN_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */ |
| group-onsemi | 0:098463de4c5d | 602 | #define _DMA_IEN_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */ |
| group-onsemi | 0:098463de4c5d | 603 | #define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */ |
| group-onsemi | 0:098463de4c5d | 604 | #define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IEN */ |
| group-onsemi | 0:098463de4c5d | 605 | #define DMA_IEN_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Enable */ |
| group-onsemi | 0:098463de4c5d | 606 | #define _DMA_IEN_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */ |
| group-onsemi | 0:098463de4c5d | 607 | #define _DMA_IEN_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */ |
| group-onsemi | 0:098463de4c5d | 608 | #define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */ |
| group-onsemi | 0:098463de4c5d | 609 | #define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IEN */ |
| group-onsemi | 0:098463de4c5d | 610 | #define DMA_IEN_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Enable */ |
| group-onsemi | 0:098463de4c5d | 611 | #define _DMA_IEN_ERR_SHIFT 31 /**< Shift value for DMA_ERR */ |
| group-onsemi | 0:098463de4c5d | 612 | #define _DMA_IEN_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */ |
| group-onsemi | 0:098463de4c5d | 613 | #define _DMA_IEN_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */ |
| group-onsemi | 0:098463de4c5d | 614 | #define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IEN */ |
| group-onsemi | 0:098463de4c5d | 615 | |
| group-onsemi | 0:098463de4c5d | 616 | /* Bit fields for DMA CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 617 | #define _DMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 618 | #define _DMA_CH_CTRL_MASK 0x003F000FUL /**< Mask for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 619 | #define _DMA_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for DMA_SIGSEL */ |
| group-onsemi | 0:098463de4c5d | 620 | #define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL /**< Bit mask for DMA_SIGSEL */ |
| group-onsemi | 0:098463de4c5d | 621 | #define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 622 | #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 623 | #define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 624 | #define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 625 | #define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 626 | #define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 627 | #define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 628 | #define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL /**< Mode AESDATAWR for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 629 | #define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 630 | #define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 631 | #define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 632 | #define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 633 | #define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 634 | #define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 635 | #define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL /**< Mode AESXORDATAWR for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 636 | #define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 637 | #define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 638 | #define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 639 | #define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 640 | #define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL /**< Mode AESDATARD for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 641 | #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 642 | #define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 643 | #define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 644 | #define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL /**< Mode AESKEYWR for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 645 | #define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 646 | #define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 647 | #define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 648 | #define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 649 | #define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 650 | #define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 651 | #define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 652 | #define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 653 | #define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0) /**< Shifted mode AESDATAWR for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 654 | #define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 655 | #define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 656 | #define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 657 | #define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 658 | #define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 659 | #define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 660 | #define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0) /**< Shifted mode AESXORDATAWR for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 661 | #define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 662 | #define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 663 | #define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 664 | #define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 665 | #define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0) /**< Shifted mode AESDATARD for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 666 | #define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 667 | #define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 668 | #define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 669 | #define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0) /**< Shifted mode AESKEYWR for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 670 | #define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 671 | #define _DMA_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for DMA_SOURCESEL */ |
| group-onsemi | 0:098463de4c5d | 672 | #define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for DMA_SOURCESEL */ |
| group-onsemi | 0:098463de4c5d | 673 | #define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 674 | #define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 675 | #define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 676 | #define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 677 | #define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 678 | #define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 679 | #define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 680 | #define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 681 | #define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL /**< Mode AES for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 682 | #define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 683 | #define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 684 | #define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 685 | #define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 686 | #define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 687 | #define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 688 | #define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 689 | #define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 690 | #define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16) /**< Shifted mode AES for DMA_CH_CTRL */ |
| group-onsemi | 0:098463de4c5d | 691 | |
| group-onsemi | 0:098463de4c5d | 692 | /** @} End of group EFM32ZG_DMA */ |
| group-onsemi | 0:098463de4c5d | 693 | /** @} End of group Parts */ |
| group-onsemi | 0:098463de4c5d | 694 |