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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_NORDIC/TARGET_MCU_NRF51822/spi_api.c@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 * Copyright (c) 2013 Nordic Semiconductor
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Licensed under the Apache License, Version 2.0 (the "License");
group-onsemi 0:098463de4c5d 5 * you may not use this file except in compliance with the License.
group-onsemi 0:098463de4c5d 6 * You may obtain a copy of the License at
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * http://www.apache.org/licenses/LICENSE-2.0
group-onsemi 0:098463de4c5d 9 *
group-onsemi 0:098463de4c5d 10 * Unless required by applicable law or agreed to in writing, software
group-onsemi 0:098463de4c5d 11 * distributed under the License is distributed on an "AS IS" BASIS,
group-onsemi 0:098463de4c5d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
group-onsemi 0:098463de4c5d 13 * See the License for the specific language governing permissions and
group-onsemi 0:098463de4c5d 14 * limitations under the License.
group-onsemi 0:098463de4c5d 15 */
group-onsemi 0:098463de4c5d 16 //#include <math.h>
group-onsemi 0:098463de4c5d 17 #include "mbed_assert.h"
group-onsemi 0:098463de4c5d 18 #include "spi_api.h"
group-onsemi 0:098463de4c5d 19 #include "cmsis.h"
group-onsemi 0:098463de4c5d 20 #include "pinmap.h"
group-onsemi 0:098463de4c5d 21 #include "mbed_error.h"
group-onsemi 0:098463de4c5d 22
group-onsemi 0:098463de4c5d 23 #define SPIS_MESSAGE_SIZE 1
group-onsemi 0:098463de4c5d 24 volatile uint8_t m_tx_buf[SPIS_MESSAGE_SIZE] = {0};
group-onsemi 0:098463de4c5d 25 volatile uint8_t m_rx_buf[SPIS_MESSAGE_SIZE] = {0};
group-onsemi 0:098463de4c5d 26
group-onsemi 0:098463de4c5d 27 // nRF51822's I2C_0 and SPI_0 (I2C_1, SPI_1 and SPIS1) share the same address.
group-onsemi 0:098463de4c5d 28 // They can't be used at the same time. So we use two global variable to track the usage.
group-onsemi 0:098463de4c5d 29 // See nRF51822 address information at nRF51822_PS v2.0.pdf - Table 15 Peripheral instance reference
group-onsemi 0:098463de4c5d 30 extern volatile i2c_spi_peripheral_t i2c0_spi0_peripheral; // from i2c_api.c
group-onsemi 0:098463de4c5d 31 extern volatile i2c_spi_peripheral_t i2c1_spi1_peripheral;
group-onsemi 0:098463de4c5d 32
group-onsemi 0:098463de4c5d 33 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
group-onsemi 0:098463de4c5d 34 {
group-onsemi 0:098463de4c5d 35 SPIName spi = SPI_0;
group-onsemi 0:098463de4c5d 36
group-onsemi 0:098463de4c5d 37 if (ssel == NC && i2c0_spi0_peripheral.usage == I2C_SPI_PERIPHERAL_FOR_SPI &&
group-onsemi 0:098463de4c5d 38 i2c0_spi0_peripheral.sda_mosi == (uint8_t)mosi &&
group-onsemi 0:098463de4c5d 39 i2c0_spi0_peripheral.scl_miso == (uint8_t)miso &&
group-onsemi 0:098463de4c5d 40 i2c0_spi0_peripheral.sclk == (uint8_t)sclk) {
group-onsemi 0:098463de4c5d 41 // The SPI with the same pins is already initialized
group-onsemi 0:098463de4c5d 42 spi = SPI_0;
group-onsemi 0:098463de4c5d 43 obj->peripheral = 0x1;
group-onsemi 0:098463de4c5d 44 } else if (ssel == NC && i2c1_spi1_peripheral.usage == I2C_SPI_PERIPHERAL_FOR_SPI &&
group-onsemi 0:098463de4c5d 45 i2c1_spi1_peripheral.sda_mosi == (uint8_t)mosi &&
group-onsemi 0:098463de4c5d 46 i2c1_spi1_peripheral.scl_miso == (uint8_t)miso &&
group-onsemi 0:098463de4c5d 47 i2c1_spi1_peripheral.sclk == (uint8_t)sclk) {
group-onsemi 0:098463de4c5d 48 // The SPI with the same pins is already initialized
group-onsemi 0:098463de4c5d 49 spi = SPI_1;
group-onsemi 0:098463de4c5d 50 obj->peripheral = 0x2;
group-onsemi 0:098463de4c5d 51 } else if (i2c1_spi1_peripheral.usage == 0) {
group-onsemi 0:098463de4c5d 52 i2c1_spi1_peripheral.usage = I2C_SPI_PERIPHERAL_FOR_SPI;
group-onsemi 0:098463de4c5d 53 i2c1_spi1_peripheral.sda_mosi = (uint8_t)mosi;
group-onsemi 0:098463de4c5d 54 i2c1_spi1_peripheral.scl_miso = (uint8_t)miso;
group-onsemi 0:098463de4c5d 55 i2c1_spi1_peripheral.sclk = (uint8_t)sclk;
group-onsemi 0:098463de4c5d 56
group-onsemi 0:098463de4c5d 57 spi = SPI_1;
group-onsemi 0:098463de4c5d 58 obj->peripheral = 0x2;
group-onsemi 0:098463de4c5d 59 } else if (i2c0_spi0_peripheral.usage == 0) {
group-onsemi 0:098463de4c5d 60 i2c0_spi0_peripheral.usage = I2C_SPI_PERIPHERAL_FOR_SPI;
group-onsemi 0:098463de4c5d 61 i2c0_spi0_peripheral.sda_mosi = (uint8_t)mosi;
group-onsemi 0:098463de4c5d 62 i2c0_spi0_peripheral.scl_miso = (uint8_t)miso;
group-onsemi 0:098463de4c5d 63 i2c0_spi0_peripheral.sclk = (uint8_t)sclk;
group-onsemi 0:098463de4c5d 64
group-onsemi 0:098463de4c5d 65 spi = SPI_0;
group-onsemi 0:098463de4c5d 66 obj->peripheral = 0x1;
group-onsemi 0:098463de4c5d 67 } else {
group-onsemi 0:098463de4c5d 68 // No available peripheral
group-onsemi 0:098463de4c5d 69 error("No available SPI");
group-onsemi 0:098463de4c5d 70 }
group-onsemi 0:098463de4c5d 71
group-onsemi 0:098463de4c5d 72 if (ssel==NC) {
group-onsemi 0:098463de4c5d 73 obj->spi = (NRF_SPI_Type *)spi;
group-onsemi 0:098463de4c5d 74 obj->spis = (NRF_SPIS_Type *)NC;
group-onsemi 0:098463de4c5d 75 } else {
group-onsemi 0:098463de4c5d 76 obj->spi = (NRF_SPI_Type *)NC;
group-onsemi 0:098463de4c5d 77 obj->spis = (NRF_SPIS_Type *)spi;
group-onsemi 0:098463de4c5d 78 }
group-onsemi 0:098463de4c5d 79
group-onsemi 0:098463de4c5d 80 // pin out the spi pins
group-onsemi 0:098463de4c5d 81 if (ssel != NC) { //slave
group-onsemi 0:098463de4c5d 82 obj->spis->POWER = 0;
group-onsemi 0:098463de4c5d 83 obj->spis->POWER = 1;
group-onsemi 0:098463de4c5d 84
group-onsemi 0:098463de4c5d 85 NRF_GPIO->PIN_CNF[mosi] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
group-onsemi 0:098463de4c5d 86 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
group-onsemi 0:098463de4c5d 87 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
group-onsemi 0:098463de4c5d 88 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
group-onsemi 0:098463de4c5d 89 | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
group-onsemi 0:098463de4c5d 90 NRF_GPIO->PIN_CNF[miso] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
group-onsemi 0:098463de4c5d 91 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
group-onsemi 0:098463de4c5d 92 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
group-onsemi 0:098463de4c5d 93 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
group-onsemi 0:098463de4c5d 94 | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
group-onsemi 0:098463de4c5d 95 NRF_GPIO->PIN_CNF[sclk] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
group-onsemi 0:098463de4c5d 96 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
group-onsemi 0:098463de4c5d 97 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
group-onsemi 0:098463de4c5d 98 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
group-onsemi 0:098463de4c5d 99 | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
group-onsemi 0:098463de4c5d 100 NRF_GPIO->PIN_CNF[ssel] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
group-onsemi 0:098463de4c5d 101 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
group-onsemi 0:098463de4c5d 102 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
group-onsemi 0:098463de4c5d 103 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
group-onsemi 0:098463de4c5d 104 | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
group-onsemi 0:098463de4c5d 105
group-onsemi 0:098463de4c5d 106 obj->spis->PSELMOSI = mosi;
group-onsemi 0:098463de4c5d 107 obj->spis->PSELMISO = miso;
group-onsemi 0:098463de4c5d 108 obj->spis->PSELSCK = sclk;
group-onsemi 0:098463de4c5d 109 obj->spis->PSELCSN = ssel;
group-onsemi 0:098463de4c5d 110
group-onsemi 0:098463de4c5d 111 obj->spis->EVENTS_END = 0;
group-onsemi 0:098463de4c5d 112 obj->spis->EVENTS_ACQUIRED = 0;
group-onsemi 0:098463de4c5d 113 obj->spis->MAXRX = SPIS_MESSAGE_SIZE;
group-onsemi 0:098463de4c5d 114 obj->spis->MAXTX = SPIS_MESSAGE_SIZE;
group-onsemi 0:098463de4c5d 115 obj->spis->TXDPTR = (uint32_t)&m_tx_buf[0];
group-onsemi 0:098463de4c5d 116 obj->spis->RXDPTR = (uint32_t)&m_rx_buf[0];
group-onsemi 0:098463de4c5d 117 obj->spis->SHORTS = (SPIS_SHORTS_END_ACQUIRE_Enabled << SPIS_SHORTS_END_ACQUIRE_Pos);
group-onsemi 0:098463de4c5d 118
group-onsemi 0:098463de4c5d 119 spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
group-onsemi 0:098463de4c5d 120 } else { //master
group-onsemi 0:098463de4c5d 121 obj->spi->POWER = 0;
group-onsemi 0:098463de4c5d 122 obj->spi->POWER = 1;
group-onsemi 0:098463de4c5d 123
group-onsemi 0:098463de4c5d 124 //NRF_GPIO->DIR |= (1<<mosi);
group-onsemi 0:098463de4c5d 125 NRF_GPIO->PIN_CNF[mosi] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
group-onsemi 0:098463de4c5d 126 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
group-onsemi 0:098463de4c5d 127 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
group-onsemi 0:098463de4c5d 128 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
group-onsemi 0:098463de4c5d 129 | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
group-onsemi 0:098463de4c5d 130 obj->spi->PSELMOSI = mosi;
group-onsemi 0:098463de4c5d 131
group-onsemi 0:098463de4c5d 132 NRF_GPIO->PIN_CNF[sclk] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
group-onsemi 0:098463de4c5d 133 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
group-onsemi 0:098463de4c5d 134 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
group-onsemi 0:098463de4c5d 135 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
group-onsemi 0:098463de4c5d 136 | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
group-onsemi 0:098463de4c5d 137 obj->spi->PSELSCK = sclk;
group-onsemi 0:098463de4c5d 138
group-onsemi 0:098463de4c5d 139 //NRF_GPIO->DIR &= ~(1<<miso);
group-onsemi 0:098463de4c5d 140 NRF_GPIO->PIN_CNF[miso] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
group-onsemi 0:098463de4c5d 141 | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
group-onsemi 0:098463de4c5d 142 | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
group-onsemi 0:098463de4c5d 143 | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
group-onsemi 0:098463de4c5d 144 | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
group-onsemi 0:098463de4c5d 145
group-onsemi 0:098463de4c5d 146 obj->spi->PSELMISO = miso;
group-onsemi 0:098463de4c5d 147
group-onsemi 0:098463de4c5d 148 obj->spi->EVENTS_READY = 0U;
group-onsemi 0:098463de4c5d 149
group-onsemi 0:098463de4c5d 150 spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
group-onsemi 0:098463de4c5d 151 spi_frequency(obj, 1000000);
group-onsemi 0:098463de4c5d 152 }
group-onsemi 0:098463de4c5d 153 }
group-onsemi 0:098463de4c5d 154
group-onsemi 0:098463de4c5d 155 void spi_free(spi_t *obj)
group-onsemi 0:098463de4c5d 156 {
group-onsemi 0:098463de4c5d 157 }
group-onsemi 0:098463de4c5d 158
group-onsemi 0:098463de4c5d 159 static inline void spi_disable(spi_t *obj, int slave)
group-onsemi 0:098463de4c5d 160 {
group-onsemi 0:098463de4c5d 161 if (slave) {
group-onsemi 0:098463de4c5d 162 obj->spis->ENABLE = (SPIS_ENABLE_ENABLE_Disabled << SPIS_ENABLE_ENABLE_Pos);
group-onsemi 0:098463de4c5d 163 } else {
group-onsemi 0:098463de4c5d 164 obj->spi->ENABLE = (SPI_ENABLE_ENABLE_Disabled << SPI_ENABLE_ENABLE_Pos);
group-onsemi 0:098463de4c5d 165 }
group-onsemi 0:098463de4c5d 166 }
group-onsemi 0:098463de4c5d 167
group-onsemi 0:098463de4c5d 168 static inline void spi_enable(spi_t *obj, int slave)
group-onsemi 0:098463de4c5d 169 {
group-onsemi 0:098463de4c5d 170 if (slave) {
group-onsemi 0:098463de4c5d 171 obj->spis->ENABLE = (SPIS_ENABLE_ENABLE_Enabled << SPIS_ENABLE_ENABLE_Pos);
group-onsemi 0:098463de4c5d 172 } else {
group-onsemi 0:098463de4c5d 173 obj->spi->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos);
group-onsemi 0:098463de4c5d 174 }
group-onsemi 0:098463de4c5d 175 }
group-onsemi 0:098463de4c5d 176
group-onsemi 0:098463de4c5d 177 void spi_format(spi_t *obj, int bits, int mode, int slave)
group-onsemi 0:098463de4c5d 178 {
group-onsemi 0:098463de4c5d 179 uint32_t config_mode = 0;
group-onsemi 0:098463de4c5d 180 spi_disable(obj, slave);
group-onsemi 0:098463de4c5d 181
group-onsemi 0:098463de4c5d 182 if (bits != 8) {
group-onsemi 0:098463de4c5d 183 error("Only 8bits SPI supported");
group-onsemi 0:098463de4c5d 184 }
group-onsemi 0:098463de4c5d 185
group-onsemi 0:098463de4c5d 186 switch (mode) {
group-onsemi 0:098463de4c5d 187 case 0:
group-onsemi 0:098463de4c5d 188 config_mode = (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
group-onsemi 0:098463de4c5d 189 break;
group-onsemi 0:098463de4c5d 190 case 1:
group-onsemi 0:098463de4c5d 191 config_mode = (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos);
group-onsemi 0:098463de4c5d 192 break;
group-onsemi 0:098463de4c5d 193 case 2:
group-onsemi 0:098463de4c5d 194 config_mode = (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
group-onsemi 0:098463de4c5d 195 break;
group-onsemi 0:098463de4c5d 196 case 3:
group-onsemi 0:098463de4c5d 197 config_mode = (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos);
group-onsemi 0:098463de4c5d 198 break;
group-onsemi 0:098463de4c5d 199 default:
group-onsemi 0:098463de4c5d 200 error("SPI format error");
group-onsemi 0:098463de4c5d 201 break;
group-onsemi 0:098463de4c5d 202 }
group-onsemi 0:098463de4c5d 203 //default to msb first
group-onsemi 0:098463de4c5d 204 if (slave) {
group-onsemi 0:098463de4c5d 205 obj->spis->CONFIG = (config_mode | (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos));
group-onsemi 0:098463de4c5d 206 } else {
group-onsemi 0:098463de4c5d 207 obj->spi->CONFIG = (config_mode | (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos));
group-onsemi 0:098463de4c5d 208 }
group-onsemi 0:098463de4c5d 209
group-onsemi 0:098463de4c5d 210 spi_enable(obj, slave);
group-onsemi 0:098463de4c5d 211 }
group-onsemi 0:098463de4c5d 212
group-onsemi 0:098463de4c5d 213 void spi_frequency(spi_t *obj, int hz)
group-onsemi 0:098463de4c5d 214 {
group-onsemi 0:098463de4c5d 215 if ((int)obj->spi==NC) {
group-onsemi 0:098463de4c5d 216 return;
group-onsemi 0:098463de4c5d 217 }
group-onsemi 0:098463de4c5d 218 spi_disable(obj, 0);
group-onsemi 0:098463de4c5d 219
group-onsemi 0:098463de4c5d 220 if (hz<250000) { //125Kbps
group-onsemi 0:098463de4c5d 221 obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_K125;
group-onsemi 0:098463de4c5d 222 } else if (hz<500000) { //250Kbps
group-onsemi 0:098463de4c5d 223 obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_K250;
group-onsemi 0:098463de4c5d 224 } else if (hz<1000000) { //500Kbps
group-onsemi 0:098463de4c5d 225 obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_K500;
group-onsemi 0:098463de4c5d 226 } else if (hz<2000000) { //1Mbps
group-onsemi 0:098463de4c5d 227 obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_M1;
group-onsemi 0:098463de4c5d 228 } else if (hz<4000000) { //2Mbps
group-onsemi 0:098463de4c5d 229 obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_M2;
group-onsemi 0:098463de4c5d 230 } else if (hz<8000000) { //4Mbps
group-onsemi 0:098463de4c5d 231 obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_M4;
group-onsemi 0:098463de4c5d 232 } else { //8Mbps
group-onsemi 0:098463de4c5d 233 obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_M8;
group-onsemi 0:098463de4c5d 234 }
group-onsemi 0:098463de4c5d 235
group-onsemi 0:098463de4c5d 236 spi_enable(obj, 0);
group-onsemi 0:098463de4c5d 237 }
group-onsemi 0:098463de4c5d 238
group-onsemi 0:098463de4c5d 239 static inline int spi_readable(spi_t *obj)
group-onsemi 0:098463de4c5d 240 {
group-onsemi 0:098463de4c5d 241 return (obj->spi->EVENTS_READY == 1);
group-onsemi 0:098463de4c5d 242 }
group-onsemi 0:098463de4c5d 243
group-onsemi 0:098463de4c5d 244 static inline int spi_writeable(spi_t *obj)
group-onsemi 0:098463de4c5d 245 {
group-onsemi 0:098463de4c5d 246 return (obj->spi->EVENTS_READY == 0);
group-onsemi 0:098463de4c5d 247 }
group-onsemi 0:098463de4c5d 248
group-onsemi 0:098463de4c5d 249 static inline int spi_read(spi_t *obj)
group-onsemi 0:098463de4c5d 250 {
group-onsemi 0:098463de4c5d 251 while (!spi_readable(obj)) {
group-onsemi 0:098463de4c5d 252 }
group-onsemi 0:098463de4c5d 253
group-onsemi 0:098463de4c5d 254 obj->spi->EVENTS_READY = 0;
group-onsemi 0:098463de4c5d 255 return (int)obj->spi->RXD;
group-onsemi 0:098463de4c5d 256 }
group-onsemi 0:098463de4c5d 257
group-onsemi 0:098463de4c5d 258 int spi_master_write(spi_t *obj, int value)
group-onsemi 0:098463de4c5d 259 {
group-onsemi 0:098463de4c5d 260 while (!spi_writeable(obj)) {
group-onsemi 0:098463de4c5d 261 }
group-onsemi 0:098463de4c5d 262 obj->spi->TXD = (uint32_t)value;
group-onsemi 0:098463de4c5d 263 return spi_read(obj);
group-onsemi 0:098463de4c5d 264 }
group-onsemi 0:098463de4c5d 265
group-onsemi 0:098463de4c5d 266 //static inline int spis_writeable(spi_t *obj) {
group-onsemi 0:098463de4c5d 267 // return (obj->spis->EVENTS_ACQUIRED==1);
group-onsemi 0:098463de4c5d 268 //}
group-onsemi 0:098463de4c5d 269
group-onsemi 0:098463de4c5d 270 int spi_slave_receive(spi_t *obj)
group-onsemi 0:098463de4c5d 271 {
group-onsemi 0:098463de4c5d 272 return obj->spis->EVENTS_END;
group-onsemi 0:098463de4c5d 273 }
group-onsemi 0:098463de4c5d 274
group-onsemi 0:098463de4c5d 275 int spi_slave_read(spi_t *obj)
group-onsemi 0:098463de4c5d 276 {
group-onsemi 0:098463de4c5d 277 return m_rx_buf[0];
group-onsemi 0:098463de4c5d 278 }
group-onsemi 0:098463de4c5d 279
group-onsemi 0:098463de4c5d 280 void spi_slave_write(spi_t *obj, int value)
group-onsemi 0:098463de4c5d 281 {
group-onsemi 0:098463de4c5d 282 m_tx_buf[0] = value & 0xFF;
group-onsemi 0:098463de4c5d 283 obj->spis->TASKS_RELEASE = 1;
group-onsemi 0:098463de4c5d 284 obj->spis->EVENTS_ACQUIRED = 0;
group-onsemi 0:098463de4c5d 285 obj->spis->EVENTS_END = 0;
group-onsemi 0:098463de4c5d 286 }