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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_ublox/TARGET_HI2110/device/system_hi2110.c@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 * Copyright (c) 2016 u-blox
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Licensed under the Apache License, Version 2.0 (the "License");
group-onsemi 0:098463de4c5d 5 * you may not use this file except in compliance with the License.
group-onsemi 0:098463de4c5d 6 * You may obtain a copy of the License at
group-onsemi 0:098463de4c5d 7 *
group-onsemi 0:098463de4c5d 8 * http://www.apache.org/licenses/LICENSE-2.0
group-onsemi 0:098463de4c5d 9 *
group-onsemi 0:098463de4c5d 10 * Unless required by applicable law or agreed to in writing, software
group-onsemi 0:098463de4c5d 11 * distributed under the License is distributed on an "AS IS" BASIS,
group-onsemi 0:098463de4c5d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
group-onsemi 0:098463de4c5d 13 * See the License for the specific language governing permissions and
group-onsemi 0:098463de4c5d 14 * limitations under the License.
group-onsemi 0:098463de4c5d 15 */
group-onsemi 0:098463de4c5d 16
group-onsemi 0:098463de4c5d 17 #include <stdint.h>
group-onsemi 0:098463de4c5d 18 #include <stdbool.h>
group-onsemi 0:098463de4c5d 19
group-onsemi 0:098463de4c5d 20 #include "system_hi2110.h"
group-onsemi 0:098463de4c5d 21 #include "cmsis.h"
group-onsemi 0:098463de4c5d 22
group-onsemi 0:098463de4c5d 23 /*lint ++flb "Enter library region" */
group-onsemi 0:098463de4c5d 24
group-onsemi 0:098463de4c5d 25 #define __SYSTEM_CLOCK (48000000UL)
group-onsemi 0:098463de4c5d 26
group-onsemi 0:098463de4c5d 27 #if defined ( __CC_ARM )
group-onsemi 0:098463de4c5d 28 uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
group-onsemi 0:098463de4c5d 29 #elif defined ( __ICCARM__ )
group-onsemi 0:098463de4c5d 30 __root uint32_t SystemCoreClock = __SYSTEM_CLOCK;
group-onsemi 0:098463de4c5d 31 #elif defined ( __GNUC__ )
group-onsemi 0:098463de4c5d 32 uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
group-onsemi 0:098463de4c5d 33 #endif
group-onsemi 0:098463de4c5d 34
group-onsemi 0:098463de4c5d 35 void SystemCoreClockUpdate(void)
group-onsemi 0:098463de4c5d 36 {
group-onsemi 0:098463de4c5d 37 SystemCoreClock = __SYSTEM_CLOCK;
group-onsemi 0:098463de4c5d 38 }
group-onsemi 0:098463de4c5d 39
group-onsemi 0:098463de4c5d 40 /* Restart the core if we're in an interrupt context to ensure a known state.
group-onsemi 0:098463de4c5d 41 * Also reset any PIOs and ensure interrupts are disabled. */
group-onsemi 0:098463de4c5d 42 void SystemInit(void)
group-onsemi 0:098463de4c5d 43 {
group-onsemi 0:098463de4c5d 44 uint32_t x = __get_xPSR();
group-onsemi 0:098463de4c5d 45
group-onsemi 0:098463de4c5d 46 /* Check for interrupt context and reboot needed. */
group-onsemi 0:098463de4c5d 47 if (x & 0x3f) {
group-onsemi 0:098463de4c5d 48 /* Processor is in an interrupt context, reset the core by triggering
group-onsemi 0:098463de4c5d 49 * the reset vector using the SYSRESETREQ bit in the AIRCR register */
group-onsemi 0:098463de4c5d 50 x = SCB->AIRCR;
group-onsemi 0:098463de4c5d 51 x &= 0xffff; /* Mask out the top 16 bits */
group-onsemi 0:098463de4c5d 52 x |= 0x05fa0000; /* Must write with this value for the write to take effect */
group-onsemi 0:098463de4c5d 53 x |= 0x04; /* Set the SYSRESETREQ bit */
group-onsemi 0:098463de4c5d 54 SCB->AIRCR = x; /* Reset the core */
group-onsemi 0:098463de4c5d 55 }
group-onsemi 0:098463de4c5d 56
group-onsemi 0:098463de4c5d 57 /* Release claim on any pins */
group-onsemi 0:098463de4c5d 58 PIO_FUNC0_BITCLR = 0xFFFFFFFF;
group-onsemi 0:098463de4c5d 59 PIO_FUNC1_BITCLR = 0xFFFFFFFF;
group-onsemi 0:098463de4c5d 60 PIO_FUNC2_BITCLR = 0xFFFFFFFF;
group-onsemi 0:098463de4c5d 61 PIO_FUNC3_BITCLR = 0xFFFFFFFF;
group-onsemi 0:098463de4c5d 62 PIO_FUNC4_BITCLR = 0xFFFFFFFF;
group-onsemi 0:098463de4c5d 63
group-onsemi 0:098463de4c5d 64 /* Disable all IRQ interrupts */
group-onsemi 0:098463de4c5d 65 NVIC->ICER[0] = 0xffffffff;
group-onsemi 0:098463de4c5d 66
group-onsemi 0:098463de4c5d 67 /* Ensure interrupts are enabled */
group-onsemi 0:098463de4c5d 68 __set_PRIMASK(0);
group-onsemi 0:098463de4c5d 69
group-onsemi 0:098463de4c5d 70 /* Allow sleep */
group-onsemi 0:098463de4c5d 71 SystemAllowSleep(true);
group-onsemi 0:098463de4c5d 72 }
group-onsemi 0:098463de4c5d 73
group-onsemi 0:098463de4c5d 74 void SystemAllowSleep(bool sleepAllowed)
group-onsemi 0:098463de4c5d 75 {
group-onsemi 0:098463de4c5d 76 if (sleepAllowed) {
group-onsemi 0:098463de4c5d 77 /* Set deep sleep, though not on exit */
group-onsemi 0:098463de4c5d 78 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
group-onsemi 0:098463de4c5d 79 SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
group-onsemi 0:098463de4c5d 80 } else {
group-onsemi 0:098463de4c5d 81 /* Unset deep sleep */
group-onsemi 0:098463de4c5d 82 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
group-onsemi 0:098463de4c5d 83 }
group-onsemi 0:098463de4c5d 84 }
group-onsemi 0:098463de4c5d 85
group-onsemi 0:098463de4c5d 86 /*lint --flb "Leave library region" */