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targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_dma.c@0:098463de4c5d, 2017-01-25 (annotated)
- Committer:
- group-onsemi
- Date:
- Wed Jan 25 20:34:15 2017 +0000
- Revision:
- 0:098463de4c5d
Initial commit
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| group-onsemi | 0:098463de4c5d | 1 | /** |
| group-onsemi | 0:098463de4c5d | 2 | ****************************************************************************** |
| group-onsemi | 0:098463de4c5d | 3 | * @file stm32l4xx_ll_dma.c |
| group-onsemi | 0:098463de4c5d | 4 | * @author MCD Application Team |
| group-onsemi | 0:098463de4c5d | 5 | * @version V1.5.1 |
| group-onsemi | 0:098463de4c5d | 6 | * @date 31-May-2016 |
| group-onsemi | 0:098463de4c5d | 7 | * @brief DMA LL module driver. |
| group-onsemi | 0:098463de4c5d | 8 | ****************************************************************************** |
| group-onsemi | 0:098463de4c5d | 9 | * @attention |
| group-onsemi | 0:098463de4c5d | 10 | * |
| group-onsemi | 0:098463de4c5d | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| group-onsemi | 0:098463de4c5d | 12 | * |
| group-onsemi | 0:098463de4c5d | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| group-onsemi | 0:098463de4c5d | 14 | * are permitted provided that the following conditions are met: |
| group-onsemi | 0:098463de4c5d | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| group-onsemi | 0:098463de4c5d | 16 | * this list of conditions and the following disclaimer. |
| group-onsemi | 0:098463de4c5d | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| group-onsemi | 0:098463de4c5d | 18 | * this list of conditions and the following disclaimer in the documentation |
| group-onsemi | 0:098463de4c5d | 19 | * and/or other materials provided with the distribution. |
| group-onsemi | 0:098463de4c5d | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| group-onsemi | 0:098463de4c5d | 21 | * may be used to endorse or promote products derived from this software |
| group-onsemi | 0:098463de4c5d | 22 | * without specific prior written permission. |
| group-onsemi | 0:098463de4c5d | 23 | * |
| group-onsemi | 0:098463de4c5d | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| group-onsemi | 0:098463de4c5d | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| group-onsemi | 0:098463de4c5d | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| group-onsemi | 0:098463de4c5d | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| group-onsemi | 0:098463de4c5d | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| group-onsemi | 0:098463de4c5d | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| group-onsemi | 0:098463de4c5d | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| group-onsemi | 0:098463de4c5d | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| group-onsemi | 0:098463de4c5d | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| group-onsemi | 0:098463de4c5d | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| group-onsemi | 0:098463de4c5d | 34 | * |
| group-onsemi | 0:098463de4c5d | 35 | ****************************************************************************** |
| group-onsemi | 0:098463de4c5d | 36 | */ |
| group-onsemi | 0:098463de4c5d | 37 | #if defined(USE_FULL_LL_DRIVER) |
| group-onsemi | 0:098463de4c5d | 38 | |
| group-onsemi | 0:098463de4c5d | 39 | /* Includes ------------------------------------------------------------------*/ |
| group-onsemi | 0:098463de4c5d | 40 | #include "stm32l4xx_ll_dma.h" |
| group-onsemi | 0:098463de4c5d | 41 | #include "stm32l4xx_ll_bus.h" |
| group-onsemi | 0:098463de4c5d | 42 | #ifdef USE_FULL_ASSERT |
| group-onsemi | 0:098463de4c5d | 43 | #include "stm32_assert.h" |
| group-onsemi | 0:098463de4c5d | 44 | #else |
| group-onsemi | 0:098463de4c5d | 45 | #define assert_param(expr) ((void)0U) |
| group-onsemi | 0:098463de4c5d | 46 | #endif |
| group-onsemi | 0:098463de4c5d | 47 | |
| group-onsemi | 0:098463de4c5d | 48 | /** @addtogroup STM32L4xx_LL_Driver |
| group-onsemi | 0:098463de4c5d | 49 | * @{ |
| group-onsemi | 0:098463de4c5d | 50 | */ |
| group-onsemi | 0:098463de4c5d | 51 | |
| group-onsemi | 0:098463de4c5d | 52 | #if defined (DMA1) || defined (DMA2) |
| group-onsemi | 0:098463de4c5d | 53 | |
| group-onsemi | 0:098463de4c5d | 54 | /** @defgroup DMA_LL DMA |
| group-onsemi | 0:098463de4c5d | 55 | * @{ |
| group-onsemi | 0:098463de4c5d | 56 | */ |
| group-onsemi | 0:098463de4c5d | 57 | |
| group-onsemi | 0:098463de4c5d | 58 | /* Private types -------------------------------------------------------------*/ |
| group-onsemi | 0:098463de4c5d | 59 | /* Private variables ---------------------------------------------------------*/ |
| group-onsemi | 0:098463de4c5d | 60 | /* Private constants ---------------------------------------------------------*/ |
| group-onsemi | 0:098463de4c5d | 61 | /* Private macros ------------------------------------------------------------*/ |
| group-onsemi | 0:098463de4c5d | 62 | /** @addtogroup DMA_LL_Private_Macros |
| group-onsemi | 0:098463de4c5d | 63 | * @{ |
| group-onsemi | 0:098463de4c5d | 64 | */ |
| group-onsemi | 0:098463de4c5d | 65 | #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \ |
| group-onsemi | 0:098463de4c5d | 66 | ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \ |
| group-onsemi | 0:098463de4c5d | 67 | ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY)) |
| group-onsemi | 0:098463de4c5d | 68 | |
| group-onsemi | 0:098463de4c5d | 69 | #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \ |
| group-onsemi | 0:098463de4c5d | 70 | ((__VALUE__) == LL_DMA_MODE_CIRCULAR)) |
| group-onsemi | 0:098463de4c5d | 71 | |
| group-onsemi | 0:098463de4c5d | 72 | #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \ |
| group-onsemi | 0:098463de4c5d | 73 | ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT)) |
| group-onsemi | 0:098463de4c5d | 74 | |
| group-onsemi | 0:098463de4c5d | 75 | #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \ |
| group-onsemi | 0:098463de4c5d | 76 | ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT)) |
| group-onsemi | 0:098463de4c5d | 77 | |
| group-onsemi | 0:098463de4c5d | 78 | #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \ |
| group-onsemi | 0:098463de4c5d | 79 | ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \ |
| group-onsemi | 0:098463de4c5d | 80 | ((__VALUE__) == LL_DMA_PDATAALIGN_WORD)) |
| group-onsemi | 0:098463de4c5d | 81 | |
| group-onsemi | 0:098463de4c5d | 82 | #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \ |
| group-onsemi | 0:098463de4c5d | 83 | ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \ |
| group-onsemi | 0:098463de4c5d | 84 | ((__VALUE__) == LL_DMA_MDATAALIGN_WORD)) |
| group-onsemi | 0:098463de4c5d | 85 | |
| group-onsemi | 0:098463de4c5d | 86 | #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= (uint32_t)0x0000FFFFU) |
| group-onsemi | 0:098463de4c5d | 87 | |
| group-onsemi | 0:098463de4c5d | 88 | #define IS_LL_DMA_PERIPHREQUEST(__VALUE__) (((__VALUE__) == LL_DMA_REQUEST_0) || \ |
| group-onsemi | 0:098463de4c5d | 89 | ((__VALUE__) == LL_DMA_REQUEST_1) || \ |
| group-onsemi | 0:098463de4c5d | 90 | ((__VALUE__) == LL_DMA_REQUEST_2) || \ |
| group-onsemi | 0:098463de4c5d | 91 | ((__VALUE__) == LL_DMA_REQUEST_3) || \ |
| group-onsemi | 0:098463de4c5d | 92 | ((__VALUE__) == LL_DMA_REQUEST_4) || \ |
| group-onsemi | 0:098463de4c5d | 93 | ((__VALUE__) == LL_DMA_REQUEST_5) || \ |
| group-onsemi | 0:098463de4c5d | 94 | ((__VALUE__) == LL_DMA_REQUEST_6) || \ |
| group-onsemi | 0:098463de4c5d | 95 | ((__VALUE__) == LL_DMA_REQUEST_7)) |
| group-onsemi | 0:098463de4c5d | 96 | |
| group-onsemi | 0:098463de4c5d | 97 | #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \ |
| group-onsemi | 0:098463de4c5d | 98 | ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \ |
| group-onsemi | 0:098463de4c5d | 99 | ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \ |
| group-onsemi | 0:098463de4c5d | 100 | ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH)) |
| group-onsemi | 0:098463de4c5d | 101 | |
| group-onsemi | 0:098463de4c5d | 102 | #if defined (DMA2) |
| group-onsemi | 0:098463de4c5d | 103 | #if defined (DMA2_Channel6) && defined (DMA2_Channel7) |
| group-onsemi | 0:098463de4c5d | 104 | #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ |
| group-onsemi | 0:098463de4c5d | 105 | (((CHANNEL) == LL_DMA_CHANNEL_1) || \ |
| group-onsemi | 0:098463de4c5d | 106 | ((CHANNEL) == LL_DMA_CHANNEL_2) || \ |
| group-onsemi | 0:098463de4c5d | 107 | ((CHANNEL) == LL_DMA_CHANNEL_3) || \ |
| group-onsemi | 0:098463de4c5d | 108 | ((CHANNEL) == LL_DMA_CHANNEL_4) || \ |
| group-onsemi | 0:098463de4c5d | 109 | ((CHANNEL) == LL_DMA_CHANNEL_5) || \ |
| group-onsemi | 0:098463de4c5d | 110 | ((CHANNEL) == LL_DMA_CHANNEL_6) || \ |
| group-onsemi | 0:098463de4c5d | 111 | ((CHANNEL) == LL_DMA_CHANNEL_7))) || \ |
| group-onsemi | 0:098463de4c5d | 112 | (((INSTANCE) == DMA2) && \ |
| group-onsemi | 0:098463de4c5d | 113 | (((CHANNEL) == LL_DMA_CHANNEL_1) || \ |
| group-onsemi | 0:098463de4c5d | 114 | ((CHANNEL) == LL_DMA_CHANNEL_2) || \ |
| group-onsemi | 0:098463de4c5d | 115 | ((CHANNEL) == LL_DMA_CHANNEL_3) || \ |
| group-onsemi | 0:098463de4c5d | 116 | ((CHANNEL) == LL_DMA_CHANNEL_4) || \ |
| group-onsemi | 0:098463de4c5d | 117 | ((CHANNEL) == LL_DMA_CHANNEL_5) || \ |
| group-onsemi | 0:098463de4c5d | 118 | ((CHANNEL) == LL_DMA_CHANNEL_6) || \ |
| group-onsemi | 0:098463de4c5d | 119 | ((CHANNEL) == LL_DMA_CHANNEL_7)))) |
| group-onsemi | 0:098463de4c5d | 120 | #else |
| group-onsemi | 0:098463de4c5d | 121 | #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ |
| group-onsemi | 0:098463de4c5d | 122 | (((CHANNEL) == LL_DMA_CHANNEL_1) || \ |
| group-onsemi | 0:098463de4c5d | 123 | ((CHANNEL) == LL_DMA_CHANNEL_2) || \ |
| group-onsemi | 0:098463de4c5d | 124 | ((CHANNEL) == LL_DMA_CHANNEL_3) || \ |
| group-onsemi | 0:098463de4c5d | 125 | ((CHANNEL) == LL_DMA_CHANNEL_4) || \ |
| group-onsemi | 0:098463de4c5d | 126 | ((CHANNEL) == LL_DMA_CHANNEL_5) || \ |
| group-onsemi | 0:098463de4c5d | 127 | ((CHANNEL) == LL_DMA_CHANNEL_6) || \ |
| group-onsemi | 0:098463de4c5d | 128 | ((CHANNEL) == LL_DMA_CHANNEL_7))) || \ |
| group-onsemi | 0:098463de4c5d | 129 | (((INSTANCE) == DMA2) && \ |
| group-onsemi | 0:098463de4c5d | 130 | (((CHANNEL) == LL_DMA_CHANNEL_1) || \ |
| group-onsemi | 0:098463de4c5d | 131 | ((CHANNEL) == LL_DMA_CHANNEL_2) || \ |
| group-onsemi | 0:098463de4c5d | 132 | ((CHANNEL) == LL_DMA_CHANNEL_3) || \ |
| group-onsemi | 0:098463de4c5d | 133 | ((CHANNEL) == LL_DMA_CHANNEL_4) || \ |
| group-onsemi | 0:098463de4c5d | 134 | ((CHANNEL) == LL_DMA_CHANNEL_5)))) |
| group-onsemi | 0:098463de4c5d | 135 | #endif |
| group-onsemi | 0:098463de4c5d | 136 | #else |
| group-onsemi | 0:098463de4c5d | 137 | #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ |
| group-onsemi | 0:098463de4c5d | 138 | (((CHANNEL) == LL_DMA_CHANNEL_1)|| \ |
| group-onsemi | 0:098463de4c5d | 139 | ((CHANNEL) == LL_DMA_CHANNEL_2) || \ |
| group-onsemi | 0:098463de4c5d | 140 | ((CHANNEL) == LL_DMA_CHANNEL_3) || \ |
| group-onsemi | 0:098463de4c5d | 141 | ((CHANNEL) == LL_DMA_CHANNEL_4) || \ |
| group-onsemi | 0:098463de4c5d | 142 | ((CHANNEL) == LL_DMA_CHANNEL_5) || \ |
| group-onsemi | 0:098463de4c5d | 143 | ((CHANNEL) == LL_DMA_CHANNEL_6) || \ |
| group-onsemi | 0:098463de4c5d | 144 | ((CHANNEL) == LL_DMA_CHANNEL_7)))) |
| group-onsemi | 0:098463de4c5d | 145 | #endif |
| group-onsemi | 0:098463de4c5d | 146 | /** |
| group-onsemi | 0:098463de4c5d | 147 | * @} |
| group-onsemi | 0:098463de4c5d | 148 | */ |
| group-onsemi | 0:098463de4c5d | 149 | |
| group-onsemi | 0:098463de4c5d | 150 | /* Private function prototypes -----------------------------------------------*/ |
| group-onsemi | 0:098463de4c5d | 151 | |
| group-onsemi | 0:098463de4c5d | 152 | /* Exported functions --------------------------------------------------------*/ |
| group-onsemi | 0:098463de4c5d | 153 | /** @addtogroup DMA_LL_Exported_Functions |
| group-onsemi | 0:098463de4c5d | 154 | * @{ |
| group-onsemi | 0:098463de4c5d | 155 | */ |
| group-onsemi | 0:098463de4c5d | 156 | |
| group-onsemi | 0:098463de4c5d | 157 | /** @addtogroup DMA_LL_EF_Init |
| group-onsemi | 0:098463de4c5d | 158 | * @{ |
| group-onsemi | 0:098463de4c5d | 159 | */ |
| group-onsemi | 0:098463de4c5d | 160 | |
| group-onsemi | 0:098463de4c5d | 161 | /** |
| group-onsemi | 0:098463de4c5d | 162 | * @brief De-initialize the DMA registers to their default reset values. |
| group-onsemi | 0:098463de4c5d | 163 | * @param DMAx DMAx Instance |
| group-onsemi | 0:098463de4c5d | 164 | * @param Channel This parameter can be one of the following values: |
| group-onsemi | 0:098463de4c5d | 165 | * @arg @ref LL_DMA_CHANNEL_1 |
| group-onsemi | 0:098463de4c5d | 166 | * @arg @ref LL_DMA_CHANNEL_2 |
| group-onsemi | 0:098463de4c5d | 167 | * @arg @ref LL_DMA_CHANNEL_3 |
| group-onsemi | 0:098463de4c5d | 168 | * @arg @ref LL_DMA_CHANNEL_4 |
| group-onsemi | 0:098463de4c5d | 169 | * @arg @ref LL_DMA_CHANNEL_5 |
| group-onsemi | 0:098463de4c5d | 170 | * @arg @ref LL_DMA_CHANNEL_6 |
| group-onsemi | 0:098463de4c5d | 171 | * @arg @ref LL_DMA_CHANNEL_7 |
| group-onsemi | 0:098463de4c5d | 172 | * @arg @ref LL_DMA_CHANNEL_ALL |
| group-onsemi | 0:098463de4c5d | 173 | * @retval An ErrorStatus enumeration value: |
| group-onsemi | 0:098463de4c5d | 174 | * - SUCCESS: DMA registers are de-initialized |
| group-onsemi | 0:098463de4c5d | 175 | * - ERROR: DMA registers are not de-initialized |
| group-onsemi | 0:098463de4c5d | 176 | */ |
| group-onsemi | 0:098463de4c5d | 177 | uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) |
| group-onsemi | 0:098463de4c5d | 178 | { |
| group-onsemi | 0:098463de4c5d | 179 | DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1; |
| group-onsemi | 0:098463de4c5d | 180 | ErrorStatus status = SUCCESS; |
| group-onsemi | 0:098463de4c5d | 181 | |
| group-onsemi | 0:098463de4c5d | 182 | /* Check the DMA Instance DMAx and Channel parameters*/ |
| group-onsemi | 0:098463de4c5d | 183 | assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL)); |
| group-onsemi | 0:098463de4c5d | 184 | |
| group-onsemi | 0:098463de4c5d | 185 | if (Channel == LL_DMA_CHANNEL_ALL) |
| group-onsemi | 0:098463de4c5d | 186 | { |
| group-onsemi | 0:098463de4c5d | 187 | if (DMAx == DMA1) |
| group-onsemi | 0:098463de4c5d | 188 | { |
| group-onsemi | 0:098463de4c5d | 189 | /* Force reset of DMA clock */ |
| group-onsemi | 0:098463de4c5d | 190 | LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1); |
| group-onsemi | 0:098463de4c5d | 191 | |
| group-onsemi | 0:098463de4c5d | 192 | /* Release reset of DMA clock */ |
| group-onsemi | 0:098463de4c5d | 193 | LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1); |
| group-onsemi | 0:098463de4c5d | 194 | } |
| group-onsemi | 0:098463de4c5d | 195 | #if defined(DMA2) |
| group-onsemi | 0:098463de4c5d | 196 | else if (DMAx == DMA2) |
| group-onsemi | 0:098463de4c5d | 197 | { |
| group-onsemi | 0:098463de4c5d | 198 | /* Force reset of DMA clock */ |
| group-onsemi | 0:098463de4c5d | 199 | LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2); |
| group-onsemi | 0:098463de4c5d | 200 | |
| group-onsemi | 0:098463de4c5d | 201 | /* Release reset of DMA clock */ |
| group-onsemi | 0:098463de4c5d | 202 | LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2); |
| group-onsemi | 0:098463de4c5d | 203 | } |
| group-onsemi | 0:098463de4c5d | 204 | #endif |
| group-onsemi | 0:098463de4c5d | 205 | else |
| group-onsemi | 0:098463de4c5d | 206 | { |
| group-onsemi | 0:098463de4c5d | 207 | status = ERROR; |
| group-onsemi | 0:098463de4c5d | 208 | } |
| group-onsemi | 0:098463de4c5d | 209 | } |
| group-onsemi | 0:098463de4c5d | 210 | else |
| group-onsemi | 0:098463de4c5d | 211 | { |
| group-onsemi | 0:098463de4c5d | 212 | tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel)); |
| group-onsemi | 0:098463de4c5d | 213 | |
| group-onsemi | 0:098463de4c5d | 214 | /* Disable the selected DMAx_Channely */ |
| group-onsemi | 0:098463de4c5d | 215 | CLEAR_BIT(tmp->CCR, DMA_CCR_EN); |
| group-onsemi | 0:098463de4c5d | 216 | |
| group-onsemi | 0:098463de4c5d | 217 | /* Reset DMAx_Channely control register */ |
| group-onsemi | 0:098463de4c5d | 218 | LL_DMA_WriteReg(tmp, CCR, 0U); |
| group-onsemi | 0:098463de4c5d | 219 | |
| group-onsemi | 0:098463de4c5d | 220 | /* Reset DMAx_Channely remaining bytes register */ |
| group-onsemi | 0:098463de4c5d | 221 | LL_DMA_WriteReg(tmp, CNDTR, 0U); |
| group-onsemi | 0:098463de4c5d | 222 | |
| group-onsemi | 0:098463de4c5d | 223 | /* Reset DMAx_Channely peripheral address register */ |
| group-onsemi | 0:098463de4c5d | 224 | LL_DMA_WriteReg(tmp, CPAR, 0U); |
| group-onsemi | 0:098463de4c5d | 225 | |
| group-onsemi | 0:098463de4c5d | 226 | /* Reset DMAx_Channely memory address register */ |
| group-onsemi | 0:098463de4c5d | 227 | LL_DMA_WriteReg(tmp, CMAR, 0U); |
| group-onsemi | 0:098463de4c5d | 228 | |
| group-onsemi | 0:098463de4c5d | 229 | /* Reset Request register field for DMAx Channel */ |
| group-onsemi | 0:098463de4c5d | 230 | LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMA_REQUEST_0); |
| group-onsemi | 0:098463de4c5d | 231 | |
| group-onsemi | 0:098463de4c5d | 232 | if (Channel == LL_DMA_CHANNEL_1) |
| group-onsemi | 0:098463de4c5d | 233 | { |
| group-onsemi | 0:098463de4c5d | 234 | /* Reset interrupt pending bits for DMAx Channel1 */ |
| group-onsemi | 0:098463de4c5d | 235 | LL_DMA_ClearFlag_GI1(DMAx); |
| group-onsemi | 0:098463de4c5d | 236 | } |
| group-onsemi | 0:098463de4c5d | 237 | else if (Channel == LL_DMA_CHANNEL_2) |
| group-onsemi | 0:098463de4c5d | 238 | { |
| group-onsemi | 0:098463de4c5d | 239 | /* Reset interrupt pending bits for DMAx Channel2 */ |
| group-onsemi | 0:098463de4c5d | 240 | LL_DMA_ClearFlag_GI2(DMAx); |
| group-onsemi | 0:098463de4c5d | 241 | } |
| group-onsemi | 0:098463de4c5d | 242 | else if (Channel == LL_DMA_CHANNEL_3) |
| group-onsemi | 0:098463de4c5d | 243 | { |
| group-onsemi | 0:098463de4c5d | 244 | /* Reset interrupt pending bits for DMAx Channel3 */ |
| group-onsemi | 0:098463de4c5d | 245 | LL_DMA_ClearFlag_GI3(DMAx); |
| group-onsemi | 0:098463de4c5d | 246 | } |
| group-onsemi | 0:098463de4c5d | 247 | else if (Channel == LL_DMA_CHANNEL_4) |
| group-onsemi | 0:098463de4c5d | 248 | { |
| group-onsemi | 0:098463de4c5d | 249 | /* Reset interrupt pending bits for DMAx Channel4 */ |
| group-onsemi | 0:098463de4c5d | 250 | LL_DMA_ClearFlag_GI4(DMAx); |
| group-onsemi | 0:098463de4c5d | 251 | } |
| group-onsemi | 0:098463de4c5d | 252 | else if (Channel == LL_DMA_CHANNEL_5) |
| group-onsemi | 0:098463de4c5d | 253 | { |
| group-onsemi | 0:098463de4c5d | 254 | /* Reset interrupt pending bits for DMAx Channel5 */ |
| group-onsemi | 0:098463de4c5d | 255 | LL_DMA_ClearFlag_GI5(DMAx); |
| group-onsemi | 0:098463de4c5d | 256 | } |
| group-onsemi | 0:098463de4c5d | 257 | |
| group-onsemi | 0:098463de4c5d | 258 | else if (Channel == LL_DMA_CHANNEL_6) |
| group-onsemi | 0:098463de4c5d | 259 | { |
| group-onsemi | 0:098463de4c5d | 260 | /* Reset interrupt pending bits for DMAx Channel6 */ |
| group-onsemi | 0:098463de4c5d | 261 | LL_DMA_ClearFlag_GI6(DMAx); |
| group-onsemi | 0:098463de4c5d | 262 | } |
| group-onsemi | 0:098463de4c5d | 263 | else if (Channel == LL_DMA_CHANNEL_7) |
| group-onsemi | 0:098463de4c5d | 264 | { |
| group-onsemi | 0:098463de4c5d | 265 | /* Reset interrupt pending bits for DMAx Channel7 */ |
| group-onsemi | 0:098463de4c5d | 266 | LL_DMA_ClearFlag_GI7(DMAx); |
| group-onsemi | 0:098463de4c5d | 267 | } |
| group-onsemi | 0:098463de4c5d | 268 | else |
| group-onsemi | 0:098463de4c5d | 269 | { |
| group-onsemi | 0:098463de4c5d | 270 | status = ERROR; |
| group-onsemi | 0:098463de4c5d | 271 | } |
| group-onsemi | 0:098463de4c5d | 272 | } |
| group-onsemi | 0:098463de4c5d | 273 | |
| group-onsemi | 0:098463de4c5d | 274 | return status; |
| group-onsemi | 0:098463de4c5d | 275 | } |
| group-onsemi | 0:098463de4c5d | 276 | |
| group-onsemi | 0:098463de4c5d | 277 | /** |
| group-onsemi | 0:098463de4c5d | 278 | * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct. |
| group-onsemi | 0:098463de4c5d | 279 | * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros : |
| group-onsemi | 0:098463de4c5d | 280 | * @arg @ref __LL_DMA_GET_INSTANCE |
| group-onsemi | 0:098463de4c5d | 281 | * @arg @ref __LL_DMA_GET_CHANNEL |
| group-onsemi | 0:098463de4c5d | 282 | * @param DMAx DMAx Instance |
| group-onsemi | 0:098463de4c5d | 283 | * @param Channel This parameter can be one of the following values: |
| group-onsemi | 0:098463de4c5d | 284 | * @arg @ref LL_DMA_CHANNEL_1 |
| group-onsemi | 0:098463de4c5d | 285 | * @arg @ref LL_DMA_CHANNEL_2 |
| group-onsemi | 0:098463de4c5d | 286 | * @arg @ref LL_DMA_CHANNEL_3 |
| group-onsemi | 0:098463de4c5d | 287 | * @arg @ref LL_DMA_CHANNEL_4 |
| group-onsemi | 0:098463de4c5d | 288 | * @arg @ref LL_DMA_CHANNEL_5 |
| group-onsemi | 0:098463de4c5d | 289 | * @arg @ref LL_DMA_CHANNEL_6 |
| group-onsemi | 0:098463de4c5d | 290 | * @arg @ref LL_DMA_CHANNEL_7 |
| group-onsemi | 0:098463de4c5d | 291 | * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure. |
| group-onsemi | 0:098463de4c5d | 292 | * @retval An ErrorStatus enumeration value: |
| group-onsemi | 0:098463de4c5d | 293 | * - SUCCESS: DMA registers are initialized |
| group-onsemi | 0:098463de4c5d | 294 | * - ERROR: Not applicable |
| group-onsemi | 0:098463de4c5d | 295 | */ |
| group-onsemi | 0:098463de4c5d | 296 | uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct) |
| group-onsemi | 0:098463de4c5d | 297 | { |
| group-onsemi | 0:098463de4c5d | 298 | /* Check the DMA Instance DMAx and Channel parameters*/ |
| group-onsemi | 0:098463de4c5d | 299 | assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); |
| group-onsemi | 0:098463de4c5d | 300 | |
| group-onsemi | 0:098463de4c5d | 301 | /* Check the DMA parameters from DMA_InitStruct */ |
| group-onsemi | 0:098463de4c5d | 302 | assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction)); |
| group-onsemi | 0:098463de4c5d | 303 | assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode)); |
| group-onsemi | 0:098463de4c5d | 304 | assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode)); |
| group-onsemi | 0:098463de4c5d | 305 | assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode)); |
| group-onsemi | 0:098463de4c5d | 306 | assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize)); |
| group-onsemi | 0:098463de4c5d | 307 | assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize)); |
| group-onsemi | 0:098463de4c5d | 308 | assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData)); |
| group-onsemi | 0:098463de4c5d | 309 | assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest)); |
| group-onsemi | 0:098463de4c5d | 310 | assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority)); |
| group-onsemi | 0:098463de4c5d | 311 | |
| group-onsemi | 0:098463de4c5d | 312 | /*---------------------------- DMAx CCR Configuration ------------------------ |
| group-onsemi | 0:098463de4c5d | 313 | * Configure DMAx_Channely: data transfer direction, data transfer mode, |
| group-onsemi | 0:098463de4c5d | 314 | * peripheral and memory increment mode, |
| group-onsemi | 0:098463de4c5d | 315 | * data size alignment and priority level with parameters : |
| group-onsemi | 0:098463de4c5d | 316 | * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits |
| group-onsemi | 0:098463de4c5d | 317 | * - Mode: DMA_CCR_CIRC bit |
| group-onsemi | 0:098463de4c5d | 318 | * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit |
| group-onsemi | 0:098463de4c5d | 319 | * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit |
| group-onsemi | 0:098463de4c5d | 320 | * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits |
| group-onsemi | 0:098463de4c5d | 321 | * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits |
| group-onsemi | 0:098463de4c5d | 322 | * - Priority: DMA_CCR_PL[1:0] bits |
| group-onsemi | 0:098463de4c5d | 323 | */ |
| group-onsemi | 0:098463de4c5d | 324 | LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \ |
| group-onsemi | 0:098463de4c5d | 325 | DMA_InitStruct->Mode | \ |
| group-onsemi | 0:098463de4c5d | 326 | DMA_InitStruct->PeriphOrM2MSrcIncMode | \ |
| group-onsemi | 0:098463de4c5d | 327 | DMA_InitStruct->MemoryOrM2MDstIncMode | \ |
| group-onsemi | 0:098463de4c5d | 328 | DMA_InitStruct->PeriphOrM2MSrcDataSize | \ |
| group-onsemi | 0:098463de4c5d | 329 | DMA_InitStruct->MemoryOrM2MDstDataSize | \ |
| group-onsemi | 0:098463de4c5d | 330 | DMA_InitStruct->Priority); |
| group-onsemi | 0:098463de4c5d | 331 | |
| group-onsemi | 0:098463de4c5d | 332 | /*-------------------------- DMAx CMAR Configuration ------------------------- |
| group-onsemi | 0:098463de4c5d | 333 | * Configure the memory or destination base address with parameter : |
| group-onsemi | 0:098463de4c5d | 334 | * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits |
| group-onsemi | 0:098463de4c5d | 335 | */ |
| group-onsemi | 0:098463de4c5d | 336 | LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress); |
| group-onsemi | 0:098463de4c5d | 337 | |
| group-onsemi | 0:098463de4c5d | 338 | /*-------------------------- DMAx CPAR Configuration ------------------------- |
| group-onsemi | 0:098463de4c5d | 339 | * Configure the peripheral or source base address with parameter : |
| group-onsemi | 0:098463de4c5d | 340 | * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits |
| group-onsemi | 0:098463de4c5d | 341 | */ |
| group-onsemi | 0:098463de4c5d | 342 | LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress); |
| group-onsemi | 0:098463de4c5d | 343 | |
| group-onsemi | 0:098463de4c5d | 344 | /*--------------------------- DMAx CNDTR Configuration ----------------------- |
| group-onsemi | 0:098463de4c5d | 345 | * Configure the peripheral base address with parameter : |
| group-onsemi | 0:098463de4c5d | 346 | * - NbData: DMA_CNDTR_NDT[15:0] bits |
| group-onsemi | 0:098463de4c5d | 347 | */ |
| group-onsemi | 0:098463de4c5d | 348 | LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData); |
| group-onsemi | 0:098463de4c5d | 349 | |
| group-onsemi | 0:098463de4c5d | 350 | /*--------------------------- DMAx CSELR Configuration ----------------------- |
| group-onsemi | 0:098463de4c5d | 351 | * Configure the peripheral base address with parameter : |
| group-onsemi | 0:098463de4c5d | 352 | * - PeriphRequest: DMA_CSELR[31:0] bits |
| group-onsemi | 0:098463de4c5d | 353 | */ |
| group-onsemi | 0:098463de4c5d | 354 | LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest); |
| group-onsemi | 0:098463de4c5d | 355 | |
| group-onsemi | 0:098463de4c5d | 356 | return SUCCESS; |
| group-onsemi | 0:098463de4c5d | 357 | } |
| group-onsemi | 0:098463de4c5d | 358 | |
| group-onsemi | 0:098463de4c5d | 359 | /** |
| group-onsemi | 0:098463de4c5d | 360 | * @brief Set each @ref LL_DMA_InitTypeDef field to default value. |
| group-onsemi | 0:098463de4c5d | 361 | * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure. |
| group-onsemi | 0:098463de4c5d | 362 | * @retval None |
| group-onsemi | 0:098463de4c5d | 363 | */ |
| group-onsemi | 0:098463de4c5d | 364 | void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) |
| group-onsemi | 0:098463de4c5d | 365 | { |
| group-onsemi | 0:098463de4c5d | 366 | /* Set DMA_InitStruct fields to default values */ |
| group-onsemi | 0:098463de4c5d | 367 | DMA_InitStruct->PeriphOrM2MSrcAddress = (uint32_t)0x00000000U; |
| group-onsemi | 0:098463de4c5d | 368 | DMA_InitStruct->MemoryOrM2MDstAddress = (uint32_t)0x00000000U; |
| group-onsemi | 0:098463de4c5d | 369 | DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; |
| group-onsemi | 0:098463de4c5d | 370 | DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL; |
| group-onsemi | 0:098463de4c5d | 371 | DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; |
| group-onsemi | 0:098463de4c5d | 372 | DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; |
| group-onsemi | 0:098463de4c5d | 373 | DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; |
| group-onsemi | 0:098463de4c5d | 374 | DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; |
| group-onsemi | 0:098463de4c5d | 375 | DMA_InitStruct->NbData = (uint32_t)0x00000000U; |
| group-onsemi | 0:098463de4c5d | 376 | DMA_InitStruct->PeriphRequest = LL_DMA_REQUEST_0; |
| group-onsemi | 0:098463de4c5d | 377 | DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW; |
| group-onsemi | 0:098463de4c5d | 378 | } |
| group-onsemi | 0:098463de4c5d | 379 | |
| group-onsemi | 0:098463de4c5d | 380 | /** |
| group-onsemi | 0:098463de4c5d | 381 | * @} |
| group-onsemi | 0:098463de4c5d | 382 | */ |
| group-onsemi | 0:098463de4c5d | 383 | |
| group-onsemi | 0:098463de4c5d | 384 | /** |
| group-onsemi | 0:098463de4c5d | 385 | * @} |
| group-onsemi | 0:098463de4c5d | 386 | */ |
| group-onsemi | 0:098463de4c5d | 387 | |
| group-onsemi | 0:098463de4c5d | 388 | /** |
| group-onsemi | 0:098463de4c5d | 389 | * @} |
| group-onsemi | 0:098463de4c5d | 390 | */ |
| group-onsemi | 0:098463de4c5d | 391 | |
| group-onsemi | 0:098463de4c5d | 392 | #endif /* DMA1 || DMA2 */ |
| group-onsemi | 0:098463de4c5d | 393 | |
| group-onsemi | 0:098463de4c5d | 394 | /** |
| group-onsemi | 0:098463de4c5d | 395 | * @} |
| group-onsemi | 0:098463de4c5d | 396 | */ |
| group-onsemi | 0:098463de4c5d | 397 | |
| group-onsemi | 0:098463de4c5d | 398 | #endif /* USE_FULL_LL_DRIVER */ |
| group-onsemi | 0:098463de4c5d | 399 | |
| group-onsemi | 0:098463de4c5d | 400 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |