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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nand.c@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /**
group-onsemi 0:098463de4c5d 2 ******************************************************************************
group-onsemi 0:098463de4c5d 3 * @file stm32f1xx_hal_nand.c
group-onsemi 0:098463de4c5d 4 * @author MCD Application Team
group-onsemi 0:098463de4c5d 5 * @version V1.0.5
group-onsemi 0:098463de4c5d 6 * @date 06-December-2016
group-onsemi 0:098463de4c5d 7 * @brief NAND HAL module driver.
group-onsemi 0:098463de4c5d 8 * This file provides a generic firmware to drive NAND memories mounted
group-onsemi 0:098463de4c5d 9 * as external device.
group-onsemi 0:098463de4c5d 10 *
group-onsemi 0:098463de4c5d 11 @verbatim
group-onsemi 0:098463de4c5d 12 ==============================================================================
group-onsemi 0:098463de4c5d 13 ##### How to use this driver #####
group-onsemi 0:098463de4c5d 14 ==============================================================================
group-onsemi 0:098463de4c5d 15 [..]
group-onsemi 0:098463de4c5d 16 This driver is a generic layered driver which contains a set of APIs used to
group-onsemi 0:098463de4c5d 17 control NAND flash memories. It uses the FSMC/FSMC layer functions to interface
group-onsemi 0:098463de4c5d 18 with NAND devices. This driver is used as follows:
group-onsemi 0:098463de4c5d 19
group-onsemi 0:098463de4c5d 20 (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
group-onsemi 0:098463de4c5d 21 with control and timing parameters for both common and attribute spaces.
group-onsemi 0:098463de4c5d 22
group-onsemi 0:098463de4c5d 23 (+) Read NAND flash memory maker and device IDs using the function
group-onsemi 0:098463de4c5d 24 HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
group-onsemi 0:098463de4c5d 25 structure declared by the function caller.
group-onsemi 0:098463de4c5d 26
group-onsemi 0:098463de4c5d 27 (+) Access NAND flash memory by read/write operations using the functions
group-onsemi 0:098463de4c5d 28 HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()
group-onsemi 0:098463de4c5d 29 to read/write page(s)/spare area(s). These functions use specific device
group-onsemi 0:098463de4c5d 30 information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
group-onsemi 0:098463de4c5d 31 structure. The read/write address information is contained by the Nand_Address_Typedef
group-onsemi 0:098463de4c5d 32 structure passed as parameter.
group-onsemi 0:098463de4c5d 33
group-onsemi 0:098463de4c5d 34 (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
group-onsemi 0:098463de4c5d 35
group-onsemi 0:098463de4c5d 36 (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
group-onsemi 0:098463de4c5d 37 The erase block address information is contained in the Nand_Address_Typedef
group-onsemi 0:098463de4c5d 38 structure passed as parameter.
group-onsemi 0:098463de4c5d 39
group-onsemi 0:098463de4c5d 40 (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
group-onsemi 0:098463de4c5d 41
group-onsemi 0:098463de4c5d 42 (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
group-onsemi 0:098463de4c5d 43 HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
group-onsemi 0:098463de4c5d 44 feature or the function HAL_NAND_GetECC() to get the ECC correction code.
group-onsemi 0:098463de4c5d 45
group-onsemi 0:098463de4c5d 46 (+) You can monitor the NAND device HAL state by calling the function
group-onsemi 0:098463de4c5d 47 HAL_NAND_GetState()
group-onsemi 0:098463de4c5d 48
group-onsemi 0:098463de4c5d 49 [..]
group-onsemi 0:098463de4c5d 50 (@) This driver is a set of generic APIs which handle standard NAND flash operations.
group-onsemi 0:098463de4c5d 51 If a NAND flash device contains different operations and/or implementations,
group-onsemi 0:098463de4c5d 52 it should be implemented separately.
group-onsemi 0:098463de4c5d 53
group-onsemi 0:098463de4c5d 54 @endverbatim
group-onsemi 0:098463de4c5d 55 ******************************************************************************
group-onsemi 0:098463de4c5d 56 * @attention
group-onsemi 0:098463de4c5d 57 *
group-onsemi 0:098463de4c5d 58 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
group-onsemi 0:098463de4c5d 59 *
group-onsemi 0:098463de4c5d 60 * Redistribution and use in source and binary forms, with or without modification,
group-onsemi 0:098463de4c5d 61 * are permitted provided that the following conditions are met:
group-onsemi 0:098463de4c5d 62 * 1. Redistributions of source code must retain the above copyright notice,
group-onsemi 0:098463de4c5d 63 * this list of conditions and the following disclaimer.
group-onsemi 0:098463de4c5d 64 * 2. Redistributions in binary form must reproduce the above copyright notice,
group-onsemi 0:098463de4c5d 65 * this list of conditions and the following disclaimer in the documentation
group-onsemi 0:098463de4c5d 66 * and/or other materials provided with the distribution.
group-onsemi 0:098463de4c5d 67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
group-onsemi 0:098463de4c5d 68 * may be used to endorse or promote products derived from this software
group-onsemi 0:098463de4c5d 69 * without specific prior written permission.
group-onsemi 0:098463de4c5d 70 *
group-onsemi 0:098463de4c5d 71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
group-onsemi 0:098463de4c5d 72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
group-onsemi 0:098463de4c5d 73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
group-onsemi 0:098463de4c5d 74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
group-onsemi 0:098463de4c5d 75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
group-onsemi 0:098463de4c5d 76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
group-onsemi 0:098463de4c5d 77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
group-onsemi 0:098463de4c5d 78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
group-onsemi 0:098463de4c5d 79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
group-onsemi 0:098463de4c5d 80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
group-onsemi 0:098463de4c5d 81 *
group-onsemi 0:098463de4c5d 82 ******************************************************************************
group-onsemi 0:098463de4c5d 83 */
group-onsemi 0:098463de4c5d 84
group-onsemi 0:098463de4c5d 85 /* Includes ------------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 86 #include "stm32f1xx_hal.h"
group-onsemi 0:098463de4c5d 87
group-onsemi 0:098463de4c5d 88 /** @addtogroup STM32F1xx_HAL_Driver
group-onsemi 0:098463de4c5d 89 * @{
group-onsemi 0:098463de4c5d 90 */
group-onsemi 0:098463de4c5d 91
group-onsemi 0:098463de4c5d 92 #ifdef HAL_NAND_MODULE_ENABLED
group-onsemi 0:098463de4c5d 93
group-onsemi 0:098463de4c5d 94 #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
group-onsemi 0:098463de4c5d 95
group-onsemi 0:098463de4c5d 96 /** @defgroup NAND NAND
group-onsemi 0:098463de4c5d 97 * @brief NAND HAL module driver
group-onsemi 0:098463de4c5d 98 * @{
group-onsemi 0:098463de4c5d 99 */
group-onsemi 0:098463de4c5d 100
group-onsemi 0:098463de4c5d 101 /* Private typedef -----------------------------------------------------------*/
group-onsemi 0:098463de4c5d 102 /* Private define ------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 103 /** @defgroup NAND_Private_Constants NAND Private Constants
group-onsemi 0:098463de4c5d 104 * @{
group-onsemi 0:098463de4c5d 105 */
group-onsemi 0:098463de4c5d 106
group-onsemi 0:098463de4c5d 107 /**
group-onsemi 0:098463de4c5d 108 * @}
group-onsemi 0:098463de4c5d 109 */
group-onsemi 0:098463de4c5d 110
group-onsemi 0:098463de4c5d 111 /* Private macro -------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 112 /** @defgroup NAND_Private_Macros NAND Private Macros
group-onsemi 0:098463de4c5d 113 * @{
group-onsemi 0:098463de4c5d 114 */
group-onsemi 0:098463de4c5d 115
group-onsemi 0:098463de4c5d 116 /**
group-onsemi 0:098463de4c5d 117 * @}
group-onsemi 0:098463de4c5d 118 */
group-onsemi 0:098463de4c5d 119
group-onsemi 0:098463de4c5d 120 /* Private variables ---------------------------------------------------------*/
group-onsemi 0:098463de4c5d 121 /* Private function prototypes -----------------------------------------------*/
group-onsemi 0:098463de4c5d 122 /** @defgroup NAND_Private_Functions NAND Private Functions
group-onsemi 0:098463de4c5d 123 * @{
group-onsemi 0:098463de4c5d 124 */
group-onsemi 0:098463de4c5d 125 static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address);
group-onsemi 0:098463de4c5d 126 /**
group-onsemi 0:098463de4c5d 127 * @}
group-onsemi 0:098463de4c5d 128 */
group-onsemi 0:098463de4c5d 129
group-onsemi 0:098463de4c5d 130 /* Exported functions ---------------------------------------------------------*/
group-onsemi 0:098463de4c5d 131
group-onsemi 0:098463de4c5d 132 /** @defgroup NAND_Exported_Functions NAND Exported Functions
group-onsemi 0:098463de4c5d 133 * @{
group-onsemi 0:098463de4c5d 134 */
group-onsemi 0:098463de4c5d 135
group-onsemi 0:098463de4c5d 136 /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
group-onsemi 0:098463de4c5d 137 * @brief Initialization and Configuration functions
group-onsemi 0:098463de4c5d 138 *
group-onsemi 0:098463de4c5d 139 @verbatim
group-onsemi 0:098463de4c5d 140 ==============================================================================
group-onsemi 0:098463de4c5d 141 ##### NAND Initialization and de-initialization functions #####
group-onsemi 0:098463de4c5d 142 ==============================================================================
group-onsemi 0:098463de4c5d 143 [..]
group-onsemi 0:098463de4c5d 144 This section provides functions allowing to initialize/de-initialize
group-onsemi 0:098463de4c5d 145 the NAND memory
group-onsemi 0:098463de4c5d 146
group-onsemi 0:098463de4c5d 147 @endverbatim
group-onsemi 0:098463de4c5d 148 * @{
group-onsemi 0:098463de4c5d 149 */
group-onsemi 0:098463de4c5d 150
group-onsemi 0:098463de4c5d 151 /**
group-onsemi 0:098463de4c5d 152 * @brief Perform NAND memory Initialization sequence
group-onsemi 0:098463de4c5d 153 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 154 * the configuration information for NAND module.
group-onsemi 0:098463de4c5d 155 * @param ComSpace_Timing: pointer to Common space timing structure
group-onsemi 0:098463de4c5d 156 * @param AttSpace_Timing: pointer to Attribute space timing structure
group-onsemi 0:098463de4c5d 157 * @retval HAL status
group-onsemi 0:098463de4c5d 158 */
group-onsemi 0:098463de4c5d 159 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
group-onsemi 0:098463de4c5d 160 {
group-onsemi 0:098463de4c5d 161 /* Check the NAND handle state */
group-onsemi 0:098463de4c5d 162 if(hnand == NULL)
group-onsemi 0:098463de4c5d 163 {
group-onsemi 0:098463de4c5d 164 return HAL_ERROR;
group-onsemi 0:098463de4c5d 165 }
group-onsemi 0:098463de4c5d 166
group-onsemi 0:098463de4c5d 167 if(hnand->State == HAL_NAND_STATE_RESET)
group-onsemi 0:098463de4c5d 168 {
group-onsemi 0:098463de4c5d 169 /* Allocate lock resource and initialize it */
group-onsemi 0:098463de4c5d 170 hnand->Lock = HAL_UNLOCKED;
group-onsemi 0:098463de4c5d 171
group-onsemi 0:098463de4c5d 172 /* Initialize the low level hardware (MSP) */
group-onsemi 0:098463de4c5d 173 HAL_NAND_MspInit(hnand);
group-onsemi 0:098463de4c5d 174 }
group-onsemi 0:098463de4c5d 175
group-onsemi 0:098463de4c5d 176 /* Initialize NAND control Interface */
group-onsemi 0:098463de4c5d 177 FSMC_NAND_Init(hnand->Instance, &(hnand->Init));
group-onsemi 0:098463de4c5d 178
group-onsemi 0:098463de4c5d 179 /* Initialize NAND common space timing Interface */
group-onsemi 0:098463de4c5d 180 FSMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
group-onsemi 0:098463de4c5d 181
group-onsemi 0:098463de4c5d 182 /* Initialize NAND attribute space timing Interface */
group-onsemi 0:098463de4c5d 183 FSMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
group-onsemi 0:098463de4c5d 184
group-onsemi 0:098463de4c5d 185 /* Enable the NAND device */
group-onsemi 0:098463de4c5d 186 __FSMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
group-onsemi 0:098463de4c5d 187
group-onsemi 0:098463de4c5d 188 /* Update the NAND controller state */
group-onsemi 0:098463de4c5d 189 hnand->State = HAL_NAND_STATE_READY;
group-onsemi 0:098463de4c5d 190
group-onsemi 0:098463de4c5d 191 return HAL_OK;
group-onsemi 0:098463de4c5d 192 }
group-onsemi 0:098463de4c5d 193
group-onsemi 0:098463de4c5d 194 /**
group-onsemi 0:098463de4c5d 195 * @brief Perform NAND memory De-Initialization sequence
group-onsemi 0:098463de4c5d 196 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 197 * the configuration information for NAND module.
group-onsemi 0:098463de4c5d 198 * @retval HAL status
group-onsemi 0:098463de4c5d 199 */
group-onsemi 0:098463de4c5d 200 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
group-onsemi 0:098463de4c5d 201 {
group-onsemi 0:098463de4c5d 202 /* Initialize the low level hardware (MSP) */
group-onsemi 0:098463de4c5d 203 HAL_NAND_MspDeInit(hnand);
group-onsemi 0:098463de4c5d 204
group-onsemi 0:098463de4c5d 205 /* Configure the NAND registers with their reset values */
group-onsemi 0:098463de4c5d 206 FSMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
group-onsemi 0:098463de4c5d 207
group-onsemi 0:098463de4c5d 208 /* Reset the NAND controller state */
group-onsemi 0:098463de4c5d 209 hnand->State = HAL_NAND_STATE_RESET;
group-onsemi 0:098463de4c5d 210
group-onsemi 0:098463de4c5d 211 /* Release Lock */
group-onsemi 0:098463de4c5d 212 __HAL_UNLOCK(hnand);
group-onsemi 0:098463de4c5d 213
group-onsemi 0:098463de4c5d 214 return HAL_OK;
group-onsemi 0:098463de4c5d 215 }
group-onsemi 0:098463de4c5d 216
group-onsemi 0:098463de4c5d 217 /**
group-onsemi 0:098463de4c5d 218 * @brief NAND MSP Init
group-onsemi 0:098463de4c5d 219 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 220 * the configuration information for NAND module.
group-onsemi 0:098463de4c5d 221 * @retval None
group-onsemi 0:098463de4c5d 222 */
group-onsemi 0:098463de4c5d 223 __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
group-onsemi 0:098463de4c5d 224 {
group-onsemi 0:098463de4c5d 225 /* Prevent unused argument(s) compilation warning */
group-onsemi 0:098463de4c5d 226 UNUSED(hnand);
group-onsemi 0:098463de4c5d 227 /* NOTE : This function Should not be modified, when the callback is needed,
group-onsemi 0:098463de4c5d 228 the HAL_NAND_MspInit could be implemented in the user file
group-onsemi 0:098463de4c5d 229 */
group-onsemi 0:098463de4c5d 230 }
group-onsemi 0:098463de4c5d 231
group-onsemi 0:098463de4c5d 232 /**
group-onsemi 0:098463de4c5d 233 * @brief NAND MSP DeInit
group-onsemi 0:098463de4c5d 234 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 235 * the configuration information for NAND module.
group-onsemi 0:098463de4c5d 236 * @retval None
group-onsemi 0:098463de4c5d 237 */
group-onsemi 0:098463de4c5d 238 __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
group-onsemi 0:098463de4c5d 239 {
group-onsemi 0:098463de4c5d 240 /* Prevent unused argument(s) compilation warning */
group-onsemi 0:098463de4c5d 241 UNUSED(hnand);
group-onsemi 0:098463de4c5d 242 /* NOTE : This function Should not be modified, when the callback is needed,
group-onsemi 0:098463de4c5d 243 the HAL_NAND_MspDeInit could be implemented in the user file
group-onsemi 0:098463de4c5d 244 */
group-onsemi 0:098463de4c5d 245 }
group-onsemi 0:098463de4c5d 246
group-onsemi 0:098463de4c5d 247
group-onsemi 0:098463de4c5d 248 /**
group-onsemi 0:098463de4c5d 249 * @brief This function handles NAND device interrupt request.
group-onsemi 0:098463de4c5d 250 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 251 * the configuration information for NAND module.
group-onsemi 0:098463de4c5d 252 * @retval HAL status
group-onsemi 0:098463de4c5d 253 */
group-onsemi 0:098463de4c5d 254 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
group-onsemi 0:098463de4c5d 255 {
group-onsemi 0:098463de4c5d 256 /* Check NAND interrupt Rising edge flag */
group-onsemi 0:098463de4c5d 257 if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE))
group-onsemi 0:098463de4c5d 258 {
group-onsemi 0:098463de4c5d 259 /* NAND interrupt callback*/
group-onsemi 0:098463de4c5d 260 HAL_NAND_ITCallback(hnand);
group-onsemi 0:098463de4c5d 261
group-onsemi 0:098463de4c5d 262 /* Clear NAND interrupt Rising edge pending bit */
group-onsemi 0:098463de4c5d 263 __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_RISING_EDGE);
group-onsemi 0:098463de4c5d 264 }
group-onsemi 0:098463de4c5d 265
group-onsemi 0:098463de4c5d 266 /* Check NAND interrupt Level flag */
group-onsemi 0:098463de4c5d 267 if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL))
group-onsemi 0:098463de4c5d 268 {
group-onsemi 0:098463de4c5d 269 /* NAND interrupt callback*/
group-onsemi 0:098463de4c5d 270 HAL_NAND_ITCallback(hnand);
group-onsemi 0:098463de4c5d 271
group-onsemi 0:098463de4c5d 272 /* Clear NAND interrupt Level pending bit */
group-onsemi 0:098463de4c5d 273 __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_LEVEL);
group-onsemi 0:098463de4c5d 274 }
group-onsemi 0:098463de4c5d 275
group-onsemi 0:098463de4c5d 276 /* Check NAND interrupt Falling edge flag */
group-onsemi 0:098463de4c5d 277 if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE))
group-onsemi 0:098463de4c5d 278 {
group-onsemi 0:098463de4c5d 279 /* NAND interrupt callback*/
group-onsemi 0:098463de4c5d 280 HAL_NAND_ITCallback(hnand);
group-onsemi 0:098463de4c5d 281
group-onsemi 0:098463de4c5d 282 /* Clear NAND interrupt Falling edge pending bit */
group-onsemi 0:098463de4c5d 283 __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FALLING_EDGE);
group-onsemi 0:098463de4c5d 284 }
group-onsemi 0:098463de4c5d 285
group-onsemi 0:098463de4c5d 286 /* Check NAND interrupt FIFO empty flag */
group-onsemi 0:098463de4c5d 287 if(__FSMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT))
group-onsemi 0:098463de4c5d 288 {
group-onsemi 0:098463de4c5d 289 /* NAND interrupt callback*/
group-onsemi 0:098463de4c5d 290 HAL_NAND_ITCallback(hnand);
group-onsemi 0:098463de4c5d 291
group-onsemi 0:098463de4c5d 292 /* Clear NAND interrupt FIFO empty pending bit */
group-onsemi 0:098463de4c5d 293 __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT);
group-onsemi 0:098463de4c5d 294 }
group-onsemi 0:098463de4c5d 295
group-onsemi 0:098463de4c5d 296 }
group-onsemi 0:098463de4c5d 297
group-onsemi 0:098463de4c5d 298 /**
group-onsemi 0:098463de4c5d 299 * @brief NAND interrupt feature callback
group-onsemi 0:098463de4c5d 300 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 301 * the configuration information for NAND module.
group-onsemi 0:098463de4c5d 302 * @retval None
group-onsemi 0:098463de4c5d 303 */
group-onsemi 0:098463de4c5d 304 __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
group-onsemi 0:098463de4c5d 305 {
group-onsemi 0:098463de4c5d 306 /* Prevent unused argument(s) compilation warning */
group-onsemi 0:098463de4c5d 307 UNUSED(hnand);
group-onsemi 0:098463de4c5d 308 /* NOTE : This function Should not be modified, when the callback is needed,
group-onsemi 0:098463de4c5d 309 the HAL_NAND_ITCallback could be implemented in the user file
group-onsemi 0:098463de4c5d 310 */
group-onsemi 0:098463de4c5d 311 }
group-onsemi 0:098463de4c5d 312
group-onsemi 0:098463de4c5d 313 /**
group-onsemi 0:098463de4c5d 314 * @}
group-onsemi 0:098463de4c5d 315 */
group-onsemi 0:098463de4c5d 316
group-onsemi 0:098463de4c5d 317 /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
group-onsemi 0:098463de4c5d 318 * @brief Input Output and memory control functions
group-onsemi 0:098463de4c5d 319 *
group-onsemi 0:098463de4c5d 320 @verbatim
group-onsemi 0:098463de4c5d 321 ==============================================================================
group-onsemi 0:098463de4c5d 322 ##### NAND Input and Output functions #####
group-onsemi 0:098463de4c5d 323 ==============================================================================
group-onsemi 0:098463de4c5d 324 [..]
group-onsemi 0:098463de4c5d 325 This section provides functions allowing to use and control the NAND
group-onsemi 0:098463de4c5d 326 memory
group-onsemi 0:098463de4c5d 327
group-onsemi 0:098463de4c5d 328 @endverbatim
group-onsemi 0:098463de4c5d 329 * @{
group-onsemi 0:098463de4c5d 330 */
group-onsemi 0:098463de4c5d 331
group-onsemi 0:098463de4c5d 332 /**
group-onsemi 0:098463de4c5d 333 * @brief Read the NAND memory electronic signature
group-onsemi 0:098463de4c5d 334 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 335 * the configuration information for NAND module.
group-onsemi 0:098463de4c5d 336 * @param pNAND_ID: NAND ID structure
group-onsemi 0:098463de4c5d 337 * @retval HAL status
group-onsemi 0:098463de4c5d 338 */
group-onsemi 0:098463de4c5d 339 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
group-onsemi 0:098463de4c5d 340 {
group-onsemi 0:098463de4c5d 341 __IO uint32_t data = 0;
group-onsemi 0:098463de4c5d 342 uint32_t deviceaddress = 0;
group-onsemi 0:098463de4c5d 343
group-onsemi 0:098463de4c5d 344 /* Process Locked */
group-onsemi 0:098463de4c5d 345 __HAL_LOCK(hnand);
group-onsemi 0:098463de4c5d 346
group-onsemi 0:098463de4c5d 347 /* Check the NAND controller state */
group-onsemi 0:098463de4c5d 348 if(hnand->State == HAL_NAND_STATE_BUSY)
group-onsemi 0:098463de4c5d 349 {
group-onsemi 0:098463de4c5d 350 return HAL_BUSY;
group-onsemi 0:098463de4c5d 351 }
group-onsemi 0:098463de4c5d 352
group-onsemi 0:098463de4c5d 353 /* Identify the device address */
group-onsemi 0:098463de4c5d 354 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
group-onsemi 0:098463de4c5d 355 {
group-onsemi 0:098463de4c5d 356 deviceaddress = NAND_DEVICE1;
group-onsemi 0:098463de4c5d 357 }
group-onsemi 0:098463de4c5d 358 else
group-onsemi 0:098463de4c5d 359 {
group-onsemi 0:098463de4c5d 360 deviceaddress = NAND_DEVICE2;
group-onsemi 0:098463de4c5d 361 }
group-onsemi 0:098463de4c5d 362
group-onsemi 0:098463de4c5d 363 /* Update the NAND controller state */
group-onsemi 0:098463de4c5d 364 hnand->State = HAL_NAND_STATE_BUSY;
group-onsemi 0:098463de4c5d 365
group-onsemi 0:098463de4c5d 366 /* Send Read ID command sequence */
group-onsemi 0:098463de4c5d 367 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
group-onsemi 0:098463de4c5d 368 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
group-onsemi 0:098463de4c5d 369
group-onsemi 0:098463de4c5d 370 /* Read the electronic signature from NAND flash */
group-onsemi 0:098463de4c5d 371 data = *(__IO uint32_t *)deviceaddress;
group-onsemi 0:098463de4c5d 372
group-onsemi 0:098463de4c5d 373 /* Return the data read */
group-onsemi 0:098463de4c5d 374 pNAND_ID->Maker_Id = ADDR_1st_CYCLE(data);
group-onsemi 0:098463de4c5d 375 pNAND_ID->Device_Id = ADDR_2nd_CYCLE(data);
group-onsemi 0:098463de4c5d 376 pNAND_ID->Third_Id = ADDR_3rd_CYCLE(data);
group-onsemi 0:098463de4c5d 377 pNAND_ID->Fourth_Id = ADDR_4th_CYCLE(data);
group-onsemi 0:098463de4c5d 378
group-onsemi 0:098463de4c5d 379 /* Update the NAND controller state */
group-onsemi 0:098463de4c5d 380 hnand->State = HAL_NAND_STATE_READY;
group-onsemi 0:098463de4c5d 381
group-onsemi 0:098463de4c5d 382 /* Process unlocked */
group-onsemi 0:098463de4c5d 383 __HAL_UNLOCK(hnand);
group-onsemi 0:098463de4c5d 384
group-onsemi 0:098463de4c5d 385 return HAL_OK;
group-onsemi 0:098463de4c5d 386 }
group-onsemi 0:098463de4c5d 387
group-onsemi 0:098463de4c5d 388 /**
group-onsemi 0:098463de4c5d 389 * @brief NAND memory reset
group-onsemi 0:098463de4c5d 390 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 391 * the configuration information for NAND module.
group-onsemi 0:098463de4c5d 392 * @retval HAL status
group-onsemi 0:098463de4c5d 393 */
group-onsemi 0:098463de4c5d 394 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
group-onsemi 0:098463de4c5d 395 {
group-onsemi 0:098463de4c5d 396 uint32_t deviceaddress = 0;
group-onsemi 0:098463de4c5d 397
group-onsemi 0:098463de4c5d 398 /* Process Locked */
group-onsemi 0:098463de4c5d 399 __HAL_LOCK(hnand);
group-onsemi 0:098463de4c5d 400
group-onsemi 0:098463de4c5d 401 /* Check the NAND controller state */
group-onsemi 0:098463de4c5d 402 if(hnand->State == HAL_NAND_STATE_BUSY)
group-onsemi 0:098463de4c5d 403 {
group-onsemi 0:098463de4c5d 404 return HAL_BUSY;
group-onsemi 0:098463de4c5d 405 }
group-onsemi 0:098463de4c5d 406
group-onsemi 0:098463de4c5d 407 /* Identify the device address */
group-onsemi 0:098463de4c5d 408 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
group-onsemi 0:098463de4c5d 409 {
group-onsemi 0:098463de4c5d 410 deviceaddress = NAND_DEVICE1;
group-onsemi 0:098463de4c5d 411 }
group-onsemi 0:098463de4c5d 412 else
group-onsemi 0:098463de4c5d 413 {
group-onsemi 0:098463de4c5d 414 deviceaddress = NAND_DEVICE2;
group-onsemi 0:098463de4c5d 415 }
group-onsemi 0:098463de4c5d 416
group-onsemi 0:098463de4c5d 417 /* Update the NAND controller state */
group-onsemi 0:098463de4c5d 418 hnand->State = HAL_NAND_STATE_BUSY;
group-onsemi 0:098463de4c5d 419
group-onsemi 0:098463de4c5d 420 /* Send NAND reset command */
group-onsemi 0:098463de4c5d 421 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
group-onsemi 0:098463de4c5d 422
group-onsemi 0:098463de4c5d 423
group-onsemi 0:098463de4c5d 424 /* Update the NAND controller state */
group-onsemi 0:098463de4c5d 425 hnand->State = HAL_NAND_STATE_READY;
group-onsemi 0:098463de4c5d 426
group-onsemi 0:098463de4c5d 427 /* Process unlocked */
group-onsemi 0:098463de4c5d 428 __HAL_UNLOCK(hnand);
group-onsemi 0:098463de4c5d 429
group-onsemi 0:098463de4c5d 430 return HAL_OK;
group-onsemi 0:098463de4c5d 431
group-onsemi 0:098463de4c5d 432 }
group-onsemi 0:098463de4c5d 433
group-onsemi 0:098463de4c5d 434 /**
group-onsemi 0:098463de4c5d 435 * @brief Read Page(s) from NAND memory block
group-onsemi 0:098463de4c5d 436 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 437 * the configuration information for NAND module.
group-onsemi 0:098463de4c5d 438 * @param pAddress : pointer to NAND address structure
group-onsemi 0:098463de4c5d 439 * @param pBuffer : pointer to destination read buffer
group-onsemi 0:098463de4c5d 440 * @param NumPageToRead : number of pages to read from block
group-onsemi 0:098463de4c5d 441 * @retval HAL status
group-onsemi 0:098463de4c5d 442 */
group-onsemi 0:098463de4c5d 443 HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
group-onsemi 0:098463de4c5d 444 {
group-onsemi 0:098463de4c5d 445 __IO uint32_t index = 0;
group-onsemi 0:098463de4c5d 446 uint32_t deviceaddress = 0, size = 0, numpagesread = 0, addressstatus = NAND_VALID_ADDRESS;
group-onsemi 0:098463de4c5d 447 NAND_AddressTypeDef nandaddress;
group-onsemi 0:098463de4c5d 448 uint32_t addressoffset = 0;
group-onsemi 0:098463de4c5d 449
group-onsemi 0:098463de4c5d 450 /* Process Locked */
group-onsemi 0:098463de4c5d 451 __HAL_LOCK(hnand);
group-onsemi 0:098463de4c5d 452
group-onsemi 0:098463de4c5d 453 /* Check the NAND controller state */
group-onsemi 0:098463de4c5d 454 if(hnand->State == HAL_NAND_STATE_BUSY)
group-onsemi 0:098463de4c5d 455 {
group-onsemi 0:098463de4c5d 456 return HAL_BUSY;
group-onsemi 0:098463de4c5d 457 }
group-onsemi 0:098463de4c5d 458
group-onsemi 0:098463de4c5d 459 /* Identify the device address */
group-onsemi 0:098463de4c5d 460 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
group-onsemi 0:098463de4c5d 461 {
group-onsemi 0:098463de4c5d 462 deviceaddress = NAND_DEVICE1;
group-onsemi 0:098463de4c5d 463 }
group-onsemi 0:098463de4c5d 464 else
group-onsemi 0:098463de4c5d 465 {
group-onsemi 0:098463de4c5d 466 deviceaddress = NAND_DEVICE2;
group-onsemi 0:098463de4c5d 467 }
group-onsemi 0:098463de4c5d 468
group-onsemi 0:098463de4c5d 469 /* Update the NAND controller state */
group-onsemi 0:098463de4c5d 470 hnand->State = HAL_NAND_STATE_BUSY;
group-onsemi 0:098463de4c5d 471
group-onsemi 0:098463de4c5d 472 /* Save the content of pAddress as it will be modified */
group-onsemi 0:098463de4c5d 473 nandaddress.Block = pAddress->Block;
group-onsemi 0:098463de4c5d 474 nandaddress.Page = pAddress->Page;
group-onsemi 0:098463de4c5d 475 nandaddress.Zone = pAddress->Zone;
group-onsemi 0:098463de4c5d 476
group-onsemi 0:098463de4c5d 477 /* Page(s) read loop */
group-onsemi 0:098463de4c5d 478 while((NumPageToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
group-onsemi 0:098463de4c5d 479 {
group-onsemi 0:098463de4c5d 480 /* update the buffer size */
group-onsemi 0:098463de4c5d 481 size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread);
group-onsemi 0:098463de4c5d 482
group-onsemi 0:098463de4c5d 483 /* Get the address offset */
group-onsemi 0:098463de4c5d 484 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
group-onsemi 0:098463de4c5d 485
group-onsemi 0:098463de4c5d 486 /* Send read page command sequence */
group-onsemi 0:098463de4c5d 487 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
group-onsemi 0:098463de4c5d 488
group-onsemi 0:098463de4c5d 489 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
group-onsemi 0:098463de4c5d 490 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1st_CYCLE(addressoffset);
group-onsemi 0:098463de4c5d 491 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2nd_CYCLE(addressoffset);
group-onsemi 0:098463de4c5d 492 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3rd_CYCLE(addressoffset);
group-onsemi 0:098463de4c5d 493
group-onsemi 0:098463de4c5d 494 /* for 512 and 1 GB devices, 4th cycle is required */
group-onsemi 0:098463de4c5d 495 if(hnand->Info.BlockNbr >= 1024)
group-onsemi 0:098463de4c5d 496 {
group-onsemi 0:098463de4c5d 497 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4th_CYCLE(addressoffset);
group-onsemi 0:098463de4c5d 498 }
group-onsemi 0:098463de4c5d 499
group-onsemi 0:098463de4c5d 500 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
group-onsemi 0:098463de4c5d 501
group-onsemi 0:098463de4c5d 502 /* Get Data into Buffer */
group-onsemi 0:098463de4c5d 503 for(; index < size; index++)
group-onsemi 0:098463de4c5d 504 {
group-onsemi 0:098463de4c5d 505 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
group-onsemi 0:098463de4c5d 506 }
group-onsemi 0:098463de4c5d 507
group-onsemi 0:098463de4c5d 508 /* Increment read pages number */
group-onsemi 0:098463de4c5d 509 numpagesread++;
group-onsemi 0:098463de4c5d 510
group-onsemi 0:098463de4c5d 511 /* Decrement pages to read */
group-onsemi 0:098463de4c5d 512 NumPageToRead--;
group-onsemi 0:098463de4c5d 513
group-onsemi 0:098463de4c5d 514 /* Increment the NAND address */
group-onsemi 0:098463de4c5d 515 addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
group-onsemi 0:098463de4c5d 516 }
group-onsemi 0:098463de4c5d 517
group-onsemi 0:098463de4c5d 518 /* Update the NAND controller state */
group-onsemi 0:098463de4c5d 519 hnand->State = HAL_NAND_STATE_READY;
group-onsemi 0:098463de4c5d 520
group-onsemi 0:098463de4c5d 521 /* Process unlocked */
group-onsemi 0:098463de4c5d 522 __HAL_UNLOCK(hnand);
group-onsemi 0:098463de4c5d 523
group-onsemi 0:098463de4c5d 524 return HAL_OK;
group-onsemi 0:098463de4c5d 525
group-onsemi 0:098463de4c5d 526 }
group-onsemi 0:098463de4c5d 527
group-onsemi 0:098463de4c5d 528 /**
group-onsemi 0:098463de4c5d 529 * @brief Write Page(s) to NAND memory block
group-onsemi 0:098463de4c5d 530 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 531 * the configuration information for NAND module.
group-onsemi 0:098463de4c5d 532 * @param pAddress : pointer to NAND address structure
group-onsemi 0:098463de4c5d 533 * @param pBuffer : pointer to source buffer to write
group-onsemi 0:098463de4c5d 534 * @param NumPageToWrite : number of pages to write to block
group-onsemi 0:098463de4c5d 535 * @retval HAL status
group-onsemi 0:098463de4c5d 536 */
group-onsemi 0:098463de4c5d 537 HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
group-onsemi 0:098463de4c5d 538 {
group-onsemi 0:098463de4c5d 539 __IO uint32_t index = 0;
group-onsemi 0:098463de4c5d 540 uint32_t tickstart = 0;
group-onsemi 0:098463de4c5d 541 uint32_t deviceaddress = 0 , size = 0, numpageswritten = 0, addressstatus = NAND_VALID_ADDRESS;
group-onsemi 0:098463de4c5d 542 NAND_AddressTypeDef nandaddress;
group-onsemi 0:098463de4c5d 543 uint32_t addressoffset = 0;
group-onsemi 0:098463de4c5d 544
group-onsemi 0:098463de4c5d 545 /* Process Locked */
group-onsemi 0:098463de4c5d 546 __HAL_LOCK(hnand);
group-onsemi 0:098463de4c5d 547
group-onsemi 0:098463de4c5d 548 /* Check the NAND controller state */
group-onsemi 0:098463de4c5d 549 if(hnand->State == HAL_NAND_STATE_BUSY)
group-onsemi 0:098463de4c5d 550 {
group-onsemi 0:098463de4c5d 551 return HAL_BUSY;
group-onsemi 0:098463de4c5d 552 }
group-onsemi 0:098463de4c5d 553
group-onsemi 0:098463de4c5d 554 /* Identify the device address */
group-onsemi 0:098463de4c5d 555 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
group-onsemi 0:098463de4c5d 556 {
group-onsemi 0:098463de4c5d 557 deviceaddress = NAND_DEVICE1;
group-onsemi 0:098463de4c5d 558 }
group-onsemi 0:098463de4c5d 559 else
group-onsemi 0:098463de4c5d 560 {
group-onsemi 0:098463de4c5d 561 deviceaddress = NAND_DEVICE2;
group-onsemi 0:098463de4c5d 562 }
group-onsemi 0:098463de4c5d 563
group-onsemi 0:098463de4c5d 564 /* Update the NAND controller state */
group-onsemi 0:098463de4c5d 565 hnand->State = HAL_NAND_STATE_BUSY;
group-onsemi 0:098463de4c5d 566
group-onsemi 0:098463de4c5d 567 /* Save the content of pAddress as it will be modified */
group-onsemi 0:098463de4c5d 568 nandaddress.Block = pAddress->Block;
group-onsemi 0:098463de4c5d 569 nandaddress.Page = pAddress->Page;
group-onsemi 0:098463de4c5d 570 nandaddress.Zone = pAddress->Zone;
group-onsemi 0:098463de4c5d 571
group-onsemi 0:098463de4c5d 572 /* Page(s) write loop */
group-onsemi 0:098463de4c5d 573 while((NumPageToWrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
group-onsemi 0:098463de4c5d 574 {
group-onsemi 0:098463de4c5d 575 /* update the buffer size */
group-onsemi 0:098463de4c5d 576 size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpageswritten);
group-onsemi 0:098463de4c5d 577
group-onsemi 0:098463de4c5d 578 /* Get the address offset */
group-onsemi 0:098463de4c5d 579 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
group-onsemi 0:098463de4c5d 580
group-onsemi 0:098463de4c5d 581 /* Send write page command sequence */
group-onsemi 0:098463de4c5d 582 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
group-onsemi 0:098463de4c5d 583 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
group-onsemi 0:098463de4c5d 584
group-onsemi 0:098463de4c5d 585 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
group-onsemi 0:098463de4c5d 586 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1st_CYCLE(addressoffset);
group-onsemi 0:098463de4c5d 587 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2nd_CYCLE(addressoffset);
group-onsemi 0:098463de4c5d 588 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3rd_CYCLE(addressoffset);
group-onsemi 0:098463de4c5d 589
group-onsemi 0:098463de4c5d 590 /* for 512 and 1 GB devices, 4th cycle is required */
group-onsemi 0:098463de4c5d 591 if(hnand->Info.BlockNbr >= 1024)
group-onsemi 0:098463de4c5d 592 {
group-onsemi 0:098463de4c5d 593 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4th_CYCLE(addressoffset);
group-onsemi 0:098463de4c5d 594 }
group-onsemi 0:098463de4c5d 595
group-onsemi 0:098463de4c5d 596 /* Write data to memory */
group-onsemi 0:098463de4c5d 597 for(; index < size; index++)
group-onsemi 0:098463de4c5d 598 {
group-onsemi 0:098463de4c5d 599 *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
group-onsemi 0:098463de4c5d 600 }
group-onsemi 0:098463de4c5d 601
group-onsemi 0:098463de4c5d 602 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
group-onsemi 0:098463de4c5d 603
group-onsemi 0:098463de4c5d 604 /* Get tick */
group-onsemi 0:098463de4c5d 605 tickstart = HAL_GetTick();
group-onsemi 0:098463de4c5d 606
group-onsemi 0:098463de4c5d 607 /* Read status until NAND is ready */
group-onsemi 0:098463de4c5d 608 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
group-onsemi 0:098463de4c5d 609 {
group-onsemi 0:098463de4c5d 610 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
group-onsemi 0:098463de4c5d 611 {
group-onsemi 0:098463de4c5d 612 return HAL_TIMEOUT;
group-onsemi 0:098463de4c5d 613 }
group-onsemi 0:098463de4c5d 614 }
group-onsemi 0:098463de4c5d 615
group-onsemi 0:098463de4c5d 616 /* Increment written pages number */
group-onsemi 0:098463de4c5d 617 numpageswritten++;
group-onsemi 0:098463de4c5d 618
group-onsemi 0:098463de4c5d 619 /* Decrement pages to write */
group-onsemi 0:098463de4c5d 620 NumPageToWrite--;
group-onsemi 0:098463de4c5d 621
group-onsemi 0:098463de4c5d 622 /* Increment the NAND address */
group-onsemi 0:098463de4c5d 623 addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
group-onsemi 0:098463de4c5d 624 }
group-onsemi 0:098463de4c5d 625
group-onsemi 0:098463de4c5d 626 /* Update the NAND controller state */
group-onsemi 0:098463de4c5d 627 hnand->State = HAL_NAND_STATE_READY;
group-onsemi 0:098463de4c5d 628
group-onsemi 0:098463de4c5d 629 /* Process unlocked */
group-onsemi 0:098463de4c5d 630 __HAL_UNLOCK(hnand);
group-onsemi 0:098463de4c5d 631
group-onsemi 0:098463de4c5d 632 return HAL_OK;
group-onsemi 0:098463de4c5d 633 }
group-onsemi 0:098463de4c5d 634
group-onsemi 0:098463de4c5d 635 /**
group-onsemi 0:098463de4c5d 636 * @brief Read Spare area(s) from NAND memory
group-onsemi 0:098463de4c5d 637 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 638 * the configuration information for NAND module.
group-onsemi 0:098463de4c5d 639 * @param pAddress : pointer to NAND address structure
group-onsemi 0:098463de4c5d 640 * @param pBuffer: pointer to source buffer to write
group-onsemi 0:098463de4c5d 641 * @param NumSpareAreaToRead: Number of spare area to read
group-onsemi 0:098463de4c5d 642 * @retval HAL status
group-onsemi 0:098463de4c5d 643 */
group-onsemi 0:098463de4c5d 644 HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
group-onsemi 0:098463de4c5d 645 {
group-onsemi 0:098463de4c5d 646 __IO uint32_t index = 0;
group-onsemi 0:098463de4c5d 647 uint32_t deviceaddress = 0, size = 0, num_spare_area_read = 0, addressstatus = NAND_VALID_ADDRESS;
group-onsemi 0:098463de4c5d 648 NAND_AddressTypeDef nandaddress;
group-onsemi 0:098463de4c5d 649 uint32_t addressoffset = 0;
group-onsemi 0:098463de4c5d 650
group-onsemi 0:098463de4c5d 651 /* Process Locked */
group-onsemi 0:098463de4c5d 652 __HAL_LOCK(hnand);
group-onsemi 0:098463de4c5d 653
group-onsemi 0:098463de4c5d 654 /* Check the NAND controller state */
group-onsemi 0:098463de4c5d 655 if(hnand->State == HAL_NAND_STATE_BUSY)
group-onsemi 0:098463de4c5d 656 {
group-onsemi 0:098463de4c5d 657 return HAL_BUSY;
group-onsemi 0:098463de4c5d 658 }
group-onsemi 0:098463de4c5d 659
group-onsemi 0:098463de4c5d 660 /* Identify the device address */
group-onsemi 0:098463de4c5d 661 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
group-onsemi 0:098463de4c5d 662 {
group-onsemi 0:098463de4c5d 663 deviceaddress = NAND_DEVICE1;
group-onsemi 0:098463de4c5d 664 }
group-onsemi 0:098463de4c5d 665 else
group-onsemi 0:098463de4c5d 666 {
group-onsemi 0:098463de4c5d 667 deviceaddress = NAND_DEVICE2;
group-onsemi 0:098463de4c5d 668 }
group-onsemi 0:098463de4c5d 669
group-onsemi 0:098463de4c5d 670 /* Update the NAND controller state */
group-onsemi 0:098463de4c5d 671 hnand->State = HAL_NAND_STATE_BUSY;
group-onsemi 0:098463de4c5d 672
group-onsemi 0:098463de4c5d 673 /* Save the content of pAddress as it will be modified */
group-onsemi 0:098463de4c5d 674 nandaddress.Block = pAddress->Block;
group-onsemi 0:098463de4c5d 675 nandaddress.Page = pAddress->Page;
group-onsemi 0:098463de4c5d 676 nandaddress.Zone = pAddress->Zone;
group-onsemi 0:098463de4c5d 677
group-onsemi 0:098463de4c5d 678 /* Spare area(s) read loop */
group-onsemi 0:098463de4c5d 679 while((NumSpareAreaToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
group-onsemi 0:098463de4c5d 680 {
group-onsemi 0:098463de4c5d 681 /* update the buffer size */
group-onsemi 0:098463de4c5d 682 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read);
group-onsemi 0:098463de4c5d 683
group-onsemi 0:098463de4c5d 684 /* Get the address offset */
group-onsemi 0:098463de4c5d 685 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
group-onsemi 0:098463de4c5d 686
group-onsemi 0:098463de4c5d 687 /* Send read spare area command sequence */
group-onsemi 0:098463de4c5d 688 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
group-onsemi 0:098463de4c5d 689
group-onsemi 0:098463de4c5d 690 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
group-onsemi 0:098463de4c5d 691 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1st_CYCLE(addressoffset);
group-onsemi 0:098463de4c5d 692 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2nd_CYCLE(addressoffset);
group-onsemi 0:098463de4c5d 693 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3rd_CYCLE(addressoffset);
group-onsemi 0:098463de4c5d 694
group-onsemi 0:098463de4c5d 695 /* for 512 and 1 GB devices, 4th cycle is required */
group-onsemi 0:098463de4c5d 696 if(hnand->Info.BlockNbr >= 1024)
group-onsemi 0:098463de4c5d 697 {
group-onsemi 0:098463de4c5d 698 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4th_CYCLE(addressoffset);
group-onsemi 0:098463de4c5d 699 }
group-onsemi 0:098463de4c5d 700
group-onsemi 0:098463de4c5d 701 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
group-onsemi 0:098463de4c5d 702
group-onsemi 0:098463de4c5d 703 /* Get Data into Buffer */
group-onsemi 0:098463de4c5d 704 for ( ;index < size; index++)
group-onsemi 0:098463de4c5d 705 {
group-onsemi 0:098463de4c5d 706 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
group-onsemi 0:098463de4c5d 707 }
group-onsemi 0:098463de4c5d 708
group-onsemi 0:098463de4c5d 709 /* Increment read spare areas number */
group-onsemi 0:098463de4c5d 710 num_spare_area_read++;
group-onsemi 0:098463de4c5d 711
group-onsemi 0:098463de4c5d 712 /* Decrement spare areas to read */
group-onsemi 0:098463de4c5d 713 NumSpareAreaToRead--;
group-onsemi 0:098463de4c5d 714
group-onsemi 0:098463de4c5d 715 /* Increment the NAND address */
group-onsemi 0:098463de4c5d 716 addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
group-onsemi 0:098463de4c5d 717 }
group-onsemi 0:098463de4c5d 718
group-onsemi 0:098463de4c5d 719 /* Update the NAND controller state */
group-onsemi 0:098463de4c5d 720 hnand->State = HAL_NAND_STATE_READY;
group-onsemi 0:098463de4c5d 721
group-onsemi 0:098463de4c5d 722 /* Process unlocked */
group-onsemi 0:098463de4c5d 723 __HAL_UNLOCK(hnand);
group-onsemi 0:098463de4c5d 724
group-onsemi 0:098463de4c5d 725 return HAL_OK;
group-onsemi 0:098463de4c5d 726 }
group-onsemi 0:098463de4c5d 727
group-onsemi 0:098463de4c5d 728 /**
group-onsemi 0:098463de4c5d 729 * @brief Write Spare area(s) to NAND memory
group-onsemi 0:098463de4c5d 730 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 731 * the configuration information for NAND module.
group-onsemi 0:098463de4c5d 732 * @param pAddress : pointer to NAND address structure
group-onsemi 0:098463de4c5d 733 * @param pBuffer : pointer to source buffer to write
group-onsemi 0:098463de4c5d 734 * @param NumSpareAreaTowrite : number of spare areas to write to block
group-onsemi 0:098463de4c5d 735 * @retval HAL status
group-onsemi 0:098463de4c5d 736 */
group-onsemi 0:098463de4c5d 737 HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
group-onsemi 0:098463de4c5d 738 {
group-onsemi 0:098463de4c5d 739 __IO uint32_t index = 0;
group-onsemi 0:098463de4c5d 740 uint32_t tickstart = 0;
group-onsemi 0:098463de4c5d 741 uint32_t deviceaddress = 0, size = 0, num_spare_area_written = 0, addressstatus = NAND_VALID_ADDRESS;
group-onsemi 0:098463de4c5d 742 NAND_AddressTypeDef nandaddress;
group-onsemi 0:098463de4c5d 743 uint32_t addressoffset = 0;
group-onsemi 0:098463de4c5d 744
group-onsemi 0:098463de4c5d 745 /* Process Locked */
group-onsemi 0:098463de4c5d 746 __HAL_LOCK(hnand);
group-onsemi 0:098463de4c5d 747
group-onsemi 0:098463de4c5d 748 /* Check the NAND controller state */
group-onsemi 0:098463de4c5d 749 if(hnand->State == HAL_NAND_STATE_BUSY)
group-onsemi 0:098463de4c5d 750 {
group-onsemi 0:098463de4c5d 751 return HAL_BUSY;
group-onsemi 0:098463de4c5d 752 }
group-onsemi 0:098463de4c5d 753
group-onsemi 0:098463de4c5d 754 /* Identify the device address */
group-onsemi 0:098463de4c5d 755 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
group-onsemi 0:098463de4c5d 756 {
group-onsemi 0:098463de4c5d 757 deviceaddress = NAND_DEVICE1;
group-onsemi 0:098463de4c5d 758 }
group-onsemi 0:098463de4c5d 759 else
group-onsemi 0:098463de4c5d 760 {
group-onsemi 0:098463de4c5d 761 deviceaddress = NAND_DEVICE2;
group-onsemi 0:098463de4c5d 762 }
group-onsemi 0:098463de4c5d 763
group-onsemi 0:098463de4c5d 764 /* Update the FSMC_NAND controller state */
group-onsemi 0:098463de4c5d 765 hnand->State = HAL_NAND_STATE_BUSY;
group-onsemi 0:098463de4c5d 766
group-onsemi 0:098463de4c5d 767 /* Save the content of pAddress as it will be modified */
group-onsemi 0:098463de4c5d 768 nandaddress.Block = pAddress->Block;
group-onsemi 0:098463de4c5d 769 nandaddress.Page = pAddress->Page;
group-onsemi 0:098463de4c5d 770 nandaddress.Zone = pAddress->Zone;
group-onsemi 0:098463de4c5d 771
group-onsemi 0:098463de4c5d 772 /* Spare area(s) write loop */
group-onsemi 0:098463de4c5d 773 while((NumSpareAreaTowrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
group-onsemi 0:098463de4c5d 774 {
group-onsemi 0:098463de4c5d 775 /* update the buffer size */
group-onsemi 0:098463de4c5d 776 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written);
group-onsemi 0:098463de4c5d 777
group-onsemi 0:098463de4c5d 778 /* Get the address offset */
group-onsemi 0:098463de4c5d 779 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
group-onsemi 0:098463de4c5d 780
group-onsemi 0:098463de4c5d 781 /* Send write Spare area command sequence */
group-onsemi 0:098463de4c5d 782 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
group-onsemi 0:098463de4c5d 783 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
group-onsemi 0:098463de4c5d 784
group-onsemi 0:098463de4c5d 785 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
group-onsemi 0:098463de4c5d 786 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1st_CYCLE(addressoffset);
group-onsemi 0:098463de4c5d 787 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2nd_CYCLE(addressoffset);
group-onsemi 0:098463de4c5d 788 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3rd_CYCLE(addressoffset);
group-onsemi 0:098463de4c5d 789
group-onsemi 0:098463de4c5d 790 /* for 512 and 1 GB devices, 4th cycle is required */
group-onsemi 0:098463de4c5d 791 if(hnand->Info.BlockNbr >= 1024)
group-onsemi 0:098463de4c5d 792 {
group-onsemi 0:098463de4c5d 793 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4th_CYCLE(addressoffset);
group-onsemi 0:098463de4c5d 794 }
group-onsemi 0:098463de4c5d 795
group-onsemi 0:098463de4c5d 796 /* Write data to memory */
group-onsemi 0:098463de4c5d 797 for(; index < size; index++)
group-onsemi 0:098463de4c5d 798 {
group-onsemi 0:098463de4c5d 799 *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
group-onsemi 0:098463de4c5d 800 }
group-onsemi 0:098463de4c5d 801
group-onsemi 0:098463de4c5d 802 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
group-onsemi 0:098463de4c5d 803
group-onsemi 0:098463de4c5d 804 /* Get tick */
group-onsemi 0:098463de4c5d 805 tickstart = HAL_GetTick();
group-onsemi 0:098463de4c5d 806
group-onsemi 0:098463de4c5d 807 /* Read status until NAND is ready */
group-onsemi 0:098463de4c5d 808 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
group-onsemi 0:098463de4c5d 809 {
group-onsemi 0:098463de4c5d 810 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
group-onsemi 0:098463de4c5d 811 {
group-onsemi 0:098463de4c5d 812 return HAL_TIMEOUT;
group-onsemi 0:098463de4c5d 813 }
group-onsemi 0:098463de4c5d 814 }
group-onsemi 0:098463de4c5d 815
group-onsemi 0:098463de4c5d 816 /* Increment written spare areas number */
group-onsemi 0:098463de4c5d 817 num_spare_area_written++;
group-onsemi 0:098463de4c5d 818
group-onsemi 0:098463de4c5d 819 /* Decrement spare areas to write */
group-onsemi 0:098463de4c5d 820 NumSpareAreaTowrite--;
group-onsemi 0:098463de4c5d 821
group-onsemi 0:098463de4c5d 822 /* Increment the NAND address */
group-onsemi 0:098463de4c5d 823 addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
group-onsemi 0:098463de4c5d 824 }
group-onsemi 0:098463de4c5d 825
group-onsemi 0:098463de4c5d 826 /* Update the NAND controller state */
group-onsemi 0:098463de4c5d 827 hnand->State = HAL_NAND_STATE_READY;
group-onsemi 0:098463de4c5d 828
group-onsemi 0:098463de4c5d 829 /* Process unlocked */
group-onsemi 0:098463de4c5d 830 __HAL_UNLOCK(hnand);
group-onsemi 0:098463de4c5d 831
group-onsemi 0:098463de4c5d 832 return HAL_OK;
group-onsemi 0:098463de4c5d 833 }
group-onsemi 0:098463de4c5d 834
group-onsemi 0:098463de4c5d 835 /**
group-onsemi 0:098463de4c5d 836 * @brief NAND memory Block erase
group-onsemi 0:098463de4c5d 837 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 838 * the configuration information for NAND module.
group-onsemi 0:098463de4c5d 839 * @param pAddress : pointer to NAND address structure
group-onsemi 0:098463de4c5d 840 * @retval HAL status
group-onsemi 0:098463de4c5d 841 */
group-onsemi 0:098463de4c5d 842 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
group-onsemi 0:098463de4c5d 843 {
group-onsemi 0:098463de4c5d 844 uint32_t deviceaddress = 0;
group-onsemi 0:098463de4c5d 845 uint32_t tickstart = 0;
group-onsemi 0:098463de4c5d 846
group-onsemi 0:098463de4c5d 847 /* Process Locked */
group-onsemi 0:098463de4c5d 848 __HAL_LOCK(hnand);
group-onsemi 0:098463de4c5d 849
group-onsemi 0:098463de4c5d 850 /* Check the NAND controller state */
group-onsemi 0:098463de4c5d 851 if(hnand->State == HAL_NAND_STATE_BUSY)
group-onsemi 0:098463de4c5d 852 {
group-onsemi 0:098463de4c5d 853 return HAL_BUSY;
group-onsemi 0:098463de4c5d 854 }
group-onsemi 0:098463de4c5d 855
group-onsemi 0:098463de4c5d 856 /* Identify the device address */
group-onsemi 0:098463de4c5d 857 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
group-onsemi 0:098463de4c5d 858 {
group-onsemi 0:098463de4c5d 859 deviceaddress = NAND_DEVICE1;
group-onsemi 0:098463de4c5d 860 }
group-onsemi 0:098463de4c5d 861 else
group-onsemi 0:098463de4c5d 862 {
group-onsemi 0:098463de4c5d 863 deviceaddress = NAND_DEVICE2;
group-onsemi 0:098463de4c5d 864 }
group-onsemi 0:098463de4c5d 865
group-onsemi 0:098463de4c5d 866 /* Update the NAND controller state */
group-onsemi 0:098463de4c5d 867 hnand->State = HAL_NAND_STATE_BUSY;
group-onsemi 0:098463de4c5d 868
group-onsemi 0:098463de4c5d 869 /* Send Erase block command sequence */
group-onsemi 0:098463de4c5d 870 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
group-onsemi 0:098463de4c5d 871
group-onsemi 0:098463de4c5d 872 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1st_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
group-onsemi 0:098463de4c5d 873 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2nd_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
group-onsemi 0:098463de4c5d 874 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3rd_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
group-onsemi 0:098463de4c5d 875
group-onsemi 0:098463de4c5d 876 /* for 512 and 1 GB devices, 4th cycle is required */
group-onsemi 0:098463de4c5d 877 if(hnand->Info.BlockNbr >= 1024)
group-onsemi 0:098463de4c5d 878 {
group-onsemi 0:098463de4c5d 879 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4th_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
group-onsemi 0:098463de4c5d 880 }
group-onsemi 0:098463de4c5d 881
group-onsemi 0:098463de4c5d 882 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
group-onsemi 0:098463de4c5d 883
group-onsemi 0:098463de4c5d 884 /* Update the NAND controller state */
group-onsemi 0:098463de4c5d 885 hnand->State = HAL_NAND_STATE_READY;
group-onsemi 0:098463de4c5d 886
group-onsemi 0:098463de4c5d 887 /* Get tick */
group-onsemi 0:098463de4c5d 888 tickstart = HAL_GetTick();
group-onsemi 0:098463de4c5d 889
group-onsemi 0:098463de4c5d 890 /* Read status until NAND is ready */
group-onsemi 0:098463de4c5d 891 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
group-onsemi 0:098463de4c5d 892 {
group-onsemi 0:098463de4c5d 893 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
group-onsemi 0:098463de4c5d 894 {
group-onsemi 0:098463de4c5d 895 /* Process unlocked */
group-onsemi 0:098463de4c5d 896 __HAL_UNLOCK(hnand);
group-onsemi 0:098463de4c5d 897
group-onsemi 0:098463de4c5d 898 return HAL_TIMEOUT;
group-onsemi 0:098463de4c5d 899 }
group-onsemi 0:098463de4c5d 900 }
group-onsemi 0:098463de4c5d 901
group-onsemi 0:098463de4c5d 902 /* Process unlocked */
group-onsemi 0:098463de4c5d 903 __HAL_UNLOCK(hnand);
group-onsemi 0:098463de4c5d 904
group-onsemi 0:098463de4c5d 905 return HAL_OK;
group-onsemi 0:098463de4c5d 906 }
group-onsemi 0:098463de4c5d 907
group-onsemi 0:098463de4c5d 908 /**
group-onsemi 0:098463de4c5d 909 * @brief NAND memory read status
group-onsemi 0:098463de4c5d 910 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 911 * the configuration information for NAND module.
group-onsemi 0:098463de4c5d 912 * @retval NAND status
group-onsemi 0:098463de4c5d 913 */
group-onsemi 0:098463de4c5d 914 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
group-onsemi 0:098463de4c5d 915 {
group-onsemi 0:098463de4c5d 916 uint32_t data = 0;
group-onsemi 0:098463de4c5d 917 uint32_t deviceaddress = 0;
group-onsemi 0:098463de4c5d 918
group-onsemi 0:098463de4c5d 919 /* Identify the device address */
group-onsemi 0:098463de4c5d 920 if(hnand->Init.NandBank == FSMC_NAND_BANK2)
group-onsemi 0:098463de4c5d 921 {
group-onsemi 0:098463de4c5d 922 deviceaddress = NAND_DEVICE1;
group-onsemi 0:098463de4c5d 923 }
group-onsemi 0:098463de4c5d 924 else
group-onsemi 0:098463de4c5d 925 {
group-onsemi 0:098463de4c5d 926 deviceaddress = NAND_DEVICE2;
group-onsemi 0:098463de4c5d 927 }
group-onsemi 0:098463de4c5d 928
group-onsemi 0:098463de4c5d 929 /* Send Read status operation command */
group-onsemi 0:098463de4c5d 930 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
group-onsemi 0:098463de4c5d 931
group-onsemi 0:098463de4c5d 932 /* Read status register data */
group-onsemi 0:098463de4c5d 933 data = *(__IO uint8_t *)deviceaddress;
group-onsemi 0:098463de4c5d 934
group-onsemi 0:098463de4c5d 935 /* Return the status */
group-onsemi 0:098463de4c5d 936 if((data & NAND_ERROR) == NAND_ERROR)
group-onsemi 0:098463de4c5d 937 {
group-onsemi 0:098463de4c5d 938 return NAND_ERROR;
group-onsemi 0:098463de4c5d 939 }
group-onsemi 0:098463de4c5d 940 else if((data & NAND_READY) == NAND_READY)
group-onsemi 0:098463de4c5d 941 {
group-onsemi 0:098463de4c5d 942 return NAND_READY;
group-onsemi 0:098463de4c5d 943 }
group-onsemi 0:098463de4c5d 944
group-onsemi 0:098463de4c5d 945 return NAND_BUSY;
group-onsemi 0:098463de4c5d 946 }
group-onsemi 0:098463de4c5d 947
group-onsemi 0:098463de4c5d 948 /**
group-onsemi 0:098463de4c5d 949 * @brief Increment the NAND memory address
group-onsemi 0:098463de4c5d 950 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 951 * the configuration information for NAND module.
group-onsemi 0:098463de4c5d 952 * @param pAddress: pointer to NAND address structure
group-onsemi 0:098463de4c5d 953 * @retval The new status of the increment address operation. It can be:
group-onsemi 0:098463de4c5d 954 * - NAND_VALID_ADDRESS: When the new address is valid address
group-onsemi 0:098463de4c5d 955 * - NAND_INVALID_ADDRESS: When the new address is invalid address
group-onsemi 0:098463de4c5d 956 */
group-onsemi 0:098463de4c5d 957 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
group-onsemi 0:098463de4c5d 958 {
group-onsemi 0:098463de4c5d 959 uint32_t status = NAND_VALID_ADDRESS;
group-onsemi 0:098463de4c5d 960
group-onsemi 0:098463de4c5d 961 /* Increment page address */
group-onsemi 0:098463de4c5d 962 pAddress->Page++;
group-onsemi 0:098463de4c5d 963
group-onsemi 0:098463de4c5d 964 /* Check NAND address is valid */
group-onsemi 0:098463de4c5d 965 if(pAddress->Page == hnand->Info.BlockSize)
group-onsemi 0:098463de4c5d 966 {
group-onsemi 0:098463de4c5d 967 pAddress->Page = 0;
group-onsemi 0:098463de4c5d 968 pAddress->Block++;
group-onsemi 0:098463de4c5d 969
group-onsemi 0:098463de4c5d 970 if(pAddress->Block == hnand->Info.ZoneSize)
group-onsemi 0:098463de4c5d 971 {
group-onsemi 0:098463de4c5d 972 pAddress->Block = 0;
group-onsemi 0:098463de4c5d 973 pAddress->Zone++;
group-onsemi 0:098463de4c5d 974
group-onsemi 0:098463de4c5d 975 if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))
group-onsemi 0:098463de4c5d 976 {
group-onsemi 0:098463de4c5d 977 status = NAND_INVALID_ADDRESS;
group-onsemi 0:098463de4c5d 978 }
group-onsemi 0:098463de4c5d 979 }
group-onsemi 0:098463de4c5d 980 }
group-onsemi 0:098463de4c5d 981
group-onsemi 0:098463de4c5d 982 return (status);
group-onsemi 0:098463de4c5d 983 }
group-onsemi 0:098463de4c5d 984 /**
group-onsemi 0:098463de4c5d 985 * @}
group-onsemi 0:098463de4c5d 986 */
group-onsemi 0:098463de4c5d 987
group-onsemi 0:098463de4c5d 988 /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
group-onsemi 0:098463de4c5d 989 * @brief management functions
group-onsemi 0:098463de4c5d 990 *
group-onsemi 0:098463de4c5d 991 @verbatim
group-onsemi 0:098463de4c5d 992 ==============================================================================
group-onsemi 0:098463de4c5d 993 ##### NAND Control functions #####
group-onsemi 0:098463de4c5d 994 ==============================================================================
group-onsemi 0:098463de4c5d 995 [..]
group-onsemi 0:098463de4c5d 996 This subsection provides a set of functions allowing to control dynamically
group-onsemi 0:098463de4c5d 997 the NAND interface.
group-onsemi 0:098463de4c5d 998
group-onsemi 0:098463de4c5d 999 @endverbatim
group-onsemi 0:098463de4c5d 1000 * @{
group-onsemi 0:098463de4c5d 1001 */
group-onsemi 0:098463de4c5d 1002
group-onsemi 0:098463de4c5d 1003
group-onsemi 0:098463de4c5d 1004 /**
group-onsemi 0:098463de4c5d 1005 * @brief Enables dynamically NAND ECC feature.
group-onsemi 0:098463de4c5d 1006 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 1007 * the configuration information for NAND module.
group-onsemi 0:098463de4c5d 1008 * @retval HAL status
group-onsemi 0:098463de4c5d 1009 */
group-onsemi 0:098463de4c5d 1010 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
group-onsemi 0:098463de4c5d 1011 {
group-onsemi 0:098463de4c5d 1012 /* Check the NAND controller state */
group-onsemi 0:098463de4c5d 1013 if(hnand->State == HAL_NAND_STATE_BUSY)
group-onsemi 0:098463de4c5d 1014 {
group-onsemi 0:098463de4c5d 1015 return HAL_BUSY;
group-onsemi 0:098463de4c5d 1016 }
group-onsemi 0:098463de4c5d 1017
group-onsemi 0:098463de4c5d 1018 /* Update the NAND state */
group-onsemi 0:098463de4c5d 1019 hnand->State = HAL_NAND_STATE_BUSY;
group-onsemi 0:098463de4c5d 1020
group-onsemi 0:098463de4c5d 1021 /* Enable ECC feature */
group-onsemi 0:098463de4c5d 1022 FSMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
group-onsemi 0:098463de4c5d 1023
group-onsemi 0:098463de4c5d 1024 /* Update the NAND state */
group-onsemi 0:098463de4c5d 1025 hnand->State = HAL_NAND_STATE_READY;
group-onsemi 0:098463de4c5d 1026
group-onsemi 0:098463de4c5d 1027 return HAL_OK;
group-onsemi 0:098463de4c5d 1028 }
group-onsemi 0:098463de4c5d 1029
group-onsemi 0:098463de4c5d 1030 /**
group-onsemi 0:098463de4c5d 1031 * @brief Disables dynamically FSMC_NAND ECC feature.
group-onsemi 0:098463de4c5d 1032 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 1033 * the configuration information for NAND module.
group-onsemi 0:098463de4c5d 1034 * @retval HAL status
group-onsemi 0:098463de4c5d 1035 */
group-onsemi 0:098463de4c5d 1036 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
group-onsemi 0:098463de4c5d 1037 {
group-onsemi 0:098463de4c5d 1038 /* Check the NAND controller state */
group-onsemi 0:098463de4c5d 1039 if(hnand->State == HAL_NAND_STATE_BUSY)
group-onsemi 0:098463de4c5d 1040 {
group-onsemi 0:098463de4c5d 1041 return HAL_BUSY;
group-onsemi 0:098463de4c5d 1042 }
group-onsemi 0:098463de4c5d 1043
group-onsemi 0:098463de4c5d 1044 /* Update the NAND state */
group-onsemi 0:098463de4c5d 1045 hnand->State = HAL_NAND_STATE_BUSY;
group-onsemi 0:098463de4c5d 1046
group-onsemi 0:098463de4c5d 1047 /* Disable ECC feature */
group-onsemi 0:098463de4c5d 1048 FSMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
group-onsemi 0:098463de4c5d 1049
group-onsemi 0:098463de4c5d 1050 /* Update the NAND state */
group-onsemi 0:098463de4c5d 1051 hnand->State = HAL_NAND_STATE_READY;
group-onsemi 0:098463de4c5d 1052
group-onsemi 0:098463de4c5d 1053 return HAL_OK;
group-onsemi 0:098463de4c5d 1054 }
group-onsemi 0:098463de4c5d 1055
group-onsemi 0:098463de4c5d 1056 /**
group-onsemi 0:098463de4c5d 1057 * @brief Disables dynamically NAND ECC feature.
group-onsemi 0:098463de4c5d 1058 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 1059 * the configuration information for NAND module.
group-onsemi 0:098463de4c5d 1060 * @param ECCval: pointer to ECC value
group-onsemi 0:098463de4c5d 1061 * @param Timeout: maximum timeout to wait
group-onsemi 0:098463de4c5d 1062 * @retval HAL status
group-onsemi 0:098463de4c5d 1063 */
group-onsemi 0:098463de4c5d 1064 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
group-onsemi 0:098463de4c5d 1065 {
group-onsemi 0:098463de4c5d 1066 HAL_StatusTypeDef status = HAL_OK;
group-onsemi 0:098463de4c5d 1067
group-onsemi 0:098463de4c5d 1068 /* Check the NAND controller state */
group-onsemi 0:098463de4c5d 1069 if(hnand->State == HAL_NAND_STATE_BUSY)
group-onsemi 0:098463de4c5d 1070 {
group-onsemi 0:098463de4c5d 1071 return HAL_BUSY;
group-onsemi 0:098463de4c5d 1072 }
group-onsemi 0:098463de4c5d 1073
group-onsemi 0:098463de4c5d 1074 /* Update the NAND state */
group-onsemi 0:098463de4c5d 1075 hnand->State = HAL_NAND_STATE_BUSY;
group-onsemi 0:098463de4c5d 1076
group-onsemi 0:098463de4c5d 1077 /* Get NAND ECC value */
group-onsemi 0:098463de4c5d 1078 status = FSMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
group-onsemi 0:098463de4c5d 1079
group-onsemi 0:098463de4c5d 1080 /* Update the NAND state */
group-onsemi 0:098463de4c5d 1081 hnand->State = HAL_NAND_STATE_READY;
group-onsemi 0:098463de4c5d 1082
group-onsemi 0:098463de4c5d 1083 return status;
group-onsemi 0:098463de4c5d 1084 }
group-onsemi 0:098463de4c5d 1085
group-onsemi 0:098463de4c5d 1086 /**
group-onsemi 0:098463de4c5d 1087 * @}
group-onsemi 0:098463de4c5d 1088 */
group-onsemi 0:098463de4c5d 1089
group-onsemi 0:098463de4c5d 1090
group-onsemi 0:098463de4c5d 1091 /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
group-onsemi 0:098463de4c5d 1092 * @brief Peripheral State functions
group-onsemi 0:098463de4c5d 1093 *
group-onsemi 0:098463de4c5d 1094 @verbatim
group-onsemi 0:098463de4c5d 1095 ==============================================================================
group-onsemi 0:098463de4c5d 1096 ##### NAND State functions #####
group-onsemi 0:098463de4c5d 1097 ==============================================================================
group-onsemi 0:098463de4c5d 1098 [..]
group-onsemi 0:098463de4c5d 1099 This subsection permits to get in run-time the status of the NAND controller
group-onsemi 0:098463de4c5d 1100 and the data flow.
group-onsemi 0:098463de4c5d 1101
group-onsemi 0:098463de4c5d 1102 @endverbatim
group-onsemi 0:098463de4c5d 1103 * @{
group-onsemi 0:098463de4c5d 1104 */
group-onsemi 0:098463de4c5d 1105
group-onsemi 0:098463de4c5d 1106 /**
group-onsemi 0:098463de4c5d 1107 * @brief return the NAND state
group-onsemi 0:098463de4c5d 1108 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 1109 * the configuration information for NAND module.
group-onsemi 0:098463de4c5d 1110 * @retval HAL state
group-onsemi 0:098463de4c5d 1111 */
group-onsemi 0:098463de4c5d 1112 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
group-onsemi 0:098463de4c5d 1113 {
group-onsemi 0:098463de4c5d 1114 return hnand->State;
group-onsemi 0:098463de4c5d 1115 }
group-onsemi 0:098463de4c5d 1116
group-onsemi 0:098463de4c5d 1117 /**
group-onsemi 0:098463de4c5d 1118 * @}
group-onsemi 0:098463de4c5d 1119 */
group-onsemi 0:098463de4c5d 1120
group-onsemi 0:098463de4c5d 1121 /**
group-onsemi 0:098463de4c5d 1122 * @}
group-onsemi 0:098463de4c5d 1123 */
group-onsemi 0:098463de4c5d 1124
group-onsemi 0:098463de4c5d 1125 /** @addtogroup NAND_Private_Functions
group-onsemi 0:098463de4c5d 1126 * @{
group-onsemi 0:098463de4c5d 1127 */
group-onsemi 0:098463de4c5d 1128
group-onsemi 0:098463de4c5d 1129 /**
group-onsemi 0:098463de4c5d 1130 * @brief Increment the NAND memory address.
group-onsemi 0:098463de4c5d 1131 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
group-onsemi 0:098463de4c5d 1132 * the configuration information for NAND module.
group-onsemi 0:098463de4c5d 1133 * @param Address: address to be incremented.
group-onsemi 0:098463de4c5d 1134 * @retval The new status of the increment address operation. It can be:
group-onsemi 0:098463de4c5d 1135 * - NAND_VALID_ADDRESS: When the new address is valid address
group-onsemi 0:098463de4c5d 1136 * - NAND_INVALID_ADDRESS: When the new address is invalid address
group-onsemi 0:098463de4c5d 1137 */
group-onsemi 0:098463de4c5d 1138 static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address)
group-onsemi 0:098463de4c5d 1139 {
group-onsemi 0:098463de4c5d 1140 uint32_t status = NAND_VALID_ADDRESS;
group-onsemi 0:098463de4c5d 1141
group-onsemi 0:098463de4c5d 1142 Address->Page++;
group-onsemi 0:098463de4c5d 1143
group-onsemi 0:098463de4c5d 1144 if(Address->Page == hnand->Info.BlockSize)
group-onsemi 0:098463de4c5d 1145 {
group-onsemi 0:098463de4c5d 1146 Address->Page = 0;
group-onsemi 0:098463de4c5d 1147 Address->Block++;
group-onsemi 0:098463de4c5d 1148
group-onsemi 0:098463de4c5d 1149 if(Address->Block == hnand->Info.ZoneSize)
group-onsemi 0:098463de4c5d 1150 {
group-onsemi 0:098463de4c5d 1151 Address->Block = 0;
group-onsemi 0:098463de4c5d 1152 Address->Zone++;
group-onsemi 0:098463de4c5d 1153
group-onsemi 0:098463de4c5d 1154 if(Address->Zone == hnand->Info.BlockNbr)
group-onsemi 0:098463de4c5d 1155 {
group-onsemi 0:098463de4c5d 1156 status = NAND_INVALID_ADDRESS;
group-onsemi 0:098463de4c5d 1157 }
group-onsemi 0:098463de4c5d 1158 }
group-onsemi 0:098463de4c5d 1159 }
group-onsemi 0:098463de4c5d 1160
group-onsemi 0:098463de4c5d 1161 return (status);
group-onsemi 0:098463de4c5d 1162 }
group-onsemi 0:098463de4c5d 1163
group-onsemi 0:098463de4c5d 1164 /**
group-onsemi 0:098463de4c5d 1165 * @}
group-onsemi 0:098463de4c5d 1166 */
group-onsemi 0:098463de4c5d 1167
group-onsemi 0:098463de4c5d 1168 /**
group-onsemi 0:098463de4c5d 1169 * @}
group-onsemi 0:098463de4c5d 1170 */
group-onsemi 0:098463de4c5d 1171
group-onsemi 0:098463de4c5d 1172 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
group-onsemi 0:098463de4c5d 1173 #endif /* HAL_NAND_MODULE_ENABLED */
group-onsemi 0:098463de4c5d 1174
group-onsemi 0:098463de4c5d 1175 /**
group-onsemi 0:098463de4c5d 1176 * @}
group-onsemi 0:098463de4c5d 1177 */
group-onsemi 0:098463de4c5d 1178
group-onsemi 0:098463de4c5d 1179 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/