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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_ONSEMI/TARGET_NCS36510/serial_api.c@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /**
group-onsemi 0:098463de4c5d 2 ******************************************************************************
group-onsemi 0:098463de4c5d 3 * @file Serial.c
group-onsemi 0:098463de4c5d 4 * @brief Implementation of a 16C550 UART driver
group-onsemi 0:098463de4c5d 5 * @internal
group-onsemi 0:098463de4c5d 6 * @author ON Semiconductor
group-onsemi 0:098463de4c5d 7 * $Rev: 0.1 $
group-onsemi 0:098463de4c5d 8 * $Date: 2015-11-04 05:30:00 +0530 (Wed, 04 Nov 2015) $
group-onsemi 0:098463de4c5d 9 ******************************************************************************
group-onsemi 0:098463de4c5d 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
group-onsemi 0:098463de4c5d 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
group-onsemi 0:098463de4c5d 12 * under limited terms and conditions. The terms and conditions pertaining to the software
group-onsemi 0:098463de4c5d 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
group-onsemi 0:098463de4c5d 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
group-onsemi 0:098463de4c5d 15 * if applicable the software license agreement. Do not use this software and/or
group-onsemi 0:098463de4c5d 16 * documentation unless you have carefully read and you agree to the limited terms and
group-onsemi 0:098463de4c5d 17 * conditions. By using this software and/or documentation, you agree to the limited
group-onsemi 0:098463de4c5d 18 * terms and conditions.
group-onsemi 0:098463de4c5d 19 *
group-onsemi 0:098463de4c5d 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
group-onsemi 0:098463de4c5d 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
group-onsemi 0:098463de4c5d 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
group-onsemi 0:098463de4c5d 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
group-onsemi 0:098463de4c5d 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
group-onsemi 0:098463de4c5d 25 * @endinternal
group-onsemi 0:098463de4c5d 26 *
group-onsemi 0:098463de4c5d 27 * @ingroup uart_16c550
group-onsemi 0:098463de4c5d 28 *
group-onsemi 0:098463de4c5d 29 */
group-onsemi 0:098463de4c5d 30 #if DEVICE_SERIAL
group-onsemi 0:098463de4c5d 31
group-onsemi 0:098463de4c5d 32 #include "serial_api.h"
group-onsemi 0:098463de4c5d 33
group-onsemi 0:098463de4c5d 34 #include "cmsis.h"
group-onsemi 0:098463de4c5d 35 #include "pinmap.h"
group-onsemi 0:098463de4c5d 36 #include "PeripheralPins.h"
group-onsemi 0:098463de4c5d 37
group-onsemi 0:098463de4c5d 38 #include "mbed_assert.h"
group-onsemi 0:098463de4c5d 39 #include <string.h>
group-onsemi 0:098463de4c5d 40 #include "uart_16c550.h"
group-onsemi 0:098463de4c5d 41 #include "cmsis_nvic.h"
group-onsemi 0:098463de4c5d 42
group-onsemi 0:098463de4c5d 43 static IRQn_Type Irq;
group-onsemi 0:098463de4c5d 44
group-onsemi 0:098463de4c5d 45 uint32_t stdio_uart_inited = 0;
group-onsemi 0:098463de4c5d 46 serial_t stdio_uart;
group-onsemi 0:098463de4c5d 47
group-onsemi 0:098463de4c5d 48 static uint32_t serial_irq_ids[UART_NUM] = {0};
group-onsemi 0:098463de4c5d 49 static uart_irq_handler irq_handler;
group-onsemi 0:098463de4c5d 50 static inline void uart_irq(uint8_t status, uint32_t index);
group-onsemi 0:098463de4c5d 51
group-onsemi 0:098463de4c5d 52
group-onsemi 0:098463de4c5d 53 /** Opens UART device.
group-onsemi 0:098463de4c5d 54 * @details
group-onsemi 0:098463de4c5d 55 * Sets the necessary registers. Set to default Baud rate 115200, 8 bit, parity None and stop bit 1.
group-onsemi 0:098463de4c5d 56 * The UART interrupt is enabled.
group-onsemi 0:098463de4c5d 57 *
group-onsemi 0:098463de4c5d 58 * @note The UART transmit interrupt is not enabled, because sending is controlled
group-onsemi 0:098463de4c5d 59 * by the task.
group-onsemi 0:098463de4c5d 60 *
group-onsemi 0:098463de4c5d 61 * @param UartNum A UART device instance.
group-onsemi 0:098463de4c5d 62 * @param options The options parameter containing the baud rate.
group-onsemi 0:098463de4c5d 63 * @return True if opening was successful.
group-onsemi 0:098463de4c5d 64 */
group-onsemi 0:098463de4c5d 65
group-onsemi 0:098463de4c5d 66 void serial_init(serial_t *obj, PinName tx, PinName rx)
group-onsemi 0:098463de4c5d 67 {
group-onsemi 0:098463de4c5d 68 uint16_t clockDivisor;
group-onsemi 0:098463de4c5d 69
group-onsemi 0:098463de4c5d 70 CrossbReg_t *CbRegOffSet;
group-onsemi 0:098463de4c5d 71 PadReg_t *PadRegOffset;
group-onsemi 0:098463de4c5d 72
group-onsemi 0:098463de4c5d 73 //find which peripheral is associated with the rx and tx pins
group-onsemi 0:098463de4c5d 74 uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
group-onsemi 0:098463de4c5d 75 uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
group-onsemi 0:098463de4c5d 76 //check if the peripherals for each pin are the same or not
group-onsemi 0:098463de4c5d 77 //returns the enum associated with the peripheral
group-onsemi 0:098463de4c5d 78 //in the case of this target, the enum is the base address of the peripheral
group-onsemi 0:098463de4c5d 79 obj->UARTREG = (Uart16C550Reg_pt) pinmap_merge(uart_tx, uart_rx);
group-onsemi 0:098463de4c5d 80 MBED_ASSERT(obj->UARTREG != (Uart16C550Reg_pt) NC);
group-onsemi 0:098463de4c5d 81
group-onsemi 0:098463de4c5d 82 pinmap_pinout(tx, PinMap_UART_TX);
group-onsemi 0:098463de4c5d 83 pinmap_pinout(rx, PinMap_UART_RX);
group-onsemi 0:098463de4c5d 84
group-onsemi 0:098463de4c5d 85 /*TODO: Mac Lobdell - we should recommend using the instance method and not using base addresses as index */
group-onsemi 0:098463de4c5d 86
group-onsemi 0:098463de4c5d 87 if (obj->UARTREG == (Uart16C550Reg_pt)STDIO_UART) {
group-onsemi 0:098463de4c5d 88 stdio_uart_inited = 1;
group-onsemi 0:098463de4c5d 89 memcpy(&stdio_uart, obj, sizeof(serial_t));
group-onsemi 0:098463de4c5d 90 }
group-onsemi 0:098463de4c5d 91 /*TODO: determine if pullups are needed/recommended */
group-onsemi 0:098463de4c5d 92 /* if (tx != NC) {
group-onsemi 0:098463de4c5d 93 pin_mode(tx, PullUp);
group-onsemi 0:098463de4c5d 94 }
group-onsemi 0:098463de4c5d 95 if (rx != NC) {
group-onsemi 0:098463de4c5d 96 pin_mode(rx, PullUp);
group-onsemi 0:098463de4c5d 97 }
group-onsemi 0:098463de4c5d 98 */
group-onsemi 0:098463de4c5d 99 /* Configure IOs to UART using cross bar, pad and GPIO settings */
group-onsemi 0:098463de4c5d 100
group-onsemi 0:098463de4c5d 101 if(obj->UARTREG == UART2REG) {
group-onsemi 0:098463de4c5d 102 /* UART 2 */
group-onsemi 0:098463de4c5d 103 CLOCK_ENABLE(CLOCK_UART2);
group-onsemi 0:098463de4c5d 104 Irq = Uart2_IRQn;
group-onsemi 0:098463de4c5d 105 } else if(obj->UARTREG == UART1REG) {
group-onsemi 0:098463de4c5d 106 /* UART 1 */
group-onsemi 0:098463de4c5d 107 CLOCK_ENABLE(CLOCK_UART1);
group-onsemi 0:098463de4c5d 108
group-onsemi 0:098463de4c5d 109 Irq = Uart1_IRQn;
group-onsemi 0:098463de4c5d 110 } else {
group-onsemi 0:098463de4c5d 111 MBED_ASSERT(False);
group-onsemi 0:098463de4c5d 112 }
group-onsemi 0:098463de4c5d 113
group-onsemi 0:098463de4c5d 114 CLOCK_ENABLE(CLOCK_GPIO);
group-onsemi 0:098463de4c5d 115 CLOCK_ENABLE(CLOCK_CROSSB);
group-onsemi 0:098463de4c5d 116 CLOCK_ENABLE(CLOCK_PAD);
group-onsemi 0:098463de4c5d 117
group-onsemi 0:098463de4c5d 118 /*TODO: determine if tx and rx are used correctly in this case - this depends on the pin enum matching the position in the crossbar*/
group-onsemi 0:098463de4c5d 119
group-onsemi 0:098463de4c5d 120 /* Configure tx pin as UART */
group-onsemi 0:098463de4c5d 121 CbRegOffSet = (CrossbReg_t*)(CROSSBREG_BASE + (tx * CROSS_REG_ADRS_BYTE_SIZE));
group-onsemi 0:098463de4c5d 122 CbRegOffSet->DIOCTRL0 = CONFIGURE_AS_UART; /* tx pin as UART */
group-onsemi 0:098463de4c5d 123
group-onsemi 0:098463de4c5d 124 /* Configure rx pin as UART */
group-onsemi 0:098463de4c5d 125 CbRegOffSet = (CrossbReg_t*)(CROSSBREG_BASE + (rx * CROSS_REG_ADRS_BYTE_SIZE));
group-onsemi 0:098463de4c5d 126 CbRegOffSet->DIOCTRL0 = CONFIGURE_AS_UART; /* rx pin as UART */
group-onsemi 0:098463de4c5d 127
group-onsemi 0:098463de4c5d 128 /** - Set pad parameters, output drive strength, pull piece control, output drive type */
group-onsemi 0:098463de4c5d 129 PadRegOffset = (PadReg_t*)(PADREG_BASE + (tx * PAD_REG_ADRS_BYTE_SIZE));
group-onsemi 0:098463de4c5d 130 PadRegOffset->PADIO0.WORD = PAD_UART_TX; /* Pad setting for UART Tx */
group-onsemi 0:098463de4c5d 131
group-onsemi 0:098463de4c5d 132 PadRegOffset = (PadReg_t*)(PADREG_BASE + (rx * PAD_REG_ADRS_BYTE_SIZE));
group-onsemi 0:098463de4c5d 133 PadRegOffset->PADIO0.WORD = PAD_UART_RX; /* Pad settings for UART Rx */
group-onsemi 0:098463de4c5d 134
group-onsemi 0:098463de4c5d 135 GPIOREG->W_OUT = (0x1 << tx); /* tx as OUT direction */
group-onsemi 0:098463de4c5d 136 GPIOREG->W_IN = (0x1 << rx); /* rx as IN directon */
group-onsemi 0:098463de4c5d 137
group-onsemi 0:098463de4c5d 138 CLOCK_DISABLE(CLOCK_PAD);
group-onsemi 0:098463de4c5d 139 CLOCK_DISABLE(CLOCK_CROSSB);
group-onsemi 0:098463de4c5d 140 CLOCK_DISABLE(CLOCK_GPIO);
group-onsemi 0:098463de4c5d 141
group-onsemi 0:098463de4c5d 142 /* Set the divisor value. To do so, LCR[7] needs to be set to 1 in order to access the divisor registers.
group-onsemi 0:098463de4c5d 143 * The right-shift of 4 is a division of 16, representing the oversampling rate. */
group-onsemi 0:098463de4c5d 144 clockDivisor = (fClockGetPeriphClockfrequency() / UART_DEFAULT_BAUD) >> 4;
group-onsemi 0:098463de4c5d 145 obj->UARTREG->LCR.WORD = 0x80;
group-onsemi 0:098463de4c5d 146 obj->UARTREG->DLL = clockDivisor & 0xFF;
group-onsemi 0:098463de4c5d 147 obj->UARTREG->DLM = clockDivisor >> 8;
group-onsemi 0:098463de4c5d 148
group-onsemi 0:098463de4c5d 149 /* Set the character width to 8 data bits, no parity, 1 stop bit. Write the entire line control register,
group-onsemi 0:098463de4c5d 150 * effectively disabling the divisor latch. */
group-onsemi 0:098463de4c5d 151 obj->UARTREG->LCR.WORD = 0x03;
group-onsemi 0:098463de4c5d 152
group-onsemi 0:098463de4c5d 153 /* Enable the FIFOs, reset the Tx and Rx FIFOs, set the Rx FIFO trigger level to 8 bytes, and set DMA Mode
group-onsemi 0:098463de4c5d 154 to 1. */
group-onsemi 0:098463de4c5d 155 obj->UARTREG->FCR.WORD = (FCR_RXFIFOTRIGGERLEVEL_8 | FCR_DMA_MODE_1 |
group-onsemi 0:098463de4c5d 156 FCR_TXFIFO_RESET | FCR_RXFIFO_RESET | FCR_FIFO_ENABLE);
group-onsemi 0:098463de4c5d 157
group-onsemi 0:098463de4c5d 158 /* Make a copy of the current MSR to the SCR register. This is used from task space to determine the
group-onsemi 0:098463de4c5d 159 * flow control state. */
group-onsemi 0:098463de4c5d 160 obj->UARTREG->SCR = obj->UARTREG->MSR.WORD;
group-onsemi 0:098463de4c5d 161
group-onsemi 0:098463de4c5d 162 if((int)obj->UARTREG == STDIO_UART) {
group-onsemi 0:098463de4c5d 163 stdio_uart_inited = 1;
group-onsemi 0:098463de4c5d 164 memcpy(&stdio_uart, obj, sizeof(serial_t));
group-onsemi 0:098463de4c5d 165 }
group-onsemi 0:098463de4c5d 166
group-onsemi 0:098463de4c5d 167 NVIC_ClearPendingIRQ(Irq);
group-onsemi 0:098463de4c5d 168
group-onsemi 0:098463de4c5d 169 return;
group-onsemi 0:098463de4c5d 170 }
group-onsemi 0:098463de4c5d 171
group-onsemi 0:098463de4c5d 172 /** Closes a UART device.
group-onsemi 0:098463de4c5d 173 * @details
group-onsemi 0:098463de4c5d 174 * Disables the UART interrupt.
group-onsemi 0:098463de4c5d 175 *
group-onsemi 0:098463de4c5d 176 * @param device The UART device to close.
group-onsemi 0:098463de4c5d 177 */
group-onsemi 0:098463de4c5d 178 void serial_free(serial_t *obj)
group-onsemi 0:098463de4c5d 179 {
group-onsemi 0:098463de4c5d 180 NVIC_DisableIRQ(obj->IRQType);
group-onsemi 0:098463de4c5d 181 }
group-onsemi 0:098463de4c5d 182
group-onsemi 0:098463de4c5d 183 void serial_baud(serial_t *obj, int baudrate)
group-onsemi 0:098463de4c5d 184 {
group-onsemi 0:098463de4c5d 185 /* Set the divisor value. To do so, LCR[7] needs to be set to 1 in order to access the divisor registers.
group-onsemi 0:098463de4c5d 186 * The right-shift of 4 is a division of 16, representing the oversampling rate. */
group-onsemi 0:098463de4c5d 187 uint16_t clockDivisor = (fClockGetPeriphClockfrequency() / baudrate) >> 4;
group-onsemi 0:098463de4c5d 188
group-onsemi 0:098463de4c5d 189 obj->UARTREG->LCR.BITS.DLAB = True;
group-onsemi 0:098463de4c5d 190 obj->UARTREG->DLL = clockDivisor & 0xFF;
group-onsemi 0:098463de4c5d 191 obj->UARTREG->DLM = clockDivisor >> 8;
group-onsemi 0:098463de4c5d 192 obj->UARTREG->LCR.BITS.DLAB = False;
group-onsemi 0:098463de4c5d 193 }
group-onsemi 0:098463de4c5d 194
group-onsemi 0:098463de4c5d 195 /*
group-onsemi 0:098463de4c5d 196 Parity XX0 – Parity disabled; 001 – Odd Parity; 011 – Even Parity; 101 – Stick Parity, checked as 1; 111 – Stick Parity, checked as 0.
group-onsemi 0:098463de4c5d 197 StopBit 0 – 1 stop bit; 1 – 2 stop bits.
group-onsemi 0:098463de4c5d 198 DataLen 00 – 5 bits; 01 – 6 bits; 10 – 7 bits; 11 – 8 bits
group-onsemi 0:098463de4c5d 199 */
group-onsemi 0:098463de4c5d 200 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
group-onsemi 0:098463de4c5d 201 {
group-onsemi 0:098463de4c5d 202 if(data_bits >= 5 && data_bits <= 8 && parity <= 7 && stop_bits >= 1 && stop_bits <= 2) {
group-onsemi 0:098463de4c5d 203 if(parity == (SerialParity)0) {
group-onsemi 0:098463de4c5d 204 parity = (SerialParity)0;
group-onsemi 0:098463de4c5d 205 } else {
group-onsemi 0:098463de4c5d 206 parity = (SerialParity)(parity + parity - 1) ;
group-onsemi 0:098463de4c5d 207 }
group-onsemi 0:098463de4c5d 208
group-onsemi 0:098463de4c5d 209 obj->UARTREG->LCR.WORD |= ((((data_bits - 5) << UART_LCR_DATALEN_BIT_POS) |
group-onsemi 0:098463de4c5d 210 (parity << UART_LCR_PARITY_BIT_POS) |
group-onsemi 0:098463de4c5d 211 ((stop_bits - 1) << UART_LCR_STPBIT_BIT_POS)) & 0x3F);
group-onsemi 0:098463de4c5d 212 } else {
group-onsemi 0:098463de4c5d 213 MBED_ASSERT(False);
group-onsemi 0:098463de4c5d 214 }
group-onsemi 0:098463de4c5d 215 }
group-onsemi 0:098463de4c5d 216
group-onsemi 0:098463de4c5d 217 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
group-onsemi 0:098463de4c5d 218 {
group-onsemi 0:098463de4c5d 219 irq_handler = handler;
group-onsemi 0:098463de4c5d 220 serial_irq_ids[obj->index] = id;
group-onsemi 0:098463de4c5d 221 }
group-onsemi 0:098463de4c5d 222
group-onsemi 0:098463de4c5d 223 /******************************************************
group-onsemi 0:098463de4c5d 224 ************* Internal IRQ functions ******************
group-onsemi 0:098463de4c5d 225 *******************************************************/
group-onsemi 0:098463de4c5d 226 void Uart1_Irq()
group-onsemi 0:098463de4c5d 227 {
group-onsemi 0:098463de4c5d 228 uint8_t active_irq = (uint8_t)(UART1REG->LSR.WORD) & 0xFF;
group-onsemi 0:098463de4c5d 229 uint8_t irq_mask = 0;
group-onsemi 0:098463de4c5d 230
group-onsemi 0:098463de4c5d 231 if(UART1REG->IER.WORD & UART_IER_TX_EMPTY_MASK) { /*check if TX interrupt is enabled*/
group-onsemi 0:098463de4c5d 232 irq_mask |= active_irq & UART_LSR_TX_EMPTY_MASK;
group-onsemi 0:098463de4c5d 233 }
group-onsemi 0:098463de4c5d 234
group-onsemi 0:098463de4c5d 235 if(UART1REG->IER.WORD & UART_IER_RX_DATA_READY_MASK) { /*check if RX interrupt is enabled*/
group-onsemi 0:098463de4c5d 236 irq_mask |= active_irq & UART_LSR_RX_DATA_READY_MASK;
group-onsemi 0:098463de4c5d 237 }
group-onsemi 0:098463de4c5d 238
group-onsemi 0:098463de4c5d 239 //uart_irq((uint8_t)(UART1REG->LSR.WORD & 0xFF), 0);
group-onsemi 0:098463de4c5d 240 uart_irq(active_irq & irq_mask, 0);
group-onsemi 0:098463de4c5d 241 }
group-onsemi 0:098463de4c5d 242
group-onsemi 0:098463de4c5d 243 void Uart2_Irq()
group-onsemi 0:098463de4c5d 244 {
group-onsemi 0:098463de4c5d 245 uint8_t active_irq = (uint8_t)(UART2REG->LSR.WORD) & 0xFF;
group-onsemi 0:098463de4c5d 246 uint8_t irq_mask = 0;
group-onsemi 0:098463de4c5d 247
group-onsemi 0:098463de4c5d 248 if(UART2REG->IER.WORD & UART_IER_TX_EMPTY_MASK) { /*check if TX interrupt is enabled*/
group-onsemi 0:098463de4c5d 249 irq_mask |= active_irq & UART_LSR_TX_EMPTY_MASK;
group-onsemi 0:098463de4c5d 250 }
group-onsemi 0:098463de4c5d 251
group-onsemi 0:098463de4c5d 252 if(UART2REG->IER.WORD & UART_IER_RX_DATA_READY_MASK) { /*check if RX interrupt is enabled*/
group-onsemi 0:098463de4c5d 253 irq_mask |= active_irq & UART_LSR_RX_DATA_READY_MASK;
group-onsemi 0:098463de4c5d 254 }
group-onsemi 0:098463de4c5d 255
group-onsemi 0:098463de4c5d 256 //uart_irq((uint8_t)(UART2REG->LSR.WORD & 0xFF), 1);
group-onsemi 0:098463de4c5d 257 uart_irq(active_irq & irq_mask, 1);
group-onsemi 0:098463de4c5d 258
group-onsemi 0:098463de4c5d 259 }
group-onsemi 0:098463de4c5d 260
group-onsemi 0:098463de4c5d 261 static inline void uart_irq(uint8_t status, uint32_t index)
group-onsemi 0:098463de4c5d 262 {
group-onsemi 0:098463de4c5d 263 if (serial_irq_ids[index] != 0) {
group-onsemi 0:098463de4c5d 264 if (status & UART_LSR_TX_EMPTY_MASK) {
group-onsemi 0:098463de4c5d 265 irq_handler(serial_irq_ids[index], TxIrq);
group-onsemi 0:098463de4c5d 266 }
group-onsemi 0:098463de4c5d 267 if (status & UART_LSR_RX_DATA_READY_MASK) {
group-onsemi 0:098463de4c5d 268 irq_handler(serial_irq_ids[index], RxIrq);
group-onsemi 0:098463de4c5d 269 }
group-onsemi 0:098463de4c5d 270 }
group-onsemi 0:098463de4c5d 271 }
group-onsemi 0:098463de4c5d 272 /******************************************************/
group-onsemi 0:098463de4c5d 273
group-onsemi 0:098463de4c5d 274 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
group-onsemi 0:098463de4c5d 275 {
group-onsemi 0:098463de4c5d 276 IRQn_Type irq_n = (IRQn_Type)0;
group-onsemi 0:098463de4c5d 277 uint32_t Vector = 0;
group-onsemi 0:098463de4c5d 278
group-onsemi 0:098463de4c5d 279 /* Check UART number & assign irq handler */
group-onsemi 0:098463de4c5d 280 if(obj->UARTREG == UART1REG) {
group-onsemi 0:098463de4c5d 281 /* UART 2 */
group-onsemi 0:098463de4c5d 282 Vector = (uint32_t)&Uart1_Irq;
group-onsemi 0:098463de4c5d 283 irq_n = Uart1_IRQn;
group-onsemi 0:098463de4c5d 284 } else if(obj->UARTREG == UART2REG) {
group-onsemi 0:098463de4c5d 285 /* UART 1 */
group-onsemi 0:098463de4c5d 286 Vector = (uint32_t)&Uart2_Irq;
group-onsemi 0:098463de4c5d 287 irq_n = Uart2_IRQn;
group-onsemi 0:098463de4c5d 288 } else {
group-onsemi 0:098463de4c5d 289 MBED_ASSERT(False);
group-onsemi 0:098463de4c5d 290 }
group-onsemi 0:098463de4c5d 291
group-onsemi 0:098463de4c5d 292 /* Check IRQ type & enable/disable accordingly */
group-onsemi 0:098463de4c5d 293 if(enable) {
group-onsemi 0:098463de4c5d 294 /* Enable */
group-onsemi 0:098463de4c5d 295 if(irq == RxIrq) {
group-onsemi 0:098463de4c5d 296 /* Rx IRQ */
group-onsemi 0:098463de4c5d 297 obj->UARTREG->FCR.BITS.RX_FIFO_TRIG = 0x0;
group-onsemi 0:098463de4c5d 298 obj->UARTREG->IER.BITS.RX_DATA_INT = True;
group-onsemi 0:098463de4c5d 299 } else if(irq == TxIrq) {
group-onsemi 0:098463de4c5d 300 /* Tx IRQ */
group-onsemi 0:098463de4c5d 301 obj->UARTREG->IER.BITS.TX_HOLD_INT = True;
group-onsemi 0:098463de4c5d 302 } else {
group-onsemi 0:098463de4c5d 303 MBED_ASSERT(False);
group-onsemi 0:098463de4c5d 304 }
group-onsemi 0:098463de4c5d 305 NVIC_SetVector(irq_n, Vector);
group-onsemi 0:098463de4c5d 306 NVIC_EnableIRQ(irq_n);
group-onsemi 0:098463de4c5d 307 } else {
group-onsemi 0:098463de4c5d 308 /* Disable */
group-onsemi 0:098463de4c5d 309 NVIC_DisableIRQ(irq_n);
group-onsemi 0:098463de4c5d 310 if(irq == RxIrq) {
group-onsemi 0:098463de4c5d 311 /* Rx IRQ */
group-onsemi 0:098463de4c5d 312 obj->UARTREG->IER.BITS.RX_DATA_INT = False;
group-onsemi 0:098463de4c5d 313 } else if(irq == TxIrq) {
group-onsemi 0:098463de4c5d 314 /* Tx IRQ */
group-onsemi 0:098463de4c5d 315
group-onsemi 0:098463de4c5d 316 obj->UARTREG->IER.BITS.TX_HOLD_INT = False;
group-onsemi 0:098463de4c5d 317 } else {
group-onsemi 0:098463de4c5d 318 MBED_ASSERT(False);
group-onsemi 0:098463de4c5d 319 }
group-onsemi 0:098463de4c5d 320 }
group-onsemi 0:098463de4c5d 321 }
group-onsemi 0:098463de4c5d 322
group-onsemi 0:098463de4c5d 323 int serial_getc(serial_t *obj)
group-onsemi 0:098463de4c5d 324 {
group-onsemi 0:098463de4c5d 325 uint8_t c;
group-onsemi 0:098463de4c5d 326
group-onsemi 0:098463de4c5d 327 while(!obj->UARTREG->LSR.BITS.READY); /* Wait for received data is ready */
group-onsemi 0:098463de4c5d 328 c = obj->UARTREG->RBR & 0xFF; /* Get received character */
group-onsemi 0:098463de4c5d 329 return c;
group-onsemi 0:098463de4c5d 330 }
group-onsemi 0:098463de4c5d 331
group-onsemi 0:098463de4c5d 332 void serial_putc(serial_t *obj, int c)
group-onsemi 0:098463de4c5d 333 {
group-onsemi 0:098463de4c5d 334
group-onsemi 0:098463de4c5d 335 while(!obj->UARTREG->LSR.BITS.TX_HOLD_EMPTY);/* Wait till THR is empty */
group-onsemi 0:098463de4c5d 336 obj->UARTREG->THR = c; /* Transmit byte */
group-onsemi 0:098463de4c5d 337
group-onsemi 0:098463de4c5d 338 }
group-onsemi 0:098463de4c5d 339
group-onsemi 0:098463de4c5d 340 int serial_readable(serial_t *obj)
group-onsemi 0:098463de4c5d 341 {
group-onsemi 0:098463de4c5d 342 return obj->UARTREG->LSR.BITS.READY;
group-onsemi 0:098463de4c5d 343 }
group-onsemi 0:098463de4c5d 344
group-onsemi 0:098463de4c5d 345 int serial_writable(serial_t *obj)
group-onsemi 0:098463de4c5d 346 {
group-onsemi 0:098463de4c5d 347 return obj->UARTREG->LSR.BITS.TX_HOLD_EMPTY;
group-onsemi 0:098463de4c5d 348 }
group-onsemi 0:098463de4c5d 349
group-onsemi 0:098463de4c5d 350 void serial_clear(serial_t *obj)
group-onsemi 0:098463de4c5d 351 {
group-onsemi 0:098463de4c5d 352 /* Reset TX & RX FIFO */
group-onsemi 0:098463de4c5d 353 obj->UARTREG->FCR.WORD |= ((True << UART_FCS_TX_FIFO_RST_BIT_POS) |
group-onsemi 0:098463de4c5d 354 (True << UART_FCS_RX_FIFO_RST_BIT_POS));
group-onsemi 0:098463de4c5d 355 }
group-onsemi 0:098463de4c5d 356
group-onsemi 0:098463de4c5d 357 void serial_break_set(serial_t *obj)
group-onsemi 0:098463de4c5d 358 {
group-onsemi 0:098463de4c5d 359 obj->UARTREG->LCR.BITS.BREAK = True;
group-onsemi 0:098463de4c5d 360 }
group-onsemi 0:098463de4c5d 361
group-onsemi 0:098463de4c5d 362 void serial_break_clear(serial_t *obj)
group-onsemi 0:098463de4c5d 363 {
group-onsemi 0:098463de4c5d 364 obj->UARTREG->LCR.BITS.BREAK = False;
group-onsemi 0:098463de4c5d 365 }
group-onsemi 0:098463de4c5d 366
group-onsemi 0:098463de4c5d 367 void serial_pinout_tx(PinName tx)
group-onsemi 0:098463de4c5d 368 {
group-onsemi 0:098463de4c5d 369 /* COnfigure PinNo to drive strength of 1, Push pull and pull none */
group-onsemi 0:098463de4c5d 370 fPadIOCtrl(tx, 1, 0, 1);
group-onsemi 0:098463de4c5d 371 }
group-onsemi 0:098463de4c5d 372
group-onsemi 0:098463de4c5d 373 /** Configure the serial for the flow control. It sets flow control in the hardware
group-onsemi 0:098463de4c5d 374 * if a serial peripheral supports it, otherwise software emulation is used.
group-onsemi 0:098463de4c5d 375 *
group-onsemi 0:098463de4c5d 376 * @param obj The serial object
group-onsemi 0:098463de4c5d 377 * @param type The type of the flow control. Look at the available FlowControl types.
group-onsemi 0:098463de4c5d 378 * @param rxflow The TX pin name
group-onsemi 0:098463de4c5d 379 * @param txflow The RX pin name
group-onsemi 0:098463de4c5d 380 */
group-onsemi 0:098463de4c5d 381 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
group-onsemi 0:098463de4c5d 382 {
group-onsemi 0:098463de4c5d 383 /* TODO: This is an empty implementation for now.*/
group-onsemi 0:098463de4c5d 384 }
group-onsemi 0:098463de4c5d 385
group-onsemi 0:098463de4c5d 386 #endif /* DEVICE_SERIAL */