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targets/TARGET_Maxim/TARGET_MAX32625/device/spim_regs.h@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /*******************************************************************************
group-onsemi 0:098463de4c5d 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Permission is hereby granted, free of charge, to any person obtaining a
group-onsemi 0:098463de4c5d 5 * copy of this software and associated documentation files (the "Software"),
group-onsemi 0:098463de4c5d 6 * to deal in the Software without restriction, including without limitation
group-onsemi 0:098463de4c5d 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
group-onsemi 0:098463de4c5d 8 * and/or sell copies of the Software, and to permit persons to whom the
group-onsemi 0:098463de4c5d 9 * Software is furnished to do so, subject to the following conditions:
group-onsemi 0:098463de4c5d 10 *
group-onsemi 0:098463de4c5d 11 * The above copyright notice and this permission notice shall be included
group-onsemi 0:098463de4c5d 12 * in all copies or substantial portions of the Software.
group-onsemi 0:098463de4c5d 13 *
group-onsemi 0:098463de4c5d 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
group-onsemi 0:098463de4c5d 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
group-onsemi 0:098463de4c5d 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
group-onsemi 0:098463de4c5d 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
group-onsemi 0:098463de4c5d 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
group-onsemi 0:098463de4c5d 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
group-onsemi 0:098463de4c5d 20 * OTHER DEALINGS IN THE SOFTWARE.
group-onsemi 0:098463de4c5d 21 *
group-onsemi 0:098463de4c5d 22 * Except as contained in this notice, the name of Maxim Integrated
group-onsemi 0:098463de4c5d 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
group-onsemi 0:098463de4c5d 24 * Products, Inc. Branding Policy.
group-onsemi 0:098463de4c5d 25 *
group-onsemi 0:098463de4c5d 26 * The mere transfer of this software does not imply any licenses
group-onsemi 0:098463de4c5d 27 * of trade secrets, proprietary technology, copyrights, patents,
group-onsemi 0:098463de4c5d 28 * trademarks, maskwork rights, or any other form of intellectual
group-onsemi 0:098463de4c5d 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
group-onsemi 0:098463de4c5d 30 * ownership rights.
group-onsemi 0:098463de4c5d 31 ******************************************************************************/
group-onsemi 0:098463de4c5d 32
group-onsemi 0:098463de4c5d 33 #ifndef _MXC_SPIM_REGS_H_
group-onsemi 0:098463de4c5d 34 #define _MXC_SPIM_REGS_H_
group-onsemi 0:098463de4c5d 35
group-onsemi 0:098463de4c5d 36 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 37 extern "C" {
group-onsemi 0:098463de4c5d 38 #endif
group-onsemi 0:098463de4c5d 39
group-onsemi 0:098463de4c5d 40 #include <stdint.h>
group-onsemi 0:098463de4c5d 41 #include "mxc_device.h"
group-onsemi 0:098463de4c5d 42
group-onsemi 0:098463de4c5d 43 /*
group-onsemi 0:098463de4c5d 44 If types are not defined elsewhere (CMSIS) define them here
group-onsemi 0:098463de4c5d 45 */
group-onsemi 0:098463de4c5d 46 #ifndef __IO
group-onsemi 0:098463de4c5d 47 #define __IO volatile
group-onsemi 0:098463de4c5d 48 #endif
group-onsemi 0:098463de4c5d 49 #ifndef __I
group-onsemi 0:098463de4c5d 50 #define __I volatile const
group-onsemi 0:098463de4c5d 51 #endif
group-onsemi 0:098463de4c5d 52 #ifndef __O
group-onsemi 0:098463de4c5d 53 #define __O volatile
group-onsemi 0:098463de4c5d 54 #endif
group-onsemi 0:098463de4c5d 55
group-onsemi 0:098463de4c5d 56
group-onsemi 0:098463de4c5d 57 /*
group-onsemi 0:098463de4c5d 58 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
group-onsemi 0:098463de4c5d 59 access to each register in module.
group-onsemi 0:098463de4c5d 60 */
group-onsemi 0:098463de4c5d 61
group-onsemi 0:098463de4c5d 62 /* Offset Register Description
group-onsemi 0:098463de4c5d 63 ============= ============================================================================ */
group-onsemi 0:098463de4c5d 64 typedef struct {
group-onsemi 0:098463de4c5d 65 __IO uint32_t mstr_cfg; /* 0x0000 SPI Master Configuration Register */
group-onsemi 0:098463de4c5d 66 __IO uint32_t ss_sr_polarity; /* 0x0004 SPI Master Polarity Control for SS and SR Signals */
group-onsemi 0:098463de4c5d 67 __IO uint32_t gen_ctrl; /* 0x0008 SPI Master General Control Register */
group-onsemi 0:098463de4c5d 68 __IO uint32_t fifo_ctrl; /* 0x000C SPI Master FIFO Control Register */
group-onsemi 0:098463de4c5d 69 __IO uint32_t spcl_ctrl; /* 0x0010 SPI Master Special Mode Controls */
group-onsemi 0:098463de4c5d 70 __IO uint32_t intfl; /* 0x0014 SPI Master Interrupt Flags */
group-onsemi 0:098463de4c5d 71 __IO uint32_t inten; /* 0x0018 SPI Master Interrupt Enable/Disable Settings */
group-onsemi 0:098463de4c5d 72 __IO uint32_t simple_headers; /* 0x001C SPI Master Simple Mode Transaction Headers */
group-onsemi 0:098463de4c5d 73 } mxc_spim_regs_t;
group-onsemi 0:098463de4c5d 74
group-onsemi 0:098463de4c5d 75
group-onsemi 0:098463de4c5d 76 /* Offset Register Description
group-onsemi 0:098463de4c5d 77 ============= ============================================================================ */
group-onsemi 0:098463de4c5d 78 typedef struct {
group-onsemi 0:098463de4c5d 79 union { /* 0x0000-0x07FC SPI Master FIFO Write Space for Transaction Setup */
group-onsemi 0:098463de4c5d 80 __IO uint8_t trans_8[2048];
group-onsemi 0:098463de4c5d 81 __IO uint16_t trans_16[1024];
group-onsemi 0:098463de4c5d 82 __IO uint32_t trans_32[512];
group-onsemi 0:098463de4c5d 83 };
group-onsemi 0:098463de4c5d 84 union { /* 0x0800-0x0FFC SPI Master FIFO Read Space for Results Data */
group-onsemi 0:098463de4c5d 85 __IO uint8_t rslts_8[2048];
group-onsemi 0:098463de4c5d 86 __IO uint16_t rslts_16[1024];
group-onsemi 0:098463de4c5d 87 __IO uint32_t rslts_32[512];
group-onsemi 0:098463de4c5d 88 };
group-onsemi 0:098463de4c5d 89 } mxc_spim_fifo_regs_t;
group-onsemi 0:098463de4c5d 90
group-onsemi 0:098463de4c5d 91
group-onsemi 0:098463de4c5d 92 /*
group-onsemi 0:098463de4c5d 93 Register offsets for module SPIM.
group-onsemi 0:098463de4c5d 94 */
group-onsemi 0:098463de4c5d 95
group-onsemi 0:098463de4c5d 96 #define MXC_R_SPIM_OFFS_MSTR_CFG ((uint32_t)0x00000000UL)
group-onsemi 0:098463de4c5d 97 #define MXC_R_SPIM_OFFS_SS_SR_POLARITY ((uint32_t)0x00000004UL)
group-onsemi 0:098463de4c5d 98 #define MXC_R_SPIM_OFFS_GEN_CTRL ((uint32_t)0x00000008UL)
group-onsemi 0:098463de4c5d 99 #define MXC_R_SPIM_OFFS_FIFO_CTRL ((uint32_t)0x0000000CUL)
group-onsemi 0:098463de4c5d 100 #define MXC_R_SPIM_OFFS_SPCL_CTRL ((uint32_t)0x00000010UL)
group-onsemi 0:098463de4c5d 101 #define MXC_R_SPIM_OFFS_INTFL ((uint32_t)0x00000014UL)
group-onsemi 0:098463de4c5d 102 #define MXC_R_SPIM_OFFS_INTEN ((uint32_t)0x00000018UL)
group-onsemi 0:098463de4c5d 103 #define MXC_R_SPIM_OFFS_SIMPLE_HEADERS ((uint32_t)0x0000001CUL)
group-onsemi 0:098463de4c5d 104 #define MXC_R_SPIM_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL)
group-onsemi 0:098463de4c5d 105 #define MXC_R_SPIM_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL)
group-onsemi 0:098463de4c5d 106
group-onsemi 0:098463de4c5d 107
group-onsemi 0:098463de4c5d 108 /*
group-onsemi 0:098463de4c5d 109 Field positions and masks for module SPIM.
group-onsemi 0:098463de4c5d 110 */
group-onsemi 0:098463de4c5d 111
group-onsemi 0:098463de4c5d 112 #define MXC_F_SPIM_MSTR_CFG_SLAVE_SEL_POS 0
group-onsemi 0:098463de4c5d 113 #define MXC_F_SPIM_MSTR_CFG_SLAVE_SEL ((uint32_t)(0x00000007UL << MXC_F_SPIM_MSTR_CFG_SLAVE_SEL_POS))
group-onsemi 0:098463de4c5d 114 #define MXC_F_SPIM_MSTR_CFG_THREE_WIRE_MODE_POS 3
group-onsemi 0:098463de4c5d 115 #define MXC_F_SPIM_MSTR_CFG_THREE_WIRE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_MSTR_CFG_THREE_WIRE_MODE_POS))
group-onsemi 0:098463de4c5d 116 #define MXC_F_SPIM_MSTR_CFG_SPI_MODE_POS 4
group-onsemi 0:098463de4c5d 117 #define MXC_F_SPIM_MSTR_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIM_MSTR_CFG_SPI_MODE_POS))
group-onsemi 0:098463de4c5d 118 #define MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS 6
group-onsemi 0:098463de4c5d 119 #define MXC_F_SPIM_MSTR_CFG_PAGE_SIZE ((uint32_t)(0x00000003UL << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS))
group-onsemi 0:098463de4c5d 120 #define MXC_F_SPIM_MSTR_CFG_SCK_HI_CLK_POS 8
group-onsemi 0:098463de4c5d 121 #define MXC_F_SPIM_MSTR_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIM_MSTR_CFG_SCK_HI_CLK_POS))
group-onsemi 0:098463de4c5d 122 #define MXC_F_SPIM_MSTR_CFG_SCK_LO_CLK_POS 12
group-onsemi 0:098463de4c5d 123 #define MXC_F_SPIM_MSTR_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIM_MSTR_CFG_SCK_LO_CLK_POS))
group-onsemi 0:098463de4c5d 124 #define MXC_F_SPIM_MSTR_CFG_ACT_DELAY_POS 16
group-onsemi 0:098463de4c5d 125 #define MXC_F_SPIM_MSTR_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIM_MSTR_CFG_ACT_DELAY_POS))
group-onsemi 0:098463de4c5d 126 #define MXC_F_SPIM_MSTR_CFG_INACT_DELAY_POS 18
group-onsemi 0:098463de4c5d 127 #define MXC_F_SPIM_MSTR_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIM_MSTR_CFG_INACT_DELAY_POS))
group-onsemi 0:098463de4c5d 128 #define MXC_F_SPIM_MSTR_CFG_SDIO_SAMPLE_POINT_POS 20
group-onsemi 0:098463de4c5d 129 #define MXC_F_SPIM_MSTR_CFG_SDIO_SAMPLE_POINT ((uint32_t)(0x0000000FUL << MXC_F_SPIM_MSTR_CFG_SDIO_SAMPLE_POINT_POS))
group-onsemi 0:098463de4c5d 130
group-onsemi 0:098463de4c5d 131 #define MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_4B ((uint32_t)0x00000000UL)
group-onsemi 0:098463de4c5d 132 #define MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_8B ((uint32_t)0x00000001UL)
group-onsemi 0:098463de4c5d 133 #define MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_16B ((uint32_t)0x00000002UL)
group-onsemi 0:098463de4c5d 134 #define MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_32B ((uint32_t)0x00000003UL)
group-onsemi 0:098463de4c5d 135
group-onsemi 0:098463de4c5d 136 #define MXC_S_SPIM_MSTR_CFG_PAGE_4B (MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_4B << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS)
group-onsemi 0:098463de4c5d 137 #define MXC_S_SPIM_MSTR_CFG_PAGE_8B (MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_8B << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS)
group-onsemi 0:098463de4c5d 138 #define MXC_S_SPIM_MSTR_CFG_PAGE_16B (MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_16B << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS)
group-onsemi 0:098463de4c5d 139 #define MXC_S_SPIM_MSTR_CFG_PAGE_32B (MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_32B << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS)
group-onsemi 0:098463de4c5d 140
group-onsemi 0:098463de4c5d 141 #define MXC_F_SPIM_SS_SR_POLARITY_SS_POLARITY_POS 0
group-onsemi 0:098463de4c5d 142 #define MXC_F_SPIM_SS_SR_POLARITY_SS_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPIM_SS_SR_POLARITY_SS_POLARITY_POS))
group-onsemi 0:098463de4c5d 143 #define MXC_F_SPIM_SS_SR_POLARITY_FC_POLARITY_POS 8
group-onsemi 0:098463de4c5d 144 #define MXC_F_SPIM_SS_SR_POLARITY_FC_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPIM_SS_SR_POLARITY_FC_POLARITY_POS))
group-onsemi 0:098463de4c5d 145
group-onsemi 0:098463de4c5d 146 #define MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN_POS 0
group-onsemi 0:098463de4c5d 147 #define MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN_POS))
group-onsemi 0:098463de4c5d 148 #define MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN_POS 1
group-onsemi 0:098463de4c5d 149 #define MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN_POS))
group-onsemi 0:098463de4c5d 150 #define MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN_POS 2
group-onsemi 0:098463de4c5d 151 #define MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN_POS))
group-onsemi 0:098463de4c5d 152 #define MXC_F_SPIM_GEN_CTRL_BIT_BANG_MODE_POS 3
group-onsemi 0:098463de4c5d 153 #define MXC_F_SPIM_GEN_CTRL_BIT_BANG_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_BIT_BANG_MODE_POS))
group-onsemi 0:098463de4c5d 154 #define MXC_F_SPIM_GEN_CTRL_BB_SS_IN_OUT_POS 4
group-onsemi 0:098463de4c5d 155 #define MXC_F_SPIM_GEN_CTRL_BB_SS_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_BB_SS_IN_OUT_POS))
group-onsemi 0:098463de4c5d 156 #define MXC_F_SPIM_GEN_CTRL_BB_SR_IN_POS 5
group-onsemi 0:098463de4c5d 157 #define MXC_F_SPIM_GEN_CTRL_BB_SR_IN ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_BB_SR_IN_POS))
group-onsemi 0:098463de4c5d 158 #define MXC_F_SPIM_GEN_CTRL_BB_SCK_IN_OUT_POS 6
group-onsemi 0:098463de4c5d 159 #define MXC_F_SPIM_GEN_CTRL_BB_SCK_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_BB_SCK_IN_OUT_POS))
group-onsemi 0:098463de4c5d 160 #define MXC_F_SPIM_GEN_CTRL_BB_SDIO_IN_POS 8
group-onsemi 0:098463de4c5d 161 #define MXC_F_SPIM_GEN_CTRL_BB_SDIO_IN ((uint32_t)(0x0000000FUL << MXC_F_SPIM_GEN_CTRL_BB_SDIO_IN_POS))
group-onsemi 0:098463de4c5d 162 #define MXC_F_SPIM_GEN_CTRL_BB_SDIO_OUT_POS 12
group-onsemi 0:098463de4c5d 163 #define MXC_F_SPIM_GEN_CTRL_BB_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPIM_GEN_CTRL_BB_SDIO_OUT_POS))
group-onsemi 0:098463de4c5d 164 #define MXC_F_SPIM_GEN_CTRL_BB_SDIO_DR_EN_POS 16
group-onsemi 0:098463de4c5d 165 #define MXC_F_SPIM_GEN_CTRL_BB_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPIM_GEN_CTRL_BB_SDIO_DR_EN_POS))
group-onsemi 0:098463de4c5d 166 #define MXC_F_SPIM_GEN_CTRL_SIMPLE_MODE_POS 20
group-onsemi 0:098463de4c5d 167 #define MXC_F_SPIM_GEN_CTRL_SIMPLE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_SIMPLE_MODE_POS))
group-onsemi 0:098463de4c5d 168 #define MXC_F_SPIM_GEN_CTRL_START_RX_ONLY_POS 21
group-onsemi 0:098463de4c5d 169 #define MXC_F_SPIM_GEN_CTRL_START_RX_ONLY ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_START_RX_ONLY_POS))
group-onsemi 0:098463de4c5d 170 #define MXC_F_SPIM_GEN_CTRL_DEASSERT_ACT_SS_POS 22
group-onsemi 0:098463de4c5d 171 #define MXC_F_SPIM_GEN_CTRL_DEASSERT_ACT_SS ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_DEASSERT_ACT_SS_POS))
group-onsemi 0:098463de4c5d 172 #define MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE_POS 24
group-onsemi 0:098463de4c5d 173 #define MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE_POS))
group-onsemi 0:098463de4c5d 174 #define MXC_F_SPIM_GEN_CTRL_INVERT_SCK_FB_CLK_POS 25
group-onsemi 0:098463de4c5d 175 #define MXC_F_SPIM_GEN_CTRL_INVERT_SCK_FB_CLK ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_INVERT_SCK_FB_CLK_POS))
group-onsemi 0:098463de4c5d 176
group-onsemi 0:098463de4c5d 177 #define MXC_F_SPIM_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0
group-onsemi 0:098463de4c5d 178 #define MXC_F_SPIM_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0x0000000FUL << MXC_F_SPIM_FIFO_CTRL_TX_FIFO_AE_LVL_POS))
group-onsemi 0:098463de4c5d 179 #define MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED_POS 8
group-onsemi 0:098463de4c5d 180 #define MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED ((uint32_t)(0x0000001FUL << MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED_POS))
group-onsemi 0:098463de4c5d 181 #define MXC_F_SPIM_FIFO_CTRL_RX_FIFO_AF_LVL_POS 16
group-onsemi 0:098463de4c5d 182 #define MXC_F_SPIM_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPIM_FIFO_CTRL_RX_FIFO_AF_LVL_POS))
group-onsemi 0:098463de4c5d 183 #define MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS 24
group-onsemi 0:098463de4c5d 184 #define MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS))
group-onsemi 0:098463de4c5d 185
group-onsemi 0:098463de4c5d 186 #define MXC_F_SPIM_SPCL_CTRL_SS_SAMPLE_MODE_POS 0
group-onsemi 0:098463de4c5d 187 #define MXC_F_SPIM_SPCL_CTRL_SS_SAMPLE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_SPCL_CTRL_SS_SAMPLE_MODE_POS))
group-onsemi 0:098463de4c5d 188 #define MXC_F_SPIM_SPCL_CTRL_MISO_FC_EN_POS 1
group-onsemi 0:098463de4c5d 189 #define MXC_F_SPIM_SPCL_CTRL_MISO_FC_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_SPCL_CTRL_MISO_FC_EN_POS))
group-onsemi 0:098463de4c5d 190 #define MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_OUT_POS 4
group-onsemi 0:098463de4c5d 191 #define MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_OUT_POS))
group-onsemi 0:098463de4c5d 192 #define MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS 8
group-onsemi 0:098463de4c5d 193 #define MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS))
group-onsemi 0:098463de4c5d 194
group-onsemi 0:098463de4c5d 195 #if (MXC_SPIM_REV == 0)
group-onsemi 0:098463de4c5d 196 #define MXC_F_SPIM_SPCL_CTRL_SPECIAL_MODE_3_EN_POS 16
group-onsemi 0:098463de4c5d 197 #define MXC_F_SPIM_SPCL_CTRL_SPECIAL_MODE_3_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_SPCL_CTRL_SPECIAL_MODE_3_EN_POS))
group-onsemi 0:098463de4c5d 198 #else
group-onsemi 0:098463de4c5d 199 #define MXC_F_SPIM_SPCL_CTRL_RX_FIFO_MARGIN_POS 12
group-onsemi 0:098463de4c5d 200 #define MXC_F_SPIM_SPCL_CTRL_RX_FIFO_MARGIN ((uint32_t)(0x00000007UL << MXC_F_SPIM_SPCL_CTRL_RX_FIFO_MARGIN_POS))
group-onsemi 0:098463de4c5d 201 #define MXC_F_SPIM_SPCL_CTRL_SCK_FB_DELAY_POS 16
group-onsemi 0:098463de4c5d 202 #define MXC_F_SPIM_SPCL_CTRL_SCK_FB_DELAY ((uint32_t)(0x0000000FUL << MXC_F_SPIM_SPCL_CTRL_SCK_FB_DELAY_POS))
group-onsemi 0:098463de4c5d 203 #define MXC_F_SPIM_SPCL_CTRL_SPARE_RESERVED_POS 20
group-onsemi 0:098463de4c5d 204 #define MXC_F_SPIM_SPCL_CTRL_SPARE_RESERVED ((uint32_t)(0x00000FFFUL << MXC_F_SPIM_SPCL_CTRL_SPARE_RESERVED_POS))
group-onsemi 0:098463de4c5d 205 #endif
group-onsemi 0:098463de4c5d 206
group-onsemi 0:098463de4c5d 207 #define MXC_F_SPIM_INTFL_TX_STALLED_POS 0
group-onsemi 0:098463de4c5d 208 #define MXC_F_SPIM_INTFL_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_TX_STALLED_POS))
group-onsemi 0:098463de4c5d 209 #define MXC_F_SPIM_INTFL_RX_STALLED_POS 1
group-onsemi 0:098463de4c5d 210 #define MXC_F_SPIM_INTFL_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_RX_STALLED_POS))
group-onsemi 0:098463de4c5d 211 #define MXC_F_SPIM_INTFL_TX_READY_POS 2
group-onsemi 0:098463de4c5d 212 #define MXC_F_SPIM_INTFL_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_TX_READY_POS))
group-onsemi 0:098463de4c5d 213 #define MXC_F_SPIM_INTFL_RX_DONE_POS 3
group-onsemi 0:098463de4c5d 214 #define MXC_F_SPIM_INTFL_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_RX_DONE_POS))
group-onsemi 0:098463de4c5d 215 #define MXC_F_SPIM_INTFL_TX_FIFO_AE_POS 4
group-onsemi 0:098463de4c5d 216 #define MXC_F_SPIM_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_TX_FIFO_AE_POS))
group-onsemi 0:098463de4c5d 217 #define MXC_F_SPIM_INTFL_RX_FIFO_AF_POS 5
group-onsemi 0:098463de4c5d 218 #define MXC_F_SPIM_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_RX_FIFO_AF_POS))
group-onsemi 0:098463de4c5d 219
group-onsemi 0:098463de4c5d 220 #define MXC_F_SPIM_INTEN_TX_STALLED_POS 0
group-onsemi 0:098463de4c5d 221 #define MXC_F_SPIM_INTEN_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_TX_STALLED_POS))
group-onsemi 0:098463de4c5d 222 #define MXC_F_SPIM_INTEN_RX_STALLED_POS 1
group-onsemi 0:098463de4c5d 223 #define MXC_F_SPIM_INTEN_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_RX_STALLED_POS))
group-onsemi 0:098463de4c5d 224 #define MXC_F_SPIM_INTEN_TX_READY_POS 2
group-onsemi 0:098463de4c5d 225 #define MXC_F_SPIM_INTEN_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_TX_READY_POS))
group-onsemi 0:098463de4c5d 226 #define MXC_F_SPIM_INTEN_RX_DONE_POS 3
group-onsemi 0:098463de4c5d 227 #define MXC_F_SPIM_INTEN_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_RX_DONE_POS))
group-onsemi 0:098463de4c5d 228 #define MXC_F_SPIM_INTEN_TX_FIFO_AE_POS 4
group-onsemi 0:098463de4c5d 229 #define MXC_F_SPIM_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_TX_FIFO_AE_POS))
group-onsemi 0:098463de4c5d 230 #define MXC_F_SPIM_INTEN_RX_FIFO_AF_POS 5
group-onsemi 0:098463de4c5d 231 #define MXC_F_SPIM_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_RX_FIFO_AF_POS))
group-onsemi 0:098463de4c5d 232
group-onsemi 0:098463de4c5d 233 #define MXC_F_SPIM_SIMPLE_HEADERS_TX_BIDIR_HEADER_POS 0
group-onsemi 0:098463de4c5d 234 #define MXC_F_SPIM_SIMPLE_HEADERS_TX_BIDIR_HEADER ((uint32_t)(0x00003FFFUL << MXC_F_SPIM_SIMPLE_HEADERS_TX_BIDIR_HEADER_POS))
group-onsemi 0:098463de4c5d 235 #define MXC_F_SPIM_SIMPLE_HEADERS_RX_ONLY_HEADER_POS 16
group-onsemi 0:098463de4c5d 236 #define MXC_F_SPIM_SIMPLE_HEADERS_RX_ONLY_HEADER ((uint32_t)(0x00003FFFUL << MXC_F_SPIM_SIMPLE_HEADERS_RX_ONLY_HEADER_POS))
group-onsemi 0:098463de4c5d 237
group-onsemi 0:098463de4c5d 238
group-onsemi 0:098463de4c5d 239
group-onsemi 0:098463de4c5d 240 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 241 }
group-onsemi 0:098463de4c5d 242 #endif
group-onsemi 0:098463de4c5d 243
group-onsemi 0:098463de4c5d 244 #endif /* _MXC_SPIM_REGS_H_ */
group-onsemi 0:098463de4c5d 245