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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_Maxim/TARGET_MAX32620/gpio_irq_api.c@0:098463de4c5d, 2017-01-25 (annotated)

Committer:
group-onsemi
Date:
Wed Jan 25 20:34:15 2017 +0000
Revision:
0:098463de4c5d
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /*******************************************************************************
group-onsemi 0:098463de4c5d 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
group-onsemi 0:098463de4c5d 3 *
group-onsemi 0:098463de4c5d 4 * Permission is hereby granted, free of charge, to any person obtaining a
group-onsemi 0:098463de4c5d 5 * copy of this software and associated documentation files (the "Software"),
group-onsemi 0:098463de4c5d 6 * to deal in the Software without restriction, including without limitation
group-onsemi 0:098463de4c5d 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
group-onsemi 0:098463de4c5d 8 * and/or sell copies of the Software, and to permit persons to whom the
group-onsemi 0:098463de4c5d 9 * Software is furnished to do so, subject to the following conditions:
group-onsemi 0:098463de4c5d 10 *
group-onsemi 0:098463de4c5d 11 * The above copyright notice and this permission notice shall be included
group-onsemi 0:098463de4c5d 12 * in all copies or substantial portions of the Software.
group-onsemi 0:098463de4c5d 13 *
group-onsemi 0:098463de4c5d 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
group-onsemi 0:098463de4c5d 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
group-onsemi 0:098463de4c5d 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
group-onsemi 0:098463de4c5d 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
group-onsemi 0:098463de4c5d 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
group-onsemi 0:098463de4c5d 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
group-onsemi 0:098463de4c5d 20 * OTHER DEALINGS IN THE SOFTWARE.
group-onsemi 0:098463de4c5d 21 *
group-onsemi 0:098463de4c5d 22 * Except as contained in this notice, the name of Maxim Integrated
group-onsemi 0:098463de4c5d 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
group-onsemi 0:098463de4c5d 24 * Products, Inc. Branding Policy.
group-onsemi 0:098463de4c5d 25 *
group-onsemi 0:098463de4c5d 26 * The mere transfer of this software does not imply any licenses
group-onsemi 0:098463de4c5d 27 * of trade secrets, proprietary technology, copyrights, patents,
group-onsemi 0:098463de4c5d 28 * trademarks, maskwork rights, or any other form of intellectual
group-onsemi 0:098463de4c5d 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
group-onsemi 0:098463de4c5d 30 * ownership rights.
group-onsemi 0:098463de4c5d 31 *******************************************************************************
group-onsemi 0:098463de4c5d 32 */
group-onsemi 0:098463de4c5d 33
group-onsemi 0:098463de4c5d 34 #include <stddef.h>
group-onsemi 0:098463de4c5d 35 #include "cmsis.h"
group-onsemi 0:098463de4c5d 36 #include "gpio_irq_api.h"
group-onsemi 0:098463de4c5d 37 #include "mbed_error.h"
group-onsemi 0:098463de4c5d 38 #include "ioman_regs.h"
group-onsemi 0:098463de4c5d 39 #include "pwrman_regs.h"
group-onsemi 0:098463de4c5d 40 #include "pwrseq_regs.h"
group-onsemi 0:098463de4c5d 41
group-onsemi 0:098463de4c5d 42 static gpio_irq_t *objs[MXC_GPIO_NUM_PORTS][MXC_GPIO_MAX_PINS_PER_PORT] = {{0}};
group-onsemi 0:098463de4c5d 43 static gpio_irq_handler irq_handler;
group-onsemi 0:098463de4c5d 44
group-onsemi 0:098463de4c5d 45 static void gpio_irq_wud_req(gpio_irq_t *obj)
group-onsemi 0:098463de4c5d 46 {
group-onsemi 0:098463de4c5d 47 unsigned int port = obj->port;
group-onsemi 0:098463de4c5d 48 unsigned int pin = obj->pin;
group-onsemi 0:098463de4c5d 49 uint32_t pin_mask = 1 << pin;
group-onsemi 0:098463de4c5d 50
group-onsemi 0:098463de4c5d 51 /* Ports 0-3 are controlled by wud_req0, while 4-7 are controlled by wud_req1 */
group-onsemi 0:098463de4c5d 52 /* During the time the WUD IOMAN requests are asserted (1), the GPIO Pad */
group-onsemi 0:098463de4c5d 53 /* is in HIGH Z mode, regardless of GPIO setting. This may cause bogus interrupts. */
group-onsemi 0:098463de4c5d 54 if (port < 4) {
group-onsemi 0:098463de4c5d 55 uint32_t mask = pin_mask << (port << 3);
group-onsemi 0:098463de4c5d 56 if (!(MXC_IOMAN->wud_ack0 & mask)) {
group-onsemi 0:098463de4c5d 57 MXC_IOMAN->wud_req0 |= mask;
group-onsemi 0:098463de4c5d 58 while(!(MXC_IOMAN->wud_ack0 & mask));
group-onsemi 0:098463de4c5d 59 }
group-onsemi 0:098463de4c5d 60 } else if (port < 8) {
group-onsemi 0:098463de4c5d 61 uint32_t mask = pin_mask << ((port-4) << 3);
group-onsemi 0:098463de4c5d 62 if (!(MXC_IOMAN->wud_ack1 & mask)) {
group-onsemi 0:098463de4c5d 63 MXC_IOMAN->wud_req1 |= mask;
group-onsemi 0:098463de4c5d 64 while(!(MXC_IOMAN->wud_ack1 & mask));
group-onsemi 0:098463de4c5d 65 }
group-onsemi 0:098463de4c5d 66 }
group-onsemi 0:098463de4c5d 67 }
group-onsemi 0:098463de4c5d 68
group-onsemi 0:098463de4c5d 69 /* Clear the selected pin from wake-up detect */
group-onsemi 0:098463de4c5d 70 static void gpio_irq_wud_clear(gpio_irq_t *obj)
group-onsemi 0:098463de4c5d 71 {
group-onsemi 0:098463de4c5d 72 unsigned int port = obj->port;
group-onsemi 0:098463de4c5d 73 unsigned int pin = obj->pin;
group-onsemi 0:098463de4c5d 74
group-onsemi 0:098463de4c5d 75 /* Enable modifications to WUD configuration */
group-onsemi 0:098463de4c5d 76 MXC_PWRMAN->wud_ctrl = MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE;
group-onsemi 0:098463de4c5d 77
group-onsemi 0:098463de4c5d 78 /* Select pad in WUD control */
group-onsemi 0:098463de4c5d 79 /* Note: Pads are numbered from 0-48; {0-7} => {P0.0-P0.7}, {8-15} => {P1.0-P1.7}, etc. */
group-onsemi 0:098463de4c5d 80 MXC_PWRMAN->wud_ctrl |= (port * 8) + pin;
group-onsemi 0:098463de4c5d 81
group-onsemi 0:098463de4c5d 82 /* Clear any existing WUD configuration for this pad */
group-onsemi 0:098463de4c5d 83 MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE);
group-onsemi 0:098463de4c5d 84 MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
group-onsemi 0:098463de4c5d 85 /* Clear with PULSE0; PULSE1 enables WUD */
group-onsemi 0:098463de4c5d 86 MXC_PWRMAN->wud_pulse0 = 1;
group-onsemi 0:098463de4c5d 87
group-onsemi 0:098463de4c5d 88 /* Disable configuration */
group-onsemi 0:098463de4c5d 89 MXC_PWRMAN->wud_ctrl = 0;
group-onsemi 0:098463de4c5d 90 MXC_IOMAN->wud_req0 = 0;
group-onsemi 0:098463de4c5d 91 MXC_IOMAN->wud_req1 = 0;
group-onsemi 0:098463de4c5d 92 }
group-onsemi 0:098463de4c5d 93
group-onsemi 0:098463de4c5d 94 /* Configure the selected pin for wake-up detect */
group-onsemi 0:098463de4c5d 95 static void gpio_irq_wud_config(gpio_irq_t *obj)
group-onsemi 0:098463de4c5d 96 {
group-onsemi 0:098463de4c5d 97 unsigned int port = obj->port;
group-onsemi 0:098463de4c5d 98 unsigned int pin = obj->pin;
group-onsemi 0:098463de4c5d 99 uint32_t pin_mask = 1 << pin;
group-onsemi 0:098463de4c5d 100
group-onsemi 0:098463de4c5d 101 /* Enable modifications to WUD configuration */
group-onsemi 0:098463de4c5d 102 MXC_PWRMAN->wud_ctrl = MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE;
group-onsemi 0:098463de4c5d 103
group-onsemi 0:098463de4c5d 104 /* Select pad in WUD control */
group-onsemi 0:098463de4c5d 105 /* Note: Pads are numbered from 0-48; {0-7} => {P0.0-P0.7}, {8-15} => {P1.0-P1.7}, etc. */
group-onsemi 0:098463de4c5d 106 MXC_PWRMAN->wud_ctrl |= (port * 8) + pin;
group-onsemi 0:098463de4c5d 107
group-onsemi 0:098463de4c5d 108 /* First clear any existing WUD configuration for this pad */
group-onsemi 0:098463de4c5d 109 MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE);
group-onsemi 0:098463de4c5d 110 MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
group-onsemi 0:098463de4c5d 111 /* Clear with PULSE0; PULSE1 enables WUD */
group-onsemi 0:098463de4c5d 112 MXC_PWRMAN->wud_pulse0 = 1;
group-onsemi 0:098463de4c5d 113
group-onsemi 0:098463de4c5d 114 if (obj->fall_en || obj->rise_en) {
group-onsemi 0:098463de4c5d 115 /* Configure sense level on this pad */
group-onsemi 0:098463de4c5d 116 MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE);
group-onsemi 0:098463de4c5d 117 MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
group-onsemi 0:098463de4c5d 118
group-onsemi 0:098463de4c5d 119 uint32_t in_val = MXC_GPIO->in_val[port] & pin_mask;
group-onsemi 0:098463de4c5d 120 do {
group-onsemi 0:098463de4c5d 121 if (in_val) {
group-onsemi 0:098463de4c5d 122 /* Select active low with PULSE1 (backwards from what you'd expect) */
group-onsemi 0:098463de4c5d 123 MXC_PWRMAN->wud_pulse1 = 1;
group-onsemi 0:098463de4c5d 124 } else {
group-onsemi 0:098463de4c5d 125 /* Select active high with PULSE0 (backwards from what you'd expect) */
group-onsemi 0:098463de4c5d 126 MXC_PWRMAN->wud_pulse0 = 1;
group-onsemi 0:098463de4c5d 127 }
group-onsemi 0:098463de4c5d 128 } while ((MXC_GPIO->in_val[port] & pin_mask) != in_val);
group-onsemi 0:098463de4c5d 129
group-onsemi 0:098463de4c5d 130 /* Select this pad to have the wake-up function enabled */
group-onsemi 0:098463de4c5d 131 MXC_PWRMAN->wud_ctrl &= ~(MXC_F_PWRMAN_WUD_CTRL_PAD_MODE);
group-onsemi 0:098463de4c5d 132 MXC_PWRMAN->wud_ctrl |= (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS);
group-onsemi 0:098463de4c5d 133 /* Activate with PULSE1 */
group-onsemi 0:098463de4c5d 134 MXC_PWRMAN->wud_pulse1 = 1;
group-onsemi 0:098463de4c5d 135
group-onsemi 0:098463de4c5d 136 // NOTE: Low Power Pullup/down is not normally needed in addition to
group-onsemi 0:098463de4c5d 137 // standard GPIO Pullup/downs.
group-onsemi 0:098463de4c5d 138
group-onsemi 0:098463de4c5d 139 /* Enable IOWakeup, as there is at least 1 GPIO pin configured as a wake source */
group-onsemi 0:098463de4c5d 140 MXC_PWRSEQ->msk_flags |= MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP;
group-onsemi 0:098463de4c5d 141 }
group-onsemi 0:098463de4c5d 142
group-onsemi 0:098463de4c5d 143 /* Disable configuration */
group-onsemi 0:098463de4c5d 144 MXC_PWRMAN->wud_ctrl = 0;
group-onsemi 0:098463de4c5d 145 MXC_IOMAN->wud_req0 = 0;
group-onsemi 0:098463de4c5d 146 MXC_IOMAN->wud_req1 = 0;
group-onsemi 0:098463de4c5d 147 }
group-onsemi 0:098463de4c5d 148
group-onsemi 0:098463de4c5d 149 static void handle_irq(unsigned int port)
group-onsemi 0:098463de4c5d 150 {
group-onsemi 0:098463de4c5d 151 uint32_t intfl, in_val;
group-onsemi 0:098463de4c5d 152 uint32_t mask;
group-onsemi 0:098463de4c5d 153 unsigned int pin;
group-onsemi 0:098463de4c5d 154
group-onsemi 0:098463de4c5d 155 /* Read pin state */
group-onsemi 0:098463de4c5d 156 in_val = MXC_GPIO->in_val[port];
group-onsemi 0:098463de4c5d 157
group-onsemi 0:098463de4c5d 158 /* Read interrupts */
group-onsemi 0:098463de4c5d 159 intfl = MXC_GPIO->intfl[port] & MXC_GPIO->inten[port];
group-onsemi 0:098463de4c5d 160
group-onsemi 0:098463de4c5d 161 mask = 1;
group-onsemi 0:098463de4c5d 162
group-onsemi 0:098463de4c5d 163 for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) {
group-onsemi 0:098463de4c5d 164 if (intfl & mask) {
group-onsemi 0:098463de4c5d 165 MXC_GPIO->intfl[port] = mask; /* clear interrupt */
group-onsemi 0:098463de4c5d 166 gpio_irq_event event = (in_val & mask) ? IRQ_RISE : IRQ_FALL;
group-onsemi 0:098463de4c5d 167 gpio_irq_t *obj = objs[port][pin];
group-onsemi 0:098463de4c5d 168 if (obj && obj->id) {
group-onsemi 0:098463de4c5d 169 if ((event == IRQ_RISE) && obj->rise_en) {
group-onsemi 0:098463de4c5d 170 irq_handler(obj->id, IRQ_RISE);
group-onsemi 0:098463de4c5d 171 } else if ((event == IRQ_FALL) && obj->fall_en) {
group-onsemi 0:098463de4c5d 172 irq_handler(obj->id, IRQ_FALL);
group-onsemi 0:098463de4c5d 173 }
group-onsemi 0:098463de4c5d 174 }
group-onsemi 0:098463de4c5d 175
group-onsemi 0:098463de4c5d 176 gpio_irq_wud_config(obj);
group-onsemi 0:098463de4c5d 177 }
group-onsemi 0:098463de4c5d 178 mask <<= 1;
group-onsemi 0:098463de4c5d 179 }
group-onsemi 0:098463de4c5d 180 }
group-onsemi 0:098463de4c5d 181
group-onsemi 0:098463de4c5d 182 void gpio_irq_0(void) { handle_irq(0); }
group-onsemi 0:098463de4c5d 183 void gpio_irq_1(void) { handle_irq(1); }
group-onsemi 0:098463de4c5d 184 void gpio_irq_2(void) { handle_irq(2); }
group-onsemi 0:098463de4c5d 185 void gpio_irq_3(void) { handle_irq(3); }
group-onsemi 0:098463de4c5d 186 void gpio_irq_4(void) { handle_irq(4); }
group-onsemi 0:098463de4c5d 187 void gpio_irq_5(void) { handle_irq(5); }
group-onsemi 0:098463de4c5d 188 void gpio_irq_6(void) { handle_irq(6); }
group-onsemi 0:098463de4c5d 189
group-onsemi 0:098463de4c5d 190 int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint32_t id)
group-onsemi 0:098463de4c5d 191 {
group-onsemi 0:098463de4c5d 192 if (name == NC) {
group-onsemi 0:098463de4c5d 193 return -1;
group-onsemi 0:098463de4c5d 194 }
group-onsemi 0:098463de4c5d 195
group-onsemi 0:098463de4c5d 196 uint8_t port = PINNAME_TO_PORT(name);
group-onsemi 0:098463de4c5d 197 uint8_t pin = PINNAME_TO_PIN(name);
group-onsemi 0:098463de4c5d 198
group-onsemi 0:098463de4c5d 199 if ((port > MXC_GPIO_NUM_PORTS) || (pin > MXC_GPIO_MAX_PINS_PER_PORT)) {
group-onsemi 0:098463de4c5d 200 return 1;
group-onsemi 0:098463de4c5d 201 }
group-onsemi 0:098463de4c5d 202
group-onsemi 0:098463de4c5d 203 obj->port = port;
group-onsemi 0:098463de4c5d 204 obj->pin = pin;
group-onsemi 0:098463de4c5d 205 obj->id = id;
group-onsemi 0:098463de4c5d 206 objs[port][pin] = obj;
group-onsemi 0:098463de4c5d 207
group-onsemi 0:098463de4c5d 208 /* register handlers */
group-onsemi 0:098463de4c5d 209 irq_handler = handler;
group-onsemi 0:098463de4c5d 210 NVIC_SetVector(GPIO_P0_IRQn, (uint32_t)gpio_irq_0);
group-onsemi 0:098463de4c5d 211 NVIC_SetVector(GPIO_P1_IRQn, (uint32_t)gpio_irq_1);
group-onsemi 0:098463de4c5d 212 NVIC_SetVector(GPIO_P2_IRQn, (uint32_t)gpio_irq_2);
group-onsemi 0:098463de4c5d 213 NVIC_SetVector(GPIO_P3_IRQn, (uint32_t)gpio_irq_3);
group-onsemi 0:098463de4c5d 214 NVIC_SetVector(GPIO_P4_IRQn, (uint32_t)gpio_irq_4);
group-onsemi 0:098463de4c5d 215 NVIC_SetVector(GPIO_P5_IRQn, (uint32_t)gpio_irq_5);
group-onsemi 0:098463de4c5d 216 NVIC_SetVector(GPIO_P6_IRQn, (uint32_t)gpio_irq_6);
group-onsemi 0:098463de4c5d 217
group-onsemi 0:098463de4c5d 218 /* request WUD in case the application is going to sleep */
group-onsemi 0:098463de4c5d 219 gpio_irq_wud_req(obj);
group-onsemi 0:098463de4c5d 220
group-onsemi 0:098463de4c5d 221 /* disable the interrupt locally */
group-onsemi 0:098463de4c5d 222 MXC_GPIO->int_mode[port] &= ~(0xF << (pin*4));
group-onsemi 0:098463de4c5d 223
group-onsemi 0:098463de4c5d 224 /* clear a pending request */
group-onsemi 0:098463de4c5d 225 MXC_GPIO->intfl[port] = 1 << pin;
group-onsemi 0:098463de4c5d 226
group-onsemi 0:098463de4c5d 227 /* enable the requested interrupt */
group-onsemi 0:098463de4c5d 228 MXC_GPIO->inten[port] |= (1 << pin);
group-onsemi 0:098463de4c5d 229 NVIC_EnableIRQ((IRQn_Type)((uint32_t)GPIO_P0_IRQn + port));
group-onsemi 0:098463de4c5d 230
group-onsemi 0:098463de4c5d 231 return 0;
group-onsemi 0:098463de4c5d 232 }
group-onsemi 0:098463de4c5d 233
group-onsemi 0:098463de4c5d 234 void gpio_irq_free(gpio_irq_t *obj)
group-onsemi 0:098463de4c5d 235 {
group-onsemi 0:098463de4c5d 236 /* disable interrupt */
group-onsemi 0:098463de4c5d 237 MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin);
group-onsemi 0:098463de4c5d 238 MXC_GPIO->int_mode[obj->port] &= ~(MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
group-onsemi 0:098463de4c5d 239 objs[obj->port][obj->pin] = NULL;
group-onsemi 0:098463de4c5d 240 gpio_irq_wud_clear(obj);
group-onsemi 0:098463de4c5d 241 }
group-onsemi 0:098463de4c5d 242
group-onsemi 0:098463de4c5d 243 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
group-onsemi 0:098463de4c5d 244 {
group-onsemi 0:098463de4c5d 245 if (event == IRQ_FALL) {
group-onsemi 0:098463de4c5d 246 obj->fall_en = enable;
group-onsemi 0:098463de4c5d 247 } else if (event == IRQ_RISE) {
group-onsemi 0:098463de4c5d 248 obj->rise_en = enable;
group-onsemi 0:098463de4c5d 249 }
group-onsemi 0:098463de4c5d 250
group-onsemi 0:098463de4c5d 251 if (obj->fall_en || obj->rise_en) {
group-onsemi 0:098463de4c5d 252 MXC_GPIO->int_mode[obj->port] |= (MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
group-onsemi 0:098463de4c5d 253 gpio_irq_wud_config(obj); /* enable WUD for this pin so we may wake from deepsleep as well */
group-onsemi 0:098463de4c5d 254 } else {
group-onsemi 0:098463de4c5d 255 MXC_GPIO->int_mode[obj->port] &= (MXC_V_GPIO_INT_MODE_ANY_EDGE << (obj->pin*4));
group-onsemi 0:098463de4c5d 256 gpio_irq_wud_clear(obj);
group-onsemi 0:098463de4c5d 257 }
group-onsemi 0:098463de4c5d 258 }
group-onsemi 0:098463de4c5d 259
group-onsemi 0:098463de4c5d 260 void gpio_irq_enable(gpio_irq_t *obj)
group-onsemi 0:098463de4c5d 261 {
group-onsemi 0:098463de4c5d 262 MXC_GPIO->inten[obj->port] |= (1 << obj->pin);
group-onsemi 0:098463de4c5d 263 gpio_irq_wud_config(obj);
group-onsemi 0:098463de4c5d 264 }
group-onsemi 0:098463de4c5d 265
group-onsemi 0:098463de4c5d 266 void gpio_irq_disable(gpio_irq_t *obj)
group-onsemi 0:098463de4c5d 267 {
group-onsemi 0:098463de4c5d 268 MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin);
group-onsemi 0:098463de4c5d 269 gpio_irq_wud_clear(obj);
group-onsemi 0:098463de4c5d 270 }
group-onsemi 0:098463de4c5d 271
group-onsemi 0:098463de4c5d 272 gpio_irq_t *gpio_irq_get_obj(PinName name)
group-onsemi 0:098463de4c5d 273 {
group-onsemi 0:098463de4c5d 274 if (name == NC) {
group-onsemi 0:098463de4c5d 275 return NULL;
group-onsemi 0:098463de4c5d 276 }
group-onsemi 0:098463de4c5d 277
group-onsemi 0:098463de4c5d 278 unsigned int port = PINNAME_TO_PORT(name);
group-onsemi 0:098463de4c5d 279 unsigned int pin = PINNAME_TO_PIN(name);
group-onsemi 0:098463de4c5d 280
group-onsemi 0:098463de4c5d 281 if ((port > MXC_GPIO_NUM_PORTS) || (pin > MXC_GPIO_MAX_PINS_PER_PORT)) {
group-onsemi 0:098463de4c5d 282 return NULL;
group-onsemi 0:098463de4c5d 283 }
group-onsemi 0:098463de4c5d 284
group-onsemi 0:098463de4c5d 285 return objs[port][pin];
group-onsemi 0:098463de4c5d 286 }