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targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_bus.h@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /**
group-onsemi 0:098463de4c5d 2 ******************************************************************************
group-onsemi 0:098463de4c5d 3 * @file stm32l1xx_ll_bus.h
group-onsemi 0:098463de4c5d 4 * @author MCD Application Team
group-onsemi 0:098463de4c5d 5 * @version V1.2.0
group-onsemi 0:098463de4c5d 6 * @date 01-July-2016
group-onsemi 0:098463de4c5d 7 * @brief Header file of BUS LL module.
group-onsemi 0:098463de4c5d 8
group-onsemi 0:098463de4c5d 9 @verbatim
group-onsemi 0:098463de4c5d 10 ##### RCC Limitations #####
group-onsemi 0:098463de4c5d 11 ==============================================================================
group-onsemi 0:098463de4c5d 12 [..]
group-onsemi 0:098463de4c5d 13 A delay between an RCC peripheral clock enable and the effective peripheral
group-onsemi 0:098463de4c5d 14 enabling should be taken into account in order to manage the peripheral read/write
group-onsemi 0:098463de4c5d 15 from/to registers.
group-onsemi 0:098463de4c5d 16 (+) This delay depends on the peripheral mapping.
group-onsemi 0:098463de4c5d 17 (++) AHB & APB peripherals, 1 dummy read is necessary
group-onsemi 0:098463de4c5d 18
group-onsemi 0:098463de4c5d 19 [..]
group-onsemi 0:098463de4c5d 20 Workarounds:
group-onsemi 0:098463de4c5d 21 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
group-onsemi 0:098463de4c5d 22 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
group-onsemi 0:098463de4c5d 23
group-onsemi 0:098463de4c5d 24 @endverbatim
group-onsemi 0:098463de4c5d 25 ******************************************************************************
group-onsemi 0:098463de4c5d 26 * @attention
group-onsemi 0:098463de4c5d 27 *
group-onsemi 0:098463de4c5d 28 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
group-onsemi 0:098463de4c5d 29 *
group-onsemi 0:098463de4c5d 30 * Redistribution and use in source and binary forms, with or without modification,
group-onsemi 0:098463de4c5d 31 * are permitted provided that the following conditions are met:
group-onsemi 0:098463de4c5d 32 * 1. Redistributions of source code must retain the above copyright notice,
group-onsemi 0:098463de4c5d 33 * this list of conditions and the following disclaimer.
group-onsemi 0:098463de4c5d 34 * 2. Redistributions in binary form must reproduce the above copyright notice,
group-onsemi 0:098463de4c5d 35 * this list of conditions and the following disclaimer in the documentation
group-onsemi 0:098463de4c5d 36 * and/or other materials provided with the distribution.
group-onsemi 0:098463de4c5d 37 * 3. Neither the name of STMicroelectronics nor the names of its contributors
group-onsemi 0:098463de4c5d 38 * may be used to endorse or promote products derived from this software
group-onsemi 0:098463de4c5d 39 * without specific prior written permission.
group-onsemi 0:098463de4c5d 40 *
group-onsemi 0:098463de4c5d 41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
group-onsemi 0:098463de4c5d 42 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
group-onsemi 0:098463de4c5d 43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
group-onsemi 0:098463de4c5d 44 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
group-onsemi 0:098463de4c5d 45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
group-onsemi 0:098463de4c5d 46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
group-onsemi 0:098463de4c5d 47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
group-onsemi 0:098463de4c5d 48 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
group-onsemi 0:098463de4c5d 49 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
group-onsemi 0:098463de4c5d 50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
group-onsemi 0:098463de4c5d 51 *
group-onsemi 0:098463de4c5d 52 ******************************************************************************
group-onsemi 0:098463de4c5d 53 */
group-onsemi 0:098463de4c5d 54
group-onsemi 0:098463de4c5d 55 /* Define to prevent recursive inclusion -------------------------------------*/
group-onsemi 0:098463de4c5d 56 #ifndef __STM32L1xx_LL_BUS_H
group-onsemi 0:098463de4c5d 57 #define __STM32L1xx_LL_BUS_H
group-onsemi 0:098463de4c5d 58
group-onsemi 0:098463de4c5d 59 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 60 extern "C" {
group-onsemi 0:098463de4c5d 61 #endif
group-onsemi 0:098463de4c5d 62
group-onsemi 0:098463de4c5d 63 /* Includes ------------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 64 #include "stm32l1xx.h"
group-onsemi 0:098463de4c5d 65
group-onsemi 0:098463de4c5d 66 /** @addtogroup STM32L1xx_LL_Driver
group-onsemi 0:098463de4c5d 67 * @{
group-onsemi 0:098463de4c5d 68 */
group-onsemi 0:098463de4c5d 69
group-onsemi 0:098463de4c5d 70 #if defined(RCC)
group-onsemi 0:098463de4c5d 71
group-onsemi 0:098463de4c5d 72 /** @defgroup BUS_LL BUS
group-onsemi 0:098463de4c5d 73 * @{
group-onsemi 0:098463de4c5d 74 */
group-onsemi 0:098463de4c5d 75
group-onsemi 0:098463de4c5d 76 /* Private types -------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 77 /* Private variables ---------------------------------------------------------*/
group-onsemi 0:098463de4c5d 78
group-onsemi 0:098463de4c5d 79 /* Private constants ---------------------------------------------------------*/
group-onsemi 0:098463de4c5d 80
group-onsemi 0:098463de4c5d 81 /* Private macros ------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 82
group-onsemi 0:098463de4c5d 83 /* Exported types ------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 84 /* Exported constants --------------------------------------------------------*/
group-onsemi 0:098463de4c5d 85 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
group-onsemi 0:098463de4c5d 86 * @{
group-onsemi 0:098463de4c5d 87 */
group-onsemi 0:098463de4c5d 88
group-onsemi 0:098463de4c5d 89 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
group-onsemi 0:098463de4c5d 90 * @{
group-onsemi 0:098463de4c5d 91 */
group-onsemi 0:098463de4c5d 92 #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
group-onsemi 0:098463de4c5d 93 #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN
group-onsemi 0:098463de4c5d 94 #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN
group-onsemi 0:098463de4c5d 95 #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN
group-onsemi 0:098463de4c5d 96 #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN
group-onsemi 0:098463de4c5d 97 #if defined(GPIOE)
group-onsemi 0:098463de4c5d 98 #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN
group-onsemi 0:098463de4c5d 99 #endif/*GPIOE*/
group-onsemi 0:098463de4c5d 100 #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHBENR_GPIOHEN
group-onsemi 0:098463de4c5d 101 #if defined(GPIOF)
group-onsemi 0:098463de4c5d 102 #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN
group-onsemi 0:098463de4c5d 103 #endif/*GPIOF*/
group-onsemi 0:098463de4c5d 104 #if defined(GPIOG)
group-onsemi 0:098463de4c5d 105 #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHBENR_GPIOGEN
group-onsemi 0:098463de4c5d 106 #endif/*GPIOG*/
group-onsemi 0:098463de4c5d 107 #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBLPENR_SRAMLPEN
group-onsemi 0:098463de4c5d 108 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
group-onsemi 0:098463de4c5d 109 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
group-onsemi 0:098463de4c5d 110 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
group-onsemi 0:098463de4c5d 111 #if defined(DMA2)
group-onsemi 0:098463de4c5d 112 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
group-onsemi 0:098463de4c5d 113 #endif/*DMA2*/
group-onsemi 0:098463de4c5d 114 #if defined(AES)
group-onsemi 0:098463de4c5d 115 #define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_AESEN
group-onsemi 0:098463de4c5d 116 #endif/*AES*/
group-onsemi 0:098463de4c5d 117 #if defined(FSMC_Bank1)
group-onsemi 0:098463de4c5d 118 #define LL_AHB1_GRP1_PERIPH_FSMC RCC_AHBENR_FSMCEN
group-onsemi 0:098463de4c5d 119 #endif/*FSMC_Bank1*/
group-onsemi 0:098463de4c5d 120 /**
group-onsemi 0:098463de4c5d 121 * @}
group-onsemi 0:098463de4c5d 122 */
group-onsemi 0:098463de4c5d 123
group-onsemi 0:098463de4c5d 124 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
group-onsemi 0:098463de4c5d 125 * @{
group-onsemi 0:098463de4c5d 126 */
group-onsemi 0:098463de4c5d 127 #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
group-onsemi 0:098463de4c5d 128 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
group-onsemi 0:098463de4c5d 129 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
group-onsemi 0:098463de4c5d 130 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
group-onsemi 0:098463de4c5d 131 #if defined(TIM5)
group-onsemi 0:098463de4c5d 132 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
group-onsemi 0:098463de4c5d 133 #endif /*TIM5*/
group-onsemi 0:098463de4c5d 134 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
group-onsemi 0:098463de4c5d 135 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
group-onsemi 0:098463de4c5d 136 #if defined(LCD)
group-onsemi 0:098463de4c5d 137 #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR_LCDEN
group-onsemi 0:098463de4c5d 138 #endif /*LCD*/
group-onsemi 0:098463de4c5d 139 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
group-onsemi 0:098463de4c5d 140 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
group-onsemi 0:098463de4c5d 141 #if defined(SPI3)
group-onsemi 0:098463de4c5d 142 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
group-onsemi 0:098463de4c5d 143 #endif /*SPI3*/
group-onsemi 0:098463de4c5d 144 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
group-onsemi 0:098463de4c5d 145 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
group-onsemi 0:098463de4c5d 146 #if defined(UART4)
group-onsemi 0:098463de4c5d 147 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
group-onsemi 0:098463de4c5d 148 #endif /*UART4*/
group-onsemi 0:098463de4c5d 149 #if defined(UART5)
group-onsemi 0:098463de4c5d 150 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
group-onsemi 0:098463de4c5d 151 #endif /*UART5*/
group-onsemi 0:098463de4c5d 152 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
group-onsemi 0:098463de4c5d 153 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
group-onsemi 0:098463de4c5d 154 #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
group-onsemi 0:098463de4c5d 155 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
group-onsemi 0:098463de4c5d 156 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
group-onsemi 0:098463de4c5d 157 #define LL_APB1_GRP1_PERIPH_COMP RCC_APB1ENR_COMPEN
group-onsemi 0:098463de4c5d 158 #if defined(OPAMP)
group-onsemi 0:098463de4c5d 159 /* Note: Peripherals COMP and OPAMP share the same clock domain */
group-onsemi 0:098463de4c5d 160 #define LL_APB1_GRP1_PERIPH_OPAMP LL_APB1_GRP1_PERIPH_COMP
group-onsemi 0:098463de4c5d 161 #endif
group-onsemi 0:098463de4c5d 162 /**
group-onsemi 0:098463de4c5d 163 * @}
group-onsemi 0:098463de4c5d 164 */
group-onsemi 0:098463de4c5d 165
group-onsemi 0:098463de4c5d 166 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
group-onsemi 0:098463de4c5d 167 * @{
group-onsemi 0:098463de4c5d 168 */
group-onsemi 0:098463de4c5d 169 #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
group-onsemi 0:098463de4c5d 170 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
group-onsemi 0:098463de4c5d 171 #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
group-onsemi 0:098463de4c5d 172 #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
group-onsemi 0:098463de4c5d 173 #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
group-onsemi 0:098463de4c5d 174 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
group-onsemi 0:098463de4c5d 175 #if defined(SDIO)
group-onsemi 0:098463de4c5d 176 #define LL_APB2_GRP1_PERIPH_SDIO RCC_APB2ENR_SDIOEN
group-onsemi 0:098463de4c5d 177 #endif /*SDIO*/
group-onsemi 0:098463de4c5d 178 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
group-onsemi 0:098463de4c5d 179 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
group-onsemi 0:098463de4c5d 180 /**
group-onsemi 0:098463de4c5d 181 * @}
group-onsemi 0:098463de4c5d 182 */
group-onsemi 0:098463de4c5d 183
group-onsemi 0:098463de4c5d 184 /**
group-onsemi 0:098463de4c5d 185 * @}
group-onsemi 0:098463de4c5d 186 */
group-onsemi 0:098463de4c5d 187
group-onsemi 0:098463de4c5d 188 /* Exported macro ------------------------------------------------------------*/
group-onsemi 0:098463de4c5d 189
group-onsemi 0:098463de4c5d 190 /* Exported functions --------------------------------------------------------*/
group-onsemi 0:098463de4c5d 191 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
group-onsemi 0:098463de4c5d 192 * @{
group-onsemi 0:098463de4c5d 193 */
group-onsemi 0:098463de4c5d 194
group-onsemi 0:098463de4c5d 195 /** @defgroup BUS_LL_EF_AHB1 AHB1
group-onsemi 0:098463de4c5d 196 * @{
group-onsemi 0:098463de4c5d 197 */
group-onsemi 0:098463de4c5d 198
group-onsemi 0:098463de4c5d 199 /**
group-onsemi 0:098463de4c5d 200 * @brief Enable AHB1 peripherals clock.
group-onsemi 0:098463de4c5d 201 * @rmtoll AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 202 * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 203 * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 204 * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 205 * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 206 * AHBENR GPIOHEN LL_AHB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 207 * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 208 * AHBENR GPIOGEN LL_AHB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 209 * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 210 * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 211 * AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 212 * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 213 * AHBENR AESEN LL_AHB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 214 * AHBENR FSMCEN LL_AHB1_GRP1_EnableClock
group-onsemi 0:098463de4c5d 215 * @param Periphs This parameter can be a combination of the following values:
group-onsemi 0:098463de4c5d 216 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
group-onsemi 0:098463de4c5d 217 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
group-onsemi 0:098463de4c5d 218 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
group-onsemi 0:098463de4c5d 219 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
group-onsemi 0:098463de4c5d 220 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
group-onsemi 0:098463de4c5d 221 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
group-onsemi 0:098463de4c5d 222 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
group-onsemi 0:098463de4c5d 223 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
group-onsemi 0:098463de4c5d 224 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
group-onsemi 0:098463de4c5d 225 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
group-onsemi 0:098463de4c5d 226 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
group-onsemi 0:098463de4c5d 227 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
group-onsemi 0:098463de4c5d 228 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
group-onsemi 0:098463de4c5d 229 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
group-onsemi 0:098463de4c5d 230 *
group-onsemi 0:098463de4c5d 231 * (*) value not defined in all devices.
group-onsemi 0:098463de4c5d 232 * @retval None
group-onsemi 0:098463de4c5d 233 */
group-onsemi 0:098463de4c5d 234 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
group-onsemi 0:098463de4c5d 235 {
group-onsemi 0:098463de4c5d 236 __IO uint32_t tmpreg;
group-onsemi 0:098463de4c5d 237 SET_BIT(RCC->AHBENR, Periphs);
group-onsemi 0:098463de4c5d 238 /* Delay after an RCC peripheral clock enabling */
group-onsemi 0:098463de4c5d 239 tmpreg = READ_BIT(RCC->AHBENR, Periphs);
group-onsemi 0:098463de4c5d 240 (void)tmpreg;
group-onsemi 0:098463de4c5d 241 }
group-onsemi 0:098463de4c5d 242
group-onsemi 0:098463de4c5d 243 /**
group-onsemi 0:098463de4c5d 244 * @brief Check if AHB1 peripheral clock is enabled or not
group-onsemi 0:098463de4c5d 245 * @rmtoll AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 246 * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 247 * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 248 * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 249 * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 250 * AHBENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 251 * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 252 * AHBENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 253 * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 254 * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 255 * AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 256 * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 257 * AHBENR AESEN LL_AHB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 258 * AHBENR FSMCEN LL_AHB1_GRP1_IsEnabledClock
group-onsemi 0:098463de4c5d 259 * @param Periphs This parameter can be a combination of the following values:
group-onsemi 0:098463de4c5d 260 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
group-onsemi 0:098463de4c5d 261 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
group-onsemi 0:098463de4c5d 262 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
group-onsemi 0:098463de4c5d 263 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
group-onsemi 0:098463de4c5d 264 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
group-onsemi 0:098463de4c5d 265 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
group-onsemi 0:098463de4c5d 266 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
group-onsemi 0:098463de4c5d 267 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
group-onsemi 0:098463de4c5d 268 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
group-onsemi 0:098463de4c5d 269 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
group-onsemi 0:098463de4c5d 270 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
group-onsemi 0:098463de4c5d 271 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
group-onsemi 0:098463de4c5d 272 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
group-onsemi 0:098463de4c5d 273 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
group-onsemi 0:098463de4c5d 274 *
group-onsemi 0:098463de4c5d 275 * (*) value not defined in all devices.
group-onsemi 0:098463de4c5d 276 * @retval State of Periphs (1 or 0).
group-onsemi 0:098463de4c5d 277 */
group-onsemi 0:098463de4c5d 278 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
group-onsemi 0:098463de4c5d 279 {
group-onsemi 0:098463de4c5d 280 return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
group-onsemi 0:098463de4c5d 281 }
group-onsemi 0:098463de4c5d 282
group-onsemi 0:098463de4c5d 283 /**
group-onsemi 0:098463de4c5d 284 * @brief Disable AHB1 peripherals clock.
group-onsemi 0:098463de4c5d 285 * @rmtoll AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 286 * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 287 * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 288 * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 289 * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 290 * AHBENR GPIOHEN LL_AHB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 291 * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 292 * AHBENR GPIOGEN LL_AHB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 293 * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 294 * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 295 * AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 296 * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 297 * AHBENR AESEN LL_AHB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 298 * AHBENR FSMCEN LL_AHB1_GRP1_DisableClock
group-onsemi 0:098463de4c5d 299 * @param Periphs This parameter can be a combination of the following values:
group-onsemi 0:098463de4c5d 300 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
group-onsemi 0:098463de4c5d 301 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
group-onsemi 0:098463de4c5d 302 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
group-onsemi 0:098463de4c5d 303 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
group-onsemi 0:098463de4c5d 304 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
group-onsemi 0:098463de4c5d 305 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
group-onsemi 0:098463de4c5d 306 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
group-onsemi 0:098463de4c5d 307 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
group-onsemi 0:098463de4c5d 308 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
group-onsemi 0:098463de4c5d 309 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
group-onsemi 0:098463de4c5d 310 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
group-onsemi 0:098463de4c5d 311 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
group-onsemi 0:098463de4c5d 312 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
group-onsemi 0:098463de4c5d 313 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
group-onsemi 0:098463de4c5d 314 *
group-onsemi 0:098463de4c5d 315 * (*) value not defined in all devices.
group-onsemi 0:098463de4c5d 316 * @retval None
group-onsemi 0:098463de4c5d 317 */
group-onsemi 0:098463de4c5d 318 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
group-onsemi 0:098463de4c5d 319 {
group-onsemi 0:098463de4c5d 320 CLEAR_BIT(RCC->AHBENR, Periphs);
group-onsemi 0:098463de4c5d 321 }
group-onsemi 0:098463de4c5d 322
group-onsemi 0:098463de4c5d 323 /**
group-onsemi 0:098463de4c5d 324 * @brief Force AHB1 peripherals reset.
group-onsemi 0:098463de4c5d 325 * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 326 * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 327 * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 328 * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 329 * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 330 * AHBRSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 331 * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 332 * AHBRSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 333 * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 334 * AHBRSTR FLITFRST LL_AHB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 335 * AHBRSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 336 * AHBRSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 337 * AHBRSTR AESRST LL_AHB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 338 * AHBRSTR FSMCRST LL_AHB1_GRP1_ForceReset
group-onsemi 0:098463de4c5d 339 * @param Periphs This parameter can be a combination of the following values:
group-onsemi 0:098463de4c5d 340 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
group-onsemi 0:098463de4c5d 341 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
group-onsemi 0:098463de4c5d 342 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
group-onsemi 0:098463de4c5d 343 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
group-onsemi 0:098463de4c5d 344 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
group-onsemi 0:098463de4c5d 345 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
group-onsemi 0:098463de4c5d 346 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
group-onsemi 0:098463de4c5d 347 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
group-onsemi 0:098463de4c5d 348 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
group-onsemi 0:098463de4c5d 349 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
group-onsemi 0:098463de4c5d 350 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
group-onsemi 0:098463de4c5d 351 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
group-onsemi 0:098463de4c5d 352 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
group-onsemi 0:098463de4c5d 353 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
group-onsemi 0:098463de4c5d 354 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
group-onsemi 0:098463de4c5d 355 *
group-onsemi 0:098463de4c5d 356 * (*) value not defined in all devices.
group-onsemi 0:098463de4c5d 357 * @retval None
group-onsemi 0:098463de4c5d 358 */
group-onsemi 0:098463de4c5d 359 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
group-onsemi 0:098463de4c5d 360 {
group-onsemi 0:098463de4c5d 361 SET_BIT(RCC->AHBRSTR, Periphs);
group-onsemi 0:098463de4c5d 362 }
group-onsemi 0:098463de4c5d 363
group-onsemi 0:098463de4c5d 364 /**
group-onsemi 0:098463de4c5d 365 * @brief Release AHB1 peripherals reset.
group-onsemi 0:098463de4c5d 366 * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 367 * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 368 * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 369 * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 370 * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 371 * AHBRSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 372 * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 373 * AHBRSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 374 * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 375 * AHBRSTR FLITFRST LL_AHB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 376 * AHBRSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 377 * AHBRSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 378 * AHBRSTR AESRST LL_AHB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 379 * AHBRSTR FSMCRST LL_AHB1_GRP1_ReleaseReset
group-onsemi 0:098463de4c5d 380 * @param Periphs This parameter can be a combination of the following values:
group-onsemi 0:098463de4c5d 381 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
group-onsemi 0:098463de4c5d 382 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
group-onsemi 0:098463de4c5d 383 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
group-onsemi 0:098463de4c5d 384 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
group-onsemi 0:098463de4c5d 385 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
group-onsemi 0:098463de4c5d 386 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
group-onsemi 0:098463de4c5d 387 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
group-onsemi 0:098463de4c5d 388 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
group-onsemi 0:098463de4c5d 389 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
group-onsemi 0:098463de4c5d 390 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
group-onsemi 0:098463de4c5d 391 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
group-onsemi 0:098463de4c5d 392 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
group-onsemi 0:098463de4c5d 393 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
group-onsemi 0:098463de4c5d 394 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
group-onsemi 0:098463de4c5d 395 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
group-onsemi 0:098463de4c5d 396 *
group-onsemi 0:098463de4c5d 397 * (*) value not defined in all devices.
group-onsemi 0:098463de4c5d 398 * @retval None
group-onsemi 0:098463de4c5d 399 */
group-onsemi 0:098463de4c5d 400 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
group-onsemi 0:098463de4c5d 401 {
group-onsemi 0:098463de4c5d 402 CLEAR_BIT(RCC->AHBRSTR, Periphs);
group-onsemi 0:098463de4c5d 403 }
group-onsemi 0:098463de4c5d 404
group-onsemi 0:098463de4c5d 405 /**
group-onsemi 0:098463de4c5d 406 * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode.
group-onsemi 0:098463de4c5d 407 * @rmtoll AHBLPENR GPIOALPEN LL_AHB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 408 * AHBLPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 409 * AHBLPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 410 * AHBLPENR GPIODLPEN LL_AHB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 411 * AHBLPENR GPIOELPEN LL_AHB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 412 * AHBLPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 413 * AHBLPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 414 * AHBLPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 415 * AHBLPENR CRCLPEN LL_AHB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 416 * AHBLPENR FLITFLPEN LL_AHB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 417 * AHBLPENR SRAMLPEN LL_AHB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 418 * AHBLPENR DMA1LPEN LL_AHB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 419 * AHBLPENR DMA2LPEN LL_AHB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 420 * AHBLPENR AESLPEN LL_AHB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 421 * AHBLPENR FSMCLPEN LL_AHB1_GRP1_EnableClockSleep
group-onsemi 0:098463de4c5d 422 * @param Periphs This parameter can be a combination of the following values:
group-onsemi 0:098463de4c5d 423 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
group-onsemi 0:098463de4c5d 424 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
group-onsemi 0:098463de4c5d 425 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
group-onsemi 0:098463de4c5d 426 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
group-onsemi 0:098463de4c5d 427 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
group-onsemi 0:098463de4c5d 428 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
group-onsemi 0:098463de4c5d 429 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
group-onsemi 0:098463de4c5d 430 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
group-onsemi 0:098463de4c5d 431 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
group-onsemi 0:098463de4c5d 432 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
group-onsemi 0:098463de4c5d 433 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
group-onsemi 0:098463de4c5d 434 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
group-onsemi 0:098463de4c5d 435 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
group-onsemi 0:098463de4c5d 436 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
group-onsemi 0:098463de4c5d 437 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
group-onsemi 0:098463de4c5d 438 *
group-onsemi 0:098463de4c5d 439 * (*) value not defined in all devices.
group-onsemi 0:098463de4c5d 440 * @retval None
group-onsemi 0:098463de4c5d 441 */
group-onsemi 0:098463de4c5d 442 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
group-onsemi 0:098463de4c5d 443 {
group-onsemi 0:098463de4c5d 444 __IO uint32_t tmpreg;
group-onsemi 0:098463de4c5d 445 SET_BIT(RCC->AHBLPENR, Periphs);
group-onsemi 0:098463de4c5d 446 /* Delay after an RCC peripheral clock enabling */
group-onsemi 0:098463de4c5d 447 tmpreg = READ_BIT(RCC->AHBLPENR, Periphs);
group-onsemi 0:098463de4c5d 448 (void)tmpreg;
group-onsemi 0:098463de4c5d 449 }
group-onsemi 0:098463de4c5d 450
group-onsemi 0:098463de4c5d 451 /**
group-onsemi 0:098463de4c5d 452 * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode.
group-onsemi 0:098463de4c5d 453 * @rmtoll AHBLPENR GPIOALPEN LL_AHB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 454 * AHBLPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 455 * AHBLPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 456 * AHBLPENR GPIODLPEN LL_AHB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 457 * AHBLPENR GPIOELPEN LL_AHB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 458 * AHBLPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 459 * AHBLPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 460 * AHBLPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 461 * AHBLPENR CRCLPEN LL_AHB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 462 * AHBLPENR FLITFLPEN LL_AHB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 463 * AHBLPENR SRAMLPEN LL_AHB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 464 * AHBLPENR DMA1LPEN LL_AHB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 465 * AHBLPENR DMA2LPEN LL_AHB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 466 * AHBLPENR AESLPEN LL_AHB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 467 * AHBLPENR FSMCLPEN LL_AHB1_GRP1_DisableClockSleep
group-onsemi 0:098463de4c5d 468 * @param Periphs This parameter can be a combination of the following values:
group-onsemi 0:098463de4c5d 469 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
group-onsemi 0:098463de4c5d 470 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
group-onsemi 0:098463de4c5d 471 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
group-onsemi 0:098463de4c5d 472 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
group-onsemi 0:098463de4c5d 473 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
group-onsemi 0:098463de4c5d 474 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
group-onsemi 0:098463de4c5d 475 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
group-onsemi 0:098463de4c5d 476 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
group-onsemi 0:098463de4c5d 477 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
group-onsemi 0:098463de4c5d 478 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
group-onsemi 0:098463de4c5d 479 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
group-onsemi 0:098463de4c5d 480 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
group-onsemi 0:098463de4c5d 481 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
group-onsemi 0:098463de4c5d 482 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
group-onsemi 0:098463de4c5d 483 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
group-onsemi 0:098463de4c5d 484 *
group-onsemi 0:098463de4c5d 485 * (*) value not defined in all devices.
group-onsemi 0:098463de4c5d 486 * @retval None
group-onsemi 0:098463de4c5d 487 */
group-onsemi 0:098463de4c5d 488 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
group-onsemi 0:098463de4c5d 489 {
group-onsemi 0:098463de4c5d 490 CLEAR_BIT(RCC->AHBLPENR, Periphs);
group-onsemi 0:098463de4c5d 491 }
group-onsemi 0:098463de4c5d 492
group-onsemi 0:098463de4c5d 493 /**
group-onsemi 0:098463de4c5d 494 * @}
group-onsemi 0:098463de4c5d 495 */
group-onsemi 0:098463de4c5d 496
group-onsemi 0:098463de4c5d 497 /** @defgroup BUS_LL_EF_APB1 APB1
group-onsemi 0:098463de4c5d 498 * @{
group-onsemi 0:098463de4c5d 499 */
group-onsemi 0:098463de4c5d 500
group-onsemi 0:098463de4c5d 501 /**
group-onsemi 0:098463de4c5d 502 * @brief Enable APB1 peripherals clock.
group-onsemi 0:098463de4c5d 503 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 504 * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 505 * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 506 * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 507 * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 508 * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 509 * APB1ENR LCDEN LL_APB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 510 * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 511 * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 512 * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 513 * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 514 * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 515 * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 516 * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 517 * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 518 * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 519 * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 520 * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 521 * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 522 * APB1ENR COMPEN LL_APB1_GRP1_EnableClock
group-onsemi 0:098463de4c5d 523 * @param Periphs This parameter can be a combination of the following values:
group-onsemi 0:098463de4c5d 524 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
group-onsemi 0:098463de4c5d 525 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
group-onsemi 0:098463de4c5d 526 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
group-onsemi 0:098463de4c5d 527 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
group-onsemi 0:098463de4c5d 528 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
group-onsemi 0:098463de4c5d 529 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
group-onsemi 0:098463de4c5d 530 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
group-onsemi 0:098463de4c5d 531 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
group-onsemi 0:098463de4c5d 532 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
group-onsemi 0:098463de4c5d 533 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
group-onsemi 0:098463de4c5d 534 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
group-onsemi 0:098463de4c5d 535 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
group-onsemi 0:098463de4c5d 536 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
group-onsemi 0:098463de4c5d 537 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
group-onsemi 0:098463de4c5d 538 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
group-onsemi 0:098463de4c5d 539 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
group-onsemi 0:098463de4c5d 540 * @arg @ref LL_APB1_GRP1_PERIPH_USB
group-onsemi 0:098463de4c5d 541 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
group-onsemi 0:098463de4c5d 542 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
group-onsemi 0:098463de4c5d 543 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
group-onsemi 0:098463de4c5d 544 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
group-onsemi 0:098463de4c5d 545 *
group-onsemi 0:098463de4c5d 546 * (*) value not defined in all devices.
group-onsemi 0:098463de4c5d 547 * @retval None
group-onsemi 0:098463de4c5d 548 */
group-onsemi 0:098463de4c5d 549 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
group-onsemi 0:098463de4c5d 550 {
group-onsemi 0:098463de4c5d 551 __IO uint32_t tmpreg;
group-onsemi 0:098463de4c5d 552 SET_BIT(RCC->APB1ENR, Periphs);
group-onsemi 0:098463de4c5d 553 /* Delay after an RCC peripheral clock enabling */
group-onsemi 0:098463de4c5d 554 tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
group-onsemi 0:098463de4c5d 555 (void)tmpreg;
group-onsemi 0:098463de4c5d 556 }
group-onsemi 0:098463de4c5d 557
group-onsemi 0:098463de4c5d 558 /**
group-onsemi 0:098463de4c5d 559 * @brief Check if APB1 peripheral clock is enabled or not
group-onsemi 0:098463de4c5d 560 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 561 * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 562 * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 563 * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 564 * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 565 * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 566 * APB1ENR LCDEN LL_APB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 567 * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 568 * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 569 * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 570 * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 571 * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 572 * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 573 * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 574 * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 575 * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 576 * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 577 * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 578 * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 579 * APB1ENR COMPEN LL_APB1_GRP1_IsEnabledClock
group-onsemi 0:098463de4c5d 580 * @param Periphs This parameter can be a combination of the following values:
group-onsemi 0:098463de4c5d 581 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
group-onsemi 0:098463de4c5d 582 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
group-onsemi 0:098463de4c5d 583 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
group-onsemi 0:098463de4c5d 584 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
group-onsemi 0:098463de4c5d 585 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
group-onsemi 0:098463de4c5d 586 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
group-onsemi 0:098463de4c5d 587 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
group-onsemi 0:098463de4c5d 588 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
group-onsemi 0:098463de4c5d 589 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
group-onsemi 0:098463de4c5d 590 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
group-onsemi 0:098463de4c5d 591 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
group-onsemi 0:098463de4c5d 592 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
group-onsemi 0:098463de4c5d 593 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
group-onsemi 0:098463de4c5d 594 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
group-onsemi 0:098463de4c5d 595 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
group-onsemi 0:098463de4c5d 596 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
group-onsemi 0:098463de4c5d 597 * @arg @ref LL_APB1_GRP1_PERIPH_USB
group-onsemi 0:098463de4c5d 598 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
group-onsemi 0:098463de4c5d 599 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
group-onsemi 0:098463de4c5d 600 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
group-onsemi 0:098463de4c5d 601 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
group-onsemi 0:098463de4c5d 602 *
group-onsemi 0:098463de4c5d 603 * (*) value not defined in all devices.
group-onsemi 0:098463de4c5d 604 * @retval State of Periphs (1 or 0).
group-onsemi 0:098463de4c5d 605 */
group-onsemi 0:098463de4c5d 606 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
group-onsemi 0:098463de4c5d 607 {
group-onsemi 0:098463de4c5d 608 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
group-onsemi 0:098463de4c5d 609 }
group-onsemi 0:098463de4c5d 610
group-onsemi 0:098463de4c5d 611 /**
group-onsemi 0:098463de4c5d 612 * @brief Disable APB1 peripherals clock.
group-onsemi 0:098463de4c5d 613 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 614 * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 615 * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 616 * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 617 * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 618 * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 619 * APB1ENR LCDEN LL_APB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 620 * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 621 * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 622 * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 623 * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 624 * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 625 * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 626 * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 627 * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 628 * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 629 * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 630 * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 631 * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 632 * APB1ENR COMPEN LL_APB1_GRP1_DisableClock
group-onsemi 0:098463de4c5d 633 * @param Periphs This parameter can be a combination of the following values:
group-onsemi 0:098463de4c5d 634 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
group-onsemi 0:098463de4c5d 635 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
group-onsemi 0:098463de4c5d 636 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
group-onsemi 0:098463de4c5d 637 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
group-onsemi 0:098463de4c5d 638 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
group-onsemi 0:098463de4c5d 639 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
group-onsemi 0:098463de4c5d 640 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
group-onsemi 0:098463de4c5d 641 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
group-onsemi 0:098463de4c5d 642 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
group-onsemi 0:098463de4c5d 643 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
group-onsemi 0:098463de4c5d 644 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
group-onsemi 0:098463de4c5d 645 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
group-onsemi 0:098463de4c5d 646 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
group-onsemi 0:098463de4c5d 647 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
group-onsemi 0:098463de4c5d 648 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
group-onsemi 0:098463de4c5d 649 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
group-onsemi 0:098463de4c5d 650 * @arg @ref LL_APB1_GRP1_PERIPH_USB
group-onsemi 0:098463de4c5d 651 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
group-onsemi 0:098463de4c5d 652 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
group-onsemi 0:098463de4c5d 653 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
group-onsemi 0:098463de4c5d 654 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
group-onsemi 0:098463de4c5d 655 *
group-onsemi 0:098463de4c5d 656 * (*) value not defined in all devices.
group-onsemi 0:098463de4c5d 657 * @retval None
group-onsemi 0:098463de4c5d 658 */
group-onsemi 0:098463de4c5d 659 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
group-onsemi 0:098463de4c5d 660 {
group-onsemi 0:098463de4c5d 661 CLEAR_BIT(RCC->APB1ENR, Periphs);
group-onsemi 0:098463de4c5d 662 }
group-onsemi 0:098463de4c5d 663
group-onsemi 0:098463de4c5d 664 /**
group-onsemi 0:098463de4c5d 665 * @brief Force APB1 peripherals reset.
group-onsemi 0:098463de4c5d 666 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 667 * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 668 * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 669 * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 670 * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 671 * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 672 * APB1RSTR LCDRST LL_APB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 673 * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 674 * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 675 * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 676 * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 677 * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 678 * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 679 * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 680 * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 681 * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 682 * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 683 * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 684 * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 685 * APB1RSTR COMPRST LL_APB1_GRP1_ForceReset
group-onsemi 0:098463de4c5d 686 * @param Periphs This parameter can be a combination of the following values:
group-onsemi 0:098463de4c5d 687 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
group-onsemi 0:098463de4c5d 688 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
group-onsemi 0:098463de4c5d 689 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
group-onsemi 0:098463de4c5d 690 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
group-onsemi 0:098463de4c5d 691 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
group-onsemi 0:098463de4c5d 692 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
group-onsemi 0:098463de4c5d 693 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
group-onsemi 0:098463de4c5d 694 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
group-onsemi 0:098463de4c5d 695 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
group-onsemi 0:098463de4c5d 696 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
group-onsemi 0:098463de4c5d 697 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
group-onsemi 0:098463de4c5d 698 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
group-onsemi 0:098463de4c5d 699 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
group-onsemi 0:098463de4c5d 700 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
group-onsemi 0:098463de4c5d 701 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
group-onsemi 0:098463de4c5d 702 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
group-onsemi 0:098463de4c5d 703 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
group-onsemi 0:098463de4c5d 704 * @arg @ref LL_APB1_GRP1_PERIPH_USB
group-onsemi 0:098463de4c5d 705 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
group-onsemi 0:098463de4c5d 706 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
group-onsemi 0:098463de4c5d 707 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
group-onsemi 0:098463de4c5d 708 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
group-onsemi 0:098463de4c5d 709 *
group-onsemi 0:098463de4c5d 710 * (*) value not defined in all devices.
group-onsemi 0:098463de4c5d 711 * @retval None
group-onsemi 0:098463de4c5d 712 */
group-onsemi 0:098463de4c5d 713 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
group-onsemi 0:098463de4c5d 714 {
group-onsemi 0:098463de4c5d 715 SET_BIT(RCC->APB1RSTR, Periphs);
group-onsemi 0:098463de4c5d 716 }
group-onsemi 0:098463de4c5d 717
group-onsemi 0:098463de4c5d 718 /**
group-onsemi 0:098463de4c5d 719 * @brief Release APB1 peripherals reset.
group-onsemi 0:098463de4c5d 720 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 721 * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 722 * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 723 * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 724 * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 725 * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 726 * APB1RSTR LCDRST LL_APB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 727 * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 728 * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 729 * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 730 * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 731 * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 732 * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 733 * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 734 * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 735 * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 736 * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 737 * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 738 * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 739 * APB1RSTR COMPRST LL_APB1_GRP1_ReleaseReset
group-onsemi 0:098463de4c5d 740 * @param Periphs This parameter can be a combination of the following values:
group-onsemi 0:098463de4c5d 741 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
group-onsemi 0:098463de4c5d 742 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
group-onsemi 0:098463de4c5d 743 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
group-onsemi 0:098463de4c5d 744 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
group-onsemi 0:098463de4c5d 745 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
group-onsemi 0:098463de4c5d 746 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
group-onsemi 0:098463de4c5d 747 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
group-onsemi 0:098463de4c5d 748 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
group-onsemi 0:098463de4c5d 749 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
group-onsemi 0:098463de4c5d 750 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
group-onsemi 0:098463de4c5d 751 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
group-onsemi 0:098463de4c5d 752 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
group-onsemi 0:098463de4c5d 753 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
group-onsemi 0:098463de4c5d 754 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
group-onsemi 0:098463de4c5d 755 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
group-onsemi 0:098463de4c5d 756 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
group-onsemi 0:098463de4c5d 757 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
group-onsemi 0:098463de4c5d 758 * @arg @ref LL_APB1_GRP1_PERIPH_USB
group-onsemi 0:098463de4c5d 759 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
group-onsemi 0:098463de4c5d 760 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
group-onsemi 0:098463de4c5d 761 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
group-onsemi 0:098463de4c5d 762 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
group-onsemi 0:098463de4c5d 763 *
group-onsemi 0:098463de4c5d 764 * (*) value not defined in all devices.
group-onsemi 0:098463de4c5d 765 * @retval None
group-onsemi 0:098463de4c5d 766 */
group-onsemi 0:098463de4c5d 767 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
group-onsemi 0:098463de4c5d 768 {
group-onsemi 0:098463de4c5d 769 CLEAR_BIT(RCC->APB1RSTR, Periphs);
group-onsemi 0:098463de4c5d 770 }
group-onsemi 0:098463de4c5d 771
group-onsemi 0:098463de4c5d 772 /**
group-onsemi 0:098463de4c5d 773 * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode.
group-onsemi 0:098463de4c5d 774 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 775 * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 776 * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 777 * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 778 * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 779 * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 780 * APB1LPENR LCDLPEN LL_APB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 781 * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 782 * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 783 * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 784 * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 785 * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 786 * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 787 * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 788 * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 789 * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 790 * APB1LPENR USBLPEN LL_APB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 791 * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 792 * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 793 * APB1LPENR COMPLPEN LL_APB1_GRP1_EnableClockSleep
group-onsemi 0:098463de4c5d 794 * @param Periphs This parameter can be a combination of the following values:
group-onsemi 0:098463de4c5d 795 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
group-onsemi 0:098463de4c5d 796 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
group-onsemi 0:098463de4c5d 797 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
group-onsemi 0:098463de4c5d 798 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
group-onsemi 0:098463de4c5d 799 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
group-onsemi 0:098463de4c5d 800 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
group-onsemi 0:098463de4c5d 801 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
group-onsemi 0:098463de4c5d 802 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
group-onsemi 0:098463de4c5d 803 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
group-onsemi 0:098463de4c5d 804 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
group-onsemi 0:098463de4c5d 805 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
group-onsemi 0:098463de4c5d 806 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
group-onsemi 0:098463de4c5d 807 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
group-onsemi 0:098463de4c5d 808 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
group-onsemi 0:098463de4c5d 809 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
group-onsemi 0:098463de4c5d 810 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
group-onsemi 0:098463de4c5d 811 * @arg @ref LL_APB1_GRP1_PERIPH_USB
group-onsemi 0:098463de4c5d 812 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
group-onsemi 0:098463de4c5d 813 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
group-onsemi 0:098463de4c5d 814 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
group-onsemi 0:098463de4c5d 815 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
group-onsemi 0:098463de4c5d 816 *
group-onsemi 0:098463de4c5d 817 * (*) value not defined in all devices.
group-onsemi 0:098463de4c5d 818 * @retval None
group-onsemi 0:098463de4c5d 819 */
group-onsemi 0:098463de4c5d 820 __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
group-onsemi 0:098463de4c5d 821 {
group-onsemi 0:098463de4c5d 822 __IO uint32_t tmpreg;
group-onsemi 0:098463de4c5d 823 SET_BIT(RCC->APB1LPENR, Periphs);
group-onsemi 0:098463de4c5d 824 /* Delay after an RCC peripheral clock enabling */
group-onsemi 0:098463de4c5d 825 tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);
group-onsemi 0:098463de4c5d 826 (void)tmpreg;
group-onsemi 0:098463de4c5d 827 }
group-onsemi 0:098463de4c5d 828
group-onsemi 0:098463de4c5d 829 /**
group-onsemi 0:098463de4c5d 830 * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode.
group-onsemi 0:098463de4c5d 831 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 832 * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 833 * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 834 * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 835 * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 836 * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 837 * APB1LPENR LCDLPEN LL_APB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 838 * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 839 * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 840 * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 841 * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 842 * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 843 * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 844 * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 845 * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 846 * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 847 * APB1LPENR USBLPEN LL_APB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 848 * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 849 * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 850 * APB1LPENR COMPLPEN LL_APB1_GRP1_DisableClockSleep
group-onsemi 0:098463de4c5d 851 * @param Periphs This parameter can be a combination of the following values:
group-onsemi 0:098463de4c5d 852 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
group-onsemi 0:098463de4c5d 853 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
group-onsemi 0:098463de4c5d 854 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
group-onsemi 0:098463de4c5d 855 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
group-onsemi 0:098463de4c5d 856 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
group-onsemi 0:098463de4c5d 857 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
group-onsemi 0:098463de4c5d 858 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
group-onsemi 0:098463de4c5d 859 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
group-onsemi 0:098463de4c5d 860 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
group-onsemi 0:098463de4c5d 861 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
group-onsemi 0:098463de4c5d 862 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
group-onsemi 0:098463de4c5d 863 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
group-onsemi 0:098463de4c5d 864 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
group-onsemi 0:098463de4c5d 865 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
group-onsemi 0:098463de4c5d 866 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
group-onsemi 0:098463de4c5d 867 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
group-onsemi 0:098463de4c5d 868 * @arg @ref LL_APB1_GRP1_PERIPH_USB
group-onsemi 0:098463de4c5d 869 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
group-onsemi 0:098463de4c5d 870 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
group-onsemi 0:098463de4c5d 871 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
group-onsemi 0:098463de4c5d 872 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
group-onsemi 0:098463de4c5d 873 *
group-onsemi 0:098463de4c5d 874 * (*) value not defined in all devices.
group-onsemi 0:098463de4c5d 875 * @retval None
group-onsemi 0:098463de4c5d 876 */
group-onsemi 0:098463de4c5d 877 __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
group-onsemi 0:098463de4c5d 878 {
group-onsemi 0:098463de4c5d 879 CLEAR_BIT(RCC->APB1LPENR, Periphs);
group-onsemi 0:098463de4c5d 880 }
group-onsemi 0:098463de4c5d 881
group-onsemi 0:098463de4c5d 882 /**
group-onsemi 0:098463de4c5d 883 * @}
group-onsemi 0:098463de4c5d 884 */
group-onsemi 0:098463de4c5d 885
group-onsemi 0:098463de4c5d 886 /** @defgroup BUS_LL_EF_APB2 APB2
group-onsemi 0:098463de4c5d 887 * @{
group-onsemi 0:098463de4c5d 888 */
group-onsemi 0:098463de4c5d 889
group-onsemi 0:098463de4c5d 890 /**
group-onsemi 0:098463de4c5d 891 * @brief Enable APB2 peripherals clock.
group-onsemi 0:098463de4c5d 892 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 893 * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 894 * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 895 * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 896 * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 897 * APB2ENR SDIOEN LL_APB2_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 898 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
group-onsemi 0:098463de4c5d 899 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock
group-onsemi 0:098463de4c5d 900 * @param Periphs This parameter can be a combination of the following values:
group-onsemi 0:098463de4c5d 901 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
group-onsemi 0:098463de4c5d 902 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
group-onsemi 0:098463de4c5d 903 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
group-onsemi 0:098463de4c5d 904 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
group-onsemi 0:098463de4c5d 905 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
group-onsemi 0:098463de4c5d 906 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
group-onsemi 0:098463de4c5d 907 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
group-onsemi 0:098463de4c5d 908 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
group-onsemi 0:098463de4c5d 909 *
group-onsemi 0:098463de4c5d 910 * (*) value not defined in all devices.
group-onsemi 0:098463de4c5d 911 * @retval None
group-onsemi 0:098463de4c5d 912 */
group-onsemi 0:098463de4c5d 913 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
group-onsemi 0:098463de4c5d 914 {
group-onsemi 0:098463de4c5d 915 __IO uint32_t tmpreg;
group-onsemi 0:098463de4c5d 916 SET_BIT(RCC->APB2ENR, Periphs);
group-onsemi 0:098463de4c5d 917 /* Delay after an RCC peripheral clock enabling */
group-onsemi 0:098463de4c5d 918 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
group-onsemi 0:098463de4c5d 919 (void)tmpreg;
group-onsemi 0:098463de4c5d 920 }
group-onsemi 0:098463de4c5d 921
group-onsemi 0:098463de4c5d 922 /**
group-onsemi 0:098463de4c5d 923 * @brief Check if APB2 peripheral clock is enabled or not
group-onsemi 0:098463de4c5d 924 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 925 * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 926 * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 927 * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 928 * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 929 * APB2ENR SDIOEN LL_APB2_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 930 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
group-onsemi 0:098463de4c5d 931 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock
group-onsemi 0:098463de4c5d 932 * @param Periphs This parameter can be a combination of the following values:
group-onsemi 0:098463de4c5d 933 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
group-onsemi 0:098463de4c5d 934 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
group-onsemi 0:098463de4c5d 935 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
group-onsemi 0:098463de4c5d 936 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
group-onsemi 0:098463de4c5d 937 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
group-onsemi 0:098463de4c5d 938 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
group-onsemi 0:098463de4c5d 939 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
group-onsemi 0:098463de4c5d 940 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
group-onsemi 0:098463de4c5d 941 *
group-onsemi 0:098463de4c5d 942 * (*) value not defined in all devices.
group-onsemi 0:098463de4c5d 943 * @retval State of Periphs (1 or 0).
group-onsemi 0:098463de4c5d 944 */
group-onsemi 0:098463de4c5d 945 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
group-onsemi 0:098463de4c5d 946 {
group-onsemi 0:098463de4c5d 947 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
group-onsemi 0:098463de4c5d 948 }
group-onsemi 0:098463de4c5d 949
group-onsemi 0:098463de4c5d 950 /**
group-onsemi 0:098463de4c5d 951 * @brief Disable APB2 peripherals clock.
group-onsemi 0:098463de4c5d 952 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 953 * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 954 * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 955 * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 956 * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 957 * APB2ENR SDIOEN LL_APB2_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 958 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
group-onsemi 0:098463de4c5d 959 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock
group-onsemi 0:098463de4c5d 960 * @param Periphs This parameter can be a combination of the following values:
group-onsemi 0:098463de4c5d 961 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
group-onsemi 0:098463de4c5d 962 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
group-onsemi 0:098463de4c5d 963 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
group-onsemi 0:098463de4c5d 964 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
group-onsemi 0:098463de4c5d 965 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
group-onsemi 0:098463de4c5d 966 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
group-onsemi 0:098463de4c5d 967 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
group-onsemi 0:098463de4c5d 968 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
group-onsemi 0:098463de4c5d 969 *
group-onsemi 0:098463de4c5d 970 * (*) value not defined in all devices.
group-onsemi 0:098463de4c5d 971 * @retval None
group-onsemi 0:098463de4c5d 972 */
group-onsemi 0:098463de4c5d 973 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
group-onsemi 0:098463de4c5d 974 {
group-onsemi 0:098463de4c5d 975 CLEAR_BIT(RCC->APB2ENR, Periphs);
group-onsemi 0:098463de4c5d 976 }
group-onsemi 0:098463de4c5d 977
group-onsemi 0:098463de4c5d 978 /**
group-onsemi 0:098463de4c5d 979 * @brief Force APB2 peripherals reset.
group-onsemi 0:098463de4c5d 980 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 981 * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 982 * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 983 * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 984 * APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 985 * APB2RSTR SDIORST LL_APB2_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 986 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
group-onsemi 0:098463de4c5d 987 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset
group-onsemi 0:098463de4c5d 988 * @param Periphs This parameter can be a combination of the following values:
group-onsemi 0:098463de4c5d 989 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
group-onsemi 0:098463de4c5d 990 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
group-onsemi 0:098463de4c5d 991 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
group-onsemi 0:098463de4c5d 992 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
group-onsemi 0:098463de4c5d 993 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
group-onsemi 0:098463de4c5d 994 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
group-onsemi 0:098463de4c5d 995 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
group-onsemi 0:098463de4c5d 996 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
group-onsemi 0:098463de4c5d 997 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
group-onsemi 0:098463de4c5d 998 *
group-onsemi 0:098463de4c5d 999 * (*) value not defined in all devices.
group-onsemi 0:098463de4c5d 1000 * @retval None
group-onsemi 0:098463de4c5d 1001 */
group-onsemi 0:098463de4c5d 1002 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
group-onsemi 0:098463de4c5d 1003 {
group-onsemi 0:098463de4c5d 1004 SET_BIT(RCC->APB2RSTR, Periphs);
group-onsemi 0:098463de4c5d 1005 }
group-onsemi 0:098463de4c5d 1006
group-onsemi 0:098463de4c5d 1007 /**
group-onsemi 0:098463de4c5d 1008 * @brief Release APB2 peripherals reset.
group-onsemi 0:098463de4c5d 1009 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 1010 * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 1011 * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 1012 * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 1013 * APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 1014 * APB2RSTR SDIORST LL_APB2_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 1015 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
group-onsemi 0:098463de4c5d 1016 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset
group-onsemi 0:098463de4c5d 1017 * @param Periphs This parameter can be a combination of the following values:
group-onsemi 0:098463de4c5d 1018 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
group-onsemi 0:098463de4c5d 1019 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
group-onsemi 0:098463de4c5d 1020 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
group-onsemi 0:098463de4c5d 1021 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
group-onsemi 0:098463de4c5d 1022 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
group-onsemi 0:098463de4c5d 1023 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
group-onsemi 0:098463de4c5d 1024 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
group-onsemi 0:098463de4c5d 1025 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
group-onsemi 0:098463de4c5d 1026 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
group-onsemi 0:098463de4c5d 1027 *
group-onsemi 0:098463de4c5d 1028 * (*) value not defined in all devices.
group-onsemi 0:098463de4c5d 1029 * @retval None
group-onsemi 0:098463de4c5d 1030 */
group-onsemi 0:098463de4c5d 1031 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
group-onsemi 0:098463de4c5d 1032 {
group-onsemi 0:098463de4c5d 1033 CLEAR_BIT(RCC->APB2RSTR, Periphs);
group-onsemi 0:098463de4c5d 1034 }
group-onsemi 0:098463de4c5d 1035
group-onsemi 0:098463de4c5d 1036 /**
group-onsemi 0:098463de4c5d 1037 * @brief Enable APB2 peripherals clock during Low Power (Sleep) mode.
group-onsemi 0:098463de4c5d 1038 * @rmtoll APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 1039 * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 1040 * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 1041 * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 1042 * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 1043 * APB2LPENR SDIOLPEN LL_APB2_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 1044 * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockSleep\n
group-onsemi 0:098463de4c5d 1045 * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockSleep
group-onsemi 0:098463de4c5d 1046 * @param Periphs This parameter can be a combination of the following values:
group-onsemi 0:098463de4c5d 1047 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
group-onsemi 0:098463de4c5d 1048 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
group-onsemi 0:098463de4c5d 1049 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
group-onsemi 0:098463de4c5d 1050 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
group-onsemi 0:098463de4c5d 1051 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
group-onsemi 0:098463de4c5d 1052 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
group-onsemi 0:098463de4c5d 1053 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
group-onsemi 0:098463de4c5d 1054 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
group-onsemi 0:098463de4c5d 1055 *
group-onsemi 0:098463de4c5d 1056 * (*) value not defined in all devices.
group-onsemi 0:098463de4c5d 1057 * @retval None
group-onsemi 0:098463de4c5d 1058 */
group-onsemi 0:098463de4c5d 1059 __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
group-onsemi 0:098463de4c5d 1060 {
group-onsemi 0:098463de4c5d 1061 __IO uint32_t tmpreg;
group-onsemi 0:098463de4c5d 1062 SET_BIT(RCC->APB2LPENR, Periphs);
group-onsemi 0:098463de4c5d 1063 /* Delay after an RCC peripheral clock enabling */
group-onsemi 0:098463de4c5d 1064 tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
group-onsemi 0:098463de4c5d 1065 (void)tmpreg;
group-onsemi 0:098463de4c5d 1066 }
group-onsemi 0:098463de4c5d 1067
group-onsemi 0:098463de4c5d 1068 /**
group-onsemi 0:098463de4c5d 1069 * @brief Disable APB2 peripherals clock during Low Power (Sleep) mode.
group-onsemi 0:098463de4c5d 1070 * @rmtoll APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 1071 * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 1072 * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 1073 * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 1074 * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 1075 * APB2LPENR SDIOLPEN LL_APB2_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 1076 * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockSleep\n
group-onsemi 0:098463de4c5d 1077 * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockSleep
group-onsemi 0:098463de4c5d 1078 * @param Periphs This parameter can be a combination of the following values:
group-onsemi 0:098463de4c5d 1079 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
group-onsemi 0:098463de4c5d 1080 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
group-onsemi 0:098463de4c5d 1081 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
group-onsemi 0:098463de4c5d 1082 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
group-onsemi 0:098463de4c5d 1083 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
group-onsemi 0:098463de4c5d 1084 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
group-onsemi 0:098463de4c5d 1085 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
group-onsemi 0:098463de4c5d 1086 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
group-onsemi 0:098463de4c5d 1087 *
group-onsemi 0:098463de4c5d 1088 * (*) value not defined in all devices.
group-onsemi 0:098463de4c5d 1089 * @retval None
group-onsemi 0:098463de4c5d 1090 */
group-onsemi 0:098463de4c5d 1091 __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
group-onsemi 0:098463de4c5d 1092 {
group-onsemi 0:098463de4c5d 1093 CLEAR_BIT(RCC->APB2LPENR, Periphs);
group-onsemi 0:098463de4c5d 1094 }
group-onsemi 0:098463de4c5d 1095
group-onsemi 0:098463de4c5d 1096 /**
group-onsemi 0:098463de4c5d 1097 * @}
group-onsemi 0:098463de4c5d 1098 */
group-onsemi 0:098463de4c5d 1099
group-onsemi 0:098463de4c5d 1100
group-onsemi 0:098463de4c5d 1101 /**
group-onsemi 0:098463de4c5d 1102 * @}
group-onsemi 0:098463de4c5d 1103 */
group-onsemi 0:098463de4c5d 1104
group-onsemi 0:098463de4c5d 1105 /**
group-onsemi 0:098463de4c5d 1106 * @}
group-onsemi 0:098463de4c5d 1107 */
group-onsemi 0:098463de4c5d 1108
group-onsemi 0:098463de4c5d 1109 #endif /* defined(RCC) */
group-onsemi 0:098463de4c5d 1110
group-onsemi 0:098463de4c5d 1111 /**
group-onsemi 0:098463de4c5d 1112 * @}
group-onsemi 0:098463de4c5d 1113 */
group-onsemi 0:098463de4c5d 1114
group-onsemi 0:098463de4c5d 1115 #ifdef __cplusplus
group-onsemi 0:098463de4c5d 1116 }
group-onsemi 0:098463de4c5d 1117 #endif
group-onsemi 0:098463de4c5d 1118
group-onsemi 0:098463de4c5d 1119 #endif /* __STM32L1xx_LL_BUS_H */
group-onsemi 0:098463de4c5d 1120
group-onsemi 0:098463de4c5d 1121 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/