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Dependents:   mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_STM/TARGET_STM32F7/gpio_irq_api.c@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:
jacobjohnson
Date:
Mon Feb 27 17:45:05 2017 +0000
Revision:
1:f30bdcd2b33b
Parent:
0:098463de4c5d 
changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-onsemi 0:098463de4c5d 1 /* mbed Microcontroller Library
group-onsemi 0:098463de4c5d 2 *******************************************************************************
group-onsemi 0:098463de4c5d 3 * Copyright (c) 2016, STMicroelectronics
group-onsemi 0:098463de4c5d 4 * All rights reserved.
group-onsemi 0:098463de4c5d 5 *
group-onsemi 0:098463de4c5d 6 * Redistribution and use in source and binary forms, with or without
group-onsemi 0:098463de4c5d 7 * modification, are permitted provided that the following conditions are met:
group-onsemi 0:098463de4c5d 8 *
group-onsemi 0:098463de4c5d 9 * 1. Redistributions of source code must retain the above copyright notice,
group-onsemi 0:098463de4c5d 10 * this list of conditions and the following disclaimer.
group-onsemi 0:098463de4c5d 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
group-onsemi 0:098463de4c5d 12 * this list of conditions and the following disclaimer in the documentation
group-onsemi 0:098463de4c5d 13 * and/or other materials provided with the distribution.
group-onsemi 0:098463de4c5d 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
group-onsemi 0:098463de4c5d 15 * may be used to endorse or promote products derived from this software
group-onsemi 0:098463de4c5d 16 * without specific prior written permission.
group-onsemi 0:098463de4c5d 17 *
group-onsemi 0:098463de4c5d 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
group-onsemi 0:098463de4c5d 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
group-onsemi 0:098463de4c5d 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
group-onsemi 0:098463de4c5d 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
group-onsemi 0:098463de4c5d 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
group-onsemi 0:098463de4c5d 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
group-onsemi 0:098463de4c5d 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
group-onsemi 0:098463de4c5d 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
group-onsemi 0:098463de4c5d 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
group-onsemi 0:098463de4c5d 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
group-onsemi 0:098463de4c5d 28 *******************************************************************************
group-onsemi 0:098463de4c5d 29 */
group-onsemi 0:098463de4c5d 30 #include <stddef.h>
group-onsemi 0:098463de4c5d 31 #include "cmsis.h"
group-onsemi 0:098463de4c5d 32 #include "gpio_irq_api.h"
group-onsemi 0:098463de4c5d 33 #include "pinmap.h"
group-onsemi 0:098463de4c5d 34 #include "mbed_error.h"
group-onsemi 0:098463de4c5d 35
group-onsemi 0:098463de4c5d 36 #define EDGE_NONE (0)
group-onsemi 0:098463de4c5d 37 #define EDGE_RISE (1)
group-onsemi 0:098463de4c5d 38 #define EDGE_FALL (2)
group-onsemi 0:098463de4c5d 39 #define EDGE_BOTH (3)
group-onsemi 0:098463de4c5d 40
group-onsemi 0:098463de4c5d 41 // Number of EXTI irq vectors (EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5_9, EXTI10_15)
group-onsemi 0:098463de4c5d 42 #define CHANNEL_NUM (7)
group-onsemi 0:098463de4c5d 43
group-onsemi 0:098463de4c5d 44 // Max pins for one line (max with EXTI10_15)
group-onsemi 0:098463de4c5d 45 #define MAX_PIN_LINE (6)
group-onsemi 0:098463de4c5d 46
group-onsemi 0:098463de4c5d 47 typedef struct gpio_channel {
group-onsemi 0:098463de4c5d 48 uint32_t pin_mask; // bitmask representing which pins are configured for receiving interrupts
group-onsemi 0:098463de4c5d 49 uint32_t channel_ids[MAX_PIN_LINE]; // mbed "gpio_irq_t gpio_irq" field of instance
group-onsemi 0:098463de4c5d 50 uint32_t channel_gpio[MAX_PIN_LINE]; // base address of gpio port group
group-onsemi 0:098463de4c5d 51 uint32_t channel_pin[MAX_PIN_LINE]; // pin number in port group
group-onsemi 0:098463de4c5d 52 } gpio_channel_t;
group-onsemi 0:098463de4c5d 53
group-onsemi 0:098463de4c5d 54 static gpio_channel_t channels[CHANNEL_NUM] = {
group-onsemi 0:098463de4c5d 55 {.pin_mask = 0},
group-onsemi 0:098463de4c5d 56 {.pin_mask = 0},
group-onsemi 0:098463de4c5d 57 {.pin_mask = 0},
group-onsemi 0:098463de4c5d 58 {.pin_mask = 0},
group-onsemi 0:098463de4c5d 59 {.pin_mask = 0},
group-onsemi 0:098463de4c5d 60 {.pin_mask = 0},
group-onsemi 0:098463de4c5d 61 {.pin_mask = 0}
group-onsemi 0:098463de4c5d 62 };
group-onsemi 0:098463de4c5d 63
group-onsemi 0:098463de4c5d 64 // Used to return the index for channels array.
group-onsemi 0:098463de4c5d 65 static uint32_t pin_base_nr[16] = {
group-onsemi 0:098463de4c5d 66 // EXTI0
group-onsemi 0:098463de4c5d 67 0, // pin 0
group-onsemi 0:098463de4c5d 68 // EXTI1
group-onsemi 0:098463de4c5d 69 0, // pin 1
group-onsemi 0:098463de4c5d 70 // EXTI2
group-onsemi 0:098463de4c5d 71 0, // pin 2
group-onsemi 0:098463de4c5d 72 // EXTI3
group-onsemi 0:098463de4c5d 73 0, // pin 3
group-onsemi 0:098463de4c5d 74 // EXTI4
group-onsemi 0:098463de4c5d 75 0, // pin 4
group-onsemi 0:098463de4c5d 76 // EXTI5_9
group-onsemi 0:098463de4c5d 77 0, // pin 5
group-onsemi 0:098463de4c5d 78 1, // pin 6
group-onsemi 0:098463de4c5d 79 2, // pin 7
group-onsemi 0:098463de4c5d 80 3, // pin 8
group-onsemi 0:098463de4c5d 81 4, // pin 9
group-onsemi 0:098463de4c5d 82 // EXTI10_15
group-onsemi 0:098463de4c5d 83 0, // pin 10
group-onsemi 0:098463de4c5d 84 1, // pin 11
group-onsemi 0:098463de4c5d 85 2, // pin 12
group-onsemi 0:098463de4c5d 86 3, // pin 13
group-onsemi 0:098463de4c5d 87 4, // pin 14
group-onsemi 0:098463de4c5d 88 5 // pin 15
group-onsemi 0:098463de4c5d 89 };
group-onsemi 0:098463de4c5d 90
group-onsemi 0:098463de4c5d 91 static gpio_irq_handler irq_handler;
group-onsemi 0:098463de4c5d 92
group-onsemi 0:098463de4c5d 93 static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line)
group-onsemi 0:098463de4c5d 94 {
group-onsemi 0:098463de4c5d 95 gpio_channel_t *gpio_channel = &channels[irq_index];
group-onsemi 0:098463de4c5d 96 uint32_t gpio_idx;
group-onsemi 0:098463de4c5d 97
group-onsemi 0:098463de4c5d 98 for (gpio_idx = 0; gpio_idx < max_num_pin_line; gpio_idx++) {
group-onsemi 0:098463de4c5d 99 uint32_t current_mask = (1 << gpio_idx);
group-onsemi 0:098463de4c5d 100
group-onsemi 0:098463de4c5d 101 if (gpio_channel->pin_mask & current_mask) {
group-onsemi 0:098463de4c5d 102 // Retrieve the gpio and pin that generate the irq
group-onsemi 0:098463de4c5d 103 GPIO_TypeDef *gpio = (GPIO_TypeDef *)(gpio_channel->channel_gpio[gpio_idx]);
group-onsemi 0:098463de4c5d 104 uint32_t pin = (uint32_t)(1 << (gpio_channel->channel_pin[gpio_idx]));
group-onsemi 0:098463de4c5d 105
group-onsemi 0:098463de4c5d 106 // Clear interrupt flag
group-onsemi 0:098463de4c5d 107 if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET) {
group-onsemi 0:098463de4c5d 108 __HAL_GPIO_EXTI_CLEAR_FLAG(pin);
group-onsemi 0:098463de4c5d 109
group-onsemi 0:098463de4c5d 110 if (gpio_channel->channel_ids[gpio_idx] == 0) continue;
group-onsemi 0:098463de4c5d 111
group-onsemi 0:098463de4c5d 112 // Check which edge has generated the irq
group-onsemi 0:098463de4c5d 113 if ((gpio->IDR & pin) == 0) {
group-onsemi 0:098463de4c5d 114 irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_FALL);
group-onsemi 0:098463de4c5d 115 } else {
group-onsemi 0:098463de4c5d 116 irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_RISE);
group-onsemi 0:098463de4c5d 117 }
group-onsemi 0:098463de4c5d 118 }
group-onsemi 0:098463de4c5d 119 }
group-onsemi 0:098463de4c5d 120 }
group-onsemi 0:098463de4c5d 121 }
group-onsemi 0:098463de4c5d 122
group-onsemi 0:098463de4c5d 123 // EXTI line 0
group-onsemi 0:098463de4c5d 124 static void gpio_irq0(void)
group-onsemi 0:098463de4c5d 125 {
group-onsemi 0:098463de4c5d 126 handle_interrupt_in(0, 1);
group-onsemi 0:098463de4c5d 127 }
group-onsemi 0:098463de4c5d 128
group-onsemi 0:098463de4c5d 129 // EXTI line 1
group-onsemi 0:098463de4c5d 130 static void gpio_irq1(void)
group-onsemi 0:098463de4c5d 131 {
group-onsemi 0:098463de4c5d 132 handle_interrupt_in(1, 1);
group-onsemi 0:098463de4c5d 133 }
group-onsemi 0:098463de4c5d 134
group-onsemi 0:098463de4c5d 135 // EXTI line 2
group-onsemi 0:098463de4c5d 136 static void gpio_irq2(void)
group-onsemi 0:098463de4c5d 137 {
group-onsemi 0:098463de4c5d 138 handle_interrupt_in(2, 1);
group-onsemi 0:098463de4c5d 139 }
group-onsemi 0:098463de4c5d 140
group-onsemi 0:098463de4c5d 141 // EXTI line 3
group-onsemi 0:098463de4c5d 142 static void gpio_irq3(void)
group-onsemi 0:098463de4c5d 143 {
group-onsemi 0:098463de4c5d 144 handle_interrupt_in(3, 1);
group-onsemi 0:098463de4c5d 145 }
group-onsemi 0:098463de4c5d 146
group-onsemi 0:098463de4c5d 147 // EXTI line 4
group-onsemi 0:098463de4c5d 148 static void gpio_irq4(void)
group-onsemi 0:098463de4c5d 149 {
group-onsemi 0:098463de4c5d 150 handle_interrupt_in(4, 1);
group-onsemi 0:098463de4c5d 151 }
group-onsemi 0:098463de4c5d 152
group-onsemi 0:098463de4c5d 153 // EXTI lines 5 to 9
group-onsemi 0:098463de4c5d 154 static void gpio_irq5(void)
group-onsemi 0:098463de4c5d 155 {
group-onsemi 0:098463de4c5d 156 handle_interrupt_in(5, 5);
group-onsemi 0:098463de4c5d 157 }
group-onsemi 0:098463de4c5d 158
group-onsemi 0:098463de4c5d 159 // EXTI lines 10 to 15
group-onsemi 0:098463de4c5d 160 static void gpio_irq6(void)
group-onsemi 0:098463de4c5d 161 {
group-onsemi 0:098463de4c5d 162 handle_interrupt_in(6, 6);
group-onsemi 0:098463de4c5d 163 }
group-onsemi 0:098463de4c5d 164
group-onsemi 0:098463de4c5d 165 extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
group-onsemi 0:098463de4c5d 166 extern void pin_function_gpiomode(PinName pin, uint32_t gpiomode);
group-onsemi 0:098463de4c5d 167
group-onsemi 0:098463de4c5d 168 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
group-onsemi 0:098463de4c5d 169 {
group-onsemi 0:098463de4c5d 170 IRQn_Type irq_n = (IRQn_Type)0;
group-onsemi 0:098463de4c5d 171 uint32_t vector = 0;
group-onsemi 0:098463de4c5d 172 uint32_t irq_index;
group-onsemi 0:098463de4c5d 173 gpio_channel_t *gpio_channel;
group-onsemi 0:098463de4c5d 174 uint32_t gpio_idx;
group-onsemi 0:098463de4c5d 175
group-onsemi 0:098463de4c5d 176 if (pin == NC) return -1;
group-onsemi 0:098463de4c5d 177
group-onsemi 0:098463de4c5d 178 uint32_t port_index = STM_PORT(pin);
group-onsemi 0:098463de4c5d 179 uint32_t pin_index = STM_PIN(pin);
group-onsemi 0:098463de4c5d 180
group-onsemi 0:098463de4c5d 181 // Select irq number and interrupt routine
group-onsemi 0:098463de4c5d 182 switch (pin_index) {
group-onsemi 0:098463de4c5d 183 case 0:
group-onsemi 0:098463de4c5d 184 irq_n = EXTI0_IRQn;
group-onsemi 0:098463de4c5d 185 vector = (uint32_t)&gpio_irq0;
group-onsemi 0:098463de4c5d 186 irq_index = 0;
group-onsemi 0:098463de4c5d 187 break;
group-onsemi 0:098463de4c5d 188 case 1:
group-onsemi 0:098463de4c5d 189 irq_n = EXTI1_IRQn;
group-onsemi 0:098463de4c5d 190 vector = (uint32_t)&gpio_irq1;
group-onsemi 0:098463de4c5d 191 irq_index = 1;
group-onsemi 0:098463de4c5d 192 break;
group-onsemi 0:098463de4c5d 193 case 2:
group-onsemi 0:098463de4c5d 194 irq_n = EXTI2_IRQn;
group-onsemi 0:098463de4c5d 195 vector = (uint32_t)&gpio_irq2;
group-onsemi 0:098463de4c5d 196 irq_index = 2;
group-onsemi 0:098463de4c5d 197 break;
group-onsemi 0:098463de4c5d 198 case 3:
group-onsemi 0:098463de4c5d 199 irq_n = EXTI3_IRQn;
group-onsemi 0:098463de4c5d 200 vector = (uint32_t)&gpio_irq3;
group-onsemi 0:098463de4c5d 201 irq_index = 3;
group-onsemi 0:098463de4c5d 202 break;
group-onsemi 0:098463de4c5d 203 case 4:
group-onsemi 0:098463de4c5d 204 irq_n = EXTI4_IRQn;
group-onsemi 0:098463de4c5d 205 vector = (uint32_t)&gpio_irq4;
group-onsemi 0:098463de4c5d 206 irq_index = 4;
group-onsemi 0:098463de4c5d 207 break;
group-onsemi 0:098463de4c5d 208 case 5:
group-onsemi 0:098463de4c5d 209 case 6:
group-onsemi 0:098463de4c5d 210 case 7:
group-onsemi 0:098463de4c5d 211 case 8:
group-onsemi 0:098463de4c5d 212 case 9:
group-onsemi 0:098463de4c5d 213 irq_n = EXTI9_5_IRQn;
group-onsemi 0:098463de4c5d 214 vector = (uint32_t)&gpio_irq5;
group-onsemi 0:098463de4c5d 215 irq_index = 5;
group-onsemi 0:098463de4c5d 216 break;
group-onsemi 0:098463de4c5d 217 case 10:
group-onsemi 0:098463de4c5d 218 case 11:
group-onsemi 0:098463de4c5d 219 case 12:
group-onsemi 0:098463de4c5d 220 case 13:
group-onsemi 0:098463de4c5d 221 case 14:
group-onsemi 0:098463de4c5d 222 case 15:
group-onsemi 0:098463de4c5d 223 irq_n = EXTI15_10_IRQn;
group-onsemi 0:098463de4c5d 224 vector = (uint32_t)&gpio_irq6;
group-onsemi 0:098463de4c5d 225 irq_index = 6;
group-onsemi 0:098463de4c5d 226 break;
group-onsemi 0:098463de4c5d 227 default:
group-onsemi 0:098463de4c5d 228 error("InterruptIn error: pin not supported.\n");
group-onsemi 0:098463de4c5d 229 return -1;
group-onsemi 0:098463de4c5d 230 }
group-onsemi 0:098463de4c5d 231
group-onsemi 0:098463de4c5d 232 // Enable GPIO clock
group-onsemi 0:098463de4c5d 233 uint32_t gpio_add = Set_GPIO_Clock(port_index);
group-onsemi 0:098463de4c5d 234
group-onsemi 0:098463de4c5d 235 // Configure GPIO
group-onsemi 0:098463de4c5d 236 pin_function(pin, STM_PIN_DATA(STM_MODE_IT_FALLING, GPIO_NOPULL, 0));
group-onsemi 0:098463de4c5d 237
group-onsemi 0:098463de4c5d 238 // Enable EXTI interrupt
group-onsemi 0:098463de4c5d 239 NVIC_SetVector(irq_n, vector);
group-onsemi 0:098463de4c5d 240 NVIC_EnableIRQ(irq_n);
group-onsemi 0:098463de4c5d 241
group-onsemi 0:098463de4c5d 242 // Save informations for future use
group-onsemi 0:098463de4c5d 243 obj->irq_n = irq_n;
group-onsemi 0:098463de4c5d 244 obj->irq_index = irq_index;
group-onsemi 0:098463de4c5d 245 obj->event = EDGE_NONE;
group-onsemi 0:098463de4c5d 246 obj->pin = pin;
group-onsemi 0:098463de4c5d 247
group-onsemi 0:098463de4c5d 248 gpio_channel = &channels[irq_index];
group-onsemi 0:098463de4c5d 249 gpio_idx = pin_base_nr[pin_index];
group-onsemi 0:098463de4c5d 250 gpio_channel->pin_mask |= (1 << gpio_idx);
group-onsemi 0:098463de4c5d 251 gpio_channel->channel_ids[gpio_idx] = id;
group-onsemi 0:098463de4c5d 252 gpio_channel->channel_gpio[gpio_idx] = gpio_add;
group-onsemi 0:098463de4c5d 253 gpio_channel->channel_pin[gpio_idx] = pin_index;
group-onsemi 0:098463de4c5d 254
group-onsemi 0:098463de4c5d 255 irq_handler = handler;
group-onsemi 0:098463de4c5d 256
group-onsemi 0:098463de4c5d 257 return 0;
group-onsemi 0:098463de4c5d 258 }
group-onsemi 0:098463de4c5d 259
group-onsemi 0:098463de4c5d 260 void gpio_irq_free(gpio_irq_t *obj)
group-onsemi 0:098463de4c5d 261 {
group-onsemi 0:098463de4c5d 262 gpio_channel_t *gpio_channel = &channels[obj->irq_index];
group-onsemi 0:098463de4c5d 263 uint32_t pin_index = STM_PIN(obj->pin);
group-onsemi 0:098463de4c5d 264 uint32_t gpio_addr = GPIOA_BASE + (GPIOB_BASE-GPIOA_BASE) * STM_PORT(obj->pin);
group-onsemi 0:098463de4c5d 265 uint32_t gpio_idx = pin_base_nr[pin_index];
group-onsemi 0:098463de4c5d 266
group-onsemi 0:098463de4c5d 267 HAL_GPIO_DeInit((GPIO_TypeDef *)gpio_addr, (1<<pin_index));
group-onsemi 0:098463de4c5d 268 gpio_channel->pin_mask &= ~(1 << gpio_idx);
group-onsemi 0:098463de4c5d 269 gpio_channel->channel_ids[gpio_idx] = 0;
group-onsemi 0:098463de4c5d 270 gpio_channel->channel_gpio[gpio_idx] = 0;
group-onsemi 0:098463de4c5d 271 gpio_channel->channel_pin[gpio_idx] = 0;
group-onsemi 0:098463de4c5d 272
group-onsemi 0:098463de4c5d 273 // Disable EXTI line, but don't change pull-up config
group-onsemi 0:098463de4c5d 274 pin_function_gpiomode(obj->pin, STM_MODE_INPUT);
group-onsemi 0:098463de4c5d 275 obj->event = EDGE_NONE;
group-onsemi 0:098463de4c5d 276 }
group-onsemi 0:098463de4c5d 277
group-onsemi 0:098463de4c5d 278 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
group-onsemi 0:098463de4c5d 279 {
group-onsemi 0:098463de4c5d 280 uint32_t mode = STM_MODE_IT_EVT_RESET;
group-onsemi 0:098463de4c5d 281
group-onsemi 0:098463de4c5d 282 if (enable) {
group-onsemi 0:098463de4c5d 283 if (event == IRQ_RISE) {
group-onsemi 0:098463de4c5d 284 if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) {
group-onsemi 0:098463de4c5d 285 mode = STM_MODE_IT_RISING_FALLING;
group-onsemi 0:098463de4c5d 286 obj->event = EDGE_BOTH;
group-onsemi 0:098463de4c5d 287 } else { // NONE or RISE
group-onsemi 0:098463de4c5d 288 mode = STM_MODE_IT_RISING;
group-onsemi 0:098463de4c5d 289 obj->event = EDGE_RISE;
group-onsemi 0:098463de4c5d 290 }
group-onsemi 0:098463de4c5d 291 }
group-onsemi 0:098463de4c5d 292 if (event == IRQ_FALL) {
group-onsemi 0:098463de4c5d 293 if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) {
group-onsemi 0:098463de4c5d 294 mode = STM_MODE_IT_RISING_FALLING;
group-onsemi 0:098463de4c5d 295 obj->event = EDGE_BOTH;
group-onsemi 0:098463de4c5d 296 } else { // NONE or FALL
group-onsemi 0:098463de4c5d 297 mode = STM_MODE_IT_FALLING;
group-onsemi 0:098463de4c5d 298 obj->event = EDGE_FALL;
group-onsemi 0:098463de4c5d 299 }
group-onsemi 0:098463de4c5d 300 }
group-onsemi 0:098463de4c5d 301 } else { // Disable
group-onsemi 0:098463de4c5d 302 if (event == IRQ_RISE) {
group-onsemi 0:098463de4c5d 303 if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) {
group-onsemi 0:098463de4c5d 304 mode = STM_MODE_IT_FALLING;
group-onsemi 0:098463de4c5d 305 obj->event = EDGE_FALL;
group-onsemi 0:098463de4c5d 306 } else { // NONE or RISE
group-onsemi 0:098463de4c5d 307 mode = STM_MODE_INPUT;
group-onsemi 0:098463de4c5d 308 obj->event = EDGE_NONE;
group-onsemi 0:098463de4c5d 309 }
group-onsemi 0:098463de4c5d 310 }
group-onsemi 0:098463de4c5d 311 if (event == IRQ_FALL) {
group-onsemi 0:098463de4c5d 312 if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) {
group-onsemi 0:098463de4c5d 313 mode = STM_MODE_IT_RISING;
group-onsemi 0:098463de4c5d 314 obj->event = EDGE_RISE;
group-onsemi 0:098463de4c5d 315 } else { // NONE or FALL
group-onsemi 0:098463de4c5d 316 mode = STM_MODE_INPUT;
group-onsemi 0:098463de4c5d 317 obj->event = EDGE_NONE;
group-onsemi 0:098463de4c5d 318 }
group-onsemi 0:098463de4c5d 319 }
group-onsemi 0:098463de4c5d 320 }
group-onsemi 0:098463de4c5d 321
group-onsemi 0:098463de4c5d 322 pin_function_gpiomode(obj->pin, mode);
group-onsemi 0:098463de4c5d 323 }
group-onsemi 0:098463de4c5d 324
group-onsemi 0:098463de4c5d 325 void gpio_irq_enable(gpio_irq_t *obj)
group-onsemi 0:098463de4c5d 326 {
group-onsemi 0:098463de4c5d 327 NVIC_EnableIRQ(obj->irq_n);
group-onsemi 0:098463de4c5d 328 }
group-onsemi 0:098463de4c5d 329
group-onsemi 0:098463de4c5d 330 void gpio_irq_disable(gpio_irq_t *obj)
group-onsemi 0:098463de4c5d 331 {
group-onsemi 0:098463de4c5d 332 NVIC_DisableIRQ(obj->irq_n);
group-onsemi 0:098463de4c5d 333 obj->event = EDGE_NONE;
group-onsemi 0:098463de4c5d 334 }