mbed-os | Mbed

ON Semiconductor » Code » mbed-os

Dependents: mbed-TFT-example-NCS36510 mbed-Accelerometer-example-NCS36510 mbed-Accelerometer-example-NCS36510

targets/TARGET_STM/TARGET_STM32F7/device/stm32_hal_legacy.h@1:f30bdcd2b33b, 2017-02-27 (annotated)

Committer:: jacobjohnson
Date:: Mon Feb 27 17:45:05 2017 +0000
Revision:: 1:f30bdcd2b33b
Parent:: 0:098463de4c5d

changed the inputscale from 1 to 7 in analogin_api.c.  This will need to be changed later, and accessed from the main level, but for now this allows the  adc to read a value from 0 to 3.7V, instead of just up to 1V.;

Who changed what in which revision?

User	Revision	Line number	New contents of line
group-onsemi	0:098463de4c5d	1	/**
group-onsemi	0:098463de4c5d	2	******************************************************************************
group-onsemi	0:098463de4c5d	3	* @file stm32_hal_legacy.h
group-onsemi	0:098463de4c5d	4	* @author MCD Application Team
group-onsemi	0:098463de4c5d	5	* @version V1.1.2
group-onsemi	0:098463de4c5d	6	* @date 23-September-2016
group-onsemi	0:098463de4c5d	7	* @brief This file contains aliases definition for the STM32Cube HAL constants
group-onsemi	0:098463de4c5d	8	* macros and functions maintained for legacy purpose.
group-onsemi	0:098463de4c5d	9	******************************************************************************
group-onsemi	0:098463de4c5d	10	* @attention
group-onsemi	0:098463de4c5d	11	*
group-onsemi	0:098463de4c5d	12	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
group-onsemi	0:098463de4c5d	13	*
group-onsemi	0:098463de4c5d	14	* Redistribution and use in source and binary forms, with or without modification,
group-onsemi	0:098463de4c5d	15	* are permitted provided that the following conditions are met:
group-onsemi	0:098463de4c5d	16	* 1. Redistributions of source code must retain the above copyright notice,
group-onsemi	0:098463de4c5d	17	* this list of conditions and the following disclaimer.
group-onsemi	0:098463de4c5d	18	* 2. Redistributions in binary form must reproduce the above copyright notice,
group-onsemi	0:098463de4c5d	19	* this list of conditions and the following disclaimer in the documentation
group-onsemi	0:098463de4c5d	20	* and/or other materials provided with the distribution.
group-onsemi	0:098463de4c5d	21	* 3. Neither the name of STMicroelectronics nor the names of its contributors
group-onsemi	0:098463de4c5d	22	* may be used to endorse or promote products derived from this software
group-onsemi	0:098463de4c5d	23	* without specific prior written permission.
group-onsemi	0:098463de4c5d	24	*
group-onsemi	0:098463de4c5d	25	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
group-onsemi	0:098463de4c5d	26	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
group-onsemi	0:098463de4c5d	27	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
group-onsemi	0:098463de4c5d	28	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
group-onsemi	0:098463de4c5d	29	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
group-onsemi	0:098463de4c5d	30	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
group-onsemi	0:098463de4c5d	31	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
group-onsemi	0:098463de4c5d	32	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
group-onsemi	0:098463de4c5d	33	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
group-onsemi	0:098463de4c5d	34	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
group-onsemi	0:098463de4c5d	35	*
group-onsemi	0:098463de4c5d	36	******************************************************************************
group-onsemi	0:098463de4c5d	37	*/
group-onsemi	0:098463de4c5d	38
group-onsemi	0:098463de4c5d	39	/* Define to prevent recursive inclusion -------------------------------------*/
group-onsemi	0:098463de4c5d	40	#ifndef __STM32_HAL_LEGACY
group-onsemi	0:098463de4c5d	41	#define __STM32_HAL_LEGACY
group-onsemi	0:098463de4c5d	42
group-onsemi	0:098463de4c5d	43	#ifdef __cplusplus
group-onsemi	0:098463de4c5d	44	extern "C" {
group-onsemi	0:098463de4c5d	45	#endif
group-onsemi	0:098463de4c5d	46
group-onsemi	0:098463de4c5d	47	/* Includes ------------------------------------------------------------------*/
group-onsemi	0:098463de4c5d	48	/* Exported types ------------------------------------------------------------*/
group-onsemi	0:098463de4c5d	49	/* Exported constants --------------------------------------------------------*/
group-onsemi	0:098463de4c5d	50
group-onsemi	0:098463de4c5d	51	/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	52	* @{
group-onsemi	0:098463de4c5d	53	*/
group-onsemi	0:098463de4c5d	54	#define AES_FLAG_RDERR CRYP_FLAG_RDERR
group-onsemi	0:098463de4c5d	55	#define AES_FLAG_WRERR CRYP_FLAG_WRERR
group-onsemi	0:098463de4c5d	56	#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
group-onsemi	0:098463de4c5d	57	#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
group-onsemi	0:098463de4c5d	58	#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
group-onsemi	0:098463de4c5d	59
group-onsemi	0:098463de4c5d	60	/**
group-onsemi	0:098463de4c5d	61	* @}
group-onsemi	0:098463de4c5d	62	*/
group-onsemi	0:098463de4c5d	63
group-onsemi	0:098463de4c5d	64	/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	65	* @{
group-onsemi	0:098463de4c5d	66	*/
group-onsemi	0:098463de4c5d	67	#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
group-onsemi	0:098463de4c5d	68	#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
group-onsemi	0:098463de4c5d	69	#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
group-onsemi	0:098463de4c5d	70	#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
group-onsemi	0:098463de4c5d	71	#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
group-onsemi	0:098463de4c5d	72	#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
group-onsemi	0:098463de4c5d	73	#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
group-onsemi	0:098463de4c5d	74	#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
group-onsemi	0:098463de4c5d	75	#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
group-onsemi	0:098463de4c5d	76	#define REGULAR_GROUP ADC_REGULAR_GROUP
group-onsemi	0:098463de4c5d	77	#define INJECTED_GROUP ADC_INJECTED_GROUP
group-onsemi	0:098463de4c5d	78	#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
group-onsemi	0:098463de4c5d	79	#define AWD_EVENT ADC_AWD_EVENT
group-onsemi	0:098463de4c5d	80	#define AWD1_EVENT ADC_AWD1_EVENT
group-onsemi	0:098463de4c5d	81	#define AWD2_EVENT ADC_AWD2_EVENT
group-onsemi	0:098463de4c5d	82	#define AWD3_EVENT ADC_AWD3_EVENT
group-onsemi	0:098463de4c5d	83	#define OVR_EVENT ADC_OVR_EVENT
group-onsemi	0:098463de4c5d	84	#define JQOVF_EVENT ADC_JQOVF_EVENT
group-onsemi	0:098463de4c5d	85	#define ALL_CHANNELS ADC_ALL_CHANNELS
group-onsemi	0:098463de4c5d	86	#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
group-onsemi	0:098463de4c5d	87	#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
group-onsemi	0:098463de4c5d	88	#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
group-onsemi	0:098463de4c5d	89	#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
group-onsemi	0:098463de4c5d	90	#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
group-onsemi	0:098463de4c5d	91	#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
group-onsemi	0:098463de4c5d	92	#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
group-onsemi	0:098463de4c5d	93	#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
group-onsemi	0:098463de4c5d	94	#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
group-onsemi	0:098463de4c5d	95	#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
group-onsemi	0:098463de4c5d	96	#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
group-onsemi	0:098463de4c5d	97	#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
group-onsemi	0:098463de4c5d	98	#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
group-onsemi	0:098463de4c5d	99	#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
group-onsemi	0:098463de4c5d	100	#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
group-onsemi	0:098463de4c5d	101	#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
group-onsemi	0:098463de4c5d	102	#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
group-onsemi	0:098463de4c5d	103	#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
group-onsemi	0:098463de4c5d	104	#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
group-onsemi	0:098463de4c5d	105	#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
group-onsemi	0:098463de4c5d	106	#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
group-onsemi	0:098463de4c5d	107
group-onsemi	0:098463de4c5d	108	#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
group-onsemi	0:098463de4c5d	109	#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
group-onsemi	0:098463de4c5d	110	#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
group-onsemi	0:098463de4c5d	111	#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
group-onsemi	0:098463de4c5d	112	#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
group-onsemi	0:098463de4c5d	113	#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
group-onsemi	0:098463de4c5d	114	#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
group-onsemi	0:098463de4c5d	115	/**
group-onsemi	0:098463de4c5d	116	* @}
group-onsemi	0:098463de4c5d	117	*/
group-onsemi	0:098463de4c5d	118
group-onsemi	0:098463de4c5d	119	/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	120	* @{
group-onsemi	0:098463de4c5d	121	*/
group-onsemi	0:098463de4c5d	122
group-onsemi	0:098463de4c5d	123	#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
group-onsemi	0:098463de4c5d	124
group-onsemi	0:098463de4c5d	125	/**
group-onsemi	0:098463de4c5d	126	* @}
group-onsemi	0:098463de4c5d	127	*/
group-onsemi	0:098463de4c5d	128
group-onsemi	0:098463de4c5d	129	/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	130	* @{
group-onsemi	0:098463de4c5d	131	*/
group-onsemi	0:098463de4c5d	132	#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
group-onsemi	0:098463de4c5d	133	#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
group-onsemi	0:098463de4c5d	134	#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
group-onsemi	0:098463de4c5d	135	#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
group-onsemi	0:098463de4c5d	136	#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
group-onsemi	0:098463de4c5d	137	#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
group-onsemi	0:098463de4c5d	138	#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
group-onsemi	0:098463de4c5d	139	#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
group-onsemi	0:098463de4c5d	140	#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
group-onsemi	0:098463de4c5d	141	#define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /!< COMPX output is connected to LPTIM input 1 /
group-onsemi	0:098463de4c5d	142	#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
group-onsemi	0:098463de4c5d	143	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
group-onsemi	0:098463de4c5d	144	#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
group-onsemi	0:098463de4c5d	145	#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
group-onsemi	0:098463de4c5d	146	#endif /* STM32F373xC \|\| STM32F378xx */
group-onsemi	0:098463de4c5d	147
group-onsemi	0:098463de4c5d	148	#if defined(STM32L0) \|\| defined(STM32L4)
group-onsemi	0:098463de4c5d	149	#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
group-onsemi	0:098463de4c5d	150
group-onsemi	0:098463de4c5d	151	#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
group-onsemi	0:098463de4c5d	152	#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
group-onsemi	0:098463de4c5d	153	#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
group-onsemi	0:098463de4c5d	154	#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
group-onsemi	0:098463de4c5d	155	#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
group-onsemi	0:098463de4c5d	156	#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
group-onsemi	0:098463de4c5d	157
group-onsemi	0:098463de4c5d	158	#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
group-onsemi	0:098463de4c5d	159	#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
group-onsemi	0:098463de4c5d	160	#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
group-onsemi	0:098463de4c5d	161	#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
group-onsemi	0:098463de4c5d	162	#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
group-onsemi	0:098463de4c5d	163	#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
group-onsemi	0:098463de4c5d	164	#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
group-onsemi	0:098463de4c5d	165	#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
group-onsemi	0:098463de4c5d	166	#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
group-onsemi	0:098463de4c5d	167	#if defined(STM32L0)
group-onsemi	0:098463de4c5d	168	/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
group-onsemi	0:098463de4c5d	169	/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
group-onsemi	0:098463de4c5d	170	/* to the second dedicated IO (only for COMP2). */
group-onsemi	0:098463de4c5d	171	#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
group-onsemi	0:098463de4c5d	172	#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
group-onsemi	0:098463de4c5d	173	#else
group-onsemi	0:098463de4c5d	174	#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
group-onsemi	0:098463de4c5d	175	#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
group-onsemi	0:098463de4c5d	176	#endif
group-onsemi	0:098463de4c5d	177	#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
group-onsemi	0:098463de4c5d	178	#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
group-onsemi	0:098463de4c5d	179
group-onsemi	0:098463de4c5d	180	#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
group-onsemi	0:098463de4c5d	181	#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
group-onsemi	0:098463de4c5d	182
group-onsemi	0:098463de4c5d	183	/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
group-onsemi	0:098463de4c5d	184	/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
group-onsemi	0:098463de4c5d	185	#if defined(COMP_CSR_LOCK)
group-onsemi	0:098463de4c5d	186	#define COMP_FLAG_LOCK COMP_CSR_LOCK
group-onsemi	0:098463de4c5d	187	#elif defined(COMP_CSR_COMP1LOCK)
group-onsemi	0:098463de4c5d	188	#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
group-onsemi	0:098463de4c5d	189	#elif defined(COMP_CSR_COMPxLOCK)
group-onsemi	0:098463de4c5d	190	#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
group-onsemi	0:098463de4c5d	191	#endif
group-onsemi	0:098463de4c5d	192
group-onsemi	0:098463de4c5d	193	#if defined(STM32L4)
group-onsemi	0:098463de4c5d	194	#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
group-onsemi	0:098463de4c5d	195	#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
group-onsemi	0:098463de4c5d	196	#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
group-onsemi	0:098463de4c5d	197	#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
group-onsemi	0:098463de4c5d	198	#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
group-onsemi	0:098463de4c5d	199	#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
group-onsemi	0:098463de4c5d	200	#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
group-onsemi	0:098463de4c5d	201	#endif
group-onsemi	0:098463de4c5d	202
group-onsemi	0:098463de4c5d	203	#if defined(STM32L0)
group-onsemi	0:098463de4c5d	204	#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
group-onsemi	0:098463de4c5d	205	#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
group-onsemi	0:098463de4c5d	206	#else
group-onsemi	0:098463de4c5d	207	#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
group-onsemi	0:098463de4c5d	208	#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
group-onsemi	0:098463de4c5d	209	#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
group-onsemi	0:098463de4c5d	210	#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
group-onsemi	0:098463de4c5d	211	#endif
group-onsemi	0:098463de4c5d	212
group-onsemi	0:098463de4c5d	213	#endif
group-onsemi	0:098463de4c5d	214	/**
group-onsemi	0:098463de4c5d	215	* @}
group-onsemi	0:098463de4c5d	216	*/
group-onsemi	0:098463de4c5d	217
group-onsemi	0:098463de4c5d	218	/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	219	* @{
group-onsemi	0:098463de4c5d	220	*/
group-onsemi	0:098463de4c5d	221	#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
group-onsemi	0:098463de4c5d	222	/**
group-onsemi	0:098463de4c5d	223	* @}
group-onsemi	0:098463de4c5d	224	*/
group-onsemi	0:098463de4c5d	225
group-onsemi	0:098463de4c5d	226	/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	227	* @{
group-onsemi	0:098463de4c5d	228	*/
group-onsemi	0:098463de4c5d	229
group-onsemi	0:098463de4c5d	230	#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
group-onsemi	0:098463de4c5d	231	#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
group-onsemi	0:098463de4c5d	232
group-onsemi	0:098463de4c5d	233	/**
group-onsemi	0:098463de4c5d	234	* @}
group-onsemi	0:098463de4c5d	235	*/
group-onsemi	0:098463de4c5d	236
group-onsemi	0:098463de4c5d	237	/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	238	* @{
group-onsemi	0:098463de4c5d	239	*/
group-onsemi	0:098463de4c5d	240
group-onsemi	0:098463de4c5d	241	#define DAC1_CHANNEL_1 DAC_CHANNEL_1
group-onsemi	0:098463de4c5d	242	#define DAC1_CHANNEL_2 DAC_CHANNEL_2
group-onsemi	0:098463de4c5d	243	#define DAC2_CHANNEL_1 DAC_CHANNEL_1
group-onsemi	0:098463de4c5d	244	#define DAC_WAVE_NONE ((uint32_t)0x00000000U)
group-onsemi	0:098463de4c5d	245	#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
group-onsemi	0:098463de4c5d	246	#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
group-onsemi	0:098463de4c5d	247	#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
group-onsemi	0:098463de4c5d	248	#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
group-onsemi	0:098463de4c5d	249	#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
group-onsemi	0:098463de4c5d	250
group-onsemi	0:098463de4c5d	251	/**
group-onsemi	0:098463de4c5d	252	* @}
group-onsemi	0:098463de4c5d	253	*/
group-onsemi	0:098463de4c5d	254
group-onsemi	0:098463de4c5d	255	/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	256	* @{
group-onsemi	0:098463de4c5d	257	*/
group-onsemi	0:098463de4c5d	258	#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
group-onsemi	0:098463de4c5d	259	#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
group-onsemi	0:098463de4c5d	260	#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
group-onsemi	0:098463de4c5d	261	#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
group-onsemi	0:098463de4c5d	262	#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
group-onsemi	0:098463de4c5d	263	#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
group-onsemi	0:098463de4c5d	264	#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
group-onsemi	0:098463de4c5d	265	#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
group-onsemi	0:098463de4c5d	266	#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
group-onsemi	0:098463de4c5d	267	#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
group-onsemi	0:098463de4c5d	268	#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
group-onsemi	0:098463de4c5d	269	#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
group-onsemi	0:098463de4c5d	270	#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
group-onsemi	0:098463de4c5d	271	#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
group-onsemi	0:098463de4c5d	272	#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
group-onsemi	0:098463de4c5d	273
group-onsemi	0:098463de4c5d	274	#define IS_HAL_REMAPDMA IS_DMA_REMAP
group-onsemi	0:098463de4c5d	275	#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
group-onsemi	0:098463de4c5d	276	#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
group-onsemi	0:098463de4c5d	277
group-onsemi	0:098463de4c5d	278
group-onsemi	0:098463de4c5d	279
group-onsemi	0:098463de4c5d	280	/**
group-onsemi	0:098463de4c5d	281	* @}
group-onsemi	0:098463de4c5d	282	*/
group-onsemi	0:098463de4c5d	283
group-onsemi	0:098463de4c5d	284	/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	285	* @{
group-onsemi	0:098463de4c5d	286	*/
group-onsemi	0:098463de4c5d	287
group-onsemi	0:098463de4c5d	288	#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
group-onsemi	0:098463de4c5d	289	#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
group-onsemi	0:098463de4c5d	290	#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
group-onsemi	0:098463de4c5d	291	#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
group-onsemi	0:098463de4c5d	292	#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
group-onsemi	0:098463de4c5d	293	#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
group-onsemi	0:098463de4c5d	294	#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
group-onsemi	0:098463de4c5d	295	#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
group-onsemi	0:098463de4c5d	296	#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
group-onsemi	0:098463de4c5d	297	#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
group-onsemi	0:098463de4c5d	298	#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
group-onsemi	0:098463de4c5d	299	#define OBEX_PCROP OPTIONBYTE_PCROP
group-onsemi	0:098463de4c5d	300	#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
group-onsemi	0:098463de4c5d	301	#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
group-onsemi	0:098463de4c5d	302	#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
group-onsemi	0:098463de4c5d	303	#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
group-onsemi	0:098463de4c5d	304	#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
group-onsemi	0:098463de4c5d	305	#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
group-onsemi	0:098463de4c5d	306	#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
group-onsemi	0:098463de4c5d	307	#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
group-onsemi	0:098463de4c5d	308	#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
group-onsemi	0:098463de4c5d	309	#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
group-onsemi	0:098463de4c5d	310	#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
group-onsemi	0:098463de4c5d	311	#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
group-onsemi	0:098463de4c5d	312	#define PAGESIZE FLASH_PAGE_SIZE
group-onsemi	0:098463de4c5d	313	#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
group-onsemi	0:098463de4c5d	314	#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
group-onsemi	0:098463de4c5d	315	#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
group-onsemi	0:098463de4c5d	316	#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
group-onsemi	0:098463de4c5d	317	#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
group-onsemi	0:098463de4c5d	318	#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
group-onsemi	0:098463de4c5d	319	#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
group-onsemi	0:098463de4c5d	320	#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
group-onsemi	0:098463de4c5d	321	#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
group-onsemi	0:098463de4c5d	322	#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
group-onsemi	0:098463de4c5d	323	#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
group-onsemi	0:098463de4c5d	324	#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
group-onsemi	0:098463de4c5d	325	#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
group-onsemi	0:098463de4c5d	326	#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
group-onsemi	0:098463de4c5d	327	#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
group-onsemi	0:098463de4c5d	328	#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
group-onsemi	0:098463de4c5d	329	#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
group-onsemi	0:098463de4c5d	330	#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
group-onsemi	0:098463de4c5d	331	#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
group-onsemi	0:098463de4c5d	332	#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
group-onsemi	0:098463de4c5d	333	#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
group-onsemi	0:098463de4c5d	334	#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
group-onsemi	0:098463de4c5d	335	#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
group-onsemi	0:098463de4c5d	336	#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
group-onsemi	0:098463de4c5d	337	#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
group-onsemi	0:098463de4c5d	338	#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
group-onsemi	0:098463de4c5d	339	#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
group-onsemi	0:098463de4c5d	340	#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
group-onsemi	0:098463de4c5d	341	#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
group-onsemi	0:098463de4c5d	342	#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
group-onsemi	0:098463de4c5d	343	#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
group-onsemi	0:098463de4c5d	344	#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
group-onsemi	0:098463de4c5d	345	#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
group-onsemi	0:098463de4c5d	346	#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
group-onsemi	0:098463de4c5d	347	#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
group-onsemi	0:098463de4c5d	348	#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
group-onsemi	0:098463de4c5d	349	#define OB_WDG_SW OB_IWDG_SW
group-onsemi	0:098463de4c5d	350	#define OB_WDG_HW OB_IWDG_HW
group-onsemi	0:098463de4c5d	351	#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
group-onsemi	0:098463de4c5d	352	#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
group-onsemi	0:098463de4c5d	353	#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
group-onsemi	0:098463de4c5d	354	#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
group-onsemi	0:098463de4c5d	355	#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
group-onsemi	0:098463de4c5d	356	#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
group-onsemi	0:098463de4c5d	357	#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
group-onsemi	0:098463de4c5d	358	#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
group-onsemi	0:098463de4c5d	359
group-onsemi	0:098463de4c5d	360	/**
group-onsemi	0:098463de4c5d	361	* @}
group-onsemi	0:098463de4c5d	362	*/
group-onsemi	0:098463de4c5d	363
group-onsemi	0:098463de4c5d	364	/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	365	* @{
group-onsemi	0:098463de4c5d	366	*/
group-onsemi	0:098463de4c5d	367
group-onsemi	0:098463de4c5d	368	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
group-onsemi	0:098463de4c5d	369	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
group-onsemi	0:098463de4c5d	370	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
group-onsemi	0:098463de4c5d	371	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
group-onsemi	0:098463de4c5d	372	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
group-onsemi	0:098463de4c5d	373	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
group-onsemi	0:098463de4c5d	374	#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
group-onsemi	0:098463de4c5d	375	#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
group-onsemi	0:098463de4c5d	376	#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
group-onsemi	0:098463de4c5d	377	/**
group-onsemi	0:098463de4c5d	378	* @}
group-onsemi	0:098463de4c5d	379	*/
group-onsemi	0:098463de4c5d	380
group-onsemi	0:098463de4c5d	381
group-onsemi	0:098463de4c5d	382	/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
group-onsemi	0:098463de4c5d	383	* @{
group-onsemi	0:098463de4c5d	384	*/
group-onsemi	0:098463de4c5d	385	#if defined(STM32L4) \|\| defined(STM32F7)
group-onsemi	0:098463de4c5d	386	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
group-onsemi	0:098463de4c5d	387	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
group-onsemi	0:098463de4c5d	388	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
group-onsemi	0:098463de4c5d	389	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
group-onsemi	0:098463de4c5d	390	#else
group-onsemi	0:098463de4c5d	391	#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
group-onsemi	0:098463de4c5d	392	#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
group-onsemi	0:098463de4c5d	393	#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
group-onsemi	0:098463de4c5d	394	#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
group-onsemi	0:098463de4c5d	395	#endif
group-onsemi	0:098463de4c5d	396	/**
group-onsemi	0:098463de4c5d	397	* @}
group-onsemi	0:098463de4c5d	398	*/
group-onsemi	0:098463de4c5d	399
group-onsemi	0:098463de4c5d	400	/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	401	* @{
group-onsemi	0:098463de4c5d	402	*/
group-onsemi	0:098463de4c5d	403
group-onsemi	0:098463de4c5d	404	#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
group-onsemi	0:098463de4c5d	405	#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
group-onsemi	0:098463de4c5d	406	/**
group-onsemi	0:098463de4c5d	407	* @}
group-onsemi	0:098463de4c5d	408	*/
group-onsemi	0:098463de4c5d	409
group-onsemi	0:098463de4c5d	410	/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	411	* @{
group-onsemi	0:098463de4c5d	412	*/
group-onsemi	0:098463de4c5d	413	#define GET_GPIO_SOURCE GPIO_GET_INDEX
group-onsemi	0:098463de4c5d	414	#define GET_GPIO_INDEX GPIO_GET_INDEX
group-onsemi	0:098463de4c5d	415
group-onsemi	0:098463de4c5d	416	#if defined(STM32F4)
group-onsemi	0:098463de4c5d	417	#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
group-onsemi	0:098463de4c5d	418	#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
group-onsemi	0:098463de4c5d	419	#endif
group-onsemi	0:098463de4c5d	420
group-onsemi	0:098463de4c5d	421	#if defined(STM32F7)
group-onsemi	0:098463de4c5d	422	#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
group-onsemi	0:098463de4c5d	423	#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
group-onsemi	0:098463de4c5d	424	#endif
group-onsemi	0:098463de4c5d	425
group-onsemi	0:098463de4c5d	426	#if defined(STM32L4)
group-onsemi	0:098463de4c5d	427	#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
group-onsemi	0:098463de4c5d	428	#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
group-onsemi	0:098463de4c5d	429	#endif
group-onsemi	0:098463de4c5d	430
group-onsemi	0:098463de4c5d	431	#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
group-onsemi	0:098463de4c5d	432	#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
group-onsemi	0:098463de4c5d	433	#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
group-onsemi	0:098463de4c5d	434
group-onsemi	0:098463de4c5d	435	#if defined(STM32L0) \|\| defined(STM32L4) \|\| defined(STM32F4) \|\| defined(STM32F2) \|\| defined(STM32F7)
group-onsemi	0:098463de4c5d	436	#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
group-onsemi	0:098463de4c5d	437	#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
group-onsemi	0:098463de4c5d	438	#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
group-onsemi	0:098463de4c5d	439	#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
group-onsemi	0:098463de4c5d	440	#endif /* STM32L0 \|\| STM32L4 \|\| STM32F4 \|\| STM32F2 \|\| STM32F7 */
group-onsemi	0:098463de4c5d	441
group-onsemi	0:098463de4c5d	442	#if defined(STM32L1)
group-onsemi	0:098463de4c5d	443	#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
group-onsemi	0:098463de4c5d	444	#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
group-onsemi	0:098463de4c5d	445	#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
group-onsemi	0:098463de4c5d	446	#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
group-onsemi	0:098463de4c5d	447	#endif /* STM32L1 */
group-onsemi	0:098463de4c5d	448
group-onsemi	0:098463de4c5d	449	#if defined(STM32F0) \|\| defined(STM32F3) \|\| defined(STM32F1)
group-onsemi	0:098463de4c5d	450	#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
group-onsemi	0:098463de4c5d	451	#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
group-onsemi	0:098463de4c5d	452	#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
group-onsemi	0:098463de4c5d	453	#endif /* STM32F0 \|\| STM32F3 \|\| STM32F1 */
group-onsemi	0:098463de4c5d	454
group-onsemi	0:098463de4c5d	455	#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
group-onsemi	0:098463de4c5d	456	/**
group-onsemi	0:098463de4c5d	457	* @}
group-onsemi	0:098463de4c5d	458	*/
group-onsemi	0:098463de4c5d	459
group-onsemi	0:098463de4c5d	460	/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	461	* @{
group-onsemi	0:098463de4c5d	462	*/
group-onsemi	0:098463de4c5d	463	#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
group-onsemi	0:098463de4c5d	464	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
group-onsemi	0:098463de4c5d	465	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
group-onsemi	0:098463de4c5d	466	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
group-onsemi	0:098463de4c5d	467	#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
group-onsemi	0:098463de4c5d	468	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
group-onsemi	0:098463de4c5d	469	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
group-onsemi	0:098463de4c5d	470	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
group-onsemi	0:098463de4c5d	471	#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
group-onsemi	0:098463de4c5d	472
group-onsemi	0:098463de4c5d	473	#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
group-onsemi	0:098463de4c5d	474	#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
group-onsemi	0:098463de4c5d	475	#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
group-onsemi	0:098463de4c5d	476	#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
group-onsemi	0:098463de4c5d	477	#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
group-onsemi	0:098463de4c5d	478	#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
group-onsemi	0:098463de4c5d	479	#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
group-onsemi	0:098463de4c5d	480	#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
group-onsemi	0:098463de4c5d	481	/**
group-onsemi	0:098463de4c5d	482	* @}
group-onsemi	0:098463de4c5d	483	*/
group-onsemi	0:098463de4c5d	484
group-onsemi	0:098463de4c5d	485	/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	486	* @{
group-onsemi	0:098463de4c5d	487	*/
group-onsemi	0:098463de4c5d	488	#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
group-onsemi	0:098463de4c5d	489	#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
group-onsemi	0:098463de4c5d	490	#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
group-onsemi	0:098463de4c5d	491	#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
group-onsemi	0:098463de4c5d	492	#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
group-onsemi	0:098463de4c5d	493	#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
group-onsemi	0:098463de4c5d	494	#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
group-onsemi	0:098463de4c5d	495	#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
group-onsemi	0:098463de4c5d	496	#if defined(STM32F0) \|\| defined(STM32F1) \|\| defined(STM32F3) \|\| defined(STM32G0) \|\| defined(STM32L4) \|\| defined(STM32L1) \|\| defined(STM32F7)
group-onsemi	0:098463de4c5d	497	#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
group-onsemi	0:098463de4c5d	498	#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
group-onsemi	0:098463de4c5d	499	#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
group-onsemi	0:098463de4c5d	500	#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
group-onsemi	0:098463de4c5d	501	#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
group-onsemi	0:098463de4c5d	502	#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
group-onsemi	0:098463de4c5d	503	#endif
group-onsemi	0:098463de4c5d	504	/**
group-onsemi	0:098463de4c5d	505	* @}
group-onsemi	0:098463de4c5d	506	*/
group-onsemi	0:098463de4c5d	507
group-onsemi	0:098463de4c5d	508	/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	509	* @{
group-onsemi	0:098463de4c5d	510	*/
group-onsemi	0:098463de4c5d	511	#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
group-onsemi	0:098463de4c5d	512	#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
group-onsemi	0:098463de4c5d	513
group-onsemi	0:098463de4c5d	514	/**
group-onsemi	0:098463de4c5d	515	* @}
group-onsemi	0:098463de4c5d	516	*/
group-onsemi	0:098463de4c5d	517
group-onsemi	0:098463de4c5d	518	/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	519	* @{
group-onsemi	0:098463de4c5d	520	*/
group-onsemi	0:098463de4c5d	521	#define KR_KEY_RELOAD IWDG_KEY_RELOAD
group-onsemi	0:098463de4c5d	522	#define KR_KEY_ENABLE IWDG_KEY_ENABLE
group-onsemi	0:098463de4c5d	523	#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
group-onsemi	0:098463de4c5d	524	#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
group-onsemi	0:098463de4c5d	525	/**
group-onsemi	0:098463de4c5d	526	* @}
group-onsemi	0:098463de4c5d	527	*/
group-onsemi	0:098463de4c5d	528
group-onsemi	0:098463de4c5d	529	/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	530	* @{
group-onsemi	0:098463de4c5d	531	*/
group-onsemi	0:098463de4c5d	532
group-onsemi	0:098463de4c5d	533	#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
group-onsemi	0:098463de4c5d	534	#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
group-onsemi	0:098463de4c5d	535	#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
group-onsemi	0:098463de4c5d	536	#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
group-onsemi	0:098463de4c5d	537
group-onsemi	0:098463de4c5d	538	#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
group-onsemi	0:098463de4c5d	539	#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
group-onsemi	0:098463de4c5d	540	#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
group-onsemi	0:098463de4c5d	541
group-onsemi	0:098463de4c5d	542	#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
group-onsemi	0:098463de4c5d	543	#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
group-onsemi	0:098463de4c5d	544	#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
group-onsemi	0:098463de4c5d	545	#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
group-onsemi	0:098463de4c5d	546
group-onsemi	0:098463de4c5d	547	/* The following 3 definition have also been present in a temporary version of lptim.h */
group-onsemi	0:098463de4c5d	548	/* They need to be renamed also to the right name, just in case */
group-onsemi	0:098463de4c5d	549	#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
group-onsemi	0:098463de4c5d	550	#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
group-onsemi	0:098463de4c5d	551	#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
group-onsemi	0:098463de4c5d	552
group-onsemi	0:098463de4c5d	553	/**
group-onsemi	0:098463de4c5d	554	* @}
group-onsemi	0:098463de4c5d	555	*/
group-onsemi	0:098463de4c5d	556
group-onsemi	0:098463de4c5d	557	/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	558	* @{
group-onsemi	0:098463de4c5d	559	*/
group-onsemi	0:098463de4c5d	560	#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
group-onsemi	0:098463de4c5d	561	#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
group-onsemi	0:098463de4c5d	562	#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
group-onsemi	0:098463de4c5d	563	#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
group-onsemi	0:098463de4c5d	564
group-onsemi	0:098463de4c5d	565	#define NAND_AddressTypedef NAND_AddressTypeDef
group-onsemi	0:098463de4c5d	566
group-onsemi	0:098463de4c5d	567	#define __ARRAY_ADDRESS ARRAY_ADDRESS
group-onsemi	0:098463de4c5d	568	#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
group-onsemi	0:098463de4c5d	569	#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
group-onsemi	0:098463de4c5d	570	#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
group-onsemi	0:098463de4c5d	571	#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
group-onsemi	0:098463de4c5d	572	/**
group-onsemi	0:098463de4c5d	573	* @}
group-onsemi	0:098463de4c5d	574	*/
group-onsemi	0:098463de4c5d	575
group-onsemi	0:098463de4c5d	576	/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	577	* @{
group-onsemi	0:098463de4c5d	578	*/
group-onsemi	0:098463de4c5d	579	#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
group-onsemi	0:098463de4c5d	580	#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
group-onsemi	0:098463de4c5d	581	#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
group-onsemi	0:098463de4c5d	582	#define NOR_ERROR HAL_NOR_STATUS_ERROR
group-onsemi	0:098463de4c5d	583	#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
group-onsemi	0:098463de4c5d	584
group-onsemi	0:098463de4c5d	585	#define __NOR_WRITE NOR_WRITE
group-onsemi	0:098463de4c5d	586	#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
group-onsemi	0:098463de4c5d	587	/**
group-onsemi	0:098463de4c5d	588	* @}
group-onsemi	0:098463de4c5d	589	*/
group-onsemi	0:098463de4c5d	590
group-onsemi	0:098463de4c5d	591	/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	592	* @{
group-onsemi	0:098463de4c5d	593	*/
group-onsemi	0:098463de4c5d	594
group-onsemi	0:098463de4c5d	595	#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
group-onsemi	0:098463de4c5d	596	#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
group-onsemi	0:098463de4c5d	597	#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
group-onsemi	0:098463de4c5d	598	#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
group-onsemi	0:098463de4c5d	599
group-onsemi	0:098463de4c5d	600	#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
group-onsemi	0:098463de4c5d	601	#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
group-onsemi	0:098463de4c5d	602	#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
group-onsemi	0:098463de4c5d	603	#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
group-onsemi	0:098463de4c5d	604
group-onsemi	0:098463de4c5d	605	#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
group-onsemi	0:098463de4c5d	606	#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
group-onsemi	0:098463de4c5d	607
group-onsemi	0:098463de4c5d	608	#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
group-onsemi	0:098463de4c5d	609	#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
group-onsemi	0:098463de4c5d	610
group-onsemi	0:098463de4c5d	611	#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
group-onsemi	0:098463de4c5d	612	#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
group-onsemi	0:098463de4c5d	613
group-onsemi	0:098463de4c5d	614	#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
group-onsemi	0:098463de4c5d	615
group-onsemi	0:098463de4c5d	616	#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
group-onsemi	0:098463de4c5d	617	#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
group-onsemi	0:098463de4c5d	618	#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
group-onsemi	0:098463de4c5d	619
group-onsemi	0:098463de4c5d	620	/**
group-onsemi	0:098463de4c5d	621	* @}
group-onsemi	0:098463de4c5d	622	*/
group-onsemi	0:098463de4c5d	623
group-onsemi	0:098463de4c5d	624	/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	625	* @{
group-onsemi	0:098463de4c5d	626	*/
group-onsemi	0:098463de4c5d	627	#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
group-onsemi	0:098463de4c5d	628	#if defined(STM32F7)
group-onsemi	0:098463de4c5d	629	#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
group-onsemi	0:098463de4c5d	630	#endif
group-onsemi	0:098463de4c5d	631	/**
group-onsemi	0:098463de4c5d	632	* @}
group-onsemi	0:098463de4c5d	633	*/
group-onsemi	0:098463de4c5d	634
group-onsemi	0:098463de4c5d	635	/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	636	* @{
group-onsemi	0:098463de4c5d	637	*/
group-onsemi	0:098463de4c5d	638
group-onsemi	0:098463de4c5d	639	/* Compact Flash-ATA registers description */
group-onsemi	0:098463de4c5d	640	#define CF_DATA ATA_DATA
group-onsemi	0:098463de4c5d	641	#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
group-onsemi	0:098463de4c5d	642	#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
group-onsemi	0:098463de4c5d	643	#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
group-onsemi	0:098463de4c5d	644	#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
group-onsemi	0:098463de4c5d	645	#define CF_CARD_HEAD ATA_CARD_HEAD
group-onsemi	0:098463de4c5d	646	#define CF_STATUS_CMD ATA_STATUS_CMD
group-onsemi	0:098463de4c5d	647	#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
group-onsemi	0:098463de4c5d	648	#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
group-onsemi	0:098463de4c5d	649
group-onsemi	0:098463de4c5d	650	/* Compact Flash-ATA commands */
group-onsemi	0:098463de4c5d	651	#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
group-onsemi	0:098463de4c5d	652	#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
group-onsemi	0:098463de4c5d	653	#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
group-onsemi	0:098463de4c5d	654	#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
group-onsemi	0:098463de4c5d	655
group-onsemi	0:098463de4c5d	656	#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
group-onsemi	0:098463de4c5d	657	#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
group-onsemi	0:098463de4c5d	658	#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
group-onsemi	0:098463de4c5d	659	#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
group-onsemi	0:098463de4c5d	660	#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
group-onsemi	0:098463de4c5d	661	/**
group-onsemi	0:098463de4c5d	662	* @}
group-onsemi	0:098463de4c5d	663	*/
group-onsemi	0:098463de4c5d	664
group-onsemi	0:098463de4c5d	665	/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	666	* @{
group-onsemi	0:098463de4c5d	667	*/
group-onsemi	0:098463de4c5d	668
group-onsemi	0:098463de4c5d	669	#define FORMAT_BIN RTC_FORMAT_BIN
group-onsemi	0:098463de4c5d	670	#define FORMAT_BCD RTC_FORMAT_BCD
group-onsemi	0:098463de4c5d	671
group-onsemi	0:098463de4c5d	672	#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
group-onsemi	0:098463de4c5d	673	#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
group-onsemi	0:098463de4c5d	674	#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
group-onsemi	0:098463de4c5d	675	#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
group-onsemi	0:098463de4c5d	676	#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
group-onsemi	0:098463de4c5d	677
group-onsemi	0:098463de4c5d	678	#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
group-onsemi	0:098463de4c5d	679	#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
group-onsemi	0:098463de4c5d	680	#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
group-onsemi	0:098463de4c5d	681	#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
group-onsemi	0:098463de4c5d	682	#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
group-onsemi	0:098463de4c5d	683	#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
group-onsemi	0:098463de4c5d	684	#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
group-onsemi	0:098463de4c5d	685	#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
group-onsemi	0:098463de4c5d	686
group-onsemi	0:098463de4c5d	687	#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
group-onsemi	0:098463de4c5d	688	#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
group-onsemi	0:098463de4c5d	689	#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
group-onsemi	0:098463de4c5d	690	#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
group-onsemi	0:098463de4c5d	691
group-onsemi	0:098463de4c5d	692	#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
group-onsemi	0:098463de4c5d	693	#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
group-onsemi	0:098463de4c5d	694	#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
group-onsemi	0:098463de4c5d	695
group-onsemi	0:098463de4c5d	696	#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
group-onsemi	0:098463de4c5d	697	#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
group-onsemi	0:098463de4c5d	698	#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
group-onsemi	0:098463de4c5d	699
group-onsemi	0:098463de4c5d	700	/**
group-onsemi	0:098463de4c5d	701	* @}
group-onsemi	0:098463de4c5d	702	*/
group-onsemi	0:098463de4c5d	703
group-onsemi	0:098463de4c5d	704
group-onsemi	0:098463de4c5d	705	/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	706	* @{
group-onsemi	0:098463de4c5d	707	*/
group-onsemi	0:098463de4c5d	708	#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
group-onsemi	0:098463de4c5d	709	#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
group-onsemi	0:098463de4c5d	710
group-onsemi	0:098463de4c5d	711	#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
group-onsemi	0:098463de4c5d	712	#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
group-onsemi	0:098463de4c5d	713	#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
group-onsemi	0:098463de4c5d	714	#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
group-onsemi	0:098463de4c5d	715
group-onsemi	0:098463de4c5d	716	#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
group-onsemi	0:098463de4c5d	717	#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
group-onsemi	0:098463de4c5d	718
group-onsemi	0:098463de4c5d	719	#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
group-onsemi	0:098463de4c5d	720	#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
group-onsemi	0:098463de4c5d	721	/**
group-onsemi	0:098463de4c5d	722	* @}
group-onsemi	0:098463de4c5d	723	*/
group-onsemi	0:098463de4c5d	724
group-onsemi	0:098463de4c5d	725
group-onsemi	0:098463de4c5d	726	/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	727	* @{
group-onsemi	0:098463de4c5d	728	*/
group-onsemi	0:098463de4c5d	729	#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
group-onsemi	0:098463de4c5d	730	#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
group-onsemi	0:098463de4c5d	731	#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
group-onsemi	0:098463de4c5d	732	#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
group-onsemi	0:098463de4c5d	733	#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
group-onsemi	0:098463de4c5d	734	#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
group-onsemi	0:098463de4c5d	735	#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
group-onsemi	0:098463de4c5d	736	#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
group-onsemi	0:098463de4c5d	737	#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
group-onsemi	0:098463de4c5d	738	#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
group-onsemi	0:098463de4c5d	739	#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
group-onsemi	0:098463de4c5d	740	/**
group-onsemi	0:098463de4c5d	741	* @}
group-onsemi	0:098463de4c5d	742	*/
group-onsemi	0:098463de4c5d	743
group-onsemi	0:098463de4c5d	744	/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	745	* @{
group-onsemi	0:098463de4c5d	746	*/
group-onsemi	0:098463de4c5d	747	#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
group-onsemi	0:098463de4c5d	748	#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
group-onsemi	0:098463de4c5d	749
group-onsemi	0:098463de4c5d	750	#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
group-onsemi	0:098463de4c5d	751	#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
group-onsemi	0:098463de4c5d	752
group-onsemi	0:098463de4c5d	753	#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
group-onsemi	0:098463de4c5d	754	#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
group-onsemi	0:098463de4c5d	755
group-onsemi	0:098463de4c5d	756	/**
group-onsemi	0:098463de4c5d	757	* @}
group-onsemi	0:098463de4c5d	758	*/
group-onsemi	0:098463de4c5d	759
group-onsemi	0:098463de4c5d	760	/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	761	* @{
group-onsemi	0:098463de4c5d	762	*/
group-onsemi	0:098463de4c5d	763	#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
group-onsemi	0:098463de4c5d	764	#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
group-onsemi	0:098463de4c5d	765
group-onsemi	0:098463de4c5d	766	#define TIM_DMABase_CR1 TIM_DMABASE_CR1
group-onsemi	0:098463de4c5d	767	#define TIM_DMABase_CR2 TIM_DMABASE_CR2
group-onsemi	0:098463de4c5d	768	#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
group-onsemi	0:098463de4c5d	769	#define TIM_DMABase_DIER TIM_DMABASE_DIER
group-onsemi	0:098463de4c5d	770	#define TIM_DMABase_SR TIM_DMABASE_SR
group-onsemi	0:098463de4c5d	771	#define TIM_DMABase_EGR TIM_DMABASE_EGR
group-onsemi	0:098463de4c5d	772	#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
group-onsemi	0:098463de4c5d	773	#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
group-onsemi	0:098463de4c5d	774	#define TIM_DMABase_CCER TIM_DMABASE_CCER
group-onsemi	0:098463de4c5d	775	#define TIM_DMABase_CNT TIM_DMABASE_CNT
group-onsemi	0:098463de4c5d	776	#define TIM_DMABase_PSC TIM_DMABASE_PSC
group-onsemi	0:098463de4c5d	777	#define TIM_DMABase_ARR TIM_DMABASE_ARR
group-onsemi	0:098463de4c5d	778	#define TIM_DMABase_RCR TIM_DMABASE_RCR
group-onsemi	0:098463de4c5d	779	#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
group-onsemi	0:098463de4c5d	780	#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
group-onsemi	0:098463de4c5d	781	#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
group-onsemi	0:098463de4c5d	782	#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
group-onsemi	0:098463de4c5d	783	#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
group-onsemi	0:098463de4c5d	784	#define TIM_DMABase_DCR TIM_DMABASE_DCR
group-onsemi	0:098463de4c5d	785	#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
group-onsemi	0:098463de4c5d	786	#define TIM_DMABase_OR1 TIM_DMABASE_OR1
group-onsemi	0:098463de4c5d	787	#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
group-onsemi	0:098463de4c5d	788	#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
group-onsemi	0:098463de4c5d	789	#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
group-onsemi	0:098463de4c5d	790	#define TIM_DMABase_OR2 TIM_DMABASE_OR2
group-onsemi	0:098463de4c5d	791	#define TIM_DMABase_OR3 TIM_DMABASE_OR3
group-onsemi	0:098463de4c5d	792	#define TIM_DMABase_OR TIM_DMABASE_OR
group-onsemi	0:098463de4c5d	793
group-onsemi	0:098463de4c5d	794	#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
group-onsemi	0:098463de4c5d	795	#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
group-onsemi	0:098463de4c5d	796	#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
group-onsemi	0:098463de4c5d	797	#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
group-onsemi	0:098463de4c5d	798	#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
group-onsemi	0:098463de4c5d	799	#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
group-onsemi	0:098463de4c5d	800	#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
group-onsemi	0:098463de4c5d	801	#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
group-onsemi	0:098463de4c5d	802	#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
group-onsemi	0:098463de4c5d	803
group-onsemi	0:098463de4c5d	804	#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
group-onsemi	0:098463de4c5d	805	#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
group-onsemi	0:098463de4c5d	806	#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
group-onsemi	0:098463de4c5d	807	#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
group-onsemi	0:098463de4c5d	808	#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
group-onsemi	0:098463de4c5d	809	#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
group-onsemi	0:098463de4c5d	810	#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
group-onsemi	0:098463de4c5d	811	#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
group-onsemi	0:098463de4c5d	812	#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
group-onsemi	0:098463de4c5d	813	#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
group-onsemi	0:098463de4c5d	814	#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
group-onsemi	0:098463de4c5d	815	#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
group-onsemi	0:098463de4c5d	816	#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
group-onsemi	0:098463de4c5d	817	#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
group-onsemi	0:098463de4c5d	818	#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
group-onsemi	0:098463de4c5d	819	#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
group-onsemi	0:098463de4c5d	820	#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
group-onsemi	0:098463de4c5d	821	#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
group-onsemi	0:098463de4c5d	822
group-onsemi	0:098463de4c5d	823	/**
group-onsemi	0:098463de4c5d	824	* @}
group-onsemi	0:098463de4c5d	825	*/
group-onsemi	0:098463de4c5d	826
group-onsemi	0:098463de4c5d	827	/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	828	* @{
group-onsemi	0:098463de4c5d	829	*/
group-onsemi	0:098463de4c5d	830	#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
group-onsemi	0:098463de4c5d	831	#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
group-onsemi	0:098463de4c5d	832	/**
group-onsemi	0:098463de4c5d	833	* @}
group-onsemi	0:098463de4c5d	834	*/
group-onsemi	0:098463de4c5d	835
group-onsemi	0:098463de4c5d	836	/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	837	* @{
group-onsemi	0:098463de4c5d	838	*/
group-onsemi	0:098463de4c5d	839	#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
group-onsemi	0:098463de4c5d	840	#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
group-onsemi	0:098463de4c5d	841	#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
group-onsemi	0:098463de4c5d	842	#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
group-onsemi	0:098463de4c5d	843
group-onsemi	0:098463de4c5d	844	#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
group-onsemi	0:098463de4c5d	845	#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
group-onsemi	0:098463de4c5d	846
group-onsemi	0:098463de4c5d	847	#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
group-onsemi	0:098463de4c5d	848	#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
group-onsemi	0:098463de4c5d	849	#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
group-onsemi	0:098463de4c5d	850	#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
group-onsemi	0:098463de4c5d	851
group-onsemi	0:098463de4c5d	852	#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
group-onsemi	0:098463de4c5d	853	#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
group-onsemi	0:098463de4c5d	854	#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
group-onsemi	0:098463de4c5d	855	#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
group-onsemi	0:098463de4c5d	856
group-onsemi	0:098463de4c5d	857	#define __DIV_LPUART UART_DIV_LPUART
group-onsemi	0:098463de4c5d	858
group-onsemi	0:098463de4c5d	859	#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
group-onsemi	0:098463de4c5d	860	#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
group-onsemi	0:098463de4c5d	861
group-onsemi	0:098463de4c5d	862	/**
group-onsemi	0:098463de4c5d	863	* @}
group-onsemi	0:098463de4c5d	864	*/
group-onsemi	0:098463de4c5d	865
group-onsemi	0:098463de4c5d	866
group-onsemi	0:098463de4c5d	867	/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	868	* @{
group-onsemi	0:098463de4c5d	869	*/
group-onsemi	0:098463de4c5d	870
group-onsemi	0:098463de4c5d	871	#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
group-onsemi	0:098463de4c5d	872	#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
group-onsemi	0:098463de4c5d	873
group-onsemi	0:098463de4c5d	874	#define USARTNACK_ENABLED USART_NACK_ENABLE
group-onsemi	0:098463de4c5d	875	#define USARTNACK_DISABLED USART_NACK_DISABLE
group-onsemi	0:098463de4c5d	876	/**
group-onsemi	0:098463de4c5d	877	* @}
group-onsemi	0:098463de4c5d	878	*/
group-onsemi	0:098463de4c5d	879
group-onsemi	0:098463de4c5d	880	/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	881	* @{
group-onsemi	0:098463de4c5d	882	*/
group-onsemi	0:098463de4c5d	883	#define CFR_BASE WWDG_CFR_BASE
group-onsemi	0:098463de4c5d	884
group-onsemi	0:098463de4c5d	885	/**
group-onsemi	0:098463de4c5d	886	* @}
group-onsemi	0:098463de4c5d	887	*/
group-onsemi	0:098463de4c5d	888
group-onsemi	0:098463de4c5d	889	/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	890	* @{
group-onsemi	0:098463de4c5d	891	*/
group-onsemi	0:098463de4c5d	892	#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
group-onsemi	0:098463de4c5d	893	#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
group-onsemi	0:098463de4c5d	894	#define CAN_IT_RQCP0 CAN_IT_TME
group-onsemi	0:098463de4c5d	895	#define CAN_IT_RQCP1 CAN_IT_TME
group-onsemi	0:098463de4c5d	896	#define CAN_IT_RQCP2 CAN_IT_TME
group-onsemi	0:098463de4c5d	897	#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
group-onsemi	0:098463de4c5d	898	#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
group-onsemi	0:098463de4c5d	899	#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
group-onsemi	0:098463de4c5d	900	#define CAN_TXSTATUS_OK ((uint8_t)0x01U)
group-onsemi	0:098463de4c5d	901	#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
group-onsemi	0:098463de4c5d	902
group-onsemi	0:098463de4c5d	903	/**
group-onsemi	0:098463de4c5d	904	* @}
group-onsemi	0:098463de4c5d	905	*/
group-onsemi	0:098463de4c5d	906
group-onsemi	0:098463de4c5d	907	/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	908	* @{
group-onsemi	0:098463de4c5d	909	*/
group-onsemi	0:098463de4c5d	910
group-onsemi	0:098463de4c5d	911	#define VLAN_TAG ETH_VLAN_TAG
group-onsemi	0:098463de4c5d	912	#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
group-onsemi	0:098463de4c5d	913	#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
group-onsemi	0:098463de4c5d	914	#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
group-onsemi	0:098463de4c5d	915	#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
group-onsemi	0:098463de4c5d	916	#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
group-onsemi	0:098463de4c5d	917	#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
group-onsemi	0:098463de4c5d	918	#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
group-onsemi	0:098463de4c5d	919
group-onsemi	0:098463de4c5d	920	#define ETH_MMCCR ((uint32_t)0x00000100U)
group-onsemi	0:098463de4c5d	921	#define ETH_MMCRIR ((uint32_t)0x00000104U)
group-onsemi	0:098463de4c5d	922	#define ETH_MMCTIR ((uint32_t)0x00000108U)
group-onsemi	0:098463de4c5d	923	#define ETH_MMCRIMR ((uint32_t)0x0000010CU)
group-onsemi	0:098463de4c5d	924	#define ETH_MMCTIMR ((uint32_t)0x00000110U)
group-onsemi	0:098463de4c5d	925	#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU)
group-onsemi	0:098463de4c5d	926	#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U)
group-onsemi	0:098463de4c5d	927	#define ETH_MMCTGFCR ((uint32_t)0x00000168U)
group-onsemi	0:098463de4c5d	928	#define ETH_MMCRFCECR ((uint32_t)0x00000194U)
group-onsemi	0:098463de4c5d	929	#define ETH_MMCRFAECR ((uint32_t)0x00000198U)
group-onsemi	0:098463de4c5d	930	#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U)
group-onsemi	0:098463de4c5d	931
group-onsemi	0:098463de4c5d	932	#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
group-onsemi	0:098463de4c5d	933	#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
group-onsemi	0:098463de4c5d	934	#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
group-onsemi	0:098463de4c5d	935	#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
group-onsemi	0:098463de4c5d	936	#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
group-onsemi	0:098463de4c5d	937	#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
group-onsemi	0:098463de4c5d	938	#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
group-onsemi	0:098463de4c5d	939	#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
group-onsemi	0:098463de4c5d	940	#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
group-onsemi	0:098463de4c5d	941	#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
group-onsemi	0:098463de4c5d	942	#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
group-onsemi	0:098463de4c5d	943	#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
group-onsemi	0:098463de4c5d	944	#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
group-onsemi	0:098463de4c5d	945	#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
group-onsemi	0:098463de4c5d	946	#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
group-onsemi	0:098463de4c5d	947	#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
group-onsemi	0:098463de4c5d	948	#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
group-onsemi	0:098463de4c5d	949	#if defined(STM32F1)
group-onsemi	0:098463de4c5d	950	#else
group-onsemi	0:098463de4c5d	951	#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
group-onsemi	0:098463de4c5d	952	#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
group-onsemi	0:098463de4c5d	953	#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
group-onsemi	0:098463de4c5d	954	#endif
group-onsemi	0:098463de4c5d	955	#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
group-onsemi	0:098463de4c5d	956	#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
group-onsemi	0:098463de4c5d	957	#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
group-onsemi	0:098463de4c5d	958	#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
group-onsemi	0:098463de4c5d	959	#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
group-onsemi	0:098463de4c5d	960	#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
group-onsemi	0:098463de4c5d	961	#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
group-onsemi	0:098463de4c5d	962
group-onsemi	0:098463de4c5d	963	/**
group-onsemi	0:098463de4c5d	964	* @}
group-onsemi	0:098463de4c5d	965	*/
group-onsemi	0:098463de4c5d	966
group-onsemi	0:098463de4c5d	967	/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	968	* @{
group-onsemi	0:098463de4c5d	969	*/
group-onsemi	0:098463de4c5d	970	#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
group-onsemi	0:098463de4c5d	971	#define DCMI_IT_OVF DCMI_IT_OVR
group-onsemi	0:098463de4c5d	972	#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
group-onsemi	0:098463de4c5d	973	#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
group-onsemi	0:098463de4c5d	974
group-onsemi	0:098463de4c5d	975	#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
group-onsemi	0:098463de4c5d	976	#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
group-onsemi	0:098463de4c5d	977	#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
group-onsemi	0:098463de4c5d	978
group-onsemi	0:098463de4c5d	979	/**
group-onsemi	0:098463de4c5d	980	* @}
group-onsemi	0:098463de4c5d	981	*/
group-onsemi	0:098463de4c5d	982
group-onsemi	0:098463de4c5d	983	#if defined(STM32L4xx) \|\| defined(STM32F7) \|\| defined(STM32F427xx) \|\| defined(STM32F437xx) \|\|\
group-onsemi	0:098463de4c5d	984	defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
group-onsemi	0:098463de4c5d	985	/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	986	* @{
group-onsemi	0:098463de4c5d	987	*/
group-onsemi	0:098463de4c5d	988	#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
group-onsemi	0:098463de4c5d	989	#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
group-onsemi	0:098463de4c5d	990	#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
group-onsemi	0:098463de4c5d	991	#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
group-onsemi	0:098463de4c5d	992	#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
group-onsemi	0:098463de4c5d	993
group-onsemi	0:098463de4c5d	994	#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
group-onsemi	0:098463de4c5d	995	#define CM_RGB888 DMA2D_INPUT_RGB888
group-onsemi	0:098463de4c5d	996	#define CM_RGB565 DMA2D_INPUT_RGB565
group-onsemi	0:098463de4c5d	997	#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
group-onsemi	0:098463de4c5d	998	#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
group-onsemi	0:098463de4c5d	999	#define CM_L8 DMA2D_INPUT_L8
group-onsemi	0:098463de4c5d	1000	#define CM_AL44 DMA2D_INPUT_AL44
group-onsemi	0:098463de4c5d	1001	#define CM_AL88 DMA2D_INPUT_AL88
group-onsemi	0:098463de4c5d	1002	#define CM_L4 DMA2D_INPUT_L4
group-onsemi	0:098463de4c5d	1003	#define CM_A8 DMA2D_INPUT_A8
group-onsemi	0:098463de4c5d	1004	#define CM_A4 DMA2D_INPUT_A4
group-onsemi	0:098463de4c5d	1005	/**
group-onsemi	0:098463de4c5d	1006	* @}
group-onsemi	0:098463de4c5d	1007	*/
group-onsemi	0:098463de4c5d	1008	#endif /* STM32L4xx \|\| STM32F7*/
group-onsemi	0:098463de4c5d	1009
group-onsemi	0:098463de4c5d	1010	/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
group-onsemi	0:098463de4c5d	1011	* @{
group-onsemi	0:098463de4c5d	1012	*/
group-onsemi	0:098463de4c5d	1013
group-onsemi	0:098463de4c5d	1014	/**
group-onsemi	0:098463de4c5d	1015	* @}
group-onsemi	0:098463de4c5d	1016	*/
group-onsemi	0:098463de4c5d	1017
group-onsemi	0:098463de4c5d	1018	/* Exported functions --------------------------------------------------------*/
group-onsemi	0:098463de4c5d	1019
group-onsemi	0:098463de4c5d	1020	/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
group-onsemi	0:098463de4c5d	1021	* @{
group-onsemi	0:098463de4c5d	1022	*/
group-onsemi	0:098463de4c5d	1023	#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
group-onsemi	0:098463de4c5d	1024	/**
group-onsemi	0:098463de4c5d	1025	* @}
group-onsemi	0:098463de4c5d	1026	*/
group-onsemi	0:098463de4c5d	1027
group-onsemi	0:098463de4c5d	1028	/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
group-onsemi	0:098463de4c5d	1029	* @{
group-onsemi	0:098463de4c5d	1030	*/
group-onsemi	0:098463de4c5d	1031	#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
group-onsemi	0:098463de4c5d	1032	#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
group-onsemi	0:098463de4c5d	1033	#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
group-onsemi	0:098463de4c5d	1034	#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
group-onsemi	0:098463de4c5d	1035	#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
group-onsemi	0:098463de4c5d	1036	#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
group-onsemi	0:098463de4c5d	1037
group-onsemi	0:098463de4c5d	1038	/HASH Algorithm Selection/
group-onsemi	0:098463de4c5d	1039
group-onsemi	0:098463de4c5d	1040	#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
group-onsemi	0:098463de4c5d	1041	#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
group-onsemi	0:098463de4c5d	1042	#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
group-onsemi	0:098463de4c5d	1043	#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
group-onsemi	0:098463de4c5d	1044
group-onsemi	0:098463de4c5d	1045	#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
group-onsemi	0:098463de4c5d	1046	#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
group-onsemi	0:098463de4c5d	1047
group-onsemi	0:098463de4c5d	1048	#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
group-onsemi	0:098463de4c5d	1049	#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
group-onsemi	0:098463de4c5d	1050	/**
group-onsemi	0:098463de4c5d	1051	* @}
group-onsemi	0:098463de4c5d	1052	*/
group-onsemi	0:098463de4c5d	1053
group-onsemi	0:098463de4c5d	1054	/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
group-onsemi	0:098463de4c5d	1055	* @{
group-onsemi	0:098463de4c5d	1056	*/
group-onsemi	0:098463de4c5d	1057	#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
group-onsemi	0:098463de4c5d	1058	#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
group-onsemi	0:098463de4c5d	1059	#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
group-onsemi	0:098463de4c5d	1060	#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
group-onsemi	0:098463de4c5d	1061	#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
group-onsemi	0:098463de4c5d	1062	#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
group-onsemi	0:098463de4c5d	1063	#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
group-onsemi	0:098463de4c5d	1064	#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
group-onsemi	0:098463de4c5d	1065	#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
group-onsemi	0:098463de4c5d	1066	#if defined(STM32L0)
group-onsemi	0:098463de4c5d	1067	#else
group-onsemi	0:098463de4c5d	1068	#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
group-onsemi	0:098463de4c5d	1069	#endif
group-onsemi	0:098463de4c5d	1070	#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
group-onsemi	0:098463de4c5d	1071	#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
group-onsemi	0:098463de4c5d	1072	/**
group-onsemi	0:098463de4c5d	1073	* @}
group-onsemi	0:098463de4c5d	1074	*/
group-onsemi	0:098463de4c5d	1075
group-onsemi	0:098463de4c5d	1076	/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
group-onsemi	0:098463de4c5d	1077	* @{
group-onsemi	0:098463de4c5d	1078	*/
group-onsemi	0:098463de4c5d	1079	#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
group-onsemi	0:098463de4c5d	1080	#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
group-onsemi	0:098463de4c5d	1081	#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
group-onsemi	0:098463de4c5d	1082	#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
group-onsemi	0:098463de4c5d	1083	#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
group-onsemi	0:098463de4c5d	1084	#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
group-onsemi	0:098463de4c5d	1085	#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
group-onsemi	0:098463de4c5d	1086
group-onsemi	0:098463de4c5d	1087	/**
group-onsemi	0:098463de4c5d	1088	* @}
group-onsemi	0:098463de4c5d	1089	*/
group-onsemi	0:098463de4c5d	1090
group-onsemi	0:098463de4c5d	1091	/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
group-onsemi	0:098463de4c5d	1092	* @{
group-onsemi	0:098463de4c5d	1093	*/
group-onsemi	0:098463de4c5d	1094	#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
group-onsemi	0:098463de4c5d	1095	#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
group-onsemi	0:098463de4c5d	1096	#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
group-onsemi	0:098463de4c5d	1097	#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
group-onsemi	0:098463de4c5d	1098
group-onsemi	0:098463de4c5d	1099	#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
group-onsemi	0:098463de4c5d	1100	/**
group-onsemi	0:098463de4c5d	1101	* @}
group-onsemi	0:098463de4c5d	1102	*/
group-onsemi	0:098463de4c5d	1103
group-onsemi	0:098463de4c5d	1104	/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
group-onsemi	0:098463de4c5d	1105	* @{
group-onsemi	0:098463de4c5d	1106	*/
group-onsemi	0:098463de4c5d	1107	#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
group-onsemi	0:098463de4c5d	1108	#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
group-onsemi	0:098463de4c5d	1109	#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
group-onsemi	0:098463de4c5d	1110	#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
group-onsemi	0:098463de4c5d	1111	#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
group-onsemi	0:098463de4c5d	1112	#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
group-onsemi	0:098463de4c5d	1113	#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
group-onsemi	0:098463de4c5d	1114	#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
group-onsemi	0:098463de4c5d	1115	#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
group-onsemi	0:098463de4c5d	1116	#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
group-onsemi	0:098463de4c5d	1117	#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
group-onsemi	0:098463de4c5d	1118	#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
group-onsemi	0:098463de4c5d	1119	#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
group-onsemi	0:098463de4c5d	1120	#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
group-onsemi	0:098463de4c5d	1121	#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
group-onsemi	0:098463de4c5d	1122	#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
group-onsemi	0:098463de4c5d	1123
group-onsemi	0:098463de4c5d	1124	#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
group-onsemi	0:098463de4c5d	1125	#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
group-onsemi	0:098463de4c5d	1126	#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
group-onsemi	0:098463de4c5d	1127	#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
group-onsemi	0:098463de4c5d	1128	#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
group-onsemi	0:098463de4c5d	1129	#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
group-onsemi	0:098463de4c5d	1130	#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
group-onsemi	0:098463de4c5d	1131
group-onsemi	0:098463de4c5d	1132	#define CR_OFFSET_BB PWR_CR_OFFSET_BB
group-onsemi	0:098463de4c5d	1133	#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
group-onsemi	0:098463de4c5d	1134
group-onsemi	0:098463de4c5d	1135	#define DBP_BitNumber DBP_BIT_NUMBER
group-onsemi	0:098463de4c5d	1136	#define PVDE_BitNumber PVDE_BIT_NUMBER
group-onsemi	0:098463de4c5d	1137	#define PMODE_BitNumber PMODE_BIT_NUMBER
group-onsemi	0:098463de4c5d	1138	#define EWUP_BitNumber EWUP_BIT_NUMBER
group-onsemi	0:098463de4c5d	1139	#define FPDS_BitNumber FPDS_BIT_NUMBER
group-onsemi	0:098463de4c5d	1140	#define ODEN_BitNumber ODEN_BIT_NUMBER
group-onsemi	0:098463de4c5d	1141	#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
group-onsemi	0:098463de4c5d	1142	#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
group-onsemi	0:098463de4c5d	1143	#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
group-onsemi	0:098463de4c5d	1144	#define BRE_BitNumber BRE_BIT_NUMBER
group-onsemi	0:098463de4c5d	1145
group-onsemi	0:098463de4c5d	1146	#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
group-onsemi	0:098463de4c5d	1147
group-onsemi	0:098463de4c5d	1148	/**
group-onsemi	0:098463de4c5d	1149	* @}
group-onsemi	0:098463de4c5d	1150	*/
group-onsemi	0:098463de4c5d	1151
group-onsemi	0:098463de4c5d	1152	/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
group-onsemi	0:098463de4c5d	1153	* @{
group-onsemi	0:098463de4c5d	1154	*/
group-onsemi	0:098463de4c5d	1155	#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
group-onsemi	0:098463de4c5d	1156	#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
group-onsemi	0:098463de4c5d	1157	#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
group-onsemi	0:098463de4c5d	1158	/**
group-onsemi	0:098463de4c5d	1159	* @}
group-onsemi	0:098463de4c5d	1160	*/
group-onsemi	0:098463de4c5d	1161
group-onsemi	0:098463de4c5d	1162	/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
group-onsemi	0:098463de4c5d	1163	* @{
group-onsemi	0:098463de4c5d	1164	*/
group-onsemi	0:098463de4c5d	1165	#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
group-onsemi	0:098463de4c5d	1166	/**
group-onsemi	0:098463de4c5d	1167	* @}
group-onsemi	0:098463de4c5d	1168	*/
group-onsemi	0:098463de4c5d	1169
group-onsemi	0:098463de4c5d	1170	/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
group-onsemi	0:098463de4c5d	1171	* @{
group-onsemi	0:098463de4c5d	1172	*/
group-onsemi	0:098463de4c5d	1173	#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
group-onsemi	0:098463de4c5d	1174	#define HAL_TIM_DMAError TIM_DMAError
group-onsemi	0:098463de4c5d	1175	#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
group-onsemi	0:098463de4c5d	1176	#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
group-onsemi	0:098463de4c5d	1177	/**
group-onsemi	0:098463de4c5d	1178	* @}
group-onsemi	0:098463de4c5d	1179	*/
group-onsemi	0:098463de4c5d	1180
group-onsemi	0:098463de4c5d	1181	/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
group-onsemi	0:098463de4c5d	1182	* @{
group-onsemi	0:098463de4c5d	1183	*/
group-onsemi	0:098463de4c5d	1184	#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
group-onsemi	0:098463de4c5d	1185	/**
group-onsemi	0:098463de4c5d	1186	* @}
group-onsemi	0:098463de4c5d	1187	*/
group-onsemi	0:098463de4c5d	1188
group-onsemi	0:098463de4c5d	1189	/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
group-onsemi	0:098463de4c5d	1190	* @{
group-onsemi	0:098463de4c5d	1191	*/
group-onsemi	0:098463de4c5d	1192	#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
group-onsemi	0:098463de4c5d	1193	/**
group-onsemi	0:098463de4c5d	1194	* @}
group-onsemi	0:098463de4c5d	1195	*/
group-onsemi	0:098463de4c5d	1196
group-onsemi	0:098463de4c5d	1197
group-onsemi	0:098463de4c5d	1198	/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
group-onsemi	0:098463de4c5d	1199	* @{
group-onsemi	0:098463de4c5d	1200	*/
group-onsemi	0:098463de4c5d	1201
group-onsemi	0:098463de4c5d	1202	/**
group-onsemi	0:098463de4c5d	1203	* @}
group-onsemi	0:098463de4c5d	1204	*/
group-onsemi	0:098463de4c5d	1205
group-onsemi	0:098463de4c5d	1206	/* Exported macros ------------------------------------------------------------*/
group-onsemi	0:098463de4c5d	1207
group-onsemi	0:098463de4c5d	1208	/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	1209	* @{
group-onsemi	0:098463de4c5d	1210	*/
group-onsemi	0:098463de4c5d	1211	#define AES_IT_CC CRYP_IT_CC
group-onsemi	0:098463de4c5d	1212	#define AES_IT_ERR CRYP_IT_ERR
group-onsemi	0:098463de4c5d	1213	#define AES_FLAG_CCF CRYP_FLAG_CCF
group-onsemi	0:098463de4c5d	1214	/**
group-onsemi	0:098463de4c5d	1215	* @}
group-onsemi	0:098463de4c5d	1216	*/
group-onsemi	0:098463de4c5d	1217
group-onsemi	0:098463de4c5d	1218	/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	1219	* @{
group-onsemi	0:098463de4c5d	1220	*/
group-onsemi	0:098463de4c5d	1221	#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
group-onsemi	0:098463de4c5d	1222	#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
group-onsemi	0:098463de4c5d	1223	#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
group-onsemi	0:098463de4c5d	1224	#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
group-onsemi	0:098463de4c5d	1225	#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
group-onsemi	0:098463de4c5d	1226	#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
group-onsemi	0:098463de4c5d	1227	#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
group-onsemi	0:098463de4c5d	1228	#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
group-onsemi	0:098463de4c5d	1229	#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
group-onsemi	0:098463de4c5d	1230	#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
group-onsemi	0:098463de4c5d	1231	#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
group-onsemi	0:098463de4c5d	1232	#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
group-onsemi	0:098463de4c5d	1233	#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
group-onsemi	0:098463de4c5d	1234
group-onsemi	0:098463de4c5d	1235	#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
group-onsemi	0:098463de4c5d	1236	#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
group-onsemi	0:098463de4c5d	1237	#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
group-onsemi	0:098463de4c5d	1238	#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
group-onsemi	0:098463de4c5d	1239	#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
group-onsemi	0:098463de4c5d	1240
group-onsemi	0:098463de4c5d	1241	/**
group-onsemi	0:098463de4c5d	1242	* @}
group-onsemi	0:098463de4c5d	1243	*/
group-onsemi	0:098463de4c5d	1244
group-onsemi	0:098463de4c5d	1245
group-onsemi	0:098463de4c5d	1246	/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	1247	* @{
group-onsemi	0:098463de4c5d	1248	*/
group-onsemi	0:098463de4c5d	1249	#define __ADC_ENABLE __HAL_ADC_ENABLE
group-onsemi	0:098463de4c5d	1250	#define __ADC_DISABLE __HAL_ADC_DISABLE
group-onsemi	0:098463de4c5d	1251	#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
group-onsemi	0:098463de4c5d	1252	#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
group-onsemi	0:098463de4c5d	1253	#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
group-onsemi	0:098463de4c5d	1254	#define __ADC_IS_ENABLED ADC_IS_ENABLE
group-onsemi	0:098463de4c5d	1255	#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
group-onsemi	0:098463de4c5d	1256	#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
group-onsemi	0:098463de4c5d	1257	#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
group-onsemi	0:098463de4c5d	1258	#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
group-onsemi	0:098463de4c5d	1259	#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
group-onsemi	0:098463de4c5d	1260	#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
group-onsemi	0:098463de4c5d	1261	#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
group-onsemi	0:098463de4c5d	1262
group-onsemi	0:098463de4c5d	1263	#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
group-onsemi	0:098463de4c5d	1264	#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
group-onsemi	0:098463de4c5d	1265	#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
group-onsemi	0:098463de4c5d	1266	#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
group-onsemi	0:098463de4c5d	1267	#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
group-onsemi	0:098463de4c5d	1268	#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
group-onsemi	0:098463de4c5d	1269	#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
group-onsemi	0:098463de4c5d	1270	#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
group-onsemi	0:098463de4c5d	1271	#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
group-onsemi	0:098463de4c5d	1272	#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
group-onsemi	0:098463de4c5d	1273	#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
group-onsemi	0:098463de4c5d	1274	#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
group-onsemi	0:098463de4c5d	1275	#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
group-onsemi	0:098463de4c5d	1276	#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
group-onsemi	0:098463de4c5d	1277	#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
group-onsemi	0:098463de4c5d	1278	#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
group-onsemi	0:098463de4c5d	1279	#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
group-onsemi	0:098463de4c5d	1280	#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
group-onsemi	0:098463de4c5d	1281	#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
group-onsemi	0:098463de4c5d	1282	#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
group-onsemi	0:098463de4c5d	1283
group-onsemi	0:098463de4c5d	1284	#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
group-onsemi	0:098463de4c5d	1285	#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
group-onsemi	0:098463de4c5d	1286	#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
group-onsemi	0:098463de4c5d	1287	#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
group-onsemi	0:098463de4c5d	1288	#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
group-onsemi	0:098463de4c5d	1289	#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
group-onsemi	0:098463de4c5d	1290	#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
group-onsemi	0:098463de4c5d	1291	#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
group-onsemi	0:098463de4c5d	1292	#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
group-onsemi	0:098463de4c5d	1293	#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
group-onsemi	0:098463de4c5d	1294
group-onsemi	0:098463de4c5d	1295	#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
group-onsemi	0:098463de4c5d	1296	#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
group-onsemi	0:098463de4c5d	1297	#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
group-onsemi	0:098463de4c5d	1298	#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
group-onsemi	0:098463de4c5d	1299	#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
group-onsemi	0:098463de4c5d	1300	#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
group-onsemi	0:098463de4c5d	1301	#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
group-onsemi	0:098463de4c5d	1302	#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
group-onsemi	0:098463de4c5d	1303
group-onsemi	0:098463de4c5d	1304	#define __HAL_ADC_SQR1 ADC_SQR1
group-onsemi	0:098463de4c5d	1305	#define __HAL_ADC_SMPR1 ADC_SMPR1
group-onsemi	0:098463de4c5d	1306	#define __HAL_ADC_SMPR2 ADC_SMPR2
group-onsemi	0:098463de4c5d	1307	#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
group-onsemi	0:098463de4c5d	1308	#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
group-onsemi	0:098463de4c5d	1309	#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
group-onsemi	0:098463de4c5d	1310	#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
group-onsemi	0:098463de4c5d	1311	#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
group-onsemi	0:098463de4c5d	1312	#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
group-onsemi	0:098463de4c5d	1313	#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
group-onsemi	0:098463de4c5d	1314	#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
group-onsemi	0:098463de4c5d	1315	#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
group-onsemi	0:098463de4c5d	1316	#define __HAL_ADC_JSQR ADC_JSQR
group-onsemi	0:098463de4c5d	1317
group-onsemi	0:098463de4c5d	1318	#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
group-onsemi	0:098463de4c5d	1319	#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
group-onsemi	0:098463de4c5d	1320	#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
group-onsemi	0:098463de4c5d	1321	#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
group-onsemi	0:098463de4c5d	1322	#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
group-onsemi	0:098463de4c5d	1323	#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
group-onsemi	0:098463de4c5d	1324	#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
group-onsemi	0:098463de4c5d	1325	#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
group-onsemi	0:098463de4c5d	1326
group-onsemi	0:098463de4c5d	1327	/**
group-onsemi	0:098463de4c5d	1328	* @}
group-onsemi	0:098463de4c5d	1329	*/
group-onsemi	0:098463de4c5d	1330
group-onsemi	0:098463de4c5d	1331	/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	1332	* @{
group-onsemi	0:098463de4c5d	1333	*/
group-onsemi	0:098463de4c5d	1334	#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
group-onsemi	0:098463de4c5d	1335	#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
group-onsemi	0:098463de4c5d	1336	#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
group-onsemi	0:098463de4c5d	1337	#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
group-onsemi	0:098463de4c5d	1338
group-onsemi	0:098463de4c5d	1339	/**
group-onsemi	0:098463de4c5d	1340	* @}
group-onsemi	0:098463de4c5d	1341	*/
group-onsemi	0:098463de4c5d	1342
group-onsemi	0:098463de4c5d	1343	/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	1344	* @{
group-onsemi	0:098463de4c5d	1345	*/
group-onsemi	0:098463de4c5d	1346	#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
group-onsemi	0:098463de4c5d	1347	#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
group-onsemi	0:098463de4c5d	1348	#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
group-onsemi	0:098463de4c5d	1349	#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
group-onsemi	0:098463de4c5d	1350	#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
group-onsemi	0:098463de4c5d	1351	#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
group-onsemi	0:098463de4c5d	1352	#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
group-onsemi	0:098463de4c5d	1353	#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
group-onsemi	0:098463de4c5d	1354	#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
group-onsemi	0:098463de4c5d	1355	#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
group-onsemi	0:098463de4c5d	1356	#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
group-onsemi	0:098463de4c5d	1357	#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
group-onsemi	0:098463de4c5d	1358	#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
group-onsemi	0:098463de4c5d	1359	#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
group-onsemi	0:098463de4c5d	1360	#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
group-onsemi	0:098463de4c5d	1361	#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
group-onsemi	0:098463de4c5d	1362
group-onsemi	0:098463de4c5d	1363	#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
group-onsemi	0:098463de4c5d	1364	#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
group-onsemi	0:098463de4c5d	1365	#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
group-onsemi	0:098463de4c5d	1366	#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
group-onsemi	0:098463de4c5d	1367	#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
group-onsemi	0:098463de4c5d	1368	#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
group-onsemi	0:098463de4c5d	1369	#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
group-onsemi	0:098463de4c5d	1370	#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
group-onsemi	0:098463de4c5d	1371	#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
group-onsemi	0:098463de4c5d	1372	#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
group-onsemi	0:098463de4c5d	1373	#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
group-onsemi	0:098463de4c5d	1374	#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
group-onsemi	0:098463de4c5d	1375	#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
group-onsemi	0:098463de4c5d	1376	#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
group-onsemi	0:098463de4c5d	1377
group-onsemi	0:098463de4c5d	1378
group-onsemi	0:098463de4c5d	1379	#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
group-onsemi	0:098463de4c5d	1380	#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
group-onsemi	0:098463de4c5d	1381	#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
group-onsemi	0:098463de4c5d	1382	#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
group-onsemi	0:098463de4c5d	1383	#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
group-onsemi	0:098463de4c5d	1384	#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
group-onsemi	0:098463de4c5d	1385	#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
group-onsemi	0:098463de4c5d	1386	#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
group-onsemi	0:098463de4c5d	1387	#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
group-onsemi	0:098463de4c5d	1388	#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
group-onsemi	0:098463de4c5d	1389	#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
group-onsemi	0:098463de4c5d	1390	#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
group-onsemi	0:098463de4c5d	1391	#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
group-onsemi	0:098463de4c5d	1392	#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
group-onsemi	0:098463de4c5d	1393	#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
group-onsemi	0:098463de4c5d	1394	#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
group-onsemi	0:098463de4c5d	1395	#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
group-onsemi	0:098463de4c5d	1396	#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
group-onsemi	0:098463de4c5d	1397	#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
group-onsemi	0:098463de4c5d	1398	#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
group-onsemi	0:098463de4c5d	1399	#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
group-onsemi	0:098463de4c5d	1400	#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
group-onsemi	0:098463de4c5d	1401	#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
group-onsemi	0:098463de4c5d	1402	#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
group-onsemi	0:098463de4c5d	1403
group-onsemi	0:098463de4c5d	1404	/**
group-onsemi	0:098463de4c5d	1405	* @}
group-onsemi	0:098463de4c5d	1406	*/
group-onsemi	0:098463de4c5d	1407
group-onsemi	0:098463de4c5d	1408	/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	1409	* @{
group-onsemi	0:098463de4c5d	1410	*/
group-onsemi	0:098463de4c5d	1411	#if defined(STM32F3)
group-onsemi	0:098463de4c5d	1412	#define COMP_START __HAL_COMP_ENABLE
group-onsemi	0:098463de4c5d	1413	#define COMP_STOP __HAL_COMP_DISABLE
group-onsemi	0:098463de4c5d	1414	#define COMP_LOCK __HAL_COMP_LOCK
group-onsemi	0:098463de4c5d	1415
group-onsemi	0:098463de4c5d	1416	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
group-onsemi	0:098463de4c5d	1417	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
group-onsemi	0:098463de4c5d	1418	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
group-onsemi	0:098463de4c5d	1419	__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
group-onsemi	0:098463de4c5d	1420	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
group-onsemi	0:098463de4c5d	1421	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
group-onsemi	0:098463de4c5d	1422	__HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
group-onsemi	0:098463de4c5d	1423	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
group-onsemi	0:098463de4c5d	1424	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
group-onsemi	0:098463de4c5d	1425	__HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
group-onsemi	0:098463de4c5d	1426	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
group-onsemi	0:098463de4c5d	1427	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
group-onsemi	0:098463de4c5d	1428	__HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
group-onsemi	0:098463de4c5d	1429	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
group-onsemi	0:098463de4c5d	1430	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
group-onsemi	0:098463de4c5d	1431	__HAL_COMP_COMP6_EXTI_ENABLE_IT())
group-onsemi	0:098463de4c5d	1432	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
group-onsemi	0:098463de4c5d	1433	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
group-onsemi	0:098463de4c5d	1434	__HAL_COMP_COMP6_EXTI_DISABLE_IT())
group-onsemi	0:098463de4c5d	1435	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
group-onsemi	0:098463de4c5d	1436	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
group-onsemi	0:098463de4c5d	1437	__HAL_COMP_COMP6_EXTI_GET_FLAG())
group-onsemi	0:098463de4c5d	1438	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
group-onsemi	0:098463de4c5d	1439	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
group-onsemi	0:098463de4c5d	1440	__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
group-onsemi	0:098463de4c5d	1441	# endif
group-onsemi	0:098463de4c5d	1442	# if defined(STM32F302xE) \|\| defined(STM32F302xC)
group-onsemi	0:098463de4c5d	1443	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
group-onsemi	0:098463de4c5d	1444	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
group-onsemi	0:098463de4c5d	1445	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
group-onsemi	0:098463de4c5d	1446	__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
group-onsemi	0:098463de4c5d	1447	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
group-onsemi	0:098463de4c5d	1448	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
group-onsemi	0:098463de4c5d	1449	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
group-onsemi	0:098463de4c5d	1450	__HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
group-onsemi	0:098463de4c5d	1451	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
group-onsemi	0:098463de4c5d	1452	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
group-onsemi	0:098463de4c5d	1453	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
group-onsemi	0:098463de4c5d	1454	__HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
group-onsemi	0:098463de4c5d	1455	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
group-onsemi	0:098463de4c5d	1456	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
group-onsemi	0:098463de4c5d	1457	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
group-onsemi	0:098463de4c5d	1458	__HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
group-onsemi	0:098463de4c5d	1459	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
group-onsemi	0:098463de4c5d	1460	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
group-onsemi	0:098463de4c5d	1461	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
group-onsemi	0:098463de4c5d	1462	__HAL_COMP_COMP6_EXTI_ENABLE_IT())
group-onsemi	0:098463de4c5d	1463	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
group-onsemi	0:098463de4c5d	1464	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
group-onsemi	0:098463de4c5d	1465	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
group-onsemi	0:098463de4c5d	1466	__HAL_COMP_COMP6_EXTI_DISABLE_IT())
group-onsemi	0:098463de4c5d	1467	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
group-onsemi	0:098463de4c5d	1468	((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
group-onsemi	0:098463de4c5d	1469	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
group-onsemi	0:098463de4c5d	1470	__HAL_COMP_COMP6_EXTI_GET_FLAG())
group-onsemi	0:098463de4c5d	1471	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
group-onsemi	0:098463de4c5d	1472	((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
group-onsemi	0:098463de4c5d	1473	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
group-onsemi	0:098463de4c5d	1474	__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
group-onsemi	0:098463de4c5d	1475	# endif
group-onsemi	0:098463de4c5d	1476	# if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
group-onsemi	0:098463de4c5d	1477	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
group-onsemi	0:098463de4c5d	1478	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
group-onsemi	0:098463de4c5d	1479	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
group-onsemi	0:098463de4c5d	1480	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
group-onsemi	0:098463de4c5d	1481	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
group-onsemi	0:098463de4c5d	1482	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
group-onsemi	0:098463de4c5d	1483	__HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
group-onsemi	0:098463de4c5d	1484	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
group-onsemi	0:098463de4c5d	1485	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
group-onsemi	0:098463de4c5d	1486	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
group-onsemi	0:098463de4c5d	1487	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
group-onsemi	0:098463de4c5d	1488	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
group-onsemi	0:098463de4c5d	1489	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
group-onsemi	0:098463de4c5d	1490	__HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
group-onsemi	0:098463de4c5d	1491	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
group-onsemi	0:098463de4c5d	1492	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
group-onsemi	0:098463de4c5d	1493	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
group-onsemi	0:098463de4c5d	1494	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
group-onsemi	0:098463de4c5d	1495	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
group-onsemi	0:098463de4c5d	1496	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
group-onsemi	0:098463de4c5d	1497	__HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
group-onsemi	0:098463de4c5d	1498	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
group-onsemi	0:098463de4c5d	1499	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
group-onsemi	0:098463de4c5d	1500	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
group-onsemi	0:098463de4c5d	1501	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
group-onsemi	0:098463de4c5d	1502	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
group-onsemi	0:098463de4c5d	1503	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
group-onsemi	0:098463de4c5d	1504	__HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
group-onsemi	0:098463de4c5d	1505	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
group-onsemi	0:098463de4c5d	1506	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
group-onsemi	0:098463de4c5d	1507	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
group-onsemi	0:098463de4c5d	1508	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
group-onsemi	0:098463de4c5d	1509	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
group-onsemi	0:098463de4c5d	1510	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
group-onsemi	0:098463de4c5d	1511	__HAL_COMP_COMP7_EXTI_ENABLE_IT())
group-onsemi	0:098463de4c5d	1512	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
group-onsemi	0:098463de4c5d	1513	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
group-onsemi	0:098463de4c5d	1514	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
group-onsemi	0:098463de4c5d	1515	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
group-onsemi	0:098463de4c5d	1516	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
group-onsemi	0:098463de4c5d	1517	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
group-onsemi	0:098463de4c5d	1518	__HAL_COMP_COMP7_EXTI_DISABLE_IT())
group-onsemi	0:098463de4c5d	1519	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
group-onsemi	0:098463de4c5d	1520	((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
group-onsemi	0:098463de4c5d	1521	((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
group-onsemi	0:098463de4c5d	1522	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
group-onsemi	0:098463de4c5d	1523	((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
group-onsemi	0:098463de4c5d	1524	((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
group-onsemi	0:098463de4c5d	1525	__HAL_COMP_COMP7_EXTI_GET_FLAG())
group-onsemi	0:098463de4c5d	1526	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
group-onsemi	0:098463de4c5d	1527	((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
group-onsemi	0:098463de4c5d	1528	((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
group-onsemi	0:098463de4c5d	1529	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
group-onsemi	0:098463de4c5d	1530	((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
group-onsemi	0:098463de4c5d	1531	((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
group-onsemi	0:098463de4c5d	1532	__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
group-onsemi	0:098463de4c5d	1533	# endif
group-onsemi	0:098463de4c5d	1534	# if defined(STM32F373xC) \|\|defined(STM32F378xx)
group-onsemi	0:098463de4c5d	1535	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
group-onsemi	0:098463de4c5d	1536	__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
group-onsemi	0:098463de4c5d	1537	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
group-onsemi	0:098463de4c5d	1538	__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
group-onsemi	0:098463de4c5d	1539	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
group-onsemi	0:098463de4c5d	1540	__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
group-onsemi	0:098463de4c5d	1541	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
group-onsemi	0:098463de4c5d	1542	__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
group-onsemi	0:098463de4c5d	1543	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
group-onsemi	0:098463de4c5d	1544	__HAL_COMP_COMP2_EXTI_ENABLE_IT())
group-onsemi	0:098463de4c5d	1545	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
group-onsemi	0:098463de4c5d	1546	__HAL_COMP_COMP2_EXTI_DISABLE_IT())
group-onsemi	0:098463de4c5d	1547	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
group-onsemi	0:098463de4c5d	1548	__HAL_COMP_COMP2_EXTI_GET_FLAG())
group-onsemi	0:098463de4c5d	1549	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
group-onsemi	0:098463de4c5d	1550	__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
group-onsemi	0:098463de4c5d	1551	# endif
group-onsemi	0:098463de4c5d	1552	#else
group-onsemi	0:098463de4c5d	1553	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
group-onsemi	0:098463de4c5d	1554	__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
group-onsemi	0:098463de4c5d	1555	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
group-onsemi	0:098463de4c5d	1556	__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
group-onsemi	0:098463de4c5d	1557	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
group-onsemi	0:098463de4c5d	1558	__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
group-onsemi	0:098463de4c5d	1559	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
group-onsemi	0:098463de4c5d	1560	__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
group-onsemi	0:098463de4c5d	1561	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
group-onsemi	0:098463de4c5d	1562	__HAL_COMP_COMP2_EXTI_ENABLE_IT())
group-onsemi	0:098463de4c5d	1563	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
group-onsemi	0:098463de4c5d	1564	__HAL_COMP_COMP2_EXTI_DISABLE_IT())
group-onsemi	0:098463de4c5d	1565	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
group-onsemi	0:098463de4c5d	1566	__HAL_COMP_COMP2_EXTI_GET_FLAG())
group-onsemi	0:098463de4c5d	1567	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
group-onsemi	0:098463de4c5d	1568	__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
group-onsemi	0:098463de4c5d	1569	#endif
group-onsemi	0:098463de4c5d	1570
group-onsemi	0:098463de4c5d	1571	#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
group-onsemi	0:098463de4c5d	1572
group-onsemi	0:098463de4c5d	1573	#if defined(STM32L0) \|\| defined(STM32L4)
group-onsemi	0:098463de4c5d	1574	/* Note: On these STM32 families, the only argument of this macro */
group-onsemi	0:098463de4c5d	1575	/* is COMP_FLAG_LOCK. */
group-onsemi	0:098463de4c5d	1576	/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
group-onsemi	0:098463de4c5d	1577	/* argument. */
group-onsemi	0:098463de4c5d	1578	#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
group-onsemi	0:098463de4c5d	1579	#endif
group-onsemi	0:098463de4c5d	1580	/**
group-onsemi	0:098463de4c5d	1581	* @}
group-onsemi	0:098463de4c5d	1582	*/
group-onsemi	0:098463de4c5d	1583
group-onsemi	0:098463de4c5d	1584	#if defined(STM32L0) \|\| defined(STM32L4)
group-onsemi	0:098463de4c5d	1585	/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
group-onsemi	0:098463de4c5d	1586	* @{
group-onsemi	0:098463de4c5d	1587	*/
group-onsemi	0:098463de4c5d	1588	#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
group-onsemi	0:098463de4c5d	1589	#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
group-onsemi	0:098463de4c5d	1590	/**
group-onsemi	0:098463de4c5d	1591	* @}
group-onsemi	0:098463de4c5d	1592	*/
group-onsemi	0:098463de4c5d	1593	#endif
group-onsemi	0:098463de4c5d	1594
group-onsemi	0:098463de4c5d	1595	/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	1596	* @{
group-onsemi	0:098463de4c5d	1597	*/
group-onsemi	0:098463de4c5d	1598
group-onsemi	0:098463de4c5d	1599	#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) \|\| \
group-onsemi	0:098463de4c5d	1600	((WAVE) == DAC_WAVE_NOISE)\|\| \
group-onsemi	0:098463de4c5d	1601	((WAVE) == DAC_WAVE_TRIANGLE))
group-onsemi	0:098463de4c5d	1602
group-onsemi	0:098463de4c5d	1603	/**
group-onsemi	0:098463de4c5d	1604	* @}
group-onsemi	0:098463de4c5d	1605	*/
group-onsemi	0:098463de4c5d	1606
group-onsemi	0:098463de4c5d	1607	/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	1608	* @{
group-onsemi	0:098463de4c5d	1609	*/
group-onsemi	0:098463de4c5d	1610
group-onsemi	0:098463de4c5d	1611	#define IS_WRPAREA IS_OB_WRPAREA
group-onsemi	0:098463de4c5d	1612	#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
group-onsemi	0:098463de4c5d	1613	#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
group-onsemi	0:098463de4c5d	1614	#define IS_TYPEERASE IS_FLASH_TYPEERASE
group-onsemi	0:098463de4c5d	1615	#define IS_NBSECTORS IS_FLASH_NBSECTORS
group-onsemi	0:098463de4c5d	1616	#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
group-onsemi	0:098463de4c5d	1617
group-onsemi	0:098463de4c5d	1618	/**
group-onsemi	0:098463de4c5d	1619	* @}
group-onsemi	0:098463de4c5d	1620	*/
group-onsemi	0:098463de4c5d	1621
group-onsemi	0:098463de4c5d	1622	/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	1623	* @{
group-onsemi	0:098463de4c5d	1624	*/
group-onsemi	0:098463de4c5d	1625
group-onsemi	0:098463de4c5d	1626	#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
group-onsemi	0:098463de4c5d	1627	#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
group-onsemi	0:098463de4c5d	1628	#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
group-onsemi	0:098463de4c5d	1629	#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
group-onsemi	0:098463de4c5d	1630	#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
group-onsemi	0:098463de4c5d	1631	#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
group-onsemi	0:098463de4c5d	1632	#define __HAL_I2C_SPEED I2C_SPEED
group-onsemi	0:098463de4c5d	1633	#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
group-onsemi	0:098463de4c5d	1634	#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
group-onsemi	0:098463de4c5d	1635	#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
group-onsemi	0:098463de4c5d	1636	#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
group-onsemi	0:098463de4c5d	1637	#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
group-onsemi	0:098463de4c5d	1638	#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
group-onsemi	0:098463de4c5d	1639	#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
group-onsemi	0:098463de4c5d	1640	#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
group-onsemi	0:098463de4c5d	1641	/**
group-onsemi	0:098463de4c5d	1642	* @}
group-onsemi	0:098463de4c5d	1643	*/
group-onsemi	0:098463de4c5d	1644
group-onsemi	0:098463de4c5d	1645	/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	1646	* @{
group-onsemi	0:098463de4c5d	1647	*/
group-onsemi	0:098463de4c5d	1648
group-onsemi	0:098463de4c5d	1649	#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
group-onsemi	0:098463de4c5d	1650	#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
group-onsemi	0:098463de4c5d	1651
group-onsemi	0:098463de4c5d	1652	/**
group-onsemi	0:098463de4c5d	1653	* @}
group-onsemi	0:098463de4c5d	1654	*/
group-onsemi	0:098463de4c5d	1655
group-onsemi	0:098463de4c5d	1656	/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	1657	* @{
group-onsemi	0:098463de4c5d	1658	*/
group-onsemi	0:098463de4c5d	1659
group-onsemi	0:098463de4c5d	1660	#define __IRDA_DISABLE __HAL_IRDA_DISABLE
group-onsemi	0:098463de4c5d	1661	#define __IRDA_ENABLE __HAL_IRDA_ENABLE
group-onsemi	0:098463de4c5d	1662
group-onsemi	0:098463de4c5d	1663	#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
group-onsemi	0:098463de4c5d	1664	#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
group-onsemi	0:098463de4c5d	1665	#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
group-onsemi	0:098463de4c5d	1666	#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
group-onsemi	0:098463de4c5d	1667
group-onsemi	0:098463de4c5d	1668	#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
group-onsemi	0:098463de4c5d	1669
group-onsemi	0:098463de4c5d	1670
group-onsemi	0:098463de4c5d	1671	/**
group-onsemi	0:098463de4c5d	1672	* @}
group-onsemi	0:098463de4c5d	1673	*/
group-onsemi	0:098463de4c5d	1674
group-onsemi	0:098463de4c5d	1675
group-onsemi	0:098463de4c5d	1676	/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	1677	* @{
group-onsemi	0:098463de4c5d	1678	*/
group-onsemi	0:098463de4c5d	1679	#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
group-onsemi	0:098463de4c5d	1680	#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
group-onsemi	0:098463de4c5d	1681	/**
group-onsemi	0:098463de4c5d	1682	* @}
group-onsemi	0:098463de4c5d	1683	*/
group-onsemi	0:098463de4c5d	1684
group-onsemi	0:098463de4c5d	1685
group-onsemi	0:098463de4c5d	1686	/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	1687	* @{
group-onsemi	0:098463de4c5d	1688	*/
group-onsemi	0:098463de4c5d	1689
group-onsemi	0:098463de4c5d	1690	#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
group-onsemi	0:098463de4c5d	1691	#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
group-onsemi	0:098463de4c5d	1692	#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
group-onsemi	0:098463de4c5d	1693
group-onsemi	0:098463de4c5d	1694	/**
group-onsemi	0:098463de4c5d	1695	* @}
group-onsemi	0:098463de4c5d	1696	*/
group-onsemi	0:098463de4c5d	1697
group-onsemi	0:098463de4c5d	1698
group-onsemi	0:098463de4c5d	1699	/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	1700	* @{
group-onsemi	0:098463de4c5d	1701	*/
group-onsemi	0:098463de4c5d	1702	#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
group-onsemi	0:098463de4c5d	1703	#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
group-onsemi	0:098463de4c5d	1704	#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
group-onsemi	0:098463de4c5d	1705	#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
group-onsemi	0:098463de4c5d	1706	#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
group-onsemi	0:098463de4c5d	1707	#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
group-onsemi	0:098463de4c5d	1708	#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
group-onsemi	0:098463de4c5d	1709	#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
group-onsemi	0:098463de4c5d	1710	#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
group-onsemi	0:098463de4c5d	1711	#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
group-onsemi	0:098463de4c5d	1712	#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
group-onsemi	0:098463de4c5d	1713	#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
group-onsemi	0:098463de4c5d	1714	#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
group-onsemi	0:098463de4c5d	1715
group-onsemi	0:098463de4c5d	1716	/**
group-onsemi	0:098463de4c5d	1717	* @}
group-onsemi	0:098463de4c5d	1718	*/
group-onsemi	0:098463de4c5d	1719
group-onsemi	0:098463de4c5d	1720
group-onsemi	0:098463de4c5d	1721	/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	1722	* @{
group-onsemi	0:098463de4c5d	1723	*/
group-onsemi	0:098463de4c5d	1724	#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
group-onsemi	0:098463de4c5d	1725	#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
group-onsemi	0:098463de4c5d	1726	#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
group-onsemi	0:098463de4c5d	1727	#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
group-onsemi	0:098463de4c5d	1728	#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
group-onsemi	0:098463de4c5d	1729	#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
group-onsemi	0:098463de4c5d	1730	#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
group-onsemi	0:098463de4c5d	1731	#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
group-onsemi	0:098463de4c5d	1732	#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
group-onsemi	0:098463de4c5d	1733	#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
group-onsemi	0:098463de4c5d	1734	#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
group-onsemi	0:098463de4c5d	1735	#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
group-onsemi	0:098463de4c5d	1736	#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
group-onsemi	0:098463de4c5d	1737	#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
group-onsemi	0:098463de4c5d	1738	#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
group-onsemi	0:098463de4c5d	1739	#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
group-onsemi	0:098463de4c5d	1740	#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
group-onsemi	0:098463de4c5d	1741	#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
group-onsemi	0:098463de4c5d	1742	#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
group-onsemi	0:098463de4c5d	1743	#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
group-onsemi	0:098463de4c5d	1744	#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
group-onsemi	0:098463de4c5d	1745	#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
group-onsemi	0:098463de4c5d	1746	#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
group-onsemi	0:098463de4c5d	1747	#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
group-onsemi	0:098463de4c5d	1748	#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
group-onsemi	0:098463de4c5d	1749	#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
group-onsemi	0:098463de4c5d	1750	#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
group-onsemi	0:098463de4c5d	1751	#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
group-onsemi	0:098463de4c5d	1752	#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
group-onsemi	0:098463de4c5d	1753	#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
group-onsemi	0:098463de4c5d	1754	#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
group-onsemi	0:098463de4c5d	1755	#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
group-onsemi	0:098463de4c5d	1756	#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
group-onsemi	0:098463de4c5d	1757	#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
group-onsemi	0:098463de4c5d	1758	#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
group-onsemi	0:098463de4c5d	1759
group-onsemi	0:098463de4c5d	1760	#if defined (STM32F4)
group-onsemi	0:098463de4c5d	1761	#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
group-onsemi	0:098463de4c5d	1762	#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
group-onsemi	0:098463de4c5d	1763	#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
group-onsemi	0:098463de4c5d	1764	#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
group-onsemi	0:098463de4c5d	1765	#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
group-onsemi	0:098463de4c5d	1766	#else
group-onsemi	0:098463de4c5d	1767	#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
group-onsemi	0:098463de4c5d	1768	#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
group-onsemi	0:098463de4c5d	1769	#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
group-onsemi	0:098463de4c5d	1770	#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
group-onsemi	0:098463de4c5d	1771	#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
group-onsemi	0:098463de4c5d	1772	#endif /* STM32F4 */
group-onsemi	0:098463de4c5d	1773	/**
group-onsemi	0:098463de4c5d	1774	* @}
group-onsemi	0:098463de4c5d	1775	*/
group-onsemi	0:098463de4c5d	1776
group-onsemi	0:098463de4c5d	1777
group-onsemi	0:098463de4c5d	1778	/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
group-onsemi	0:098463de4c5d	1779	* @{
group-onsemi	0:098463de4c5d	1780	*/
group-onsemi	0:098463de4c5d	1781
group-onsemi	0:098463de4c5d	1782	#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
group-onsemi	0:098463de4c5d	1783	#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
group-onsemi	0:098463de4c5d	1784
group-onsemi	0:098463de4c5d	1785	#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
group-onsemi	0:098463de4c5d	1786	#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
group-onsemi	0:098463de4c5d	1787
group-onsemi	0:098463de4c5d	1788	#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
group-onsemi	0:098463de4c5d	1789	#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
group-onsemi	0:098463de4c5d	1790	#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	1791	#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	1792	#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
group-onsemi	0:098463de4c5d	1793	#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
group-onsemi	0:098463de4c5d	1794	#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
group-onsemi	0:098463de4c5d	1795	#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
group-onsemi	0:098463de4c5d	1796	#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
group-onsemi	0:098463de4c5d	1797	#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
group-onsemi	0:098463de4c5d	1798	#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	1799	#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	1800	#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
group-onsemi	0:098463de4c5d	1801	#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
group-onsemi	0:098463de4c5d	1802	#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
group-onsemi	0:098463de4c5d	1803	#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
group-onsemi	0:098463de4c5d	1804	#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
group-onsemi	0:098463de4c5d	1805	#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
group-onsemi	0:098463de4c5d	1806	#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
group-onsemi	0:098463de4c5d	1807	#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
group-onsemi	0:098463de4c5d	1808	#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
group-onsemi	0:098463de4c5d	1809	#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
group-onsemi	0:098463de4c5d	1810	#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	1811	#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	1812	#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
group-onsemi	0:098463de4c5d	1813	#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
group-onsemi	0:098463de4c5d	1814	#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	1815	#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	1816	#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
group-onsemi	0:098463de4c5d	1817	#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
group-onsemi	0:098463de4c5d	1818	#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
group-onsemi	0:098463de4c5d	1819	#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
group-onsemi	0:098463de4c5d	1820	#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
group-onsemi	0:098463de4c5d	1821	#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
group-onsemi	0:098463de4c5d	1822	#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
group-onsemi	0:098463de4c5d	1823	#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
group-onsemi	0:098463de4c5d	1824	#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
group-onsemi	0:098463de4c5d	1825	#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
group-onsemi	0:098463de4c5d	1826	#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
group-onsemi	0:098463de4c5d	1827	#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
group-onsemi	0:098463de4c5d	1828	#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
group-onsemi	0:098463de4c5d	1829	#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
group-onsemi	0:098463de4c5d	1830	#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
group-onsemi	0:098463de4c5d	1831	#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
group-onsemi	0:098463de4c5d	1832	#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
group-onsemi	0:098463de4c5d	1833	#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
group-onsemi	0:098463de4c5d	1834	#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
group-onsemi	0:098463de4c5d	1835	#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
group-onsemi	0:098463de4c5d	1836	#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
group-onsemi	0:098463de4c5d	1837	#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
group-onsemi	0:098463de4c5d	1838	#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
group-onsemi	0:098463de4c5d	1839	#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
group-onsemi	0:098463de4c5d	1840	#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
group-onsemi	0:098463de4c5d	1841	#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
group-onsemi	0:098463de4c5d	1842	#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	1843	#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	1844	#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
group-onsemi	0:098463de4c5d	1845	#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
group-onsemi	0:098463de4c5d	1846	#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
group-onsemi	0:098463de4c5d	1847	#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
group-onsemi	0:098463de4c5d	1848	#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
group-onsemi	0:098463de4c5d	1849	#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
group-onsemi	0:098463de4c5d	1850	#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
group-onsemi	0:098463de4c5d	1851	#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
group-onsemi	0:098463de4c5d	1852	#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
group-onsemi	0:098463de4c5d	1853	#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
group-onsemi	0:098463de4c5d	1854	#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
group-onsemi	0:098463de4c5d	1855	#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
group-onsemi	0:098463de4c5d	1856	#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
group-onsemi	0:098463de4c5d	1857	#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
group-onsemi	0:098463de4c5d	1858	#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
group-onsemi	0:098463de4c5d	1859	#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
group-onsemi	0:098463de4c5d	1860	#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	1861	#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	1862	#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
group-onsemi	0:098463de4c5d	1863	#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
group-onsemi	0:098463de4c5d	1864	#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
group-onsemi	0:098463de4c5d	1865	#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
group-onsemi	0:098463de4c5d	1866	#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	1867	#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	1868	#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
group-onsemi	0:098463de4c5d	1869	#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
group-onsemi	0:098463de4c5d	1870	#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
group-onsemi	0:098463de4c5d	1871	#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
group-onsemi	0:098463de4c5d	1872	#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
group-onsemi	0:098463de4c5d	1873	#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
group-onsemi	0:098463de4c5d	1874	#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
group-onsemi	0:098463de4c5d	1875	#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
group-onsemi	0:098463de4c5d	1876	#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	1877	#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	1878	#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
group-onsemi	0:098463de4c5d	1879	#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
group-onsemi	0:098463de4c5d	1880	#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
group-onsemi	0:098463de4c5d	1881	#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
group-onsemi	0:098463de4c5d	1882	#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
group-onsemi	0:098463de4c5d	1883	#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
group-onsemi	0:098463de4c5d	1884	#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
group-onsemi	0:098463de4c5d	1885	#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
group-onsemi	0:098463de4c5d	1886	#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	1887	#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	1888	#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
group-onsemi	0:098463de4c5d	1889	#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
group-onsemi	0:098463de4c5d	1890	#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
group-onsemi	0:098463de4c5d	1891	#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
group-onsemi	0:098463de4c5d	1892	#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	1893	#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	1894	#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
group-onsemi	0:098463de4c5d	1895	#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
group-onsemi	0:098463de4c5d	1896	#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
group-onsemi	0:098463de4c5d	1897	#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
group-onsemi	0:098463de4c5d	1898	#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	1899	#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	1900	#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
group-onsemi	0:098463de4c5d	1901	#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
group-onsemi	0:098463de4c5d	1902	#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
group-onsemi	0:098463de4c5d	1903	#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
group-onsemi	0:098463de4c5d	1904	#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
group-onsemi	0:098463de4c5d	1905	#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
group-onsemi	0:098463de4c5d	1906	#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
group-onsemi	0:098463de4c5d	1907	#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
group-onsemi	0:098463de4c5d	1908	#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
group-onsemi	0:098463de4c5d	1909	#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
group-onsemi	0:098463de4c5d	1910	#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
group-onsemi	0:098463de4c5d	1911	#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
group-onsemi	0:098463de4c5d	1912	#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
group-onsemi	0:098463de4c5d	1913	#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
group-onsemi	0:098463de4c5d	1914	#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	1915	#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	1916	#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
group-onsemi	0:098463de4c5d	1917	#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
group-onsemi	0:098463de4c5d	1918	#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
group-onsemi	0:098463de4c5d	1919	#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
group-onsemi	0:098463de4c5d	1920	#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
group-onsemi	0:098463de4c5d	1921	#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
group-onsemi	0:098463de4c5d	1922	#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	1923	#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	1924	#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
group-onsemi	0:098463de4c5d	1925	#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
group-onsemi	0:098463de4c5d	1926	#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	1927	#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	1928	#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
group-onsemi	0:098463de4c5d	1929	#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
group-onsemi	0:098463de4c5d	1930	#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
group-onsemi	0:098463de4c5d	1931	#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
group-onsemi	0:098463de4c5d	1932	#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
group-onsemi	0:098463de4c5d	1933	#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
group-onsemi	0:098463de4c5d	1934	#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	1935	#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	1936	#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
group-onsemi	0:098463de4c5d	1937	#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
group-onsemi	0:098463de4c5d	1938	#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
group-onsemi	0:098463de4c5d	1939	#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
group-onsemi	0:098463de4c5d	1940	#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	1941	#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	1942	#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
group-onsemi	0:098463de4c5d	1943	#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
group-onsemi	0:098463de4c5d	1944	#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
group-onsemi	0:098463de4c5d	1945	#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
group-onsemi	0:098463de4c5d	1946	#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	1947	#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	1948	#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
group-onsemi	0:098463de4c5d	1949	#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
group-onsemi	0:098463de4c5d	1950	#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
group-onsemi	0:098463de4c5d	1951	#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
group-onsemi	0:098463de4c5d	1952	#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	1953	#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	1954	#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
group-onsemi	0:098463de4c5d	1955	#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
group-onsemi	0:098463de4c5d	1956	#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
group-onsemi	0:098463de4c5d	1957	#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
group-onsemi	0:098463de4c5d	1958	#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	1959	#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	1960	#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
group-onsemi	0:098463de4c5d	1961	#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
group-onsemi	0:098463de4c5d	1962	#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
group-onsemi	0:098463de4c5d	1963	#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
group-onsemi	0:098463de4c5d	1964	#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	1965	#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	1966	#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
group-onsemi	0:098463de4c5d	1967	#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
group-onsemi	0:098463de4c5d	1968	#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
group-onsemi	0:098463de4c5d	1969	#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
group-onsemi	0:098463de4c5d	1970	#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	1971	#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	1972	#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
group-onsemi	0:098463de4c5d	1973	#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
group-onsemi	0:098463de4c5d	1974	#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
group-onsemi	0:098463de4c5d	1975	#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
group-onsemi	0:098463de4c5d	1976	#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	1977	#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	1978	#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
group-onsemi	0:098463de4c5d	1979	#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
group-onsemi	0:098463de4c5d	1980	#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
group-onsemi	0:098463de4c5d	1981	#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
group-onsemi	0:098463de4c5d	1982	#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	1983	#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	1984	#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
group-onsemi	0:098463de4c5d	1985	#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
group-onsemi	0:098463de4c5d	1986	#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
group-onsemi	0:098463de4c5d	1987	#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
group-onsemi	0:098463de4c5d	1988	#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	1989	#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	1990	#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
group-onsemi	0:098463de4c5d	1991	#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
group-onsemi	0:098463de4c5d	1992	#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
group-onsemi	0:098463de4c5d	1993	#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
group-onsemi	0:098463de4c5d	1994	#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	1995	#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	1996	#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
group-onsemi	0:098463de4c5d	1997	#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
group-onsemi	0:098463de4c5d	1998	#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
group-onsemi	0:098463de4c5d	1999	#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
group-onsemi	0:098463de4c5d	2000	#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2001	#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2002	#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
group-onsemi	0:098463de4c5d	2003	#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
group-onsemi	0:098463de4c5d	2004	#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
group-onsemi	0:098463de4c5d	2005	#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
group-onsemi	0:098463de4c5d	2006	#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2007	#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2008	#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
group-onsemi	0:098463de4c5d	2009	#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
group-onsemi	0:098463de4c5d	2010	#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
group-onsemi	0:098463de4c5d	2011	#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
group-onsemi	0:098463de4c5d	2012	#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2013	#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2014	#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
group-onsemi	0:098463de4c5d	2015	#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
group-onsemi	0:098463de4c5d	2016	#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
group-onsemi	0:098463de4c5d	2017	#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
group-onsemi	0:098463de4c5d	2018	#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2019	#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2020	#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
group-onsemi	0:098463de4c5d	2021	#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
group-onsemi	0:098463de4c5d	2022	#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
group-onsemi	0:098463de4c5d	2023	#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
group-onsemi	0:098463de4c5d	2024	#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2025	#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2026	#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
group-onsemi	0:098463de4c5d	2027	#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
group-onsemi	0:098463de4c5d	2028	#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
group-onsemi	0:098463de4c5d	2029	#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
group-onsemi	0:098463de4c5d	2030	#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2031	#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2032	#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
group-onsemi	0:098463de4c5d	2033	#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
group-onsemi	0:098463de4c5d	2034	#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
group-onsemi	0:098463de4c5d	2035	#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
group-onsemi	0:098463de4c5d	2036	#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2037	#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2038	#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
group-onsemi	0:098463de4c5d	2039	#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
group-onsemi	0:098463de4c5d	2040	#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
group-onsemi	0:098463de4c5d	2041	#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
group-onsemi	0:098463de4c5d	2042	#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2043	#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2044	#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
group-onsemi	0:098463de4c5d	2045	#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
group-onsemi	0:098463de4c5d	2046	#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
group-onsemi	0:098463de4c5d	2047	#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
group-onsemi	0:098463de4c5d	2048	#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2049	#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2050	#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
group-onsemi	0:098463de4c5d	2051	#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
group-onsemi	0:098463de4c5d	2052	#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
group-onsemi	0:098463de4c5d	2053	#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
group-onsemi	0:098463de4c5d	2054	#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2055	#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2056	#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
group-onsemi	0:098463de4c5d	2057	#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
group-onsemi	0:098463de4c5d	2058	#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
group-onsemi	0:098463de4c5d	2059	#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
group-onsemi	0:098463de4c5d	2060	#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2061	#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2062	#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
group-onsemi	0:098463de4c5d	2063	#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
group-onsemi	0:098463de4c5d	2064	#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
group-onsemi	0:098463de4c5d	2065	#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
group-onsemi	0:098463de4c5d	2066	#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
group-onsemi	0:098463de4c5d	2067	#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
group-onsemi	0:098463de4c5d	2068	#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2069	#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2070	#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
group-onsemi	0:098463de4c5d	2071	#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
group-onsemi	0:098463de4c5d	2072	#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
group-onsemi	0:098463de4c5d	2073	#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
group-onsemi	0:098463de4c5d	2074	#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2075	#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2076	#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
group-onsemi	0:098463de4c5d	2077	#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
group-onsemi	0:098463de4c5d	2078	#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
group-onsemi	0:098463de4c5d	2079	#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
group-onsemi	0:098463de4c5d	2080	#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2081	#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2082	#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
group-onsemi	0:098463de4c5d	2083	#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
group-onsemi	0:098463de4c5d	2084	#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
group-onsemi	0:098463de4c5d	2085	#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
group-onsemi	0:098463de4c5d	2086	#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2087	#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2088	#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
group-onsemi	0:098463de4c5d	2089	#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
group-onsemi	0:098463de4c5d	2090	#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
group-onsemi	0:098463de4c5d	2091	#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
group-onsemi	0:098463de4c5d	2092	#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2093	#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2094	#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2095	#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2096	#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
group-onsemi	0:098463de4c5d	2097	#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
group-onsemi	0:098463de4c5d	2098	#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2099	#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2100	#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
group-onsemi	0:098463de4c5d	2101	#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
group-onsemi	0:098463de4c5d	2102	#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
group-onsemi	0:098463de4c5d	2103	#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
group-onsemi	0:098463de4c5d	2104	#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2105	#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2106	#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
group-onsemi	0:098463de4c5d	2107	#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
group-onsemi	0:098463de4c5d	2108	#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
group-onsemi	0:098463de4c5d	2109	#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
group-onsemi	0:098463de4c5d	2110	#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2111	#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2112	#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
group-onsemi	0:098463de4c5d	2113	#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
group-onsemi	0:098463de4c5d	2114	#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
group-onsemi	0:098463de4c5d	2115	#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
group-onsemi	0:098463de4c5d	2116	#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
group-onsemi	0:098463de4c5d	2117	#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
group-onsemi	0:098463de4c5d	2118	#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
group-onsemi	0:098463de4c5d	2119	#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
group-onsemi	0:098463de4c5d	2120	#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
group-onsemi	0:098463de4c5d	2121	#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
group-onsemi	0:098463de4c5d	2122	#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
group-onsemi	0:098463de4c5d	2123	#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
group-onsemi	0:098463de4c5d	2124	#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
group-onsemi	0:098463de4c5d	2125	#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
group-onsemi	0:098463de4c5d	2126	#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
group-onsemi	0:098463de4c5d	2127	#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
group-onsemi	0:098463de4c5d	2128	#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
group-onsemi	0:098463de4c5d	2129	#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
group-onsemi	0:098463de4c5d	2130	#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
group-onsemi	0:098463de4c5d	2131	#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
group-onsemi	0:098463de4c5d	2132	#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
group-onsemi	0:098463de4c5d	2133	#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
group-onsemi	0:098463de4c5d	2134	#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
group-onsemi	0:098463de4c5d	2135	#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
group-onsemi	0:098463de4c5d	2136	#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2137	#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2138	#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
group-onsemi	0:098463de4c5d	2139	#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
group-onsemi	0:098463de4c5d	2140	#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
group-onsemi	0:098463de4c5d	2141	#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
group-onsemi	0:098463de4c5d	2142	#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2143	#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2144	#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
group-onsemi	0:098463de4c5d	2145	#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
group-onsemi	0:098463de4c5d	2146	#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
group-onsemi	0:098463de4c5d	2147	#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
group-onsemi	0:098463de4c5d	2148	#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2149	#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2150	#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
group-onsemi	0:098463de4c5d	2151	#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
group-onsemi	0:098463de4c5d	2152	#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
group-onsemi	0:098463de4c5d	2153	#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
group-onsemi	0:098463de4c5d	2154	#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2155	#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2156	#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
group-onsemi	0:098463de4c5d	2157	#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
group-onsemi	0:098463de4c5d	2158	#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
group-onsemi	0:098463de4c5d	2159	#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
group-onsemi	0:098463de4c5d	2160	#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2161	#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2162	#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
group-onsemi	0:098463de4c5d	2163	#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
group-onsemi	0:098463de4c5d	2164	#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
group-onsemi	0:098463de4c5d	2165	#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
group-onsemi	0:098463de4c5d	2166	#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2167	#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2168	#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
group-onsemi	0:098463de4c5d	2169	#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
group-onsemi	0:098463de4c5d	2170	#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
group-onsemi	0:098463de4c5d	2171	#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
group-onsemi	0:098463de4c5d	2172	#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2173	#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2174	#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
group-onsemi	0:098463de4c5d	2175	#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
group-onsemi	0:098463de4c5d	2176	#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
group-onsemi	0:098463de4c5d	2177	#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
group-onsemi	0:098463de4c5d	2178	#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2179	#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2180	#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
group-onsemi	0:098463de4c5d	2181	#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
group-onsemi	0:098463de4c5d	2182	#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
group-onsemi	0:098463de4c5d	2183	#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
group-onsemi	0:098463de4c5d	2184	#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2185	#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2186	#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
group-onsemi	0:098463de4c5d	2187	#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
group-onsemi	0:098463de4c5d	2188	#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
group-onsemi	0:098463de4c5d	2189	#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
group-onsemi	0:098463de4c5d	2190	#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2191	#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2192	#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
group-onsemi	0:098463de4c5d	2193	#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
group-onsemi	0:098463de4c5d	2194	#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
group-onsemi	0:098463de4c5d	2195	#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
group-onsemi	0:098463de4c5d	2196	#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
group-onsemi	0:098463de4c5d	2197	#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
group-onsemi	0:098463de4c5d	2198	#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
group-onsemi	0:098463de4c5d	2199	#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
group-onsemi	0:098463de4c5d	2200	#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2201	#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2202	#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
group-onsemi	0:098463de4c5d	2203	#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
group-onsemi	0:098463de4c5d	2204	#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
group-onsemi	0:098463de4c5d	2205	#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
group-onsemi	0:098463de4c5d	2206	#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2207	#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2208	#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
group-onsemi	0:098463de4c5d	2209	#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
group-onsemi	0:098463de4c5d	2210	#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
group-onsemi	0:098463de4c5d	2211	#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
group-onsemi	0:098463de4c5d	2212	#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2213	#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2214	#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
group-onsemi	0:098463de4c5d	2215	#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
group-onsemi	0:098463de4c5d	2216	#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
group-onsemi	0:098463de4c5d	2217	#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
group-onsemi	0:098463de4c5d	2218	#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2219	#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2220	#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
group-onsemi	0:098463de4c5d	2221	#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
group-onsemi	0:098463de4c5d	2222	#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
group-onsemi	0:098463de4c5d	2223	#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
group-onsemi	0:098463de4c5d	2224	#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2225	#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2226	#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
group-onsemi	0:098463de4c5d	2227	#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
group-onsemi	0:098463de4c5d	2228	#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
group-onsemi	0:098463de4c5d	2229	#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
group-onsemi	0:098463de4c5d	2230	#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2231	#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2232	#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
group-onsemi	0:098463de4c5d	2233	#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
group-onsemi	0:098463de4c5d	2234	#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
group-onsemi	0:098463de4c5d	2235	#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
group-onsemi	0:098463de4c5d	2236	#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2237	#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2238	#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
group-onsemi	0:098463de4c5d	2239	#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
group-onsemi	0:098463de4c5d	2240	#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
group-onsemi	0:098463de4c5d	2241	#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
group-onsemi	0:098463de4c5d	2242	#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2243	#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2244	#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
group-onsemi	0:098463de4c5d	2245	#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
group-onsemi	0:098463de4c5d	2246	#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
group-onsemi	0:098463de4c5d	2247	#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
group-onsemi	0:098463de4c5d	2248	#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
group-onsemi	0:098463de4c5d	2249	#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
group-onsemi	0:098463de4c5d	2250	#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
group-onsemi	0:098463de4c5d	2251	#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
group-onsemi	0:098463de4c5d	2252	#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
group-onsemi	0:098463de4c5d	2253	#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
group-onsemi	0:098463de4c5d	2254	#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
group-onsemi	0:098463de4c5d	2255	#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
group-onsemi	0:098463de4c5d	2256	#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
group-onsemi	0:098463de4c5d	2257	#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2258	#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2259	#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
group-onsemi	0:098463de4c5d	2260	#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
group-onsemi	0:098463de4c5d	2261	#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
group-onsemi	0:098463de4c5d	2262	#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
group-onsemi	0:098463de4c5d	2263	#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
group-onsemi	0:098463de4c5d	2264	#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2265	#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2266	#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
group-onsemi	0:098463de4c5d	2267	#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
group-onsemi	0:098463de4c5d	2268	#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
group-onsemi	0:098463de4c5d	2269	#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
group-onsemi	0:098463de4c5d	2270	#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
group-onsemi	0:098463de4c5d	2271	#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
group-onsemi	0:098463de4c5d	2272	#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2273	#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2274	#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
group-onsemi	0:098463de4c5d	2275	#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
group-onsemi	0:098463de4c5d	2276	#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
group-onsemi	0:098463de4c5d	2277	#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
group-onsemi	0:098463de4c5d	2278	#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2279	#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2280	#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
group-onsemi	0:098463de4c5d	2281	#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
group-onsemi	0:098463de4c5d	2282	#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2283	#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2284	#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
group-onsemi	0:098463de4c5d	2285	#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
group-onsemi	0:098463de4c5d	2286	#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
group-onsemi	0:098463de4c5d	2287	#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
group-onsemi	0:098463de4c5d	2288
group-onsemi	0:098463de4c5d	2289	#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
group-onsemi	0:098463de4c5d	2290	#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
group-onsemi	0:098463de4c5d	2291	#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2292	#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2293	#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
group-onsemi	0:098463de4c5d	2294	#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
group-onsemi	0:098463de4c5d	2295	#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
group-onsemi	0:098463de4c5d	2296	#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
group-onsemi	0:098463de4c5d	2297	#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2298	#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2299	#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2300	#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2301	#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2302	#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2303	#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2304	#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2305	#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
group-onsemi	0:098463de4c5d	2306	#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
group-onsemi	0:098463de4c5d	2307	#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
group-onsemi	0:098463de4c5d	2308	#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
group-onsemi	0:098463de4c5d	2309	#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
group-onsemi	0:098463de4c5d	2310	#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2311	#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2312	#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
group-onsemi	0:098463de4c5d	2313	#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
group-onsemi	0:098463de4c5d	2314	#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
group-onsemi	0:098463de4c5d	2315	#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
group-onsemi	0:098463de4c5d	2316	#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
group-onsemi	0:098463de4c5d	2317	#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2318	#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2319	#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
group-onsemi	0:098463de4c5d	2320	#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
group-onsemi	0:098463de4c5d	2321	#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
group-onsemi	0:098463de4c5d	2322	#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
group-onsemi	0:098463de4c5d	2323	#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2324	#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2325	#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
group-onsemi	0:098463de4c5d	2326	#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
group-onsemi	0:098463de4c5d	2327	#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
group-onsemi	0:098463de4c5d	2328	#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
group-onsemi	0:098463de4c5d	2329	#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2330	#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2331	#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2332	#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2333	#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2334	#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2335	#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2336	#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2337	#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2338	#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2339	#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2340	#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2341	#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2342	#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
group-onsemi	0:098463de4c5d	2343	#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
group-onsemi	0:098463de4c5d	2344	#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2345	#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2346	#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
group-onsemi	0:098463de4c5d	2347	#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
group-onsemi	0:098463de4c5d	2348	#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
group-onsemi	0:098463de4c5d	2349	#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
group-onsemi	0:098463de4c5d	2350	#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
group-onsemi	0:098463de4c5d	2351	#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
group-onsemi	0:098463de4c5d	2352	#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2353	#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2354	#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
group-onsemi	0:098463de4c5d	2355	#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
group-onsemi	0:098463de4c5d	2356	#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
group-onsemi	0:098463de4c5d	2357	#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
group-onsemi	0:098463de4c5d	2358	#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2359	#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2360	#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
group-onsemi	0:098463de4c5d	2361	#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
group-onsemi	0:098463de4c5d	2362	#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
group-onsemi	0:098463de4c5d	2363	#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
group-onsemi	0:098463de4c5d	2364	#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2365	#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2366	#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
group-onsemi	0:098463de4c5d	2367	#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
group-onsemi	0:098463de4c5d	2368	#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
group-onsemi	0:098463de4c5d	2369	#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
group-onsemi	0:098463de4c5d	2370	#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2371	#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2372	#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
group-onsemi	0:098463de4c5d	2373	#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
group-onsemi	0:098463de4c5d	2374	#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
group-onsemi	0:098463de4c5d	2375	#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2376	#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2377	#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
group-onsemi	0:098463de4c5d	2378	#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
group-onsemi	0:098463de4c5d	2379	#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
group-onsemi	0:098463de4c5d	2380	#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
group-onsemi	0:098463de4c5d	2381	#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
group-onsemi	0:098463de4c5d	2382	#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
group-onsemi	0:098463de4c5d	2383	#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2384	#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2385	#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
group-onsemi	0:098463de4c5d	2386	#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
group-onsemi	0:098463de4c5d	2387	#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
group-onsemi	0:098463de4c5d	2388	#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
group-onsemi	0:098463de4c5d	2389	#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2390	#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2391	#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
group-onsemi	0:098463de4c5d	2392	#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
group-onsemi	0:098463de4c5d	2393	#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
group-onsemi	0:098463de4c5d	2394	#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
group-onsemi	0:098463de4c5d	2395	#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2396	#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2397	#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2398	#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2399	#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
group-onsemi	0:098463de4c5d	2400	#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
group-onsemi	0:098463de4c5d	2401	#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2402	#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2403	#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2404	#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2405	#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
group-onsemi	0:098463de4c5d	2406	#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
group-onsemi	0:098463de4c5d	2407	#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
group-onsemi	0:098463de4c5d	2408	#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
group-onsemi	0:098463de4c5d	2409	#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2410	#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2411	#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
group-onsemi	0:098463de4c5d	2412	#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
group-onsemi	0:098463de4c5d	2413	#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
group-onsemi	0:098463de4c5d	2414	#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2415	#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2416	#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2417	#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2418	#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2419	#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2420	#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2421	#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2422	#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2423	#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
group-onsemi	0:098463de4c5d	2424	#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
group-onsemi	0:098463de4c5d	2425	#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2426	#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2427	#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
group-onsemi	0:098463de4c5d	2428	#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
group-onsemi	0:098463de4c5d	2429	#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2430	#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2431	#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
group-onsemi	0:098463de4c5d	2432	#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
group-onsemi	0:098463de4c5d	2433	#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
group-onsemi	0:098463de4c5d	2434	#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
group-onsemi	0:098463de4c5d	2435	#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2436	#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2437
group-onsemi	0:098463de4c5d	2438	/* alias define maintained for legacy */
group-onsemi	0:098463de4c5d	2439	#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
group-onsemi	0:098463de4c5d	2440	#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
group-onsemi	0:098463de4c5d	2441
group-onsemi	0:098463de4c5d	2442	#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
group-onsemi	0:098463de4c5d	2443	#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
group-onsemi	0:098463de4c5d	2444	#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
group-onsemi	0:098463de4c5d	2445	#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
group-onsemi	0:098463de4c5d	2446	#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
group-onsemi	0:098463de4c5d	2447	#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
group-onsemi	0:098463de4c5d	2448	#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
group-onsemi	0:098463de4c5d	2449	#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
group-onsemi	0:098463de4c5d	2450	#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
group-onsemi	0:098463de4c5d	2451	#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
group-onsemi	0:098463de4c5d	2452	#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
group-onsemi	0:098463de4c5d	2453	#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
group-onsemi	0:098463de4c5d	2454	#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
group-onsemi	0:098463de4c5d	2455	#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
group-onsemi	0:098463de4c5d	2456	#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
group-onsemi	0:098463de4c5d	2457	#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
group-onsemi	0:098463de4c5d	2458	#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
group-onsemi	0:098463de4c5d	2459	#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
group-onsemi	0:098463de4c5d	2460	#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
group-onsemi	0:098463de4c5d	2461	#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
group-onsemi	0:098463de4c5d	2462	#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
group-onsemi	0:098463de4c5d	2463	#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
group-onsemi	0:098463de4c5d	2464
group-onsemi	0:098463de4c5d	2465	#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
group-onsemi	0:098463de4c5d	2466	#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
group-onsemi	0:098463de4c5d	2467	#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
group-onsemi	0:098463de4c5d	2468	#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
group-onsemi	0:098463de4c5d	2469	#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
group-onsemi	0:098463de4c5d	2470	#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
group-onsemi	0:098463de4c5d	2471	#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
group-onsemi	0:098463de4c5d	2472	#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
group-onsemi	0:098463de4c5d	2473	#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
group-onsemi	0:098463de4c5d	2474	#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
group-onsemi	0:098463de4c5d	2475	#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
group-onsemi	0:098463de4c5d	2476	#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
group-onsemi	0:098463de4c5d	2477	#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
group-onsemi	0:098463de4c5d	2478	#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
group-onsemi	0:098463de4c5d	2479	#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
group-onsemi	0:098463de4c5d	2480	#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
group-onsemi	0:098463de4c5d	2481	#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
group-onsemi	0:098463de4c5d	2482	#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
group-onsemi	0:098463de4c5d	2483	#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
group-onsemi	0:098463de4c5d	2484	#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
group-onsemi	0:098463de4c5d	2485	#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
group-onsemi	0:098463de4c5d	2486	#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
group-onsemi	0:098463de4c5d	2487
group-onsemi	0:098463de4c5d	2488	#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2489	#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2490	#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2491	#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2492	#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2493	#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2494	#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2495	#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2496	#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2497	#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2498	#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2499	#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2500	#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2501	#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2502	#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2503	#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2504	#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2505	#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2506	#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2507	#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2508	#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2509	#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2510	#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2511	#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2512	#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2513	#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2514	#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2515	#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2516	#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2517	#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2518	#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2519	#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2520	#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2521	#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2522	#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2523	#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2524	#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2525	#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2526	#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2527	#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2528	#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2529	#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2530	#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2531	#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2532	#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2533	#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2534	#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2535	#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2536	#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2537	#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2538	#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2539	#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2540	#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2541	#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2542	#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2543	#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2544	#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2545	#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2546	#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2547	#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2548	#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2549	#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2550	#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2551	#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2552	#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2553	#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2554	#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2555	#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2556	#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2557	#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2558	#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2559	#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2560	#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2561	#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2562	#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2563	#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2564	#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2565	#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2566	#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2567	#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2568	#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2569	#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2570	#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2571	#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2572	#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2573	#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2574	#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2575	#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2576	#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2577	#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2578	#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2579	#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2580	#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2581	#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2582	#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2583	#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2584	#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2585	#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2586	#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2587	#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2588	#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2589	#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2590	#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2591	#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2592	#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2593	#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2594	#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2595	#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2596	#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2597	#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2598	#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2599	#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2600	#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2601	#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2602	#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2603	#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2604
group-onsemi	0:098463de4c5d	2605	#if defined(STM32F4)
group-onsemi	0:098463de4c5d	2606	#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
group-onsemi	0:098463de4c5d	2607	#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
group-onsemi	0:098463de4c5d	2608	#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2609	#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2610	#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
group-onsemi	0:098463de4c5d	2611	#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
group-onsemi	0:098463de4c5d	2612	#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2613	#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2614	#define Sdmmc1ClockSelection SdioClockSelection
group-onsemi	0:098463de4c5d	2615	#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
group-onsemi	0:098463de4c5d	2616	#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
group-onsemi	0:098463de4c5d	2617	#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
group-onsemi	0:098463de4c5d	2618	#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
group-onsemi	0:098463de4c5d	2619	#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
group-onsemi	0:098463de4c5d	2620	#endif
group-onsemi	0:098463de4c5d	2621
group-onsemi	0:098463de4c5d	2622	#if defined(STM32F7) \|\| defined(STM32L4)
group-onsemi	0:098463de4c5d	2623	#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
group-onsemi	0:098463de4c5d	2624	#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
group-onsemi	0:098463de4c5d	2625	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2626	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2627	#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
group-onsemi	0:098463de4c5d	2628	#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
group-onsemi	0:098463de4c5d	2629	#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2630	#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2631	#define SdioClockSelection Sdmmc1ClockSelection
group-onsemi	0:098463de4c5d	2632	#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
group-onsemi	0:098463de4c5d	2633	#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
group-onsemi	0:098463de4c5d	2634	#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
group-onsemi	0:098463de4c5d	2635	#endif
group-onsemi	0:098463de4c5d	2636
group-onsemi	0:098463de4c5d	2637	#if defined(STM32F7)
group-onsemi	0:098463de4c5d	2638	#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
group-onsemi	0:098463de4c5d	2639	#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
group-onsemi	0:098463de4c5d	2640	#endif
group-onsemi	0:098463de4c5d	2641
group-onsemi	0:098463de4c5d	2642	#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
group-onsemi	0:098463de4c5d	2643	#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
group-onsemi	0:098463de4c5d	2644
group-onsemi	0:098463de4c5d	2645	#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
group-onsemi	0:098463de4c5d	2646
group-onsemi	0:098463de4c5d	2647	#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
group-onsemi	0:098463de4c5d	2648	#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
group-onsemi	0:098463de4c5d	2649	#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
group-onsemi	0:098463de4c5d	2650	#define IS_RCC_HCLK_DIV IS_RCC_PCLK
group-onsemi	0:098463de4c5d	2651	#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
group-onsemi	0:098463de4c5d	2652
group-onsemi	0:098463de4c5d	2653	#define RCC_IT_HSI14 RCC_IT_HSI14RDY
group-onsemi	0:098463de4c5d	2654
group-onsemi	0:098463de4c5d	2655	#define RCC_IT_CSSLSE RCC_IT_LSECSS
group-onsemi	0:098463de4c5d	2656	#define RCC_IT_CSSHSE RCC_IT_CSS
group-onsemi	0:098463de4c5d	2657
group-onsemi	0:098463de4c5d	2658	#define RCC_PLLMUL_3 RCC_PLL_MUL3
group-onsemi	0:098463de4c5d	2659	#define RCC_PLLMUL_4 RCC_PLL_MUL4
group-onsemi	0:098463de4c5d	2660	#define RCC_PLLMUL_6 RCC_PLL_MUL6
group-onsemi	0:098463de4c5d	2661	#define RCC_PLLMUL_8 RCC_PLL_MUL8
group-onsemi	0:098463de4c5d	2662	#define RCC_PLLMUL_12 RCC_PLL_MUL12
group-onsemi	0:098463de4c5d	2663	#define RCC_PLLMUL_16 RCC_PLL_MUL16
group-onsemi	0:098463de4c5d	2664	#define RCC_PLLMUL_24 RCC_PLL_MUL24
group-onsemi	0:098463de4c5d	2665	#define RCC_PLLMUL_32 RCC_PLL_MUL32
group-onsemi	0:098463de4c5d	2666	#define RCC_PLLMUL_48 RCC_PLL_MUL48
group-onsemi	0:098463de4c5d	2667
group-onsemi	0:098463de4c5d	2668	#define RCC_PLLDIV_2 RCC_PLL_DIV2
group-onsemi	0:098463de4c5d	2669	#define RCC_PLLDIV_3 RCC_PLL_DIV3
group-onsemi	0:098463de4c5d	2670	#define RCC_PLLDIV_4 RCC_PLL_DIV4
group-onsemi	0:098463de4c5d	2671
group-onsemi	0:098463de4c5d	2672	#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
group-onsemi	0:098463de4c5d	2673	#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
group-onsemi	0:098463de4c5d	2674	#define RCC_MCO_NODIV RCC_MCODIV_1
group-onsemi	0:098463de4c5d	2675	#define RCC_MCO_DIV1 RCC_MCODIV_1
group-onsemi	0:098463de4c5d	2676	#define RCC_MCO_DIV2 RCC_MCODIV_2
group-onsemi	0:098463de4c5d	2677	#define RCC_MCO_DIV4 RCC_MCODIV_4
group-onsemi	0:098463de4c5d	2678	#define RCC_MCO_DIV8 RCC_MCODIV_8
group-onsemi	0:098463de4c5d	2679	#define RCC_MCO_DIV16 RCC_MCODIV_16
group-onsemi	0:098463de4c5d	2680	#define RCC_MCO_DIV32 RCC_MCODIV_32
group-onsemi	0:098463de4c5d	2681	#define RCC_MCO_DIV64 RCC_MCODIV_64
group-onsemi	0:098463de4c5d	2682	#define RCC_MCO_DIV128 RCC_MCODIV_128
group-onsemi	0:098463de4c5d	2683	#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
group-onsemi	0:098463de4c5d	2684	#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
group-onsemi	0:098463de4c5d	2685	#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
group-onsemi	0:098463de4c5d	2686	#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
group-onsemi	0:098463de4c5d	2687	#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
group-onsemi	0:098463de4c5d	2688	#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
group-onsemi	0:098463de4c5d	2689	#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
group-onsemi	0:098463de4c5d	2690	#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
group-onsemi	0:098463de4c5d	2691	#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
group-onsemi	0:098463de4c5d	2692	#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
group-onsemi	0:098463de4c5d	2693	#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
group-onsemi	0:098463de4c5d	2694
group-onsemi	0:098463de4c5d	2695	#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
group-onsemi	0:098463de4c5d	2696
group-onsemi	0:098463de4c5d	2697	#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
group-onsemi	0:098463de4c5d	2698	#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
group-onsemi	0:098463de4c5d	2699	#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
group-onsemi	0:098463de4c5d	2700	#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
group-onsemi	0:098463de4c5d	2701	#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
group-onsemi	0:098463de4c5d	2702	#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
group-onsemi	0:098463de4c5d	2703	#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
group-onsemi	0:098463de4c5d	2704	#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
group-onsemi	0:098463de4c5d	2705
group-onsemi	0:098463de4c5d	2706	#define HSION_BitNumber RCC_HSION_BIT_NUMBER
group-onsemi	0:098463de4c5d	2707	#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
group-onsemi	0:098463de4c5d	2708	#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
group-onsemi	0:098463de4c5d	2709	#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
group-onsemi	0:098463de4c5d	2710	#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
group-onsemi	0:098463de4c5d	2711	#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
group-onsemi	0:098463de4c5d	2712	#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
group-onsemi	0:098463de4c5d	2713	#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
group-onsemi	0:098463de4c5d	2714	#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
group-onsemi	0:098463de4c5d	2715	#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
group-onsemi	0:098463de4c5d	2716	#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
group-onsemi	0:098463de4c5d	2717	#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
group-onsemi	0:098463de4c5d	2718	#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
group-onsemi	0:098463de4c5d	2719	#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
group-onsemi	0:098463de4c5d	2720	#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
group-onsemi	0:098463de4c5d	2721	#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
group-onsemi	0:098463de4c5d	2722	#define LSION_BitNumber RCC_LSION_BIT_NUMBER
group-onsemi	0:098463de4c5d	2723	#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
group-onsemi	0:098463de4c5d	2724	#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
group-onsemi	0:098463de4c5d	2725	#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
group-onsemi	0:098463de4c5d	2726	#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
group-onsemi	0:098463de4c5d	2727	#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
group-onsemi	0:098463de4c5d	2728	#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
group-onsemi	0:098463de4c5d	2729	#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
group-onsemi	0:098463de4c5d	2730	#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
group-onsemi	0:098463de4c5d	2731	#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
group-onsemi	0:098463de4c5d	2732	#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
group-onsemi	0:098463de4c5d	2733	#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
group-onsemi	0:098463de4c5d	2734	#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
group-onsemi	0:098463de4c5d	2735	#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
group-onsemi	0:098463de4c5d	2736	#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
group-onsemi	0:098463de4c5d	2737	#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
group-onsemi	0:098463de4c5d	2738
group-onsemi	0:098463de4c5d	2739	#define CR_HSION_BB RCC_CR_HSION_BB
group-onsemi	0:098463de4c5d	2740	#define CR_CSSON_BB RCC_CR_CSSON_BB
group-onsemi	0:098463de4c5d	2741	#define CR_PLLON_BB RCC_CR_PLLON_BB
group-onsemi	0:098463de4c5d	2742	#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
group-onsemi	0:098463de4c5d	2743	#define CR_MSION_BB RCC_CR_MSION_BB
group-onsemi	0:098463de4c5d	2744	#define CSR_LSION_BB RCC_CSR_LSION_BB
group-onsemi	0:098463de4c5d	2745	#define CSR_LSEON_BB RCC_CSR_LSEON_BB
group-onsemi	0:098463de4c5d	2746	#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
group-onsemi	0:098463de4c5d	2747	#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
group-onsemi	0:098463de4c5d	2748	#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
group-onsemi	0:098463de4c5d	2749	#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
group-onsemi	0:098463de4c5d	2750	#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
group-onsemi	0:098463de4c5d	2751	#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
group-onsemi	0:098463de4c5d	2752	#define CR_HSEON_BB RCC_CR_HSEON_BB
group-onsemi	0:098463de4c5d	2753	#define CSR_RMVF_BB RCC_CSR_RMVF_BB
group-onsemi	0:098463de4c5d	2754	#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
group-onsemi	0:098463de4c5d	2755	#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
group-onsemi	0:098463de4c5d	2756
group-onsemi	0:098463de4c5d	2757	#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
group-onsemi	0:098463de4c5d	2758	#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
group-onsemi	0:098463de4c5d	2759	#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
group-onsemi	0:098463de4c5d	2760	#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
group-onsemi	0:098463de4c5d	2761	#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
group-onsemi	0:098463de4c5d	2762
group-onsemi	0:098463de4c5d	2763	#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
group-onsemi	0:098463de4c5d	2764
group-onsemi	0:098463de4c5d	2765	#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
group-onsemi	0:098463de4c5d	2766	#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
group-onsemi	0:098463de4c5d	2767
group-onsemi	0:098463de4c5d	2768	#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
group-onsemi	0:098463de4c5d	2769	#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
group-onsemi	0:098463de4c5d	2770	#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
group-onsemi	0:098463de4c5d	2771	#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
group-onsemi	0:098463de4c5d	2772	#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
group-onsemi	0:098463de4c5d	2773	#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
group-onsemi	0:098463de4c5d	2774
group-onsemi	0:098463de4c5d	2775	#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
group-onsemi	0:098463de4c5d	2776	#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
group-onsemi	0:098463de4c5d	2777	#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
group-onsemi	0:098463de4c5d	2778	#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
group-onsemi	0:098463de4c5d	2779	#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
group-onsemi	0:098463de4c5d	2780	#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
group-onsemi	0:098463de4c5d	2781	#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
group-onsemi	0:098463de4c5d	2782	#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
group-onsemi	0:098463de4c5d	2783	#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
group-onsemi	0:098463de4c5d	2784	#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
group-onsemi	0:098463de4c5d	2785	#define DfsdmClockSelection Dfsdm1ClockSelection
group-onsemi	0:098463de4c5d	2786	#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
group-onsemi	0:098463de4c5d	2787	#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK
group-onsemi	0:098463de4c5d	2788	#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
group-onsemi	0:098463de4c5d	2789	#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
group-onsemi	0:098463de4c5d	2790	#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
group-onsemi	0:098463de4c5d	2791
group-onsemi	0:098463de4c5d	2792	/**
group-onsemi	0:098463de4c5d	2793	* @}
group-onsemi	0:098463de4c5d	2794	*/
group-onsemi	0:098463de4c5d	2795
group-onsemi	0:098463de4c5d	2796	/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	2797	* @{
group-onsemi	0:098463de4c5d	2798	*/
group-onsemi	0:098463de4c5d	2799	#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
group-onsemi	0:098463de4c5d	2800
group-onsemi	0:098463de4c5d	2801	/**
group-onsemi	0:098463de4c5d	2802	* @}
group-onsemi	0:098463de4c5d	2803	*/
group-onsemi	0:098463de4c5d	2804
group-onsemi	0:098463de4c5d	2805	/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	2806	* @{
group-onsemi	0:098463de4c5d	2807	*/
group-onsemi	0:098463de4c5d	2808
group-onsemi	0:098463de4c5d	2809	#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
group-onsemi	0:098463de4c5d	2810	#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
group-onsemi	0:098463de4c5d	2811	#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
group-onsemi	0:098463de4c5d	2812
group-onsemi	0:098463de4c5d	2813	#if defined (STM32F1)
group-onsemi	0:098463de4c5d	2814	#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
group-onsemi	0:098463de4c5d	2815
group-onsemi	0:098463de4c5d	2816	#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
group-onsemi	0:098463de4c5d	2817
group-onsemi	0:098463de4c5d	2818	#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
group-onsemi	0:098463de4c5d	2819
group-onsemi	0:098463de4c5d	2820	#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
group-onsemi	0:098463de4c5d	2821
group-onsemi	0:098463de4c5d	2822	#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
group-onsemi	0:098463de4c5d	2823	#else
group-onsemi	0:098463de4c5d	2824	#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
group-onsemi	0:098463de4c5d	2825	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
group-onsemi	0:098463de4c5d	2826	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
group-onsemi	0:098463de4c5d	2827	#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
group-onsemi	0:098463de4c5d	2828	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
group-onsemi	0:098463de4c5d	2829	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
group-onsemi	0:098463de4c5d	2830	#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
group-onsemi	0:098463de4c5d	2831	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
group-onsemi	0:098463de4c5d	2832	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
group-onsemi	0:098463de4c5d	2833	#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
group-onsemi	0:098463de4c5d	2834	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
group-onsemi	0:098463de4c5d	2835	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
group-onsemi	0:098463de4c5d	2836	#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
group-onsemi	0:098463de4c5d	2837	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
group-onsemi	0:098463de4c5d	2838	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
group-onsemi	0:098463de4c5d	2839	#endif /* STM32F1 */
group-onsemi	0:098463de4c5d	2840
group-onsemi	0:098463de4c5d	2841	#define IS_ALARM IS_RTC_ALARM
group-onsemi	0:098463de4c5d	2842	#define IS_ALARM_MASK IS_RTC_ALARM_MASK
group-onsemi	0:098463de4c5d	2843	#define IS_TAMPER IS_RTC_TAMPER
group-onsemi	0:098463de4c5d	2844	#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
group-onsemi	0:098463de4c5d	2845	#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
group-onsemi	0:098463de4c5d	2846	#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
group-onsemi	0:098463de4c5d	2847	#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
group-onsemi	0:098463de4c5d	2848	#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
group-onsemi	0:098463de4c5d	2849	#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
group-onsemi	0:098463de4c5d	2850	#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
group-onsemi	0:098463de4c5d	2851	#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
group-onsemi	0:098463de4c5d	2852	#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
group-onsemi	0:098463de4c5d	2853	#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
group-onsemi	0:098463de4c5d	2854	#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
group-onsemi	0:098463de4c5d	2855
group-onsemi	0:098463de4c5d	2856	#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
group-onsemi	0:098463de4c5d	2857	#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
group-onsemi	0:098463de4c5d	2858
group-onsemi	0:098463de4c5d	2859	/**
group-onsemi	0:098463de4c5d	2860	* @}
group-onsemi	0:098463de4c5d	2861	*/
group-onsemi	0:098463de4c5d	2862
group-onsemi	0:098463de4c5d	2863	/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	2864	* @{
group-onsemi	0:098463de4c5d	2865	*/
group-onsemi	0:098463de4c5d	2866
group-onsemi	0:098463de4c5d	2867	#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
group-onsemi	0:098463de4c5d	2868	#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
group-onsemi	0:098463de4c5d	2869
group-onsemi	0:098463de4c5d	2870	#if defined(STM32F4)
group-onsemi	0:098463de4c5d	2871	#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
group-onsemi	0:098463de4c5d	2872	#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
group-onsemi	0:098463de4c5d	2873	#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
group-onsemi	0:098463de4c5d	2874	#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
group-onsemi	0:098463de4c5d	2875	#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
group-onsemi	0:098463de4c5d	2876	#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
group-onsemi	0:098463de4c5d	2877	#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
group-onsemi	0:098463de4c5d	2878	#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
group-onsemi	0:098463de4c5d	2879	#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
group-onsemi	0:098463de4c5d	2880	#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
group-onsemi	0:098463de4c5d	2881	#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
group-onsemi	0:098463de4c5d	2882	#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
group-onsemi	0:098463de4c5d	2883	#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
group-onsemi	0:098463de4c5d	2884	#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
group-onsemi	0:098463de4c5d	2885	#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
group-onsemi	0:098463de4c5d	2886	#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
group-onsemi	0:098463de4c5d	2887	#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
group-onsemi	0:098463de4c5d	2888	#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
group-onsemi	0:098463de4c5d	2889	#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
group-onsemi	0:098463de4c5d	2890	#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
group-onsemi	0:098463de4c5d	2891	/* alias CMSIS */
group-onsemi	0:098463de4c5d	2892	#define SDMMC1_IRQn SDIO_IRQn
group-onsemi	0:098463de4c5d	2893	#define SDMMC1_IRQHandler SDIO_IRQHandler
group-onsemi	0:098463de4c5d	2894	#endif
group-onsemi	0:098463de4c5d	2895
group-onsemi	0:098463de4c5d	2896	#if defined(STM32F7) \|\| defined(STM32L4)
group-onsemi	0:098463de4c5d	2897	#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
group-onsemi	0:098463de4c5d	2898	#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
group-onsemi	0:098463de4c5d	2899	#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
group-onsemi	0:098463de4c5d	2900	#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
group-onsemi	0:098463de4c5d	2901	#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
group-onsemi	0:098463de4c5d	2902	#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
group-onsemi	0:098463de4c5d	2903	#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
group-onsemi	0:098463de4c5d	2904	#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
group-onsemi	0:098463de4c5d	2905	#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
group-onsemi	0:098463de4c5d	2906	#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
group-onsemi	0:098463de4c5d	2907	#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
group-onsemi	0:098463de4c5d	2908	#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
group-onsemi	0:098463de4c5d	2909	#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
group-onsemi	0:098463de4c5d	2910	#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
group-onsemi	0:098463de4c5d	2911	#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
group-onsemi	0:098463de4c5d	2912	#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
group-onsemi	0:098463de4c5d	2913	#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
group-onsemi	0:098463de4c5d	2914	#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
group-onsemi	0:098463de4c5d	2915	#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
group-onsemi	0:098463de4c5d	2916	#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
group-onsemi	0:098463de4c5d	2917	/* alias CMSIS for compatibilities */
group-onsemi	0:098463de4c5d	2918	#define SDIO_IRQn SDMMC1_IRQn
group-onsemi	0:098463de4c5d	2919	#define SDIO_IRQHandler SDMMC1_IRQHandler
group-onsemi	0:098463de4c5d	2920	#endif
group-onsemi	0:098463de4c5d	2921	/**
group-onsemi	0:098463de4c5d	2922	* @}
group-onsemi	0:098463de4c5d	2923	*/
group-onsemi	0:098463de4c5d	2924
group-onsemi	0:098463de4c5d	2925	/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	2926	* @{
group-onsemi	0:098463de4c5d	2927	*/
group-onsemi	0:098463de4c5d	2928
group-onsemi	0:098463de4c5d	2929	#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
group-onsemi	0:098463de4c5d	2930	#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
group-onsemi	0:098463de4c5d	2931	#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
group-onsemi	0:098463de4c5d	2932	#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
group-onsemi	0:098463de4c5d	2933	#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
group-onsemi	0:098463de4c5d	2934	#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
group-onsemi	0:098463de4c5d	2935
group-onsemi	0:098463de4c5d	2936	#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
group-onsemi	0:098463de4c5d	2937	#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
group-onsemi	0:098463de4c5d	2938
group-onsemi	0:098463de4c5d	2939	#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
group-onsemi	0:098463de4c5d	2940
group-onsemi	0:098463de4c5d	2941	/**
group-onsemi	0:098463de4c5d	2942	* @}
group-onsemi	0:098463de4c5d	2943	*/
group-onsemi	0:098463de4c5d	2944
group-onsemi	0:098463de4c5d	2945	/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	2946	* @{
group-onsemi	0:098463de4c5d	2947	*/
group-onsemi	0:098463de4c5d	2948	#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
group-onsemi	0:098463de4c5d	2949	#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
group-onsemi	0:098463de4c5d	2950	#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
group-onsemi	0:098463de4c5d	2951	#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
group-onsemi	0:098463de4c5d	2952	#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
group-onsemi	0:098463de4c5d	2953	#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
group-onsemi	0:098463de4c5d	2954	#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
group-onsemi	0:098463de4c5d	2955	#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
group-onsemi	0:098463de4c5d	2956	/**
group-onsemi	0:098463de4c5d	2957	* @}
group-onsemi	0:098463de4c5d	2958	*/
group-onsemi	0:098463de4c5d	2959
group-onsemi	0:098463de4c5d	2960	/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	2961	* @{
group-onsemi	0:098463de4c5d	2962	*/
group-onsemi	0:098463de4c5d	2963
group-onsemi	0:098463de4c5d	2964	#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
group-onsemi	0:098463de4c5d	2965	#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
group-onsemi	0:098463de4c5d	2966	#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
group-onsemi	0:098463de4c5d	2967
group-onsemi	0:098463de4c5d	2968	/**
group-onsemi	0:098463de4c5d	2969	* @}
group-onsemi	0:098463de4c5d	2970	*/
group-onsemi	0:098463de4c5d	2971
group-onsemi	0:098463de4c5d	2972	/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	2973	* @{
group-onsemi	0:098463de4c5d	2974	*/
group-onsemi	0:098463de4c5d	2975
group-onsemi	0:098463de4c5d	2976	#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
group-onsemi	0:098463de4c5d	2977	#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
group-onsemi	0:098463de4c5d	2978	#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
group-onsemi	0:098463de4c5d	2979	#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
group-onsemi	0:098463de4c5d	2980
group-onsemi	0:098463de4c5d	2981	#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
group-onsemi	0:098463de4c5d	2982
group-onsemi	0:098463de4c5d	2983	#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
group-onsemi	0:098463de4c5d	2984	#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
group-onsemi	0:098463de4c5d	2985
group-onsemi	0:098463de4c5d	2986	/**
group-onsemi	0:098463de4c5d	2987	* @}
group-onsemi	0:098463de4c5d	2988	*/
group-onsemi	0:098463de4c5d	2989
group-onsemi	0:098463de4c5d	2990
group-onsemi	0:098463de4c5d	2991	/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	2992	* @{
group-onsemi	0:098463de4c5d	2993	*/
group-onsemi	0:098463de4c5d	2994
group-onsemi	0:098463de4c5d	2995	#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
group-onsemi	0:098463de4c5d	2996	#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
group-onsemi	0:098463de4c5d	2997	#define __USART_ENABLE __HAL_USART_ENABLE
group-onsemi	0:098463de4c5d	2998	#define __USART_DISABLE __HAL_USART_DISABLE
group-onsemi	0:098463de4c5d	2999
group-onsemi	0:098463de4c5d	3000	#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
group-onsemi	0:098463de4c5d	3001	#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
group-onsemi	0:098463de4c5d	3002
group-onsemi	0:098463de4c5d	3003	/**
group-onsemi	0:098463de4c5d	3004	* @}
group-onsemi	0:098463de4c5d	3005	*/
group-onsemi	0:098463de4c5d	3006
group-onsemi	0:098463de4c5d	3007	/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	3008	* @{
group-onsemi	0:098463de4c5d	3009	*/
group-onsemi	0:098463de4c5d	3010	#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
group-onsemi	0:098463de4c5d	3011
group-onsemi	0:098463de4c5d	3012	#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
group-onsemi	0:098463de4c5d	3013	#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
group-onsemi	0:098463de4c5d	3014	#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
group-onsemi	0:098463de4c5d	3015	#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
group-onsemi	0:098463de4c5d	3016
group-onsemi	0:098463de4c5d	3017	#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
group-onsemi	0:098463de4c5d	3018	#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
group-onsemi	0:098463de4c5d	3019	#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
group-onsemi	0:098463de4c5d	3020	#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
group-onsemi	0:098463de4c5d	3021
group-onsemi	0:098463de4c5d	3022	#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
group-onsemi	0:098463de4c5d	3023	#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
group-onsemi	0:098463de4c5d	3024	#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
group-onsemi	0:098463de4c5d	3025	#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
group-onsemi	0:098463de4c5d	3026	#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
group-onsemi	0:098463de4c5d	3027	#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
group-onsemi	0:098463de4c5d	3028	#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
group-onsemi	0:098463de4c5d	3029
group-onsemi	0:098463de4c5d	3030	#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
group-onsemi	0:098463de4c5d	3031	#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
group-onsemi	0:098463de4c5d	3032	#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
group-onsemi	0:098463de4c5d	3033	#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
group-onsemi	0:098463de4c5d	3034	#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
group-onsemi	0:098463de4c5d	3035	#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
group-onsemi	0:098463de4c5d	3036	#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
group-onsemi	0:098463de4c5d	3037	#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
group-onsemi	0:098463de4c5d	3038
group-onsemi	0:098463de4c5d	3039	#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
group-onsemi	0:098463de4c5d	3040	#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
group-onsemi	0:098463de4c5d	3041	#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
group-onsemi	0:098463de4c5d	3042	#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
group-onsemi	0:098463de4c5d	3043	#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
group-onsemi	0:098463de4c5d	3044	#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
group-onsemi	0:098463de4c5d	3045	#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
group-onsemi	0:098463de4c5d	3046	#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
group-onsemi	0:098463de4c5d	3047
group-onsemi	0:098463de4c5d	3048	#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
group-onsemi	0:098463de4c5d	3049	#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
group-onsemi	0:098463de4c5d	3050
group-onsemi	0:098463de4c5d	3051	#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
group-onsemi	0:098463de4c5d	3052	#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
group-onsemi	0:098463de4c5d	3053	/**
group-onsemi	0:098463de4c5d	3054	* @}
group-onsemi	0:098463de4c5d	3055	*/
group-onsemi	0:098463de4c5d	3056
group-onsemi	0:098463de4c5d	3057	/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	3058	* @{
group-onsemi	0:098463de4c5d	3059	*/
group-onsemi	0:098463de4c5d	3060	#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
group-onsemi	0:098463de4c5d	3061	#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
group-onsemi	0:098463de4c5d	3062
group-onsemi	0:098463de4c5d	3063	#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
group-onsemi	0:098463de4c5d	3064	#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
group-onsemi	0:098463de4c5d	3065
group-onsemi	0:098463de4c5d	3066	#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
group-onsemi	0:098463de4c5d	3067
group-onsemi	0:098463de4c5d	3068	#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
group-onsemi	0:098463de4c5d	3069	#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
group-onsemi	0:098463de4c5d	3070	#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
group-onsemi	0:098463de4c5d	3071	#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
group-onsemi	0:098463de4c5d	3072	#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
group-onsemi	0:098463de4c5d	3073	#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
group-onsemi	0:098463de4c5d	3074	#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
group-onsemi	0:098463de4c5d	3075	#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
group-onsemi	0:098463de4c5d	3076	#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
group-onsemi	0:098463de4c5d	3077	#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
group-onsemi	0:098463de4c5d	3078	#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
group-onsemi	0:098463de4c5d	3079	#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
group-onsemi	0:098463de4c5d	3080
group-onsemi	0:098463de4c5d	3081	#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
group-onsemi	0:098463de4c5d	3082	/**
group-onsemi	0:098463de4c5d	3083	* @}
group-onsemi	0:098463de4c5d	3084	*/
group-onsemi	0:098463de4c5d	3085
group-onsemi	0:098463de4c5d	3086	/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	3087	* @{
group-onsemi	0:098463de4c5d	3088	*/
group-onsemi	0:098463de4c5d	3089
group-onsemi	0:098463de4c5d	3090	#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
group-onsemi	0:098463de4c5d	3091	#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
group-onsemi	0:098463de4c5d	3092	#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
group-onsemi	0:098463de4c5d	3093	#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
group-onsemi	0:098463de4c5d	3094	#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
group-onsemi	0:098463de4c5d	3095	#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
group-onsemi	0:098463de4c5d	3096	#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
group-onsemi	0:098463de4c5d	3097
group-onsemi	0:098463de4c5d	3098	#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
group-onsemi	0:098463de4c5d	3099	#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
group-onsemi	0:098463de4c5d	3100	#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
group-onsemi	0:098463de4c5d	3101	/**
group-onsemi	0:098463de4c5d	3102	* @}
group-onsemi	0:098463de4c5d	3103	*/
group-onsemi	0:098463de4c5d	3104
group-onsemi	0:098463de4c5d	3105	/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	3106	* @{
group-onsemi	0:098463de4c5d	3107	*/
group-onsemi	0:098463de4c5d	3108	#define __HAL_LTDC_LAYER LTDC_LAYER
group-onsemi	0:098463de4c5d	3109	/**
group-onsemi	0:098463de4c5d	3110	* @}
group-onsemi	0:098463de4c5d	3111	*/
group-onsemi	0:098463de4c5d	3112
group-onsemi	0:098463de4c5d	3113	/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	3114	* @{
group-onsemi	0:098463de4c5d	3115	*/
group-onsemi	0:098463de4c5d	3116	#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
group-onsemi	0:098463de4c5d	3117	#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
group-onsemi	0:098463de4c5d	3118	#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
group-onsemi	0:098463de4c5d	3119	#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
group-onsemi	0:098463de4c5d	3120	#define SAI_STREOMODE SAI_STEREOMODE
group-onsemi	0:098463de4c5d	3121	#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
group-onsemi	0:098463de4c5d	3122	#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
group-onsemi	0:098463de4c5d	3123	#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
group-onsemi	0:098463de4c5d	3124	#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
group-onsemi	0:098463de4c5d	3125	#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
group-onsemi	0:098463de4c5d	3126	#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
group-onsemi	0:098463de4c5d	3127	#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
group-onsemi	0:098463de4c5d	3128	#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
group-onsemi	0:098463de4c5d	3129	#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
group-onsemi	0:098463de4c5d	3130	/**
group-onsemi	0:098463de4c5d	3131	* @}
group-onsemi	0:098463de4c5d	3132	*/
group-onsemi	0:098463de4c5d	3133
group-onsemi	0:098463de4c5d	3134
group-onsemi	0:098463de4c5d	3135	/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
group-onsemi	0:098463de4c5d	3136	* @{
group-onsemi	0:098463de4c5d	3137	*/
group-onsemi	0:098463de4c5d	3138
group-onsemi	0:098463de4c5d	3139	/**
group-onsemi	0:098463de4c5d	3140	* @}
group-onsemi	0:098463de4c5d	3141	*/
group-onsemi	0:098463de4c5d	3142
group-onsemi	0:098463de4c5d	3143	#ifdef __cplusplus
group-onsemi	0:098463de4c5d	3144	}
group-onsemi	0:098463de4c5d	3145	#endif
group-onsemi	0:098463de4c5d	3146
group-onsemi	0:098463de4c5d	3147	#endif /* ___STM32_HAL_LEGACY */
group-onsemi	0:098463de4c5d	3148
group-onsemi	0:098463de4c5d	3149	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
group-onsemi	0:098463de4c5d	3150

Repository toolbox

Repository details

Type:	Library
Created:	25 Jan 2017
Imports:	32
Forks:	0
Commits:	2
Dependents:	3
Dependencies:	0
Followers:	15

This repository is Public (Unlisted).

Important changes to repositories hosted on mbed.com

targets/TARGET_STM/TARGET_STM32F7/device/stm32_hal_legacy.h@1:f30bdcd2b33b, 2017-02-27 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Important changes to repositories hosted on mbed.com

targets/TARGET_STM/TARGET_STM32F7/device/stm32_hal_legacy.h@1:f30bdcd2b33b, 2017-02-27 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning